1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
29 /* External variables defined in xtensa.c. */
33 CMP_SI, /* four byte integers */
34 CMP_DI, /* eight byte integers */
35 CMP_SF, /* single precision floats */
36 CMP_DF, /* double precision floats */
37 CMP_MAX /* max comparison type */
40 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
41 extern enum cmp_type branch_type; /* what type of branch to use */
42 extern unsigned xtensa_current_frame_size;
44 /* Macros used in the machine description to select various Xtensa
45 configuration options. */
46 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
47 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
48 #define TARGET_MAC16 XCHAL_HAVE_MAC16
49 #define TARGET_MUL16 XCHAL_HAVE_MUL16
50 #define TARGET_MUL32 XCHAL_HAVE_MUL32
51 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
52 #define TARGET_DIV32 XCHAL_HAVE_DIV32
53 #define TARGET_NSA XCHAL_HAVE_NSA
54 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
55 #define TARGET_SEXT XCHAL_HAVE_SEXT
56 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
57 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
58 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
59 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
60 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
61 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
62 #define TARGET_ABS XCHAL_HAVE_ABS
63 #define TARGET_ADDX XCHAL_HAVE_ADDX
65 #define TARGET_DEFAULT ( \
66 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
68 #define OVERRIDE_OPTIONS override_options ()
70 /* Reordering blocks for Xtensa is not a good idea unless the compiler
71 understands the range of conditional branches. Currently all branch
72 relaxation for Xtensa is handled in the assembler, so GCC cannot do a
73 good job of reordering blocks. Do not enable reordering unless it is
74 explicitly requested. */
75 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
78 flag_reorder_blocks = 0; \
83 /* Target CPU builtins. */
84 #define TARGET_CPU_CPP_BUILTINS() \
86 builtin_assert ("cpu=xtensa"); \
87 builtin_assert ("machine=xtensa"); \
88 builtin_define ("__xtensa__"); \
89 builtin_define ("__XTENSA__"); \
90 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
91 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
92 if (!TARGET_HARD_FLOAT) \
93 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
96 #define CPP_SPEC " %(subtarget_cpp_spec) "
98 #ifndef SUBTARGET_CPP_SPEC
99 #define SUBTARGET_CPP_SPEC ""
102 #define EXTRA_SPECS \
103 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
106 #define LIBGCC2_WORDS_BIG_ENDIAN 1
108 #define LIBGCC2_WORDS_BIG_ENDIAN 0
111 /* Show we can debug even without a frame pointer. */
112 #define CAN_DEBUG_WITHOUT_FP
115 /* Target machine storage layout */
117 /* Define this if most significant bit is lowest numbered
118 in instructions that operate on numbered bit-fields. */
119 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
121 /* Define this if most significant byte of a word is the lowest numbered. */
122 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
124 /* Define this if most significant word of a multiword number is the lowest. */
125 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
127 #define MAX_BITS_PER_WORD 32
129 /* Width of a word, in units (bytes). */
130 #define UNITS_PER_WORD 4
131 #define MIN_UNITS_PER_WORD 4
133 /* Width of a floating point register. */
134 #define UNITS_PER_FPREG 4
136 /* Size in bits of various types on the target machine. */
137 #define INT_TYPE_SIZE 32
138 #define SHORT_TYPE_SIZE 16
139 #define LONG_TYPE_SIZE 32
140 #define LONG_LONG_TYPE_SIZE 64
141 #define FLOAT_TYPE_SIZE 32
142 #define DOUBLE_TYPE_SIZE 64
143 #define LONG_DOUBLE_TYPE_SIZE 64
145 /* Allocation boundary (in *bits*) for storing pointers in memory. */
146 #define POINTER_BOUNDARY 32
148 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
149 #define PARM_BOUNDARY 32
151 /* Allocation boundary (in *bits*) for the code of a function. */
152 #define FUNCTION_BOUNDARY 32
154 /* Alignment of field after 'int : 0' in a structure. */
155 #define EMPTY_FIELD_BOUNDARY 32
157 /* Every structure's size must be a multiple of this. */
158 #define STRUCTURE_SIZE_BOUNDARY 8
160 /* There is no point aligning anything to a rounder boundary than this. */
161 #define BIGGEST_ALIGNMENT 128
163 /* Set this nonzero if move instructions will actually fail to work
164 when given unaligned data. */
165 #define STRICT_ALIGNMENT 1
167 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
168 for QImode, because there is no 8-bit load from memory with sign
169 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
170 loads both with and without sign extension. */
171 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
173 if (GET_MODE_CLASS (MODE) == MODE_INT \
174 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
176 if ((MODE) == QImode) \
182 /* Imitate the way many other C compilers handle alignment of
183 bitfields and the structures that contain them. */
184 #define PCC_BITFIELD_TYPE_MATTERS 1
186 /* Disable the use of word-sized or smaller complex modes for structures,
187 and for function arguments in particular, where they cause problems with
188 register a7. The xtensa_copy_incoming_a7 function assumes that there is
189 a single reference to an argument in a7, but with small complex modes the
190 real and imaginary components may be extracted separately, leading to two
191 uses of the register, only one of which would be replaced. */
192 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
193 ((MODE) == CQImode || (MODE) == CHImode)
195 /* Align string constants and constructors to at least a word boundary.
196 The typical use of this macro is to increase alignment for string
197 constants to be word aligned so that 'strcpy' calls that copy
198 constants can be done inline. */
199 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
200 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
201 && (ALIGN) < BITS_PER_WORD \
205 /* Align arrays, unions and records to at least a word boundary.
206 One use of this macro is to increase alignment of medium-size
207 data to make it all fit in fewer cache lines. Another is to
208 cause character arrays to be word-aligned so that 'strcpy' calls
209 that copy constants to character arrays can be done inline. */
210 #undef DATA_ALIGNMENT
211 #define DATA_ALIGNMENT(TYPE, ALIGN) \
212 ((((ALIGN) < BITS_PER_WORD) \
213 && (TREE_CODE (TYPE) == ARRAY_TYPE \
214 || TREE_CODE (TYPE) == UNION_TYPE \
215 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
217 /* Operations between registers always perform the operation
218 on the full register even if a narrower mode is specified. */
219 #define WORD_REGISTER_OPERATIONS
221 /* Xtensa loads are zero-extended by default. */
222 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
224 /* Standard register usage. */
226 /* Number of actual hardware registers.
227 The hardware registers are assigned numbers for the compiler
228 from 0 to just below FIRST_PSEUDO_REGISTER.
229 All registers that the compiler knows about must be given numbers,
230 even those that are not normally considered general registers.
232 The fake frame pointer and argument pointer will never appear in
233 the generated code, since they will always be eliminated and replaced
234 by either the stack pointer or the hard frame pointer.
236 0 - 15 AR[0] - AR[15]
237 16 FRAME_POINTER (fake = initial sp)
238 17 ARG_POINTER (fake = initial sp + framesize)
239 18 BR[0] for floating-point CC
240 19 - 34 FR[0] - FR[15]
241 35 MAC16 accumulator */
243 #define FIRST_PSEUDO_REGISTER 36
245 /* Return the stabs register number to use for REGNO. */
246 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
248 /* 1 for registers that have pervasive standard uses
249 and are not available for the register allocator. */
250 #define FIXED_REGISTERS \
252 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
258 /* 1 for registers not available across function calls.
259 These must include the FIXED_REGISTERS and also any
260 registers that can be used without being saved.
261 The latter must include the registers where values are returned
262 and the register where structure-value addresses are passed.
263 Aside from that, you can include as many other registers as you like. */
264 #define CALL_USED_REGISTERS \
266 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
272 /* For non-leaf procedures on Xtensa processors, the allocation order
273 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
274 want to use the lowest numbered registers first to minimize
275 register window overflows. However, local-alloc is not smart
276 enough to consider conflicts with incoming arguments. If an
277 incoming argument in a2 is live throughout the function and
278 local-alloc decides to use a2, then the incoming argument must
279 either be spilled or copied to another register. To get around
280 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
281 reg_alloc_order for leaf functions such that lowest numbered
282 registers are used first with the exception that the incoming
283 argument registers are not used until after other register choices
284 have been exhausted. */
286 #define REG_ALLOC_ORDER \
287 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
289 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
294 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
296 /* For Xtensa, the only point of this is to prevent GCC from otherwise
297 giving preference to call-used registers. To minimize window
298 overflows for the AR registers, we want to give preference to the
299 lower-numbered AR registers. For other register files, which are
300 not windowed, we still prefer call-used registers, if there are any. */
301 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
302 #define LEAF_REGISTERS xtensa_leaf_regs
304 /* For Xtensa, no remapping is necessary, but this macro must be
305 defined if LEAF_REGISTERS is defined. */
306 #define LEAF_REG_REMAP(REGNO) (REGNO)
308 /* This must be declared if LEAF_REGISTERS is set. */
309 extern int leaf_function;
311 /* Internal macros to classify a register number. */
313 /* 16 address registers + fake registers */
314 #define GP_REG_FIRST 0
315 #define GP_REG_LAST 17
316 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
318 /* Coprocessor registers */
319 #define BR_REG_FIRST 18
320 #define BR_REG_LAST 18
321 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
323 /* 16 floating-point registers */
324 #define FP_REG_FIRST 19
325 #define FP_REG_LAST 34
326 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
328 /* MAC16 accumulator */
329 #define ACC_REG_FIRST 35
330 #define ACC_REG_LAST 35
331 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
333 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
334 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
335 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
336 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
338 /* Return number of consecutive hard regs needed starting at reg REGNO
339 to hold something of mode MODE. */
340 #define HARD_REGNO_NREGS(REGNO, MODE) \
341 (FP_REG_P (REGNO) ? \
342 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
343 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
345 /* Value is 1 if hard register REGNO can hold a value of machine-mode
347 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
349 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
350 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
352 /* Value is 1 if it is a good idea to tie two pseudo registers
353 when one has mode MODE1 and one has mode MODE2.
354 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
355 for any hard reg, then this must be 0 for correct output. */
356 #define MODES_TIEABLE_P(MODE1, MODE2) \
357 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
358 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
359 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
360 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
362 /* Register to use for pushing function arguments. */
363 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
365 /* Base register for access to local variables of the function. */
366 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
368 /* The register number of the frame pointer register, which is used to
369 access automatic variables in the stack frame. For Xtensa, this
370 register never appears in the output. It is always eliminated to
371 either the stack pointer or the hard frame pointer. */
372 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
374 /* Value should be nonzero if functions must have frame pointers.
375 Zero means the frame pointer need not be set up (and parms
376 may be accessed via the stack pointer) in functions that seem suitable.
377 This is computed in 'reload', in reload1.c. */
378 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
380 /* Base register for access to arguments of the function. */
381 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
383 /* If the static chain is passed in memory, these macros provide rtx
384 giving 'mem' expressions that denote where they are stored.
385 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
386 seen by the calling and called functions, respectively. */
388 #define STATIC_CHAIN \
389 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
391 #define STATIC_CHAIN_INCOMING \
392 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
394 /* For now we don't try to use the full set of boolean registers. Without
395 software pipelining of FP operations, there's not much to gain and it's
396 a real pain to get them reloaded. */
397 #define FPCC_REGNUM (BR_REG_FIRST + 0)
399 /* It is as good or better to call a constant function address than to
400 call an address kept in a register. */
401 #define NO_FUNCTION_CSE 1
403 /* Xtensa processors have "register windows". GCC does not currently
404 take advantage of the possibility for variable-sized windows; instead,
405 we use a fixed window size of 8. */
407 #define INCOMING_REGNO(OUT) \
408 ((GP_REG_P (OUT) && \
409 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
410 (OUT) - WINDOW_SIZE : (OUT))
412 #define OUTGOING_REGNO(IN) \
414 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
415 (IN) + WINDOW_SIZE : (IN))
418 /* Define the classes of registers for register constraints in the
419 machine description. */
422 NO_REGS, /* no registers in set */
423 BR_REGS, /* coprocessor boolean registers */
424 FP_REGS, /* floating point registers */
425 ACC_REG, /* MAC16 accumulator */
426 SP_REG, /* sp register (aka a1) */
427 RL_REGS, /* preferred reload regs (not sp or fp) */
428 GR_REGS, /* integer registers except sp */
429 AR_REGS, /* all integer registers */
430 ALL_REGS, /* all registers */
431 LIM_REG_CLASSES /* max value + 1 */
434 #define N_REG_CLASSES (int) LIM_REG_CLASSES
436 #define GENERAL_REGS AR_REGS
438 /* An initializer containing the names of the register classes as C
439 string constants. These names are used in writing some of the
441 #define REG_CLASS_NAMES \
454 /* Contents of the register classes. The Nth integer specifies the
455 contents of class N. The way the integer MASK is interpreted is
456 that register R is in the class if 'MASK & (1 << R)' is 1. */
457 #define REG_CLASS_CONTENTS \
459 { 0x00000000, 0x00000000 }, /* no registers */ \
460 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
461 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
462 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
463 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
464 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
465 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
466 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
467 { 0xffffffff, 0x0000000f } /* all registers */ \
470 /* A C expression whose value is a register class containing hard
471 register REGNO. In general there is more that one such class;
472 choose a class which is "minimal", meaning that no smaller class
473 also contains the register. */
474 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
476 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
478 /* Use the Xtensa AR register file for base registers.
479 No index registers. */
480 #define BASE_REG_CLASS AR_REGS
481 #define INDEX_REG_CLASS NO_REGS
483 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
484 16 AR registers may be explicitly used in the RTL, as either
485 incoming or outgoing arguments. */
486 #define SMALL_REGISTER_CLASSES 1
488 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
489 xtensa_preferred_reload_class (X, CLASS, 0)
491 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
492 xtensa_preferred_reload_class (X, CLASS, 1)
494 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
495 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
497 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
498 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
500 /* Return the maximum number of consecutive registers
501 needed to represent mode MODE in a register of class CLASS. */
502 #define CLASS_UNITS(mode, size) \
503 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
505 #define CLASS_MAX_NREGS(CLASS, MODE) \
506 (CLASS_UNITS (MODE, UNITS_PER_WORD))
509 /* Stack layout; function entry, exit and calling. */
511 #define STACK_GROWS_DOWNWARD
513 /* Offset within stack frame to start allocating local variables at. */
514 #define STARTING_FRAME_OFFSET \
515 current_function_outgoing_args_size
517 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
518 they are eliminated to either the stack pointer or hard frame pointer. */
519 #define ELIMINABLE_REGS \
520 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
521 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
522 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
523 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
525 #define CAN_ELIMINATE(FROM, TO) 1
527 /* Specify the initial difference between the specified pair of registers. */
528 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
530 compute_frame_size (get_frame_size ()); \
533 case FRAME_POINTER_REGNUM: \
536 case ARG_POINTER_REGNUM: \
537 (OFFSET) = xtensa_current_frame_size; \
540 gcc_unreachable (); \
544 /* If defined, the maximum amount of space required for outgoing
545 arguments will be computed and placed into the variable
546 'current_function_outgoing_args_size'. No space will be pushed
547 onto the stack for each call; instead, the function prologue
548 should increase the stack frame size by this amount. */
549 #define ACCUMULATE_OUTGOING_ARGS 1
551 /* Offset from the argument pointer register to the first argument's
552 address. On some machines it may depend on the data type of the
553 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
554 location above the first argument's address. */
555 #define FIRST_PARM_OFFSET(FNDECL) 0
557 /* Align stack frames on 128 bits for Xtensa. This is necessary for
558 128-bit datatypes defined in TIE (e.g., for Vectra). */
559 #define STACK_BOUNDARY 128
561 /* Functions do not pop arguments off the stack. */
562 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
564 /* Use a fixed register window size of 8. */
565 #define WINDOW_SIZE 8
567 /* Symbolic macros for the registers used to return integer, floating
568 point, and values of coprocessor and user-defined modes. */
569 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
570 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
572 /* Symbolic macros for the first/last argument registers. */
573 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
574 #define GP_ARG_LAST (GP_REG_FIRST + 7)
575 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
576 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
578 #define MAX_ARGS_IN_REGISTERS 6
580 /* Don't worry about compatibility with PCC. */
581 #define DEFAULT_PCC_STRUCT_RETURN 0
583 /* Define how to find the value returned by a library function
584 assuming the value has mode MODE. Because we have defined
585 TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
586 perform the same promotions as PROMOTE_MODE. */
587 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
588 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
589 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
591 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
593 #define LIBCALL_VALUE(MODE) \
594 XTENSA_LIBCALL_VALUE ((MODE), 0)
596 #define LIBCALL_OUTGOING_VALUE(MODE) \
597 XTENSA_LIBCALL_VALUE ((MODE), 1)
599 /* Define how to find the value returned by a function.
600 VALTYPE is the data type of the value (as a tree).
601 If the precise function being called is known, FUNC is its FUNCTION_DECL;
602 otherwise, FUNC is 0. */
603 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
604 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
605 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
606 ? SImode: TYPE_MODE (VALTYPE), \
607 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
609 #define FUNCTION_VALUE(VALTYPE, FUNC) \
610 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
612 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
613 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
615 /* A C expression that is nonzero if REGNO is the number of a hard
616 register in which the values of called function may come back. A
617 register whose use for returning values is limited to serving as
618 the second of a pair (for a value of type 'double', say) need not
619 be recognized by this macro. If the machine has register windows,
620 so that the caller and the called function use different registers
621 for the return value, this macro should recognize only the caller's
623 #define FUNCTION_VALUE_REGNO_P(N) \
626 /* A C expression that is nonzero if REGNO is the number of a hard
627 register in which function arguments are sometimes passed. This
628 does *not* include implicit arguments such as the static chain and
629 the structure-value address. On many machines, no registers can be
630 used for this purpose since all function arguments are pushed on
632 #define FUNCTION_ARG_REGNO_P(N) \
633 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
635 /* Record the number of argument words seen so far, along with a flag to
636 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
637 is used for both incoming and outgoing args, so a separate flag is
639 typedef struct xtensa_args
645 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
646 init_cumulative_args (&CUM, 0)
648 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
649 init_cumulative_args (&CUM, 1)
651 /* Update the data in CUM to advance over an argument
652 of mode MODE and data type TYPE.
653 (TYPE is null for libcalls where that information may not be available.) */
654 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
655 function_arg_advance (&CUM, MODE, TYPE)
657 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
658 function_arg (&CUM, MODE, TYPE, FALSE)
660 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
661 function_arg (&CUM, MODE, TYPE, TRUE)
663 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
665 /* Profiling Xtensa code is typically done with the built-in profiling
666 feature of Tensilica's instruction set simulator, which does not
667 require any compiler support. Profiling code on a real (i.e.,
668 non-simulated) Xtensa processor is currently only supported by
669 GNU/Linux with glibc. The glibc version of _mcount doesn't require
670 counter variables. The _mcount function needs the current PC and
671 the current return address to identify an arc in the call graph.
672 Pass the current return address as the first argument; the current
673 PC is available as a0 in _mcount's register window. Both of these
674 values contain window size information in the two most significant
675 bits; we assume that _mcount will mask off those bits. The call to
676 _mcount uses a window size of 8 to make sure that it doesn't clobber
677 any incoming argument values. */
679 #define NO_PROFILE_COUNTERS 1
681 #define FUNCTION_PROFILER(FILE, LABELNO) \
683 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
686 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
687 fprintf (FILE, "\tcallx8\ta8\n"); \
690 fprintf (FILE, "\tcall8\t_mcount\n"); \
693 /* Stack pointer value doesn't matter at exit. */
694 #define EXIT_IGNORE_STACK 1
696 /* A C statement to output, on the stream FILE, assembler code for a
697 block of data that contains the constant parts of a trampoline.
698 This code should not include a label--the label is taken care of
701 For Xtensa, the trampoline must perform an entry instruction with a
702 minimal stack frame in order to get some free registers. Once the
703 actual call target is known, the proper stack frame size is extracted
704 from the entry instruction at the target and the current frame is
705 adjusted to match. The trampoline then transfers control to the
706 instruction following the entry at the target. Note: this assumes
707 that the target begins with an entry instruction. */
709 /* minimum frame = reg save area (4 words) plus static chain (1 word)
710 and the total number of words must be a multiple of 128 bits */
711 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
713 #define TRAMPOLINE_TEMPLATE(STREAM) \
715 fprintf (STREAM, "\t.begin no-transform\n"); \
716 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
718 /* save the return address */ \
719 fprintf (STREAM, "\tmov\ta10, a0\n"); \
721 /* Use a CALL0 instruction to skip past the constants and in the \
722 process get the PC into A0. This allows PC-relative access to \
723 the constants without relying on L32R, which may not always be \
726 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
727 fprintf (STREAM, "\t.align\t4\n"); \
728 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
729 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
730 fprintf (STREAM, ".Lskipconsts:\n"); \
732 /* store the static chain */ \
733 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
734 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
735 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
737 /* set the proper stack pointer value */ \
738 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
739 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
740 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
741 TARGET_BIG_ENDIAN ? 8 : 12); \
742 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
743 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
744 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
745 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
747 /* restore the return address */ \
748 fprintf (STREAM, "\tmov\ta0, a10\n"); \
750 /* jump to the instruction following the entry */ \
751 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
752 fprintf (STREAM, "\tjx\ta8\n"); \
753 fprintf (STREAM, "\t.byte\t0\n"); \
754 fprintf (STREAM, "\t.end no-transform\n"); \
757 /* Size in bytes of the trampoline, as an integer. Make sure this is
758 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
759 #define TRAMPOLINE_SIZE 60
761 /* Alignment required for trampolines, in bits. */
762 #define TRAMPOLINE_ALIGNMENT (32)
764 /* A C statement to initialize the variable parts of a trampoline. */
765 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
768 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
769 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
770 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
771 0, VOIDmode, 1, addr, Pmode); \
774 /* Implement `va_start' for varargs and stdarg. */
775 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
776 xtensa_va_start (valist, nextarg)
778 /* If defined, a C expression that produces the machine-specific code
779 to setup the stack so that arbitrary frames can be accessed.
781 On Xtensa, a stack back-trace must always begin from the stack pointer,
782 so that the register overflow save area can be located. However, the
783 stack-walking code in GCC always begins from the hard_frame_pointer
784 register, not the stack pointer. The frame pointer is usually equal
785 to the stack pointer, but the __builtin_return_address and
786 __builtin_frame_address functions will not work if count > 0 and
787 they are called from a routine that uses alloca. These functions
788 are not guaranteed to work at all if count > 0 so maybe that is OK.
790 A nicer solution would be to allow the architecture-specific files to
791 specify whether to start from the stack pointer or frame pointer. That
792 would also allow us to skip the machine->accesses_prev_frame stuff that
793 we currently need to ensure that there is a frame pointer when these
794 builtin functions are used. */
796 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
798 /* A C expression whose value is RTL representing the address in a
799 stack frame where the pointer to the caller's frame is stored.
800 Assume that FRAMEADDR is an RTL expression for the address of the
803 For Xtensa, there is no easy way to get the frame pointer if it is
804 not equivalent to the stack pointer. Moreover, the result of this
805 macro is used for continuing to walk back up the stack, so it must
806 return the stack pointer address. Thus, there is some inconsistency
807 here in that __builtin_frame_address will return the frame pointer
808 when count == 0 and the stack pointer when count > 0. */
810 #define DYNAMIC_CHAIN_ADDRESS(frame) \
811 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
813 /* Define this if the return address of a particular stack frame is
814 accessed from the frame pointer of the previous stack frame. */
815 #define RETURN_ADDR_IN_PREVIOUS_FRAME
817 /* A C expression whose value is RTL representing the value of the
818 return address for the frame COUNT steps up from the current
819 frame, after the prologue. */
820 #define RETURN_ADDR_RTX xtensa_return_addr
822 /* Addressing modes, and classification of registers for them. */
824 /* C expressions which are nonzero if register number NUM is suitable
825 for use as a base or index register in operand addresses. It may
826 be either a suitable hard register or a pseudo register that has
827 been allocated such a hard register. The difference between an
828 index register and a base register is that the index register may
831 #define REGNO_OK_FOR_BASE_P(NUM) \
832 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
834 #define REGNO_OK_FOR_INDEX_P(NUM) 0
836 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
837 valid for use as a base or index register. For hard registers, it
838 should always accept those which the hardware permits and reject
839 the others. Whether the macro accepts or rejects pseudo registers
840 must be controlled by `REG_OK_STRICT'. This usually requires two
841 variant definitions, of which `REG_OK_STRICT' controls the one
842 actually used. The difference between an index register and a base
843 register is that the index register may be scaled. */
847 #define REG_OK_FOR_INDEX_P(X) 0
848 #define REG_OK_FOR_BASE_P(X) \
849 REGNO_OK_FOR_BASE_P (REGNO (X))
851 #else /* !REG_OK_STRICT */
853 #define REG_OK_FOR_INDEX_P(X) 0
854 #define REG_OK_FOR_BASE_P(X) \
855 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
857 #endif /* !REG_OK_STRICT */
859 /* Maximum number of registers that can appear in a valid memory address. */
860 #define MAX_REGS_PER_ADDRESS 1
862 /* Identify valid Xtensa addresses. */
863 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
865 rtx xinsn = (ADDR); \
867 /* allow constant pool addresses */ \
868 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
869 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
872 while (GET_CODE (xinsn) == SUBREG) \
873 xinsn = SUBREG_REG (xinsn); \
875 /* allow base registers */ \
876 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
879 /* check for "register + offset" addressing */ \
880 if (GET_CODE (xinsn) == PLUS) \
882 rtx xplus0 = XEXP (xinsn, 0); \
883 rtx xplus1 = XEXP (xinsn, 1); \
884 enum rtx_code code0; \
885 enum rtx_code code1; \
887 while (GET_CODE (xplus0) == SUBREG) \
888 xplus0 = SUBREG_REG (xplus0); \
889 code0 = GET_CODE (xplus0); \
891 while (GET_CODE (xplus1) == SUBREG) \
892 xplus1 = SUBREG_REG (xplus1); \
893 code1 = GET_CODE (xplus1); \
895 /* swap operands if necessary so the register is first */ \
896 if (code0 != REG && code1 == REG) \
898 xplus0 = XEXP (xinsn, 1); \
899 xplus1 = XEXP (xinsn, 0); \
900 code0 = GET_CODE (xplus0); \
901 code1 = GET_CODE (xplus1); \
904 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
905 && code1 == CONST_INT \
906 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
913 /* A C expression that is 1 if the RTX X is a constant which is a
914 valid address. This is defined to be the same as 'CONSTANT_P (X)',
915 but rejecting CONST_DOUBLE. */
916 #define CONSTANT_ADDRESS_P(X) \
917 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
918 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
919 || (GET_CODE (X) == CONST)))
921 /* Nonzero if the constant value X is a legitimate general operand.
922 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
923 #define LEGITIMATE_CONSTANT_P(X) 1
925 /* A C expression that is nonzero if X is a legitimate immediate
926 operand on the target machine when generating position independent
928 #define LEGITIMATE_PIC_OPERAND_P(X) \
929 ((GET_CODE (X) != SYMBOL_REF \
930 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
931 && GET_CODE (X) != LABEL_REF \
932 && GET_CODE (X) != CONST)
934 /* Tell GCC how to use ADDMI to generate addresses. */
935 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
938 if (GET_CODE (xinsn) == PLUS) \
940 rtx plus0 = XEXP (xinsn, 0); \
941 rtx plus1 = XEXP (xinsn, 1); \
943 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
945 plus0 = XEXP (xinsn, 1); \
946 plus1 = XEXP (xinsn, 0); \
949 if (GET_CODE (plus0) == REG \
950 && GET_CODE (plus1) == CONST_INT \
951 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
952 && !xtensa_simm8 (INTVAL (plus1)) \
953 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
954 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
956 rtx temp = gen_reg_rtx (Pmode); \
957 emit_insn (gen_rtx_SET (Pmode, temp, \
958 gen_rtx_PLUS (Pmode, plus0, \
959 GEN_INT (INTVAL (plus1) & ~0xff)))); \
960 (X) = gen_rtx_PLUS (Pmode, temp, \
961 GEN_INT (INTVAL (plus1) & 0xff)); \
968 /* Treat constant-pool references as "mode dependent" since they can
969 only be accessed with SImode loads. This works around a bug in the
970 combiner where a constant pool reference is temporarily converted
971 to an HImode load, which is then assumed to zero-extend based on
972 our definition of LOAD_EXTEND_OP. This is wrong because the high
973 bits of a 16-bit value in the constant pool are now sign-extended
976 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
978 if (constantpool_address_p (ADDR)) \
982 /* Specify the machine mode that this machine uses
983 for the index in the tablejump instruction. */
984 #define CASE_VECTOR_MODE (SImode)
986 /* Define this as 1 if 'char' should by default be signed; else as 0. */
987 #define DEFAULT_SIGNED_CHAR 0
989 /* Max number of bytes we can move from memory to memory
990 in one reasonably fast instruction. */
992 #define MAX_MOVE_MAX 4
994 /* Prefer word-sized loads. */
995 #define SLOW_BYTE_ACCESS 1
997 /* Shift instructions ignore all but the low-order few bits. */
998 #define SHIFT_COUNT_TRUNCATED 1
1000 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1001 is done just by pretending it is already truncated. */
1002 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1004 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1005 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
1007 /* Specify the machine mode that pointers have.
1008 After generation of rtl, the compiler makes no further distinction
1009 between pointers and any other objects of this machine mode. */
1010 #define Pmode SImode
1012 /* A function address in a call instruction is a word address (for
1013 indexing purposes) so give the MEM rtx a words's mode. */
1014 #define FUNCTION_MODE SImode
1016 /* A C expression for the cost of moving data from a register in
1017 class FROM to one in class TO. The classes are expressed using
1018 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1019 the default; other values are interpreted relative to that. */
1020 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1021 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1023 : (reg_class_subset_p ((FROM), AR_REGS) \
1024 && reg_class_subset_p ((TO), AR_REGS) \
1026 : (reg_class_subset_p ((FROM), AR_REGS) \
1027 && (TO) == ACC_REG \
1029 : ((FROM) == ACC_REG \
1030 && reg_class_subset_p ((TO), AR_REGS) \
1034 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1036 #define BRANCH_COST 3
1038 /* How to refer to registers in assembler output.
1039 This sequence is indexed by compiler's hard-register-number (see above). */
1040 #define REGISTER_NAMES \
1042 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1043 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1044 "fp", "argp", "b0", \
1045 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1046 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1050 /* If defined, a C initializer for an array of structures containing a
1051 name and a register number. This macro defines additional names
1052 for hard registers, thus allowing the 'asm' option in declarations
1053 to refer to registers using alternate names. */
1054 #define ADDITIONAL_REGISTER_NAMES \
1056 { "a1", 1 + GP_REG_FIRST } \
1059 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1060 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1062 /* Recognize machine-specific patterns that may appear within
1063 constants. Used for PIC-specific UNSPECs. */
1064 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1066 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1068 switch (XINT ((X), 1)) \
1071 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1072 fputs ("@PLT", (STREAM)); \
1083 /* Globalizing directive for a label. */
1084 #define GLOBAL_ASM_OP "\t.global\t"
1086 /* Declare an uninitialized external linkage data object. */
1087 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1088 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1090 /* This is how to output an element of a case-vector that is absolute. */
1091 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1092 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1093 LOCAL_LABEL_PREFIX, VALUE)
1095 /* This is how to output an element of a case-vector that is relative.
1096 This is used for pc-relative code. */
1097 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1099 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1100 LOCAL_LABEL_PREFIX, (VALUE), \
1101 LOCAL_LABEL_PREFIX, (REL)); \
1104 /* This is how to output an assembler line that says to advance the
1105 location counter to a multiple of 2**LOG bytes. */
1106 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1109 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1112 /* Indicate that jump tables go in the text section. This is
1113 necessary when compiling PIC code. */
1114 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1117 /* Define the strings to put out for each section in the object file. */
1118 #define TEXT_SECTION_ASM_OP "\t.text"
1119 #define DATA_SECTION_ASM_OP "\t.data"
1120 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1123 /* Define output to appear before the constant pool. */
1124 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1128 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1129 switch_to_section (function_section (FUNDECL)); \
1130 fprintf (FILE, "\t.literal_position\n"); \
1135 /* A C statement (with or without semicolon) to output a constant in
1136 the constant pool, if it needs special treatment. */
1137 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1139 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1143 /* How to start an assembler comment. */
1144 #define ASM_COMMENT_START "#"
1146 /* Exception handling TODO!! */
1147 #define DWARF_UNWIND_INFO 0
1149 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1150 section in where code resides. We have to write it as asm code. Use
1151 a MOVI and let the assembler relax it -- for the .init and .fini
1152 sections, the assembler knows to put the literal in the right
1154 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1155 asm (SECTION_OP "\n\
1156 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1158 TEXT_SECTION_ASM_OP);