1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 /* Enumeration for all of the relational tests, so that we can build
55 arrays indexed by the test type, and not worry about the order
73 /* Array giving truth value on whether or not a given hard register
74 can support a given mode. */
75 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
77 /* Current frame size calculated by compute_frame_size. */
78 unsigned xtensa_current_frame_size;
80 /* Largest block move to handle in-line. */
81 #define LARGEST_MOVE_RATIO 15
83 /* Define the structure for the machine field in struct function. */
84 struct GTY(()) machine_function
86 int accesses_prev_frame;
90 rtx set_frame_ptr_insn;
93 /* Vector, indexed by hard register number, which contains 1 for a
94 register that is allowable in a candidate for leaf function
97 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
101 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
105 /* Map hard register number to register class */
106 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
108 RL_REGS, SP_REG, RL_REGS, RL_REGS,
109 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
110 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
111 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
112 AR_REGS, AR_REGS, BR_REGS,
113 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
114 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
115 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
116 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
120 static void xtensa_option_override (void);
121 static enum internal_test map_test_to_internal_test (enum rtx_code);
122 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
123 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
124 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
125 static rtx fixup_subreg_mem (rtx);
126 static struct machine_function * xtensa_init_machine_status (void);
127 static rtx xtensa_legitimize_tls_address (rtx);
128 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
129 static bool xtensa_return_in_msb (const_tree);
130 static void printx (FILE *, signed int);
131 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
132 static rtx xtensa_builtin_saveregs (void);
133 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
134 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
135 int) ATTRIBUTE_UNUSED;
136 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
137 unsigned HOST_WIDE_INT);
138 static bool xtensa_rtx_costs (rtx, int, int, int *, bool);
139 static tree xtensa_build_builtin_va_list (void);
140 static bool xtensa_return_in_memory (const_tree, const_tree);
141 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
143 static void xtensa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
145 static rtx xtensa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
147 static rtx xtensa_function_incoming_arg (CUMULATIVE_ARGS *,
148 enum machine_mode, const_tree, bool);
149 static rtx xtensa_function_value (const_tree, const_tree, bool);
150 static rtx xtensa_libcall_value (enum machine_mode, const_rtx);
151 static bool xtensa_function_value_regno_p (const unsigned int);
152 static unsigned int xtensa_function_arg_boundary (enum machine_mode,
154 static void xtensa_init_builtins (void);
155 static tree xtensa_fold_builtin (tree, int, tree *, bool);
156 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
157 static void xtensa_va_start (tree, rtx);
158 static bool xtensa_frame_pointer_required (void);
159 static rtx xtensa_static_chain (const_tree, bool);
160 static void xtensa_asm_trampoline_template (FILE *);
161 static void xtensa_trampoline_init (rtx, tree, rtx);
162 static bool xtensa_output_addr_const_extra (FILE *, rtx);
164 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
167 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
169 static const struct default_options xtensa_option_optimization_table[] =
171 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
172 /* Reordering blocks for Xtensa is not a good idea unless the
173 compiler understands the range of conditional branches.
174 Currently all branch relaxation for Xtensa is handled in the
175 assembler, so GCC cannot do a good job of reordering blocks.
176 Do not enable reordering unless it is explicitly requested. */
177 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
178 { OPT_LEVELS_NONE, 0, NULL, 0 }
182 /* This macro generates the assembly code for function exit,
183 on machines that need it. If FUNCTION_EPILOGUE is not defined
184 then individual return instructions are generated for each
185 return statement. Args are same as for FUNCTION_PROLOGUE. */
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
190 /* These hooks specify assembly directives for creating certain kinds
191 of integer object. */
193 #undef TARGET_ASM_ALIGNED_SI_OP
194 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
196 #undef TARGET_ASM_SELECT_RTX_SECTION
197 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
199 #undef TARGET_DEFAULT_TARGET_FLAGS
200 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
202 #undef TARGET_LEGITIMIZE_ADDRESS
203 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
205 #undef TARGET_RTX_COSTS
206 #define TARGET_RTX_COSTS xtensa_rtx_costs
207 #undef TARGET_ADDRESS_COST
208 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
210 #undef TARGET_BUILD_BUILTIN_VA_LIST
211 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
213 #undef TARGET_EXPAND_BUILTIN_VA_START
214 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
216 #undef TARGET_PROMOTE_FUNCTION_MODE
217 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
218 #undef TARGET_PROMOTE_PROTOTYPES
219 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
221 #undef TARGET_RETURN_IN_MEMORY
222 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
223 #undef TARGET_FUNCTION_VALUE
224 #define TARGET_FUNCTION_VALUE xtensa_function_value
225 #undef TARGET_LIBCALL_VALUE
226 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
227 #undef TARGET_FUNCTION_VALUE_REGNO_P
228 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
230 #undef TARGET_SPLIT_COMPLEX_ARG
231 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
232 #undef TARGET_MUST_PASS_IN_STACK
233 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
234 #undef TARGET_FUNCTION_ARG_ADVANCE
235 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
236 #undef TARGET_FUNCTION_ARG
237 #define TARGET_FUNCTION_ARG xtensa_function_arg
238 #undef TARGET_FUNCTION_INCOMING_ARG
239 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
240 #undef TARGET_FUNCTION_ARG_BOUNDARY
241 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
243 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
244 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
245 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
246 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
248 #undef TARGET_RETURN_IN_MSB
249 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
251 #undef TARGET_INIT_BUILTINS
252 #define TARGET_INIT_BUILTINS xtensa_init_builtins
253 #undef TARGET_FOLD_BUILTIN
254 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
255 #undef TARGET_EXPAND_BUILTIN
256 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
258 #undef TARGET_SECONDARY_RELOAD
259 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
261 #undef TARGET_HAVE_TLS
262 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
264 #undef TARGET_CANNOT_FORCE_CONST_MEM
265 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
267 #undef TARGET_LEGITIMATE_ADDRESS_P
268 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
270 #undef TARGET_FRAME_POINTER_REQUIRED
271 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
273 #undef TARGET_STATIC_CHAIN
274 #define TARGET_STATIC_CHAIN xtensa_static_chain
275 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
276 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
277 #undef TARGET_TRAMPOLINE_INIT
278 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
280 #undef TARGET_OPTION_OVERRIDE
281 #define TARGET_OPTION_OVERRIDE xtensa_option_override
282 #undef TARGET_OPTION_OPTIMIZATION_TABLE
283 #define TARGET_OPTION_OPTIMIZATION_TABLE xtensa_option_optimization_table
285 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
286 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
288 struct gcc_target targetm = TARGET_INITIALIZER;
291 /* Functions to test Xtensa immediate operand validity. */
294 xtensa_simm8 (HOST_WIDE_INT v)
296 return v >= -128 && v <= 127;
301 xtensa_simm8x256 (HOST_WIDE_INT v)
303 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
308 xtensa_simm12b (HOST_WIDE_INT v)
310 return v >= -2048 && v <= 2047;
315 xtensa_uimm8 (HOST_WIDE_INT v)
317 return v >= 0 && v <= 255;
322 xtensa_uimm8x2 (HOST_WIDE_INT v)
324 return (v & 1) == 0 && (v >= 0 && v <= 510);
329 xtensa_uimm8x4 (HOST_WIDE_INT v)
331 return (v & 3) == 0 && (v >= 0 && v <= 1020);
336 xtensa_b4const (HOST_WIDE_INT v)
363 xtensa_b4const_or_zero (HOST_WIDE_INT v)
367 return xtensa_b4const (v);
372 xtensa_b4constu (HOST_WIDE_INT v)
399 xtensa_mask_immediate (HOST_WIDE_INT v)
401 #define MAX_MASK_SIZE 16
404 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
417 /* This is just like the standard true_regnum() function except that it
418 works even when reg_renumber is not initialized. */
421 xt_true_regnum (rtx x)
423 if (GET_CODE (x) == REG)
426 && REGNO (x) >= FIRST_PSEUDO_REGISTER
427 && reg_renumber[REGNO (x)] >= 0)
428 return reg_renumber[REGNO (x)];
431 if (GET_CODE (x) == SUBREG)
433 int base = xt_true_regnum (SUBREG_REG (x));
434 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
435 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
436 GET_MODE (SUBREG_REG (x)),
437 SUBREG_BYTE (x), GET_MODE (x));
444 xtensa_valid_move (enum machine_mode mode, rtx *operands)
446 /* Either the destination or source must be a register, and the
447 MAC16 accumulator doesn't count. */
449 if (register_operand (operands[0], mode))
451 int dst_regnum = xt_true_regnum (operands[0]);
453 /* The stack pointer can only be assigned with a MOVSP opcode. */
454 if (dst_regnum == STACK_POINTER_REGNUM)
455 return (mode == SImode
456 && register_operand (operands[1], mode)
457 && !ACC_REG_P (xt_true_regnum (operands[1])));
459 if (!ACC_REG_P (dst_regnum))
462 if (register_operand (operands[1], mode))
464 int src_regnum = xt_true_regnum (operands[1]);
465 if (!ACC_REG_P (src_regnum))
473 smalloffset_mem_p (rtx op)
475 if (GET_CODE (op) == MEM)
477 rtx addr = XEXP (op, 0);
478 if (GET_CODE (addr) == REG)
479 return BASE_REG_P (addr, 0);
480 if (GET_CODE (addr) == PLUS)
482 rtx offset = XEXP (addr, 0);
484 if (GET_CODE (offset) != CONST_INT)
485 offset = XEXP (addr, 1);
486 if (GET_CODE (offset) != CONST_INT)
489 val = INTVAL (offset);
490 return (val & 3) == 0 && (val >= 0 && val <= 60);
498 constantpool_address_p (rtx addr)
502 if (GET_CODE (addr) == CONST)
506 /* Only handle (PLUS (SYM, OFFSET)) form. */
507 addr = XEXP (addr, 0);
508 if (GET_CODE (addr) != PLUS)
511 /* Make sure the address is word aligned. */
512 offset = XEXP (addr, 1);
513 if ((GET_CODE (offset) != CONST_INT)
514 || ((INTVAL (offset) & 3) != 0))
517 sym = XEXP (addr, 0);
520 if ((GET_CODE (sym) == SYMBOL_REF)
521 && CONSTANT_POOL_ADDRESS_P (sym))
528 constantpool_mem_p (rtx op)
530 if (GET_CODE (op) == SUBREG)
531 op = SUBREG_REG (op);
532 if (GET_CODE (op) == MEM)
533 return constantpool_address_p (XEXP (op, 0));
538 /* Return TRUE if X is a thread-local symbol. */
541 xtensa_tls_symbol_p (rtx x)
543 if (! TARGET_HAVE_TLS)
546 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
551 xtensa_extend_reg (rtx dst, rtx src)
553 rtx temp = gen_reg_rtx (SImode);
554 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
556 /* Generate paradoxical subregs as needed so that the modes match. */
557 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
558 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
560 emit_insn (gen_ashlsi3 (temp, src, shift));
561 emit_insn (gen_ashrsi3 (dst, temp, shift));
566 xtensa_mem_offset (unsigned v, enum machine_mode mode)
571 /* Handle the worst case for block moves. See xtensa_expand_block_move
572 where we emit an optimized block move operation if the block can be
573 moved in < "move_ratio" pieces. The worst case is when the block is
574 aligned but has a size of (3 mod 4) (does this happen?) so that the
575 last piece requires a byte load/store. */
576 return (xtensa_uimm8 (v)
577 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
580 return xtensa_uimm8 (v);
583 return xtensa_uimm8x2 (v);
586 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
592 return xtensa_uimm8x4 (v);
596 /* Make normal rtx_code into something we can index from an array. */
598 static enum internal_test
599 map_test_to_internal_test (enum rtx_code test_code)
601 enum internal_test test = ITEST_MAX;
606 case EQ: test = ITEST_EQ; break;
607 case NE: test = ITEST_NE; break;
608 case GT: test = ITEST_GT; break;
609 case GE: test = ITEST_GE; break;
610 case LT: test = ITEST_LT; break;
611 case LE: test = ITEST_LE; break;
612 case GTU: test = ITEST_GTU; break;
613 case GEU: test = ITEST_GEU; break;
614 case LTU: test = ITEST_LTU; break;
615 case LEU: test = ITEST_LEU; break;
622 /* Generate the code to compare two integer values. The return value is
623 the comparison expression. */
626 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
627 rtx cmp0, /* first operand to compare */
628 rtx cmp1, /* second operand to compare */
629 int *p_invert /* whether branch needs to reverse test */)
633 enum rtx_code test_code; /* test code to use in insn */
634 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
635 int const_add; /* constant to add (convert LE -> LT) */
636 int reverse_regs; /* reverse registers in test */
637 int invert_const; /* != 0 if invert value if cmp1 is constant */
638 int invert_reg; /* != 0 if invert value if cmp1 is register */
639 int unsignedp; /* != 0 for unsigned comparisons. */
642 static struct cmp_info info[ (int)ITEST_MAX ] = {
644 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
645 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
647 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
648 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
649 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
650 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
652 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
653 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
654 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
655 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
658 enum internal_test test;
659 enum machine_mode mode;
660 struct cmp_info *p_info;
662 test = map_test_to_internal_test (test_code);
663 gcc_assert (test != ITEST_MAX);
665 p_info = &info[ (int)test ];
667 mode = GET_MODE (cmp0);
668 if (mode == VOIDmode)
669 mode = GET_MODE (cmp1);
671 /* Make sure we can handle any constants given to us. */
672 if (GET_CODE (cmp1) == CONST_INT)
674 HOST_WIDE_INT value = INTVAL (cmp1);
675 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
677 /* if the immediate overflows or does not fit in the immediate field,
678 spill it to a register */
680 if ((p_info->unsignedp ?
681 (uvalue + p_info->const_add > uvalue) :
682 (value + p_info->const_add > value)) != (p_info->const_add > 0))
684 cmp1 = force_reg (mode, cmp1);
686 else if (!(p_info->const_range_p) (value + p_info->const_add))
688 cmp1 = force_reg (mode, cmp1);
691 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
693 cmp1 = force_reg (mode, cmp1);
696 /* See if we need to invert the result. */
697 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
698 ? p_info->invert_const
699 : p_info->invert_reg);
701 /* Comparison to constants, may involve adding 1 to change a LT into LE.
702 Comparison between two registers, may involve switching operands. */
703 if (GET_CODE (cmp1) == CONST_INT)
705 if (p_info->const_add != 0)
706 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
709 else if (p_info->reverse_regs)
716 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
720 /* Generate the code to compare two float values. The return value is
721 the comparison expression. */
724 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
725 rtx cmp0, /* first operand to compare */
726 rtx cmp1 /* second operand to compare */)
728 rtx (*gen_fn) (rtx, rtx, rtx);
730 int reverse_regs, invert;
734 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
735 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
736 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
737 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
738 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
739 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
740 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
741 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
742 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
743 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
744 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
745 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
747 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
749 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
751 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
752 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
762 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
763 emit_insn (gen_fn (brtmp, cmp0, cmp1));
765 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
770 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
772 enum rtx_code test_code = GET_CODE (operands[0]);
773 rtx cmp0 = operands[1];
774 rtx cmp1 = operands[2];
783 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
787 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
791 if (!TARGET_HARD_FLOAT)
792 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
795 cmp = gen_float_relational (test_code, cmp0, cmp1);
799 /* Generate the branch. */
801 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
810 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
811 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
818 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
825 /* Jump optimization calls get_condition() which canonicalizes
826 comparisons like (GE x <const>) to (GT x <const-1>).
827 Transform those comparisons back to GE, since that is the
828 comparison supported in Xtensa. We shouldn't have to
829 transform <LE x const> comparisons, because neither
830 xtensa_expand_conditional_branch() nor get_condition() will
833 if ((code == GT) && (op1 == constm1_rtx))
838 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
840 if (boolean_operator (cmp, VOIDmode))
842 /* Swap the operands to make const0 second. */
843 if (op0 == const0_rtx)
849 /* If not comparing against zero, emit a comparison (subtract). */
850 if (op1 != const0_rtx)
852 op0 = expand_binop (SImode, sub_optab, op0, op1,
853 0, 0, OPTAB_LIB_WIDEN);
857 else if (branch_operator (cmp, VOIDmode))
859 /* Swap the operands to make const0 second. */
860 if (op0 == const0_rtx)
867 case LT: code = GE; break;
868 case GE: code = LT; break;
869 default: gcc_unreachable ();
873 if (op1 != const0_rtx)
879 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
882 if (TARGET_HARD_FLOAT && mode == SFmode)
883 return gen_float_relational (code, op0, op1);
890 xtensa_expand_conditional_move (rtx *operands, int isflt)
892 rtx dest = operands[0];
893 rtx cmp = operands[1];
894 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
895 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
897 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
898 XEXP (cmp, 0), XEXP (cmp, 1))))
902 gen_fn = (cmp_mode == SImode
903 ? gen_movsfcc_internal0
904 : gen_movsfcc_internal1);
906 gen_fn = (cmp_mode == SImode
907 ? gen_movsicc_internal0
908 : gen_movsicc_internal1);
910 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
916 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
918 rtx dest = operands[0];
920 rtx one_tmp, zero_tmp;
921 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
923 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
924 operands[2], operands[3])))
927 one_tmp = gen_reg_rtx (SImode);
928 zero_tmp = gen_reg_rtx (SImode);
929 emit_insn (gen_movsi (one_tmp, const_true_rtx));
930 emit_insn (gen_movsi (zero_tmp, const0_rtx));
932 gen_fn = (cmp_mode == SImode
933 ? gen_movsicc_internal0
934 : gen_movsicc_internal1);
935 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
940 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
941 for the output, i.e., the input operands are twice as big as MODE. */
944 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
946 switch (GET_CODE (operands[1]))
949 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
950 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
954 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
955 operands[2] = adjust_address (operands[1], mode, 0);
960 split_double (operands[1], &operands[2], &operands[3]);
967 switch (GET_CODE (operands[0]))
970 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
971 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
975 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
976 operands[0] = adjust_address (operands[0], mode, 0);
985 /* Emit insns to move operands[1] into operands[0].
986 Return 1 if we have written out everything that needs to be done to
987 do the move. Otherwise, return 0 and the caller will emit the move
991 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
993 rtx src = operands[1];
996 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
998 rtx dst = operands[0];
1000 if (xtensa_tls_referenced_p (src))
1004 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
1006 addend = XEXP (XEXP (src, 0), 1);
1007 src = XEXP (XEXP (src, 0), 0);
1010 src = xtensa_legitimize_tls_address (src);
1013 src = gen_rtx_PLUS (mode, src, addend);
1014 src = force_operand (src, dst);
1016 emit_move_insn (dst, src);
1020 if (! TARGET_CONST16)
1022 src = force_const_mem (SImode, src);
1026 /* PC-relative loads are always SImode, and CONST16 is only
1027 supported in the movsi pattern, so add a SUBREG for any other
1032 if (register_operand (dst, mode))
1034 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1039 src = force_reg (SImode, src);
1040 src = gen_lowpart_SUBREG (mode, src);
1046 if (!(reload_in_progress | reload_completed)
1047 && !xtensa_valid_move (mode, operands))
1048 operands[1] = force_reg (mode, operands[1]);
1050 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1052 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1053 instruction won't be recognized after reload, so we remove the
1054 subreg and adjust mem accordingly. */
1055 if (reload_in_progress)
1057 operands[0] = fixup_subreg_mem (operands[0]);
1058 operands[1] = fixup_subreg_mem (operands[1]);
1065 fixup_subreg_mem (rtx x)
1067 if (GET_CODE (x) == SUBREG
1068 && GET_CODE (SUBREG_REG (x)) == REG
1069 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1072 gen_rtx_SUBREG (GET_MODE (x),
1073 reg_equiv_mem [REGNO (SUBREG_REG (x))],
1075 x = alter_subreg (&temp);
1081 /* Check if an incoming argument in a7 is expected to be used soon and
1082 if OPND is a register or register pair that includes a7. If so,
1083 create a new pseudo and copy a7 into that pseudo at the very
1084 beginning of the function, followed by the special "set_frame_ptr"
1085 unspec_volatile insn. The return value is either the original
1086 operand, if it is not a7, or the new pseudo containing a copy of
1087 the incoming argument. This is necessary because the register
1088 allocator will ignore conflicts with a7 and may either assign some
1089 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1090 the incoming argument in a7. By copying the argument out of a7 as
1091 the very first thing, and then immediately following that with an
1092 unspec_volatile to keep the scheduler away, we should avoid any
1093 problems. Putting the set_frame_ptr insn at the beginning, with
1094 only the a7 copy before it, also makes it easier for the prologue
1095 expander to initialize the frame pointer after the a7 copy and to
1096 fix up the a7 copy to use the stack pointer instead of the frame
1100 xtensa_copy_incoming_a7 (rtx opnd)
1102 rtx entry_insns = 0;
1104 enum machine_mode mode;
1106 if (!cfun->machine->need_a7_copy)
1109 /* This function should never be called again once a7 has been copied. */
1110 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1112 mode = GET_MODE (opnd);
1114 /* The operand using a7 may come in a later instruction, so just return
1115 the original operand if it doesn't use a7. */
1117 if (GET_CODE (reg) == SUBREG)
1119 gcc_assert (SUBREG_BYTE (reg) == 0);
1120 reg = SUBREG_REG (reg);
1122 if (GET_CODE (reg) != REG
1123 || REGNO (reg) > A7_REG
1124 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1127 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1128 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1130 cfun->machine->need_a7_copy = false;
1132 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1133 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1136 tmp = gen_reg_rtx (mode);
1142 /* Copy the value out of A7 here but keep the first word in A6 until
1143 after the set_frame_ptr insn. Otherwise, the register allocator
1144 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1146 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1147 gen_raw_REG (SImode, A7_REG)));
1150 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1153 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1156 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1159 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1165 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1167 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1168 if (mode == DFmode || mode == DImode)
1169 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1170 gen_rtx_REG (SImode, A7_REG - 1)));
1171 entry_insns = get_insns ();
1174 if (cfun->machine->vararg_a7)
1176 /* This is called from within builtin_saveregs, which will insert the
1177 saveregs code at the function entry, ahead of anything placed at
1178 the function entry now. Instead, save the sequence to be inserted
1179 at the beginning of the saveregs code. */
1180 cfun->machine->vararg_a7_copy = entry_insns;
1184 /* Put entry_insns after the NOTE that starts the function. If
1185 this is inside a start_sequence, make the outer-level insn
1186 chain current, so the code is placed at the start of the
1188 push_topmost_sequence ();
1189 /* Do not use entry_of_function() here. This is called from within
1190 expand_function_start, when the CFG still holds GIMPLE. */
1191 emit_insn_after (entry_insns, get_insns ());
1192 pop_topmost_sequence ();
1199 /* Try to expand a block move operation to a sequence of RTL move
1200 instructions. If not optimizing, or if the block size is not a
1201 constant, or if the block is too large, the expansion fails and GCC
1202 falls back to calling memcpy().
1204 operands[0] is the destination
1205 operands[1] is the source
1206 operands[2] is the length
1207 operands[3] is the alignment */
1210 xtensa_expand_block_move (rtx *operands)
1212 static const enum machine_mode mode_from_align[] =
1214 VOIDmode, QImode, HImode, VOIDmode, SImode,
1217 rtx dst_mem = operands[0];
1218 rtx src_mem = operands[1];
1219 HOST_WIDE_INT bytes, align;
1220 int num_pieces, move_ratio;
1222 enum machine_mode mode[2];
1231 /* If this is not a fixed size move, just call memcpy. */
1232 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1235 bytes = INTVAL (operands[2]);
1236 align = INTVAL (operands[3]);
1238 /* Anything to move? */
1242 if (align > MOVE_MAX)
1245 /* Decide whether to expand inline based on the optimization level. */
1248 move_ratio = LARGEST_MOVE_RATIO;
1249 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1250 if (num_pieces > move_ratio)
1253 x = XEXP (dst_mem, 0);
1256 x = force_reg (Pmode, x);
1257 dst_mem = replace_equiv_address (dst_mem, x);
1260 x = XEXP (src_mem, 0);
1263 x = force_reg (Pmode, x);
1264 src_mem = replace_equiv_address (src_mem, x);
1267 active[0] = active[1] = false;
1278 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1279 next_amount = MIN (next_amount, align);
1281 amount[next] = next_amount;
1282 mode[next] = mode_from_align[next_amount];
1283 temp[next] = gen_reg_rtx (mode[next]);
1285 x = adjust_address (src_mem, mode[next], offset_ld);
1286 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1288 offset_ld += next_amount;
1289 bytes -= next_amount;
1290 active[next] = true;
1295 active[phase] = false;
1297 x = adjust_address (dst_mem, mode[phase], offset_st);
1298 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1300 offset_st += amount[phase];
1303 while (active[next]);
1310 xtensa_expand_nonlocal_goto (rtx *operands)
1312 rtx goto_handler = operands[1];
1313 rtx containing_fp = operands[3];
1315 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1316 is too big to generate in-line. */
1318 if (GET_CODE (containing_fp) != REG)
1319 containing_fp = force_reg (Pmode, containing_fp);
1321 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1322 LCT_NORMAL, VOIDmode, 2,
1323 containing_fp, Pmode,
1324 goto_handler, Pmode);
1328 static struct machine_function *
1329 xtensa_init_machine_status (void)
1331 return ggc_alloc_cleared_machine_function ();
1335 /* Shift VAL of mode MODE left by COUNT bits. */
1338 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1340 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1341 NULL_RTX, 1, OPTAB_DIRECT);
1342 return expand_simple_binop (SImode, ASHIFT, val, count,
1343 NULL_RTX, 1, OPTAB_DIRECT);
1347 /* Structure to hold the initial parameters for a compare_and_swap operation
1348 in HImode and QImode. */
1350 struct alignment_context
1352 rtx memsi; /* SI aligned memory location. */
1353 rtx shift; /* Bit offset with regard to lsb. */
1354 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1355 rtx modemaski; /* ~modemask */
1359 /* Initialize structure AC for word access to HI and QI mode memory. */
1362 init_alignment_context (struct alignment_context *ac, rtx mem)
1364 enum machine_mode mode = GET_MODE (mem);
1365 rtx byteoffset = NULL_RTX;
1366 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1369 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1372 /* Alignment is unknown. */
1375 /* Force the address into a register. */
1376 addr = force_reg (Pmode, XEXP (mem, 0));
1378 /* Align it to SImode. */
1379 align = expand_simple_binop (Pmode, AND, addr,
1380 GEN_INT (-GET_MODE_SIZE (SImode)),
1381 NULL_RTX, 1, OPTAB_DIRECT);
1383 ac->memsi = gen_rtx_MEM (SImode, align);
1384 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1385 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1386 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1388 byteoffset = expand_simple_binop (Pmode, AND, addr,
1389 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1390 NULL_RTX, 1, OPTAB_DIRECT);
1393 /* Calculate shiftcount. */
1394 if (TARGET_BIG_ENDIAN)
1396 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1398 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1399 NULL_RTX, 1, OPTAB_DIRECT);
1404 ac->shift = NULL_RTX;
1406 ac->shift = byteoffset;
1409 if (ac->shift != NULL_RTX)
1411 /* Shift is the byte count, but we need the bitcount. */
1412 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1413 GEN_INT (BITS_PER_UNIT),
1414 NULL_RTX, 1, OPTAB_DIRECT);
1415 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1416 GEN_INT (GET_MODE_MASK (mode)),
1418 NULL_RTX, 1, OPTAB_DIRECT);
1421 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1423 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1427 /* Expand an atomic compare and swap operation for HImode and QImode.
1428 MEM is the memory location, CMP the old value to compare MEM with
1429 and NEW_RTX the value to set if CMP == MEM. */
1432 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1434 enum machine_mode mode = GET_MODE (mem);
1435 struct alignment_context ac;
1436 rtx tmp, cmpv, newv, val;
1437 rtx oldval = gen_reg_rtx (SImode);
1438 rtx res = gen_reg_rtx (SImode);
1439 rtx csloop = gen_label_rtx ();
1440 rtx csend = gen_label_rtx ();
1442 init_alignment_context (&ac, mem);
1444 if (ac.shift != NULL_RTX)
1446 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1447 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1450 /* Load the surrounding word into VAL with the MEM value masked out. */
1451 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1452 ac.modemaski, NULL_RTX, 1,
1454 emit_label (csloop);
1456 /* Patch CMP and NEW_RTX into VAL at correct position. */
1457 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1458 NULL_RTX, 1, OPTAB_DIRECT));
1459 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1460 NULL_RTX, 1, OPTAB_DIRECT));
1462 /* Jump to end if we're done. */
1463 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1464 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1466 /* Check for changes outside mode. */
1467 emit_move_insn (oldval, val);
1468 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1469 val, 1, OPTAB_DIRECT);
1471 emit_move_insn (val, tmp);
1473 /* Loop internal if so. */
1474 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1478 /* Return the correct part of the bitfield. */
1479 convert_move (target,
1480 (ac.shift == NULL_RTX ? res
1481 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1482 NULL_RTX, 1, OPTAB_DIRECT)),
1487 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1488 the default expansion works fine for SImode). MEM is the memory location
1489 and VAL the value to play with. If AFTER is true then store the value
1490 MEM holds after the operation, if AFTER is false then store the value MEM
1491 holds before the operation. If TARGET is zero then discard that value, else
1492 store it to TARGET. */
1495 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1498 enum machine_mode mode = GET_MODE (mem);
1499 struct alignment_context ac;
1500 rtx csloop = gen_label_rtx ();
1502 rtx old = gen_reg_rtx (SImode);
1503 rtx new_rtx = gen_reg_rtx (SImode);
1504 rtx orig = NULL_RTX;
1506 init_alignment_context (&ac, mem);
1508 /* Prepare values before the compare-and-swap loop. */
1509 if (ac.shift != NULL_RTX)
1510 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1515 orig = gen_reg_rtx (SImode);
1516 convert_move (orig, val, 1);
1524 case MULT: /* NAND */
1526 /* val = "11..1<val>11..1" */
1527 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1528 NULL_RTX, 1, OPTAB_DIRECT);
1535 /* Load full word. Subsequent loads are performed by S32C1I. */
1536 cmp = force_reg (SImode, ac.memsi);
1538 emit_label (csloop);
1539 emit_move_insn (old, cmp);
1545 val = expand_simple_binop (SImode, code, old, orig,
1546 NULL_RTX, 1, OPTAB_DIRECT);
1547 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1548 NULL_RTX, 1, OPTAB_DIRECT);
1551 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1552 NULL_RTX, 1, OPTAB_DIRECT);
1553 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1554 new_rtx, 1, OPTAB_DIRECT);
1560 tmp = expand_simple_binop (SImode, code, old, val,
1561 new_rtx, 1, OPTAB_DIRECT);
1564 case MULT: /* NAND */
1565 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1566 NULL_RTX, 1, OPTAB_DIRECT);
1567 tmp = expand_simple_binop (SImode, AND, tmp, val,
1568 new_rtx, 1, OPTAB_DIRECT);
1576 emit_move_insn (new_rtx, tmp);
1577 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1578 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1582 tmp = (after ? new_rtx : cmp);
1583 convert_move (target,
1584 (ac.shift == NULL_RTX ? tmp
1585 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1586 NULL_RTX, 1, OPTAB_DIRECT)),
1593 xtensa_setup_frame_addresses (void)
1595 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1596 cfun->machine->accesses_prev_frame = 1;
1599 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1600 LCT_NORMAL, VOIDmode, 0);
1604 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1605 a comment showing where the end of the loop is. However, if there is a
1606 label or a branch at the end of the loop then we need to place a nop
1607 there. If the loop ends with a label we need the nop so that branches
1608 targeting that label will target the nop (and thus remain in the loop),
1609 instead of targeting the instruction after the loop (and thus exiting
1610 the loop). If the loop ends with a branch, we need the nop in case the
1611 branch is targeting a location inside the loop. When the branch
1612 executes it will cause the loop count to be decremented even if it is
1613 taken (because it is the last instruction in the loop), so we need to
1614 nop after the branch to prevent the loop count from being decremented
1615 when the branch is taken. */
1618 xtensa_emit_loop_end (rtx insn, rtx *operands)
1622 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1624 switch (GET_CODE (insn))
1631 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1637 rtx body = PATTERN (insn);
1639 if (GET_CODE (body) == JUMP_INSN)
1641 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1644 else if ((GET_CODE (body) != USE)
1645 && (GET_CODE (body) != CLOBBER))
1652 output_asm_insn ("# loop end for %0", operands);
1657 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1659 static char result[64];
1663 code = GET_CODE (operands[3]);
1666 case EQ: op = inverted ? "ne" : "eq"; break;
1667 case NE: op = inverted ? "eq" : "ne"; break;
1668 case LT: op = inverted ? "ge" : "lt"; break;
1669 case GE: op = inverted ? "lt" : "ge"; break;
1670 case LTU: op = inverted ? "geu" : "ltu"; break;
1671 case GEU: op = inverted ? "ltu" : "geu"; break;
1672 default: gcc_unreachable ();
1677 if (INTVAL (operands[1]) == 0)
1678 sprintf (result, "b%sz%s\t%%0, %%2", op,
1679 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1681 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1684 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1691 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1693 static char result[64];
1696 switch (GET_CODE (operands[3]))
1698 case EQ: op = inverted ? "bs" : "bc"; break;
1699 case NE: op = inverted ? "bc" : "bs"; break;
1700 default: gcc_unreachable ();
1705 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1706 operands[1] = GEN_INT (bitnum);
1707 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1710 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1717 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1719 static char result[64];
1723 code = GET_CODE (operands[4]);
1728 case EQ: op = inverted ? "t" : "f"; break;
1729 case NE: op = inverted ? "f" : "t"; break;
1730 default: gcc_unreachable ();
1737 case EQ: op = inverted ? "nez" : "eqz"; break;
1738 case NE: op = inverted ? "eqz" : "nez"; break;
1739 case LT: op = inverted ? "gez" : "ltz"; break;
1740 case GE: op = inverted ? "ltz" : "gez"; break;
1741 default: gcc_unreachable ();
1745 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1746 op, isfp ? ".s" : "", inverted ? 3 : 2);
1752 xtensa_emit_call (int callop, rtx *operands)
1754 static char result[64];
1755 rtx tgt = operands[callop];
1757 if (GET_CODE (tgt) == CONST_INT)
1758 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1759 else if (register_operand (tgt, VOIDmode))
1760 sprintf (result, "callx8\t%%%d", callop);
1762 sprintf (result, "call8\t%%%d", callop);
1769 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1771 /* Allow constant pool addresses. */
1772 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1773 && ! TARGET_CONST16 && constantpool_address_p (addr)
1774 && ! xtensa_tls_referenced_p (addr))
1777 while (GET_CODE (addr) == SUBREG)
1778 addr = SUBREG_REG (addr);
1780 /* Allow base registers. */
1781 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1784 /* Check for "register + offset" addressing. */
1785 if (GET_CODE (addr) == PLUS)
1787 rtx xplus0 = XEXP (addr, 0);
1788 rtx xplus1 = XEXP (addr, 1);
1789 enum rtx_code code0;
1790 enum rtx_code code1;
1792 while (GET_CODE (xplus0) == SUBREG)
1793 xplus0 = SUBREG_REG (xplus0);
1794 code0 = GET_CODE (xplus0);
1796 while (GET_CODE (xplus1) == SUBREG)
1797 xplus1 = SUBREG_REG (xplus1);
1798 code1 = GET_CODE (xplus1);
1800 /* Swap operands if necessary so the register is first. */
1801 if (code0 != REG && code1 == REG)
1803 xplus0 = XEXP (addr, 1);
1804 xplus1 = XEXP (addr, 0);
1805 code0 = GET_CODE (xplus0);
1806 code1 = GET_CODE (xplus1);
1809 if (code0 == REG && BASE_REG_P (xplus0, strict)
1810 && code1 == CONST_INT
1811 && xtensa_mem_offset (INTVAL (xplus1), mode))
1819 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1821 static GTY(()) rtx xtensa_tls_module_base_symbol;
1824 xtensa_tls_module_base (void)
1826 if (! xtensa_tls_module_base_symbol)
1828 xtensa_tls_module_base_symbol =
1829 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1830 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1831 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1834 return xtensa_tls_module_base_symbol;
1839 xtensa_call_tls_desc (rtx sym, rtx *retp)
1841 rtx fn, arg, a10, call_insn, insns;
1844 fn = gen_reg_rtx (Pmode);
1845 arg = gen_reg_rtx (Pmode);
1846 a10 = gen_rtx_REG (Pmode, 10);
1848 emit_insn (gen_tls_func (fn, sym));
1849 emit_insn (gen_tls_arg (arg, sym));
1850 emit_move_insn (a10, arg);
1851 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1852 CALL_INSN_FUNCTION_USAGE (call_insn)
1853 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, a10),
1854 CALL_INSN_FUNCTION_USAGE (call_insn));
1855 insns = get_insns ();
1864 xtensa_legitimize_tls_address (rtx x)
1866 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1867 rtx dest, tp, ret, modbase, base, addend, insns;
1869 dest = gen_reg_rtx (Pmode);
1872 case TLS_MODEL_GLOBAL_DYNAMIC:
1873 insns = xtensa_call_tls_desc (x, &ret);
1874 emit_libcall_block (insns, dest, ret, x);
1877 case TLS_MODEL_LOCAL_DYNAMIC:
1878 base = gen_reg_rtx (Pmode);
1879 modbase = xtensa_tls_module_base ();
1880 insns = xtensa_call_tls_desc (modbase, &ret);
1881 emit_libcall_block (insns, base, ret, modbase);
1882 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1883 emit_insn (gen_addsi3 (dest, base, addend));
1886 case TLS_MODEL_INITIAL_EXEC:
1887 case TLS_MODEL_LOCAL_EXEC:
1888 tp = gen_reg_rtx (SImode);
1889 emit_insn (gen_load_tp (tp));
1890 addend = force_reg (SImode, gen_sym_TPOFF (x));
1891 emit_insn (gen_addsi3 (dest, tp, addend));
1903 xtensa_legitimize_address (rtx x,
1904 rtx oldx ATTRIBUTE_UNUSED,
1905 enum machine_mode mode)
1907 if (xtensa_tls_symbol_p (x))
1908 return xtensa_legitimize_tls_address (x);
1910 if (GET_CODE (x) == PLUS)
1912 rtx plus0 = XEXP (x, 0);
1913 rtx plus1 = XEXP (x, 1);
1915 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1917 plus0 = XEXP (x, 1);
1918 plus1 = XEXP (x, 0);
1921 /* Try to split up the offset to use an ADDMI instruction. */
1922 if (GET_CODE (plus0) == REG
1923 && GET_CODE (plus1) == CONST_INT
1924 && !xtensa_mem_offset (INTVAL (plus1), mode)
1925 && !xtensa_simm8 (INTVAL (plus1))
1926 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1927 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1929 rtx temp = gen_reg_rtx (Pmode);
1930 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1931 emit_insn (gen_rtx_SET (Pmode, temp,
1932 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1933 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1941 /* Helper for xtensa_tls_referenced_p. */
1944 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1946 if (GET_CODE (*x) == SYMBOL_REF)
1947 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1949 /* Ignore TLS references that have already been legitimized. */
1950 if (GET_CODE (*x) == UNSPEC)
1952 switch (XINT (*x, 1))
1956 case UNSPEC_TLS_FUNC:
1957 case UNSPEC_TLS_ARG:
1958 case UNSPEC_TLS_CALL:
1969 /* Return TRUE if X contains any TLS symbol references. */
1972 xtensa_tls_referenced_p (rtx x)
1974 if (! TARGET_HAVE_TLS)
1977 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
1981 /* Return the debugger register number to use for 'regno'. */
1984 xtensa_dbx_register_number (int regno)
1988 if (GP_REG_P (regno))
1990 regno -= GP_REG_FIRST;
1993 else if (BR_REG_P (regno))
1995 regno -= BR_REG_FIRST;
1998 else if (FP_REG_P (regno))
2000 regno -= FP_REG_FIRST;
2003 else if (ACC_REG_P (regno))
2005 first = 0x200; /* Start of Xtensa special registers. */
2006 regno = 16; /* ACCLO is special register 16. */
2009 /* When optimizing, we sometimes get asked about pseudo-registers
2010 that don't represent hard registers. Return 0 for these. */
2014 return first + regno;
2018 /* Argument support functions. */
2020 /* Initialize CUMULATIVE_ARGS for a function. */
2023 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2026 cum->incoming = incoming;
2030 /* Advance the argument to the next argument position. */
2033 xtensa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2034 const_tree type, bool named ATTRIBUTE_UNUSED)
2039 arg_words = &cum->arg_words;
2040 max = MAX_ARGS_IN_REGISTERS;
2042 words = (((mode != BLKmode)
2043 ? (int) GET_MODE_SIZE (mode)
2044 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2046 if (*arg_words < max
2047 && (targetm.calls.must_pass_in_stack (mode, type)
2048 || *arg_words + words > max))
2051 *arg_words += words;
2055 /* Return an RTL expression containing the register for the given mode,
2056 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2057 if this is an incoming argument to the current function. */
2060 xtensa_function_arg_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2061 const_tree type, bool incoming_p)
2063 int regbase, words, max;
2067 arg_words = &cum->arg_words;
2068 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2069 max = MAX_ARGS_IN_REGISTERS;
2071 words = (((mode != BLKmode)
2072 ? (int) GET_MODE_SIZE (mode)
2073 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2075 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2077 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2078 *arg_words = (*arg_words + align - 1) & -align;
2081 if (*arg_words + words > max)
2084 regno = regbase + *arg_words;
2086 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2087 cfun->machine->need_a7_copy = true;
2089 return gen_rtx_REG (mode, regno);
2092 /* Implement TARGET_FUNCTION_ARG. */
2095 xtensa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2096 const_tree type, bool named ATTRIBUTE_UNUSED)
2098 return xtensa_function_arg_1 (cum, mode, type, false);
2101 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2104 xtensa_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2105 const_tree type, bool named ATTRIBUTE_UNUSED)
2107 return xtensa_function_arg_1 (cum, mode, type, true);
2111 xtensa_function_arg_boundary (enum machine_mode mode, const_tree type)
2113 unsigned int alignment;
2115 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2116 if (alignment < PARM_BOUNDARY)
2117 alignment = PARM_BOUNDARY;
2118 if (alignment > STACK_BOUNDARY)
2119 alignment = STACK_BOUNDARY;
2125 xtensa_return_in_msb (const_tree valtype)
2127 return (TARGET_BIG_ENDIAN
2128 && AGGREGATE_TYPE_P (valtype)
2129 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2134 xtensa_option_override (void)
2137 enum machine_mode mode;
2139 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2140 error ("boolean registers required for the floating-point option");
2142 /* Set up array giving whether a given register can hold a given mode. */
2143 for (mode = VOIDmode;
2144 mode != MAX_MACHINE_MODE;
2145 mode = (enum machine_mode) ((int) mode + 1))
2147 int size = GET_MODE_SIZE (mode);
2148 enum mode_class mclass = GET_MODE_CLASS (mode);
2150 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2154 if (ACC_REG_P (regno))
2155 temp = (TARGET_MAC16
2156 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2157 else if (GP_REG_P (regno))
2158 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2159 else if (FP_REG_P (regno))
2160 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2161 else if (BR_REG_P (regno))
2162 temp = (TARGET_BOOLEANS && (mode == CCmode));
2166 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2170 init_machine_status = xtensa_init_machine_status;
2172 /* Check PIC settings. PIC is only supported when using L32R
2173 instructions, and some targets need to always use PIC. */
2174 if (flag_pic && TARGET_CONST16)
2175 error ("-f%s is not supported with CONST16 instructions",
2176 (flag_pic > 1 ? "PIC" : "pic"));
2177 else if (TARGET_FORCE_NO_PIC)
2179 else if (XTENSA_ALWAYS_PIC)
2182 error ("PIC is required but not supported with CONST16 instructions");
2185 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2188 if (flag_pic && !flag_pie)
2191 /* Hot/cold partitioning does not work on this architecture, because of
2192 constant pools (the load instruction cannot necessarily reach that far).
2193 Therefore disable it on this architecture. */
2194 if (flag_reorder_blocks_and_partition)
2196 flag_reorder_blocks_and_partition = 0;
2197 flag_reorder_blocks = 1;
2201 /* A C compound statement to output to stdio stream STREAM the
2202 assembler syntax for an instruction operand X. X is an RTL
2205 CODE is a value that can be used to specify one of several ways
2206 of printing the operand. It is used when identical operands
2207 must be printed differently depending on the context. CODE
2208 comes from the '%' specification that was used to request
2209 printing of the operand. If the specification was just '%DIGIT'
2210 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2211 is the ASCII code for LTR.
2213 If X is a register, this macro should print the register's name.
2214 The names can be found in an array 'reg_names' whose type is
2215 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2217 When the machine description has a specification '%PUNCT' (a '%'
2218 followed by a punctuation character), this macro is called with
2219 a null pointer for X and the punctuation character for CODE.
2221 'a', 'c', 'l', and 'n' are reserved.
2223 The Xtensa specific codes are:
2225 'd' CONST_INT, print as signed decimal
2226 'x' CONST_INT, print as signed hexadecimal
2227 'K' CONST_INT, print number of bits in mask for EXTUI
2228 'R' CONST_INT, print (X & 0x1f)
2229 'L' CONST_INT, print ((32 - X) & 0x1f)
2230 'D' REG, print second register of double-word register operand
2231 'N' MEM, print address of next word following a memory operand
2232 'v' MEM, if memory reference is volatile, output a MEMW before it
2233 't' any constant, add "@h" suffix for top 16 bits
2234 'b' any constant, add "@l" suffix for bottom 16 bits
2238 printx (FILE *file, signed int val)
2240 /* Print a hexadecimal value in a nice way. */
2241 if ((val > -0xa) && (val < 0xa))
2242 fprintf (file, "%d", val);
2244 fprintf (file, "-0x%x", -val);
2246 fprintf (file, "0x%x", val);
2251 print_operand (FILE *file, rtx x, int letter)
2254 error ("PRINT_OPERAND null pointer");
2259 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2260 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2262 output_operand_lossage ("invalid %%D value");
2266 if (GET_CODE (x) == MEM)
2268 /* For a volatile memory reference, emit a MEMW before the
2270 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2271 fprintf (file, "memw\n\t");
2274 output_operand_lossage ("invalid %%v value");
2278 if (GET_CODE (x) == MEM
2279 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2281 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2282 output_address (XEXP (x, 0));
2285 output_operand_lossage ("invalid %%N value");
2289 if (GET_CODE (x) == CONST_INT)
2292 unsigned val = INTVAL (x);
2298 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2299 fatal_insn ("invalid mask", x);
2301 fprintf (file, "%d", num_bits);
2304 output_operand_lossage ("invalid %%K value");
2308 if (GET_CODE (x) == CONST_INT)
2309 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2311 output_operand_lossage ("invalid %%L value");
2315 if (GET_CODE (x) == CONST_INT)
2316 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2318 output_operand_lossage ("invalid %%R value");
2322 if (GET_CODE (x) == CONST_INT)
2323 printx (file, INTVAL (x));
2325 output_operand_lossage ("invalid %%x value");
2329 if (GET_CODE (x) == CONST_INT)
2330 fprintf (file, "%ld", INTVAL (x));
2332 output_operand_lossage ("invalid %%d value");
2337 if (GET_CODE (x) == CONST_INT)
2339 printx (file, INTVAL (x));
2340 fputs (letter == 't' ? "@h" : "@l", file);
2342 else if (GET_CODE (x) == CONST_DOUBLE)
2345 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2346 if (GET_MODE (x) == SFmode)
2349 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2350 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2353 output_operand_lossage ("invalid %%t/%%b value");
2355 else if (GET_CODE (x) == CONST)
2357 /* X must be a symbolic constant on ELF. Write an expression
2358 suitable for 'const16' that sets the high or low 16 bits. */
2359 if (GET_CODE (XEXP (x, 0)) != PLUS
2360 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2361 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2362 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2363 output_operand_lossage ("invalid %%t/%%b value");
2364 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2365 fputs (letter == 't' ? "@h" : "@l", file);
2366 /* There must be a non-alphanumeric character between 'h' or 'l'
2367 and the number. The '-' is added by print_operand() already. */
2368 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2370 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2374 output_addr_const (file, x);
2375 fputs (letter == 't' ? "@h" : "@l", file);
2380 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2381 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2382 else if (GET_CODE (x) == MEM)
2383 output_address (XEXP (x, 0));
2384 else if (GET_CODE (x) == CONST_INT)
2385 fprintf (file, "%ld", INTVAL (x));
2387 output_addr_const (file, x);
2392 /* A C compound statement to output to stdio stream STREAM the
2393 assembler syntax for an instruction operand that is a memory
2394 reference whose address is ADDR. ADDR is an RTL expression. */
2397 print_operand_address (FILE *file, rtx addr)
2400 error ("PRINT_OPERAND_ADDRESS, null pointer");
2402 switch (GET_CODE (addr))
2405 fatal_insn ("invalid address", addr);
2409 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2415 rtx offset = (rtx)0;
2416 rtx arg0 = XEXP (addr, 0);
2417 rtx arg1 = XEXP (addr, 1);
2419 if (GET_CODE (arg0) == REG)
2424 else if (GET_CODE (arg1) == REG)
2430 fatal_insn ("no register in address", addr);
2432 if (CONSTANT_P (offset))
2434 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2435 output_addr_const (file, offset);
2438 fatal_insn ("address offset not a constant", addr);
2446 output_addr_const (file, addr);
2451 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2454 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2456 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2458 switch (XINT (x, 1))
2461 output_addr_const (fp, XVECEXP (x, 0, 0));
2462 fputs ("@TPOFF", fp);
2465 output_addr_const (fp, XVECEXP (x, 0, 0));
2466 fputs ("@DTPOFF", fp);
2471 output_addr_const (fp, XVECEXP (x, 0, 0));
2485 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2492 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2494 switch (GET_MODE_CLASS (mode))
2497 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2499 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2503 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2504 if (HOST_BITS_PER_LONG > 32)
2505 value_long[0] &= 0xffffffff;
2506 fprintf (file, "0x%08lx\n", value_long[0]);
2510 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2511 if (HOST_BITS_PER_LONG > 32)
2513 value_long[0] &= 0xffffffff;
2514 value_long[1] &= 0xffffffff;
2516 fprintf (file, "0x%08lx, 0x%08lx\n",
2517 value_long[0], value_long[1]);
2527 case MODE_PARTIAL_INT:
2528 size = GET_MODE_SIZE (mode);
2532 output_addr_const (file, x);
2537 split_double (x, &first, &second);
2538 output_addr_const (file, first);
2540 output_addr_const (file, second);
2555 /* Return the bytes needed to compute the frame pointer from the current
2558 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2559 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2562 compute_frame_size (int size)
2564 /* Add space for the incoming static chain value. */
2565 if (cfun->static_chain_decl != NULL)
2566 size += (1 * UNITS_PER_WORD);
2568 xtensa_current_frame_size =
2569 XTENSA_STACK_ALIGN (size
2570 + crtl->outgoing_args_size
2571 + (WINDOW_SIZE * UNITS_PER_WORD));
2572 return xtensa_current_frame_size;
2577 xtensa_frame_pointer_required (void)
2579 /* The code to expand builtin_frame_addr and builtin_return_addr
2580 currently uses the hard_frame_pointer instead of frame_pointer.
2581 This seems wrong but maybe it's necessary for other architectures.
2582 This function is derived from the i386 code. */
2584 if (cfun->machine->accesses_prev_frame)
2591 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2592 and the total number of words must be a multiple of 128 bits. */
2593 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2596 xtensa_expand_prologue (void)
2598 HOST_WIDE_INT total_size;
2602 total_size = compute_frame_size (get_frame_size ());
2603 size_rtx = GEN_INT (total_size);
2605 if (total_size < (1 << (12+3)))
2606 insn = emit_insn (gen_entry (size_rtx));
2609 /* Use a8 as a temporary since a0-a7 may be live. */
2610 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2611 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2612 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2613 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2614 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2617 if (frame_pointer_needed)
2619 if (cfun->machine->set_frame_ptr_insn)
2623 push_topmost_sequence ();
2624 first = get_insns ();
2625 pop_topmost_sequence ();
2627 /* For all instructions prior to set_frame_ptr_insn, replace
2628 hard_frame_pointer references with stack_pointer. */
2630 insn != cfun->machine->set_frame_ptr_insn;
2631 insn = NEXT_INSN (insn))
2635 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2636 hard_frame_pointer_rtx,
2638 df_insn_rescan (insn);
2643 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2644 stack_pointer_rtx));
2647 /* Create a note to describe the CFA. Because this is only used to set
2648 DW_AT_frame_base for debug info, don't bother tracking changes through
2649 each instruction in the prologue. It just takes up space. */
2650 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2651 ? hard_frame_pointer_rtx
2652 : stack_pointer_rtx),
2653 plus_constant (stack_pointer_rtx, -total_size));
2654 RTX_FRAME_RELATED_P (insn) = 1;
2655 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2659 /* Clear variables at function end. */
2662 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2663 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2665 xtensa_current_frame_size = 0;
2670 xtensa_return_addr (int count, rtx frame)
2672 rtx result, retaddr, curaddr, label;
2675 retaddr = gen_rtx_REG (Pmode, A0_REG);
2678 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2679 addr = memory_address (Pmode, addr);
2680 retaddr = gen_reg_rtx (Pmode);
2681 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2684 /* The 2 most-significant bits of the return address on Xtensa hold
2685 the register window size. To get the real return address, these
2686 bits must be replaced with the high bits from some address in the
2689 /* Get the 2 high bits of a local label in the code. */
2690 curaddr = gen_reg_rtx (Pmode);
2691 label = gen_label_rtx ();
2693 LABEL_PRESERVE_P (label) = 1;
2694 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2695 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2696 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2698 /* Clear the 2 high bits of the return address. */
2699 result = gen_reg_rtx (Pmode);
2700 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2701 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2703 /* Combine them to get the result. */
2704 emit_insn (gen_iorsi3 (result, result, curaddr));
2709 /* Create the va_list data type.
2711 This structure is set up by __builtin_saveregs. The __va_reg field
2712 points to a stack-allocated region holding the contents of the
2713 incoming argument registers. The __va_ndx field is an index
2714 initialized to the position of the first unnamed (variable)
2715 argument. This same index is also used to address the arguments
2716 passed in memory. Thus, the __va_stk field is initialized to point
2717 to the position of the first argument in memory offset to account
2718 for the arguments passed in registers and to account for the size
2719 of the argument registers not being 16-byte aligned. E.G., there
2720 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2721 for the first stack argument to have the maximal alignment of 16
2722 bytes, so we offset the __va_stk address by 32 bytes so that
2723 __va_stk[32] references the first argument on the stack. */
2726 xtensa_build_builtin_va_list (void)
2728 tree f_stk, f_reg, f_ndx, record, type_decl;
2730 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2731 type_decl = build_decl (BUILTINS_LOCATION,
2732 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2734 f_stk = build_decl (BUILTINS_LOCATION,
2735 FIELD_DECL, get_identifier ("__va_stk"),
2737 f_reg = build_decl (BUILTINS_LOCATION,
2738 FIELD_DECL, get_identifier ("__va_reg"),
2740 f_ndx = build_decl (BUILTINS_LOCATION,
2741 FIELD_DECL, get_identifier ("__va_ndx"),
2744 DECL_FIELD_CONTEXT (f_stk) = record;
2745 DECL_FIELD_CONTEXT (f_reg) = record;
2746 DECL_FIELD_CONTEXT (f_ndx) = record;
2748 TYPE_STUB_DECL (record) = type_decl;
2749 TYPE_NAME (record) = type_decl;
2750 TYPE_FIELDS (record) = f_stk;
2751 DECL_CHAIN (f_stk) = f_reg;
2752 DECL_CHAIN (f_reg) = f_ndx;
2754 layout_type (record);
2759 /* Save the incoming argument registers on the stack. Returns the
2760 address of the saved registers. */
2763 xtensa_builtin_saveregs (void)
2766 int arg_words = crtl->args.info.arg_words;
2767 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2772 /* Allocate the general-purpose register space. */
2773 gp_regs = assign_stack_local
2774 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2775 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2777 /* Now store the incoming registers. */
2778 cfun->machine->need_a7_copy = true;
2779 cfun->machine->vararg_a7 = true;
2780 move_block_from_reg (GP_ARG_FIRST + arg_words,
2781 adjust_address (gp_regs, BLKmode,
2782 arg_words * UNITS_PER_WORD),
2784 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2785 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2787 return XEXP (gp_regs, 0);
2791 /* Implement `va_start' for varargs and stdarg. We look at the
2792 current function to fill in an initial va_list. */
2795 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2803 arg_words = crtl->args.info.arg_words;
2805 f_stk = TYPE_FIELDS (va_list_type_node);
2806 f_reg = DECL_CHAIN (f_stk);
2807 f_ndx = DECL_CHAIN (f_reg);
2809 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2810 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2812 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2815 /* Call __builtin_saveregs; save the result in __va_reg */
2816 u = make_tree (sizetype, expand_builtin_saveregs ());
2817 u = fold_convert (ptr_type_node, u);
2818 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2819 TREE_SIDE_EFFECTS (t) = 1;
2820 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2822 /* Set the __va_stk member to ($arg_ptr - 32). */
2823 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2824 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2825 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2826 TREE_SIDE_EFFECTS (t) = 1;
2827 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2829 /* Set the __va_ndx member. If the first variable argument is on
2830 the stack, adjust __va_ndx by 2 words to account for the extra
2831 alignment offset for __va_stk. */
2832 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2834 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2835 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2836 TREE_SIDE_EFFECTS (t) = 1;
2837 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2841 /* Implement `va_arg'. */
2844 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2845 gimple_seq *post_p ATTRIBUTE_UNUSED)
2850 tree type_size, array, orig_ndx, addr, size, va_size, t;
2851 tree lab_false, lab_over, lab_false2;
2854 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2856 type = build_pointer_type (type);
2858 /* Handle complex values as separate real and imaginary parts. */
2859 if (TREE_CODE (type) == COMPLEX_TYPE)
2861 tree real_part, imag_part;
2863 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2865 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2867 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2870 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2872 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2875 f_stk = TYPE_FIELDS (va_list_type_node);
2876 f_reg = DECL_CHAIN (f_stk);
2877 f_ndx = DECL_CHAIN (f_reg);
2879 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2881 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2883 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2886 type_size = size_in_bytes (type);
2887 va_size = round_up (type_size, UNITS_PER_WORD);
2888 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2891 /* First align __va_ndx if necessary for this arg:
2893 orig_ndx = (AP).__va_ndx;
2894 if (__alignof__ (TYPE) > 4 )
2895 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2896 & -__alignof__ (TYPE)); */
2898 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2900 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2902 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2904 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2905 build_int_cst (integer_type_node, align - 1));
2906 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2907 build_int_cst (integer_type_node, -align));
2908 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2912 /* Increment __va_ndx to point past the argument:
2914 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2916 t = fold_convert (integer_type_node, va_size);
2917 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2918 gimplify_assign (unshare_expr (ndx), t, pre_p);
2921 /* Check if the argument is in registers:
2923 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2924 && !must_pass_in_stack (type))
2925 __array = (AP).__va_reg; */
2927 array = create_tmp_var (ptr_type_node, NULL);
2930 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2932 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2933 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2935 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2936 build_int_cst (integer_type_node,
2937 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2938 t = build3 (COND_EXPR, void_type_node, t,
2939 build1 (GOTO_EXPR, void_type_node, lab_false),
2941 gimplify_and_add (t, pre_p);
2943 gimplify_assign (unshare_expr (array), reg, pre_p);
2945 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2946 gimplify_and_add (t, pre_p);
2948 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2949 gimplify_and_add (t, pre_p);
2953 /* ...otherwise, the argument is on the stack (never split between
2954 registers and the stack -- change __va_ndx if necessary):
2958 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2959 (AP).__va_ndx = 32 + __va_size (TYPE);
2960 __array = (AP).__va_stk;
2963 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
2965 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
2966 build_int_cst (integer_type_node,
2967 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2968 t = build3 (COND_EXPR, void_type_node, t,
2969 build1 (GOTO_EXPR, void_type_node, lab_false2),
2971 gimplify_and_add (t, pre_p);
2973 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
2974 t = fold_convert (integer_type_node, t);
2975 gimplify_assign (unshare_expr (ndx), t, pre_p);
2977 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2978 gimplify_and_add (t, pre_p);
2980 gimplify_assign (array, stk, pre_p);
2984 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2985 gimplify_and_add (t, pre_p);
2989 /* Given the base array pointer (__array) and index to the subsequent
2990 argument (__va_ndx), find the address:
2992 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2996 The results are endian-dependent because values smaller than one word
2997 are aligned differently. */
3000 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
3002 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
3003 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
3004 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
3005 unshare_expr (type_size));
3009 size = unshare_expr (va_size);
3011 t = fold_convert (sizetype, unshare_expr (ndx));
3012 t = build2 (MINUS_EXPR, sizetype, t, size);
3013 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
3015 addr = fold_convert (build_pointer_type (type), addr);
3017 addr = build_va_arg_indirect_ref (addr);
3018 return build_va_arg_indirect_ref (addr);
3026 XTENSA_BUILTIN_UMULSIDI3,
3027 XTENSA_BUILTIN_THREAD_POINTER,
3028 XTENSA_BUILTIN_SET_THREAD_POINTER,
3034 xtensa_init_builtins (void)
3038 ftype = build_function_type_list (unsigned_intDI_type_node,
3039 unsigned_intSI_type_node,
3040 unsigned_intSI_type_node, NULL_TREE);
3042 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3043 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3044 "__umulsidi3", NULL_TREE);
3045 TREE_NOTHROW (decl) = 1;
3046 TREE_READONLY (decl) = 1;
3048 if (TARGET_THREADPTR)
3050 ftype = build_function_type (ptr_type_node, void_list_node);
3051 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
3052 XTENSA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
3054 TREE_READONLY (decl) = 1;
3055 TREE_NOTHROW (decl) = 1;
3057 ftype = build_function_type_list (void_type_node, ptr_type_node,
3059 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
3060 XTENSA_BUILTIN_SET_THREAD_POINTER,
3061 BUILT_IN_MD, NULL, NULL_TREE);
3062 TREE_NOTHROW (decl) = 1;
3068 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3069 bool ignore ATTRIBUTE_UNUSED)
3071 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3076 case XTENSA_BUILTIN_UMULSIDI3:
3079 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3080 || TARGET_MUL32_HIGH)
3081 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3082 fold_convert (unsigned_intDI_type_node, arg0),
3083 fold_convert (unsigned_intDI_type_node, arg1));
3086 case XTENSA_BUILTIN_THREAD_POINTER:
3087 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3091 internal_error ("bad builtin code");
3100 xtensa_expand_builtin (tree exp, rtx target,
3101 rtx subtarget ATTRIBUTE_UNUSED,
3102 enum machine_mode mode ATTRIBUTE_UNUSED,
3105 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3106 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3111 case XTENSA_BUILTIN_UMULSIDI3:
3112 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3113 __umulsidi3 function when the Xtensa configuration can directly
3114 implement it. If not, just call the function. */
3115 return expand_call (exp, target, ignore);
3117 case XTENSA_BUILTIN_THREAD_POINTER:
3118 if (!target || !register_operand (target, Pmode))
3119 target = gen_reg_rtx (Pmode);
3120 emit_insn (gen_load_tp (target));
3123 case XTENSA_BUILTIN_SET_THREAD_POINTER:
3124 arg = expand_normal (CALL_EXPR_ARG (exp, 0));
3125 if (!register_operand (arg, Pmode))
3126 arg = copy_to_mode_reg (Pmode, arg);
3127 emit_insn (gen_set_tp (arg));
3131 internal_error ("bad builtin code");
3138 xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
3140 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
3143 /* Don't use the stack pointer or hard frame pointer for reloads!
3144 The hard frame pointer would normally be OK except that it may
3145 briefly hold an incoming argument in the prologue, and reload
3146 won't know that it is live because the hard frame pointer is
3147 treated specially. */
3149 if (rclass == AR_REGS || rclass == GR_REGS)
3157 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3158 enum machine_mode mode, secondary_reload_info *sri)
3162 if (in_p && constantpool_mem_p (x))
3164 if (rclass == FP_REGS)
3168 sri->icode = CODE_FOR_reloadqi_literal;
3169 else if (mode == HImode)
3170 sri->icode = CODE_FOR_reloadhi_literal;
3173 regno = xt_true_regnum (x);
3174 if (ACC_REG_P (regno))
3175 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3176 if (rclass == ACC_REG)
3177 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3184 order_regs_for_local_alloc (void)
3186 if (!leaf_function_p ())
3188 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3189 FIRST_PSEUDO_REGISTER * sizeof (int));
3193 int i, num_arg_regs;
3196 /* Use the AR registers in increasing order (skipping a0 and a1)
3197 but save the incoming argument registers for a last resort. */
3198 num_arg_regs = crtl->args.info.arg_words;
3199 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3200 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3201 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3202 reg_alloc_order[nxt++] = i + num_arg_regs;
3203 for (i = 0; i < num_arg_regs; i++)
3204 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3206 /* List the coprocessor registers in order. */
3207 for (i = 0; i < BR_REG_NUM; i++)
3208 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3210 /* List the FP registers in order for now. */
3211 for (i = 0; i < 16; i++)
3212 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3214 /* GCC requires that we list *all* the registers.... */
3215 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3216 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3217 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3218 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3220 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3225 /* Some Xtensa targets support multiple bss sections. If the section
3226 name ends with ".bss", add SECTION_BSS to the flags. */
3229 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3231 unsigned int flags = default_section_type_flags (decl, name, reloc);
3234 suffix = strrchr (name, '.');
3235 if (suffix && strcmp (suffix, ".bss") == 0)
3237 if (!decl || (TREE_CODE (decl) == VAR_DECL
3238 && DECL_INITIAL (decl) == NULL_TREE))
3239 flags |= SECTION_BSS; /* @nobits */
3241 warning (0, "only uninitialized variables can be placed in a "
3249 /* The literal pool stays with the function. */
3252 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3253 rtx x ATTRIBUTE_UNUSED,
3254 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3256 return function_section (current_function_decl);
3260 /* Compute a (partial) cost for rtx X. Return true if the complete
3261 cost has been computed, and false if subexpressions should be
3262 scanned. In either case, *TOTAL contains the cost result. */
3265 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total,
3266 bool speed ATTRIBUTE_UNUSED)
3274 if (xtensa_simm12b (INTVAL (x)))
3281 if (xtensa_simm8 (INTVAL (x))
3282 || xtensa_simm8x256 (INTVAL (x)))
3289 if (xtensa_mask_immediate (INTVAL (x)))
3296 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3307 /* No way to tell if X is the 2nd operand so be conservative. */
3310 if (xtensa_simm12b (INTVAL (x)))
3312 else if (TARGET_CONST16)
3313 *total = COSTS_N_INSNS (2);
3322 *total = COSTS_N_INSNS (2);
3329 *total = COSTS_N_INSNS (4);
3337 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3339 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3340 *total = COSTS_N_INSNS (num_words);
3342 *total = COSTS_N_INSNS (2*num_words);
3348 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3352 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3356 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3362 if (GET_MODE (x) == DImode)
3363 *total = COSTS_N_INSNS (2);
3365 *total = COSTS_N_INSNS (1);
3371 if (GET_MODE (x) == DImode)
3372 *total = COSTS_N_INSNS (50);
3374 *total = COSTS_N_INSNS (1);
3379 enum machine_mode xmode = GET_MODE (x);
3380 if (xmode == SFmode)
3381 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3382 else if (xmode == DFmode)
3383 *total = COSTS_N_INSNS (50);
3385 *total = COSTS_N_INSNS (4);
3392 enum machine_mode xmode = GET_MODE (x);
3393 if (xmode == SFmode)
3394 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3395 else if (xmode == DFmode || xmode == DImode)
3396 *total = COSTS_N_INSNS (50);
3398 *total = COSTS_N_INSNS (1);
3403 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3408 enum machine_mode xmode = GET_MODE (x);
3409 if (xmode == SFmode)
3410 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3411 else if (xmode == DFmode)
3412 *total = COSTS_N_INSNS (50);
3413 else if (xmode == DImode)
3414 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3415 else if (TARGET_MUL32)
3416 *total = COSTS_N_INSNS (4);
3417 else if (TARGET_MAC16)
3418 *total = COSTS_N_INSNS (16);
3419 else if (TARGET_MUL16)
3420 *total = COSTS_N_INSNS (12);
3422 *total = COSTS_N_INSNS (50);
3429 enum machine_mode xmode = GET_MODE (x);
3430 if (xmode == SFmode)
3432 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3435 else if (xmode == DFmode)
3437 *total = COSTS_N_INSNS (50);
3446 enum machine_mode xmode = GET_MODE (x);
3447 if (xmode == DImode)
3448 *total = COSTS_N_INSNS (50);
3449 else if (TARGET_DIV32)
3450 *total = COSTS_N_INSNS (32);
3452 *total = COSTS_N_INSNS (50);
3457 if (GET_MODE (x) == SFmode)
3458 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3460 *total = COSTS_N_INSNS (50);
3467 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3472 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3477 *total = COSTS_N_INSNS (1);
3485 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3488 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3490 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3491 > 4 * UNITS_PER_WORD);
3494 /* Worker function for TARGET_FUNCTION_VALUE. */
3497 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3500 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3501 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3502 ? SImode : TYPE_MODE (valtype),
3503 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3506 /* Worker function for TARGET_LIBCALL_VALUE. */
3509 xtensa_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
3511 return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT
3512 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3513 ? SImode : mode, GP_RETURN);
3516 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3519 xtensa_function_value_regno_p (const unsigned int regno)
3521 return (regno == GP_RETURN);
3524 /* The static chain is passed in memory. Provide rtx giving 'mem'
3525 expressions that denote where they are stored. */
3528 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3530 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3531 return gen_frame_mem (Pmode, plus_constant (base, -5 * UNITS_PER_WORD));
3535 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3536 instruction with a minimal stack frame in order to get some free
3537 registers. Once the actual call target is known, the proper stack frame
3538 size is extracted from the ENTRY instruction at the target and the
3539 current frame is adjusted to match. The trampoline then transfers
3540 control to the instruction following the ENTRY at the target. Note:
3541 this assumes that the target begins with an ENTRY instruction. */
3544 xtensa_asm_trampoline_template (FILE *stream)
3546 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3548 fprintf (stream, "\t.begin no-transform\n");
3549 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3553 /* Save the return address. */
3554 fprintf (stream, "\tmov\ta10, a0\n");
3556 /* Use a CALL0 instruction to skip past the constants and in the
3557 process get the PC into A0. This allows PC-relative access to
3558 the constants without relying on L32R. */
3559 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3562 fprintf (stream, "\tj\t.Lskipconsts\n");
3564 fprintf (stream, "\t.align\t4\n");
3565 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3566 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3567 fprintf (stream, ".Lskipconsts:\n");
3569 /* Load the static chain and function address from the trampoline. */
3572 fprintf (stream, "\taddi\ta0, a0, 3\n");
3573 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3574 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3578 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3579 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3582 /* Store the static chain. */
3583 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3585 /* Set the proper stack pointer value. */
3586 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3587 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3588 TARGET_BIG_ENDIAN ? 8 : 12);
3589 fprintf (stream, "\tslli\ta9, a9, 3\n");
3590 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3591 fprintf (stream, "\tsub\ta9, sp, a9\n");
3592 fprintf (stream, "\tmovsp\tsp, a9\n");
3595 /* Restore the return address. */
3596 fprintf (stream, "\tmov\ta0, a10\n");
3598 /* Jump to the instruction following the ENTRY. */
3599 fprintf (stream, "\taddi\ta8, a8, 3\n");
3600 fprintf (stream, "\tjx\ta8\n");
3602 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3604 fprintf (stream, "\t.byte\t0\n");
3606 fprintf (stream, "\tnop\n");
3608 fprintf (stream, "\t.end no-transform\n");
3612 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3614 rtx func = XEXP (DECL_RTL (fndecl), 0);
3615 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3616 int chain_off = use_call0 ? 12 : 8;
3617 int func_off = use_call0 ? 16 : 12;
3619 emit_block_move (m_tramp, assemble_trampoline_template (),
3620 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3622 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3623 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3624 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3625 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3629 #include "gt-xtensa.h"