1 ;;- Machine description for GNU compiler, Vax Version
2 ;; Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 ;;- Instruction patterns. When multiple patterns apply,
22 ;;- the first one in the file is chosen.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
27 ;;- updates for most instructions.
29 ;; We don't want to allow a constant operand for test insns because
30 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
31 ;; be folded while optimizing anyway.
35 (match_operand:SI 0 "nonimmediate_operand" "g"))]
41 (match_operand:HI 0 "nonimmediate_operand" "g"))]
47 (match_operand:QI 0 "nonimmediate_operand" "g"))]
53 (match_operand:DF 0 "general_operand" "gF"))]
59 (match_operand:SF 0 "general_operand" "gF"))]
65 (compare (match_operand:SI 0 "nonimmediate_operand" "g")
66 (match_operand:SI 1 "general_operand" "g")))]
72 (compare (match_operand:HI 0 "nonimmediate_operand" "g")
73 (match_operand:HI 1 "general_operand" "g")))]
79 (compare (match_operand:QI 0 "nonimmediate_operand" "g")
80 (match_operand:QI 1 "general_operand" "g")))]
86 (compare (match_operand:DF 0 "general_operand" "gF")
87 (match_operand:DF 1 "general_operand" "gF")))]
93 (compare (match_operand:SF 0 "general_operand" "gF")
94 (match_operand:SF 1 "general_operand" "gF")))]
100 (and:SI (match_operand:SI 0 "general_operand" "g")
101 (match_operand:SI 1 "general_operand" "g")))]
107 (and:HI (match_operand:HI 0 "general_operand" "g")
108 (match_operand:HI 1 "general_operand" "g")))]
114 (and:QI (match_operand:QI 0 "general_operand" "g")
115 (match_operand:QI 1 "general_operand" "g")))]
119 ;; The vax has no sltu or sgeu patterns, but does have two-operand
120 ;; add/subtract with carry. This is still better than the alternative.
121 ;; Since the cc0-using insn cannot be separated from the cc0-setting insn,
122 ;; and the two are created independently, we can't just use a define_expand
123 ;; to try to optimize this. (The "movl" and "clrl" insns alter the cc0
124 ;; flags, but leave the carry flag alone, but that can't easily be expressed.)
126 ;; Several two-operator combinations could be added to make slightly more
127 ;; optimal code, but they'd have to cover all combinations of plus and minus
128 ;; using match_dup. If you want to do this, I'd suggest changing the "sgeu"
129 ;; pattern to something like (minus (const_int 1) (ltu ...)), so fewer
130 ;; patterns need to be recognized.
131 ;; -- Ken Raeburn (Raeburn@Watch.COM) 24 August 1991.
134 [(set (match_operand:SI 0 "general_operand" "=ro")
135 (ltu (cc0) (const_int 0)))]
137 "clrl %0\;adwc $0,%0")
140 [(set (match_operand:SI 0 "general_operand" "=ro")
141 (geu (cc0) (const_int 0)))]
143 "movl $1,%0\;sbwc $0,%0")
146 [(set (match_operand:DF 0 "general_operand" "=g,g")
147 (match_operand:DF 1 "general_operand" "G,gF"))]
154 [(set (match_operand:SF 0 "general_operand" "=g,g")
155 (match_operand:SF 1 "general_operand" "G,gF"))]
161 ;; Some vaxes don't support this instruction.
162 ;;(define_insn "movti"
163 ;; [(set (match_operand:TI 0 "general_operand" "=g")
164 ;; (match_operand:TI 1 "general_operand" "g"))]
169 [(set (match_operand:DI 0 "general_operand" "=g,g")
170 (match_operand:DI 1 "general_operand" "I,g"))]
177 [(set (match_operand:SI 0 "general_operand" "=g")
178 (match_operand:SI 1 "general_operand" "g"))]
183 if (operands[1] == const1_rtx
184 && (link = find_reg_note (insn, REG_WAS_0, 0))
185 /* Make sure the insn that stored the 0 is still present. */
186 && ! INSN_DELETED_P (XEXP (link, 0))
187 && GET_CODE (XEXP (link, 0)) != NOTE
188 /* Make sure cross jumping didn't happen here. */
189 && no_labels_between_p (XEXP (link, 0), insn))
190 /* Fastest way to change a 0 to a 1. */
192 if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
194 if (push_operand (operands[0], SImode))
195 return \"pushab %a1\";
196 return \"movab %a1,%0\";
198 /* this is slower than a movl, except when pushing an operand */
199 if (operands[1] == const0_rtx)
201 if (GET_CODE (operands[1]) == CONST_INT
202 && (unsigned) INTVAL (operands[1]) >= 64)
204 int i = INTVAL (operands[1]);
205 if ((unsigned)(~i) < 64)
207 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
208 return \"mcoml %1,%0\";
210 if ((unsigned)i < 127)
212 operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
213 operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
214 return \"addl3 %2,%1,%0\";
216 /* trading speed for space */
217 if ((unsigned)i < 0x100)
218 return \"movzbl %1,%0\";
219 if (i >= -0x80 && i < 0)
220 return \"cvtbl %1,%0\";
221 if ((unsigned)i < 0x10000)
222 return \"movzwl %1,%0\";
223 if (i >= -0x8000 && i < 0)
224 return \"cvtwl %1,%0\";
226 if (push_operand (operands[0], SImode))
228 return \"movl %1,%0\";
232 [(set (match_operand:HI 0 "general_operand" "=g")
233 (match_operand:HI 1 "general_operand" "g"))]
238 if (operands[1] == const1_rtx
239 && (link = find_reg_note (insn, REG_WAS_0, 0))
240 /* Make sure the insn that stored the 0 is still present. */
241 && ! INSN_DELETED_P (XEXP (link, 0))
242 && GET_CODE (XEXP (link, 0)) != NOTE
243 /* Make sure cross jumping didn't happen here. */
244 && no_labels_between_p (XEXP (link, 0), insn))
245 /* Fastest way to change a 0 to a 1. */
247 if (operands[1] == const0_rtx)
249 if (GET_CODE (operands[1]) == CONST_INT
250 && (unsigned) INTVAL (operands[1]) >= 64)
252 int i = INTVAL (operands[1]);
253 if ((unsigned)((~i) & 0xffff) < 64)
255 operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff);
256 return \"mcomw %1,%0\";
258 if ((unsigned)(i & 0xffff) < 127)
260 operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
261 operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff);
262 return \"addw3 %2,%1,%0\";
264 /* this is a lot slower, and only saves 1 measly byte! */
265 /* if ((unsigned)i < 0x100)
266 return \"movzbw %1,%0\"; */
267 /* if (i >= -0x80 && i < 0)
268 return \"cvtbw %1,%0\"; */
270 return \"movw %1,%0\";
274 [(set (match_operand:QI 0 "general_operand" "=g")
275 (match_operand:QI 1 "general_operand" "g"))]
279 if (operands[1] == const0_rtx)
281 if (GET_CODE (operands[1]) == CONST_INT
282 && (unsigned) INTVAL (operands[1]) >= 64)
284 int i = INTVAL (operands[1]);
285 if ((unsigned)((~i) & 0xff) < 64)
287 operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff);
288 return \"mcomb %1,%0\";
291 return \"movb %1,%0\";
294 ;; The definition of this insn does not really explain what it does,
295 ;; but it should suffice
296 ;; that anything generated as this insn will be recognized as one
297 ;; and that it won't successfully combine with anything.
298 (define_insn "movstrhi"
299 [(set (match_operand:BLK 0 "general_operand" "=g")
300 (match_operand:BLK 1 "general_operand" "g"))
301 (use (match_operand:HI 2 "general_operand" "g"))
307 (clobber (reg:SI 5))]
311 ;; Extension and truncation insns.
313 (define_insn "truncsiqi2"
314 [(set (match_operand:QI 0 "general_operand" "=g")
315 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
319 (define_insn "truncsihi2"
320 [(set (match_operand:HI 0 "general_operand" "=g")
321 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
325 (define_insn "trunchiqi2"
326 [(set (match_operand:QI 0 "general_operand" "=g")
327 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
331 (define_insn "extendhisi2"
332 [(set (match_operand:SI 0 "general_operand" "=g")
333 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
337 (define_insn "extendqihi2"
338 [(set (match_operand:HI 0 "general_operand" "=g")
339 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
343 (define_insn "extendqisi2"
344 [(set (match_operand:SI 0 "general_operand" "=g")
345 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
349 (define_insn "extendsfdf2"
350 [(set (match_operand:DF 0 "general_operand" "=g")
351 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
355 (define_insn "truncdfsf2"
356 [(set (match_operand:SF 0 "general_operand" "=g")
357 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
361 (define_insn "zero_extendhisi2"
362 [(set (match_operand:SI 0 "general_operand" "=g")
363 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
367 (define_insn "zero_extendqihi2"
368 [(set (match_operand:HI 0 "general_operand" "=g")
369 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
373 (define_insn "zero_extendqisi2"
374 [(set (match_operand:SI 0 "general_operand" "=g")
375 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
379 ;; Fix-to-float conversion insns.
381 (define_insn "floatsisf2"
382 [(set (match_operand:SF 0 "general_operand" "=g")
383 (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
387 (define_insn "floatsidf2"
388 [(set (match_operand:DF 0 "general_operand" "=g")
389 (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
393 (define_insn "floathisf2"
394 [(set (match_operand:SF 0 "general_operand" "=g")
395 (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
399 (define_insn "floathidf2"
400 [(set (match_operand:DF 0 "general_operand" "=g")
401 (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
405 (define_insn "floatqisf2"
406 [(set (match_operand:SF 0 "general_operand" "=g")
407 (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
411 (define_insn "floatqidf2"
412 [(set (match_operand:DF 0 "general_operand" "=g")
413 (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
417 ;; Float-to-fix conversion insns.
419 (define_insn "fix_truncsfqi2"
420 [(set (match_operand:QI 0 "general_operand" "=g")
421 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
425 (define_insn "fix_truncsfhi2"
426 [(set (match_operand:HI 0 "general_operand" "=g")
427 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
431 (define_insn "fix_truncsfsi2"
432 [(set (match_operand:SI 0 "general_operand" "=g")
433 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
437 (define_insn "fix_truncdfqi2"
438 [(set (match_operand:QI 0 "general_operand" "=g")
439 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
443 (define_insn "fix_truncdfhi2"
444 [(set (match_operand:HI 0 "general_operand" "=g")
445 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
449 (define_insn "fix_truncdfsi2"
450 [(set (match_operand:SI 0 "general_operand" "=g")
451 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
455 ;;- All kinds of add instructions.
457 (define_insn "adddf3"
458 [(set (match_operand:DF 0 "general_operand" "=g,g,g")
459 (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
460 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
467 (define_insn "addsf3"
468 [(set (match_operand:SF 0 "general_operand" "=g,g,g")
469 (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
470 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
477 (define_insn "addsi3"
478 [(set (match_operand:SI 0 "general_operand" "=g")
479 (plus:SI (match_operand:SI 1 "general_operand" "g")
480 (match_operand:SI 2 "general_operand" "g")))]
484 if (rtx_equal_p (operands[0], operands[1]))
486 if (operands[2] == const1_rtx)
488 if (operands[2] == constm1_rtx)
490 if (GET_CODE (operands[2]) == CONST_INT
491 && (unsigned) (- INTVAL (operands[2])) < 64)
492 return \"subl2 $%n2,%0\";
493 if (GET_CODE (operands[2]) == CONST_INT
494 && (unsigned) INTVAL (operands[2]) >= 64
495 && GET_CODE (operands[1]) == REG)
496 return \"movab %c2(%1),%0\";
497 return \"addl2 %2,%0\";
499 if (rtx_equal_p (operands[0], operands[2]))
500 return \"addl2 %1,%0\";
501 if (GET_CODE (operands[2]) == CONST_INT
502 && (unsigned) (- INTVAL (operands[2])) < 64)
503 return \"subl3 $%n2,%1,%0\";
504 if (GET_CODE (operands[2]) == CONST_INT
505 && (unsigned) INTVAL (operands[2]) >= 64
506 && GET_CODE (operands[1]) == REG)
508 if (push_operand (operands[0], SImode))
509 return \"pushab %c2(%1)\";
510 return \"movab %c2(%1),%0\";
512 return \"addl3 %1,%2,%0\";
515 (define_insn "addhi3"
516 [(set (match_operand:HI 0 "general_operand" "=g")
517 (plus:HI (match_operand:HI 1 "general_operand" "g")
518 (match_operand:HI 2 "general_operand" "g")))]
522 if (rtx_equal_p (operands[0], operands[1]))
524 if (operands[2] == const1_rtx)
526 if (operands[2] == constm1_rtx)
528 if (GET_CODE (operands[2]) == CONST_INT
529 && (unsigned) (- INTVAL (operands[2])) < 64)
530 return \"subw2 $%n2,%0\";
531 return \"addw2 %2,%0\";
533 if (rtx_equal_p (operands[0], operands[2]))
534 return \"addw2 %1,%0\";
535 if (GET_CODE (operands[2]) == CONST_INT
536 && (unsigned) (- INTVAL (operands[2])) < 64)
537 return \"subw3 $%n2,%1,%0\";
538 return \"addw3 %1,%2,%0\";
541 (define_insn "addqi3"
542 [(set (match_operand:QI 0 "general_operand" "=g")
543 (plus:QI (match_operand:QI 1 "general_operand" "g")
544 (match_operand:QI 2 "general_operand" "g")))]
548 if (rtx_equal_p (operands[0], operands[1]))
550 if (operands[2] == const1_rtx)
552 if (operands[2] == constm1_rtx)
554 if (GET_CODE (operands[2]) == CONST_INT
555 && (unsigned) (- INTVAL (operands[2])) < 64)
556 return \"subb2 $%n2,%0\";
557 return \"addb2 %2,%0\";
559 if (rtx_equal_p (operands[0], operands[2]))
560 return \"addb2 %1,%0\";
561 if (GET_CODE (operands[2]) == CONST_INT
562 && (unsigned) (- INTVAL (operands[2])) < 64)
563 return \"subb3 $%n2,%1,%0\";
564 return \"addb3 %1,%2,%0\";
567 ;; The add-with-carry (adwc) instruction only accepts two operands.
568 (define_insn "adddi3"
569 [(set (match_operand:DI 0 "general_operand" "=ro>,ro>")
570 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
571 (match_operand:DI 2 "general_operand" "Fro,F")))]
579 split_quadword_operands (operands, low, 3);
581 if (rtx_equal_p (operands[0], operands[1]))
583 if (low[2] == const0_rtx)
584 /* Should examine operand, punt if not POST_INC. */
585 pattern = \"tstl %0\", carry = 0;
586 else if (low[2] == const1_rtx)
587 pattern = \"incl %0\";
589 pattern = \"addl2 %2,%0\";
593 if (low[2] == const0_rtx)
594 pattern = \"movl %1,%0\", carry = 0;
596 pattern = \"addl3 %2,%1,%0\";
599 output_asm_insn (pattern, low);
601 /* If CARRY is 0, we don't have any carry value to worry about. */
602 return OUT_FCN (CODE_FOR_addsi3) (operands, insn);
603 /* %0 = C + %1 + %2 */
604 if (!rtx_equal_p (operands[0], operands[1]))
605 output_asm_insn ((operands[1] == const0_rtx
607 : \"movl %1,%0\"), operands);
608 return \"adwc %2,%0\";
611 ;;- All kinds of subtract instructions.
613 (define_insn "subdf3"
614 [(set (match_operand:DF 0 "general_operand" "=g,g")
615 (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
616 (match_operand:DF 2 "general_operand" "gF,gF")))]
622 (define_insn "subsf3"
623 [(set (match_operand:SF 0 "general_operand" "=g,g")
624 (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
625 (match_operand:SF 2 "general_operand" "gF,gF")))]
631 (define_insn "subsi3"
632 [(set (match_operand:SI 0 "general_operand" "=g,g")
633 (minus:SI (match_operand:SI 1 "general_operand" "0,g")
634 (match_operand:SI 2 "general_operand" "g,g")))]
640 (define_insn "subhi3"
641 [(set (match_operand:HI 0 "general_operand" "=g,g")
642 (minus:HI (match_operand:HI 1 "general_operand" "0,g")
643 (match_operand:HI 2 "general_operand" "g,g")))]
649 (define_insn "subqi3"
650 [(set (match_operand:QI 0 "general_operand" "=g,g")
651 (minus:QI (match_operand:QI 1 "general_operand" "0,g")
652 (match_operand:QI 2 "general_operand" "g,g")))]
658 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
659 (define_insn "subdi3"
660 [(set (match_operand:DI 0 "general_operand" "=or>,or>")
661 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
662 (match_operand:DI 2 "general_operand" "For,F")))]
670 split_quadword_operands (operands, low, 3);
671 /* Subtract low parts. */
672 if (rtx_equal_p (operands[0], operands[1]))
674 if (low[2] == const0_rtx)
675 pattern = 0, carry = 0;
676 else if (low[2] == constm1_rtx)
677 pattern = \"decl %0\";
679 pattern = \"subl2 %2,%0\";
683 if (low[2] == constm1_rtx)
684 pattern = \"decl %0\";
685 else if (low[2] == const0_rtx)
686 pattern = OUT_FCN (CODE_FOR_movsi) (low, insn), carry = 0;
688 pattern = \"subl3 %2,%1,%0\";
691 output_asm_insn (pattern, low);
694 if (!rtx_equal_p (operands[0], operands[1]))
695 return \"movl %1,%0\;sbwc %2,%0\";
696 return \"sbwc %2,%0\";
697 /* %0 = %2 - %1 - C */
699 return OUT_FCN (CODE_FOR_subsi3) (operands, insn);
702 ;;- Multiply instructions.
704 (define_insn "muldf3"
705 [(set (match_operand:DF 0 "general_operand" "=g,g,g")
706 (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
707 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
714 (define_insn "mulsf3"
715 [(set (match_operand:SF 0 "general_operand" "=g,g,g")
716 (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
717 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
724 (define_insn "mulsi3"
725 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
726 (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
727 (match_operand:SI 2 "general_operand" "g,0,g")))]
734 (define_insn "mulhi3"
735 [(set (match_operand:HI 0 "general_operand" "=g,g,")
736 (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
737 (match_operand:HI 2 "general_operand" "g,0,g")))]
744 (define_insn "mulqi3"
745 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
746 (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
747 (match_operand:QI 2 "general_operand" "g,0,g")))]
754 (define_insn "mulsidi3"
755 [(set (match_operand:DI 0 "general_operand" "=g")
756 (mult:DI (sign_extend:DI
757 (match_operand:SI 1 "nonimmediate_operand" "g"))
759 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
764 [(set (match_operand:DI 0 "general_operand" "=g")
766 (mult:DI (sign_extend:DI
767 (match_operand:SI 1 "nonimmediate_operand" "g"))
769 (match_operand:SI 2 "nonimmediate_operand" "g")))
770 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
774 ;; 'F' constraint means type CONST_DOUBLE
776 [(set (match_operand:DI 0 "general_operand" "=g")
778 (mult:DI (sign_extend:DI
779 (match_operand:SI 1 "nonimmediate_operand" "g"))
781 (match_operand:SI 2 "nonimmediate_operand" "g")))
782 (match_operand:DI 3 "immediate_operand" "F")))]
783 "GET_CODE (operands[3]) == CONST_DOUBLE
784 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
787 if (CONST_DOUBLE_HIGH (operands[3]))
788 operands[3] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[3]));
789 return \"emul %1,%2,%3,%0\";
792 ;;- Divide instructions.
794 (define_insn "divdf3"
795 [(set (match_operand:DF 0 "general_operand" "=g,g")
796 (div:DF (match_operand:DF 1 "general_operand" "0,gF")
797 (match_operand:DF 2 "general_operand" "gF,gF")))]
803 (define_insn "divsf3"
804 [(set (match_operand:SF 0 "general_operand" "=g,g")
805 (div:SF (match_operand:SF 1 "general_operand" "0,gF")
806 (match_operand:SF 2 "general_operand" "gF,gF")))]
812 (define_insn "divsi3"
813 [(set (match_operand:SI 0 "general_operand" "=g,g")
814 (div:SI (match_operand:SI 1 "general_operand" "0,g")
815 (match_operand:SI 2 "general_operand" "g,g")))]
821 (define_insn "divhi3"
822 [(set (match_operand:HI 0 "general_operand" "=g,g")
823 (div:HI (match_operand:HI 1 "general_operand" "0,g")
824 (match_operand:HI 2 "general_operand" "g,g")))]
830 (define_insn "divqi3"
831 [(set (match_operand:QI 0 "general_operand" "=g,g")
832 (div:QI (match_operand:QI 1 "general_operand" "0,g")
833 (match_operand:QI 2 "general_operand" "g,g")))]
839 ;This is left out because it is very slow;
840 ;we are better off programming around the "lack" of this insn.
841 ;(define_insn "divmoddisi4"
842 ; [(set (match_operand:SI 0 "general_operand" "=g")
843 ; (div:SI (match_operand:DI 1 "general_operand" "g")
844 ; (match_operand:SI 2 "general_operand" "g")))
845 ; (set (match_operand:SI 3 "general_operand" "=g")
846 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
847 ; (match_operand:SI 2 "general_operand" "g")))]
849 ; "ediv %2,%1,%0,%3")
851 ;; Bit-and on the vax is done with a clear-bits insn.
852 (define_expand "andsi3"
853 [(set (match_operand:SI 0 "general_operand" "=g")
854 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
855 (match_operand:SI 2 "general_operand" "g")))]
859 if (GET_CODE (operands[1]) == CONST_INT)
860 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[1]));
862 operands[1] = expand_unop (SImode, one_cmpl_optab, operands[1], 0, 1);
865 (define_expand "andhi3"
866 [(set (match_operand:HI 0 "general_operand" "=g")
867 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
868 (match_operand:HI 2 "general_operand" "g")))]
872 rtx op = operands[1];
873 if (GET_CODE (op) == CONST_INT)
874 operands[1] = gen_rtx (CONST_INT, VOIDmode,
875 ((1 << 16) - 1) & ~INTVAL (op));
877 operands[1] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
880 (define_expand "andqi3"
881 [(set (match_operand:QI 0 "general_operand" "=g")
882 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
883 (match_operand:QI 2 "general_operand" "g")))]
887 rtx op = operands[1];
888 if (GET_CODE (op) == CONST_INT)
889 operands[1] = gen_rtx (CONST_INT, VOIDmode,
890 ((1 << 8) - 1) & ~INTVAL (op));
892 operands[1] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
896 [(set (match_operand:SI 0 "general_operand" "=g,g")
897 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
898 (match_operand:SI 2 "general_operand" "0,g")))]
905 [(set (match_operand:HI 0 "general_operand" "=g,g")
906 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
907 (match_operand:HI 2 "general_operand" "0,g")))]
914 [(set (match_operand:QI 0 "general_operand" "=g,g")
915 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
916 (match_operand:QI 2 "general_operand" "0,g")))]
922 ;; The following used to be needed because constant propagation can
923 ;; create them starting from the bic insn patterns above. This is no
924 ;; longer a problem. However, having these patterns allows optimization
925 ;; opportunities in combine.c.
928 [(set (match_operand:SI 0 "general_operand" "=g,g")
929 (and:SI (match_operand:SI 1 "general_operand" "0,g")
930 (match_operand:SI 2 "const_int_operand" "n,n")))]
937 [(set (match_operand:HI 0 "general_operand" "=g,g")
938 (and:HI (match_operand:HI 1 "general_operand" "0,g")
939 (match_operand:HI 2 "const_int_operand" "n,n")))]
946 [(set (match_operand:QI 0 "general_operand" "=g,g")
947 (and:QI (match_operand:QI 1 "general_operand" "0,g")
948 (match_operand:QI 2 "const_int_operand" "n,n")))]
954 ;;- Bit set instructions.
956 (define_insn "iorsi3"
957 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
958 (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
959 (match_operand:SI 2 "general_operand" "g,0,g")))]
966 (define_insn "iorhi3"
967 [(set (match_operand:HI 0 "general_operand" "=g,g,g")
968 (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
969 (match_operand:HI 2 "general_operand" "g,0,g")))]
976 (define_insn "iorqi3"
977 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
978 (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
979 (match_operand:QI 2 "general_operand" "g,0,g")))]
986 ;;- xor instructions.
988 (define_insn "xorsi3"
989 [(set (match_operand:SI 0 "general_operand" "=g,g,g")
990 (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
991 (match_operand:SI 2 "general_operand" "g,0,g")))]
998 (define_insn "xorhi3"
999 [(set (match_operand:HI 0 "general_operand" "=g,g,g")
1000 (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1001 (match_operand:HI 2 "general_operand" "g,0,g")))]
1008 (define_insn "xorqi3"
1009 [(set (match_operand:QI 0 "general_operand" "=g,g,g")
1010 (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1011 (match_operand:QI 2 "general_operand" "g,0,g")))]
1018 (define_insn "negdf2"
1019 [(set (match_operand:DF 0 "general_operand" "=g")
1020 (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1024 (define_insn "negsf2"
1025 [(set (match_operand:SF 0 "general_operand" "=g")
1026 (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1030 (define_insn "negsi2"
1031 [(set (match_operand:SI 0 "general_operand" "=g")
1032 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1036 (define_insn "neghi2"
1037 [(set (match_operand:HI 0 "general_operand" "=g")
1038 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1042 (define_insn "negqi2"
1043 [(set (match_operand:QI 0 "general_operand" "=g")
1044 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1048 (define_insn "one_cmplsi2"
1049 [(set (match_operand:SI 0 "general_operand" "=g")
1050 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1054 (define_insn "one_cmplhi2"
1055 [(set (match_operand:HI 0 "general_operand" "=g")
1056 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1060 (define_insn "one_cmplqi2"
1061 [(set (match_operand:QI 0 "general_operand" "=g")
1062 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1066 ;; Arithmetic right shift on the vax works by negating the shift count,
1067 ;; then emitting a right shift with the shift count negated. This means
1068 ;; that all actual shift counts in the RTL will be positive. This
1069 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1070 ;; which isn't valid.
1071 (define_expand "ashrsi3"
1072 [(set (match_operand:SI 0 "general_operand" "=g")
1073 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1074 (match_operand:QI 2 "general_operand" "g")))]
1078 if (GET_CODE (operands[2]) != CONST_INT)
1079 operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1083 [(set (match_operand:SI 0 "general_operand" "=g")
1084 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1085 (match_operand:QI 2 "const_int_operand" "n")))]
1090 [(set (match_operand:SI 0 "general_operand" "=g")
1091 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1092 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1096 (define_insn "ashlsi3"
1097 [(set (match_operand:SI 0 "general_operand" "=g")
1098 (ashift:SI (match_operand:SI 1 "general_operand" "g")
1099 (match_operand:QI 2 "general_operand" "g")))]
1103 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1104 return \"addl2 %0,%0\";
1105 if (GET_CODE (operands[1]) == REG
1106 && GET_CODE (operands[2]) == CONST_INT)
1108 int i = INTVAL (operands[2]);
1110 return \"addl3 %1,%1,%0\";
1112 return \"moval 0[%1],%0\";
1114 return \"movad 0[%1],%0\";
1116 return \"ashl %2,%1,%0\";
1119 ;; Arithmetic right shift on the vax works by negating the shift count.
1120 (define_expand "ashrdi3"
1121 [(set (match_operand:DI 0 "general_operand" "=g")
1122 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1123 (match_operand:QI 2 "general_operand" "g")))]
1127 operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1130 (define_insn "ashldi3"
1131 [(set (match_operand:DI 0 "general_operand" "=g")
1132 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1133 (match_operand:QI 2 "general_operand" "g")))]
1138 [(set (match_operand:DI 0 "general_operand" "=g")
1139 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1140 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1144 ;; Rotate right on the vax works by negating the shift count.
1145 (define_expand "rotrsi3"
1146 [(set (match_operand:SI 0 "general_operand" "=g")
1147 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1148 (match_operand:QI 2 "general_operand" "g")))]
1152 if (GET_CODE (operands[2]) != CONST_INT)
1153 operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1156 (define_insn "rotlsi3"
1157 [(set (match_operand:SI 0 "general_operand" "=g")
1158 (rotate:SI (match_operand:SI 1 "general_operand" "g")
1159 (match_operand:QI 2 "general_operand" "g")))]
1164 [(set (match_operand:SI 0 "general_operand" "=g")
1165 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1166 (match_operand:QI 2 "const_int_operand" "n")))]
1171 [(set (match_operand:SI 0 "general_operand" "=g")
1172 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1173 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1177 ;This insn is probably slower than a multiply and an add.
1179 ; [(set (match_operand:SI 0 "general_operand" "=g")
1180 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1181 ; (match_operand:SI 2 "general_operand" "g"))
1182 ; (match_operand:SI 3 "general_operand" "g")))]
1184 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1186 ;; Special cases of bit-field insns which we should
1187 ;; recognize in preference to the general case.
1188 ;; These handle aligned 8-bit and 16-bit fields,
1189 ;; which can usually be done with move instructions.
1192 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1193 (match_operand:QI 1 "const_int_operand" "n")
1194 (match_operand:SI 2 "const_int_operand" "n"))
1195 (match_operand:SI 3 "general_operand" "g"))]
1196 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1197 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1198 && (GET_CODE (operands[0]) == REG
1199 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1202 if (REG_P (operands[0]))
1204 if (INTVAL (operands[2]) != 0)
1205 return \"insv %3,%2,%1,%0\";
1209 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1211 if (INTVAL (operands[1]) == 8)
1212 return \"movb %3,%0\";
1213 return \"movw %3,%0\";
1217 [(set (match_operand:SI 0 "general_operand" "=&g")
1218 (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1219 (match_operand:QI 2 "const_int_operand" "n")
1220 (match_operand:SI 3 "const_int_operand" "n")))]
1221 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1222 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1223 && (GET_CODE (operands[1]) == REG
1224 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1227 if (REG_P (operands[1]))
1229 if (INTVAL (operands[3]) != 0)
1230 return \"extzv %3,%2,%1,%0\";
1234 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1236 if (INTVAL (operands[2]) == 8)
1237 return \"movzbl %1,%0\";
1238 return \"movzwl %1,%0\";
1242 [(set (match_operand:SI 0 "general_operand" "=g")
1243 (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1244 (match_operand:QI 2 "const_int_operand" "n")
1245 (match_operand:SI 3 "const_int_operand" "n")))]
1246 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1247 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1248 && (GET_CODE (operands[1]) == REG
1249 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1252 if (REG_P (operands[1]))
1254 if (INTVAL (operands[3]) != 0)
1255 return \"extv %3,%2,%1,%0\";
1259 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1261 if (INTVAL (operands[2]) == 8)
1262 return \"cvtbl %1,%0\";
1263 return \"cvtwl %1,%0\";
1266 ;; Register-only SImode cases of bit-field insns.
1271 (sign_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
1272 (match_operand:QI 1 "general_operand" "g")
1273 (match_operand:SI 2 "general_operand" "g"))
1274 (match_operand:SI 3 "general_operand" "g")))]
1281 (zero_extract:SI (match_operand:SI 0 "nonmemory_operand" "r")
1282 (match_operand:QI 1 "general_operand" "g")
1283 (match_operand:SI 2 "general_operand" "g"))
1284 (match_operand:SI 3 "general_operand" "g")))]
1286 "cmpzv %2,%1,%0,%3")
1289 [(set (match_operand:SI 0 "general_operand" "=g")
1290 (sign_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
1291 (match_operand:QI 2 "general_operand" "g")
1292 (match_operand:SI 3 "general_operand" "g")))]
1297 [(set (match_operand:SI 0 "general_operand" "=g")
1298 (zero_extract:SI (match_operand:SI 1 "nonmemory_operand" "r")
1299 (match_operand:QI 2 "general_operand" "g")
1300 (match_operand:SI 3 "general_operand" "g")))]
1302 "extzv %3,%2,%1,%0")
1304 ;; Non-register cases.
1305 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1306 ;; don't match these (and therefore match the cases above instead).
1311 (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1312 (match_operand:QI 1 "general_operand" "g")
1313 (match_operand:SI 2 "general_operand" "g"))
1314 (match_operand:SI 3 "general_operand" "g")))]
1321 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1322 (match_operand:QI 1 "general_operand" "g")
1323 (match_operand:SI 2 "general_operand" "g"))
1324 (match_operand:SI 3 "general_operand" "g")))]
1326 "cmpzv %2,%1,%0,%3")
1329 [(set (match_operand:SI 0 "general_operand" "=g")
1330 (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1331 (match_operand:QI 2 "general_operand" "g")
1332 (match_operand:SI 3 "general_operand" "g")))]
1336 (define_insn "extzv"
1337 [(set (match_operand:SI 0 "general_operand" "=g")
1338 (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1339 (match_operand:QI 2 "general_operand" "g")
1340 (match_operand:SI 3 "general_operand" "g")))]
1342 "extzv %3,%2,%1,%0")
1345 [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1346 (match_operand:QI 1 "general_operand" "g")
1347 (match_operand:SI 2 "general_operand" "g"))
1348 (match_operand:SI 3 "general_operand" "g"))]
1353 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1354 (match_operand:QI 1 "general_operand" "g")
1355 (match_operand:SI 2 "general_operand" "g"))
1356 (match_operand:SI 3 "general_operand" "g"))]
1362 (label_ref (match_operand 0 "" "")))]
1368 (if_then_else (eq (cc0)
1370 (label_ref (match_operand 0 "" ""))
1377 (if_then_else (ne (cc0)
1379 (label_ref (match_operand 0 "" ""))
1386 (if_then_else (gt (cc0)
1388 (label_ref (match_operand 0 "" ""))
1395 (if_then_else (gtu (cc0)
1397 (label_ref (match_operand 0 "" ""))
1404 (if_then_else (lt (cc0)
1406 (label_ref (match_operand 0 "" ""))
1413 (if_then_else (ltu (cc0)
1415 (label_ref (match_operand 0 "" ""))
1422 (if_then_else (ge (cc0)
1424 (label_ref (match_operand 0 "" ""))
1431 (if_then_else (geu (cc0)
1433 (label_ref (match_operand 0 "" ""))
1440 (if_then_else (le (cc0)
1442 (label_ref (match_operand 0 "" ""))
1449 (if_then_else (leu (cc0)
1451 (label_ref (match_operand 0 "" ""))
1456 ;; Recognize reversed jumps.
1459 (if_then_else (match_operator 0 "comparison_operator"
1463 (label_ref (match_operand 1 "" ""))))]
1465 "j%C0 %l1") ; %C0 negates condition
1467 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1468 ;; if this insn is SImode in the hardware. However, if it is memory,
1469 ;; we use QImode. So we can't allow the memory address to be indexed.
1474 (ne (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
1476 (match_operand:SI 1 "general_operand" "I,g"))
1478 (label_ref (match_operand 2 "" ""))
1488 (eq (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
1490 (match_operand:SI 1 "general_operand" "I,g"))
1492 (label_ref (match_operand 2 "" ""))
1502 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1504 (match_operand:SI 1 "general_operand" "I,g"))
1506 (label_ref (match_operand 2 "" ""))
1516 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1518 (match_operand:SI 1 "general_operand" "I,g"))
1520 (label_ref (match_operand 2 "" ""))
1527 ;; Subtract-and-jump and Add-and-jump insns.
1528 ;; These are not used when output is for the Unix assembler
1529 ;; because it does not know how to modify them to reach far.
1531 ;; Normal sob insns.
1536 (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1539 (label_ref (match_operand 1 "" ""))
1542 (plus:SI (match_dup 0)
1550 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1553 (label_ref (match_operand 1 "" ""))
1556 (plus:SI (match_dup 0)
1561 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1565 (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1567 (match_operand:SI 1 "general_operand" "g"))
1568 (label_ref (match_operand 2 "" ""))
1571 (plus:SI (match_dup 0)
1574 "jaoblss %1,%0,%l2")
1579 (lt (match_operand:SI 0 "general_operand" "+g")
1580 (match_operand:SI 1 "general_operand" "g"))
1581 (label_ref (match_operand 2 "" ""))
1584 (plus:SI (match_dup 0)
1586 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1587 "jaoblss %P1,%0,%l2")
1592 (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1594 (match_operand:SI 1 "general_operand" "g"))
1595 (label_ref (match_operand 2 "" ""))
1598 (plus:SI (match_dup 0)
1601 "jaobleq %1,%0,%l2")
1606 (le (match_operand:SI 0 "general_operand" "+g")
1607 (match_operand:SI 1 "general_operand" "g"))
1608 (label_ref (match_operand 2 "" ""))
1611 (plus:SI (match_dup 0)
1613 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1614 "jaobleq %P1,%0,%l2")
1616 ;; Something like a sob insn, but compares against -1.
1617 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1622 (ne (match_operand:SI 0 "general_operand" "g")
1624 (label_ref (match_operand 1 "" ""))
1627 (plus:SI (match_dup 0)
1630 "decl %0\;jgequ %l1")
1632 ;; Note that operand 1 is total size of args, in bytes,
1633 ;; and what the call insn wants is the number of words.
1634 (define_insn "call_pop"
1635 [(call (match_operand:QI 0 "memory_operand" "m")
1636 (match_operand:QI 1 "general_operand" "g"))
1637 (set (reg:SI 14) (plus:SI (reg:SI 14)
1638 (match_operand:SI 3 "immediate_operand" "i")))]
1641 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4)
1642 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1643 return \"calls $0,%0\;addl2 %1,sp\";
1644 operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1645 return \"calls %1,%0\";
1648 (define_insn "call_value_pop"
1649 [(set (match_operand 0 "" "=g")
1650 (call (match_operand:QI 1 "memory_operand" "m")
1651 (match_operand:QI 2 "general_operand" "g")))
1652 (set (reg:SI 14) (plus:SI (reg:SI 14)
1653 (match_operand:SI 4 "immediate_operand" "i")))]
1656 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4)
1657 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1658 return \"calls $0,%1\;addl2 %2,sp\";
1659 operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1660 return \"calls %2,%1\";
1663 ;; Define another set of these for the case of functions with no
1664 ;; operands. In that case, combine may simplify the adjustment of sp.
1666 [(call (match_operand:QI 0 "memory_operand" "m")
1667 (match_operand:QI 1 "general_operand" "g"))
1668 (set (reg:SI 14) (reg:SI 14))]
1671 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 255 * 4)
1672 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1673 return \"calls $0,%0\;addl2 %1,sp\";
1674 operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1675 return \"calls %1,%0\";
1679 [(set (match_operand 0 "" "=g")
1680 (call (match_operand:QI 1 "memory_operand" "m")
1681 (match_operand:QI 2 "general_operand" "g")))
1682 (set (reg:SI 14) (reg:SI 14))]
1685 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 255 * 4)
1686 /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1687 return \"calls $0,%1\;addl2 %2,sp\";
1688 operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1689 return \"calls %2,%1\";
1692 (define_insn "return"
1702 (define_insn "indirect_jump"
1703 [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
1704 "(GET_CODE (operands[0]) != MEM || offsettable_memref_p (operands[0]))"
1707 (define_insn "casesi"
1709 (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1710 (match_operand:SI 1 "general_operand" "g"))
1711 (match_operand:SI 2 "general_operand" "g"))
1712 (plus:SI (sign_extend:SI
1715 (mult:SI (minus:SI (match_dup 0)
1718 (label_ref:SI (match_operand 3 "" "")))
1723 ;; This used to arise from the preceding by simplification
1724 ;; if operand 1 is zero. Perhaps it is no longer necessary.
1727 (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
1728 (match_operand:SI 1 "general_operand" "g"))
1729 (plus:SI (sign_extend:SI
1732 (mult:SI (minus:SI (match_dup 0)
1735 (label_ref:SI (match_operand 3 "" "")))
1740 ;;- load or push effective address
1741 ;; These come after the move and add/sub patterns
1742 ;; because we don't want pushl $1 turned into pushad 1.
1743 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1746 [(set (match_operand:SI 0 "general_operand" "=<,g")
1747 (match_operand:QI 1 "address_operand" "p,p"))]
1754 [(set (match_operand:SI 0 "general_operand" "=<,g")
1755 (match_operand:HI 1 "address_operand" "p,p"))]
1762 [(set (match_operand:SI 0 "general_operand" "=<,g")
1763 (match_operand:SI 1 "address_operand" "p,p"))]
1770 [(set (match_operand:SI 0 "general_operand" "=<,g")
1771 (match_operand:DI 1 "address_operand" "p,p"))]
1778 [(set (match_operand:SI 0 "general_operand" "=<,g")
1779 (match_operand:SF 1 "address_operand" "p,p"))]
1786 [(set (match_operand:SI 0 "general_operand" "=<,g")
1787 (match_operand:DF 1 "address_operand" "p,p"))]
1793 ;; These used to be peepholes, but it is more straightforward to do them
1794 ;; as single insns. However, we must force the output to be a register
1795 ;; if it is not an offsettable address so that we know that we can assign
1798 ;; If we had a good way of evaluating the relative costs, these could be
1799 ;; machine-independent.
1801 ;; Optimize extzv ...,z; andl2 ...,z
1802 ;; or ashl ...,z; andl2 ...,z
1803 ;; with other operands constant. This is what the combiner converts the
1804 ;; above sequences to before attempting to recognize the new insn.
1807 [(set (match_operand:SI 0 "general_operand" "=ro")
1808 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1809 (match_operand:QI 2 "const_int_operand" "n"))
1810 (match_operand:SI 3 "const_int_operand" "n")))]
1811 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1814 unsigned long mask1 = INTVAL (operands[3]);
1815 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1817 if ((mask1 & mask2) != mask1)
1818 operands[3] = gen_rtx (CONST_INT, VOIDmode, mask1 & mask2);
1820 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1823 ;; left-shift and mask
1824 ;; The only case where `ashl' is better is if the mask only turns off
1825 ;; bits that the ashl would anyways, in which case it should have been
1829 [(set (match_operand:SI 0 "general_operand" "=ro")
1830 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
1831 (match_operand:QI 2 "const_int_operand" "n"))
1832 (match_operand:SI 3 "const_int_operand" "n")))]
1836 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1837 INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1838 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1841 ;;- Local variables:
1843 ;;- comment-start: ";;- "
1844 ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1845 ;;- eval: (modify-syntax-entry ?[ "(]")
1846 ;;- eval: (modify-syntax-entry ?] ")[")
1847 ;;- eval: (modify-syntax-entry ?{ "(}")
1848 ;;- eval: (modify-syntax-entry ?} "){")