1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; UNSPEC_VOLATILE usage:
34 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
36 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
40 ;; Integer modes supported on VAX, withd a mapping from machine mode
41 ;; to mnemonic suffix. DImode is always a special case.
42 (define_mode_macro VAXint [QI HI SI])
43 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l")])
45 ;; Similar for float modes supported on VAX.
46 (define_mode_macro VAXfp [SF DF])
47 (define_mode_attr fsfx [(SF "f") (DF "%#")])
49 ;; Some ouput patterns want integer immediates with a prefix...
50 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
52 ;; We don't want to allow a constant operand for test insns because
53 ;; We don't want to allow a constant operand for test insns because
54 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
55 ;; be folded while optimizing anyway.
57 (define_insn "tst<mode>"
59 (match_operand:VAXint 0 "nonimmediate_operand" "g"))]
61 "tst<VAXint:isfx> %0")
63 (define_insn "tst<mode>"
65 (match_operand:VAXfp 0 "general_operand" "gF"))]
69 (define_insn "cmp<mode>"
71 (compare (match_operand:VAXint 0 "nonimmediate_operand" "g")
72 (match_operand:VAXint 1 "general_operand" "g")))]
74 "cmp<VAXint:isfx> %0,%1")
76 (define_insn "cmp<mode>"
78 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
79 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
83 cmp<VAXfp:fsfx> %0,%1")
85 (define_insn "*bit<mode>"
87 (and:VAXint (match_operand:VAXint 0 "general_operand" "g")
88 (match_operand:VAXint 1 "general_operand" "g")))]
90 "bit<VAXint:isfx> %0,%1")
92 ;; The VAX has no sCOND insns. It does have add/subtract with carry
93 ;; which could be used to implement the sltu and sgeu patterns. However,
94 ;; to do this properly requires a complete rewrite of the compare insns
95 ;; to keep them together with the sltu/sgeu insns until after the
96 ;; reload pass is complete. The previous implementation didn't do this
97 ;; and has been deleted.
100 (define_insn "mov<mode>"
101 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
102 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
106 mov<VAXfp:fsfx> %1,%0")
108 ;; Some VAXen don't support this instruction.
109 ;;(define_insn "movti"
110 ;; [(set (match_operand:TI 0 "general_operand" "=g")
111 ;; (match_operand:TI 1 "general_operand" "g"))]
116 [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
117 (match_operand:DI 1 "general_operand" "I,g"))]
123 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
124 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
125 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
126 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
127 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
128 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
129 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
130 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
133 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
134 ;; but on a VAX 9000 most move and add instructions with one constant
135 ;; operand take 1 cycle).
137 ;; Loads of constants between 64 and 128 used to be done with
138 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
140 (define_insn "mov<mode>"
141 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
142 (match_operand:VAXint 1 "general_operand" "g"))]
144 "* return vax_output_int_move (insn, operands, <MODE>mode);")
146 (define_insn "movstricthi"
147 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
148 (match_operand:HI 1 "general_operand" "g"))]
152 if (GET_CODE (operands[1]) == CONST_INT)
154 int i = INTVAL (operands[1]);
157 else if ((unsigned int)i < 64)
158 return \"movw %1,%0\";
159 else if ((unsigned int)~i < 64)
160 return \"mcomw %H1,%0\";
161 else if ((unsigned int)i < 256)
162 return \"movzbw %1,%0\";
164 return \"movw %1,%0\";
167 (define_insn "movstrictqi"
168 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
169 (match_operand:QI 1 "general_operand" "g"))]
173 if (GET_CODE (operands[1]) == CONST_INT)
175 int i = INTVAL (operands[1]);
178 else if ((unsigned int)~i < 64)
179 return \"mcomb %B1,%0\";
181 return \"movb %1,%0\";
184 ;; This is here to accept 4 arguments and pass the first 3 along
185 ;; to the movmemhi1 pattern that really does the work.
186 (define_expand "movmemhi"
187 [(set (match_operand:BLK 0 "general_operand" "=g")
188 (match_operand:BLK 1 "general_operand" "g"))
189 (use (match_operand:HI 2 "general_operand" "g"))
190 (match_operand 3 "" "")]
193 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
197 ;; The definition of this insn does not really explain what it does,
198 ;; but it should suffice
199 ;; that anything generated as this insn will be recognized as one
200 ;; and that it won't successfully combine with anything.
201 (define_insn "movmemhi1"
202 [(set (match_operand:BLK 0 "memory_operand" "=m")
203 (match_operand:BLK 1 "memory_operand" "m"))
204 (use (match_operand:HI 2 "general_operand" "g"))
210 (clobber (reg:SI 5))]
214 ;; Extension and truncation insns.
216 (define_insn "truncsiqi2"
217 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
218 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
222 (define_insn "truncsihi2"
223 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
224 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
228 (define_insn "trunchiqi2"
229 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
230 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
234 (define_insn "extendhisi2"
235 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
236 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
240 (define_insn "extendqihi2"
241 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
242 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
246 (define_insn "extendqisi2"
247 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
248 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
252 (define_insn "extendsfdf2"
253 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
254 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
258 (define_insn "truncdfsf2"
259 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
260 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
264 (define_insn "zero_extendhisi2"
265 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
266 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
270 (define_insn "zero_extendqihi2"
271 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
272 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
276 (define_insn "zero_extendqisi2"
277 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
278 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
282 ;; Fix-to-float conversion insns.
284 (define_insn "float<VAXint:mode><VAXfp:mode>2"
285 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
286 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
288 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
290 ;; Float-to-fix conversion insns.
292 (define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2"
293 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
294 (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
296 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
298 ;;- All kinds of add instructions.
300 (define_insn "add<mode>3"
301 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
302 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
303 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
306 add<VAXfp:fsfx>2 %2,%0
307 add<VAXfp:fsfx>2 %1,%0
308 add<VAXfp:fsfx>3 %1,%2,%0")
310 (define_insn "add<mode>3"
311 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
312 (plus:VAXint (match_operand:VAXint 1 "general_operand" "g")
313 (match_operand:VAXint 2 "general_operand" "g")))]
315 "* return vax_output_int_add (insn, operands, <MODE>mode);")
317 ;; The add-with-carry (adwc) instruction only accepts two operands.
318 (define_insn "adddi3"
319 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
320 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
321 (match_operand:DI 2 "general_operand" "Fro,F")))]
329 split_quadword_operands (operands, low, 3);
331 if (rtx_equal_p (operands[0], operands[1]))
333 if (low[2] == const0_rtx)
334 /* Should examine operand, punt if not POST_INC. */
335 pattern = \"tstl %0\", carry = 0;
336 else if (low[2] == const1_rtx)
337 pattern = \"incl %0\";
339 pattern = \"addl2 %2,%0\";
343 if (low[2] == const0_rtx)
344 pattern = \"movl %1,%0\", carry = 0;
346 pattern = \"addl3 %2,%1,%0\";
349 output_asm_insn (pattern, low);
351 /* If CARRY is 0, we don't have any carry value to worry about. */
352 return get_insn_template (CODE_FOR_addsi3, insn);
353 /* %0 = C + %1 + %2 */
354 if (!rtx_equal_p (operands[0], operands[1]))
355 output_asm_insn ((operands[1] == const0_rtx
357 : \"movl %1,%0\"), operands);
358 return \"adwc %2,%0\";
361 ;;- All kinds of subtract instructions.
363 (define_insn "sub<mode>3"
364 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
365 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
366 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
369 sub<VAXfp:fsfx>2 %2,%0
370 sub<VAXfp:fsfx>3 %2,%1,%0")
372 (define_insn "sub<mode>3"
373 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
374 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
375 (match_operand:VAXint 2 "general_operand" "g,g")))]
378 sub<VAXint:isfx>2 %2,%0
379 sub<VAXint:isfx>3 %2,%1,%0")
381 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
382 (define_insn "subdi3"
383 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
384 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
385 (match_operand:DI 2 "general_operand" "For,F")))]
393 split_quadword_operands (operands, low, 3);
394 /* Subtract low parts. */
395 if (rtx_equal_p (operands[0], operands[1]))
397 if (low[2] == const0_rtx)
398 pattern = 0, carry = 0;
399 else if (low[2] == constm1_rtx)
400 pattern = \"decl %0\";
402 pattern = \"subl2 %2,%0\";
406 if (low[2] == constm1_rtx)
407 pattern = \"decl %0\";
408 else if (low[2] == const0_rtx)
409 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
411 pattern = \"subl3 %2,%1,%0\";
414 output_asm_insn (pattern, low);
417 if (!rtx_equal_p (operands[0], operands[1]))
418 return \"movl %1,%0\;sbwc %2,%0\";
419 return \"sbwc %2,%0\";
420 /* %0 = %2 - %1 - C */
422 return get_insn_template (CODE_FOR_subsi3, insn);
425 ;;- Multiply instructions.
427 (define_insn "mul<mode>3"
428 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
429 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
430 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
433 mul<VAXfp:fsfx>2 %2,%0
434 mul<VAXfp:fsfx>2 %1,%0
435 mul<VAXfp:fsfx>3 %1,%2,%0")
437 (define_insn "mul<mode>3"
438 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
439 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
440 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
443 mul<VAXint:isfx>2 %2,%0
444 mul<VAXint:isfx>2 %1,%0
445 mul<VAXint:isfx>3 %1,%2,%0")
447 (define_insn "mulsidi3"
448 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
449 (mult:DI (sign_extend:DI
450 (match_operand:SI 1 "nonimmediate_operand" "g"))
452 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
457 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
459 (mult:DI (sign_extend:DI
460 (match_operand:SI 1 "nonimmediate_operand" "g"))
462 (match_operand:SI 2 "nonimmediate_operand" "g")))
463 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
467 ;; 'F' constraint means type CONST_DOUBLE
469 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
471 (mult:DI (sign_extend:DI
472 (match_operand:SI 1 "nonimmediate_operand" "g"))
474 (match_operand:SI 2 "nonimmediate_operand" "g")))
475 (match_operand:DI 3 "immediate_operand" "F")))]
476 "GET_CODE (operands[3]) == CONST_DOUBLE
477 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
480 if (CONST_DOUBLE_HIGH (operands[3]))
481 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
482 return \"emul %1,%2,%3,%0\";
485 ;;- Divide instructions.
487 (define_insn "div<mode>3"
488 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
489 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
490 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
493 div<VAXfp:fsfx>2 %2,%0
494 div<VAXfp:fsfx>3 %2,%1,%0")
496 (define_insn "div<mode>3"
497 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
498 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
499 (match_operand:VAXint 2 "general_operand" "g,g")))]
502 div<VAXint:isfx>2 %2,%0
503 div<VAXint:isfx>3 %2,%1,%0")
505 ;This is left out because it is very slow;
506 ;we are better off programming around the "lack" of this insn.
507 ;(define_insn "divmoddisi4"
508 ; [(set (match_operand:SI 0 "general_operand" "=g")
509 ; (div:SI (match_operand:DI 1 "general_operand" "g")
510 ; (match_operand:SI 2 "general_operand" "g")))
511 ; (set (match_operand:SI 3 "general_operand" "=g")
512 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
513 ; (match_operand:SI 2 "general_operand" "g")))]
515 ; "ediv %2,%1,%0,%3")
517 ;; Bit-and on the VAX is done with a clear-bits insn.
518 (define_expand "and<mode>3"
519 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
520 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
521 (match_operand:VAXint 2 "general_operand" "")))]
525 rtx op1 = operands[1];
527 /* If there is a constant argument, complement that one. */
528 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
530 operands[1] = operands[2];
535 if (GET_CODE (op1) == CONST_INT)
536 operands[1] = GEN_INT (~INTVAL (op1));
538 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
541 (define_insn "*and<mode>"
542 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
543 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "g,g"))
544 (match_operand:VAXint 2 "general_operand" "0,g")))]
547 bic<VAXint:isfx>2 %1,%0
548 bic<VAXint:isfx>3 %1,%2,%0")
550 ;; The following used to be needed because constant propagation can
551 ;; create them starting from the bic insn patterns above. This is no
552 ;; longer a problem. However, having these patterns allows optimization
553 ;; opportunities in combine.c.
555 (define_insn "*and<mode>_const_int"
556 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
557 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
558 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
561 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
562 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
565 ;;- Bit set instructions.
567 (define_insn "ior<mode>3"
568 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
569 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
570 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
573 bis<VAXint:isfx>2 %2,%0
574 bis<VAXint:isfx>2 %1,%0
575 bis<VAXint:isfx>3 %2,%1,%0")
577 ;;- xor instructions.
579 (define_insn "xor<mode>3"
580 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
581 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
582 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
585 xor<VAXint:isfx>2 %2,%0
586 xor<VAXint:isfx>2 %1,%0
587 xor<VAXint:isfx>3 %2,%1,%0")
590 (define_insn "neg<mode>2"
591 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
592 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
594 "mneg<VAXfp:fsfx> %1,%0")
596 (define_insn "neg<mode>2"
597 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
598 (neg:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
600 "mneg<VAXint:isfx> %1,%0")
602 (define_insn "one_cmpl<mode>2"
603 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
604 (not:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
606 "mcom<VAXint:isfx> %1,%0")
609 ;; Arithmetic right shift on the VAX works by negating the shift count,
610 ;; then emitting a right shift with the shift count negated. This means
611 ;; that all actual shift counts in the RTL will be positive. This
612 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
613 ;; which isn't valid.
614 (define_expand "ashrsi3"
615 [(set (match_operand:SI 0 "general_operand" "=g")
616 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
617 (match_operand:QI 2 "general_operand" "g")))]
621 if (GET_CODE (operands[2]) != CONST_INT)
622 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
626 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
627 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
628 (match_operand:QI 2 "const_int_operand" "n")))]
633 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
634 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
635 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
639 (define_insn "ashlsi3"
640 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
641 (ashift:SI (match_operand:SI 1 "general_operand" "g")
642 (match_operand:QI 2 "general_operand" "g")))]
646 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
647 return \"addl2 %0,%0\";
648 if (GET_CODE (operands[1]) == REG
649 && GET_CODE (operands[2]) == CONST_INT)
651 int i = INTVAL (operands[2]);
653 return \"addl3 %1,%1,%0\";
655 return \"moval 0[%1],%0\";
657 return \"movad 0[%1],%0\";
659 return \"ashl %2,%1,%0\";
662 ;; Arithmetic right shift on the VAX works by negating the shift count.
663 (define_expand "ashrdi3"
664 [(set (match_operand:DI 0 "general_operand" "=g")
665 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
666 (match_operand:QI 2 "general_operand" "g")))]
670 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
673 (define_insn "ashldi3"
674 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
675 (ashift:DI (match_operand:DI 1 "general_operand" "g")
676 (match_operand:QI 2 "general_operand" "g")))]
681 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
682 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
683 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
687 ;; We used to have expand_shift handle logical right shifts by using extzv,
688 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
689 ;; only machine with this kludge, it's better to just do this with a
690 ;; define_expand and remove that case from expand_shift.
692 (define_expand "lshrsi3"
694 (minus:QI (const_int 32)
696 (set (match_operand:SI 0 "general_operand" "=g")
697 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
699 (match_operand:SI 2 "register_operand" "g")))]
703 operands[3] = gen_reg_rtx (QImode);
704 operands[4] = gen_lowpart (QImode, operands[2]);
707 ;; Rotate right on the VAX works by negating the shift count.
708 (define_expand "rotrsi3"
709 [(set (match_operand:SI 0 "general_operand" "=g")
710 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
711 (match_operand:QI 2 "general_operand" "g")))]
715 if (GET_CODE (operands[2]) != CONST_INT)
716 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
719 (define_insn "rotlsi3"
720 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
721 (rotate:SI (match_operand:SI 1 "general_operand" "g")
722 (match_operand:QI 2 "general_operand" "g")))]
727 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
728 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
729 (match_operand:QI 2 "const_int_operand" "n")))]
734 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
735 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
736 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
740 ;This insn is probably slower than a multiply and an add.
742 ; [(set (match_operand:SI 0 "general_operand" "=g")
743 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
744 ; (match_operand:SI 2 "general_operand" "g"))
745 ; (match_operand:SI 3 "general_operand" "g")))]
747 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
749 ;; Special cases of bit-field insns which we should
750 ;; recognize in preference to the general case.
751 ;; These handle aligned 8-bit and 16-bit fields,
752 ;; which can usually be done with move instructions.
755 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
756 (match_operand:QI 1 "const_int_operand" "n")
757 (match_operand:SI 2 "const_int_operand" "n"))
758 (match_operand:SI 3 "general_operand" "g"))]
759 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
760 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
761 && (GET_CODE (operands[0]) == REG
762 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
765 if (REG_P (operands[0]))
767 if (INTVAL (operands[2]) != 0)
768 return \"insv %3,%2,%1,%0\";
772 = adjust_address (operands[0],
773 INTVAL (operands[1]) == 8 ? QImode : HImode,
774 INTVAL (operands[2]) / 8);
777 if (INTVAL (operands[1]) == 8)
778 return \"movb %3,%0\";
779 return \"movw %3,%0\";
783 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
784 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
785 (match_operand:QI 2 "const_int_operand" "n")
786 (match_operand:SI 3 "const_int_operand" "n")))]
787 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
788 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
789 && (GET_CODE (operands[1]) == REG
790 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
793 if (REG_P (operands[1]))
795 if (INTVAL (operands[3]) != 0)
796 return \"extzv %3,%2,%1,%0\";
800 = adjust_address (operands[1],
801 INTVAL (operands[2]) == 8 ? QImode : HImode,
802 INTVAL (operands[3]) / 8);
804 if (INTVAL (operands[2]) == 8)
805 return \"movzbl %1,%0\";
806 return \"movzwl %1,%0\";
810 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
811 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
812 (match_operand:QI 2 "const_int_operand" "n")
813 (match_operand:SI 3 "const_int_operand" "n")))]
814 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
815 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
816 && (GET_CODE (operands[1]) == REG
817 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
820 if (REG_P (operands[1]))
822 if (INTVAL (operands[3]) != 0)
823 return \"extv %3,%2,%1,%0\";
827 = adjust_address (operands[1],
828 INTVAL (operands[2]) == 8 ? QImode : HImode,
829 INTVAL (operands[3]) / 8);
831 if (INTVAL (operands[2]) == 8)
832 return \"cvtbl %1,%0\";
833 return \"cvtwl %1,%0\";
836 ;; Register-only SImode cases of bit-field insns.
841 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
842 (match_operand:QI 1 "general_operand" "g")
843 (match_operand:SI 2 "general_operand" "g"))
844 (match_operand:SI 3 "general_operand" "g")))]
851 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
852 (match_operand:QI 1 "general_operand" "g")
853 (match_operand:SI 2 "general_operand" "g"))
854 (match_operand:SI 3 "general_operand" "g")))]
858 ;; When the field position and size are constant and the destination
859 ;; is a register, extv and extzv are much slower than a rotate followed
860 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
861 ;; anyway, we can't allow immediate values for the primary source operand.
864 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
865 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
866 (match_operand:QI 2 "general_operand" "g")
867 (match_operand:SI 3 "general_operand" "g")))]
871 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
872 || GET_CODE (operands[0]) != REG
873 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
874 return \"extv %3,%2,%1,%0\";
875 if (INTVAL (operands[2]) == 8)
876 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
877 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
881 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
882 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
883 (match_operand:QI 2 "general_operand" "g")
884 (match_operand:SI 3 "general_operand" "g")))]
888 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
889 || GET_CODE (operands[0]) != REG)
890 return \"extzv %3,%2,%1,%0\";
891 if (INTVAL (operands[2]) == 8)
892 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
893 if (INTVAL (operands[2]) == 16)
894 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
895 if (INTVAL (operands[3]) & 31)
896 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
897 if (rtx_equal_p (operands[0], operands[1]))
898 return \"bicl2 %M2,%0\";
899 return \"bicl3 %M2,%1,%0\";
902 ;; Non-register cases.
903 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
904 ;; don't match these (and therefore match the cases above instead).
909 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
910 (match_operand:QI 1 "general_operand" "g")
911 (match_operand:SI 2 "general_operand" "g"))
912 (match_operand:SI 3 "general_operand" "g")))]
919 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
920 (match_operand:QI 1 "general_operand" "g")
921 (match_operand:SI 2 "general_operand" "g"))
922 (match_operand:SI 3 "general_operand" "g")))]
927 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
928 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
929 (match_operand:QI 2 "general_operand" "g")
930 (match_operand:SI 3 "general_operand" "g")))]
934 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
935 || GET_CODE (operands[3]) != CONST_INT
936 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
937 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
938 || side_effects_p (operands[1])
939 || (GET_CODE (operands[1]) == MEM
940 && mode_dependent_address_p (XEXP (operands[1], 0))))
941 return \"extv %3,%2,%1,%0\";
942 if (INTVAL (operands[2]) == 8)
943 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
944 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
947 (define_expand "extzv"
948 [(set (match_operand:SI 0 "general_operand" "")
949 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
950 (match_operand:QI 2 "general_operand" "")
951 (match_operand:SI 3 "general_operand" "")))]
956 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
957 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
958 (match_operand:QI 2 "general_operand" "g")
959 (match_operand:SI 3 "general_operand" "g")))]
963 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
964 || GET_CODE (operands[3]) != CONST_INT
965 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
966 || side_effects_p (operands[1])
967 || (GET_CODE (operands[1]) == MEM
968 && mode_dependent_address_p (XEXP (operands[1], 0))))
969 return \"extzv %3,%2,%1,%0\";
970 if (INTVAL (operands[2]) == 8)
971 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
972 if (INTVAL (operands[2]) == 16)
973 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
974 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
977 (define_expand "insv"
978 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
979 (match_operand:QI 1 "general_operand" "")
980 (match_operand:SI 2 "general_operand" ""))
981 (match_operand:SI 3 "general_operand" ""))]
986 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
987 (match_operand:QI 1 "general_operand" "g")
988 (match_operand:SI 2 "general_operand" "g"))
989 (match_operand:SI 3 "general_operand" "g"))]
994 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
995 (match_operand:QI 1 "general_operand" "g")
996 (match_operand:SI 2 "general_operand" "g"))
997 (match_operand:SI 3 "general_operand" "g"))]
1001 ;; Unconditional jump
1004 (label_ref (match_operand 0 "" "")))]
1008 ;; Conditional jumps
1009 (define_code_macro any_cond [eq ne gt lt gtu ltu ge le geu leu])
1011 (define_insn "b<code>"
1013 (if_then_else (any_cond (cc0)
1015 (label_ref (match_operand 0 "" ""))
1018 "* return vax_output_conditional_branch (<CODE>);")
1020 ;; Recognize reversed jumps.
1023 (if_then_else (match_operator 0 "comparison_operator"
1027 (label_ref (match_operand 1 "" ""))))]
1029 "j%C0 %l1") ; %C0 negates condition
1031 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1032 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1033 ;; memory, we use QImode in the insn. So we can't use those instructions
1034 ;; for mode-dependent addresses.
1039 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1041 (match_operand:SI 1 "general_operand" "I,g"))
1043 (label_ref (match_operand 2 "" ""))
1053 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1055 (match_operand:SI 1 "general_operand" "I,g"))
1057 (label_ref (match_operand 2 "" ""))
1067 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1069 (match_operand:SI 1 "general_operand" "I,g"))
1071 (label_ref (match_operand 2 "" ""))
1081 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1083 (match_operand:SI 1 "general_operand" "I,g"))
1085 (label_ref (match_operand 2 "" ""))
1092 ;; Subtract-and-jump and Add-and-jump insns.
1093 ;; These are not used when output is for the Unix assembler
1094 ;; because it does not know how to modify them to reach far.
1096 ;; Normal sob insns.
1101 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1104 (label_ref (match_operand 1 "" ""))
1107 (plus:SI (match_dup 0)
1115 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1118 (label_ref (match_operand 1 "" ""))
1121 (plus:SI (match_dup 0)
1126 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1130 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1132 (match_operand:SI 1 "general_operand" "g"))
1133 (label_ref (match_operand 2 "" ""))
1136 (plus:SI (match_dup 0)
1139 "jaoblss %1,%0,%l2")
1144 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1145 (match_operand:SI 1 "general_operand" "g"))
1146 (label_ref (match_operand 2 "" ""))
1149 (plus:SI (match_dup 0)
1151 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1152 "jaoblss %P1,%0,%l2")
1157 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1159 (match_operand:SI 1 "general_operand" "g"))
1160 (label_ref (match_operand 2 "" ""))
1163 (plus:SI (match_dup 0)
1166 "jaobleq %1,%0,%l2")
1171 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1172 (match_operand:SI 1 "general_operand" "g"))
1173 (label_ref (match_operand 2 "" ""))
1176 (plus:SI (match_dup 0)
1178 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1179 "jaobleq %P1,%0,%l2")
1181 ;; Something like a sob insn, but compares against -1.
1182 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1187 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1189 (label_ref (match_operand 1 "" ""))
1192 (plus:SI (match_dup 0)
1195 "decl %0\;jgequ %l1")
1197 (define_expand "call_pop"
1198 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1199 (match_operand:SI 1 "const_int_operand" ""))
1201 (plus:SI (reg:SI 14)
1202 (match_operand:SI 3 "immediate_operand" "")))])]
1205 if (INTVAL (operands[3]) > 255 * 4 || INTVAL (operands[3]) % 4)
1208 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1209 during EH unwinding. We must include the argument count pushed by
1210 the calls instruction. */
1211 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1214 (define_insn "*call_pop"
1215 [(call (match_operand:QI 0 "memory_operand" "m")
1216 (match_operand:SI 1 "const_int_operand" "n"))
1217 (set (reg:SI 14) (plus:SI (reg:SI 14)
1218 (match_operand:SI 2 "immediate_operand" "i")))]
1221 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1222 return "calls %1,%0";
1225 (define_expand "call_value_pop"
1226 [(parallel [(set (match_operand 0 "" "")
1227 (call (match_operand:QI 1 "memory_operand" "")
1228 (match_operand:SI 2 "const_int_operand" "")))
1230 (plus:SI (reg:SI 14)
1231 (match_operand:SI 4 "immediate_operand" "")))])]
1234 if (INTVAL (operands[4]) > 255 * 4 || INTVAL (operands[4]) % 4)
1237 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1238 during EH unwinding. We must include the argument count pushed by
1239 the calls instruction. */
1240 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1243 (define_insn "*call_value_pop"
1244 [(set (match_operand 0 "" "")
1245 (call (match_operand:QI 1 "memory_operand" "m")
1246 (match_operand:SI 2 "const_int_operand" "n")))
1247 (set (reg:SI 14) (plus:SI (reg:SI 14)
1248 (match_operand:SI 3 "immediate_operand" "i")))]
1252 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1253 return \"calls %2,%1\";
1256 (define_expand "call"
1257 [(call (match_operand:QI 0 "memory_operand" "")
1258 (match_operand:SI 1 "const_int_operand" ""))]
1262 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1263 during EH unwinding. We must include the argument count pushed by
1264 the calls instruction. */
1265 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1268 (define_insn "*call"
1269 [(call (match_operand:QI 0 "memory_operand" "m")
1270 (match_operand:SI 1 "const_int_operand" ""))]
1274 (define_expand "call_value"
1275 [(set (match_operand 0 "" "")
1276 (call (match_operand:QI 1 "memory_operand" "")
1277 (match_operand:SI 2 "const_int_operand" "")))]
1281 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1282 during EH unwinding. We must include the argument count pushed by
1283 the calls instruction. */
1284 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1287 (define_insn "*call_value"
1288 [(set (match_operand 0 "" "")
1289 (call (match_operand:QI 1 "memory_operand" "m")
1290 (match_operand:SI 2 "const_int_operand" "")))]
1294 ;; Call subroutine returning any type.
1296 (define_expand "untyped_call"
1297 [(parallel [(call (match_operand 0 "" "")
1299 (match_operand 1 "" "")
1300 (match_operand 2 "" "")])]
1306 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1308 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1310 rtx set = XVECEXP (operands[2], 0, i);
1311 emit_move_insn (SET_DEST (set), SET_SRC (set));
1314 /* The optimizer does not know that the call sets the function value
1315 registers we stored in the result block. We avoid problems by
1316 claiming that all hard registers are used and clobbered at this
1318 emit_insn (gen_blockage ());
1323 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1324 ;; all of memory. This blocks insns from being moved across this point.
1326 (define_insn "blockage"
1327 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1331 (define_insn "return"
1336 (define_expand "epilogue"
1341 emit_jump_insn (gen_return ());
1350 ;; This had a wider constraint once, and it had trouble.
1351 ;; If you are tempted to try `g', please don't--it's not worth
1352 ;; the risk we will reopen the same bug.
1353 (define_insn "indirect_jump"
1354 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1358 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1359 ;; and pass the first 4 along to the casesi1 pattern that really does
1360 ;; the actual casesi work. We emit a jump here to the default label
1361 ;; _before_ the casesi so that we can be sure that the casesi never
1363 ;; This is suboptimal perhaps, but so is much of the rest of this
1364 ;; machine description. For what it's worth, HPPA uses the same trick.
1366 ;; operand 0 is index
1367 ;; operand 1 is the minimum bound (a const_int)
1368 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1369 ;; operand 3 is CODE_LABEL for the table;
1370 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1373 ;; i = index - minimum_bound
1374 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
1375 ;; casesi (i, 0, table);
1377 (define_expand "casesi"
1378 [(match_operand:SI 0 "general_operand" "")
1379 (match_operand:SI 1 "general_operand" "")
1380 (match_operand:SI 2 "general_operand" "")
1381 (match_operand 3 "" "")
1382 (match_operand 4 "" "")]
1385 /* i = index - minimum_bound;
1386 But only if the lower bound is not already zero. */
1387 if (operands[1] != const0_rtx)
1389 rtx index = gen_reg_rtx (SImode);
1390 emit_insn (gen_addsi3 (index,
1392 GEN_INT (-INTVAL (operands[1]))));
1393 operands[0] = index;
1396 /* if (i > (maximum_bound - minimum_bound + 1) goto default; */
1397 emit_insn (gen_cmpsi (operands[0], operands[2]));
1398 emit_jump_insn (gen_bgtu (operands[4]));
1400 /* casesi (i, 0, table); */
1401 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1405 ;; This insn is a bit of a lier. It actually falls through if no case
1406 ;; matches. But, we prevent that from ever happening by emitting a jump
1407 ;; before this, see the define_expand above.
1408 (define_insn "casesi1"
1409 [(match_operand:SI 1 "const_int_operand" "n")
1411 (plus:SI (sign_extend:SI
1412 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "g")
1415 (label_ref:SI (match_operand 2 "" ""))))]
1419 ;;- load or push effective address
1420 ;; These come after the move and add/sub patterns
1421 ;; because we don't want pushl $1 turned into pushad 1.
1422 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1424 ;; It does not work to use constraints to distinguish pushes from moves,
1425 ;; because < matches any autodecrement, not just a push.
1428 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1429 (match_operand:QI 1 "address_operand" "p"))]
1433 if (push_operand (operands[0], SImode))
1434 return \"pushab %a1\";
1436 return \"movab %a1,%0\";
1440 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1441 (match_operand:HI 1 "address_operand" "p"))]
1445 if (push_operand (operands[0], SImode))
1446 return \"pushaw %a1\";
1448 return \"movaw %a1,%0\";
1452 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1453 (match_operand:SI 1 "address_operand" "p"))]
1457 if (push_operand (operands[0], SImode))
1458 return \"pushal %a1\";
1460 return \"moval %a1,%0\";
1464 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1465 (match_operand:DI 1 "address_operand" "p"))]
1469 if (push_operand (operands[0], SImode))
1470 return \"pushaq %a1\";
1472 return \"movaq %a1,%0\";
1476 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1477 (match_operand:SF 1 "address_operand" "p"))]
1481 if (push_operand (operands[0], SImode))
1482 return \"pushaf %a1\";
1484 return \"movaf %a1,%0\";
1488 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1489 (match_operand:DF 1 "address_operand" "p"))]
1493 if (push_operand (operands[0], SImode))
1494 return \"pushad %a1\";
1496 return \"movad %a1,%0\";
1499 ;; These used to be peepholes, but it is more straightforward to do them
1500 ;; as single insns. However, we must force the output to be a register
1501 ;; if it is not an offsettable address so that we know that we can assign
1504 ;; If we had a good way of evaluating the relative costs, these could be
1505 ;; machine-independent.
1507 ;; Optimize extzv ...,z; andl2 ...,z
1508 ;; or ashl ...,z; andl2 ...,z
1509 ;; with other operands constant. This is what the combiner converts the
1510 ;; above sequences to before attempting to recognize the new insn.
1513 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1514 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1515 (match_operand:QI 2 "const_int_operand" "n"))
1516 (match_operand:SI 3 "const_int_operand" "n")))]
1517 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1520 unsigned long mask1 = INTVAL (operands[3]);
1521 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1523 if ((mask1 & mask2) != mask1)
1524 operands[3] = GEN_INT (mask1 & mask2);
1526 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1529 ;; left-shift and mask
1530 ;; The only case where `ashl' is better is if the mask only turns off
1531 ;; bits that the ashl would anyways, in which case it should have been
1535 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1536 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
1537 (match_operand:QI 2 "const_int_operand" "n"))
1538 (match_operand:SI 3 "const_int_operand" "n")))]
1543 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1544 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1547 ;; Instruction sequence to sync the VAX instruction stream.
1548 (define_insn "sync_istream"
1549 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1551 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")