1 /* Subroutines for insn-output.c for Vax.
2 Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
33 #include "insn-attr.h"
39 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
42 split_quadword_operands (operands, low, n)
44 int n ATTRIBUTE_UNUSED;
49 low[0] = low[1] = low[2] = 0;
50 for (i = 0; i < 3; i++)
53 /* it's already been figured out */;
54 else if (GET_CODE (operands[i]) == MEM
55 && (GET_CODE (XEXP (operands[i], 0)) == POST_INC))
57 rtx addr = XEXP (operands[i], 0);
58 operands[i] = low[i] = gen_rtx_MEM (SImode, addr);
59 if (which_alternative == 0 && i == 0)
61 addr = XEXP (operands[i], 0);
62 operands[i+1] = low[i+1] = gen_rtx_MEM (SImode, addr);
67 low[i] = operand_subword (operands[i], 0, 0, DImode);
68 operands[i] = operand_subword (operands[i], 1, 0, DImode);
74 print_operand_address (file, addr)
78 register rtx reg1, breg, ireg;
82 switch (GET_CODE (addr))
86 addr = XEXP (addr, 0);
90 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
94 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
98 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
102 /* There can be either two or three things added here. One must be a
103 REG. One can be either a REG or a MULT of a REG and an appropriate
104 constant, and the third can only be a constant or a MEM.
106 We get these two or three things and put the constant or MEM in
107 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
108 a register and can't tell yet if it is a base or index register,
111 reg1 = 0; ireg = 0; breg = 0; offset = 0;
113 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
114 || GET_CODE (XEXP (addr, 0)) == MEM)
116 offset = XEXP (addr, 0);
117 addr = XEXP (addr, 1);
119 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
120 || GET_CODE (XEXP (addr, 1)) == MEM)
122 offset = XEXP (addr, 1);
123 addr = XEXP (addr, 0);
125 else if (GET_CODE (XEXP (addr, 1)) == MULT)
127 ireg = XEXP (addr, 1);
128 addr = XEXP (addr, 0);
130 else if (GET_CODE (XEXP (addr, 0)) == MULT)
132 ireg = XEXP (addr, 0);
133 addr = XEXP (addr, 1);
135 else if (GET_CODE (XEXP (addr, 1)) == REG)
137 reg1 = XEXP (addr, 1);
138 addr = XEXP (addr, 0);
140 else if (GET_CODE (XEXP (addr, 0)) == REG)
142 reg1 = XEXP (addr, 0);
143 addr = XEXP (addr, 1);
148 if (GET_CODE (addr) == REG)
155 else if (GET_CODE (addr) == MULT)
157 else if (GET_CODE (addr) == PLUS)
159 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
160 || GET_CODE (XEXP (addr, 0)) == MEM)
164 if (GET_CODE (offset) == CONST_INT)
165 offset = plus_constant (XEXP (addr, 0), INTVAL (offset));
166 else if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
167 offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
171 offset = XEXP (addr, 0);
173 else if (GET_CODE (XEXP (addr, 0)) == REG)
176 ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
178 reg1 = XEXP (addr, 0);
180 else if (GET_CODE (XEXP (addr, 0)) == MULT)
184 ireg = XEXP (addr, 0);
189 if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
190 || GET_CODE (XEXP (addr, 1)) == MEM)
194 if (GET_CODE (offset) == CONST_INT)
195 offset = plus_constant (XEXP (addr, 1), INTVAL (offset));
196 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
197 offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
201 offset = XEXP (addr, 1);
203 else if (GET_CODE (XEXP (addr, 1)) == REG)
206 ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
208 reg1 = XEXP (addr, 1);
210 else if (GET_CODE (XEXP (addr, 1)) == MULT)
214 ireg = XEXP (addr, 1);
222 /* If REG1 is non-zero, figure out if it is a base or index register. */
225 if (breg != 0 || (offset && GET_CODE (offset) == MEM))
236 output_address (offset);
239 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
243 if (GET_CODE (ireg) == MULT)
244 ireg = XEXP (ireg, 0);
245 if (GET_CODE (ireg) != REG)
247 fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
252 output_addr_const (file, addr);
260 switch (GET_CODE (op))
292 register enum machine_mode mode;
293 #if HOST_FLOAT_FORMAT == VAX_FLOAT_FORMAT
295 union {double d; int i[2];} val;
298 if (GET_CODE (c) != CONST_DOUBLE)
303 if (c == const_tiny_rtx[(int) mode][0]
304 || c == const_tiny_rtx[(int) mode][1]
305 || c == const_tiny_rtx[(int) mode][2])
308 #if HOST_FLOAT_FORMAT == VAX_FLOAT_FORMAT
310 val.i[0] = CONST_DOUBLE_LOW (c);
311 val.i[1] = CONST_DOUBLE_HIGH (c);
313 for (i = 0; i < 7; i ++)
314 if (val.d == 1 << i || val.d == 1 / (1 << i))
321 /* Return the cost in cycles of a memory address, relative to register
324 Each of the following adds the indicated number of cycles:
328 1 - indexing and/or offset(register)
333 vax_address_cost (addr)
336 int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
337 rtx plus_op0 = 0, plus_op1 = 0;
339 switch (GET_CODE (addr))
349 indexed = 1; /* 2 on VAX 2 */
352 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
354 offset = (unsigned)(INTVAL(addr)+128) > 256;
358 offset = 1; /* 2 on VAX 2 */
360 case LABEL_REF: /* this is probably a byte offset from the pc */
366 plus_op1 = XEXP (addr, 0);
368 plus_op0 = XEXP (addr, 0);
369 addr = XEXP (addr, 1);
372 indir = 2; /* 3 on VAX 2 */
373 addr = XEXP (addr, 0);
379 /* Up to 3 things can be added in an address. They are stored in
380 plus_op0, plus_op1, and addr. */
394 /* Indexing and register+offset can both be used (except on a VAX 2)
395 without increasing execution time over either one alone. */
396 if (reg && indexed && offset)
397 return reg + indir + offset + predec;
398 return reg + indexed + indir + offset + predec;
402 /* Cost of an expression on a VAX. This version has costs tuned for the
403 CVAX chip (found in the VAX 3 series) with comments for variations on
410 register enum rtx_code code = GET_CODE (x);
411 enum machine_mode mode = GET_MODE (x);
413 int i = 0; /* may be modified in switch */
414 const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */
426 c = 16; /* 4 on VAX 9000 */
429 c = 9; /* 4 on VAX 9000, 12 on VAX 2 */
432 c = 16; /* 6 on VAX 9000, 28 on VAX 2 */
437 c = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
448 c = 30; /* highly variable */
449 else if (mode == DFmode)
450 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
453 c = 11; /* 25 on VAX 2 */
462 c = 6 + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode);
466 c = 7; /* 17 on VAX 2 */
474 c = 10; /* 6 on VAX 9000 */
478 c = 6; /* 5 on VAX 2, 4 on VAX 9000 */
479 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
480 fmt = "e"; /* all constant rotate counts are short */
483 /* Check for small negative integer operand: subl2 can be used with
484 a short positive constant instead. */
485 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
486 if ((unsigned)(INTVAL (XEXP (x, 1)) + 63) < 127)
489 c = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
495 /* AND is special because the first operand is complemented. */
497 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
499 if ((unsigned)~INTVAL (XEXP (x, 0)) > 63)
508 else if (mode == SFmode)
510 else if (mode == DImode)
519 if (mode == DImode || mode == DFmode)
520 c = 5; /* 7 on VAX 2 */
522 c = 3; /* 4 on VAX 2 */
524 if (GET_CODE (x) == REG || GET_CODE (x) == POST_INC)
526 return c + vax_address_cost (x);
533 /* Now look inside the expression. Operands which are not registers or
534 short constants add to the cost.
536 FMT and I may have been adjusted in the switch above for instructions
537 which require special handling */
539 while (*fmt++ == 'e')
541 register rtx op = XEXP (x, i++);
542 code = GET_CODE (op);
544 /* A NOT is likely to be found as the first operand of an AND
545 (in which case the relevant cost is of the operand inside
546 the not) and not likely to be found anywhere else. */
548 op = XEXP (op, 0), code = GET_CODE (op);
553 if ((unsigned)INTVAL (op) > 63 && GET_MODE (x) != QImode)
554 c += 1; /* 2 on VAX 2 */
559 c += 1; /* 2 on VAX 2 */
562 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
564 /* Registers are faster than floating point constants -- even
565 those constants which can be encoded in a single byte. */
566 if (vax_float_literal (op))
569 c += (GET_MODE (x) == DFmode) ? 3 : 2;
573 if (CONST_DOUBLE_HIGH (op) != 0
574 || (unsigned)CONST_DOUBLE_LOW (op) > 63)
579 c += 1; /* 2 on VAX 2 */
580 if (GET_CODE (XEXP (op, 0)) != REG)
581 c += vax_address_cost (XEXP (op, 0));
594 /* Check a `double' value for validity for a particular machine mode. */
596 static const char *const float_strings[] =
598 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
599 "-1.70141173319264430e+38",
600 "2.93873587705571877e-39", /* 2^-128 */
601 "-2.93873587705571877e-39"
604 static REAL_VALUE_TYPE float_values[4];
606 static int inited_float_values = 0;
610 check_float_value (mode, d, overflow)
611 enum machine_mode mode;
615 if (inited_float_values == 0)
618 for (i = 0; i < 4; i++)
620 float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
623 inited_float_values = 1;
628 memcpy (d, &float_values[0], sizeof (REAL_VALUE_TYPE));
632 if ((mode) == SFmode)
635 memcpy (&r, d, sizeof (REAL_VALUE_TYPE));
636 if (REAL_VALUES_LESS (float_values[0], r))
638 memcpy (d, &float_values[0], sizeof (REAL_VALUE_TYPE));
641 else if (REAL_VALUES_LESS (r, float_values[1]))
643 memcpy (d, &float_values[1], sizeof (REAL_VALUE_TYPE));
646 else if (REAL_VALUES_LESS (dconst0, r)
647 && REAL_VALUES_LESS (r, float_values[2]))
649 memcpy (d, &dconst0, sizeof (REAL_VALUE_TYPE));
652 else if (REAL_VALUES_LESS (r, dconst0)
653 && REAL_VALUES_LESS (float_values[3], r))
655 memcpy (d, &dconst0, sizeof (REAL_VALUE_TYPE));
664 /* Additional support code for VMS target. */
666 /* Linked list of all externals that are to be emitted when optimizing
667 for the global pointer if they haven't been declared by the end of
668 the program with an appropriate .comm or initialization. */
672 struct extern_list *next; /* next external */
673 const char *name; /* name of the external */
674 int size; /* external's actual size */
675 int in_const; /* section type flag */
676 } *extern_head = 0, *pending_head = 0;
678 /* Check whether NAME is already on the external definition list. If not,
679 add it to either that list or the pending definition list. */
682 vms_check_external (decl, name, pending)
687 register struct extern_list *p, *p0;
689 for (p = extern_head; p; p = p->next)
690 if (!strcmp (p->name, name))
693 for (p = pending_head, p0 = 0; p; p0 = p, p = p->next)
694 if (!strcmp (p->name, name))
699 /* Was pending, but has now been defined; move it to other list. */
700 if (p == pending_head)
701 pending_head = p->next;
704 p->next = extern_head;
709 /* Not previously seen; create a new list entry. */
710 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
715 /* Save the size and section type and link to `pending' list. */
716 p->size = (DECL_SIZE (decl) == 0) ? 0 :
717 TREE_INT_CST_LOW (size_binop (CEIL_DIV_EXPR, DECL_SIZE (decl),
718 size_int (BITS_PER_UNIT)));
719 p->in_const = (TREE_READONLY (decl) && ! TREE_THIS_VOLATILE (decl));
721 p->next = pending_head;
726 /* Size and section type don't matter; link to `declared' list. */
727 p->size = p->in_const = 0; /* arbitrary init */
729 p->next = extern_head;
736 vms_flush_pending_externals (file)
739 register struct extern_list *p;
743 /* Move next pending declaration to the "done" list. */
745 pending_head = p->next;
746 p->next = extern_head;
749 /* Now output the actual declaration. */
754 fputs (".comm ", file);
755 assemble_name (file, p->name);
756 fprintf (file, ",%d\n", p->size);
759 #endif /* VMS_TARGET */
762 /* Additional support code for VMS host. */
764 #ifdef QSORT_WORKAROUND
766 Do not use VAXCRTL's qsort() due to a severe bug: once you've
767 sorted something which has a size that's an exact multiple of 4
768 and is longword aligned, you cannot safely sort anything which
769 is either not a multiple of 4 in size or not longword aligned.
770 A static "move-by-longword" optimization flag inside qsort() is
771 never reset. This is known of affect VMS V4.6 through VMS V5.5-1,
772 and was finally fixed in VMS V5.5-2.
774 In this work-around an insertion sort is used for simplicity.
775 The qsort code from glibc should probably be used instead.
778 not_qsort (array, count, size, compare)
780 unsigned count, size;
784 if (size == sizeof (short))
787 register short *next, *prev;
788 short tmp, *base = array;
790 for (next = base, i = count - 1; i > 0; i--)
793 if ((*compare)(next, prev) < 0)
796 do *(prev + 1) = *prev;
797 while (--prev >= base ? (*compare)(&tmp, prev) < 0 : 0);
802 else if (size == sizeof (long))
805 register long *next, *prev;
806 long tmp, *base = array;
808 for (next = base, i = count - 1; i > 0; i--)
811 if ((*compare)(next, prev) < 0)
814 do *(prev + 1) = *prev;
815 while (--prev >= base ? (*compare)(&tmp, prev) < 0 : 0);
820 else /* arbitrary size */
823 register char *next, *prev, *tmp = alloca (size), *base = array;
825 for (next = base, i = count - 1; i > 0; i--)
826 { /* count-1 forward iterations */
827 prev = next, next += size; /* increment front pointer */
828 if ((*compare)(next, prev) < 0)
829 { /* found element out of order; move others up then re-insert */
830 memcpy (tmp, next, size); /* save smaller element */
831 do { memcpy (prev + size, prev, size); /* move larger elem. up */
832 prev -= size; /* decrement back pointer */
833 } while (prev >= base ? (*compare)(tmp, prev) < 0 : 0);
834 memcpy (prev + size, tmp, size); /* restore small element */
844 #endif /* QSORT_WORKAROUND */