1 ;; Predicate definitions for CELL SPU
2 ;; Copyright (C) 2006 Free Software Foundation, Inc.
4 ;; This file is free software; you can redistribute it and/or modify it under
5 ;; the terms of the GNU General Public License as published by the Free
6 ;; Software Foundation; either version 2 of the License, or (at your option)
9 ;; This file is distributed in the hope that it will be useful, but WITHOUT
10 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 ;; You should have received a copy of the GNU General Public License
15 ;; along with this file; see the file COPYING. If not, write to the Free
16 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
19 (define_predicate "spu_reg_operand"
20 (and (match_operand 0 "register_operand")
21 (ior (not (match_code "subreg"))
22 (match_test "valid_subreg (op)"))))
24 (define_predicate "spu_nonimm_operand"
25 (and (match_operand 0 "nonimmediate_operand")
26 (ior (not (match_code "subreg"))
27 (match_test "valid_subreg (op)"))))
29 (define_predicate "spu_nonmem_operand"
30 (and (match_operand 0 "nonmemory_operand")
31 (ior (not (match_code "subreg"))
32 (match_test "valid_subreg (op)"))))
34 (define_predicate "spu_mem_operand"
35 (and (match_operand 0 "memory_operand")
36 (match_test "reload_in_progress || reload_completed || aligned_mem_p (op)")))
38 (define_predicate "call_operand"
39 (and (match_code "mem")
40 (match_test "(!TARGET_LARGE_MEM && satisfies_constraint_S (op))
41 || (satisfies_constraint_R (op)
42 && REGNO (XEXP (op, 0)) != FRAME_POINTER_REGNUM
43 && REGNO (XEXP (op, 0)) != ARG_POINTER_REGNUM
44 && (REGNO (XEXP (op, 0)) < FIRST_PSEUDO_REGISTER
45 || REGNO (XEXP (op, 0)) > LAST_VIRTUAL_REGISTER))")))
47 (define_predicate "vec_imm_operand"
48 (and (match_code "const_int,const_double,const_vector")
49 (match_test "spu_legitimate_constant_p (op)")))
51 (define_predicate "spu_arith_operand"
52 (match_code "reg,subreg,const_int,const_vector")
54 if (spu_reg_operand (op, mode))
56 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
57 return arith_immediate_p (op, mode, -0x200, 0x1ff);
61 (define_predicate "spu_logical_operand"
62 (match_code "reg,subreg,const_int,const_double,const_vector")
64 if (spu_reg_operand (op, mode))
66 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
67 || GET_CODE (op) == CONST_VECTOR)
68 return logical_immediate_p (op, mode);
72 (define_predicate "spu_ior_operand"
73 (match_code "reg,subreg,const_int,const_double,const_vector")
75 if (spu_reg_operand (op, mode))
77 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
78 || GET_CODE (op) == CONST_VECTOR)
79 return logical_immediate_p (op, mode)
80 || iohl_immediate_p (op, mode);
84 (define_predicate "spu_shift_operand"
85 (match_code "reg,subreg,const_int,const_vector")
87 if (spu_reg_operand (op, mode))
89 if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
90 return arith_immediate_p (op, mode, -0x40, 0x3f);
94 ;; Return 1 if OP is a comparison operation that is valid for a branch insn.
95 ;; We only check the opcode against the mode of the register value here.
96 (define_predicate "branch_comparison_operator"
97 (and (match_code "eq,ne")
98 (ior (match_test "GET_MODE (XEXP (op, 0)) == HImode")
99 (match_test "GET_MODE (XEXP (op, 0)) == SImode"))))