1 ;; GCC machine description for SPARC synchronization instructions.
2 ;; Copyright (C) 2005, 2007, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_mode_iterator I12MODE [QI HI])
22 (define_mode_iterator I24MODE [HI SI])
23 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
24 (define_mode_attr modesuffix [(SI "") (DI "x")])
26 (define_expand "mem_thread_fence"
27 [(match_operand:SI 0 "const_int_operand")]
28 "TARGET_V8 || TARGET_V9"
30 enum memmodel model = (enum memmodel) INTVAL (operands[0]);
31 sparc_emit_membar_for_model (model, 3, 3);
35 (define_expand "memory_barrier"
37 "TARGET_V8 || TARGET_V9"
39 sparc_emit_membar_for_model (MEMMODEL_SEQ_CST, 3, 3);
43 (define_expand "membar"
45 (unspec:BLK [(match_dup 1)
46 (match_operand:SI 0 "const_int_operand")]
48 "TARGET_V8 || TARGET_V9"
50 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
51 MEM_VOLATILE_P (operands[1]) = 1;
54 ;; A compiler-only memory barrier. Generic code, when checking for the
55 ;; existance of various named patterns, uses asm("":::"memory") when we
56 ;; don't need an actual instruction. Here, it's easiest to pretend that
57 ;; membar 0 is such a barrier. Further, this gives us a nice hook to
58 ;; ignore all such barriers on Sparc V7.
59 (define_insn "*membar_empty"
60 [(set (match_operand:BLK 0 "" "")
61 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
65 [(set_attr "type" "multi")
66 (set_attr "length" "0")])
68 ;; For V8, STBAR is exactly membar #StoreStore, by definition.
69 (define_insn "*membar_storestore"
70 [(set (match_operand:BLK 0 "" "")
71 (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
74 [(set_attr "type" "multi")])
76 ;; For V8, LDSTUB has the effect of membar #StoreLoad
77 (define_insn "*membar_storeload"
78 [(set (match_operand:BLK 0 "" "")
79 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
81 "ldstub\t[%%sp-1], %%g0"
82 [(set_attr "type" "multi")])
84 ;; Put the two together, in combination with the fact that V8 implements PSO
85 ;; as its weakest memory model, means a full barrier. Match all remaining
86 ;; instances of the membar pattern for Sparc V8.
87 (define_insn "*membar_v8"
88 [(set (match_operand:BLK 0 "" "")
89 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
92 "stbar\n\tldstub\t[%%sp-1], %%g0"
93 [(set_attr "type" "multi")
94 (set_attr "length" "2")])
96 ;; For V9, we have the full membar instruction.
97 (define_insn "*membar"
98 [(set (match_operand:BLK 0 "" "")
99 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
103 [(set_attr "type" "multi")])
105 (define_expand "atomic_load<mode>"
106 [(match_operand:I 0 "register_operand" "")
107 (match_operand:I 1 "memory_operand" "")
108 (match_operand:SI 2 "const_int_operand" "")]
111 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
113 sparc_emit_membar_for_model (model, 1, 1);
115 if (TARGET_ARCH64 || <MODE>mode != DImode)
116 emit_move_insn (operands[0], operands[1]);
118 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
120 sparc_emit_membar_for_model (model, 1, 2);
124 (define_insn "atomic_loaddi_1"
125 [(set (match_operand:DI 0 "register_operand" "=U,?*f")
126 (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
130 [(set_attr "type" "load,fpload")])
132 (define_expand "atomic_store<mode>"
133 [(match_operand:I 0 "register_operand" "")
134 (match_operand:I 1 "memory_operand" "")
135 (match_operand:SI 2 "const_int_operand" "")]
138 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
140 sparc_emit_membar_for_model (model, 2, 1);
142 if (TARGET_ARCH64 || <MODE>mode != DImode)
143 emit_move_insn (operands[0], operands[1]);
145 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
147 sparc_emit_membar_for_model (model, 2, 2);
151 (define_insn "atomic_storedi_1"
152 [(set (match_operand:DI 0 "memory_operand" "=m,m,m")
154 [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
161 [(set_attr "type" "store,store,fpstore")
162 (set_attr "cpu_feature" "v9,*,*")])
166 (define_expand "sync_compare_and_swap<mode>"
167 [(match_operand:I12MODE 0 "register_operand" "")
168 (match_operand:I12MODE 1 "memory_operand" "")
169 (match_operand:I12MODE 2 "register_operand" "")
170 (match_operand:I12MODE 3 "register_operand" "")]
173 sparc_expand_compare_and_swap_12 (operands[0], operands[1],
174 operands[2], operands[3]);
178 (define_expand "sync_compare_and_swap<mode>"
180 [(set (match_operand:I48MODE 0 "register_operand" "")
181 (match_operand:I48MODE 1 "memory_operand" ""))
183 (unspec_volatile:I48MODE
184 [(match_operand:I48MODE 2 "register_operand" "")
185 (match_operand:I48MODE 3 "register_operand" "")]
189 if (!REG_P (XEXP (operands[1], 0)))
191 rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
192 operands[1] = replace_equiv_address (operands[1], addr);
194 emit_insn (gen_memory_barrier ());
197 (define_insn "*sync_compare_and_swap<mode>"
198 [(set (match_operand:I48MODE 0 "register_operand" "=r")
199 (mem:I48MODE (match_operand 1 "register_operand" "r")))
200 (set (mem:I48MODE (match_dup 1))
201 (unspec_volatile:I48MODE
202 [(match_operand:I48MODE 2 "register_operand" "r")
203 (match_operand:I48MODE 3 "register_operand" "0")]
205 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
206 "cas<modesuffix>\t[%1], %2, %0"
207 [(set_attr "type" "multi")])
209 (define_insn "*sync_compare_and_swapdi_v8plus"
210 [(set (match_operand:DI 0 "register_operand" "=h")
211 (mem:DI (match_operand 1 "register_operand" "r")))
212 (set (mem:DI (match_dup 1))
214 [(match_operand:DI 2 "register_operand" "h")
215 (match_operand:DI 3 "register_operand" "0")]
219 if (sparc_check_64 (operands[3], insn) <= 0)
220 output_asm_insn ("srl\t%L3, 0, %L3", operands);
221 output_asm_insn ("sllx\t%H3, 32, %H3", operands);
222 output_asm_insn ("or\t%L3, %H3, %L3", operands);
223 if (sparc_check_64 (operands[2], insn) <= 0)
224 output_asm_insn ("srl\t%L2, 0, %L2", operands);
225 output_asm_insn ("sllx\t%H2, 32, %H3", operands);
226 output_asm_insn ("or\t%L2, %H3, %H3", operands);
227 output_asm_insn ("casx\t[%1], %H3, %L3", operands);
228 return "srlx\t%L3, 32, %H3";
230 [(set_attr "type" "multi")
231 (set_attr "length" "8")])
233 (define_expand "sync_lock_test_and_set<mode>"
234 [(match_operand:I12MODE 0 "register_operand" "")
235 (match_operand:I12MODE 1 "memory_operand" "")
236 (match_operand:I12MODE 2 "arith_operand" "")]
239 if (operands[2] != const1_rtx)
242 emit_insn (gen_memory_barrier ());
243 if (<MODE>mode != QImode)
244 operands[1] = adjust_address (operands[1], QImode, 0);
245 emit_insn (gen_ldstub<mode> (operands[0], operands[1]));
249 (define_expand "sync_lock_test_and_setsi"
251 [(set (match_operand:SI 0 "register_operand" "")
252 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "")]
255 (match_operand:SI 2 "arith_operand" ""))])]
258 if (! TARGET_V8 && ! TARGET_V9)
260 if (operands[2] != const1_rtx)
262 operands[1] = adjust_address (operands[1], QImode, 0);
263 emit_insn (gen_ldstubsi (operands[0], operands[1]));
266 emit_insn (gen_memory_barrier ());
267 operands[2] = force_reg (SImode, operands[2]);
270 (define_insn "*swapsi"
271 [(set (match_operand:SI 0 "register_operand" "=r")
272 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
275 (match_operand:SI 2 "register_operand" "0"))]
276 "TARGET_V8 || TARGET_V9"
278 [(set_attr "type" "multi")])
280 (define_expand "ldstubqi"
281 [(parallel [(set (match_operand:QI 0 "register_operand" "")
282 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
284 (set (match_dup 1) (const_int -1))])]
288 (define_expand "ldstub<mode>"
289 [(parallel [(set (match_operand:I24MODE 0 "register_operand" "")
291 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
293 (set (match_dup 1) (const_int -1))])]
297 (define_insn "*ldstubqi"
298 [(set (match_operand:QI 0 "register_operand" "=r")
299 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
301 (set (match_dup 1) (const_int -1))]
304 [(set_attr "type" "multi")])
306 (define_insn "*ldstub<mode>"
307 [(set (match_operand:I24MODE 0 "register_operand" "=r")
309 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
311 (set (match_dup 1) (const_int -1))]
314 [(set_attr "type" "multi")])