1 ;; GCC machine description for SPARC synchronization instructions.
2 ;; Copyright (C) 2005, 2007, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_mode_iterator I12MODE [QI HI])
22 (define_mode_iterator I124MODE [QI HI SI])
23 (define_mode_iterator I24MODE [HI SI])
24 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
25 (define_mode_attr modesuffix [(SI "") (DI "x")])
27 (define_expand "mem_thread_fence"
28 [(match_operand:SI 0 "const_int_operand")]
29 "TARGET_V8 || TARGET_V9"
31 enum memmodel model = (enum memmodel) INTVAL (operands[0]);
32 sparc_emit_membar_for_model (model, 3, 3);
36 (define_expand "membar"
38 (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
40 "TARGET_V8 || TARGET_V9"
42 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
43 MEM_VOLATILE_P (operands[1]) = 1;
46 ;; A compiler-only memory barrier. Generic code, when checking for the
47 ;; existance of various named patterns, uses asm("":::"memory") when we
48 ;; don't need an actual instruction. Here, it's easiest to pretend that
49 ;; membar 0 is such a barrier. Further, this gives us a nice hook to
50 ;; ignore all such barriers on Sparc V7.
51 (define_insn "*membar_empty"
52 [(set (match_operand:BLK 0 "" "")
53 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
57 [(set_attr "type" "multi")
58 (set_attr "length" "0")])
60 ;; For V8, STBAR is exactly membar #StoreStore, by definition.
61 (define_insn "*membar_storestore"
62 [(set (match_operand:BLK 0 "" "")
63 (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
66 [(set_attr "type" "multi")])
68 ;; For V8, LDSTUB has the effect of membar #StoreLoad.
69 (define_insn "*membar_storeload"
70 [(set (match_operand:BLK 0 "" "")
71 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
73 "ldstub\t[%%sp-1], %%g0"
74 [(set_attr "type" "multi")])
76 ;; Put the two together, in combination with the fact that V8 implements PSO
77 ;; as its weakest memory model, means a full barrier. Match all remaining
78 ;; instances of the membar pattern for Sparc V8.
79 (define_insn "*membar_v8"
80 [(set (match_operand:BLK 0 "" "")
81 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
84 "stbar\n\tldstub\t[%%sp-1], %%g0"
85 [(set_attr "type" "multi")
86 (set_attr "length" "2")])
88 ;; For V9, we have the full membar instruction.
89 (define_insn "*membar"
90 [(set (match_operand:BLK 0 "" "")
91 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
95 [(set_attr "type" "multi")])
97 (define_expand "atomic_load<mode>"
98 [(match_operand:I 0 "register_operand" "")
99 (match_operand:I 1 "memory_operand" "")
100 (match_operand:SI 2 "const_int_operand" "")]
103 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
105 sparc_emit_membar_for_model (model, 1, 1);
107 if (TARGET_ARCH64 || <MODE>mode != DImode)
108 emit_move_insn (operands[0], operands[1]);
110 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
112 sparc_emit_membar_for_model (model, 1, 2);
116 (define_insn "atomic_loaddi_1"
117 [(set (match_operand:DI 0 "register_operand" "=U,?*f")
118 (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
122 [(set_attr "type" "load,fpload")])
124 (define_expand "atomic_store<mode>"
125 [(match_operand:I 0 "memory_operand" "")
126 (match_operand:I 1 "register_operand" "")
127 (match_operand:SI 2 "const_int_operand" "")]
130 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
132 sparc_emit_membar_for_model (model, 2, 1);
134 if (TARGET_ARCH64 || <MODE>mode != DImode)
135 emit_move_insn (operands[0], operands[1]);
137 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
139 sparc_emit_membar_for_model (model, 2, 2);
143 (define_insn "atomic_storedi_1"
144 [(set (match_operand:DI 0 "memory_operand" "=m,m,m")
146 [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
153 [(set_attr "type" "store,store,fpstore")
154 (set_attr "cpu_feature" "v9,*,*")])
156 (define_expand "atomic_compare_and_swap<mode>"
157 [(match_operand:SI 0 "register_operand" "") ;; bool output
158 (match_operand:I 1 "register_operand" "") ;; val output
159 (match_operand:I 2 "mem_noofs_operand" "") ;; memory
160 (match_operand:I 3 "register_operand" "") ;; expected
161 (match_operand:I 4 "register_operand" "") ;; desired
162 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
163 (match_operand:SI 6 "const_int_operand" "") ;; mod_s
164 (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
165 "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
167 sparc_expand_compare_and_swap (operands);
171 (define_expand "atomic_compare_and_swap<mode>_1"
173 [(set (match_operand:I48MODE 0 "register_operand" "")
174 (match_operand:I48MODE 1 "mem_noofs_operand" ""))
176 (unspec_volatile:I48MODE
177 [(match_operand:I48MODE 2 "register_operand" "")
178 (match_operand:I48MODE 3 "register_operand" "")]
183 (define_insn "*atomic_compare_and_swap<mode>_1"
184 [(set (match_operand:I48MODE 0 "register_operand" "=r")
185 (match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
187 (unspec_volatile:I48MODE
188 [(match_operand:I48MODE 2 "register_operand" "r")
189 (match_operand:I48MODE 3 "register_operand" "0")]
191 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
192 "cas<modesuffix>\t%1, %2, %0"
193 [(set_attr "type" "multi")])
195 (define_insn "*atomic_compare_and_swapdi_v8plus"
196 [(set (match_operand:DI 0 "register_operand" "=h")
197 (match_operand:DI 1 "mem_noofs_operand" "+w"))
200 [(match_operand:DI 2 "register_operand" "h")
201 (match_operand:DI 3 "register_operand" "0")]
205 if (sparc_check_64 (operands[3], insn) <= 0)
206 output_asm_insn ("srl\t%L3, 0, %L3", operands);
207 output_asm_insn ("sllx\t%H3, 32, %H3", operands);
208 output_asm_insn ("or\t%L3, %H3, %L3", operands);
209 if (sparc_check_64 (operands[2], insn) <= 0)
210 output_asm_insn ("srl\t%L2, 0, %L2", operands);
211 output_asm_insn ("sllx\t%H2, 32, %H3", operands);
212 output_asm_insn ("or\t%L2, %H3, %H3", operands);
213 output_asm_insn ("casx\t%1, %H3, %L3", operands);
214 return "srlx\t%L3, 32, %H3";
216 [(set_attr "type" "multi")
217 (set_attr "length" "8")])
219 (define_expand "atomic_exchangesi"
220 [(match_operand:SI 0 "register_operand" "")
221 (match_operand:SI 1 "memory_operand" "")
222 (match_operand:SI 2 "register_operand" "")
223 (match_operand:SI 3 "const_int_operand" "")]
224 "TARGET_V8 || TARGET_V9"
226 enum memmodel model = (enum memmodel) INTVAL (operands[3]);
228 sparc_emit_membar_for_model (model, 3, 1);
229 emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
230 sparc_emit_membar_for_model (model, 3, 2);
234 (define_insn "swapsi"
235 [(set (match_operand:SI 0 "register_operand" "=r")
236 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
239 (match_operand:SI 2 "register_operand" "0"))]
240 "TARGET_V8 || TARGET_V9"
242 [(set_attr "type" "multi")])
244 (define_expand "atomic_test_and_set"
245 [(match_operand:QI 0 "register_operand" "")
246 (match_operand:QI 1 "memory_operand" "")
247 (match_operand:SI 2 "const_int_operand" "")]
250 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
253 sparc_emit_membar_for_model (model, 3, 1);
254 emit_insn (gen_ldstub (operands[0], operands[1]));
255 sparc_emit_membar_for_model (model, 3, 2);
257 /* Convert the 0/0xff result we would otherwise have to a boolean.
258 I.e. ignore all but bit 0. */
259 ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
260 operands[0], true, OPTAB_LIB_WIDEN);
261 if (ret != operands[0])
262 emit_move_insn (operands[0], ret);
267 (define_insn "ldstub"
268 [(set (match_operand:QI 0 "register_operand" "=r")
269 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
271 (set (match_dup 1) (const_int -1))]
274 [(set_attr "type" "multi")])