[pf3gnuchains/gcc-fork.git] / gcc / config / sparc / sparc.md

;; Machine description for SPARC chip for GCC
;;  Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
;;  1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
;;  64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
;;  at Cygnus Support.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

(define_constants
  [(UNSPEC_MOVE_PIC             0)
   (UNSPEC_UPDATE_RETURN        1)
   (UNSPEC_LOAD_PCREL_SYM       2)
   (UNSPEC_MOVE_PIC_LABEL       5)
   (UNSPEC_SETH44               6)
   (UNSPEC_SETM44               7)
   (UNSPEC_SETHH                9)
   (UNSPEC_SETLM                10)
   (UNSPEC_EMB_HISUM            11)
   (UNSPEC_EMB_TEXTUHI          13)
   (UNSPEC_EMB_TEXTHI           14)
   (UNSPEC_EMB_TEXTULO          15)
   (UNSPEC_EMB_SETHM            18)

   (UNSPEC_TLSGD                30)
   (UNSPEC_TLSLDM               31)
   (UNSPEC_TLSLDO               32)
   (UNSPEC_TLSIE                33)
   (UNSPEC_TLSLE                34)
   (UNSPEC_TLSLD_BASE           35)
  ])

(define_constants
  [(UNSPECV_BLOCKAGE            0)
   (UNSPECV_FLUSHW              1)
   (UNSPECV_GOTO                2)
   (UNSPECV_FLUSH               4)
   (UNSPECV_SETJMP              5)
   (UNSPECV_SAVEW               6)
  ])

;; The upper 32 fp regs on the v9 can't hold SFmode values.  To deal with this
;; a second register class, EXTRA_FP_REGS, exists for the v9 chip.  The name
;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
;; constraint letter is 'e'.  To avoid any confusion, 'e' is used instead of
;; 'f' for all DF/TFmode values, including those that are specific to the v8.

;; Attribute for cpu type.
;; These must match the values for enum processor_type in sparc.h.
(define_attr "cpu"
  "v7,
   cypress,
   v8,
   supersparc,
   sparclite,f930,f934,
   hypersparc,sparclite86x,
   sparclet,tsc701,
   v9,
   ultrasparc,
   ultrasparc3"
  (const (symbol_ref "sparc_cpu_attr")))

;; Attribute for the instruction set.
;; At present we only need to distinguish v9/!v9, but for clarity we
;; test TARGET_V8 too.
(define_attr "isa" "v7,v8,v9,sparclet"
 (const
  (cond [(symbol_ref "TARGET_V9") (const_string "v9")
         (symbol_ref "TARGET_V8") (const_string "v8")
         (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
        (const_string "v7"))))

;; Insn type.
(define_attr "type"
  "ialu,compare,shift,
   load,sload,store,
   uncond_branch,branch,call,sibcall,call_no_delay_slot,return,
   imul,idiv,
   fpload,fpstore,
   fp,fpmove,
   fpcmove,fpcrmove,
   fpcmp,
   fpmul,fpdivs,fpdivd,
   fpsqrts,fpsqrtd,
   fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,
   cmove,
   ialuX,
   multi,savew,flushw,iflush,trap"
  (const_string "ialu"))

;; True if branch/call has empty delay slot and will emit a nop in it
(define_attr "empty_delay_slot" "false,true"
  (symbol_ref "empty_delay_slot (insn)"))

(define_attr "branch_type" "none,icc,fcc,reg"
  (const_string "none"))

(define_attr "pic" "false,true"
  (symbol_ref "flag_pic != 0"))

(define_attr "calls_alloca" "false,true"
  (symbol_ref "current_function_calls_alloca != 0"))

(define_attr "calls_eh_return" "false,true"
   (symbol_ref "current_function_calls_eh_return !=0 "))
   
(define_attr "leaf_function" "false,true"
  (symbol_ref "current_function_uses_only_leaf_regs != 0"))

(define_attr "delayed_branch" "false,true"
  (symbol_ref "flag_delayed_branch != 0"))

;; Length (in # of insns).
(define_attr "length" ""
  (cond [(eq_attr "type" "uncond_branch,call")
           (if_then_else (eq_attr "empty_delay_slot" "true")
             (const_int 2)
             (const_int 1))
         (eq_attr "type" "sibcall")
           (if_then_else (eq_attr "leaf_function" "true")
             (if_then_else (eq_attr "empty_delay_slot" "true")
               (const_int 3)
               (const_int 2))
             (if_then_else (eq_attr "empty_delay_slot" "true")
               (const_int 2)
               (const_int 1)))
         (eq_attr "branch_type" "icc")
           (if_then_else (match_operand 0 "noov_compare64_op" "")
             (if_then_else (lt (pc) (match_dup 1))
               (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 2)
                   (const_int 1))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 4)
                   (const_int 3)))
               (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 2)
                   (const_int 1))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 4)
                   (const_int 3))))
             (if_then_else (eq_attr "empty_delay_slot" "true")
               (const_int 2)
               (const_int 1)))
         (eq_attr "branch_type" "fcc")
           (if_then_else (match_operand 0 "fcc0_reg_operand" "")
             (if_then_else (eq_attr "empty_delay_slot" "true")
               (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
                 (const_int 3)
                 (const_int 2))
               (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
                 (const_int 2)
                 (const_int 1)))
             (if_then_else (lt (pc) (match_dup 2))
               (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 2)
                   (const_int 1))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 4)
                   (const_int 3)))
               (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 2)
                   (const_int 1))
                 (if_then_else (eq_attr "empty_delay_slot" "true")
                   (const_int 4)
                   (const_int 3)))))
         (eq_attr "branch_type" "reg")
           (if_then_else (lt (pc) (match_dup 2))
             (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000))
               (if_then_else (eq_attr "empty_delay_slot" "true")
                 (const_int 2)
                 (const_int 1))
               (if_then_else (eq_attr "empty_delay_slot" "true")
                 (const_int 4)
                 (const_int 3)))
             (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000))
               (if_then_else (eq_attr "empty_delay_slot" "true")
                 (const_int 2)
                 (const_int 1))
               (if_then_else (eq_attr "empty_delay_slot" "true")
                 (const_int 4)
                 (const_int 3))))
         ] (const_int 1)))

;; FP precision.
(define_attr "fptype" "single,double"
  (const_string "single"))

;; UltraSPARC-III integer load type.
(define_attr "us3load_type" "2cycle,3cycle"
  (const_string "2cycle"))

(define_asm_attributes
  [(set_attr "length" "2")
   (set_attr "type" "multi")])

;; Attributes for instruction and branch scheduling
(define_attr "tls_call_delay" "false,true"
  (symbol_ref "tls_call_delay (insn)"))

(define_attr "in_call_delay" "false,true"
  (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
                (const_string "false")
         (eq_attr "type" "load,fpload,store,fpstore")
                (if_then_else (eq_attr "length" "1")
                              (const_string "true")
                              (const_string "false"))]
        (if_then_else (and (eq_attr "length" "1")
                           (eq_attr "tls_call_delay" "true"))
                      (const_string "true")
                      (const_string "false"))))

(define_attr "eligible_for_sibcall_delay" "false,true"
  (symbol_ref "eligible_for_sibcall_delay (insn)"))

(define_attr "eligible_for_return_delay" "false,true"
  (symbol_ref "eligible_for_return_delay (insn)"))

;; ??? !v9: Should implement the notion of predelay slots for floating-point
;; branches.  This would allow us to remove the nop always inserted before
;; a floating point branch.

;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
;; This is because doing so will add several pipeline stalls to the path
;; that the load/store did not come from.  Unfortunately, there is no way
;; to prevent fill_eager_delay_slots from using load/store without completely
;; disabling them.  For the SPEC benchmark set, this is a serious lose,
;; because it prevents us from moving back the final store of inner loops.

(define_attr "in_branch_delay" "false,true"
  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
                     (eq_attr "length" "1"))
                (const_string "true")
                (const_string "false")))

(define_attr "in_uncond_branch_delay" "false,true"
  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
                     (eq_attr "length" "1"))
                (const_string "true")
                (const_string "false")))

(define_attr "in_annul_branch_delay" "false,true"
  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
                     (eq_attr "length" "1"))
                (const_string "true")
                (const_string "false")))

(define_delay (eq_attr "type" "call")
  [(eq_attr "in_call_delay" "true") (nil) (nil)])

(define_delay (eq_attr "type" "sibcall")
  [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])

(define_delay (eq_attr "type" "branch")
  [(eq_attr "in_branch_delay" "true")
   (nil) (eq_attr "in_annul_branch_delay" "true")])

(define_delay (eq_attr "type" "uncond_branch")
  [(eq_attr "in_uncond_branch_delay" "true")
   (nil) (nil)])

(define_delay (eq_attr "type" "return")
  [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])

;; Include SPARC DFA schedulers

(include "cypress.md")
(include "supersparc.md")
(include "hypersparc.md")
(include "sparclet.md")
(include "ultra1_2.md")
(include "ultra3.md")

\f
;; Compare instructions.
;; This controls RTL generation and register allocation.

;; We generate RTL for comparisons and branches by having the cmpxx 
;; patterns store away the operands.  Then, the scc and bcc patterns
;; emit RTL for both the compare and the branch.
;;
;; We do this because we want to generate different code for an sne and
;; seq insn.  In those cases, if the second operand of the compare is not
;; const0_rtx, we want to compute the xor of the two operands and test
;; it against zero.
;;
;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match
;; the patterns.  Finally, we have the DEFINE_SPLITs for some of the scc
;; insns that actually require more than one machine instruction.

;; Put cmpsi first among compare insns so it matches two CONST_INT operands.

(define_expand "cmpsi"
  [(set (reg:CC 100)
        (compare:CC (match_operand:SI 0 "compare_operand" "")
                    (match_operand:SI 1 "arith_operand" "")))]
  ""
{
  if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
    operands[0] = force_reg (SImode, operands[0]);

  sparc_compare_op0 = operands[0];
  sparc_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpdi"
  [(set (reg:CCX 100)
        (compare:CCX (match_operand:DI 0 "compare_operand" "")
                     (match_operand:DI 1 "arith_double_operand" "")))]
  "TARGET_ARCH64"
{
  if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
    operands[0] = force_reg (DImode, operands[0]);

  sparc_compare_op0 = operands[0];
  sparc_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpsf"
  ;; The 96 here isn't ever used by anyone.
  [(set (reg:CCFP 96)
        (compare:CCFP (match_operand:SF 0 "register_operand" "")
                      (match_operand:SF 1 "register_operand" "")))]
  "TARGET_FPU"
{
  sparc_compare_op0 = operands[0];
  sparc_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpdf"
  ;; The 96 here isn't ever used by anyone.
  [(set (reg:CCFP 96)
        (compare:CCFP (match_operand:DF 0 "register_operand" "")
                      (match_operand:DF 1 "register_operand" "")))]
  "TARGET_FPU"
{
  sparc_compare_op0 = operands[0];
  sparc_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmptf"
  ;; The 96 here isn't ever used by anyone.
  [(set (reg:CCFP 96)
        (compare:CCFP (match_operand:TF 0 "register_operand" "")
                      (match_operand:TF 1 "register_operand" "")))]
  "TARGET_FPU"
{
  sparc_compare_op0 = operands[0];
  sparc_compare_op1 = operands[1];
  DONE;
})

;; Now the compare DEFINE_INSNs.

(define_insn "*cmpsi_insn"
  [(set (reg:CC 100)
        (compare:CC (match_operand:SI 0 "register_operand" "r")
                    (match_operand:SI 1 "arith_operand" "rI")))]
  ""
  "cmp\t%0, %1"
  [(set_attr "type" "compare")])

(define_insn "*cmpdi_sp64"
  [(set (reg:CCX 100)
        (compare:CCX (match_operand:DI 0 "register_operand" "r")
                     (match_operand:DI 1 "arith_double_operand" "rHI")))]
  "TARGET_ARCH64"
  "cmp\t%0, %1"
  [(set_attr "type" "compare")])

(define_insn "*cmpsf_fpe"
  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
        (compare:CCFPE (match_operand:SF 1 "register_operand" "f")
                       (match_operand:SF 2 "register_operand" "f")))]
  "TARGET_FPU"
{
  if (TARGET_V9)
    return "fcmpes\t%0, %1, %2";
  return "fcmpes\t%1, %2";
}
  [(set_attr "type" "fpcmp")])

(define_insn "*cmpdf_fpe"
  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
        (compare:CCFPE (match_operand:DF 1 "register_operand" "e")
                       (match_operand:DF 2 "register_operand" "e")))]
  "TARGET_FPU"
{
  if (TARGET_V9)
    return "fcmped\t%0, %1, %2";
  return "fcmped\t%1, %2";
}
  [(set_attr "type" "fpcmp")
   (set_attr "fptype" "double")])

(define_insn "*cmptf_fpe"
  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
        (compare:CCFPE (match_operand:TF 1 "register_operand" "e")
                       (match_operand:TF 2 "register_operand" "e")))]
  "TARGET_FPU && TARGET_HARD_QUAD"
{
  if (TARGET_V9)
    return "fcmpeq\t%0, %1, %2";
  return "fcmpeq\t%1, %2";
}
  [(set_attr "type" "fpcmp")])

(define_insn "*cmpsf_fp"
  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
        (compare:CCFP (match_operand:SF 1 "register_operand" "f")
                      (match_operand:SF 2 "register_operand" "f")))]
  "TARGET_FPU"
{
  if (TARGET_V9)
    return "fcmps\t%0, %1, %2";
  return "fcmps\t%1, %2";
}
  [(set_attr "type" "fpcmp")])

(define_insn "*cmpdf_fp"
  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
        (compare:CCFP (match_operand:DF 1 "register_operand" "e")
                      (match_operand:DF 2 "register_operand" "e")))]
  "TARGET_FPU"
{
  if (TARGET_V9)
    return "fcmpd\t%0, %1, %2";
  return "fcmpd\t%1, %2";
}
  [(set_attr "type" "fpcmp")
   (set_attr "fptype" "double")])

(define_insn "*cmptf_fp"
  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
        (compare:CCFP (match_operand:TF 1 "register_operand" "e")
                      (match_operand:TF 2 "register_operand" "e")))]
  "TARGET_FPU && TARGET_HARD_QUAD"
{
  if (TARGET_V9)
    return "fcmpq\t%0, %1, %2";
  return "fcmpq\t%1, %2";
}
  [(set_attr "type" "fpcmp")])
\f
;; Next come the scc insns.  For seq, sne, sgeu, and sltu, we can do this
;; without jumps using the addx/subx instructions.  For seq/sne on v9 we use
;; the same code as v8 (the addx/subx method has more applications).  The
;; exception to this is "reg != 0" which can be done in one instruction on v9
;; (so we do it).  For the rest, on v9 we use conditional moves; on v8, we do
;; branches.

;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they
;; generate addcc/subcc instructions.

(define_expand "seqsi_special"
  [(set (match_dup 3)
        (xor:SI (match_operand:SI 1 "register_operand" "")
                (match_operand:SI 2 "register_operand" "")))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (eq:SI (match_dup 3) (const_int 0)))
              (clobber (reg:CC 100))])]
  ""
  { operands[3] = gen_reg_rtx (SImode); })

(define_expand "seqdi_special"
  [(set (match_dup 3)
        (xor:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "register_operand" "")))
   (set (match_operand:DI 0 "register_operand" "")
        (eq:DI (match_dup 3) (const_int 0)))]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (DImode); })

(define_expand "snesi_special"
  [(set (match_dup 3)
        (xor:SI (match_operand:SI 1 "register_operand" "")
                (match_operand:SI 2 "register_operand" "")))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (ne:SI (match_dup 3) (const_int 0)))
              (clobber (reg:CC 100))])]
  ""
  { operands[3] = gen_reg_rtx (SImode); })

(define_expand "snedi_special"
  [(set (match_dup 3)
        (xor:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "register_operand" "")))
   (set (match_operand:DI 0 "register_operand" "")
        (ne:DI (match_dup 3) (const_int 0)))]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (DImode); })

(define_expand "seqdi_special_trunc"
  [(set (match_dup 3)
        (xor:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "register_operand" "")))
   (set (match_operand:SI 0 "register_operand" "")
        (eq:SI (match_dup 3) (const_int 0)))]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (DImode); })

(define_expand "snedi_special_trunc"
  [(set (match_dup 3)
        (xor:DI (match_operand:DI 1 "register_operand" "")
                (match_operand:DI 2 "register_operand" "")))
   (set (match_operand:SI 0 "register_operand" "")
        (ne:SI (match_dup 3) (const_int 0)))]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (DImode); })

(define_expand "seqsi_special_extend"
  [(set (match_dup 3)
        (xor:SI (match_operand:SI 1 "register_operand" "")
                (match_operand:SI 2 "register_operand" "")))
   (parallel [(set (match_operand:DI 0 "register_operand" "")
                   (eq:DI (match_dup 3) (const_int 0)))
              (clobber (reg:CC 100))])]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (SImode); })

(define_expand "snesi_special_extend"
  [(set (match_dup 3)
        (xor:SI (match_operand:SI 1 "register_operand" "")
                (match_operand:SI 2 "register_operand" "")))
   (parallel [(set (match_operand:DI 0 "register_operand" "")
                   (ne:DI (match_dup 3) (const_int 0)))
              (clobber (reg:CC 100))])]
  "TARGET_ARCH64"
  { operands[3] = gen_reg_rtx (SImode); })

;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
;; However, the code handles both SImode and DImode.
(define_expand "seq"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (eq:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == SImode)
    {
      rtx pat;

      if (GET_MODE (operands[0]) == SImode)
        pat = gen_seqsi_special (operands[0], sparc_compare_op0,
                                 sparc_compare_op1);
      else if (! TARGET_ARCH64)
        FAIL;
      else
        pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0,
                                        sparc_compare_op1);
      emit_insn (pat);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == DImode)
    {
      rtx pat;

      if (! TARGET_ARCH64)
        FAIL;
      else if (GET_MODE (operands[0]) == SImode)
        pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0,
                                       sparc_compare_op1);
      else
        pat = gen_seqdi_special (operands[0], sparc_compare_op0,
                                 sparc_compare_op1);
      emit_insn (pat);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (EQ, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
;; However, the code handles both SImode and DImode.
(define_expand "sne"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (ne:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == SImode)
    {
      rtx pat;

      if (GET_MODE (operands[0]) == SImode)
        pat = gen_snesi_special (operands[0], sparc_compare_op0,
                                 sparc_compare_op1);
      else if (! TARGET_ARCH64)
        FAIL;
      else
        pat = gen_snesi_special_extend (operands[0], sparc_compare_op0,
                                        sparc_compare_op1);
      emit_insn (pat);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == DImode)
    {
      rtx pat;

      if (! TARGET_ARCH64)
        FAIL;
      else if (GET_MODE (operands[0]) == SImode)
        pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0,
                                       sparc_compare_op1);
      else
        pat = gen_snedi_special (operands[0], sparc_compare_op0,
                                 sparc_compare_op1);
      emit_insn (pat);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (NE, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

(define_expand "sgt"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (gt:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (GT, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

(define_expand "slt"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (lt:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (LT, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

(define_expand "sge"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (ge:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (GE, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

(define_expand "sle"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (le:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
      emit_jump_insn (gen_sne (operands[0]));
      DONE;
    }
  else if (TARGET_V9)
    {
      if (gen_v9_scc (LE, operands))
        DONE;
      /* fall through */
    }
  FAIL;
})

(define_expand "sgtu"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (gtu:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (! TARGET_V9)
    {
      rtx tem, pat;

      /* We can do ltu easily, so if both operands are registers, swap them and
         do a LTU.  */
      if ((GET_CODE (sparc_compare_op0) == REG
           || GET_CODE (sparc_compare_op0) == SUBREG)
          && (GET_CODE (sparc_compare_op1) == REG
              || GET_CODE (sparc_compare_op1) == SUBREG))
        {
          tem = sparc_compare_op0;
          sparc_compare_op0 = sparc_compare_op1;
          sparc_compare_op1 = tem;
          pat = gen_sltu (operands[0]);
          if (pat == NULL_RTX)
            FAIL;
          emit_insn (pat);
          DONE;
        }
    }
  else
    {
      if (gen_v9_scc (GTU, operands))
        DONE;
    }
  FAIL;
})

(define_expand "sltu"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (ltu:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (TARGET_V9)
    {
      if (gen_v9_scc (LTU, operands))
        DONE;
    }
  operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "sgeu"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (geu:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (TARGET_V9)
    {
      if (gen_v9_scc (GEU, operands))
        DONE;
    }
  operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "sleu"
  [(set (match_operand:SI 0 "intreg_operand" "")
        (leu:SI (match_dup 1) (const_int 0)))]
  ""
{
  if (! TARGET_V9)
    {
      rtx tem, pat;

      /* We can do geu easily, so if both operands are registers, swap them and
         do a GEU.  */
      if ((GET_CODE (sparc_compare_op0) == REG
           || GET_CODE (sparc_compare_op0) == SUBREG)
          && (GET_CODE (sparc_compare_op1) == REG
              || GET_CODE (sparc_compare_op1) == SUBREG))
        {
          tem = sparc_compare_op0;
          sparc_compare_op0 = sparc_compare_op1;
          sparc_compare_op1 = tem;
          pat = gen_sgeu (operands[0]);
          if (pat == NULL_RTX)
            FAIL;
          emit_insn (pat);
          DONE;
        }
    }
  else
    {
      if (gen_v9_scc (LEU, operands))
        DONE;
    }
  FAIL;
})

;; Now the DEFINE_INSNs for the scc cases.

;; The SEQ and SNE patterns are special because they can be done
;; without any branching and do not involve a COMPARE.  We want
;; them to always use the splitz below so the results can be
;; scheduled.

(define_insn_and_split "*snesi_zero"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (ne:SI (match_operand:SI 1 "register_operand" "r")
               (const_int 0)))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*neg_snesi_zero"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
                       (const_int 0))))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*snesi_zero_extend"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (ne:DI (match_operand:SI 1 "register_operand" "r")
               (const_int 0)))
   (clobber (reg:CC 100))]
  "TARGET_ARCH64"
  "#"
  "&& 1"
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
                                                     (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
                                                        (const_int 0))
                                               (ltu:SI (reg:CC_NOOV 100)
                                                       (const_int 0)))))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*snedi_zero"
  [(set (match_operand:DI 0 "register_operand" "=&r")
        (ne:DI (match_operand:DI 1 "register_operand" "r")
               (const_int 0)))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int 1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*neg_snedi_zero"
  [(set (match_operand:DI 0 "register_operand" "=&r")
        (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
                       (const_int 0))))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int -1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*snedi_zero_trunc"
  [(set (match_operand:SI 0 "register_operand" "=&r")
        (ne:SI (match_operand:DI 1 "register_operand" "r")
               (const_int 0)))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int 1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*seqsi_zero"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (eq:SI (match_operand:SI 1 "register_operand" "r")
               (const_int 0)))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*neg_seqsi_zero"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
                       (const_int 0))))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*seqsi_zero_extend"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (eq:DI (match_operand:SI 1 "register_operand" "r")
               (const_int 0)))
   (clobber (reg:CC 100))]
  "TARGET_ARCH64"
  "#"
  "&& 1"
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
                                                     (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
                                                          (const_int -1))
                                                (ltu:SI (reg:CC_NOOV 100)
                                                        (const_int 0)))))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*seqdi_zero"
  [(set (match_operand:DI 0 "register_operand" "=&r")
        (eq:DI (match_operand:DI 1 "register_operand" "r")
               (const_int 0)))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int 1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*neg_seqdi_zero"
  [(set (match_operand:DI 0 "register_operand" "=&r")
        (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
                       (const_int 0))))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int -1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")]) 

(define_insn_and_split "*seqdi_zero_trunc"
  [(set (match_operand:SI 0 "register_operand" "=&r")
        (eq:SI (match_operand:DI 1 "register_operand" "r")
               (const_int 0)))]
  "TARGET_ARCH64"
  "#"
  "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
                                              (const_int 0))
                                       (const_int 1)
                                       (match_dup 0)))]
  ""
  [(set_attr "length" "2")])

;; We can also do (x + (i == 0)) and related, so put them in.
;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
;; versions for v9.

(define_insn_and_split "*x_plus_i_ne_0"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
                        (const_int 0))
                 (match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
                               (match_dup 2)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*x_minus_i_ne_0"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_operand:SI 2 "register_operand" "r")
                  (ne:SI (match_operand:SI 1 "register_operand" "r")
                         (const_int 0))))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (minus:SI (match_dup 2)
                                (ltu:SI (reg:CC 100) (const_int 0))))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*x_plus_i_eq_0"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
                        (const_int 0))
                 (match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
                               (match_dup 2)))]
  ""
  [(set_attr "length" "2")])

(define_insn_and_split "*x_minus_i_eq_0"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_operand:SI 2 "register_operand" "r")
                  (eq:SI (match_operand:SI 1 "register_operand" "r")
                         (const_int 0))))
   (clobber (reg:CC 100))]
  ""
  "#"
  ""
  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
                                           (const_int 0)))
   (set (match_dup 0) (minus:SI (match_dup 2)
                                (geu:SI (reg:CC 100) (const_int 0))))]
  ""
  [(set_attr "length" "2")])

;; We can also do GEU and LTU directly, but these operate after a compare.
;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
;; versions for v9.

(define_insn "*sltu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (ltu:SI (reg:CC 100) (const_int 0)))]
  ""
  "addx\t%%g0, 0, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*neg_sltu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
  ""
  "subx\t%%g0, 0, %0"
  [(set_attr "type" "ialuX")])

;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*neg_sltu_minus_x"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
                  (match_operand:SI 1 "arith_operand" "rI")))]
  ""
  "subx\t%%g0, %1, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*neg_sltu_plus_x"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
                         (match_operand:SI 1 "arith_operand" "rI"))))]
  ""
  "subx\t%%g0, %1, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*sgeu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (geu:SI (reg:CC 100) (const_int 0)))]
  ""
  "subx\t%%g0, -1, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*neg_sgeu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
  ""
  "addx\t%%g0, -1, %0"
  [(set_attr "type" "ialuX")])

;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
;; versions for v9.

(define_insn "*sltu_plus_x"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
                 (match_operand:SI 1 "arith_operand" "rI")))]
  ""
  "addx\t%%g0, %1, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*sltu_plus_x_plus_y"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
                 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
                          (match_operand:SI 2 "arith_operand" "rI"))))]
  ""
  "addx\t%1, %2, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*x_minus_sltu"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_operand:SI 1 "register_operand" "r")
                  (ltu:SI (reg:CC 100) (const_int 0))))]
  ""
  "subx\t%1, 0, %0"
  [(set_attr "type" "ialuX")])

;; ??? Combine should canonicalize these next two to the same pattern.
(define_insn "*x_minus_y_minus_sltu"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
                            (match_operand:SI 2 "arith_operand" "rI"))
                  (ltu:SI (reg:CC 100) (const_int 0))))]
  ""
  "subx\t%r1, %2, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*x_minus_sltu_plus_y"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
                  (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
                           (match_operand:SI 2 "arith_operand" "rI"))))]
  ""
  "subx\t%r1, %2, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*sgeu_plus_x"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (geu:SI (reg:CC 100) (const_int 0))
                 (match_operand:SI 1 "register_operand" "r")))]
  ""
  "subx\t%1, -1, %0"
  [(set_attr "type" "ialuX")])

(define_insn "*x_minus_sgeu"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_operand:SI 1 "register_operand" "r")
                  (geu:SI (reg:CC 100) (const_int 0))))]
  ""
  "addx\t%1, -1, %0"
  [(set_attr "type" "ialuX")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (match_operator:SI 2 "noov_compare_op"
                           [(match_operand 1 "icc_or_fcc_reg_operand" "")
                            (const_int 0)]))]
  ;; 32 bit LTU/GEU are better implemented using addx/subx
  "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG
   && (GET_MODE (operands[1]) == CCXmode
       || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
  [(set (match_dup 0) (const_int 0))
   (set (match_dup 0)
        (if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)])
                         (const_int 1)
                         (match_dup 0)))]
  "")

\f
;; These control RTL generation for conditional jump insns

;; The quad-word fp compare library routines all return nonzero to indicate
;; true, which is different from the equivalent libgcc routines, so we must
;; handle them specially here.

(define_expand "beq"
  [(set (pc)
        (if_then_else (eq (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bne"
  [(set (pc)
        (if_then_else (ne (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bgt"
  [(set (pc)
        (if_then_else (gt (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bgtu"
  [(set (pc)
        (if_then_else (gtu (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "blt"
  [(set (pc)
        (if_then_else (lt (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bltu"
  [(set (pc)
        (if_then_else (ltu (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bge"
  [(set (pc)
        (if_then_else (ge (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bgeu"
  [(set (pc)
        (if_then_else (geu (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "ble"
  [(set (pc)
        (if_then_else (le (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode)
    {
      emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]);
      DONE;
    }
  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bleu"
  [(set (pc)
        (if_then_else (leu (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bunordered"
  [(set (pc)
        (if_then_else (unordered (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1,
                                UNORDERED);
      emit_jump_insn (gen_beq (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0,
                                 sparc_compare_op1);
})

(define_expand "bordered"
  [(set (pc)
        (if_then_else (ordered (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, ORDERED);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0,
                                 sparc_compare_op1);
})

(define_expand "bungt"
  [(set (pc)
        (if_then_else (ungt (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGT);
      emit_jump_insn (gen_bgt (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bunlt"
  [(set (pc)
        (if_then_else (unlt (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLT);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "buneq"
  [(set (pc)
        (if_then_else (uneq (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNEQ);
      emit_jump_insn (gen_beq (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bunge"
  [(set (pc)
        (if_then_else (unge (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGE);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bunle"
  [(set (pc)
        (if_then_else (unle (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLE);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1);
})

(define_expand "bltgt"
  [(set (pc)
        (if_then_else (ltgt (match_dup 1) (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
{
  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
    {
      sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LTGT);
      emit_jump_insn (gen_bne (operands[0]));
      DONE;
    }
  operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1);
})
\f
;; Now match both normal and inverted jump.

;; XXX fpcmp nop braindamage
(define_insn "*normal_branch"
  [(set (pc)
        (if_then_else (match_operator 0 "noov_compare_op"
                                      [(reg 100) (const_int 0)])
                      (label_ref (match_operand 1 "" ""))
                      (pc)))]
  ""
{
  return output_cbranch (operands[0], operands[1], 1, 0,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "icc")])

;; XXX fpcmp nop braindamage
(define_insn "*inverted_branch"
  [(set (pc)
        (if_then_else (match_operator 0 "noov_compare_op"
                                      [(reg 100) (const_int 0)])
                      (pc)
                      (label_ref (match_operand 1 "" ""))))]
  ""
{
  return output_cbranch (operands[0], operands[1], 1, 1,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "icc")])

;; XXX fpcmp nop braindamage
(define_insn "*normal_fp_branch"
  [(set (pc)
        (if_then_else (match_operator 1 "comparison_operator"
                                      [(match_operand:CCFP 0 "fcc_reg_operand" "c")
                                       (const_int 0)])
                      (label_ref (match_operand 2 "" ""))
                      (pc)))]
  ""
{
  return output_cbranch (operands[1], operands[2], 2, 0,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "fcc")])

;; XXX fpcmp nop braindamage
(define_insn "*inverted_fp_branch"
  [(set (pc)
        (if_then_else (match_operator 1 "comparison_operator"
                                      [(match_operand:CCFP 0 "fcc_reg_operand" "c")
                                       (const_int 0)])
                      (pc)
                      (label_ref (match_operand 2 "" ""))))]
  ""
{
  return output_cbranch (operands[1], operands[2], 2, 1,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "fcc")])

;; XXX fpcmp nop braindamage
(define_insn "*normal_fpe_branch"
  [(set (pc)
        (if_then_else (match_operator 1 "comparison_operator"
                                      [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
                                       (const_int 0)])
                      (label_ref (match_operand 2 "" ""))
                      (pc)))]
  ""
{
  return output_cbranch (operands[1], operands[2], 2, 0,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "fcc")])

;; XXX fpcmp nop braindamage
(define_insn "*inverted_fpe_branch"
  [(set (pc)
        (if_then_else (match_operator 1 "comparison_operator"
                                      [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
                                       (const_int 0)])
                      (pc)
                      (label_ref (match_operand 2 "" ""))))]
  ""
{
  return output_cbranch (operands[1], operands[2], 2, 1,
                         final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                         ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "fcc")])

;; SPARC V9-specific jump insns.  None of these are guaranteed to be
;; in the architecture.

;; There are no 32 bit brreg insns.

;; XXX
(define_insn "*normal_int_branch_sp64"
  [(set (pc)
        (if_then_else (match_operator 0 "v9_regcmp_op"
                                      [(match_operand:DI 1 "register_operand" "r")
                                       (const_int 0)])
                      (label_ref (match_operand 2 "" ""))
                      (pc)))]
  "TARGET_ARCH64"
{
  return output_v9branch (operands[0], operands[2], 1, 2, 0,
                          final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                          ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "reg")])

;; XXX
(define_insn "*inverted_int_branch_sp64"
  [(set (pc)
        (if_then_else (match_operator 0 "v9_regcmp_op"
                                      [(match_operand:DI 1 "register_operand" "r")
                                       (const_int 0)])
                      (pc)
                      (label_ref (match_operand 2 "" ""))))]
  "TARGET_ARCH64"
{
  return output_v9branch (operands[0], operands[2], 1, 2, 1,
                          final_sequence && INSN_ANNULLED_BRANCH_P (insn),
                          ! final_sequence, insn);
}
  [(set_attr "type" "branch")
   (set_attr "branch_type" "reg")])
\f
;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
;; value subject to a PC-relative relocation.  Operand 2 is a helper function
;; that adds the PC value at the call point to operand 0.

(define_insn "load_pcrel_sym"
  [(set (match_operand 0 "register_operand" "=r")
        (unspec [(match_operand 1 "symbolic_operand" "")
                 (match_operand 2 "call_operand_address" "")] UNSPEC_LOAD_PCREL_SYM))
   (clobber (reg:SI 15))]
  ""
{
  if (flag_delayed_branch)
    return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
  else
    return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
}
  [(set (attr "type") (const_string "multi"))
   (set (attr "length")
        (if_then_else (eq_attr "delayed_branch" "true")
                      (const_int 3)
                      (const_int 4)))])
\f
;; Move instructions

(define_expand "movqi"
  [(set (match_operand:QI 0 "general_operand" "")
        (match_operand:QI 1 "general_operand" ""))]
  ""
{
  /* Working with CONST_INTs is easier, so convert
     a double if needed.  */
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    {
      operands[1] = GEN_INT (trunc_int_for_mode
                             (CONST_DOUBLE_LOW (operands[1]), QImode));
    }

  /* Handle sets of MEM first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (reg_or_0_operand (operands[1], QImode))
        goto movqi_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (QImode, operands[1]);
        }
    }

  /* Fixup TLS cases.  */
  if (tls_symbolic_operand (operands [1]))
    operands[1] = legitimize_tls_address (operands[1]);

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], QImode, 0);

      if (symbolic_operand (operands[1], QImode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                QImode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
          goto movqi_is_ok;
        }
    }

  /* All QI constants require only one insn, so proceed.  */

 movqi_is_ok:
  ;
})

(define_insn "*movqi_insn"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
        (match_operand:QI 1 "input_operand"   "rI,m,rJ"))]
  "(register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode))"
  "@
   mov\t%1, %0
   ldub\t%1, %0
   stb\t%r1, %0"
  [(set_attr "type" "*,load,store")
   (set_attr "us3load_type" "*,3cycle,*")])

(define_expand "movhi"
  [(set (match_operand:HI 0 "general_operand" "")
        (match_operand:HI 1 "general_operand" ""))]
  ""
{
  /* Working with CONST_INTs is easier, so convert
     a double if needed.  */
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));

  /* Handle sets of MEM first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (reg_or_0_operand (operands[1], HImode))
        goto movhi_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (HImode, operands[1]);
        }
    }

  /* Fixup TLS cases.  */
  if (tls_symbolic_operand (operands [1]))
    operands[1] = legitimize_tls_address (operands[1]);

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], HImode, 0);

      if (symbolic_operand (operands[1], HImode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                HImode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
          goto movhi_is_ok;
        }
    }

  /* This makes sure we will not get rematched due to splittage.  */
  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
    ;
  else if (CONSTANT_P (operands[1])
           && GET_CODE (operands[1]) != HIGH
           && GET_CODE (operands[1]) != LO_SUM)
    {
      sparc_emit_set_const32 (operands[0], operands[1]);
      DONE;
    }
 movhi_is_ok:
  ;
})

(define_insn "*movhi_const64_special"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (match_operand:HI 1 "const64_high_operand" ""))]
  "TARGET_ARCH64"
  "sethi\t%%hi(%a1), %0")

(define_insn "*movhi_insn"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
        (match_operand:HI 1 "input_operand"   "rI,K,m,rJ"))]
  "(register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode))"
  "@
   mov\t%1, %0
   sethi\t%%hi(%a1), %0
   lduh\t%1, %0
   sth\t%r1, %0"
  [(set_attr "type" "*,*,load,store")
   (set_attr "us3load_type" "*,*,3cycle,*")])

;; We always work with constants here.
(define_insn "*movhi_lo_sum"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (ior:HI (match_operand:HI 1 "register_operand" "%r")
                (match_operand:HI 2 "small_int" "I")))]
  ""
  "or\t%1, %2, %0")

(define_expand "movsi"
  [(set (match_operand:SI 0 "general_operand" "")
        (match_operand:SI 1 "general_operand" ""))]
  ""
{
  /* Working with CONST_INTs is easier, so convert
     a double if needed.  */
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));

  /* Handle sets of MEM first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (reg_or_0_operand (operands[1], SImode))
        goto movsi_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (SImode, operands[1]);
        }
    }

  /* Fixup TLS cases.  */
  if (tls_symbolic_operand (operands [1]))
    operands[1] = legitimize_tls_address (operands[1]);

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], SImode, 0);

      if (GET_CODE (operands[1]) == LABEL_REF)
        {
          /* shit */
          emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
          DONE;
        }

      if (symbolic_operand (operands[1], SImode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                SImode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
          goto movsi_is_ok;
        }
    }

  /* If we are trying to toss an integer constant into the
     FPU registers, force it into memory.  */
  if (GET_CODE (operands[0]) == REG
      && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
      && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
      && CONSTANT_P (operands[1]))
    operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                 operands[1]));

  /* This makes sure we will not get rematched due to splittage.  */
  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
    ;
  else if (CONSTANT_P (operands[1])
           && GET_CODE (operands[1]) != HIGH
           && GET_CODE (operands[1]) != LO_SUM)
    {
      sparc_emit_set_const32 (operands[0], operands[1]);
      DONE;
    }
 movsi_is_ok:
  ;
})

;; This is needed to show CSE exactly which bits are set
;; in a 64-bit register by sethi instructions.
(define_insn "*movsi_const64_special"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "const64_high_operand" ""))]
  "TARGET_ARCH64"
  "sethi\t%%hi(%a1), %0")

(define_insn "*movsi_insn"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
        (match_operand:SI 1 "input_operand"   "rI,!f,K,J,m,!m,rJ,!f,J"))]
  "(register_operand (operands[0], SImode)
    || reg_or_0_operand (operands[1], SImode))"
  "@
   mov\t%1, %0
   fmovs\t%1, %0
   sethi\t%%hi(%a1), %0
   clr\t%0
   ld\t%1, %0
   ld\t%1, %0
   st\t%r1, %0
   st\t%1, %0
   fzeros\t%0"
  [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fga")])

(define_insn "*movsi_lo_sum"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
                   (match_operand:SI 2 "immediate_operand" "in")))]
  ""
  "or\t%1, %%lo(%a2), %0")

(define_insn "*movsi_high"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
  ""
  "sethi\t%%hi(%a1), %0")

;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
;; so that CSE won't optimize the address computation away.
(define_insn "movsi_lo_sum_pic"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
                   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
  "flag_pic"
  "or\t%1, %%lo(%a2), %0")

(define_insn "movsi_high_pic"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
  "flag_pic && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_expand "movsi_pic_label_ref"
  [(set (match_dup 3) (high:SI
     (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
                 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
   (set (match_dup 4) (lo_sum:SI (match_dup 3)
     (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
   (set (match_operand:SI 0 "register_operand" "=r")
        (minus:SI (match_dup 5) (match_dup 4)))]
  "flag_pic"
{
  current_function_uses_pic_offset_table = 1;
  operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
  if (no_new_pseudos)
    {
      operands[3] = operands[0];
      operands[4] = operands[0];
    }
  else
    {
      operands[3] = gen_reg_rtx (SImode);
      operands[4] = gen_reg_rtx (SImode);
    }
  operands[5] = pic_offset_table_rtx;
})

(define_insn "*movsi_high_pic_label_ref"
  [(set (match_operand:SI 0 "register_operand" "=r")
      (high:SI
        (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
                    (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
  "flag_pic"
  "sethi\t%%hi(%a2-(%a1-.)), %0")

(define_insn "*movsi_lo_sum_pic_label_ref"
  [(set (match_operand:SI 0 "register_operand" "=r")
      (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
        (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
                    (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
  "flag_pic"
  "or\t%1, %%lo(%a3-(%a2-.)), %0")

(define_expand "movdi"
  [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
        (match_operand:DI 1 "general_operand" ""))]
  ""
{
  /* Where possible, convert CONST_DOUBLE into a CONST_INT.  */
  if (GET_CODE (operands[1]) == CONST_DOUBLE
#if HOST_BITS_PER_WIDE_INT == 32
      && ((CONST_DOUBLE_HIGH (operands[1]) == 0
           && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
          || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
              && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
#endif
      )
    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));

  /* Handle MEM cases first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      /* If it's a REG, we can always do it.
         The const zero case is more complex, on v9
         we can always perform it.  */
      if (register_operand (operands[1], DImode)
          || (TARGET_V9
              && (operands[1] == const0_rtx)))
        goto movdi_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (DImode, operands[1]);
        }
    }

  /* Fixup TLS cases.  */
  if (tls_symbolic_operand (operands [1]))
    operands[1] = legitimize_tls_address (operands[1]);

  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], DImode, 0);

      if (GET_CODE (operands[1]) == LABEL_REF)
        {
          if (! TARGET_ARCH64)
            abort ();
          emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
          DONE;
        }

      if (symbolic_operand (operands[1], DImode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                DImode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
          goto movdi_is_ok;
        }
    }

  /* If we are trying to toss an integer constant into the
     FPU registers, force it into memory.  */
  if (GET_CODE (operands[0]) == REG
      && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
      && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
      && CONSTANT_P (operands[1]))
    operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                 operands[1]));

  /* This makes sure we will not get rematched due to splittage.  */
  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
    ;
  else if (TARGET_ARCH64
           && CONSTANT_P (operands[1])
           && GET_CODE (operands[1]) != HIGH
           && GET_CODE (operands[1]) != LO_SUM)
    {
      sparc_emit_set_const64 (operands[0], operands[1]);
      DONE;
    }

 movdi_is_ok:
  ;
})

;; Be careful, fmovd does not exist when !v9.
;; We match MEM moves directly when we have correct even
;; numbered registers, but fall into splits otherwise.
;; The constraint ordering here is really important to
;; avoid insane problems in reload, especially for patterns
;; of the form:
;;
;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
;;                       (const_int -5016)))
;;      (reg:DI 2 %g2))
;;

(define_insn "*movdi_insn_sp32_v9"
  [(set (match_operand:DI 0 "nonimmediate_operand"
                                        "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
        (match_operand:DI 1 "input_operand"
                                        " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
  "! TARGET_ARCH64 && TARGET_V9
   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
  "@
   stx\t%%g0, %0
   #
   std\t%1, %0
   ldd\t%1, %0
   #
   #
   #
   #
   std\t%1, %0
   ldd\t%1, %0
   #
   #
   fmovd\\t%1, %0
   ldd\\t%1, %0
   std\\t%1, %0"
  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])

(define_insn "*movdi_insn_sp32"
  [(set (match_operand:DI 0 "nonimmediate_operand"
                                "=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
        (match_operand:DI 1 "input_operand"
                                " J,U,T,r,o,i,r, f, T, o, f, f"))]
  "! TARGET_ARCH64
   && (register_operand (operands[0], DImode)
       || register_operand (operands[1], DImode))"
  "@
   #
   std\t%1, %0
   ldd\t%1, %0
   #
   #
   #
   #
   std\t%1, %0
   ldd\t%1, %0
   #
   #
   #"
  [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
   (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])

;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_sp64_dbl"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (match_operand:DI 1 "const64_operand" ""))]
  "(TARGET_ARCH64
    && HOST_BITS_PER_WIDE_INT != 64)"
  "mov\t%1, %0")

;; This is needed to show CSE exactly which bits are set
;; in a 64-bit register by sethi instructions.
(define_insn "*movdi_const64_special"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (match_operand:DI 1 "const64_high_operand" ""))]
  "TARGET_ARCH64"
  "sethi\t%%hi(%a1), %0")

(define_insn "*movdi_insn_sp64_novis"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
        (match_operand:DI 1 "input_operand"   "rI,N,J,m,rJ,e,W,e"))]
  "TARGET_ARCH64 && ! TARGET_VIS
   && (register_operand (operands[0], DImode)
       || reg_or_0_operand (operands[1], DImode))"
  "@
   mov\t%1, %0
   sethi\t%%hi(%a1), %0
   clr\t%0
   ldx\t%1, %0
   stx\t%r1, %0
   fmovd\t%1, %0
   ldd\t%1, %0
   std\t%1, %0"
  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
   (set_attr "fptype" "*,*,*,*,*,double,*,*")])

(define_insn "*movdi_insn_sp64_vis"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
        (match_operand:DI 1 "input_operand"   "rI,N,J,m,rJ,e,W,e,J"))]
  "TARGET_ARCH64 && TARGET_VIS &&
   (register_operand (operands[0], DImode)
    || reg_or_0_operand (operands[1], DImode))"
  "@
   mov\t%1, %0
   sethi\t%%hi(%a1), %0
   clr\t%0
   ldx\t%1, %0
   stx\t%r1, %0
   fmovd\t%1, %0
   ldd\t%1, %0
   std\t%1, %0
   fzero\t%0"
  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fga")
   (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])

(define_expand "movdi_pic_label_ref"
  [(set (match_dup 3) (high:DI
     (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
                 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
   (set (match_dup 4) (lo_sum:DI (match_dup 3)
     (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
   (set (match_operand:DI 0 "register_operand" "=r")
        (minus:DI (match_dup 5) (match_dup 4)))]
  "TARGET_ARCH64 && flag_pic"
{
  current_function_uses_pic_offset_table = 1;
  operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
  if (no_new_pseudos)
    {
      operands[3] = operands[0];
      operands[4] = operands[0];
    }
  else
    {
      operands[3] = gen_reg_rtx (DImode);
      operands[4] = gen_reg_rtx (DImode);
    }
  operands[5] = pic_offset_table_rtx;
})

(define_insn "*movdi_high_pic_label_ref"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI
          (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
                      (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
  "TARGET_ARCH64 && flag_pic"
  "sethi\t%%hi(%a2-(%a1-.)), %0")

(define_insn "*movdi_lo_sum_pic_label_ref"
  [(set (match_operand:DI 0 "register_operand" "=r")
      (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
        (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
                    (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
  "TARGET_ARCH64 && flag_pic"
  "or\t%1, %%lo(%a3-(%a2-.)), %0")

;; SPARC-v9 code model support insns.  See sparc_emit_set_symbolic_const64
;; in sparc.c to see what is going on here... PIC stuff comes first.

(define_insn "movdi_lo_sum_pic"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
  "TARGET_ARCH64 && flag_pic"
  "or\t%1, %%lo(%a2), %0")

(define_insn "movdi_high_pic"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
  "TARGET_ARCH64 && flag_pic && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_insn "*sethi_di_medlow_embmedany_pic"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
  "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_insn "*sethi_di_medlow"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
  "TARGET_CM_MEDLOW && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_insn "*losum_di_medlow"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (match_operand:DI 2 "symbolic_operand" "")))]
  "TARGET_CM_MEDLOW"
  "or\t%1, %%lo(%a2), %0")

(define_insn "seth44"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
  "TARGET_CM_MEDMID"
  "sethi\t%%h44(%a1), %0")

(define_insn "setm44"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
  "TARGET_CM_MEDMID"
  "or\t%1, %%m44(%a2), %0")

(define_insn "setl44"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (match_operand:DI 2 "symbolic_operand" "")))]
  "TARGET_CM_MEDMID"
  "or\t%1, %%l44(%a2), %0")

(define_insn "sethh"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
  "TARGET_CM_MEDANY"
  "sethi\t%%hh(%a1), %0")

(define_insn "setlm"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
  "TARGET_CM_MEDANY"
  "sethi\t%%lm(%a1), %0")

(define_insn "sethm"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
  "TARGET_CM_MEDANY"
  "or\t%1, %%hm(%a2), %0")

(define_insn "setlo"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (match_operand:DI 2 "symbolic_operand" "")))]
  "TARGET_CM_MEDANY"
  "or\t%1, %%lo(%a2), %0")

(define_insn "embmedany_sethi"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
  "TARGET_CM_EMBMEDANY && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_insn "embmedany_losum"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (match_operand:DI 2 "data_segment_operand" "")))]
  "TARGET_CM_EMBMEDANY"
  "add\t%1, %%lo(%a2), %0")

(define_insn "embmedany_brsum"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
  "TARGET_CM_EMBMEDANY"
  "add\t%1, %_, %0")

(define_insn "embmedany_textuhi"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
  "TARGET_CM_EMBMEDANY && check_pic (1)"
  "sethi\t%%uhi(%a1), %0")

(define_insn "embmedany_texthi"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
  "TARGET_CM_EMBMEDANY && check_pic (1)"
  "sethi\t%%hi(%a1), %0")

(define_insn "embmedany_textulo"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
  "TARGET_CM_EMBMEDANY"
  "or\t%1, %%ulo(%a2), %0")

(define_insn "embmedany_textlo"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                   (match_operand:DI 2 "text_segment_operand" "")))]
  "TARGET_CM_EMBMEDANY"
  "or\t%1, %%lo(%a2), %0")

;; Now some patterns to help reload out a bit.
(define_expand "reload_indi"
  [(parallel [(match_operand:DI 0 "register_operand" "=r")
              (match_operand:DI 1 "immediate_operand" "")
              (match_operand:TI 2 "register_operand" "=&r")])]
  "(TARGET_CM_MEDANY
    || TARGET_CM_EMBMEDANY)
   && ! flag_pic"
{
  sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
  DONE;
})

(define_expand "reload_outdi"
  [(parallel [(match_operand:DI 0 "register_operand" "=r")
              (match_operand:DI 1 "immediate_operand" "")
              (match_operand:TI 2 "register_operand" "=&r")])]
  "(TARGET_CM_MEDANY
    || TARGET_CM_EMBMEDANY)
   && ! flag_pic"
{
  sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
  DONE;
})

;; Split up putting CONSTs and REGs into DI regs when !arch64
(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (match_operand:DI 1 "const_int_operand" ""))]
  "! TARGET_ARCH64 && reload_completed"
  [(clobber (const_int 0))]
{
#if HOST_BITS_PER_WIDE_INT == 32
  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
                        (INTVAL (operands[1]) < 0) ?
                        constm1_rtx :
                        const0_rtx));
  emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                        operands[1]));
#else
  unsigned int low, high;

  low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
  high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));

  /* Slick... but this trick loses if this subreg constant part
     can be done in one insn.  */
  if (low == high && (low & 0x3ff) != 0 && low + 0x1000 >= 0x2000)
    emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                          gen_highpart (SImode, operands[0])));
  else
    emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
#endif
  DONE;
})

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (match_operand:DI 1 "const_double_operand" ""))]
  "reload_completed
   && (! TARGET_V9
       || (! TARGET_ARCH64
           && ((GET_CODE (operands[0]) == REG
                && REGNO (operands[0]) < 32)
               || (GET_CODE (operands[0]) == SUBREG
                   && GET_CODE (SUBREG_REG (operands[0])) == REG
                   && REGNO (SUBREG_REG (operands[0])) < 32))))"
  [(clobber (const_int 0))]
{
  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
                        GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));

  /* Slick... but this trick loses if this subreg constant part
     can be done in one insn.  */
  if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1])
      && !(SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1]))
           || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1]))))
    {
      emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                            gen_highpart (SImode, operands[0])));
    }
  else
    {
      emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                            GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
    }
  DONE;
})

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (match_operand:DI 1 "register_operand" ""))]
  "reload_completed
   && (! TARGET_V9
       || (! TARGET_ARCH64
           && ((GET_CODE (operands[0]) == REG
                && REGNO (operands[0]) < 32)
               || (GET_CODE (operands[0]) == SUBREG
                   && GET_CODE (SUBREG_REG (operands[0])) == REG
                   && REGNO (SUBREG_REG (operands[0])) < 32))))"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx set_src = operands[1];
  rtx dest1, dest2;
  rtx src1, src2;

  dest1 = gen_highpart (SImode, set_dest);
  dest2 = gen_lowpart (SImode, set_dest);
  src1 = gen_highpart (SImode, set_src);
  src2 = gen_lowpart (SImode, set_src);

  /* Now emit using the real source and destination we found, swapping
     the order if we detect overlap.  */
  if (reg_overlap_mentioned_p (dest1, src2))
    {
      emit_insn (gen_movsi (dest2, src2));
      emit_insn (gen_movsi (dest1, src1));
    }
  else
    {
      emit_insn (gen_movsi (dest1, src1));
      emit_insn (gen_movsi (dest2, src2));
    }
  DONE;
})

;; Now handle the cases of memory moves from/to non-even
;; DI mode register pairs.
(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (match_operand:DI 1 "memory_operand" ""))]
  "(! TARGET_ARCH64
    && reload_completed
    && sparc_splitdi_legitimate (operands[0], operands[1]))"
  [(clobber (const_int 0))]
{
  rtx word0 = adjust_address (operands[1], SImode, 0);
  rtx word1 = adjust_address (operands[1], SImode, 4);
  rtx high_part = gen_highpart (SImode, operands[0]);
  rtx low_part = gen_lowpart (SImode, operands[0]);

  if (reg_overlap_mentioned_p (high_part, word1))
    {
      emit_insn (gen_movsi (low_part, word1));
      emit_insn (gen_movsi (high_part, word0));
    }
  else
    {
      emit_insn (gen_movsi (high_part, word0));
      emit_insn (gen_movsi (low_part, word1));
    }
  DONE;
})

(define_split
  [(set (match_operand:DI 0 "memory_operand" "")
        (match_operand:DI 1 "register_operand" ""))]
  "(! TARGET_ARCH64
    && reload_completed
    && sparc_splitdi_legitimate (operands[1], operands[0]))"
  [(clobber (const_int 0))]
{
  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0),
                        gen_highpart (SImode, operands[1])));
  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4),
                        gen_lowpart (SImode, operands[1])));
  DONE;
})

(define_split
  [(set (match_operand:DI 0 "memory_operand" "")
        (const_int 0))]
  "reload_completed
   && (! TARGET_V9
       || (! TARGET_ARCH64
           && ! mem_min_alignment (operands[0], 8)))
   && offsettable_memref_p (operands[0])"
  [(clobber (const_int 0))]
{
  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
  emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
  DONE;
})
\f
;; Floating point move insns

(define_insn "*movsf_insn_novis"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
        (match_operand:SF 1 "input_operand"         "f,G,Q,*rR,S,m,m,f,*rG"))]
  "(TARGET_FPU && ! TARGET_VIS)
   && (register_operand (operands[0], SFmode)
       || register_operand (operands[1], SFmode)
       || fp_zero_operand (operands[1], SFmode))"
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE
      && (which_alternative == 2
          || which_alternative == 3
          || which_alternative == 4))
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      operands[1] = GEN_INT (i);
    }

  switch (which_alternative)
    {
    case 0:
      return "fmovs\t%1, %0";
    case 1:
      return "clr\t%0";
    case 2:
      return "sethi\t%%hi(%a1), %0";
    case 3:
      return "mov\t%1, %0";
    case 4:
      return "#";
    case 5:
    case 6:
      return "ld\t%1, %0";
    case 7:
    case 8:
      return "st\t%r1, %0";
    default:
      abort();
    }
}
  [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])

(define_insn "*movsf_insn_vis"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
        (match_operand:SF 1 "input_operand"         "f,G,G,Q,*rR,S,m,m,f,*rG"))]
  "(TARGET_FPU && TARGET_VIS)
   && (register_operand (operands[0], SFmode)
       || register_operand (operands[1], SFmode)
       || fp_zero_operand (operands[1], SFmode))"
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE
      && (which_alternative == 3
          || which_alternative == 4
          || which_alternative == 5))
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      operands[1] = GEN_INT (i);
    }

  switch (which_alternative)
    {
    case 0:
      return "fmovs\t%1, %0";
    case 1:
      return "fzeros\t%0";
    case 2:
      return "clr\t%0";
    case 3:
      return "sethi\t%%hi(%a1), %0";
    case 4:
      return "mov\t%1, %0";
    case 5:
      return "#";
    case 6:
    case 7:
      return "ld\t%1, %0";
    case 8:
    case 9:
      return "st\t%r1, %0";
    default:
      abort();
    }
}
  [(set_attr "type" "fpmove,fga,*,*,*,*,load,fpload,fpstore,store")])

;; Exactly the same as above, except that all `f' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `f' reg
;; when -mno-fpu.

(define_insn "*movsf_no_f_insn"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,m")
        (match_operand:SF 1 "input_operand"    "G,Q,rR,S,m,rG"))]
  "! TARGET_FPU
   && (register_operand (operands[0], SFmode)
       || register_operand (operands[1], SFmode)
       || fp_zero_operand (operands[1], SFmode))"
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE
      && (which_alternative == 1
          || which_alternative == 2
          || which_alternative == 3))
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      operands[1] = GEN_INT (i);
    }

  switch (which_alternative)
    {
    case 0:
      return "clr\t%0";
    case 1:
      return "sethi\t%%hi(%a1), %0";
    case 2:
      return "mov\t%1, %0";
    case 3:
      return "#";
    case 4:
      return "ld\t%1, %0";
    case 5:
      return "st\t%r1, %0";
    default:
      abort();
    }
}
  [(set_attr "type" "*,*,*,*,load,store")])

(define_insn "*movsf_lo_sum"
  [(set (match_operand:SF 0 "register_operand" "=r")
        (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
                   (match_operand:SF 2 "const_double_operand" "S")))]
  "fp_high_losum_p (operands[2])"
{
  REAL_VALUE_TYPE r;
  long i;

  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
  REAL_VALUE_TO_TARGET_SINGLE (r, i);
  operands[2] = GEN_INT (i);
  return "or\t%1, %%lo(%a2), %0";
})

(define_insn "*movsf_high"
  [(set (match_operand:SF 0 "register_operand" "=r")
        (high:SF (match_operand:SF 1 "const_double_operand" "S")))]
  "fp_high_losum_p (operands[1])"
{
  REAL_VALUE_TYPE r;
  long i;

  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
  REAL_VALUE_TO_TARGET_SINGLE (r, i);
  operands[1] = GEN_INT (i);
  return "sethi\t%%hi(%1), %0";
})

(define_split
  [(set (match_operand:SF 0 "register_operand" "")
        (match_operand:SF 1 "const_double_operand" ""))]
  "fp_high_losum_p (operands[1])
   && (GET_CODE (operands[0]) == REG
       && REGNO (operands[0]) < 32)"
  [(set (match_dup 0) (high:SF (match_dup 1)))
   (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])

(define_expand "movsf"
  [(set (match_operand:SF 0 "general_operand" "")
        (match_operand:SF 1 "general_operand" ""))]
  ""
{
  /* Force SFmode constants into memory.  */
  if (GET_CODE (operands[0]) == REG
      && CONSTANT_P (operands[1]))
    {
      /* emit_group_store will send such bogosity to us when it is
         not storing directly into memory.  So fix this up to avoid
         crashes in output_constant_pool.  */
      if (operands [1] == const0_rtx)
        operands[1] = CONST0_RTX (SFmode);

      if (TARGET_VIS && fp_zero_operand (operands[1], SFmode))
        goto movsf_is_ok;

      /* We are able to build any SF constant in integer registers
         with at most 2 instructions.  */
      if (REGNO (operands[0]) < 32)
        goto movsf_is_ok;

      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                   operands[1]));
    }

  /* Handle sets of MEM first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (register_operand (operands[1], SFmode)
          || fp_zero_operand (operands[1], SFmode))
        goto movsf_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (SFmode, operands[1]);
        }
    }

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], SFmode, 0);

      if (symbolic_operand (operands[1], SFmode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                SFmode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
        }
    }

 movsf_is_ok:
  ;
})

(define_expand "movdf"
  [(set (match_operand:DF 0 "general_operand" "")
        (match_operand:DF 1 "general_operand" ""))]
  ""
{
  /* Force DFmode constants into memory.  */
  if (GET_CODE (operands[0]) == REG
      && CONSTANT_P (operands[1]))
    {
      /* emit_group_store will send such bogosity to us when it is
         not storing directly into memory.  So fix this up to avoid
         crashes in output_constant_pool.  */
      if (operands [1] == const0_rtx)
        operands[1] = CONST0_RTX (DFmode);

      if ((TARGET_VIS || REGNO (operands[0]) < 32)
          && fp_zero_operand (operands[1], DFmode))
        goto movdf_is_ok;

      /* We are able to build any DF constant in integer registers.  */
      if (REGNO (operands[0]) < 32
          && (reload_completed || reload_in_progress))
        goto movdf_is_ok;

      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                   operands[1]));
    }

  /* Handle MEM cases first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (register_operand (operands[1], DFmode)
          || fp_zero_operand (operands[1], DFmode))
        goto movdf_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (DFmode, operands[1]);
        }
    }

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], DFmode, 0);

      if (symbolic_operand (operands[1], DFmode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                DFmode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
        }
    }

 movdf_is_ok:
  ;
})

;; Be careful, fmovd does not exist when !v9.
(define_insn "*movdf_insn_sp32"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
        (match_operand:DF 1 "input_operand"    "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
  "TARGET_FPU
   && ! TARGET_V9
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  ldd\t%1, %0
  std\t%1, %0
  ldd\t%1, %0
  std\t%1, %0
  #
  #
  #
  #
  #
  #"
 [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
  (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])

(define_insn "*movdf_no_e_insn_sp32"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
        (match_operand:DF 1 "input_operand"    "T,U,G,ro,r"))]
  "! TARGET_FPU
   && ! TARGET_V9
   && ! TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  ldd\t%1, %0
  std\t%1, %0
  #
  #
  #"
  [(set_attr "type" "load,store,*,*,*")
   (set_attr "length" "*,*,2,2,2")])

(define_insn "*movdf_no_e_insn_v9_sp32"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
        (match_operand:DF 1 "input_operand"    "T,U,G,ro,rG"))]
  "! TARGET_FPU
   && TARGET_V9
   && ! TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  ldd\t%1, %0
  std\t%1, %0
  stx\t%r1, %0
  #
  #"
  [(set_attr "type" "load,store,store,*,*")
   (set_attr "length" "*,*,*,2,2")])

;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS.
(define_insn "*movdf_insn_v9only_novis"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
        (match_operand:DF 1 "input_operand"    "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
  "TARGET_FPU
   && TARGET_V9
   && ! TARGET_VIS
   && ! TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  fmovd\t%1, %0
  ldd\t%1, %0
  stx\t%r1, %0
  std\t%1, %0
  ldd\t%1, %0
  std\t%1, %0
  #
  #
  #"
  [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
   (set_attr "length" "*,*,*,*,*,*,2,2,2")
   (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])

;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
(define_insn "*movdf_insn_v9only_vis"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
        (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
  "TARGET_FPU
   && TARGET_VIS
   && ! TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  fzero\t%0
  fmovd\t%1, %0
  ldd\t%1, %0
  stx\t%r1, %0
  std\t%1, %0
  ldd\t%1, %0
  std\t%1, %0
  #
  #
  #"
  [(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
   (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
   (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])

;; We have available both v9 double floats and 64-bit
;; integer registers. No VIS though.
(define_insn "*movdf_insn_sp64_novis"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r")
        (match_operand:DF 1 "input_operand"    "e,W#F,e,*rG,m,*rG,F"))]
  "TARGET_FPU
   && ! TARGET_VIS
   && TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  fmovd\t%1, %0
  ldd\t%1, %0
  std\t%1, %0
  mov\t%r1, %0
  ldx\t%1, %0
  stx\t%r1, %0
  #"
  [(set_attr "type" "fpmove,load,store,*,load,store,*")
   (set_attr "length" "*,*,*,*,*,*,2")
   (set_attr "fptype" "double,*,*,*,*,*,*")])

;; We have available both v9 double floats and 64-bit
;; integer registers. And we have VIS.
(define_insn "*movdf_insn_sp64_vis"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
        (match_operand:DF 1 "input_operand"    "G,e,W#F,e,*rG,m,*rG,F"))]
  "TARGET_FPU
   && TARGET_VIS
   && TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  fzero\t%0
  fmovd\t%1, %0
  ldd\t%1, %0
  std\t%1, %0
  mov\t%r1, %0
  ldx\t%1, %0
  stx\t%r1, %0
  #"
  [(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
   (set_attr "length" "*,*,*,*,*,*,*,2")
   (set_attr "fptype" "double,double,*,*,*,*,*,*")])

(define_insn "*movdf_no_e_insn_sp64"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
        (match_operand:DF 1 "input_operand"    "r,m,rG"))]
  "! TARGET_FPU
   && TARGET_ARCH64
   && (register_operand (operands[0], DFmode)
       || register_operand (operands[1], DFmode)
       || fp_zero_operand (operands[1], DFmode))"
  "@
  mov\t%1, %0
  ldx\t%1, %0
  stx\t%r1, %0"
  [(set_attr "type" "*,load,store")])

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
        (match_operand:DF 1 "const_double_operand" ""))]
  "TARGET_FPU
   && (GET_CODE (operands[0]) == REG
       && REGNO (operands[0]) < 32)
   && ! fp_zero_operand(operands[1], DFmode)
   && reload_completed"
  [(clobber (const_int 0))]
{
  REAL_VALUE_TYPE r;
  long l[2];

  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
  operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));

  if (TARGET_ARCH64)
    {
#if HOST_BITS_PER_WIDE_INT == 64
      HOST_WIDE_INT val;

      val = ((HOST_WIDE_INT)(unsigned long)l[1] |
             ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
      emit_insn (gen_movdi (operands[0], GEN_INT (val)));
#else
      emit_insn (gen_movdi (operands[0],
                            immed_double_const (l[1], l[0], DImode)));
#endif
    }
  else
    {
      emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
                            GEN_INT (l[0])));

      /* Slick... but this trick loses if this subreg constant part
         can be done in one insn.  */
      if (l[1] == l[0]
          && !(SPARC_SETHI32_P (l[0])
               || SPARC_SIMM13_P (l[0])))
        {
          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                                gen_highpart (SImode, operands[0])));
        }
      else
        {
          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
                                GEN_INT (l[1])));
        }
    }
  DONE;
})

;; Ok, now the splits to handle all the multi insn and
;; mis-aligned memory address cases.
;; In these splits please take note that we must be
;; careful when V9 but not ARCH64 because the integer
;; register DFmode cases must be handled.
(define_split
  [(set (match_operand:DF 0 "register_operand" "")
        (match_operand:DF 1 "register_operand" ""))]
  "(! TARGET_V9
    || (! TARGET_ARCH64
        && ((GET_CODE (operands[0]) == REG
             && REGNO (operands[0]) < 32)
            || (GET_CODE (operands[0]) == SUBREG
                && GET_CODE (SUBREG_REG (operands[0])) == REG
                && REGNO (SUBREG_REG (operands[0])) < 32))))
   && reload_completed"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx set_src = operands[1];
  rtx dest1, dest2;
  rtx src1, src2;

  dest1 = gen_highpart (SFmode, set_dest);
  dest2 = gen_lowpart (SFmode, set_dest);
  src1 = gen_highpart (SFmode, set_src);
  src2 = gen_lowpart (SFmode, set_src);

  /* Now emit using the real source and destination we found, swapping
     the order if we detect overlap.  */
  if (reg_overlap_mentioned_p (dest1, src2))
    {
      emit_insn (gen_movsf (dest2, src2));
      emit_insn (gen_movsf (dest1, src1));
    }
  else
    {
      emit_insn (gen_movsf (dest1, src1));
      emit_insn (gen_movsf (dest2, src2));
    }
  DONE;
})

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
        (match_operand:DF 1 "memory_operand" ""))]
  "reload_completed
   && ! TARGET_ARCH64
   && (((REGNO (operands[0]) % 2) != 0)
       || ! mem_min_alignment (operands[1], 8))
   && offsettable_memref_p (operands[1])"
  [(clobber (const_int 0))]
{
  rtx word0 = adjust_address (operands[1], SFmode, 0);
  rtx word1 = adjust_address (operands[1], SFmode, 4);

  if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
    {
      emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
                            word1));
      emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
                            word0));
    }
  else
    {
      emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
                            word0));
      emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
                            word1));
    }
  DONE;
})

(define_split
  [(set (match_operand:DF 0 "memory_operand" "")
        (match_operand:DF 1 "register_operand" ""))]
  "reload_completed
   && ! TARGET_ARCH64
   && (((REGNO (operands[1]) % 2) != 0)
       || ! mem_min_alignment (operands[0], 8))
   && offsettable_memref_p (operands[0])"
  [(clobber (const_int 0))]
{
  rtx word0 = adjust_address (operands[0], SFmode, 0);
  rtx word1 = adjust_address (operands[0], SFmode, 4);

  emit_insn (gen_movsf (word0,
                        gen_highpart (SFmode, operands[1])));
  emit_insn (gen_movsf (word1,
                        gen_lowpart (SFmode, operands[1])));
  DONE;
})

(define_split
  [(set (match_operand:DF 0 "memory_operand" "")
        (match_operand:DF 1 "fp_zero_operand" ""))]
  "reload_completed
   && (! TARGET_V9
       || (! TARGET_ARCH64
           && ! mem_min_alignment (operands[0], 8)))
   && offsettable_memref_p (operands[0])"
  [(clobber (const_int 0))]
{
  rtx dest1, dest2;

  dest1 = adjust_address (operands[0], SFmode, 0);
  dest2 = adjust_address (operands[0], SFmode, 4);

  emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
  emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
  DONE;
})

(define_split
  [(set (match_operand:DF 0 "register_operand" "")
        (match_operand:DF 1 "fp_zero_operand" ""))]
  "reload_completed
   && ! TARGET_ARCH64
   && ((GET_CODE (operands[0]) == REG
        && REGNO (operands[0]) < 32)
       || (GET_CODE (operands[0]) == SUBREG
           && GET_CODE (SUBREG_REG (operands[0])) == REG
           && REGNO (SUBREG_REG (operands[0])) < 32))"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx dest1, dest2;

  dest1 = gen_highpart (SFmode, set_dest);
  dest2 = gen_lowpart (SFmode, set_dest);
  emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
  emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
  DONE;
})

(define_expand "movtf"
  [(set (match_operand:TF 0 "general_operand" "")
        (match_operand:TF 1 "general_operand" ""))]
  ""
{
  /* Force TFmode constants into memory.  */
  if (GET_CODE (operands[0]) == REG
      && CONSTANT_P (operands[1]))
    {
      /* emit_group_store will send such bogosity to us when it is
         not storing directly into memory.  So fix this up to avoid
         crashes in output_constant_pool.  */
      if (operands [1] == const0_rtx)
        operands[1] = CONST0_RTX (TFmode);

      if (TARGET_VIS && fp_zero_operand (operands[1], TFmode))
        goto movtf_is_ok;

      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
                                                   operands[1]));
    }

  /* Handle MEM cases first, note that only v9 guarantees
     full 16-byte alignment for quads.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      if (register_operand (operands[1], TFmode)
          || fp_zero_operand (operands[1], TFmode))
        goto movtf_is_ok;

      if (! reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (TFmode, operands[1]);
        }
    }

  /* Fixup PIC cases.  */
  if (flag_pic)
    {
      if (CONSTANT_P (operands[1])
          && pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], TFmode, 0);

      if (symbolic_operand (operands[1], TFmode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                TFmode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
        }
    }

 movtf_is_ok:
  ;
})

;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
;; we must split them all.  :-(
(define_insn "*movtf_insn_sp32"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
        (match_operand:TF 1 "input_operand"    "oe,GeUr,o,roG"))]
  "TARGET_FPU
   && ! TARGET_VIS
   && ! TARGET_ARCH64
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "4")])

(define_insn "*movtf_insn_vis_sp32"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
        (match_operand:TF 1 "input_operand"    "Goe,GeUr,o,roG"))]
  "TARGET_FPU
   && TARGET_VIS
   && ! TARGET_ARCH64
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "4")])

;; Exactly the same as above, except that all `e' cases are deleted.
;; This is necessary to prevent reload from ever trying to use a `e' reg
;; when -mno-fpu.

(define_insn "*movtf_no_e_insn_sp32"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
        (match_operand:TF 1 "input_operand"    "G,o,U,roG,r"))]
  "! TARGET_FPU
   && ! TARGET_ARCH64
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "4")])

;; Now handle the float reg cases directly when arch64,
;; hard_quad, and proper reg number alignment are all true.
(define_insn "*movtf_insn_hq_sp64"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
        (match_operand:TF 1 "input_operand"    "e,m,e,Gr,roG"))]
  "TARGET_FPU
   && ! TARGET_VIS
   && TARGET_ARCH64
   && TARGET_HARD_QUAD
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "@
  fmovq\t%1, %0
  ldq\t%1, %0
  stq\t%1, %0
  #
  #"
  [(set_attr "type" "fpmove,fpload,fpstore,*,*")
   (set_attr "length" "*,*,*,2,2")])

(define_insn "*movtf_insn_hq_vis_sp64"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
        (match_operand:TF 1 "input_operand"    "e,m,e,G,roG,r"))]
  "TARGET_FPU
   && TARGET_VIS
   && TARGET_ARCH64
   && TARGET_HARD_QUAD
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "@
  fmovq\t%1, %0
  ldq\t%1, %0
  stq\t%1, %0
  #
  #
  #"
  [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
   (set_attr "length" "*,*,*,2,2,2")])

;; Now we allow the integer register cases even when
;; only arch64 is true.
(define_insn "*movtf_insn_sp64"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
        (match_operand:TF 1 "input_operand"    "oe,Ger,orG"))]
  "TARGET_FPU
   && ! TARGET_VIS
   && TARGET_ARCH64
   && ! TARGET_HARD_QUAD
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "2")])

(define_insn "*movtf_insn_vis_sp64"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
        (match_operand:TF 1 "input_operand"    "Goe,Ger,orG"))]
  "TARGET_FPU
   && TARGET_VIS
   && TARGET_ARCH64
   && ! TARGET_HARD_QUAD
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "2")])

(define_insn "*movtf_no_e_insn_sp64"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
        (match_operand:TF 1 "input_operand"    "orG,rG"))]
  "! TARGET_FPU
   && TARGET_ARCH64
   && (register_operand (operands[0], TFmode)
       || register_operand (operands[1], TFmode)
       || fp_zero_operand (operands[1], TFmode))"
  "#"
  [(set_attr "length" "2")])

;; Now all the splits to handle multi-insn TF mode moves.
(define_split
  [(set (match_operand:TF 0 "register_operand" "")
        (match_operand:TF 1 "register_operand" ""))]
  "reload_completed
   && (! TARGET_ARCH64
       || (TARGET_FPU
           && ! TARGET_HARD_QUAD)
       || ! fp_register_operand (operands[0], TFmode))"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx set_src = operands[1];
  rtx dest1, dest2;
  rtx src1, src2;

  dest1 = gen_df_reg (set_dest, 0);
  dest2 = gen_df_reg (set_dest, 1);
  src1 = gen_df_reg (set_src, 0);
  src2 = gen_df_reg (set_src, 1);

  /* Now emit using the real source and destination we found, swapping
     the order if we detect overlap.  */
  if (reg_overlap_mentioned_p (dest1, src2))
    {
      emit_insn (gen_movdf (dest2, src2));
      emit_insn (gen_movdf (dest1, src1));
    }
  else
    {
      emit_insn (gen_movdf (dest1, src1));
      emit_insn (gen_movdf (dest2, src2));
    }
  DONE;
})

(define_split
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
        (match_operand:TF 1 "fp_zero_operand" ""))]
  "reload_completed"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx dest1, dest2;

  switch (GET_CODE (set_dest))
    {
    case REG:
      dest1 = gen_df_reg (set_dest, 0);
      dest2 = gen_df_reg (set_dest, 1);
      break;
    case MEM:
      dest1 = adjust_address (set_dest, DFmode, 0);
      dest2 = adjust_address (set_dest, DFmode, 8);
      break;
    default:
      abort ();      
    }

  emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
  emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
  DONE;
})

(define_split
  [(set (match_operand:TF 0 "register_operand" "")
        (match_operand:TF 1 "memory_operand" ""))]
  "(reload_completed
    && offsettable_memref_p (operands[1])
    && (! TARGET_ARCH64
        || ! TARGET_HARD_QUAD
        || ! fp_register_operand (operands[0], TFmode)))"
  [(clobber (const_int 0))]
{
  rtx word0 = adjust_address (operands[1], DFmode, 0);
  rtx word1 = adjust_address (operands[1], DFmode, 8);
  rtx set_dest, dest1, dest2;

  set_dest = operands[0];

  dest1 = gen_df_reg (set_dest, 0);
  dest2 = gen_df_reg (set_dest, 1);

  /* Now output, ordering such that we don't clobber any registers
     mentioned in the address.  */
  if (reg_overlap_mentioned_p (dest1, word1))

    {
      emit_insn (gen_movdf (dest2, word1));
      emit_insn (gen_movdf (dest1, word0));
    }
  else
   {
      emit_insn (gen_movdf (dest1, word0));
      emit_insn (gen_movdf (dest2, word1));
   }
  DONE;
})

(define_split
  [(set (match_operand:TF 0 "memory_operand" "")
        (match_operand:TF 1 "register_operand" ""))]
  "(reload_completed
    && offsettable_memref_p (operands[0])
    && (! TARGET_ARCH64
        || ! TARGET_HARD_QUAD
        || ! fp_register_operand (operands[1], TFmode)))"
  [(clobber (const_int 0))]
{
  rtx set_src = operands[1];

  emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
                        gen_df_reg (set_src, 0)));
  emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
                        gen_df_reg (set_src, 1)));
  DONE;
})
\f
;; SPARC V9 conditional move instructions.

;; We can handle larger constants here for some flavors, but for now we keep
;; it simple and only allow those constants supported by all flavors.
;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
;; 3 contains the constant if one is present, but we handle either for
;; generality (sparc.c puts a constant in operand 2).

(define_expand "movqicc"
  [(set (match_operand:QI 0 "register_operand" "")
        (if_then_else:QI (match_operand 1 "comparison_operator" "")
                         (match_operand:QI 2 "arith10_operand" "")
                         (match_operand:QI 3 "arith10_operand" "")))]
  "TARGET_V9"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (GET_MODE (sparc_compare_op0) == DImode
      && ! TARGET_ARCH64)
    FAIL;

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
    }
})

(define_expand "movhicc"
  [(set (match_operand:HI 0 "register_operand" "")
        (if_then_else:HI (match_operand 1 "comparison_operator" "")
                         (match_operand:HI 2 "arith10_operand" "")
                         (match_operand:HI 3 "arith10_operand" "")))]
  "TARGET_V9"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (GET_MODE (sparc_compare_op0) == DImode
      && ! TARGET_ARCH64)
    FAIL;

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
    }
})

(define_expand "movsicc"
  [(set (match_operand:SI 0 "register_operand" "")
        (if_then_else:SI (match_operand 1 "comparison_operator" "")
                         (match_operand:SI 2 "arith10_operand" "")
                         (match_operand:SI 3 "arith10_operand" "")))]
  "TARGET_V9"
{
  enum rtx_code code = GET_CODE (operands[1]);
  enum machine_mode op0_mode = GET_MODE (sparc_compare_op0);

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && (TARGET_ARCH64 && op0_mode == DImode && v9_regcmp_p (code)))
    {
      operands[1] = gen_rtx_fmt_ee (code, op0_mode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
                                    cc_reg, const0_rtx);
    }
})

(define_expand "movdicc"
  [(set (match_operand:DI 0 "register_operand" "")
        (if_then_else:DI (match_operand 1 "comparison_operator" "")
                         (match_operand:DI 2 "arith10_double_operand" "")
                         (match_operand:DI 3 "arith10_double_operand" "")))]
  "TARGET_ARCH64"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
                                    cc_reg, const0_rtx);
    }
})

(define_expand "movsfcc"
  [(set (match_operand:SF 0 "register_operand" "")
        (if_then_else:SF (match_operand 1 "comparison_operator" "")
                         (match_operand:SF 2 "register_operand" "")
                         (match_operand:SF 3 "register_operand" "")))]
  "TARGET_V9 && TARGET_FPU"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (GET_MODE (sparc_compare_op0) == DImode
      && ! TARGET_ARCH64)
    FAIL;

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
    }
})

(define_expand "movdfcc"
  [(set (match_operand:DF 0 "register_operand" "")
        (if_then_else:DF (match_operand 1 "comparison_operator" "")
                         (match_operand:DF 2 "register_operand" "")
                         (match_operand:DF 3 "register_operand" "")))]
  "TARGET_V9 && TARGET_FPU"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (GET_MODE (sparc_compare_op0) == DImode
      && ! TARGET_ARCH64)
    FAIL;

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
    }
})

(define_expand "movtfcc"
  [(set (match_operand:TF 0 "register_operand" "")
        (if_then_else:TF (match_operand 1 "comparison_operator" "")
                         (match_operand:TF 2 "register_operand" "")
                         (match_operand:TF 3 "register_operand" "")))]
  "TARGET_V9 && TARGET_FPU"
{
  enum rtx_code code = GET_CODE (operands[1]);

  if (GET_MODE (sparc_compare_op0) == DImode
      && ! TARGET_ARCH64)
    FAIL;

  if (sparc_compare_op1 == const0_rtx
      && GET_CODE (sparc_compare_op0) == REG
      && GET_MODE (sparc_compare_op0) == DImode
      && v9_regcmp_p (code))
    {
      operands[1] = gen_rtx_fmt_ee (code, DImode,
                             sparc_compare_op0, sparc_compare_op1);
    }
  else
    {
      rtx cc_reg = gen_compare_reg (code,
                                    sparc_compare_op0, sparc_compare_op1);
      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
    }
})

;; Conditional move define_insns.

(define_insn "*movqi_cc_sp64"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (if_then_else:QI (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:QI 3 "arith11_operand" "rL,0")
                         (match_operand:QI 4 "arith11_operand" "0,rL")))]
  "TARGET_V9"
  "@
   mov%C1\t%x2, %3, %0
   mov%c1\t%x2, %4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movhi_cc_sp64"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (if_then_else:HI (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:HI 3 "arith11_operand" "rL,0")
                         (match_operand:HI 4 "arith11_operand" "0,rL")))]
  "TARGET_V9"
  "@
   mov%C1\t%x2, %3, %0
   mov%c1\t%x2, %4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movsi_cc_sp64"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:SI 3 "arith11_operand" "rL,0")
                         (match_operand:SI 4 "arith11_operand" "0,rL")))]
  "TARGET_V9"
  "@
   mov%C1\t%x2, %3, %0
   mov%c1\t%x2, %4, %0"
  [(set_attr "type" "cmove")])

;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_sp64"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (if_then_else:DI (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:DI 3 "arith11_double_operand" "rLH,0")
                         (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
  "TARGET_ARCH64"
  "@
   mov%C1\t%x2, %3, %0
   mov%c1\t%x2, %4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movdi_cc_sp64_trunc"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:SI 3 "arith11_double_operand" "rLH,0")
                         (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
  "TARGET_ARCH64"
  "@
   mov%C1\t%x2, %3, %0
   mov%c1\t%x2, %4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movsf_cc_sp64"
  [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:SF 3 "register_operand" "f,0")
                         (match_operand:SF 4 "register_operand" "0,f")))]
  "TARGET_V9 && TARGET_FPU"
  "@
   fmovs%C1\t%x2, %3, %0
   fmovs%c1\t%x2, %4, %0"
  [(set_attr "type" "fpcmove")])

(define_insn "movdf_cc_sp64"
  [(set (match_operand:DF 0 "register_operand" "=e,e")
        (if_then_else:DF (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:DF 3 "register_operand" "e,0")
                         (match_operand:DF 4 "register_operand" "0,e")))]
  "TARGET_V9 && TARGET_FPU"
  "@
   fmovd%C1\t%x2, %3, %0
   fmovd%c1\t%x2, %4, %0"
  [(set_attr "type" "fpcmove")
   (set_attr "fptype" "double")])

(define_insn "*movtf_cc_hq_sp64"
  [(set (match_operand:TF 0 "register_operand" "=e,e")
        (if_then_else:TF (match_operator 1 "comparison_operator"
                                [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                                 (const_int 0)])
                         (match_operand:TF 3 "register_operand" "e,0")
                         (match_operand:TF 4 "register_operand" "0,e")))]
  "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
  "@
   fmovq%C1\t%x2, %3, %0
   fmovq%c1\t%x2, %4, %0"
  [(set_attr "type" "fpcmove")])

(define_insn_and_split "*movtf_cc_sp64"
  [(set (match_operand:TF 0 "register_operand" "=e,e")
        (if_then_else:TF (match_operator 1 "comparison_operator"
                            [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
                             (const_int 0)])
                         (match_operand:TF 3 "register_operand" "e,0")
                         (match_operand:TF 4 "register_operand" "0,e")))]
  "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
  "#"
  "&& reload_completed"
  [(clobber (const_int 0))]
{
  rtx set_dest = operands[0];
  rtx set_srca = operands[3];
  rtx set_srcb = operands[4];
  int third = rtx_equal_p (set_dest, set_srca);
  rtx dest1, dest2;
  rtx srca1, srca2, srcb1, srcb2;

  dest1 = gen_df_reg (set_dest, 0);
  dest2 = gen_df_reg (set_dest, 1);
  srca1 = gen_df_reg (set_srca, 0);
  srca2 = gen_df_reg (set_srca, 1);
  srcb1 = gen_df_reg (set_srcb, 0);
  srcb2 = gen_df_reg (set_srcb, 1);

  /* Now emit using the real source and destination we found, swapping
     the order if we detect overlap.  */
  if ((third && reg_overlap_mentioned_p (dest1, srcb2))
      || (!third && reg_overlap_mentioned_p (dest1, srca2)))
    {
      emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
      emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
    }
  else
    {
      emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
      emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
    }
  DONE;
}
  [(set_attr "length" "2")])

(define_insn "*movqi_cc_reg_sp64"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (if_then_else:QI (match_operator 1 "v9_regcmp_op"
                                [(match_operand:DI 2 "register_operand" "r,r")
                                 (const_int 0)])
                         (match_operand:QI 3 "arith10_operand" "rM,0")
                         (match_operand:QI 4 "arith10_operand" "0,rM")))]
  "TARGET_ARCH64"
  "@
   movr%D1\t%2, %r3, %0
   movr%d1\t%2, %r4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movhi_cc_reg_sp64"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (if_then_else:HI (match_operator 1 "v9_regcmp_op"
                                [(match_operand:DI 2 "register_operand" "r,r")
                                 (const_int 0)])
                         (match_operand:HI 3 "arith10_operand" "rM,0")
                         (match_operand:HI 4 "arith10_operand" "0,rM")))]
  "TARGET_ARCH64"
  "@
   movr%D1\t%2, %r3, %0
   movr%d1\t%2, %r4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movsi_cc_reg_sp64"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "v9_regcmp_op"
                                [(match_operand:DI 2 "register_operand" "r,r")
                                 (const_int 0)])
                         (match_operand:SI 3 "arith10_operand" "rM,0")
                         (match_operand:SI 4 "arith10_operand" "0,rM")))]
  "TARGET_ARCH64"
  "@
   movr%D1\t%2, %r3, %0
   movr%d1\t%2, %r4, %0"
  [(set_attr "type" "cmove")])

;; ??? The constraints of operands 3,4 need work.
(define_insn "*movdi_cc_reg_sp64"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (if_then_else:DI (match_operator 1 "v9_regcmp_op"
                                [(match_operand:DI 2 "register_operand" "r,r")
                                 (const_int 0)])
                         (match_operand:DI 3 "arith10_double_operand" "rMH,0")
                         (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
  "TARGET_ARCH64"
  "@
   movr%D1\t%2, %r3, %0
   movr%d1\t%2, %r4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movdi_cc_reg_sp64_trunc"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (if_then_else:SI (match_operator 1 "v9_regcmp_op"
                                [(match_operand:DI 2 "register_operand" "r,r")
                                 (const_int 0)])
                         (match_operand:SI 3 "arith10_double_operand" "rMH,0")
                         (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
  "TARGET_ARCH64"
  "@
   movr%D1\t%2, %r3, %0
   movr%d1\t%2, %r4, %0"
  [(set_attr "type" "cmove")])

(define_insn "*movsf_cc_reg_sp64"
  [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF (match_operator 1 "v9_regcmp_op"