1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
29 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
31 /* Special flags to the Sun-4 assembler when using pipe for input. */
33 #define ASM_SPEC " %| %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}}"
35 /* Define macros to distinguish architectures. */
36 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mf930:-D__sparclite__} \
37 %{mf934:-D__sparclite__} %{mv8:-D__sparc_v8__}"
39 /* Prevent error on `-sun4' and `-target sun4' options. */
40 /* This used to translate -dalign to -malign, but that is no good
41 because it can't turn off the usual meaning of making debugging dumps. */
43 #define CC1_SPEC "%{sun4:} %{target:}"
45 #define PTRDIFF_TYPE "int"
46 /* In 2.4 it should work to delete this.
47 #define SIZE_TYPE "int" */
48 #define WCHAR_TYPE "short unsigned int"
49 #define WCHAR_TYPE_SIZE 16
51 /* Show we can debug even without a frame pointer. */
52 #define CAN_DEBUG_WITHOUT_FP
54 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
55 code into the rtl. Also, if we are profiling, we cannot eliminate
56 the frame pointer (because the return address will get smashed). */
58 #define OVERRIDE_OPTIONS \
60 if (profile_flag || profile_block_flag) \
64 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
65 warning ("%s and profiling conflict: disabling %s", pic_string,\
69 flag_omit_frame_pointer = 0; \
71 SUBTARGET_OVERRIDE_OPTIONS \
74 /* This is meant to be redefined in the host dependent files */
75 #define SUBTARGET_OVERRIDE_OPTIONS
77 /* These compiler options take an argument. We ignore -target for now. */
79 #define WORD_SWITCH_TAKES_ARG(STR) \
80 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
81 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
83 /* Names to predefine in the preprocessor for this target machine. */
85 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
86 the right varags.h file when bootstrapping. */
88 #define CPP_PREDEFINES \
89 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
90 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
92 /* Print subsidiary information on the compiler version in use. */
94 #define TARGET_VERSION fprintf (stderr, " (sparc)");
96 /* Generate DBX debugging information. */
98 #define DBX_DEBUGGING_INFO
100 /* Run-time compilation parameters selecting different hardware subsets. */
102 extern int target_flags;
104 /* Nonzero if we should generate code to use the fpu. */
105 #define TARGET_FPU (target_flags & 1)
107 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
108 use fast return insns, but lose some generality. */
109 #define TARGET_EPILOGUE (target_flags & 2)
111 /* Nonzero if we should assume that double pointers might be unaligned.
112 This can happen when linking gcc compiled code with other compilers,
113 because the ABI only guarantees 4 byte alignment. */
114 #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
116 /* Nonzero means that we should generate code for a v8 sparc. */
117 #define TARGET_V8 (target_flags & 64)
119 /* Nonzero means that we should generate code for a sparclite.
120 This enables the sparclite specific instructions, but does not affect
121 whether FPU instructions are emitted. */
122 #define TARGET_SPARCLITE (target_flags & 128)
124 /* Nonzero means that we should generate code using a flat register window
125 model, i.e. no save/restore instructions are generated, in the most
126 efficient manner. This code is not compatible with normal sparc code. */
127 /* This is not a user selectable option yet, because it requires changes
128 that are not yet switchable via command line arguments. */
129 /* ??? This flag is deprecated and may disappear at some point. */
130 #define TARGET_FRW (target_flags & 256)
132 /* Nonzero means that we should generate code using a flat register window
133 model, i.e. no save/restore instructions are generated, but which is
134 compatible with normal sparc code. This is the same as above, except
135 that the frame pointer is %i7 instead of %fp. */
136 /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will
137 go away, but until that time only use this one when necessary.
139 #define TARGET_FLAT (target_flags & 512)
141 /* Nonzero means use the registers that the Sparc ABI reserves for
142 application software. This is the default. */
143 #define TARGET_APP_REGS (target_flags & 1024)
145 /* Option to select how quad word floating point is implemented.
146 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
147 Otherwise, we use the SPARC ABI quad library functions. */
148 #define TARGET_HARD_QUAD (target_flags & 2048)
150 /* Macro to define tables used to set the flags.
151 This is a list in braces of pairs in braces,
152 each pair being { "NAME", VALUE }
153 where VALUE is the bits to set or minus the bits to clear.
154 An empty string NAME is used to identify the default VALUE. */
156 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
157 The Fujitsu MB86934 is the recent sparclite chip, with an fup.
158 We use -mf930 and -mf934 options to choose which.
159 ??? These should perhaps be -mcpu= options. */
161 #define TARGET_SWITCHES \
165 {"soft-float", -1}, \
167 {"no-epilogue", -2}, \
168 {"unaligned-doubles", 4}, \
169 {"no-unaligned-doubles", -4},\
172 {"sparclite", 128}, \
173 {"no-sparclite", -128}, \
178 {"no-flat", -(256+512)}, \
179 {"app-regs", 1024}, \
180 {"no-app-regs", -1024}, \
181 {"hard-quad-float", 2048}, \
182 {"soft-quad-float", -2048}, \
184 { "", TARGET_DEFAULT}}
186 #define TARGET_DEFAULT (1024+3)
188 /* This is meant to be redefined in the host dependent files */
189 #define SUBTARGET_SWITCHES
191 /* target machine storage layout */
194 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
195 Instead, it is enabled in sol2.h, because it does work under Solaris. */
196 /* Define for support of TFmode long double and REAL_ARITHMETIC.
197 Sparc ABI says that long double is 4 words. */
198 #define LONG_DOUBLE_TYPE_SIZE 128
201 /* Define for cross-compilation to a sparc target with no TFmode from a host
202 with a different float format (e.g. VAX). */
203 #define REAL_ARITHMETIC
205 /* Define this if most significant bit is lowest numbered
206 in instructions that operate on numbered bit-fields. */
207 #define BITS_BIG_ENDIAN 1
209 /* Define this if most significant byte of a word is the lowest numbered. */
210 /* This is true on the SPARC. */
211 #define BYTES_BIG_ENDIAN 1
213 /* Define this if most significant word of a multiword number is the lowest
215 /* Doubles are stored in memory with the high order word first. This
216 matters when cross-compiling. */
217 #define WORDS_BIG_ENDIAN 1
219 /* number of bits in an addressable storage unit */
220 #define BITS_PER_UNIT 8
222 /* Width in bits of a "word", which is the contents of a machine register.
223 Note that this is not necessarily the width of data type `int';
224 if using 16-bit ints on a 68000, this would still be 32.
225 But on a machine with 16-bit registers, this would be 16. */
226 #define BITS_PER_WORD 32
227 #define MAX_BITS_PER_WORD 32
229 /* Width of a word, in units (bytes). */
230 #define UNITS_PER_WORD 4
232 /* Width in bits of a pointer.
233 See also the macro `Pmode' defined below. */
234 #define POINTER_SIZE 32
236 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
237 #define PARM_BOUNDARY 32
239 /* Boundary (in *bits*) on which stack pointer should be aligned. */
240 #define STACK_BOUNDARY 64
242 /* ALIGN FRAMES on double word boundaries */
244 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & (~7))
246 /* Allocation boundary (in *bits*) for the code of a function. */
247 #define FUNCTION_BOUNDARY 32
249 /* Alignment of field after `int : 0' in a structure. */
250 #define EMPTY_FIELD_BOUNDARY 32
252 /* Every structure's size must be a multiple of this. */
253 #define STRUCTURE_SIZE_BOUNDARY 8
255 /* A bitfield declared as `int' forces `int' alignment for the struct. */
256 #define PCC_BITFIELD_TYPE_MATTERS 1
258 /* No data type wants to be aligned rounder than this. */
259 #define BIGGEST_ALIGNMENT 64
261 /* The best alignment to use in cases where we have a choice. */
262 #define FASTEST_ALIGNMENT 64
264 /* Make strings word-aligned so strcpy from constants will be faster. */
265 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
266 ((TREE_CODE (EXP) == STRING_CST \
267 && (ALIGN) < FASTEST_ALIGNMENT) \
268 ? FASTEST_ALIGNMENT : (ALIGN))
270 /* Make arrays of chars word-aligned for the same reasons. */
271 #define DATA_ALIGNMENT(TYPE, ALIGN) \
272 (TREE_CODE (TYPE) == ARRAY_TYPE \
273 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
274 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
276 /* Set this nonzero if move instructions will actually fail to work
277 when given unaligned data. */
278 #define STRICT_ALIGNMENT 1
280 /* Things that must be doubleword aligned cannot go in the text section,
281 because the linker fails to align the text section enough!
282 Put them in the data section. */
283 #define MAX_TEXT_ALIGN 32
285 #define SELECT_SECTION(T,RELOC) \
287 if (TREE_CODE (T) == VAR_DECL) \
289 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
290 && DECL_INITIAL (T) \
291 && (DECL_INITIAL (T) == error_mark_node \
292 || TREE_CONSTANT (DECL_INITIAL (T))) \
293 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
294 && ! (flag_pic && (RELOC))) \
299 else if (TREE_CODE (T) == CONSTRUCTOR) \
301 if (flag_pic != 0 && (RELOC) != 0) \
304 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
306 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
307 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
314 /* Use text section for a constant
315 unless we need more alignment than that offers. */
316 #define SELECT_RTX_SECTION(MODE, X) \
318 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
319 && ! (flag_pic && symbolic_operand (X))) \
325 /* Standard register usage. */
327 /* Number of actual hardware registers.
328 The hardware registers are assigned numbers for the compiler
329 from 0 to just below FIRST_PSEUDO_REGISTER.
330 All registers that the compiler knows about must be given numbers,
331 even those that are not normally considered general registers.
333 SPARC has 32 integer registers and 32 floating point registers. */
335 #define FIRST_PSEUDO_REGISTER 64
337 /* 1 for registers that have pervasive standard uses
338 and are not available for the register allocator.
339 g0 is used for the condition code and not to represent %g0, which is
340 hardwired to 0, so reg 0 is *not* fixed.
341 g1 is free to use as temporary.
342 g2-g4 are reserved for applications. Gcc normally uses them as
343 temporaries, but this can be disabled via the -mno-app-regs option.
344 g5 through g7 are reserved for the operating system. */
345 #define FIXED_REGISTERS \
346 {0, 0, 0, 0, 0, 1, 1, 1, \
347 0, 0, 0, 0, 0, 0, 1, 0, \
348 0, 0, 0, 0, 0, 0, 0, 0, \
349 0, 0, 0, 0, 0, 0, 1, 1, \
351 0, 0, 0, 0, 0, 0, 0, 0, \
352 0, 0, 0, 0, 0, 0, 0, 0, \
353 0, 0, 0, 0, 0, 0, 0, 0, \
354 0, 0, 0, 0, 0, 0, 0, 0}
356 /* 1 for registers not available across function calls.
357 These must include the FIXED_REGISTERS and also any
358 registers that can be used without being saved.
359 The latter must include the registers where values are returned
360 and the register where structure-value addresses are passed.
361 Aside from that, you can include as many other registers as you like. */
362 #define CALL_USED_REGISTERS \
363 {1, 1, 1, 1, 1, 1, 1, 1, \
364 1, 1, 1, 1, 1, 1, 1, 1, \
365 0, 0, 0, 0, 0, 0, 0, 0, \
366 0, 0, 0, 0, 0, 0, 1, 1, \
368 1, 1, 1, 1, 1, 1, 1, 1, \
369 1, 1, 1, 1, 1, 1, 1, 1, \
370 1, 1, 1, 1, 1, 1, 1, 1, \
371 1, 1, 1, 1, 1, 1, 1, 1}
373 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
376 #define CONDITIONAL_REGISTER_USAGE \
382 for (regno = 32; regno < 64; regno++) \
383 fixed_regs[regno] = 1; \
385 if (! TARGET_APP_REGS) \
393 /* Let the compiler believe the frame pointer is still \
394 %fp, but output it as %i7. */ \
395 fixed_regs[31] = 1; \
396 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
397 /* ??? This is a hack to disable leaf functions. */ \
398 global_regs[7] = 1; \
400 if (profile_block_flag) \
402 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
410 /* Return number of consecutive hard regs needed starting at reg REGNO
411 to hold something of mode MODE.
412 This is ordinarily the length in words of a value of mode MODE
413 but can be less for certain modes in special long registers.
415 On SPARC, ordinary registers hold 32 bits worth;
416 this means both integer and floating point registers.
418 We use vectors to keep this information about registers. */
420 /* How many hard registers it takes to make a register of this mode. */
421 extern int hard_regno_nregs[];
423 #define HARD_REGNO_NREGS(REGNO, MODE) \
424 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
426 /* Value is 1 if register/mode pair is acceptable on sparc. */
427 extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
429 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
430 See sparc.c for how we initialize this. */
431 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
432 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
434 /* Value is 1 if it is a good idea to tie two pseudo registers
435 when one has mode MODE1 and one has mode MODE2.
436 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
437 for any hard reg, then this must be 0 for correct output. */
438 #define MODES_TIEABLE_P(MODE1, MODE2) \
439 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
441 /* Specify the registers used for certain standard purposes.
442 The values of these macros are register numbers. */
444 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
445 /* #define PC_REGNUM */
447 /* Register to use for pushing function arguments. */
448 #define STACK_POINTER_REGNUM 14
450 /* Actual top-of-stack address is 92 greater than the contents
451 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
452 for the ins and local registers, 4 byte for structure return address, and
453 24 bytes for the 6 register parameters. */
454 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
456 /* Base register for access to local variables of the function. */
457 #define FRAME_POINTER_REGNUM 30
460 /* Register that is used for the return address. */
461 #define RETURN_ADDR_REGNUM 15
464 /* Value should be nonzero if functions must have frame pointers.
465 Zero means the frame pointer need not be set up (and parms
466 may be accessed via the stack pointer) in functions that seem suitable.
467 This is computed in `reload', in reload1.c.
469 Used in flow.c, global.c, and reload1.c. */
470 extern int leaf_function;
472 #define FRAME_POINTER_REQUIRED \
473 (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs) \
474 : ! (leaf_function_p () && only_leaf_regs_used ()))
476 /* C statement to store the difference between the frame pointer
477 and the stack pointer values immediately after the function prologue.
479 Note, we always pretend that this is a leaf function because if
480 it's not, there's no point in trying to eliminate the
481 frame pointer. If it is a leaf function, we guessed right! */
482 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
483 ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \
484 : compute_frame_size (get_frame_size (), 1)))
486 /* Base register for access to arguments of the function. */
487 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
489 /* Register in which static-chain is passed to a function. This must
490 not be a register used by the prologue. */
491 #define STATIC_CHAIN_REGNUM 2
493 /* Register which holds offset table for position-independent
496 #define PIC_OFFSET_TABLE_REGNUM 23
498 #define INITIALIZE_PIC initialize_pic ()
499 #define FINALIZE_PIC finalize_pic ()
501 /* Sparc ABI says that quad-precision floats and all structures are returned
503 #define RETURN_IN_MEMORY(TYPE) \
504 (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
506 /* Functions which return large structures get the address
507 to place the wanted value at offset 64 from the frame.
508 Must reserve 64 bytes for the in and local registers. */
509 /* Used only in other #defines in this file. */
510 #define STRUCT_VALUE_OFFSET 64
512 #define STRUCT_VALUE \
513 gen_rtx (MEM, Pmode, \
514 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
515 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
516 #define STRUCT_VALUE_INCOMING \
517 gen_rtx (MEM, Pmode, \
518 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
519 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
521 /* Define the classes of registers for register constraints in the
522 machine description. Also define ranges of constants.
524 One of the classes must always be named ALL_REGS and include all hard regs.
525 If there is more than one class, another class must be named NO_REGS
526 and contain no registers.
528 The name GENERAL_REGS must be the name of a class (or an alias for
529 another name such as ALL_REGS). This is the class of registers
530 that is allowed by "g" or "r" in a register constraint.
531 Also, registers outside this class are allocated only when
532 instructions express preferences for them.
534 The classes must be numbered in nondecreasing order; that is,
535 a larger-numbered class must never be contained completely
536 in a smaller-numbered class.
538 For any two classes, it is very desirable that there be another
539 class that represents their union. */
541 /* The SPARC has two kinds of registers, general and floating point. */
543 enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
545 #define N_REG_CLASSES (int) LIM_REG_CLASSES
547 /* Give names of register classes as strings for dump file. */
549 #define REG_CLASS_NAMES \
550 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
552 /* Define which registers fit in which classes.
553 This is an initializer for a vector of HARD_REG_SET
554 of length N_REG_CLASSES. */
556 #if 0 && defined (__GNUC__)
557 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
559 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
562 /* The same information, inverted:
563 Return the class number of the smallest class containing
564 reg number REGNO. This could be a conditional expression
565 or could index an array. */
567 #define REGNO_REG_CLASS(REGNO) \
568 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
570 /* This is the order in which to allocate registers
573 We put %f0/%f1 last among the float registers, so as to make it more
574 likely that a pseudo-register which dies in the float return register
575 will get allocated to the float return register, thus saving a move
576 instruction at the end of the function. */
577 #define REG_ALLOC_ORDER \
578 { 8, 9, 10, 11, 12, 13, 2, 3, \
579 15, 16, 17, 18, 19, 20, 21, 22, \
580 23, 24, 25, 26, 27, 28, 29, 31, \
581 34, 35, 36, 37, 38, 39, \
582 40, 41, 42, 43, 44, 45, 46, 47, \
583 48, 49, 50, 51, 52, 53, 54, 55, \
584 56, 57, 58, 59, 60, 61, 62, 63, \
586 1, 4, 5, 6, 7, 0, 14, 30}
588 /* This is the order in which to allocate registers for
589 leaf functions. If all registers can fit in the "i" registers,
590 then we have the possibility of having a leaf function. */
591 #define REG_LEAF_ALLOC_ORDER \
592 { 2, 3, 24, 25, 26, 27, 28, 29, \
593 15, 8, 9, 10, 11, 12, 13, \
594 16, 17, 18, 19, 20, 21, 22, 23, \
595 34, 35, 36, 37, 38, 39, \
596 40, 41, 42, 43, 44, 45, 46, 47, \
597 48, 49, 50, 51, 52, 53, 54, 55, \
598 56, 57, 58, 59, 60, 61, 62, 63, \
600 1, 4, 5, 6, 7, 0, 14, 30, 31}
602 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
604 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
605 -mflat is used. Function only_leaf_regs_used will return 0 if a global
606 register is used and is not permitted in a leaf function. We make %g7
607 a global reg if -mflat and voila. Since %g7 is a system register and is
608 fixed it won't be used by gcc anyway. */
609 #define LEAF_REGISTERS \
610 { 1, 1, 1, 1, 1, 1, 1, 0, \
611 0, 0, 0, 0, 0, 0, 1, 0, \
612 0, 0, 0, 0, 0, 0, 0, 0, \
613 1, 1, 1, 1, 1, 1, 0, 1, \
614 1, 1, 1, 1, 1, 1, 1, 1, \
615 1, 1, 1, 1, 1, 1, 1, 1, \
616 1, 1, 1, 1, 1, 1, 1, 1, \
617 1, 1, 1, 1, 1, 1, 1, 1}
619 extern char leaf_reg_remap[];
620 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
622 /* The class value for index registers, and the one for base regs. */
623 #define INDEX_REG_CLASS GENERAL_REGS
624 #define BASE_REG_CLASS GENERAL_REGS
626 /* Get reg_class from a letter such as appears in the machine description. */
628 #define REG_CLASS_FROM_LETTER(C) \
629 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
631 /* The letters I, J, K, L and M in a register constraint string
632 can be used to stand for particular ranges of immediate operands.
633 This macro defines what the ranges are.
634 C is the letter, and VALUE is a constant value.
635 Return 1 if VALUE is in the range specified by C.
637 For SPARC, `I' is used for the range of constants an insn
638 can actually contain.
639 `J' is used for the range which is just zero (since that is R0).
640 `K' is used for constants which can be loaded with a single sethi insn. */
642 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
644 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
645 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
646 : (C) == 'J' ? (VALUE) == 0 \
647 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
650 /* Similar, but for floating constants, and defining letters G and H.
651 Here VALUE is the CONST_DOUBLE rtx itself. */
653 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
654 ((C) == 'G' ? fp_zero_operand (VALUE) \
655 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
658 /* Given an rtx X being reloaded into a reg required to be
659 in class CLASS, return the class of reg to actually use.
660 In general this is just CLASS; but on some machines
661 in some cases it is preferable to use a more restrictive class. */
662 /* We can't load constants into FP registers. We can't load any FP constant
663 if an 'E' constraint fails to match it. */
664 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
666 && ((CLASS) == FP_REGS \
667 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
668 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
669 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
672 /* Return the register class of a scratch register needed to load IN into
673 a register of class CLASS in MODE.
675 On the SPARC, when PIC, we need a temporary when loading some addresses
678 Also, we need a temporary when loading/storing a HImode/QImode value
679 between memory and the FPU registers. This can happen when combine puts
680 a paradoxical subreg in a float/fix conversion insn. */
682 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
683 (((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
684 && (GET_CODE (IN) == MEM \
685 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
686 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
688 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
689 ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
690 && (GET_CODE (IN) == MEM \
691 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
692 && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
694 /* On SPARC it is not possible to directly move data between
695 GENERAL_REGS and FP_REGS. */
696 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
697 (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
698 || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
700 /* Return the stack location to use for secondary memory needed reloads. */
701 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
702 gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
703 GEN_INT (STARTING_FRAME_OFFSET)))
705 /* Return the maximum number of consecutive registers
706 needed to represent mode MODE in a register of class CLASS. */
707 /* On SPARC, this is the size of MODE in words. */
708 #define CLASS_MAX_NREGS(CLASS, MODE) \
709 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
711 /* Stack layout; function entry, exit and calling. */
713 /* Define the number of register that can hold parameters.
714 These two macros are used only in other macro definitions below. */
717 /* Define this if pushing a word on the stack
718 makes the stack pointer a smaller address. */
719 #define STACK_GROWS_DOWNWARD
721 /* Define this if the nominal address of the stack frame
722 is at the high-address end of the local variables;
723 that is, each additional local variable allocated
724 goes at a more negative offset in the frame. */
725 #define FRAME_GROWS_DOWNWARD
727 /* Offset within stack frame to start allocating local variables at.
728 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
729 first local allocated. Otherwise, it is the offset to the BEGINNING
730 of the first local allocated. */
731 /* This allows space for one TFmode floating point value. */
732 #define STARTING_FRAME_OFFSET \
733 (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
735 /* If we generate an insn to push BYTES bytes,
736 this says how many the stack pointer really advances by.
737 On SPARC, don't define this because there are no push insns. */
738 /* #define PUSH_ROUNDING(BYTES) */
740 /* Offset of first parameter from the argument pointer register value.
741 This is 64 for the ins and locals, plus 4 for the struct-return reg
742 even if this function isn't going to use it. */
743 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
745 /* When a parameter is passed in a register, stack space is still
747 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
749 /* Keep the stack pointer constant throughout the function.
750 This is both an optimization and a necessity: longjmp
751 doesn't behave itself when the stack pointer moves within
753 #define ACCUMULATE_OUTGOING_ARGS
755 /* Value is the number of bytes of arguments automatically
756 popped when returning from a subroutine call.
757 FUNTYPE is the data type of the function (as a tree),
758 or for a library call it is an identifier node for the subroutine name.
759 SIZE is the number of bytes of arguments passed on the stack. */
761 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
763 /* Some subroutine macros specific to this machine.
764 When !TARGET_FPU, put float return values in the general registers,
765 since we don't have any fp registers. */
766 #define BASE_RETURN_VALUE_REG(MODE) \
767 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
768 #define BASE_OUTGOING_VALUE_REG(MODE) \
769 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
770 : (TARGET_FRW ? 8 : 24))
771 #define BASE_PASSING_ARG_REG(MODE) (8)
772 #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
774 /* Define this macro if the target machine has "register windows". This
775 C expression returns the register number as seen by the called function
776 corresponding to register number OUT as seen by the calling function.
777 Return OUT if register number OUT is not an outbound register. */
779 #define INCOMING_REGNO(OUT) \
780 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
782 /* Define this macro if the target machine has "register windows". This
783 C expression returns the register number as seen by the calling function
784 corresponding to register number IN as seen by the called function.
785 Return IN if register number IN is not an inbound register. */
787 #define OUTGOING_REGNO(IN) \
788 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
790 /* Define how to find the value returned by a function.
791 VALTYPE is the data type of the value (as a tree).
792 If the precise function being called is known, FUNC is its FUNCTION_DECL;
793 otherwise, FUNC is 0. */
795 /* On SPARC the value is found in the first "output" register. */
797 #define FUNCTION_VALUE(VALTYPE, FUNC) \
798 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
800 /* But the called function leaves it in the first "input" register. */
802 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
803 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
805 /* Define how to find the value returned by a library function
806 assuming the value has mode MODE. */
808 #define LIBCALL_VALUE(MODE) \
809 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
811 /* 1 if N is a possible register number for a function value
812 as seen by the caller.
813 On SPARC, the first "output" reg is used for integer values,
814 and the first floating point register is used for floating point values. */
816 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
818 /* Define the size of space to allocate for the return value of an
821 #define APPLY_RESULT_SIZE 16
823 /* 1 if N is a possible register number for function argument passing.
824 On SPARC, these are the "output" registers. */
826 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
828 /* Define a data type for recording info about an argument list
829 during the scan of that argument list. This data type should
830 hold all necessary information about the function itself
831 and about the args processed so far, enough to enable macros
832 such as FUNCTION_ARG to determine where the next arg should go.
834 On SPARC, this is a single integer, which is a number of words
835 of arguments scanned so far (including the invisible argument,
836 if any, which holds the structure-value-address).
837 Thus 7 or more means all following args should go on the stack. */
839 #define CUMULATIVE_ARGS int
841 #define ROUND_ADVANCE(SIZE) \
842 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
844 /* Initialize a variable CUM of type CUMULATIVE_ARGS
845 for a call to a function whose data type is FNTYPE.
846 For a library call, FNTYPE is 0.
848 On SPARC, the offset always starts at 0: the first parm reg is always
851 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
853 /* Update the data in CUM to advance over an argument
854 of mode MODE and data type TYPE.
855 (TYPE is null for libcalls where that information may not be available.) */
857 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
858 ((CUM) += ((MODE) != BLKmode \
859 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
860 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
862 /* Determine where to put an argument to a function.
863 Value is zero to push the argument on the stack,
864 or a hard register in which to store the argument.
866 MODE is the argument's machine mode.
867 TYPE is the data type of the argument (as a tree).
868 This is null for libcalls where that information may
870 CUM is a variable of type CUMULATIVE_ARGS which gives info about
871 the preceding args and about the function being called.
872 NAMED is nonzero if this argument is a named parameter
873 (otherwise it is an extra parameter matching an ellipsis). */
875 /* On SPARC the first six args are normally in registers
876 and the rest are pushed. Any arg that starts within the first 6 words
877 is at least partially passed in a register unless its data type forbids. */
879 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
880 ((CUM) < NPARM_REGS \
881 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
882 && ((TYPE)==0 || (MODE) != BLKmode \
883 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
884 ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
887 /* Define where a function finds its arguments.
888 This is different from FUNCTION_ARG because of register windows. */
890 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
891 ((CUM) < NPARM_REGS \
892 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
893 && ((TYPE)==0 || (MODE) != BLKmode \
894 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
895 ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
898 /* For an arg passed partly in registers and partly in memory,
899 this is the number of registers used.
900 For args passed entirely in registers or entirely in memory, zero.
901 Any arg that starts in the first 6 regs but won't entirely fit in them
902 needs partial registers on the Sparc. */
904 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
905 ((CUM) < NPARM_REGS \
906 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
907 && ((TYPE)==0 || (MODE) != BLKmode \
908 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
909 && ((CUM) + ((MODE) == BLKmode \
910 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
911 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
912 ? (NPARM_REGS - (CUM)) \
915 /* The SPARC ABI stipulates passing struct arguments (of any size) and
916 quad-precision floats by invisible reference.
917 For Pascal, also pass arrays by reference. */
918 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
919 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
920 || TREE_CODE (TYPE) == UNION_TYPE \
921 || TREE_CODE (TYPE) == ARRAY_TYPE)) \
924 /* Define the information needed to generate branch and scc insns. This is
925 stored from the compare operation. Note that we can't use "rtx" here
926 since it hasn't been defined! */
928 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
930 /* Define the function that build the compare insn for scc and bcc. */
932 extern struct rtx_def *gen_compare_reg ();
934 /* Generate the special assembly code needed to tell the assembler whatever
935 it might need to know about the return value of a function.
937 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
938 information to the assembler relating to peephole optimization (done in
941 #define ASM_DECLARE_RESULT(FILE, RESULT) \
942 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
944 /* Output the label for a function definition. */
946 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
948 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
949 ASM_OUTPUT_LABEL (FILE, NAME); \
952 /* This macro generates the assembly code for function entry.
953 FILE is a stdio stream to output the code to.
954 SIZE is an int: how many units of temporary storage to allocate.
955 Refer to the array `regs_ever_live' to determine which registers
956 to save; `regs_ever_live[I]' is nonzero if register number I
957 is ever used in the function. This macro is responsible for
958 knowing which registers should not be saved even if used. */
960 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
961 of memory. If any fpu reg is used in the function, we allocate
962 such a block here, at the bottom of the frame, just in case it's needed.
964 If this function is a leaf procedure, then we may choose not
965 to do a "save" insn. The decision about whether or not
966 to do this is made in regclass.c. */
968 #define FUNCTION_PROLOGUE(FILE, SIZE) \
969 (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \
970 : output_function_prologue (FILE, SIZE, leaf_function))
972 /* Output assembler code to FILE to increment profiler label # LABELNO
973 for profiling a function entry. */
975 #define FUNCTION_PROFILER(FILE, LABELNO) \
977 fputs ("\tsethi %hi(", (FILE)); \
978 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
979 fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
980 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
981 fputs ("),%o0,%o0\n", (FILE)); \
984 /* Output assembler code to FILE to initialize this source file's
985 basic block profiling info, if that has not already been done. */
986 /* FIXME -- this does not parameterize how it generates labels (like the
987 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
989 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
990 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
991 (LABELNO), (LABELNO))
993 /* Output assembler code to FILE to increment the entry-count for
994 the BLOCKNO'th basic block in this source file. */
996 #define BLOCK_PROFILER(FILE, BLOCKNO) \
998 int blockn = (BLOCKNO); \
999 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1000 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1001 4 * blockn, 4 * blockn, 4 * blockn); \
1004 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1005 the stack pointer does not matter. The value is tested only in
1006 functions that have frame pointers.
1007 No definition is equivalent to always zero. */
1009 extern int current_function_calls_alloca;
1010 extern int current_function_outgoing_args_size;
1012 #define EXIT_IGNORE_STACK \
1013 (get_frame_size () != 0 \
1014 || current_function_calls_alloca || current_function_outgoing_args_size)
1016 /* This macro generates the assembly code for function exit,
1017 on machines that need it. If FUNCTION_EPILOGUE is not defined
1018 then individual return instructions are generated for each
1019 return statement. Args are same as for FUNCTION_PROLOGUE.
1021 The function epilogue should not depend on the current stack pointer!
1022 It should use the frame pointer only. This is mandatory because
1023 of alloca; we also take advantage of it to omit stack adjustments
1024 before returning. */
1026 /* This declaration is needed due to traditional/ANSI
1027 incompatibilities which cannot be #ifdefed away
1028 because they occur inside of macros. Sigh. */
1029 extern union tree_node *current_function_decl;
1031 #define FUNCTION_EPILOGUE(FILE, SIZE) \
1032 (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \
1033 : output_function_epilogue (FILE, SIZE, leaf_function))
1035 #define DELAY_SLOTS_FOR_EPILOGUE \
1036 (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1)
1037 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1038 (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1039 : eligible_for_epilogue_delay (trial, slots_filled))
1041 /* Output assembler code for a block containing the constant parts
1042 of a trampoline, leaving space for the variable parts. */
1044 /* On the sparc, the trampoline contains five instructions:
1045 sethi #TOP_OF_FUNCTION,%g1
1046 or #BOTTOM_OF_FUNCTION,%g1,%g1
1047 sethi #TOP_OF_STATIC,%g2
1049 or #BOTTOM_OF_STATIC,%g2,%g2 */
1050 #define TRAMPOLINE_TEMPLATE(FILE) \
1052 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1053 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1054 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1055 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
1056 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1059 /* Length in units of the trampoline for entering a nested function. */
1061 #define TRAMPOLINE_SIZE 20
1063 /* Emit RTL insns to initialize the variable parts of a trampoline.
1064 FNADDR is an RTX for the address of the function's pure code.
1065 CXT is an RTX for the static chain value for the function.
1067 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
1068 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
1069 (to store insns). This is a bit excessive. Perhaps a different
1070 mechanism would be better here.
1072 Emit 3 FLUSH instructions (UNSPEC_VOLATILE 2) to synchonize the data
1073 and instruction caches. */
1075 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1077 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1078 size_int (10), 0, 1); \
1079 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1080 size_int (10), 0, 1); \
1081 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1082 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1083 rtx g1_sethi = gen_rtx (HIGH, SImode, \
1084 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1085 rtx g2_sethi = gen_rtx (HIGH, SImode, \
1086 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1087 rtx g1_ori = gen_rtx (HIGH, SImode, \
1088 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1089 rtx g2_ori = gen_rtx (HIGH, SImode, \
1090 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1091 rtx tem = gen_reg_rtx (SImode); \
1092 emit_move_insn (tem, g1_sethi); \
1093 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1094 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1095 emit_move_insn (tem, g1_ori); \
1096 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1097 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1098 emit_move_insn (tem, g2_sethi); \
1099 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1100 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1101 emit_move_insn (tem, g2_ori); \
1102 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1103 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1104 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1105 gen_rtvec (1, plus_constant (TRAMP, 0)), \
1107 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1108 gen_rtvec (1, plus_constant (TRAMP, 8)), \
1110 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1111 gen_rtvec (1, plus_constant (TRAMP, 16)), \
1115 /* Generate necessary RTL for __builtin_saveregs().
1116 ARGLIST is the argument list; see expr.c. */
1117 extern struct rtx_def *sparc_builtin_saveregs ();
1118 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1120 /* Generate RTL to flush the register windows so as to make arbitrary frames
1122 #define SETUP_FRAME_ADDRESSES() \
1123 emit_insn (gen_flush_register_windows ())
1125 /* Given an rtx for the address of a frame,
1126 return an rtx for the address of the word in the frame
1127 that holds the dynamic chain--the previous frame's address. */
1128 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1129 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1131 /* The return address isn't on the stack, it is in a register, so we can't
1132 access it from the current frame pointer. We can access it from the
1133 previous frame pointer though by reading a value from the register window
1135 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1137 /* The current return address is in %i7. The return address of anything
1138 farther back is in the register window save area at [%fp+60]. */
1139 /* ??? This ignores the fact that the actual return address is +8 for normal
1140 returns, and +12 for structure returns. */
1141 #define RETURN_ADDR_RTX(count, frame) \
1143 ? gen_rtx (REG, Pmode, 31) \
1144 : copy_to_reg (gen_rtx (MEM, Pmode, \
1145 memory_address (Pmode, plus_constant (frame, 60)))))
1147 /* Addressing modes, and classification of registers for them. */
1149 /* #define HAVE_POST_INCREMENT */
1150 /* #define HAVE_POST_DECREMENT */
1152 /* #define HAVE_PRE_DECREMENT */
1153 /* #define HAVE_PRE_INCREMENT */
1155 /* Macros to check register numbers against specific register classes. */
1157 /* These assume that REGNO is a hard or pseudo reg number.
1158 They give nonzero only if REGNO is a hard reg of the suitable class
1159 or a pseudo reg currently allocated to a suitable hard reg.
1160 Since they use reg_renumber, they are safe only once reg_renumber
1161 has been allocated, which happens in local-alloc.c. */
1163 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1164 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1165 #define REGNO_OK_FOR_BASE_P(REGNO) \
1166 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1167 #define REGNO_OK_FOR_FP_P(REGNO) \
1168 (((REGNO) ^ 0x20) < 32 \
1169 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1171 /* Now macros that check whether X is a register and also,
1172 strictly, whether it is in a specified class.
1174 These macros are specific to the SPARC, and may be used only
1175 in code for printing assembler insns and in conditions for
1176 define_optimization. */
1178 /* 1 if X is an fp register. */
1180 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1182 /* Maximum number of registers that can appear in a valid memory address. */
1184 #define MAX_REGS_PER_ADDRESS 2
1186 /* Recognize any constant value that is a valid address.
1187 When PIC, we do not accept an address that would require a scratch reg
1188 to load into a register. */
1190 #define CONSTANT_ADDRESS_P(X) \
1191 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1192 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1193 || (GET_CODE (X) == CONST \
1194 && ! (flag_pic && pic_address_needs_scratch (X))))
1196 /* Define this, so that when PIC, reload won't try to reload invalid
1197 addresses which require two reload registers. */
1199 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
1201 /* Nonzero if the constant value X is a legitimate general operand.
1202 Anything can be made to work except floating point constants. */
1204 #define LEGITIMATE_CONSTANT_P(X) \
1205 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1207 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1208 and check its validity for a certain class.
1209 We have two alternate definitions for each of them.
1210 The usual definition accepts all pseudo regs; the other rejects
1211 them unless they have been allocated suitable hard regs.
1212 The symbol REG_OK_STRICT causes the latter definition to be used.
1214 Most source files want to accept pseudo regs in the hope that
1215 they will get allocated to the class that the insn wants them to be in.
1216 Source files for reload pass need to be strict.
1217 After reload, it makes no difference, since pseudo regs have
1218 been eliminated by then. */
1220 /* Optional extra constraints for this machine. Borrowed from romp.h.
1222 For the SPARC, `Q' means that this is a memory operand but not a
1223 symbolic memory operand. Note that an unassigned pseudo register
1224 is such a memory operand. Needed because reload will generate
1225 these things in insns and then not re-recognize the insns, causing
1226 constrain_operands to fail.
1228 `S' handles constraints for calls. */
1230 #ifndef REG_OK_STRICT
1232 /* Nonzero if X is a hard reg that can be used as an index
1233 or if it is a pseudo reg. */
1234 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1235 /* Nonzero if X is a hard reg that can be used as a base reg
1236 or if it is a pseudo reg. */
1237 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1239 #define EXTRA_CONSTRAINT(OP, C) \
1241 ? ((GET_CODE (OP) == MEM \
1242 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1243 && ! symbolic_memory_operand (OP, VOIDmode)) \
1244 || (reload_in_progress && GET_CODE (OP) == REG \
1245 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1247 ? (mem_aligned_8 (OP)) \
1249 ? (register_ok_for_ldd (OP)) \
1254 /* Nonzero if X is a hard reg that can be used as an index. */
1255 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1256 /* Nonzero if X is a hard reg that can be used as a base reg. */
1257 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1259 #define EXTRA_CONSTRAINT(OP, C) \
1261 ? (GET_CODE (OP) == REG \
1262 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1263 && reg_renumber[REGNO (OP)] < 0) \
1264 : GET_CODE (OP) == MEM) \
1266 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
1268 ? (GET_CODE (OP) == REG \
1269 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
1270 || reg_renumber[REGNO (OP)] > 0) \
1271 && register_ok_for_ldd (OP)) : 0)
1274 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1275 that is a valid memory address for an instruction.
1276 The MODE argument is the machine mode for the MEM expression
1277 that wants to use this address.
1279 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1280 ordinarily. This changes a bit when generating PIC.
1282 If you change this, execute "rm explow.o recog.o reload.o". */
1284 #define RTX_OK_FOR_BASE_P(X) \
1285 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1286 || (GET_CODE (X) == SUBREG \
1287 && GET_CODE (SUBREG_REG (X)) == REG \
1288 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1290 #define RTX_OK_FOR_INDEX_P(X) \
1291 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1292 || (GET_CODE (X) == SUBREG \
1293 && GET_CODE (SUBREG_REG (X)) == REG \
1294 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1296 #define RTX_OK_FOR_OFFSET_P(X) \
1297 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1299 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1300 { if (RTX_OK_FOR_BASE_P (X)) \
1302 else if (GET_CODE (X) == PLUS) \
1304 register rtx op0 = XEXP (X, 0); \
1305 register rtx op1 = XEXP (X, 1); \
1306 if (flag_pic && op0 == pic_offset_table_rtx) \
1308 if (RTX_OK_FOR_BASE_P (op1)) \
1310 else if (flag_pic == 1 \
1311 && GET_CODE (op1) != REG \
1312 && GET_CODE (op1) != LO_SUM \
1313 && GET_CODE (op1) != MEM \
1314 && (GET_CODE (op1) != CONST_INT \
1315 || SMALL_INT (op1))) \
1318 else if (RTX_OK_FOR_BASE_P (op0)) \
1320 if (RTX_OK_FOR_INDEX_P (op1) \
1321 || RTX_OK_FOR_OFFSET_P (op1)) \
1324 else if (RTX_OK_FOR_BASE_P (op1)) \
1326 if (RTX_OK_FOR_INDEX_P (op0) \
1327 || RTX_OK_FOR_OFFSET_P (op0)) \
1331 else if (GET_CODE (X) == LO_SUM) \
1333 register rtx op0 = XEXP (X, 0); \
1334 register rtx op1 = XEXP (X, 1); \
1335 if (RTX_OK_FOR_BASE_P (op0) \
1336 && CONSTANT_P (op1)) \
1339 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1343 /* Try machine-dependent ways of modifying an illegitimate address
1344 to be legitimate. If we find one, return the new, valid address.
1345 This macro is used in only one place: `memory_address' in explow.c.
1347 OLDX is the address as it was before break_out_memory_refs was called.
1348 In some cases it is useful to look at this to decide what needs to be done.
1350 MODE and WIN are passed so that this macro can use
1351 GO_IF_LEGITIMATE_ADDRESS.
1353 It is always safe for this macro to do nothing. It exists to recognize
1354 opportunities to optimize the output. */
1356 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1357 extern struct rtx_def *legitimize_pic_address ();
1358 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1359 { rtx sparc_x = (X); \
1360 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1361 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1362 force_operand (XEXP (X, 0), NULL_RTX)); \
1363 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1364 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1365 force_operand (XEXP (X, 1), NULL_RTX)); \
1366 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1367 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1369 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1370 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1371 force_operand (XEXP (X, 1), NULL_RTX)); \
1372 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1374 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
1375 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1376 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1377 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1378 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1379 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1380 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1381 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1382 || GET_CODE (X) == LABEL_REF) \
1383 (X) = gen_rtx (LO_SUM, Pmode, \
1384 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1385 if (memory_address_p (MODE, X)) \
1388 /* Go to LABEL if ADDR (a legitimate address expression)
1389 has an effect that depends on the machine mode it is used for.
1390 On the SPARC this is never true. */
1392 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1394 /* Specify the machine mode that this machine uses
1395 for the index in the tablejump instruction. */
1396 #define CASE_VECTOR_MODE SImode
1398 /* Define this if the tablejump instruction expects the table
1399 to contain offsets from the address of the table.
1400 Do not define this if the table should contain absolute addresses. */
1401 /* #define CASE_VECTOR_PC_RELATIVE */
1403 /* Specify the tree operation to be used to convert reals to integers. */
1404 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1406 /* This is the kind of divide that is easiest to do in the general case. */
1407 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1409 /* Define this as 1 if `char' should by default be signed; else as 0. */
1410 #define DEFAULT_SIGNED_CHAR 1
1412 /* Max number of bytes we can move from memory to memory
1413 in one reasonably fast instruction. */
1416 #if 0 /* Sun 4 has matherr, so this is no good. */
1417 /* This is the value of the error code EDOM for this machine,
1418 used by the sqrt instruction. */
1419 #define TARGET_EDOM 33
1421 /* This is how to refer to the variable errno. */
1422 #define GEN_ERRNO_RTX \
1423 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1426 /* Define if operations between registers always perform the operation
1427 on the full register even if a narrower mode is specified. */
1428 #define WORD_REGISTER_OPERATIONS
1430 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1431 will either zero-extend or sign-extend. The value of this macro should
1432 be the code that says which one of the two operations is implicitly
1433 done, NIL if none. */
1434 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1436 /* Nonzero if access to memory by bytes is slow and undesirable.
1437 For RISC chips, it means that access to memory by bytes is no
1438 better than access by words when possible, so grab a whole word
1439 and maybe make use of that. */
1440 #define SLOW_BYTE_ACCESS 1
1442 /* We assume that the store-condition-codes instructions store 0 for false
1443 and some other value for true. This is the value stored for true. */
1445 #define STORE_FLAG_VALUE 1
1447 /* When a prototype says `char' or `short', really pass an `int'. */
1448 #define PROMOTE_PROTOTYPES
1450 /* Define this to be nonzero if shift instructions ignore all but the low-order
1452 #define SHIFT_COUNT_TRUNCATED 1
1454 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1455 is done just by pretending it is already truncated. */
1456 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1458 /* Specify the machine mode that pointers have.
1459 After generation of rtl, the compiler makes no further distinction
1460 between pointers and any other objects of this machine mode. */
1461 #define Pmode SImode
1463 /* Generate calls to memcpy, memcmp and memset. */
1464 #define TARGET_MEM_FUNCTIONS
1466 /* Add any extra modes needed to represent the condition code.
1468 On the Sparc, we have a "no-overflow" mode which is used when an add or
1469 subtract insn is used to set the condition code. Different branches are
1470 used in this case for some operations.
1472 We also have two modes to indicate that the relevant condition code is
1473 in the floating-point condition code register. One for comparisons which
1474 will generate an exception if the result is unordered (CCFPEmode) and
1475 one for comparisons which will never trap (CCFPmode). This really should
1476 be a separate register, but we don't want to go to 65 registers. */
1477 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1479 /* Define the names for the modes specified above. */
1480 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1482 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1483 return the mode to be used for the comparison. For floating-point,
1484 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1485 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1486 processing is needed. */
1487 #define SELECT_CC_MODE(OP,X,Y) \
1488 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1489 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1490 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1491 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
1492 ? CC_NOOVmode : CCmode))
1494 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1495 floating point inequality comparison. */
1497 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1499 /* A function address in a call instruction
1500 is a byte address (for indexing purposes)
1501 so give the MEM rtx a byte's mode. */
1502 #define FUNCTION_MODE SImode
1504 /* Define this if addresses of constant functions
1505 shouldn't be put through pseudo regs where they can be cse'd.
1506 Desirable on machines where ordinary constants are expensive
1507 but a CALL with constant address is cheap. */
1508 #define NO_FUNCTION_CSE
1510 /* alloca should avoid clobbering the old register save area. */
1511 #define SETJMP_VIA_SAVE_AREA
1513 /* Define subroutines to call to handle multiply and divide.
1514 Use the subroutines that Sun's library provides.
1515 The `*' prevents an underscore from being prepended by the compiler. */
1517 #define DIVSI3_LIBCALL "*.div"
1518 #define UDIVSI3_LIBCALL "*.udiv"
1519 #define MODSI3_LIBCALL "*.rem"
1520 #define UMODSI3_LIBCALL "*.urem"
1521 /* .umul is a little faster than .mul. */
1522 #define MULSI3_LIBCALL "*.umul"
1524 /* Define library calls for quad FP operations. These are all part of the
1526 #define ADDTF3_LIBCALL "_Q_add"
1527 #define SUBTF3_LIBCALL "_Q_sub"
1528 #define MULTF3_LIBCALL "_Q_mul"
1529 #define DIVTF3_LIBCALL "_Q_div"
1530 #define SQRTTF2_LIBCALL "_Q_sqrt"
1531 #define FLOATSITF2_LIBCALL "_Q_itoq"
1532 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
1533 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
1534 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
1535 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
1536 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
1537 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
1538 #define EQTF2_LIBCALL "_Q_feq"
1539 #define NETF2_LIBCALL "_Q_fne"
1540 #define GTTF2_LIBCALL "_Q_fgt"
1541 #define GETF2_LIBCALL "_Q_fge"
1542 #define LTTF2_LIBCALL "_Q_flt"
1543 #define LETF2_LIBCALL "_Q_fle"
1545 /* Compute the cost of computing a constant rtl expression RTX
1546 whose rtx-code is CODE. The body of this macro is a portion
1547 of a switch statement. If the code is computed here,
1548 return it with a return statement. Otherwise, break from the switch. */
1550 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1552 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1560 case CONST_DOUBLE: \
1561 if (GET_MODE (RTX) == DImode) \
1562 if ((XINT (RTX, 3) == 0 \
1563 && (unsigned) XINT (RTX, 2) < 0x1000) \
1564 || (XINT (RTX, 3) == -1 \
1565 && XINT (RTX, 2) < 0 \
1566 && XINT (RTX, 2) >= -0x1000)) \
1570 /* Compute the cost of an address. For the sparc, all valid addresses are
1573 #define ADDRESS_COST(RTX) 1
1575 /* Compute extra cost of moving data between one register class
1577 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1578 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1579 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1581 /* Provide the costs of a rtl expression. This is in the body of a
1582 switch on CODE. The purpose for the cost of MULT is to encourage
1583 `synth_mult' to find a synthetic multiply when reasonable.
1585 If we need more than 12 insns to do a multiply, then go out-of-line,
1586 since the call overhead will be < 10% of the cost of the multiply. */
1588 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1590 return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
1595 return COSTS_N_INSNS (25); \
1596 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1597 so that cse will favor the latter. */ \
1602 /* Conditional branches with empty delay slots have a length of two. */
1603 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1604 if (GET_CODE (INSN) == CALL_INSN \
1605 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1608 /* Control the assembler format that we output. */
1610 /* Output at beginning of assembler file. */
1612 #define ASM_FILE_START(file)
1614 /* Output to assembler file text saying following lines
1615 may contain character constants, extra white space, comments, etc. */
1617 #define ASM_APP_ON ""
1619 /* Output to assembler file text saying following lines
1620 no longer contain unusual constructs. */
1622 #define ASM_APP_OFF ""
1624 #define ASM_LONG ".word"
1625 #define ASM_SHORT ".half"
1626 #define ASM_BYTE_OP ".byte"
1628 /* Output before read-only data. */
1630 #define TEXT_SECTION_ASM_OP ".text"
1632 /* Output before writable data. */
1634 #define DATA_SECTION_ASM_OP ".data"
1636 /* How to refer to registers in assembler output.
1637 This sequence is indexed by compiler's hard-register-number (see above). */
1639 #define REGISTER_NAMES \
1640 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1641 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1642 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1643 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1644 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1645 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1646 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1647 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1649 /* Define additional names for use in asm clobbers and asm declarations.
1651 We define the fake Condition Code register as an alias for reg 0 (which
1652 is our `condition code' register), so that condition codes can easily
1653 be clobbered by an asm. No such register actually exists. Condition
1654 codes are partly stored in the PSR and partly in the FSR. */
1656 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1658 /* How to renumber registers for dbx and gdb. */
1660 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1662 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1663 since the length can run past this up to a continuation point. */
1664 #define DBX_CONTIN_LENGTH 1500
1666 /* This is how to output a note to DBX telling it the line number
1667 to which the following sequence of instructions corresponds.
1669 This is needed for SunOS 4.0, and should not hurt for 3.2
1671 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1672 { static int sym_lineno = 1; \
1673 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1674 line, sym_lineno, sym_lineno); \
1677 /* This is how to output the definition of a user-level label named NAME,
1678 such as the label on a static function or variable NAME. */
1680 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1681 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1683 /* This is how to output a command to make the user-level label named NAME
1684 defined for reference from other files. */
1686 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1687 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1689 /* This is how to output a reference to a user-level label named NAME.
1690 `assemble_name' uses this. */
1692 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1693 fprintf (FILE, "_%s", NAME)
1695 /* This is how to output a definition of an internal numbered label where
1696 PREFIX is the class of label and NUM is the number within the class. */
1698 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1699 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1701 /* This is how to output a reference to an internal numbered label where
1702 PREFIX is the class of label and NUM is the number within the class. */
1703 /* FIXME: This should be used throughout gcc, and documented in the texinfo
1704 files. There is no reason you should have to allocate a buffer and
1705 `sprintf' to reference an internal label (as opposed to defining it). */
1707 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1708 fprintf (FILE, "%s%d", PREFIX, NUM)
1710 /* This is how to store into the string LABEL
1711 the symbol_ref name of an internal numbered label where
1712 PREFIX is the class of label and NUM is the number within the class.
1713 This is suitable for output with `assemble_name'. */
1715 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1716 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1718 /* This is how to output an assembler line defining a `double' constant. */
1720 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1723 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1724 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1725 ASM_LONG, t[0], ASM_LONG, t[1]); \
1728 /* This is how to output an assembler line defining a `float' constant. */
1730 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1733 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1734 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1737 /* This is how to output an assembler line defining a `long double'
1740 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1743 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1744 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1745 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1748 /* This is how to output an assembler line defining an `int' constant. */
1750 #define ASM_OUTPUT_INT(FILE,VALUE) \
1751 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1752 output_addr_const (FILE, (VALUE)), \
1753 fprintf (FILE, "\n"))
1755 /* This is how to output an assembler line defining a DImode constant. */
1756 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1757 output_double_int (FILE, VALUE)
1759 /* Likewise for `char' and `short' constants. */
1761 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1762 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1763 output_addr_const (FILE, (VALUE)), \
1764 fprintf (FILE, "\n"))
1766 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1767 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1768 output_addr_const (FILE, (VALUE)), \
1769 fprintf (FILE, "\n"))
1771 /* This is how to output an assembler line for a numeric constant byte. */
1773 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1774 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1776 /* This is how to output an element of a case-vector that is absolute. */
1778 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1781 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1782 fprintf (FILE, "\t.word\t"); \
1783 assemble_name (FILE, label); \
1784 fprintf (FILE, "\n"); \
1787 /* This is how to output an element of a case-vector that is relative.
1788 (SPARC uses such vectors only when generating PIC.) */
1790 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1793 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1794 fprintf (FILE, "\t.word\t"); \
1795 assemble_name (FILE, label); \
1796 fprintf (FILE, "-1b\n"); \
1799 /* This is how to output an assembler line
1800 that says to advance the location counter
1801 to a multiple of 2**LOG bytes. */
1803 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1805 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1807 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1808 fprintf (FILE, "\t.skip %u\n", (SIZE))
1810 /* This says how to output an assembler line
1811 to define a global common symbol. */
1813 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1814 ( fputs ("\t.common ", (FILE)), \
1815 assemble_name ((FILE), (NAME)), \
1816 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
1818 /* This says how to output an assembler line to define a local common
1821 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1822 ( fputs ("\t.reserve ", (FILE)), \
1823 assemble_name ((FILE), (NAME)), \
1824 fprintf ((FILE), ",%u,\"bss\",%u\n", \
1825 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1827 /* Store in OUTPUT a string (made with alloca) containing
1828 an assembler-name for a local static variable named NAME.
1829 LABELNO is an integer which is different for each call. */
1831 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1832 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1833 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1835 #define IDENT_ASM_OP ".ident"
1837 /* Output #ident as a .ident. */
1839 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1840 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1842 /* Define the parentheses used to group arithmetic operations
1843 in assembler code. */
1845 #define ASM_OPEN_PAREN "("
1846 #define ASM_CLOSE_PAREN ")"
1848 /* Define results of standard character escape sequences. */
1849 #define TARGET_BELL 007
1850 #define TARGET_BS 010
1851 #define TARGET_TAB 011
1852 #define TARGET_NEWLINE 012
1853 #define TARGET_VT 013
1854 #define TARGET_FF 014
1855 #define TARGET_CR 015
1857 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1858 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1860 /* Print operand X (an rtx) in assembler syntax to file FILE.
1861 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1862 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1864 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1866 /* Print a memory address as an operand to reference that memory location. */
1868 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1869 { register rtx base, index = 0; \
1871 register rtx addr = ADDR; \
1872 if (GET_CODE (addr) == REG) \
1873 fputs (reg_names[REGNO (addr)], FILE); \
1874 else if (GET_CODE (addr) == PLUS) \
1876 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1877 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1878 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1879 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1881 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1882 fputs (reg_names[REGNO (base)], FILE); \
1884 fprintf (FILE, "%+d", offset); \
1885 else if (GET_CODE (index) == REG) \
1886 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1887 else if (GET_CODE (index) == SYMBOL_REF) \
1888 fputc ('+', FILE), output_addr_const (FILE, index); \
1891 else if (GET_CODE (addr) == MINUS \
1892 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1894 output_addr_const (FILE, XEXP (addr, 0)); \
1895 fputs ("-(", FILE); \
1896 output_addr_const (FILE, XEXP (addr, 1)); \
1897 fputs ("-.)", FILE); \
1899 else if (GET_CODE (addr) == LO_SUM) \
1901 output_operand (XEXP (addr, 0), 0); \
1902 fputs ("+%lo(", FILE); \
1903 output_address (XEXP (addr, 1)); \
1904 fputc (')', FILE); \
1906 else if (flag_pic && GET_CODE (addr) == CONST \
1907 && GET_CODE (XEXP (addr, 0)) == MINUS \
1908 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1909 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1910 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1912 addr = XEXP (addr, 0); \
1913 output_addr_const (FILE, XEXP (addr, 0)); \
1914 /* Group the args of the second CONST in parenthesis. */ \
1915 fputs ("-(", FILE); \
1916 /* Skip past the second CONST--it does nothing for us. */\
1917 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1918 /* Close the parenthesis. */ \
1919 fputc (')', FILE); \
1923 output_addr_const (FILE, addr); \
1927 /* Declare functions defined in sparc.c and used in templates. */
1929 extern char *singlemove_string ();
1930 extern char *output_move_double ();
1931 extern char *output_move_quad ();
1932 extern char *output_fp_move_double ();
1933 extern char *output_fp_move_quad ();
1934 extern char *output_block_move ();
1935 extern char *output_scc_insn ();
1936 extern char *output_cbranch ();
1937 extern char *output_return ();
1939 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1941 extern int flag_pic;
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