1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
29 Solaris only; otherwise just define __sparc__. Sadly the headers
30 are such a mess there is no Solaris-specific header. */
31 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define_std ("sparc"); \
37 builtin_assert ("cpu=sparc64"); \
38 builtin_assert ("machine=sparc64"); \
42 builtin_assert ("cpu=sparc"); \
43 builtin_assert ("machine=sparc"); \
48 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
49 /* #define SPARC_BI_ARCH */
51 /* Macro used later in this file to determine default architecture. */
52 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
54 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
55 architectures to compile for. We allow targets to choose compile time or
58 #if defined(__sparcv9) || defined(__arch64__)
59 #define TARGET_ARCH32 0
61 #define TARGET_ARCH32 1
65 #define TARGET_ARCH32 (! TARGET_64BIT)
67 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
68 #endif /* SPARC_BI_ARCH */
69 #endif /* IN_LIBGCC2 */
70 #define TARGET_ARCH64 (! TARGET_ARCH32)
72 /* Code model selection in 64-bit environment.
74 The machine mode used for addresses is 32-bit wide:
76 TARGET_CM_32: 32-bit address space.
77 It is the code model used when generating 32-bit code.
79 The machine mode used for addresses is 64-bit wide:
81 TARGET_CM_MEDLOW: 32-bit address space.
82 The executable must be in the low 32 bits of memory.
83 This avoids generating %uhi and %ulo terms. Programs
84 can be statically or dynamically linked.
86 TARGET_CM_MEDMID: 44-bit address space.
87 The executable must be in the low 44 bits of memory,
88 and the %[hml]44 terms are used. The text and data
89 segments have a maximum size of 2GB (31-bit span).
90 The maximum offset from any instruction to the label
91 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
93 TARGET_CM_MEDANY: 64-bit address space.
94 The text and data segments have a maximum size of 2GB
95 (31-bit span) and may be located anywhere in memory.
96 The maximum offset from any instruction to the label
97 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
99 TARGET_CM_EMBMEDANY: 64-bit address space.
100 The text and data segments have a maximum size of 2GB
101 (31-bit span) and may be located anywhere in memory.
102 The global register %g4 contains the start address of
103 the data segment. Programs are statically linked and
104 PIC is not supported.
106 Different code models are not supported in 32-bit environment. */
116 /* Value of -mcmodel specified by user. */
117 extern const char *sparc_cmodel_string;
119 extern enum cmodel sparc_cmodel;
121 /* V9 code model selection. */
122 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
123 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
124 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
125 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
127 #define SPARC_DEFAULT_CMODEL CM_32
129 /* This is call-clobbered in the normal ABI, but is reserved in the
130 home grown (aka upward compatible) embedded ABI. */
131 #define EMBMEDANY_BASE_REG "%g4"
133 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
134 and specified by the user via --with-cpu=foo.
135 This specifies the cpu implementation, not the architecture size. */
136 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
138 #define TARGET_CPU_sparc 0
139 #define TARGET_CPU_v7 0 /* alias for previous */
140 #define TARGET_CPU_sparclet 1
141 #define TARGET_CPU_sparclite 2
142 #define TARGET_CPU_v8 3 /* generic v8 implementation */
143 #define TARGET_CPU_supersparc 4
144 #define TARGET_CPU_hypersparc 5
145 #define TARGET_CPU_sparc86x 6
146 #define TARGET_CPU_sparclite86x 6
147 #define TARGET_CPU_v9 7 /* generic v9 implementation */
148 #define TARGET_CPU_sparcv9 7 /* alias */
149 #define TARGET_CPU_sparc64 7 /* alias */
150 #define TARGET_CPU_ultrasparc 8
151 #define TARGET_CPU_ultrasparc3 9
153 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
154 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
155 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
157 #define CPP_CPU32_DEFAULT_SPEC ""
158 #define ASM_CPU32_DEFAULT_SPEC ""
160 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
161 /* ??? What does Sun's CC pass? */
162 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
163 /* ??? It's not clear how other assemblers will handle this, so by default
164 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
165 is handled in sol2.h. */
166 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
168 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
169 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
170 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
172 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
173 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
174 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
179 #define CPP_CPU64_DEFAULT_SPEC ""
180 #define ASM_CPU64_DEFAULT_SPEC ""
182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
183 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
184 #define CPP_CPU32_DEFAULT_SPEC ""
185 #define ASM_CPU32_DEFAULT_SPEC ""
188 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
189 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
190 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
193 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
194 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
195 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
198 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
199 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
200 #define ASM_CPU32_DEFAULT_SPEC ""
203 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
204 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
205 #define ASM_CPU32_DEFAULT_SPEC ""
208 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
209 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
210 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
215 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
216 #error Unrecognized value in TARGET_CPU_DEFAULT.
221 #define CPP_CPU_DEFAULT_SPEC \
222 (DEFAULT_ARCH32_P ? "\
223 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
224 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
226 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
227 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
229 #define ASM_CPU_DEFAULT_SPEC \
230 (DEFAULT_ARCH32_P ? "\
231 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
232 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
234 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
235 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
238 #else /* !SPARC_BI_ARCH */
240 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
241 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
243 #endif /* !SPARC_BI_ARCH */
245 /* Define macros to distinguish architectures. */
247 /* Common CPP definitions used by CPP_SPEC amongst the various targets
248 for handling -mcpu=xxx switches. */
249 #define CPP_CPU_SPEC "\
250 %{msoft-float:-D_SOFT_FLOAT} \
252 %{msparclite:-D__sparclite__} \
253 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
254 %{mv8:-D__sparc_v8__} \
255 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
256 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
257 %{mcpu=sparclite:-D__sparclite__} \
258 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
259 %{mcpu=v8:-D__sparc_v8__} \
260 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
261 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
262 %{mcpu=sparclite86x:-D__sparclite86x__} \
263 %{mcpu=v9:-D__sparc_v9__} \
264 %{mcpu=ultrasparc:-D__sparc_v9__} \
265 %{mcpu=ultrasparc3:-D__sparc_v9__} \
266 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
268 #define CPP_ARCH32_SPEC ""
269 #define CPP_ARCH64_SPEC "-D__arch64__"
271 #define CPP_ARCH_DEFAULT_SPEC \
272 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
274 #define CPP_ARCH_SPEC "\
275 %{m32:%(cpp_arch32)} \
276 %{m64:%(cpp_arch64)} \
277 %{!m32:%{!m64:%(cpp_arch_default)}} \
280 /* Macros to distinguish endianness. */
281 #define CPP_ENDIAN_SPEC "\
282 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
283 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
285 /* Macros to distinguish the particular subtarget. */
286 #define CPP_SUBTARGET_SPEC ""
288 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
290 /* Prevent error on `-sun4' and `-target sun4' options. */
291 /* This used to translate -dalign to -malign, but that is no good
292 because it can't turn off the usual meaning of making debugging dumps. */
293 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
294 ??? Delete support for -m<cpu> for 2.9. */
297 %{sun4:} %{target:} \
298 %{mcypress:-mcpu=cypress} \
299 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
300 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
303 /* Override in target specific files. */
304 #define ASM_CPU_SPEC "\
305 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
306 %{msparclite:-Asparclite} \
307 %{mf930:-Asparclite} %{mf934:-Asparclite} \
308 %{mcpu=sparclite:-Asparclite} \
309 %{mcpu=sparclite86x:-Asparclite} \
310 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
311 %{mv8plus:-Av8plus} \
313 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
314 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
315 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
318 /* Word size selection, among other things.
319 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
321 #define ASM_ARCH32_SPEC "-32"
322 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
323 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
325 #define ASM_ARCH64_SPEC "-64"
327 #define ASM_ARCH_DEFAULT_SPEC \
328 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
330 #define ASM_ARCH_SPEC "\
331 %{m32:%(asm_arch32)} \
332 %{m64:%(asm_arch64)} \
333 %{!m32:%{!m64:%(asm_arch_default)}} \
336 #ifdef HAVE_AS_RELAX_OPTION
337 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
339 #define ASM_RELAX_SPEC ""
342 /* Special flags to the Sun-4 assembler when using pipe for input. */
345 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
346 %(asm_cpu) %(asm_relax)"
348 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
350 /* This macro defines names of additional specifications to put in the specs
351 that can be used in various specifications like CC1_SPEC. Its definition
352 is an initializer with a subgrouping for each command option.
354 Each subgrouping contains a string constant, that defines the
355 specification name, and a string constant that used by the GCC driver
358 Do not define this macro if it does not need to do anything. */
360 #define EXTRA_SPECS \
361 { "cpp_cpu", CPP_CPU_SPEC }, \
362 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
363 { "cpp_arch32", CPP_ARCH32_SPEC }, \
364 { "cpp_arch64", CPP_ARCH64_SPEC }, \
365 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
366 { "cpp_arch", CPP_ARCH_SPEC }, \
367 { "cpp_endian", CPP_ENDIAN_SPEC }, \
368 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
369 { "asm_cpu", ASM_CPU_SPEC }, \
370 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
371 { "asm_arch32", ASM_ARCH32_SPEC }, \
372 { "asm_arch64", ASM_ARCH64_SPEC }, \
373 { "asm_relax", ASM_RELAX_SPEC }, \
374 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
375 { "asm_arch", ASM_ARCH_SPEC }, \
376 SUBTARGET_EXTRA_SPECS
378 #define SUBTARGET_EXTRA_SPECS
380 /* Because libgcc can generate references back to libc (via .umul etc.) we have
381 to list libc again after the second libgcc. */
382 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
385 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
386 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
388 /* ??? This should be 32 bits for v9 but what can we do? */
389 #define WCHAR_TYPE "short unsigned int"
390 #define WCHAR_TYPE_SIZE 16
392 /* Show we can debug even without a frame pointer. */
393 #define CAN_DEBUG_WITHOUT_FP
395 #define OVERRIDE_OPTIONS sparc_override_options ()
397 /* Generate DBX debugging information. */
399 #define DBX_DEBUGGING_INFO 1
401 /* Run-time compilation parameters selecting different hardware subsets. */
403 extern int target_flags;
405 /* Nonzero if we should generate code to use the fpu. */
407 #define TARGET_FPU (target_flags & MASK_FPU)
409 /* Nonzero if we should assume that double pointers might be unaligned.
410 This can happen when linking gcc compiled code with other compilers,
411 because the ABI only guarantees 4 byte alignment. */
412 #define MASK_UNALIGNED_DOUBLES 4
413 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
415 /* Nonzero means that we should generate code for a v8 sparc. */
417 #define TARGET_V8 (target_flags & MASK_V8)
419 /* Nonzero means that we should generate code for a sparclite.
420 This enables the sparclite specific instructions, but does not affect
421 whether FPU instructions are emitted. */
422 #define MASK_SPARCLITE 0x10
423 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
425 /* Nonzero if we're compiling for the sparclet. */
426 #define MASK_SPARCLET 0x20
427 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
429 /* Nonzero if we're compiling for v9 sparc.
430 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
431 the word size is 64. */
433 #define TARGET_V9 (target_flags & MASK_V9)
435 /* Nonzero to generate code that uses the instructions deprecated in
436 the v9 architecture. This option only applies to v9 systems. */
437 /* ??? This isn't user selectable yet. It's used to enable such insns
438 on 32 bit v9 systems and for the moment they're permanently disabled
439 on 64 bit v9 systems. */
440 #define MASK_DEPRECATED_V8_INSNS 0x80
441 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
443 /* Mask of all CPU selection flags. */
445 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
447 /* Nonzero means don't pass `-assert pure-text' to the linker. */
448 #define MASK_IMPURE_TEXT 0x100
449 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
451 /* 0x200 is unused */
453 /* Nonzero means use the registers that the SPARC ABI reserves for
454 application software. This must be the default to coincide with the
455 setting in FIXED_REGISTERS. */
456 #define MASK_APP_REGS 0x400
457 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
459 /* Option to select how quad word floating point is implemented.
460 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
461 Otherwise, we use the SPARC ABI quad library functions. */
462 #define MASK_HARD_QUAD 0x800
463 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
465 /* Nonzero on little-endian machines. */
466 /* ??? Little endian support currently only exists for sparc86x-elf and
467 sparc64-elf configurations. May eventually want to expand the support
468 to all targets, but for now it's kept local to only those two. */
469 #define MASK_LITTLE_ENDIAN 0x1000
470 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
472 /* 0x2000, 0x4000 are unused */
474 /* Nonzero if pointers are 64 bits. */
475 #define MASK_PTR64 0x8000
476 #define TARGET_PTR64 (target_flags & MASK_PTR64)
478 /* Nonzero if generating code to run in a 64 bit environment.
479 This is intended to only be used by TARGET_ARCH{32,64} as they are the
480 mechanism used to control compile time or run time selection. */
481 #define MASK_64BIT 0x10000
482 #define TARGET_64BIT (target_flags & MASK_64BIT)
484 /* 0x20000,0x40000 unused */
486 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
487 adding 2047 to %sp. This option is for v9 only and is the default. */
488 #define MASK_STACK_BIAS 0x80000
489 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
491 /* 0x100000,0x200000 unused */
493 /* Nonzero means -m{,no-}fpu was passed on the command line. */
494 #define MASK_FPU_SET 0x400000
495 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
497 /* Use the UltraSPARC Visual Instruction Set extensions. */
498 #define MASK_VIS 0x1000000
499 #define TARGET_VIS (target_flags & MASK_VIS)
501 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
502 the current out and global registers and Linux 2.2+ as well. */
503 #define MASK_V8PLUS 0x2000000
504 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
506 /* Force a the fastest alignment on structures to take advantage of
508 #define MASK_FASTER_STRUCTS 0x4000000
509 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
511 /* Use IEEE quad long double. */
512 #define MASK_LONG_DOUBLE_128 0x8000000
513 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
515 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
516 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
517 to get high 32 bits. False in V8+ or V9 because multiply stores
518 a 64 bit result in a register. */
520 #define TARGET_HARD_MUL32 \
521 ((TARGET_V8 || TARGET_SPARCLITE \
522 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
523 && ! TARGET_V8PLUS && TARGET_ARCH32)
525 #define TARGET_HARD_MUL \
526 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
527 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
530 /* Macro to define tables used to set the flags.
531 This is a list in braces of pairs in braces,
532 each pair being { "NAME", VALUE }
533 where VALUE is the bits to set or minus the bits to clear.
534 An empty string NAME is used to identify the default VALUE. */
536 #define TARGET_SWITCHES \
537 { {"fpu", MASK_FPU | MASK_FPU_SET, \
538 N_("Use hardware fp") }, \
539 {"no-fpu", -MASK_FPU, \
540 N_("Do not use hardware fp") }, \
541 {"no-fpu", MASK_FPU_SET, NULL, }, \
542 {"hard-float", MASK_FPU | MASK_FPU_SET, \
543 N_("Use hardware fp") }, \
544 {"soft-float", -MASK_FPU, \
545 N_("Do not use hardware fp") }, \
546 {"soft-float", MASK_FPU_SET, NULL }, \
547 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
548 N_("Assume possible double misalignment") }, \
549 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
550 N_("Assume all doubles are aligned") }, \
551 {"impure-text", MASK_IMPURE_TEXT, \
552 N_("Pass -assert pure-text to linker") }, \
553 {"no-impure-text", -MASK_IMPURE_TEXT, \
554 N_("Do not pass -assert pure-text to linker") }, \
555 {"app-regs", MASK_APP_REGS, \
556 N_("Use ABI reserved registers") }, \
557 {"no-app-regs", -MASK_APP_REGS, \
558 N_("Do not use ABI reserved registers") }, \
559 {"hard-quad-float", MASK_HARD_QUAD, \
560 N_("Use hardware quad fp instructions") }, \
561 {"soft-quad-float", -MASK_HARD_QUAD, \
562 N_("Do not use hardware quad fp instructions") }, \
563 {"v8plus", MASK_V8PLUS, \
564 N_("Compile for v8plus ABI") }, \
565 {"no-v8plus", -MASK_V8PLUS, \
566 N_("Do not compile for v8plus ABI") }, \
568 N_("Utilize Visual Instruction Set") }, \
569 {"no-vis", -MASK_VIS, \
570 N_("Do not utilize Visual Instruction Set") }, \
571 {"ptr64", MASK_PTR64, \
572 N_("Pointers are 64-bit") }, \
573 {"ptr32", -MASK_PTR64, \
574 N_("Pointers are 32-bit") }, \
575 {"32", -MASK_64BIT, \
576 N_("Use 32-bit ABI") }, \
578 N_("Use 64-bit ABI") }, \
579 {"stack-bias", MASK_STACK_BIAS, \
580 N_("Use stack bias") }, \
581 {"no-stack-bias", -MASK_STACK_BIAS, \
582 N_("Do not use stack bias") }, \
583 {"faster-structs", MASK_FASTER_STRUCTS, \
584 N_("Use structs on stronger alignment for double-word copies") }, \
585 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
586 N_("Do not use structs on stronger alignment for double-word copies") }, \
588 N_("Optimize tail call instructions in assembler and linker") }, \
590 N_("Do not optimize tail call instructions in assembler or linker") }, \
592 { "", TARGET_DEFAULT, ""}}
594 /* MASK_APP_REGS must always be the default because that's what
595 FIXED_REGISTERS is set to and -ffixed- is processed before
596 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
597 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
599 /* This is meant to be redefined in target specific files. */
600 #define SUBTARGET_SWITCHES
603 These must match the values for the cpu attribute in sparc.md. */
604 enum processor_type {
608 PROCESSOR_SUPERSPARC,
612 PROCESSOR_HYPERSPARC,
613 PROCESSOR_SPARCLITE86X,
617 PROCESSOR_ULTRASPARC,
618 PROCESSOR_ULTRASPARC3
621 /* This is set from -m{cpu,tune}=xxx. */
622 extern enum processor_type sparc_cpu;
624 /* Recast the cpu class to be the cpu attribute.
625 Every file includes us, but not every file includes insn-attr.h. */
626 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
628 #define TARGET_OPTIONS \
630 { "cpu=", &sparc_select[1].string, \
631 N_("Use features of and schedule code for given CPU"), 0}, \
632 { "tune=", &sparc_select[2].string, \
633 N_("Schedule code for given CPU"), 0}, \
634 { "cmodel=", &sparc_cmodel_string, \
635 N_("Use given SPARC code model"), 0}, \
639 /* This is meant to be redefined in target specific files. */
640 #define SUBTARGET_OPTIONS
642 /* Support for a compile-time default CPU, et cetera. The rules are:
643 --with-cpu is ignored if -mcpu is specified.
644 --with-tune is ignored if -mtune is specified.
645 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
647 #define OPTION_DEFAULT_SPECS \
648 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
649 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
650 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
652 /* sparc_select[0] is reserved for the default cpu. */
653 struct sparc_cpu_select
656 const char *const name;
657 const int set_tune_p;
658 const int set_arch_p;
661 extern struct sparc_cpu_select sparc_select[];
663 /* target machine storage layout */
665 /* Define this if most significant bit is lowest numbered
666 in instructions that operate on numbered bit-fields. */
667 #define BITS_BIG_ENDIAN 1
669 /* Define this if most significant byte of a word is the lowest numbered. */
670 #define BYTES_BIG_ENDIAN 1
672 /* Define this if most significant word of a multiword number is the lowest
674 #define WORDS_BIG_ENDIAN 1
676 /* Define this to set the endianness to use in libgcc2.c, which can
677 not depend on target_flags. */
678 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
679 #define LIBGCC2_WORDS_BIG_ENDIAN 0
681 #define LIBGCC2_WORDS_BIG_ENDIAN 1
684 #define MAX_BITS_PER_WORD 64
686 /* Width of a word, in units (bytes). */
687 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
689 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
691 #define MIN_UNITS_PER_WORD 4
694 /* Now define the sizes of the C data types. */
696 #define SHORT_TYPE_SIZE 16
697 #define INT_TYPE_SIZE 32
698 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
699 #define LONG_LONG_TYPE_SIZE 64
700 #define FLOAT_TYPE_SIZE 32
701 #define DOUBLE_TYPE_SIZE 64
702 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
703 SPARC ABI says that it is 128-bit wide. */
704 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
706 /* Width in bits of a pointer.
707 See also the macro `Pmode' defined below. */
708 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
710 /* If we have to extend pointers (only when TARGET_ARCH64 and not
711 TARGET_PTR64), we want to do it unsigned. This macro does nothing
712 if ptr_mode and Pmode are the same. */
713 #define POINTERS_EXTEND_UNSIGNED 1
715 /* For TARGET_ARCH64 we need this, as we don't have instructions
716 for arithmetic operations which do zero/sign extension at the same time,
717 so without this we end up with a srl/sra after every assignment to an
718 user variable, which means very very bad code. */
719 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
721 && GET_MODE_CLASS (MODE) == MODE_INT \
722 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
725 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
726 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
728 /* Boundary (in *bits*) on which stack pointer should be aligned. */
729 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
730 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
731 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
732 /* Temporary hack until the FIXME above is fixed. This macro is used
733 only in pad_to_arg_alignment in function.c; see the comment there
734 for details about what it does. */
735 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
737 /* ALIGN FRAMES on double word boundaries */
739 #define SPARC_STACK_ALIGN(LOC) \
740 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
742 /* Allocation boundary (in *bits*) for the code of a function. */
743 #define FUNCTION_BOUNDARY 32
745 /* Alignment of field after `int : 0' in a structure. */
746 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
748 /* Every structure's size must be a multiple of this. */
749 #define STRUCTURE_SIZE_BOUNDARY 8
751 /* A bit-field declared as `int' forces `int' alignment for the struct. */
752 #define PCC_BITFIELD_TYPE_MATTERS 1
754 /* No data type wants to be aligned rounder than this. */
755 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
757 /* The best alignment to use in cases where we have a choice. */
758 #define FASTEST_ALIGNMENT 64
760 /* Define this macro as an expression for the alignment of a structure
761 (given by STRUCT as a tree node) if the alignment computed in the
762 usual way is COMPUTED and the alignment explicitly specified was
765 The default is to use SPECIFIED if it is larger; otherwise, use
766 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
767 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
768 (TARGET_FASTER_STRUCTS ? \
769 ((TREE_CODE (STRUCT) == RECORD_TYPE \
770 || TREE_CODE (STRUCT) == UNION_TYPE \
771 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
772 && TYPE_FIELDS (STRUCT) != 0 \
773 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
774 : MAX ((COMPUTED), (SPECIFIED))) \
775 : MAX ((COMPUTED), (SPECIFIED)))
777 /* Make strings word-aligned so strcpy from constants will be faster. */
778 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
779 ((TREE_CODE (EXP) == STRING_CST \
780 && (ALIGN) < FASTEST_ALIGNMENT) \
781 ? FASTEST_ALIGNMENT : (ALIGN))
783 /* Make arrays of chars word-aligned for the same reasons. */
784 #define DATA_ALIGNMENT(TYPE, ALIGN) \
785 (TREE_CODE (TYPE) == ARRAY_TYPE \
786 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
787 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
789 /* Set this nonzero if move instructions will actually fail to work
790 when given unaligned data. */
791 #define STRICT_ALIGNMENT 1
793 /* Things that must be doubleword aligned cannot go in the text section,
794 because the linker fails to align the text section enough!
795 Put them in the data section. This macro is only used in this file. */
796 #define MAX_TEXT_ALIGN 32
798 /* Standard register usage. */
800 /* Number of actual hardware registers.
801 The hardware registers are assigned numbers for the compiler
802 from 0 to just below FIRST_PSEUDO_REGISTER.
803 All registers that the compiler knows about must be given numbers,
804 even those that are not normally considered general registers.
806 SPARC has 32 integer registers and 32 floating point registers.
807 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
808 accessible. We still account for them to simplify register computations
809 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
811 Register 100 is used as the integer condition code register.
812 Register 101 is used as the soft frame pointer register. */
814 #define FIRST_PSEUDO_REGISTER 102
816 #define SPARC_FIRST_FP_REG 32
817 /* Additional V9 fp regs. */
818 #define SPARC_FIRST_V9_FP_REG 64
819 #define SPARC_LAST_V9_FP_REG 95
820 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
821 #define SPARC_FIRST_V9_FCC_REG 96
822 #define SPARC_LAST_V9_FCC_REG 99
824 #define SPARC_FCC_REG 96
825 /* Integer CC reg. We don't distinguish %icc from %xcc. */
826 #define SPARC_ICC_REG 100
828 /* Nonzero if REGNO is an fp reg. */
829 #define SPARC_FP_REG_P(REGNO) \
830 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
832 /* Argument passing regs. */
833 #define SPARC_OUTGOING_INT_ARG_FIRST 8
834 #define SPARC_INCOMING_INT_ARG_FIRST 24
835 #define SPARC_FP_ARG_FIRST 32
837 /* 1 for registers that have pervasive standard uses
838 and are not available for the register allocator.
841 g1 is free to use as temporary.
842 g2-g4 are reserved for applications. Gcc normally uses them as
843 temporaries, but this can be disabled via the -mno-app-regs option.
844 g5 through g7 are reserved for the operating system.
847 g1,g5 are free to use as temporaries, and are free to use between calls
848 if the call is to an external function via the PLT.
849 g4 is free to use as a temporary in the non-embedded case.
850 g4 is reserved in the embedded case.
851 g2-g3 are reserved for applications. Gcc normally uses them as
852 temporaries, but this can be disabled via the -mno-app-regs option.
853 g6-g7 are reserved for the operating system (or application in
855 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
856 currently be a fixed register until this pattern is rewritten.
857 Register 1 is also used when restoring call-preserved registers in large
860 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
861 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
864 #define FIXED_REGISTERS \
865 {1, 0, 2, 2, 2, 2, 1, 1, \
866 0, 0, 0, 0, 0, 0, 1, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 0, 0, 0, 0, 0, 0, 1, 1, \
870 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, \
875 0, 0, 0, 0, 0, 0, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, \
877 0, 0, 0, 0, 0, 0, 0, 0, \
878 0, 0, 0, 0, 0, 0, 0, 0, \
882 /* 1 for registers not available across function calls.
883 These must include the FIXED_REGISTERS and also any
884 registers that can be used without being saved.
885 The latter must include the registers where values are returned
886 and the register where structure-value addresses are passed.
887 Aside from that, you can include as many other registers as you like. */
889 #define CALL_USED_REGISTERS \
890 {1, 1, 1, 1, 1, 1, 1, 1, \
891 1, 1, 1, 1, 1, 1, 1, 1, \
892 0, 0, 0, 0, 0, 0, 0, 0, \
893 0, 0, 0, 0, 0, 0, 1, 1, \
895 1, 1, 1, 1, 1, 1, 1, 1, \
896 1, 1, 1, 1, 1, 1, 1, 1, \
897 1, 1, 1, 1, 1, 1, 1, 1, \
898 1, 1, 1, 1, 1, 1, 1, 1, \
900 1, 1, 1, 1, 1, 1, 1, 1, \
901 1, 1, 1, 1, 1, 1, 1, 1, \
902 1, 1, 1, 1, 1, 1, 1, 1, \
903 1, 1, 1, 1, 1, 1, 1, 1, \
907 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
908 they won't be allocated. */
910 #define CONDITIONAL_REGISTER_USAGE \
913 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
915 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
916 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
918 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
919 /* then honor it. */ \
920 if (TARGET_ARCH32 && fixed_regs[5]) \
922 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
927 for (regno = SPARC_FIRST_V9_FP_REG; \
928 regno <= SPARC_LAST_V9_FP_REG; \
930 fixed_regs[regno] = 1; \
931 /* %fcc0 is used by v8 and v9. */ \
932 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
933 regno <= SPARC_LAST_V9_FCC_REG; \
935 fixed_regs[regno] = 1; \
940 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
941 fixed_regs[regno] = 1; \
943 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
944 /* then honor it. Likewise with g3 and g4. */ \
945 if (fixed_regs[2] == 2) \
946 fixed_regs[2] = ! TARGET_APP_REGS; \
947 if (fixed_regs[3] == 2) \
948 fixed_regs[3] = ! TARGET_APP_REGS; \
949 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
950 fixed_regs[4] = ! TARGET_APP_REGS; \
951 else if (TARGET_CM_EMBMEDANY) \
953 else if (fixed_regs[4] == 2) \
958 /* Return number of consecutive hard regs needed starting at reg REGNO
959 to hold something of mode MODE.
960 This is ordinarily the length in words of a value of mode MODE
961 but can be less for certain modes in special long registers.
963 On SPARC, ordinary registers hold 32 bits worth;
964 this means both integer and floating point registers.
965 On v9, integer regs hold 64 bits worth; floating point regs hold
966 32 bits worth (this includes the new fp regs as even the odd ones are
967 included in the hard register count). */
969 #define HARD_REGNO_NREGS(REGNO, MODE) \
971 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
972 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
973 : (GET_MODE_SIZE (MODE) + 3) / 4) \
974 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
976 /* Due to the ARCH64 discrepancy above we must override this next
978 #define REGMODE_NATURAL_SIZE(MODE) \
979 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
981 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
982 See sparc.c for how we initialize this. */
983 extern const int *hard_regno_mode_classes;
984 extern int sparc_mode_class[];
986 /* ??? Because of the funny way we pass parameters we should allow certain
987 ??? types of float/complex values to be in integer registers during
988 ??? RTL generation. This only matters on arch32. */
989 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
990 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
992 /* Value is 1 if it is a good idea to tie two pseudo registers
993 when one has mode MODE1 and one has mode MODE2.
994 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
995 for any hard reg, then this must be 0 for correct output.
997 For V9: SFmode can't be combined with other float modes, because they can't
998 be allocated to the %d registers. Also, DFmode won't fit in odd %f
999 registers, but SFmode will. */
1000 #define MODES_TIEABLE_P(MODE1, MODE2) \
1001 ((MODE1) == (MODE2) \
1002 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1004 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1005 || (MODE1 != SFmode && MODE2 != SFmode)))))
1007 /* Specify the registers used for certain standard purposes.
1008 The values of these macros are register numbers. */
1010 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1011 /* #define PC_REGNUM */
1013 /* Register to use for pushing function arguments. */
1014 #define STACK_POINTER_REGNUM 14
1016 /* The stack bias (amount by which the hardware register is offset by). */
1017 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1019 /* Actual top-of-stack address is 92/176 greater than the contents of the
1020 stack pointer register for !v9/v9. That is:
1021 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1022 address, and 6*4 bytes for the 6 register parameters.
1023 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1025 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1027 /* Base register for access to local variables of the function. */
1028 #define HARD_FRAME_POINTER_REGNUM 30
1030 /* The soft frame pointer does not have the stack bias applied. */
1031 #define FRAME_POINTER_REGNUM 101
1033 /* Given the stack bias, the stack pointer isn't actually aligned. */
1034 #define INIT_EXPANDERS \
1036 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1038 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1039 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1043 /* Value should be nonzero if functions must have frame pointers.
1044 Zero means the frame pointer need not be set up (and parms
1045 may be accessed via the stack pointer) in functions that seem suitable.
1046 This is computed in `reload', in reload1.c.
1047 Used in flow.c, global.c, and reload1.c. */
1048 #define FRAME_POINTER_REQUIRED \
1049 (! (leaf_function_p () && only_leaf_regs_used ()))
1051 /* Base register for access to arguments of the function. */
1052 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1054 /* Register in which static-chain is passed to a function. This must
1055 not be a register used by the prologue. */
1056 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1058 /* Register which holds offset table for position-independent
1061 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1063 /* Pick a default value we can notice from override_options:
1065 v9: Default is off. */
1067 #define DEFAULT_PCC_STRUCT_RETURN -1
1069 /* Functions which return large structures get the address
1070 to place the wanted value at offset 64 from the frame.
1071 Must reserve 64 bytes for the in and local registers.
1072 v9: Functions which return large structures get the address to place the
1073 wanted value from an invisible first argument. */
1074 #define STRUCT_VALUE_OFFSET 64
1076 /* Define the classes of registers for register constraints in the
1077 machine description. Also define ranges of constants.
1079 One of the classes must always be named ALL_REGS and include all hard regs.
1080 If there is more than one class, another class must be named NO_REGS
1081 and contain no registers.
1083 The name GENERAL_REGS must be the name of a class (or an alias for
1084 another name such as ALL_REGS). This is the class of registers
1085 that is allowed by "g" or "r" in a register constraint.
1086 Also, registers outside this class are allocated only when
1087 instructions express preferences for them.
1089 The classes must be numbered in nondecreasing order; that is,
1090 a larger-numbered class must never be contained completely
1091 in a smaller-numbered class.
1093 For any two classes, it is very desirable that there be another
1094 class that represents their union. */
1096 /* The SPARC has various kinds of registers: general, floating point,
1097 and condition codes [well, it has others as well, but none that we
1098 care directly about].
1100 For v9 we must distinguish between the upper and lower floating point
1101 registers because the upper ones can't hold SFmode values.
1102 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1103 satisfying a group need for a class will also satisfy a single need for
1104 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1107 It is important that one class contains all the general and all the standard
1108 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1109 because reg_class_record() will bias the selection in favor of fp regs,
1110 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1111 because FP_REGS > GENERAL_REGS.
1113 It is also important that one class contain all the general and all the
1114 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1115 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1116 allocate_reload_reg() to bypass it causing an abort because the compiler
1117 thinks it doesn't have a spill reg when in fact it does.
1119 v9 also has 4 floating point condition code registers. Since we don't
1120 have a class that is the union of FPCC_REGS with either of the others,
1121 it is important that it appear first. Otherwise the compiler will die
1122 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1125 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1126 may try to use it to hold an SImode value. See register_operand.
1127 ??? Should %fcc[0123] be handled similarly?
1130 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1131 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1132 ALL_REGS, LIM_REG_CLASSES };
1134 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1136 /* Give names of register classes as strings for dump file. */
1138 #define REG_CLASS_NAMES \
1139 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1140 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1143 /* Define which registers fit in which classes.
1144 This is an initializer for a vector of HARD_REG_SET
1145 of length N_REG_CLASSES. */
1147 #define REG_CLASS_CONTENTS \
1148 {{0, 0, 0, 0}, /* NO_REGS */ \
1149 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1150 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1151 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1152 {0, -1, 0, 0}, /* FP_REGS */ \
1153 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1154 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1155 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1156 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1158 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1160 SImode loads to floating-point registers are not zero-extended.
1161 The definition for LOAD_EXTEND_OP specifies that integer loads
1162 narrower than BITS_PER_WORD will be zero-extended. As a result,
1163 we inhibit changes from SImode unless they are to a mode that is
1164 identical in size. */
1166 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1168 && (FROM) == SImode \
1169 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1170 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1172 /* The same information, inverted:
1173 Return the class number of the smallest class containing
1174 reg number REGNO. This could be a conditional expression
1175 or could index an array. */
1177 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1179 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1181 /* This is the order in which to allocate registers normally.
1183 We put %f0-%f7 last among the float registers, so as to make it more
1184 likely that a pseudo-register which dies in the float return register
1185 area will get allocated to the float return register, thus saving a move
1186 instruction at the end of the function.
1188 Similarly for integer return value registers.
1190 We know in this case that we will not end up with a leaf function.
1192 The register allocator is given the global and out registers first
1193 because these registers are call clobbered and thus less useful to
1194 global register allocation.
1196 Next we list the local and in registers. They are not call clobbered
1197 and thus very useful for global register allocation. We list the input
1198 registers before the locals so that it is more likely the incoming
1199 arguments received in those registers can just stay there and not be
1202 #define REG_ALLOC_ORDER \
1203 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1204 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1206 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1207 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1208 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1209 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1210 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1211 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1212 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1213 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1214 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1215 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1216 96, 97, 98, 99, /* %fcc0-3 */ \
1217 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1219 /* This is the order in which to allocate registers for
1220 leaf functions. If all registers can fit in the global and
1221 output registers, then we have the possibility of having a leaf
1224 The macro actually mentioned the input registers first,
1225 because they get renumbered into the output registers once
1226 we know really do have a leaf function.
1228 To be more precise, this register allocation order is used
1229 when %o7 is found to not be clobbered right before register
1230 allocation. Normally, the reason %o7 would be clobbered is
1231 due to a call which could not be transformed into a sibling
1234 As a consequence, it is possible to use the leaf register
1235 allocation order and not end up with a leaf function. We will
1236 not get suboptimal register allocation in that case because by
1237 definition of being potentially leaf, there were no function
1238 calls. Therefore, allocation order within the local register
1239 window is not critical like it is when we do have function calls. */
1241 #define REG_LEAF_ALLOC_ORDER \
1242 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1243 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1245 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1246 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1247 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1248 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1249 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1250 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1251 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1252 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1253 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1254 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1255 96, 97, 98, 99, /* %fcc0-3 */ \
1256 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1258 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1260 extern char sparc_leaf_regs[];
1261 #define LEAF_REGISTERS sparc_leaf_regs
1263 extern char leaf_reg_remap[];
1264 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1266 /* The class value for index registers, and the one for base regs. */
1267 #define INDEX_REG_CLASS GENERAL_REGS
1268 #define BASE_REG_CLASS GENERAL_REGS
1270 /* Local macro to handle the two v9 classes of FP regs. */
1271 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1273 /* Get reg_class from a letter such as appears in the machine description.
1274 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1275 .md file for v8 and v9.
1276 'd' and 'b' are used for single and double precision VIS operations,
1278 'h' is used for V8+ 64 bit global and out registers. */
1280 #define REG_CLASS_FROM_LETTER(C) \
1282 ? ((C) == 'f' ? FP_REGS \
1283 : (C) == 'e' ? EXTRA_FP_REGS \
1284 : (C) == 'c' ? FPCC_REGS \
1285 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1286 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1287 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1289 : ((C) == 'f' ? FP_REGS \
1290 : (C) == 'e' ? FP_REGS \
1291 : (C) == 'c' ? FPCC_REGS \
1294 /* The letters I, J, K, L and M in a register constraint string
1295 can be used to stand for particular ranges of immediate operands.
1296 This macro defines what the ranges are.
1297 C is the letter, and VALUE is a constant value.
1298 Return 1 if VALUE is in the range specified by C.
1300 `I' is used for the range of constants an insn can actually contain.
1301 `J' is used for the range which is just zero (since that is R0).
1302 `K' is used for constants which can be loaded with a single sethi insn.
1303 `L' is used for the range of constants supported by the movcc insns.
1304 `M' is used for the range of constants supported by the movrcc insns.
1305 `N' is like K, but for constants wider than 32 bits.
1306 `O' is used for the range which is just 4096. */
1308 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1309 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1310 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1311 /* 10 and 11 bit immediates are only used for a few specific insns.
1312 SMALL_INT is used throughout the port so we continue to use it. */
1313 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1314 /* 13 bit immediate, considering only the low 32 bits */
1315 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1316 (INTVAL (X), SImode)))
1317 #define SPARC_SETHI_P(X) \
1318 (((unsigned HOST_WIDE_INT) (X) \
1319 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1320 #define SPARC_SETHI32_P(X) \
1321 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1323 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1324 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1325 : (C) == 'J' ? (VALUE) == 0 \
1326 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1327 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1328 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1329 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1330 : (C) == 'O' ? (VALUE) == 4096 \
1333 /* Similar, but for floating constants, and defining letters G and H.
1334 Here VALUE is the CONST_DOUBLE rtx itself. */
1336 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1337 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1338 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1339 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1342 /* Given an rtx X being reloaded into a reg required to be
1343 in class CLASS, return the class of reg to actually use.
1344 In general this is just CLASS; but on some machines
1345 in some cases it is preferable to use a more restrictive class. */
1346 /* - We can't load constants into FP registers.
1347 - We can't load FP constants into integer registers when soft-float,
1348 because there is no soft-float pattern with a r/F constraint.
1349 - We can't load FP constants into integer registers for TFmode unless
1350 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1351 - Try and reload integer constants (symbolic or otherwise) back into
1352 registers directly, rather than having them dumped to memory. */
1354 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1356 ? ((FP_REG_CLASS_P (CLASS) \
1357 || (CLASS) == GENERAL_OR_FP_REGS \
1358 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1359 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1361 || (GET_MODE (X) == TFmode \
1362 && ! fp_zero_operand (X, TFmode))) \
1364 : (!FP_REG_CLASS_P (CLASS) \
1365 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1370 /* Return the register class of a scratch register needed to load IN into
1371 a register of class CLASS in MODE.
1373 We need a temporary when loading/storing a HImode/QImode value
1374 between memory and the FPU registers. This can happen when combine puts
1375 a paradoxical subreg in a float/fix conversion insn.
1377 We need a temporary when loading/storing a DFmode value between
1378 unaligned memory and the upper FPU registers. */
1380 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1381 ((FP_REG_CLASS_P (CLASS) \
1382 && ((MODE) == HImode || (MODE) == QImode) \
1383 && (GET_CODE (IN) == MEM \
1384 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1385 && true_regnum (IN) == -1))) \
1387 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1388 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1389 && ! mem_min_alignment ((IN), 8)) \
1391 : (((TARGET_CM_MEDANY \
1392 && symbolic_operand ((IN), (MODE))) \
1393 || (TARGET_CM_EMBMEDANY \
1394 && text_segment_operand ((IN), (MODE)))) \
1399 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1400 ((FP_REG_CLASS_P (CLASS) \
1401 && ((MODE) == HImode || (MODE) == QImode) \
1402 && (GET_CODE (IN) == MEM \
1403 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1404 && true_regnum (IN) == -1))) \
1406 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1407 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1408 && ! mem_min_alignment ((IN), 8)) \
1410 : (((TARGET_CM_MEDANY \
1411 && symbolic_operand ((IN), (MODE))) \
1412 || (TARGET_CM_EMBMEDANY \
1413 && text_segment_operand ((IN), (MODE)))) \
1418 /* On SPARC it is not possible to directly move data between
1419 GENERAL_REGS and FP_REGS. */
1420 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1421 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1423 /* Return the stack location to use for secondary memory needed reloads.
1424 We want to use the reserved location just below the frame pointer.
1425 However, we must ensure that there is a frame, so use assign_stack_local
1426 if the frame size is zero. */
1427 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1428 (get_frame_size () == 0 \
1429 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1430 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1431 STARTING_FRAME_OFFSET)))
1433 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1434 because the movsi and movsf patterns don't handle r/f moves.
1435 For v8 we copy the default definition. */
1436 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1438 ? (GET_MODE_BITSIZE (MODE) < 32 \
1439 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1441 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1442 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1445 /* Return the maximum number of consecutive registers
1446 needed to represent mode MODE in a register of class CLASS. */
1447 /* On SPARC, this is the size of MODE in words. */
1448 #define CLASS_MAX_NREGS(CLASS, MODE) \
1449 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1450 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1452 /* Stack layout; function entry, exit and calling. */
1454 /* Define this if pushing a word on the stack
1455 makes the stack pointer a smaller address. */
1456 #define STACK_GROWS_DOWNWARD
1458 /* Define this if the nominal address of the stack frame
1459 is at the high-address end of the local variables;
1460 that is, each additional local variable allocated
1461 goes at a more negative offset in the frame. */
1462 #define FRAME_GROWS_DOWNWARD
1464 /* Offset within stack frame to start allocating local variables at.
1465 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1466 first local allocated. Otherwise, it is the offset to the BEGINNING
1467 of the first local allocated. */
1468 /* This allows space for one TFmode floating point value. */
1469 #define STARTING_FRAME_OFFSET \
1470 (TARGET_ARCH64 ? -16 \
1471 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1473 /* If we generate an insn to push BYTES bytes,
1474 this says how many the stack pointer really advances by.
1475 On SPARC, don't define this because there are no push insns. */
1476 /* #define PUSH_ROUNDING(BYTES) */
1478 /* Offset of first parameter from the argument pointer register value.
1479 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1480 even if this function isn't going to use it.
1481 v9: This is 128 for the ins and locals. */
1482 #define FIRST_PARM_OFFSET(FNDECL) \
1483 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1485 /* Offset from the argument pointer register value to the CFA.
1486 This is different from FIRST_PARM_OFFSET because the register window
1487 comes between the CFA and the arguments. */
1488 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1490 /* When a parameter is passed in a register, stack space is still
1492 !v9: All 6 possible integer registers have backing store allocated.
1493 v9: Only space for the arguments passed is allocated. */
1494 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1495 meaning to the backend. Further, we need to be able to detect if a
1496 varargs/unprototyped function is called, as they may want to spill more
1497 registers than we've provided space. Ugly, ugly. So for now we retain
1498 all 6 slots even for v9. */
1499 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1501 /* Definitions for register elimination. */
1503 #define ELIMINABLE_REGS \
1504 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1505 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1507 /* The way this is structured, we can't eliminate SFP in favor of SP
1508 if the frame pointer is required: we want to use the SFP->HFP elimination
1509 in that case. But the test in update_eliminables doesn't know we are
1510 assuming below that we only do the former elimination. */
1511 #define CAN_ELIMINATE(FROM, TO) \
1512 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1514 /* We always pretend that this is a leaf function because if it's not,
1515 there's no point in trying to eliminate the frame pointer. If it
1516 is a leaf function, we guessed right! */
1517 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1520 if ((TO) == STACK_POINTER_REGNUM) \
1521 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1522 (OFFSET) += SPARC_STACK_BIAS; \
1525 /* Keep the stack pointer constant throughout the function.
1526 This is both an optimization and a necessity: longjmp
1527 doesn't behave itself when the stack pointer moves within
1529 #define ACCUMULATE_OUTGOING_ARGS 1
1531 /* Value is the number of bytes of arguments automatically
1532 popped when returning from a subroutine call.
1533 FUNDECL is the declaration node of the function (as a tree),
1534 FUNTYPE is the data type of the function (as a tree),
1535 or for a library call it is an identifier node for the subroutine name.
1536 SIZE is the number of bytes of arguments passed on the stack. */
1538 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1540 /* Define this macro if the target machine has "register windows". This
1541 C expression returns the register number as seen by the called function
1542 corresponding to register number OUT as seen by the calling function.
1543 Return OUT if register number OUT is not an outbound register. */
1545 #define INCOMING_REGNO(OUT) \
1546 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1548 /* Define this macro if the target machine has "register windows". This
1549 C expression returns the register number as seen by the calling function
1550 corresponding to register number IN as seen by the called function.
1551 Return IN if register number IN is not an inbound register. */
1553 #define OUTGOING_REGNO(IN) \
1554 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1556 /* Define this macro if the target machine has register windows. This
1557 C expression returns true if the register is call-saved but is in the
1560 #define LOCAL_REGNO(REGNO) \
1561 ((REGNO) >= 16 && (REGNO) <= 31)
1563 /* Define how to find the value returned by a function.
1564 VALTYPE is the data type of the value (as a tree).
1565 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1566 otherwise, FUNC is 0. */
1568 /* On SPARC the value is found in the first "output" register. */
1570 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1571 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1573 /* But the called function leaves it in the first "input" register. */
1575 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1576 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1578 /* Define how to find the value returned by a library function
1579 assuming the value has mode MODE. */
1581 #define LIBCALL_VALUE(MODE) \
1582 function_value (NULL_TREE, (MODE), 1)
1584 /* 1 if N is a possible register number for a function value
1585 as seen by the caller.
1586 On SPARC, the first "output" reg is used for integer values,
1587 and the first floating point register is used for floating point values. */
1589 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1591 /* Define the size of space to allocate for the return value of an
1594 #define APPLY_RESULT_SIZE 16
1596 /* 1 if N is a possible register number for function argument passing.
1597 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1599 #define FUNCTION_ARG_REGNO_P(N) \
1601 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1602 : ((N) >= 8 && (N) <= 13))
1604 /* Define a data type for recording info about an argument list
1605 during the scan of that argument list. This data type should
1606 hold all necessary information about the function itself
1607 and about the args processed so far, enough to enable macros
1608 such as FUNCTION_ARG to determine where the next arg should go.
1610 On SPARC (!v9), this is a single integer, which is a number of words
1611 of arguments scanned so far (including the invisible argument,
1612 if any, which holds the structure-value-address).
1613 Thus 7 or more means all following args should go on the stack.
1615 For v9, we also need to know whether a prototype is present. */
1618 int words; /* number of words passed so far */
1619 int prototype_p; /* nonzero if a prototype is present */
1620 int libcall_p; /* nonzero if a library call */
1622 #define CUMULATIVE_ARGS struct sparc_args
1624 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1625 for a call to a function whose data type is FNTYPE.
1626 For a library call, FNTYPE is 0. */
1628 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1629 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1631 /* Update the data in CUM to advance over an argument
1632 of mode MODE and data type TYPE.
1633 TYPE is null for libcalls where that information may not be available. */
1635 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1636 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1638 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1640 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1642 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1643 || TREE_ADDRESSABLE (TYPE)))
1645 /* Determine where to put an argument to a function.
1646 Value is zero to push the argument on the stack,
1647 or a hard register in which to store the argument.
1649 MODE is the argument's machine mode.
1650 TYPE is the data type of the argument (as a tree).
1651 This is null for libcalls where that information may
1653 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1654 the preceding args and about the function being called.
1655 NAMED is nonzero if this argument is a named parameter
1656 (otherwise it is an extra parameter matching an ellipsis). */
1658 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1659 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1661 /* Define where a function finds its arguments.
1662 This is different from FUNCTION_ARG because of register windows. */
1664 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1665 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1667 /* For an arg passed partly in registers and partly in memory,
1668 this is the number of registers used.
1669 For args passed entirely in registers or entirely in memory, zero. */
1671 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1672 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1674 /* A C expression that indicates when an argument must be passed by reference.
1675 If nonzero for an argument, a copy of that argument is made in memory and a
1676 pointer to the argument is passed instead of the argument itself.
1677 The pointer is passed in whatever way is appropriate for passing a pointer
1680 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1681 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1683 /* If defined, a C expression which determines whether, and in which direction,
1684 to pad out an argument with extra space. The value should be of type
1685 `enum direction': either `upward' to pad above the argument,
1686 `downward' to pad below, or `none' to inhibit padding. */
1688 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1689 function_arg_padding ((MODE), (TYPE))
1691 /* If defined, a C expression that gives the alignment boundary, in bits,
1692 of an argument with the specified mode and type. If it is not defined,
1693 PARM_BOUNDARY is used for all arguments.
1694 For sparc64, objects requiring 16 byte alignment are passed that way. */
1696 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1698 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1699 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1700 ? 128 : PARM_BOUNDARY)
1702 /* Define the information needed to generate branch and scc insns. This is
1703 stored from the compare operation. Note that we can't use "rtx" here
1704 since it hasn't been defined! */
1706 extern GTY(()) rtx sparc_compare_op0;
1707 extern GTY(()) rtx sparc_compare_op1;
1710 /* Generate the special assembly code needed to tell the assembler whatever
1711 it might need to know about the return value of a function.
1713 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1714 information to the assembler relating to peephole optimization (done in
1717 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1718 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1720 /* Output the special assembly code needed to tell the assembler some
1721 register is used as global register variable.
1723 SPARC 64bit psABI declares registers %g2 and %g3 as application
1724 registers and %g6 and %g7 as OS registers. Any object using them
1725 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1726 and how they are used (scratch or some global variable).
1727 Linker will then refuse to link together objects which use those
1728 registers incompatibly.
1730 Unless the registers are used for scratch, two different global
1731 registers cannot be declared to the same name, so in the unlikely
1732 case of a global register variable occupying more than one register
1733 we prefix the second and following registers with .gnu.part1. etc. */
1735 extern char sparc_hard_reg_printed[8];
1737 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1738 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1740 if (TARGET_ARCH64) \
1742 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1744 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1745 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1747 if (reg == (REGNO)) \
1748 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1750 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1751 reg, reg - (REGNO), (NAME)); \
1752 sparc_hard_reg_printed[reg] = 1; \
1759 /* Emit rtl for profiling. */
1760 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1762 /* All the work done in PROFILE_HOOK, but still required. */
1763 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1765 /* Set the name of the mcount function for the system. */
1766 #define MCOUNT_FUNCTION "*mcount"
1768 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1769 the stack pointer does not matter. The value is tested only in
1770 functions that have frame pointers.
1771 No definition is equivalent to always zero. */
1773 #define EXIT_IGNORE_STACK \
1774 (get_frame_size () != 0 \
1775 || current_function_calls_alloca || current_function_outgoing_args_size)
1777 /* Define registers used by the epilogue and return instruction. */
1778 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1779 || (current_function_calls_eh_return && (REGNO) == 1))
1781 /* Length in units of the trampoline for entering a nested function. */
1783 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1785 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1787 /* Emit RTL insns to initialize the variable parts of a trampoline.
1788 FNADDR is an RTX for the address of the function's pure code.
1789 CXT is an RTX for the static chain value for the function. */
1791 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1792 if (TARGET_ARCH64) \
1793 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1795 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1797 /* Implement `va_start' for varargs and stdarg. */
1798 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1799 sparc_va_start (valist, nextarg)
1801 /* Implement `va_arg'. */
1802 #define EXPAND_BUILTIN_VA_ARG(valist, type) (abort (), NULL_RTX)
1804 /* Generate RTL to flush the register windows so as to make arbitrary frames
1806 #define SETUP_FRAME_ADDRESSES() \
1807 emit_insn (gen_flush_register_windows ())
1809 /* Given an rtx for the address of a frame,
1810 return an rtx for the address of the word in the frame
1811 that holds the dynamic chain--the previous frame's address. */
1812 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1813 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1815 /* The return address isn't on the stack, it is in a register, so we can't
1816 access it from the current frame pointer. We can access it from the
1817 previous frame pointer though by reading a value from the register window
1819 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1821 /* This is the offset of the return address to the true next instruction to be
1822 executed for the current function. */
1823 #define RETURN_ADDR_OFFSET \
1824 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1826 /* The current return address is in %i7. The return address of anything
1827 farther back is in the register window save area at [%fp+60]. */
1828 /* ??? This ignores the fact that the actual return address is +8 for normal
1829 returns, and +12 for structure returns. */
1830 #define RETURN_ADDR_RTX(count, frame) \
1832 ? gen_rtx_REG (Pmode, 31) \
1833 : gen_rtx_MEM (Pmode, \
1834 memory_address (Pmode, plus_constant (frame, \
1835 15 * UNITS_PER_WORD \
1836 + SPARC_STACK_BIAS))))
1838 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1839 +12, but always using +8 is close enough for frame unwind purposes.
1840 Actually, just using %o7 is close enough for unwinding, but %o7+8
1841 is something you can return to. */
1842 #define INCOMING_RETURN_ADDR_RTX \
1843 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1844 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1846 /* The offset from the incoming value of %sp to the top of the stack frame
1847 for the current function. On sparc64, we have to account for the stack
1849 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1851 /* Describe how we implement __builtin_eh_return. */
1852 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1853 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1854 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1856 /* Select a format to encode pointers in exception handling data. CODE
1857 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1858 true if the symbol may be affected by dynamic relocations.
1860 If assembler and linker properly support .uaword %r_disp32(foo),
1861 then use PC relative 32-bit relocations instead of absolute relocs
1862 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1863 for binaries, to save memory.
1865 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1866 symbol %r_disp32() is against was not local, but .hidden. In that
1867 case, we have to use DW_EH_PE_absptr for pic personality. */
1868 #ifdef HAVE_AS_SPARC_UA_PCREL
1869 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1870 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1872 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1873 : ((TARGET_ARCH64 && ! GLOBAL) \
1874 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1877 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1879 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1880 : ((TARGET_ARCH64 && ! GLOBAL) \
1881 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1885 /* Emit a PC-relative relocation. */
1886 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1888 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1889 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1890 assemble_name (FILE, LABEL); \
1891 fputc (')', FILE); \
1895 /* Addressing modes, and classification of registers for them. */
1897 /* Macros to check register numbers against specific register classes. */
1899 /* These assume that REGNO is a hard or pseudo reg number.
1900 They give nonzero only if REGNO is a hard reg of the suitable class
1901 or a pseudo reg currently allocated to a suitable hard reg.
1902 Since they use reg_renumber, they are safe only once reg_renumber
1903 has been allocated, which happens in local-alloc.c. */
1905 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1906 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1907 || (REGNO) == FRAME_POINTER_REGNUM \
1908 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1910 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1912 #define REGNO_OK_FOR_FP_P(REGNO) \
1913 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1914 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1915 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1917 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1918 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1920 /* Now macros that check whether X is a register and also,
1921 strictly, whether it is in a specified class.
1923 These macros are specific to the SPARC, and may be used only
1924 in code for printing assembler insns and in conditions for
1925 define_optimization. */
1927 /* 1 if X is an fp register. */
1929 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1931 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1932 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1934 /* Maximum number of registers that can appear in a valid memory address. */
1936 #define MAX_REGS_PER_ADDRESS 2
1938 /* Recognize any constant value that is a valid address.
1939 When PIC, we do not accept an address that would require a scratch reg
1940 to load into a register. */
1942 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1944 /* Define this, so that when PIC, reload won't try to reload invalid
1945 addresses which require two reload registers. */
1947 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1949 /* Nonzero if the constant value X is a legitimate general operand.
1950 Anything can be made to work except floating point constants.
1951 If TARGET_VIS, 0.0 can be made to work as well. */
1953 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1955 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1956 and check its validity for a certain class.
1957 We have two alternate definitions for each of them.
1958 The usual definition accepts all pseudo regs; the other rejects
1959 them unless they have been allocated suitable hard regs.
1960 The symbol REG_OK_STRICT causes the latter definition to be used.
1962 Most source files want to accept pseudo regs in the hope that
1963 they will get allocated to the class that the insn wants them to be in.
1964 Source files for reload pass need to be strict.
1965 After reload, it makes no difference, since pseudo regs have
1966 been eliminated by then. */
1968 /* Optional extra constraints for this machine.
1970 'Q' handles floating point constants which can be moved into
1971 an integer register with a single sethi instruction.
1973 'R' handles floating point constants which can be moved into
1974 an integer register with a single mov instruction.
1976 'S' handles floating point constants which can be moved into
1977 an integer register using a high/lo_sum sequence.
1979 'T' handles memory addresses where the alignment is known to
1980 be at least 8 bytes.
1982 `U' handles all pseudo registers or a hard even numbered
1983 integer register, needed for ldd/std instructions.
1985 'W' handles the memory operand when moving operands in/out
1986 of 'e' constraint floating point registers. */
1988 #ifndef REG_OK_STRICT
1990 /* Nonzero if X is a hard reg that can be used as an index
1991 or if it is a pseudo reg. */
1992 #define REG_OK_FOR_INDEX_P(X) \
1994 || REGNO (X) == FRAME_POINTER_REGNUM \
1995 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1997 /* Nonzero if X is a hard reg that can be used as a base reg
1998 or if it is a pseudo reg. */
1999 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2001 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2002 'W' is like 'T' but is assumed true on arch64.
2004 Remember to accept pseudo-registers for memory constraints if reload is
2007 #define EXTRA_CONSTRAINT(OP, C) \
2008 sparc_extra_constraint_check(OP, C, 0)
2012 /* Nonzero if X is a hard reg that can be used as an index. */
2013 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2014 /* Nonzero if X is a hard reg that can be used as a base reg. */
2015 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2017 #define EXTRA_CONSTRAINT(OP, C) \
2018 sparc_extra_constraint_check(OP, C, 1)
2022 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2024 #ifdef HAVE_AS_OFFSETABLE_LO10
2025 #define USE_AS_OFFSETABLE_LO10 1
2027 #define USE_AS_OFFSETABLE_LO10 0
2030 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2031 that is a valid memory address for an instruction.
2032 The MODE argument is the machine mode for the MEM expression
2033 that wants to use this address.
2035 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2036 ordinarily. This changes a bit when generating PIC.
2038 If you change this, execute "rm explow.o recog.o reload.o". */
2040 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
2042 #define RTX_OK_FOR_BASE_P(X) \
2043 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2044 || (GET_CODE (X) == SUBREG \
2045 && GET_CODE (SUBREG_REG (X)) == REG \
2046 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2048 #define RTX_OK_FOR_INDEX_P(X) \
2049 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2050 || (GET_CODE (X) == SUBREG \
2051 && GET_CODE (SUBREG_REG (X)) == REG \
2052 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2054 #define RTX_OK_FOR_OFFSET_P(X) \
2055 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2057 #define RTX_OK_FOR_OLO10_P(X) \
2058 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2060 #ifdef REG_OK_STRICT
2061 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2063 if (legitimate_address_p (MODE, X, 1)) \
2067 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2069 if (legitimate_address_p (MODE, X, 0)) \
2074 /* Go to LABEL if ADDR (a legitimate address expression)
2075 has an effect that depends on the machine mode it is used for.
2081 is not equivalent to
2083 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2085 because [%l7+a+1] is interpreted as the address of (a+1). */
2087 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2089 if (flag_pic == 1) \
2091 if (GET_CODE (ADDR) == PLUS) \
2093 rtx op0 = XEXP (ADDR, 0); \
2094 rtx op1 = XEXP (ADDR, 1); \
2095 if (op0 == pic_offset_table_rtx \
2096 && SYMBOLIC_CONST (op1)) \
2102 /* Try machine-dependent ways of modifying an illegitimate address
2103 to be legitimate. If we find one, return the new, valid address.
2104 This macro is used in only one place: `memory_address' in explow.c.
2106 OLDX is the address as it was before break_out_memory_refs was called.
2107 In some cases it is useful to look at this to decide what needs to be done.
2109 MODE and WIN are passed so that this macro can use
2110 GO_IF_LEGITIMATE_ADDRESS.
2112 It is always safe for this macro to do nothing. It exists to recognize
2113 opportunities to optimize the output. */
2115 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2116 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2118 (X) = legitimize_address (X, OLDX, MODE); \
2119 if (memory_address_p (MODE, X)) \
2123 /* Try a machine-dependent way of reloading an illegitimate address
2124 operand. If we find one, push the reload and jump to WIN. This
2125 macro is used in only one place: `find_reloads_address' in reload.c.
2127 For SPARC 32, we wish to handle addresses by splitting them into
2128 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2129 This cuts the number of extra insns by one.
2131 Do nothing when generating PIC code and the address is a
2132 symbolic operand or requires a scratch register. */
2134 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2136 /* Decompose SImode constants into hi+lo_sum. We do have to \
2137 rerecognize what we produce, so be careful. */ \
2138 if (CONSTANT_P (X) \
2139 && (MODE != TFmode || TARGET_ARCH64) \
2140 && GET_MODE (X) == SImode \
2141 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2143 && (symbolic_operand (X, Pmode) \
2144 || pic_address_needs_scratch (X))) \
2145 && sparc_cmodel <= CM_MEDLOW) \
2147 X = gen_rtx_LO_SUM (GET_MODE (X), \
2148 gen_rtx_HIGH (GET_MODE (X), X), X); \
2149 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2150 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2154 /* ??? 64-bit reloads. */ \
2157 /* Specify the machine mode that this machine uses
2158 for the index in the tablejump instruction. */
2159 /* If we ever implement any of the full models (such as CM_FULLANY),
2160 this has to be DImode in that case */
2161 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2162 #define CASE_VECTOR_MODE \
2163 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2165 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2166 we have to sign extend which slows things down. */
2167 #define CASE_VECTOR_MODE \
2168 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2171 /* Define this as 1 if `char' should by default be signed; else as 0. */
2172 #define DEFAULT_SIGNED_CHAR 1
2174 /* Max number of bytes we can move from memory to memory
2175 in one reasonably fast instruction. */
2178 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2179 move-instruction pairs, we will do a movstr or libcall instead. */
2181 #define MOVE_RATIO (optimize_size ? 3 : 8)
2183 /* Define if operations between registers always perform the operation
2184 on the full register even if a narrower mode is specified. */
2185 #define WORD_REGISTER_OPERATIONS
2187 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2188 will either zero-extend or sign-extend. The value of this macro should
2189 be the code that says which one of the two operations is implicitly
2190 done, NIL if none. */
2191 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2193 /* Nonzero if access to memory by bytes is slow and undesirable.
2194 For RISC chips, it means that access to memory by bytes is no
2195 better than access by words when possible, so grab a whole word
2196 and maybe make use of that. */
2197 #define SLOW_BYTE_ACCESS 1
2199 /* Define this to be nonzero if shift instructions ignore all but the low-order
2201 #define SHIFT_COUNT_TRUNCATED 1
2203 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2204 is done just by pretending it is already truncated. */
2205 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2207 /* Specify the machine mode used for addresses. */
2208 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2210 /* Generate calls to memcpy, memcmp and memset. */
2211 #define TARGET_MEM_FUNCTIONS
2213 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2214 return the mode to be used for the comparison. For floating-point,
2215 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2216 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2217 processing is needed. */
2218 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2220 /* Return nonzero if MODE implies a floating point inequality can be
2221 reversed. For SPARC this is always true because we have a full
2222 compliment of ordered and unordered comparisons, but until generic
2223 code knows how to reverse it correctly we keep the old definition. */
2224 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2226 /* A function address in a call instruction for indexing purposes. */
2227 #define FUNCTION_MODE Pmode
2229 /* Define this if addresses of constant functions
2230 shouldn't be put through pseudo regs where they can be cse'd.
2231 Desirable on machines where ordinary constants are expensive
2232 but a CALL with constant address is cheap. */
2233 #define NO_FUNCTION_CSE
2235 /* alloca should avoid clobbering the old register save area. */
2236 #define SETJMP_VIA_SAVE_AREA
2238 /* The _Q_* comparison libcalls return booleans. */
2239 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2241 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2242 that the inputs are fully consumed before the output memory is clobbered. */
2244 #define TARGET_BUGGY_QP_LIB 0
2246 /* Assume by default that we do not have the Solaris-specific conversion
2247 routines nor 64-bit integer multiply and divide routines. */
2249 #define SUN_CONVERSION_LIBFUNCS 0
2250 #define DITF_CONVERSION_LIBFUNCS 0
2251 #define SUN_INTEGER_MULTIPLY_64 0
2253 /* Compute extra cost of moving data between one register class
2255 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2256 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2257 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2258 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2259 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2260 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2261 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2263 /* Provide the cost of a branch. For pre-v9 processors we use
2264 a value of 3 to take into account the potential annulling of
2265 the delay slot (which ends up being a bubble in the pipeline slot)
2266 plus a cycle to take into consideration the instruction cache
2269 On v9 and later, which have branch prediction facilities, we set
2270 it to the depth of the pipeline as that is the cost of a
2271 mispredicted branch. */
2273 #define BRANCH_COST \
2274 ((sparc_cpu == PROCESSOR_V9 \
2275 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2277 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2280 #define PREFETCH_BLOCK \
2281 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2282 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2285 #define SIMULTANEOUS_PREFETCHES \
2286 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2288 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2291 /* Control the assembler format that we output. */
2293 /* A C string constant describing how to begin a comment in the target
2294 assembler language. The compiler assumes that the comment will end at
2295 the end of the line. */
2297 #define ASM_COMMENT_START "!"
2299 /* Output to assembler file text saying following lines
2300 may contain character constants, extra white space, comments, etc. */
2302 #define ASM_APP_ON ""
2304 /* Output to assembler file text saying following lines
2305 no longer contain unusual constructs. */
2307 #define ASM_APP_OFF ""
2309 /* How to refer to registers in assembler output.
2310 This sequence is indexed by compiler's hard-register-number (see above). */
2312 #define REGISTER_NAMES \
2313 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2314 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2315 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2316 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2317 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2318 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2319 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2320 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2321 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2322 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2323 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2324 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2325 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2327 /* Define additional names for use in asm clobbers and asm declarations. */
2329 #define ADDITIONAL_REGISTER_NAMES \
2330 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2332 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2333 can run past this up to a continuation point. Once we used 1500, but
2334 a single entry in C++ can run more than 500 bytes, due to the length of
2335 mangled symbol names. dbxout.c should really be fixed to do
2336 continuations when they are actually needed instead of trying to
2338 #define DBX_CONTIN_LENGTH 1000
2340 /* This is how to output a command to make the user-level label named NAME
2341 defined for reference from other files. */
2343 /* Globalizing directive for a label. */
2344 #define GLOBAL_ASM_OP "\t.global "
2346 /* The prefix to add to user-visible assembler symbols. */
2348 #define USER_LABEL_PREFIX "_"
2350 /* This is how to store into the string LABEL
2351 the symbol_ref name of an internal numbered label where
2352 PREFIX is the class of label and NUM is the number within the class.
2353 This is suitable for output with `assemble_name'. */
2355 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2356 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2358 /* This is how we hook in and defer the case-vector until the end of
2360 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2361 sparc_defer_case_vector ((LAB),(VEC), 0)
2363 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2364 sparc_defer_case_vector ((LAB),(VEC), 1)
2366 /* This is how to output an element of a case-vector that is absolute. */
2368 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2371 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2372 if (CASE_VECTOR_MODE == SImode) \
2373 fprintf (FILE, "\t.word\t"); \
2375 fprintf (FILE, "\t.xword\t"); \
2376 assemble_name (FILE, label); \
2377 fputc ('\n', FILE); \
2380 /* This is how to output an element of a case-vector that is relative.
2381 (SPARC uses such vectors only when generating PIC.) */
2383 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2386 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2387 if (CASE_VECTOR_MODE == SImode) \
2388 fprintf (FILE, "\t.word\t"); \
2390 fprintf (FILE, "\t.xword\t"); \
2391 assemble_name (FILE, label); \
2392 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2393 fputc ('-', FILE); \
2394 assemble_name (FILE, label); \
2395 fputc ('\n', FILE); \
2398 /* This is what to output before and after case-vector (both
2399 relative and absolute). If .subsection -1 works, we put case-vectors
2400 at the beginning of the current section. */
2402 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2404 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2405 fprintf(FILE, "\t.subsection\t-1\n")
2407 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2408 fprintf(FILE, "\t.previous\n")
2412 /* This is how to output an assembler line
2413 that says to advance the location counter
2414 to a multiple of 2**LOG bytes. */
2416 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2418 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2420 /* This is how to output an assembler line that says to advance
2421 the location counter to a multiple of 2**LOG bytes using the
2422 "nop" instruction as padding. */
2423 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2425 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2427 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2428 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2430 /* This says how to output an assembler line
2431 to define a global common symbol. */
2433 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2434 ( fputs ("\t.common ", (FILE)), \
2435 assemble_name ((FILE), (NAME)), \
2436 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2438 /* This says how to output an assembler line to define a local common
2441 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2442 ( fputs ("\t.reserve ", (FILE)), \
2443 assemble_name ((FILE), (NAME)), \
2444 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2445 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2447 /* A C statement (sans semicolon) to output to the stdio stream
2448 FILE the assembler definition of uninitialized global DECL named
2449 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2450 Try to use asm_output_aligned_bss to implement this macro. */
2452 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2454 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2457 #define IDENT_ASM_OP "\t.ident\t"
2459 /* Output #ident as a .ident. */
2461 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2462 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2464 /* Emit a dtp-relative reference to a TLS variable. */
2467 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2468 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2471 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2472 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
2473 || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&')
2475 /* Print operand X (an rtx) in assembler syntax to file FILE.
2476 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2477 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2479 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2481 /* Print a memory address as an operand to reference that memory location. */
2483 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2484 { register rtx base, index = 0; \
2486 register rtx addr = ADDR; \
2487 if (GET_CODE (addr) == REG) \
2488 fputs (reg_names[REGNO (addr)], FILE); \
2489 else if (GET_CODE (addr) == PLUS) \
2491 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2492 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2493 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2494 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2496 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2497 if (GET_CODE (base) == LO_SUM) \
2499 if (! USE_AS_OFFSETABLE_LO10 \
2501 || TARGET_CM_MEDMID) \
2503 output_operand (XEXP (base, 0), 0); \
2504 fputs ("+%lo(", FILE); \
2505 output_address (XEXP (base, 1)); \
2506 fprintf (FILE, ")+%d", offset); \
2510 fputs (reg_names[REGNO (base)], FILE); \
2512 fprintf (FILE, "%+d", offset); \
2513 else if (GET_CODE (index) == REG) \
2514 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2515 else if (GET_CODE (index) == SYMBOL_REF \
2516 || GET_CODE (index) == CONST) \
2517 fputc ('+', FILE), output_addr_const (FILE, index); \
2521 else if (GET_CODE (addr) == MINUS \
2522 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2524 output_addr_const (FILE, XEXP (addr, 0)); \
2525 fputs ("-(", FILE); \
2526 output_addr_const (FILE, XEXP (addr, 1)); \
2527 fputs ("-.)", FILE); \
2529 else if (GET_CODE (addr) == LO_SUM) \
2531 output_operand (XEXP (addr, 0), 0); \
2532 if (TARGET_CM_MEDMID) \
2533 fputs ("+%l44(", FILE); \
2535 fputs ("+%lo(", FILE); \
2536 output_address (XEXP (addr, 1)); \
2537 fputc (')', FILE); \
2539 else if (flag_pic && GET_CODE (addr) == CONST \
2540 && GET_CODE (XEXP (addr, 0)) == MINUS \
2541 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2542 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2543 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2545 addr = XEXP (addr, 0); \
2546 output_addr_const (FILE, XEXP (addr, 0)); \
2547 /* Group the args of the second CONST in parenthesis. */ \
2548 fputs ("-(", FILE); \
2549 /* Skip past the second CONST--it does nothing for us. */\
2550 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2551 /* Close the parenthesis. */ \
2552 fputc (')', FILE); \
2556 output_addr_const (FILE, addr); \
2561 #define TARGET_TLS 1
2563 #define TARGET_TLS 0
2565 #define TARGET_SUN_TLS TARGET_TLS
2566 #define TARGET_GNU_TLS 0
2568 /* Define the codes that are matched by predicates in sparc.c. */
2570 #define PREDICATE_CODES \
2571 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2572 {"const1_operand", {CONST_INT}}, \
2573 {"fp_zero_operand", {CONST_DOUBLE}}, \
2574 {"fp_register_operand", {SUBREG, REG}}, \
2575 {"intreg_operand", {SUBREG, REG}}, \
2576 {"fcc_reg_operand", {REG}}, \
2577 {"fcc0_reg_operand", {REG}}, \
2578 {"icc_or_fcc_reg_operand", {REG}}, \
2579 {"call_operand", {MEM}}, \
2580 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2581 SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2582 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2583 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2584 {"label_ref_operand", {LABEL_REF}}, \
2585 {"sp64_medium_pic_operand", {CONST}}, \
2586 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2587 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2588 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2589 {"splittable_symbolic_memory_operand", {MEM}}, \
2590 {"splittable_immediate_memory_operand", {MEM}}, \
2591 {"eq_or_neq", {EQ, NE}}, \
2592 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2593 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2594 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2595 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2596 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2597 {"cc_arithop", {AND, IOR, XOR}}, \
2598 {"cc_arithopn", {AND, IOR}}, \
2599 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2600 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2601 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2602 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2603 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2604 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2605 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2606 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2607 {"small_int", {CONST_INT}}, \
2608 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2609 {"uns_small_int", {CONST_INT}}, \
2610 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2611 {"clobbered_register", {REG}}, \
2612 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2613 {"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \
2614 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2615 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2616 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2617 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2618 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2619 {"tle_symbolic_operand", {SYMBOL_REF}},
2621 /* The number of Pmode words for the setjmp buffer. */
2622 #define JMP_BUF_SIZE 12
2624 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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