1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 94, 1995 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Sparc64 support has been added by trying to allow for a day when one
28 compiler can handle both v8 and v9. There are a few cases where this
29 isn't doable, but keep them to a minimum! Two macros are used to help out:
30 TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness.
31 SPARCV9 is defined when compiling for sparc64 only.
32 In places where it is possible to choose between the two at runtime, use
33 TARGET_V9. In places where it is currently not possible to select
34 between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a
35 minimum. No attempt is made to support both v8 and v9 in the v9 compiler.
37 If a combination v8/v9 compiler is too slow, it should always be possible
38 to #define TARGET_V9 as 0 (and potentially other v9-only options), and
41 /* What architecture we're compiling for. This must coincide with the
42 `arch_type' attribute in the .md file. The names were chosen to avoid
43 potential misunderstandings with the various 32 bit flavors (v7, v8, etc.):
44 if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that
45 could be misleading and ARCH_NOTV9 sounds klunky. */
46 enum arch_type { ARCH_32BIT, ARCH_64BIT };
47 extern enum arch_type sparc_arch_type;
49 /* Names to predefine in the preprocessor for this target machine. */
51 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
52 the right varags.h file when bootstrapping. */
55 #define CPP_PREDEFINES \
56 "-Dsparc -Dsun -Dunix -D__sparc_v9__ \
57 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
59 #define CPP_PREDEFINES \
60 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
61 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
64 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
66 /* Provide required defaults for linker -e and -d switches. */
69 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
70 %{assert*} %{shared:-assert pure-text}"
72 /* Special flags to the Sun-4 assembler when using pipe for input. */
75 " %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L}"
77 /* Define macros to distinguish architectures. */
81 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
82 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
86 %{msparclite:-D__sparclite__} \
87 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
88 %{mv8:-D__sparc_v8__} \
89 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
93 /* Prevent error on `-sun4' and `-target sun4' options. */
94 /* This used to translate -dalign to -malign, but that is no good
95 because it can't turn off the usual meaning of making debugging dumps. */
97 #define CC1_SPEC "%{sun4:} %{target:}"
100 #define PTRDIFF_TYPE "long long int"
101 #define SIZE_TYPE "long long unsigned int"
103 #define PTRDIFF_TYPE "int"
104 /* In 2.4 it should work to delete this.
105 #define SIZE_TYPE "int" */
108 /* ??? This should be 32 bits for v9 but what can we do? */
109 #define WCHAR_TYPE "short unsigned int"
110 #define WCHAR_TYPE_SIZE 16
111 #define MAX_WCHAR_TYPE_SIZE 16
113 /* Show we can debug even without a frame pointer. */
114 #define CAN_DEBUG_WITHOUT_FP
116 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
117 code into the rtl. Also, if we are profiling, we cannot eliminate
118 the frame pointer (because the return address will get smashed). */
120 void sparc_override_options ();
122 #define OVERRIDE_OPTIONS \
124 if (profile_flag || profile_block_flag) \
128 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
129 warning ("%s and profiling conflict: disabling %s", \
130 pic_string, pic_string); \
133 flag_omit_frame_pointer = 0; \
135 SUBTARGET_OVERRIDE_OPTIONS; \
136 sparc_override_options (); \
139 /* This is meant to be redefined in the host dependent files. */
140 #define SUBTARGET_OVERRIDE_OPTIONS
142 /* These compiler options take an argument. We ignore -target for now. */
144 #define WORD_SWITCH_TAKES_ARG(STR) \
145 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
146 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
148 /* Print subsidiary information on the compiler version in use. */
150 #define TARGET_VERSION fprintf (stderr, " (sparc)");
152 /* Generate DBX debugging information. */
154 #define DBX_DEBUGGING_INFO
156 /* Run-time compilation parameters selecting different hardware subsets. */
158 extern int target_flags;
160 /* Nonzero if we should generate code to use the fpu. */
162 #define TARGET_FPU (target_flags & MASK_FPU)
164 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
165 use fast return insns, but lose some generality. */
166 #define MASK_EPILOGUE 2
167 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
169 /* Nonzero if we should assume that double pointers might be unaligned.
170 This can happen when linking gcc compiled code with other compilers,
171 because the ABI only guarantees 4 byte alignment. */
172 #define MASK_UNALIGNED_DOUBLES 4
173 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
175 /* ??? Bits 0x18 are currently unused. */
177 /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */
178 #define MASK_SUPERSPARC 0x20
179 #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC)
181 /* Nonzero means that we should generate code for a v8 sparc. */
183 #define TARGET_V8 (target_flags & MASK_V8)
185 /* Nonzero means that we should generate code for a sparclite.
186 This enables the sparclite specific instructions, but does not affect
187 whether FPU instructions are emitted. */
188 #define MASK_SPARCLITE 0x80
189 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
191 /* Nonzero means that we should generate code using a flat register window
192 model, i.e. no save/restore instructions are generated, in the most
193 efficient manner. This code is not compatible with normal sparc code. */
194 /* This is not a user selectable option yet, because it requires changes
195 that are not yet switchable via command line arguments. */
196 /* ??? This flag is deprecated and may disappear at some point. */
197 #define MASK_FRW 0x100
198 #define TARGET_FRW (target_flags & MASK_FRW)
200 /* Nonzero means that we should generate code using a flat register window
201 model, i.e. no save/restore instructions are generated, but which is
202 compatible with normal sparc code. This is the same as above, except
203 that the frame pointer is %i7 instead of %fp. */
204 /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will
205 go away, but until that time only use this one when necessary.
207 #define MASK_FLAT 0x200
208 #define TARGET_FLAT (target_flags & MASK_FLAT)
210 /* Nonzero means use the registers that the Sparc ABI reserves for
211 application software. This is the default for v8, but not v9. */
212 #define MASK_APP_REGS 0x400
213 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
215 /* Option to select how quad word floating point is implemented.
216 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
217 Otherwise, we use the SPARC ABI quad library functions. */
218 #define MASK_HARD_QUAD 0x800
219 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
221 /* Nonzero if we're compiling for 64 bit sparc. */
222 #define MASK_V9 0x1000
223 #define TARGET_V9 (target_flags & MASK_V9)
225 /* Nonzero if ints are 64 bits.
226 This automatically implies longs are 64 bits too.
227 This option is for v9 only. */
228 #define MASK_INT64 0x2000
229 #define TARGET_INT64 (target_flags & MASK_INT64)
231 /* Nonzero if longs are 64 bits.
232 This option is for v9 only. */
233 #define MASK_LONG64 0x4000
234 #define TARGET_LONG64 (target_flags & MASK_LONG64)
236 /* Nonzero if pointers are 64 bits.
237 This is not a user selectable option, though it may be one day -
238 so it is used to determine pointer size instead of an architecture flag. */
239 #define MASK_PTR64 0x8000
240 #define TARGET_PTR64 (target_flags & MASK_PTR64)
242 /* Nonzero if we are generating code to be tested in a 32 bit environment.
243 Hence, we assume the upper 32 bits of symbolic addresses are zero, and
244 avoid generating %uhi and %ulo terms.
245 Pointers are still 64 bits though! This option is for v9 only. */
246 /* ??? This option is deprecated. Try to use -mmedlow. */
247 #define MASK_ENV32 0x10000
248 #define TARGET_ENV32 (target_flags & MASK_ENV32)
251 Two memory models are supported:
252 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0
253 (pointers still 64 bits)
254 TARGET_MEDANY: 32 bit address space, data segment loaded anywhere
256 TARGET_FULLANY: not supported yet.
257 These options are for v9 only. All mask values are nonzero so the v8
258 compiler can assume this stuff won't interfere. */
259 #define MASK_MEDLOW 0x20000
260 #define MASK_MEDANY 0x40000
261 #define MASK_FULLANY 0x60000
262 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
263 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
264 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
265 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
267 /* ??? There are hardcoded references to this reg in the .md file. */
268 #define MEDANY_BASE_REG "%g4"
270 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
271 adding 2047 to %sp. This option is for v9 only and is the default. */
272 #define MASK_STACK_BIAS 0x80000
273 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
275 /* Macro to define tables used to set the flags.
276 This is a list in braces of pairs in braces,
277 each pair being { "NAME", VALUE }
278 where VALUE is the bits to set or minus the bits to clear.
279 An empty string NAME is used to identify the default VALUE. */
281 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
282 The Fujitsu MB86934 is the recent sparclite chip, with an fpu.
283 We use -mf930 and -mf934 options to choose which.
284 ??? These should perhaps be -mcpu= options. */
286 #define TARGET_SWITCHES \
287 { {"fpu", MASK_FPU}, \
288 {"no-fpu", -MASK_FPU}, \
289 {"hard-float", MASK_FPU}, \
290 {"soft-float", -MASK_FPU}, \
291 {"epilogue", MASK_EPILOGUE}, \
292 {"no-epilogue", -MASK_EPILOGUE}, \
293 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
294 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
295 {"supersparc", MASK_SUPERSPARC+MASK_V8}, \
296 {"cypress", -MASK_SUPERSPARC-MASK_V8}, \
298 {"no-v8", -MASK_V8}, \
299 {"sparclite", MASK_SPARCLITE}, \
300 {"no-sparclite", -MASK_SPARCLITE}, \
301 {"f930", MASK_SPARCLITE}, \
302 {"f930", -MASK_FPU}, \
303 {"f934", MASK_SPARCLITE}, \
304 {"flat", MASK_FRW+MASK_FLAT}, \
305 {"no-flat", -(MASK_FRW+MASK_FLAT)}, \
306 {"app-regs", MASK_APP_REGS}, \
307 {"no-app-regs", -MASK_APP_REGS}, \
308 {"hard-quad-float", MASK_HARD_QUAD}, \
309 {"soft-quad-float", -MASK_HARD_QUAD}, \
312 { "", TARGET_DEFAULT}}
314 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
316 /* This is meant to be redefined in the host dependent files */
317 #define SUBTARGET_SWITCHES
319 /* ??? Until we support a combination v8/v9 compiler, the v9 specific options
320 are only defined for the v9 compiler. */
322 #define V9_SWITCHES \
323 /* {"v9", MASK_V9}, */ \
324 {"int64", MASK_INT64+MASK_LONG64}, \
325 {"int32", -MASK_INT64}, \
326 {"int32", MASK_LONG64}, \
327 {"long64", -MASK_INT64}, \
328 {"long64", MASK_LONG64}, \
329 {"long32", -(MASK_INT64+MASK_LONG64)}, \
330 /* {"ptr64", MASK_PTR64}, */ \
331 /* {"ptr32", -MASK_PTR64}, */ \
332 {"stack-bias", MASK_STACK_BIAS}, \
333 {"no-stack-bias", -MASK_STACK_BIAS}, \
334 {"medlow", -MASK_CODE_MODEL}, \
335 {"medlow", MASK_MEDLOW}, \
336 {"medany", -MASK_CODE_MODEL}, \
337 {"medany", MASK_MEDANY},
342 /* target machine storage layout */
344 /* Define for cross-compilation to a sparc target with no TFmode from a host
345 with a different float format (e.g. VAX). */
346 #define REAL_ARITHMETIC
348 /* Define this if most significant bit is lowest numbered
349 in instructions that operate on numbered bit-fields. */
350 #define BITS_BIG_ENDIAN 1
352 /* Define this if most significant byte of a word is the lowest numbered. */
353 /* This is true on the SPARC. */
354 #define BYTES_BIG_ENDIAN 1
356 /* Define this if most significant word of a multiword number is the lowest
358 /* Doubles are stored in memory with the high order word first. This
359 matters when cross-compiling. */
360 #define WORDS_BIG_ENDIAN 1
362 /* number of bits in an addressable storage unit */
363 #define BITS_PER_UNIT 8
365 /* Width in bits of a "word", which is the contents of a machine register.
366 Note that this is not necessarily the width of data type `int';
367 if using 16-bit ints on a 68000, this would still be 32.
368 But on a machine with 16-bit registers, this would be 16. */
369 #define BITS_PER_WORD (TARGET_V9 ? 64 : 32)
370 #define MAX_BITS_PER_WORD 64
372 /* Width of a word, in units (bytes). */
373 #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4)
374 #define MIN_UNITS_PER_WORD 4
376 /* Now define the sizes of the C data types. */
378 #define SHORT_TYPE_SIZE 16
379 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
380 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
381 #define LONG_LONG_TYPE_SIZE 64
382 #define FLOAT_TYPE_SIZE 32
383 #define DOUBLE_TYPE_SIZE 64
385 #define MAX_INT_TYPE_SIZE 64
386 #define MAX_LONG_TYPE_SIZE 64
389 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
390 Instead, it is enabled in sol2.h, because it does work under Solaris. */
391 /* Define for support of TFmode long double and REAL_ARITHMETIC.
392 Sparc ABI says that long double is 4 words. */
393 #define LONG_DOUBLE_TYPE_SIZE 128
396 /* Width in bits of a pointer.
397 See also the macro `Pmode' defined below. */
398 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
400 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
401 #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32)
403 /* Boundary (in *bits*) on which stack pointer should be aligned. */
404 #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64)
406 /* ALIGN FRAMES on double word boundaries */
408 #define SPARC_STACK_ALIGN(LOC) \
409 (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
411 /* Allocation boundary (in *bits*) for the code of a function. */
412 #define FUNCTION_BOUNDARY 32
414 /* Alignment of field after `int : 0' in a structure. */
415 /* ??? Should this be based on TARGET_INT64? */
416 #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32)
418 /* Every structure's size must be a multiple of this. */
419 #define STRUCTURE_SIZE_BOUNDARY 8
421 /* A bitfield declared as `int' forces `int' alignment for the struct. */
422 #define PCC_BITFIELD_TYPE_MATTERS 1
424 /* No data type wants to be aligned rounder than this. */
425 #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64)
427 /* The best alignment to use in cases where we have a choice. */
428 #define FASTEST_ALIGNMENT 64
430 /* Make strings word-aligned so strcpy from constants will be faster. */
431 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
432 ((TREE_CODE (EXP) == STRING_CST \
433 && (ALIGN) < FASTEST_ALIGNMENT) \
434 ? FASTEST_ALIGNMENT : (ALIGN))
436 /* Make arrays of chars word-aligned for the same reasons. */
437 #define DATA_ALIGNMENT(TYPE, ALIGN) \
438 (TREE_CODE (TYPE) == ARRAY_TYPE \
439 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
440 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
442 /* Set this nonzero if move instructions will actually fail to work
443 when given unaligned data. */
444 #define STRICT_ALIGNMENT 1
446 /* Things that must be doubleword aligned cannot go in the text section,
447 because the linker fails to align the text section enough!
448 Put them in the data section. This macro is only used in this file. */
449 #define MAX_TEXT_ALIGN 32
451 /* This forces all variables and constants to the data section when PIC.
452 This is because the SunOS 4 shared library scheme thinks everything in
453 text is a function, and patches the address to point to a loader stub. */
454 /* This is defined to zero for every system which doesn't use the a.out object
456 #ifndef SUNOS4_SHARED_LIBRARIES
457 #define SUNOS4_SHARED_LIBRARIES 0
460 /* This is defined differently for v9 in a cover file. */
461 #define SELECT_SECTION(T,RELOC) \
463 if (TREE_CODE (T) == VAR_DECL) \
465 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
466 && DECL_INITIAL (T) \
467 && (DECL_INITIAL (T) == error_mark_node \
468 || TREE_CONSTANT (DECL_INITIAL (T))) \
469 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
470 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
475 else if (TREE_CODE (T) == CONSTRUCTOR) \
477 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
480 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
482 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
483 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
484 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
491 /* Use text section for a constant
492 unless we need more alignment than that offers. */
493 /* This is defined differently for v9 in a cover file. */
494 #define SELECT_RTX_SECTION(MODE, X) \
496 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
497 && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \
503 /* Standard register usage. */
505 /* Number of actual hardware registers.
506 The hardware registers are assigned numbers for the compiler
507 from 0 to just below FIRST_PSEUDO_REGISTER.
508 All registers that the compiler knows about must be given numbers,
509 even those that are not normally considered general registers.
511 SPARC has 32 integer registers and 32 floating point registers.
512 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
513 accessible. We still account for them to simplify register computations
514 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
516 Register 0 is used as the integer condition code register. */
519 #define FIRST_PSEUDO_REGISTER 100
521 #define FIRST_PSEUDO_REGISTER 64
524 /* 1 for registers that have pervasive standard uses
525 and are not available for the register allocator.
526 g0 is used for the condition code and not to represent %g0, which is
527 hardwired to 0, so reg 0 is *not* fixed.
529 g1 is free to use as temporary.
530 g2-g4 are reserved for applications. Gcc normally uses them as
531 temporaries, but this can be disabled via the -mno-app-regs option.
532 g5 through g7 are reserved for the operating system.
534 g1 and g5 are free to use as temporaries.
535 g2-g4 are reserved for applications (the compiler will not normally use
536 them, but they can be used as temporaries with -mapp-regs).
537 g6-g7 are reserved for the operating system.
538 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
539 currently be a fixed register until this pattern is rewritten.
540 Register 1 is also used when restoring call-preserved registers in large
544 #define FIXED_REGISTERS \
545 {0, 1, 1, 1, 1, 0, 1, 1, \
546 0, 0, 0, 0, 0, 0, 1, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 1, 1, \
550 0, 0, 0, 0, 0, 0, 0, 0, \
551 0, 0, 0, 0, 0, 0, 0, 0, \
552 0, 0, 0, 0, 0, 0, 0, 0, \
553 0, 0, 0, 0, 0, 0, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, \
558 0, 0, 0, 0, 0, 0, 0, 0, \
562 #define FIXED_REGISTERS \
563 {0, 0, 0, 0, 0, 1, 1, 1, \
564 0, 0, 0, 0, 0, 0, 1, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 1, 1, \
568 0, 0, 0, 0, 0, 0, 0, 0, \
569 0, 0, 0, 0, 0, 0, 0, 0, \
570 0, 0, 0, 0, 0, 0, 0, 0, \
571 0, 0, 0, 0, 0, 0, 0, 0}
574 /* 1 for registers not available across function calls.
575 These must include the FIXED_REGISTERS and also any
576 registers that can be used without being saved.
577 The latter must include the registers where values are returned
578 and the register where structure-value addresses are passed.
579 Aside from that, you can include as many other registers as you like. */
582 #define CALL_USED_REGISTERS \
583 {1, 1, 1, 1, 1, 1, 1, 1, \
584 1, 1, 1, 1, 1, 1, 1, 1, \
585 0, 0, 0, 0, 0, 0, 0, 0, \
586 0, 0, 0, 0, 0, 0, 1, 1, \
588 1, 1, 1, 1, 1, 1, 1, 1, \
589 1, 1, 1, 1, 1, 1, 1, 1, \
590 0, 0, 0, 0, 0, 0, 0, 0, \
591 0, 0, 0, 0, 0, 0, 0, 0, \
593 0, 0, 0, 0, 0, 0, 0, 0, \
594 0, 0, 0, 0, 0, 0, 0, 0, \
595 1, 1, 1, 1, 1, 1, 1, 1, \
596 1, 1, 1, 1, 1, 1, 1, 1, \
600 #define CALL_USED_REGISTERS \
601 {1, 1, 1, 1, 1, 1, 1, 1, \
602 1, 1, 1, 1, 1, 1, 1, 1, \
603 0, 0, 0, 0, 0, 0, 0, 0, \
604 0, 0, 0, 0, 0, 0, 1, 1, \
606 1, 1, 1, 1, 1, 1, 1, 1, \
607 1, 1, 1, 1, 1, 1, 1, 1, \
608 1, 1, 1, 1, 1, 1, 1, 1, \
609 1, 1, 1, 1, 1, 1, 1, 1}
612 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
613 be allocated. On v9, also make the fp cc regs fixed. */
615 #define CONDITIONAL_REGISTER_USAGE \
621 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \
622 fixed_regs[regno] = 1; \
624 if (! TARGET_APP_REGS) \
634 fixed_regs[4] = TARGET_MEDANY != 0; \
638 /* Let the compiler believe the frame pointer is still \
639 %fp, but output it as %i7. */ \
640 fixed_regs[31] = 1; \
641 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
642 /* ??? This is a hack to disable leaf functions. */ \
643 global_regs[7] = 1; \
645 if (profile_block_flag) \
647 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
655 /* Return number of consecutive hard regs needed starting at reg REGNO
656 to hold something of mode MODE.
657 This is ordinarily the length in words of a value of mode MODE
658 but can be less for certain modes in special long registers.
660 On SPARC, ordinary registers hold 32 bits worth;
661 this means both integer and floating point registers.
662 On v9, integer regs hold 64 bits worth; floating point regs hold
663 32 bits worth (this includes the new fp regs as even the odd ones are
664 included in the hard register count). */
666 #define HARD_REGNO_NREGS(REGNO, MODE) \
669 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
670 : (GET_MODE_SIZE (MODE) + 3) / 4) \
671 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
673 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
674 See sparc.c for how we initialize this. */
675 extern int *hard_regno_mode_classes;
676 extern int sparc_mode_class[];
677 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
678 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
680 /* Value is 1 if it is a good idea to tie two pseudo registers
681 when one has mode MODE1 and one has mode MODE2.
682 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
683 for any hard reg, then this must be 0 for correct output.
685 For V9: SFmode can't be combined with other float modes, because they can't
686 be allocated to the %d registers. Also, DFmode won't fit in odd %f
687 registers, but SFmode will. */
688 #define MODES_TIEABLE_P(MODE1, MODE2) \
689 ((MODE1) == (MODE2) \
690 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
692 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
693 || (MODE1 != SFmode && MODE2 != SFmode)))))
695 /* Specify the registers used for certain standard purposes.
696 The values of these macros are register numbers. */
698 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
699 /* #define PC_REGNUM */
701 /* Register to use for pushing function arguments. */
702 #define STACK_POINTER_REGNUM 14
704 /* Actual top-of-stack address is 92/136 greater than the contents of the
705 stack pointer register for !v9/v9. That is:
706 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
707 address, and 24 bytes for the 6 register parameters.
708 - v9: 128 bytes for the in and local registers + 8 bytes reserved. */
709 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
711 /* The stack bias (amount by which the hardware register is offset by). */
712 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
714 /* Base register for access to local variables of the function. */
715 #define FRAME_POINTER_REGNUM 30
718 /* Register that is used for the return address. */
719 #define RETURN_ADDR_REGNUM 15
722 /* Value should be nonzero if functions must have frame pointers.
723 Zero means the frame pointer need not be set up (and parms
724 may be accessed via the stack pointer) in functions that seem suitable.
725 This is computed in `reload', in reload1.c.
726 Used in flow.c, global.c, and reload1.c.
728 Being a non-leaf function does not mean a frame pointer is needed in the
729 flat window model. However, the debugger won't be able to backtrace through
731 #define FRAME_POINTER_REQUIRED \
732 (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs \
733 || !leaf_function_p ()) \
734 : ! (leaf_function_p () && only_leaf_regs_used ()))
736 /* C statement to store the difference between the frame pointer
737 and the stack pointer values immediately after the function prologue.
739 Note, we always pretend that this is a leaf function because if
740 it's not, there's no point in trying to eliminate the
741 frame pointer. If it is a leaf function, we guessed right! */
742 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
743 ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \
744 : compute_frame_size (get_frame_size (), 1)))
746 /* Base register for access to arguments of the function. */
747 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
749 /* Register in which static-chain is passed to a function. This must
750 not be a register used by the prologue. */
751 #define STATIC_CHAIN_REGNUM (TARGET_V9 ? 5 : 2)
753 /* Register which holds offset table for position-independent
756 #define PIC_OFFSET_TABLE_REGNUM 23
758 #define INITIALIZE_PIC initialize_pic ()
759 #define FINALIZE_PIC finalize_pic ()
761 /* Sparc ABI says that quad-precision floats and all structures are returned
763 For v9, all aggregates are returned in memory. */
764 #define RETURN_IN_MEMORY(TYPE) \
765 (TYPE_MODE (TYPE) == BLKmode \
766 || (! TARGET_V9 && (TYPE_MODE (TYPE) == TFmode \
767 || TYPE_MODE (TYPE) == TCmode)))
769 /* Functions which return large structures get the address
770 to place the wanted value at offset 64 from the frame.
771 Must reserve 64 bytes for the in and local registers.
772 v9: Functions which return large structures get the address to place the
773 wanted value from an invisible first argument. */
774 /* Used only in other #defines in this file. */
775 #define STRUCT_VALUE_OFFSET 64
777 #define STRUCT_VALUE \
780 : gen_rtx (MEM, Pmode, \
781 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
782 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
783 #define STRUCT_VALUE_INCOMING \
786 : gen_rtx (MEM, Pmode, \
787 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
788 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
790 /* Define the classes of registers for register constraints in the
791 machine description. Also define ranges of constants.
793 One of the classes must always be named ALL_REGS and include all hard regs.
794 If there is more than one class, another class must be named NO_REGS
795 and contain no registers.
797 The name GENERAL_REGS must be the name of a class (or an alias for
798 another name such as ALL_REGS). This is the class of registers
799 that is allowed by "g" or "r" in a register constraint.
800 Also, registers outside this class are allocated only when
801 instructions express preferences for them.
803 The classes must be numbered in nondecreasing order; that is,
804 a larger-numbered class must never be contained completely
805 in a smaller-numbered class.
807 For any two classes, it is very desirable that there be another
808 class that represents their union. */
810 /* The SPARC has two kinds of registers, general and floating point.
812 For v9 we must distinguish between the upper and lower floating point
813 registers because the upper ones can't hold SFmode values.
814 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
815 satisfying a group need for a class will also satisfy a single need for
816 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
819 It is important that one class contains all the general and all the standard
820 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
821 because reg_class_record() will bias the selection in favor of fp regs,
822 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
823 because FP_REGS > GENERAL_REGS.
825 It is also important that one class contain all the general and all the
826 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
827 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
828 allocate_reload_reg() to bypass it causing an abort because the compiler
829 thinks it doesn't have a spill reg when in fact it does.
831 v9 also has 4 floating point condition code registers. Since we don't
832 have a class that is the union of FPCC_REGS with either of the others,
833 it is important that it appear first. Otherwise the compiler will die
834 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
838 enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
839 GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
840 ALL_REGS, LIM_REG_CLASSES };
842 enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
845 #define N_REG_CLASSES (int) LIM_REG_CLASSES
847 /* Give names of register classes as strings for dump file. */
850 #define REG_CLASS_NAMES \
851 { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \
852 "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" }
854 #define REG_CLASS_NAMES \
855 { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
858 /* Define which registers fit in which classes.
859 This is an initializer for a vector of HARD_REG_SET
860 of length N_REG_CLASSES. */
863 #define REG_CLASS_CONTENTS \
864 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \
865 {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \
868 #if 0 && defined (__GNUC__)
869 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
871 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
875 /* The same information, inverted:
876 Return the class number of the smallest class containing
877 reg number REGNO. This could be a conditional expression
878 or could index an array. */
881 #define REGNO_REG_CLASS(REGNO) \
882 ((REGNO) == 0 ? NO_REGS \
883 : (REGNO) < 32 ? GENERAL_REGS \
884 : (REGNO) < 64 ? FP_REGS \
885 : (REGNO) < 96 ? EXTRA_FP_REGS \
888 #define REGNO_REG_CLASS(REGNO) \
889 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
892 /* This is the order in which to allocate registers normally.
894 We put %f0/%f1 last among the float registers, so as to make it more
895 likely that a pseudo-register which dies in the float return register
896 will get allocated to the float return register, thus saving a move
897 instruction at the end of the function.
899 On v9, the float registers are ordered a little "funny" because some
900 of them (%f16-%f47) are call-preserved. */
902 #define REG_ALLOC_ORDER \
903 { 8, 9, 10, 11, 12, 13, \
904 15, 16, 17, 18, 19, 20, 21, 22, \
905 23, 24, 25, 26, 27, 28, 29, 31, \
906 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
907 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
908 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
909 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
910 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
911 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
912 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
913 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
914 32, 33, /* %f0,%f1 */ \
915 96, 97, 98, 99, /* %fcc0-3 */ \
916 1, 5, 2, 3, 4, 6, 7, 0, 14, 30}
918 #define REG_ALLOC_ORDER \
919 { 8, 9, 10, 11, 12, 13, 2, 3, \
920 15, 16, 17, 18, 19, 20, 21, 22, \
921 23, 24, 25, 26, 27, 28, 29, 31, \
922 34, 35, 36, 37, 38, 39, \
923 40, 41, 42, 43, 44, 45, 46, 47, \
924 48, 49, 50, 51, 52, 53, 54, 55, \
925 56, 57, 58, 59, 60, 61, 62, 63, \
927 1, 4, 5, 6, 7, 0, 14, 30}
930 /* This is the order in which to allocate registers for
931 leaf functions. If all registers can fit in the "i" registers,
932 then we have the possibility of having a leaf function.
933 v9: The floating point registers are ordered a little "funny" because some
934 of them (%f16-%f47) are call-preserved. */
936 #define REG_LEAF_ALLOC_ORDER \
937 { 24, 25, 26, 27, 28, 29, \
938 15, 8, 9, 10, 11, 12, 13, \
939 16, 17, 18, 19, 20, 21, 22, 23, \
940 34, 35, 36, 37, 38, 39, \
941 40, 41, 42, 43, 44, 45, 46, 47, \
942 80, 81, 82, 83, 84, 85, 86, 87, \
943 88, 89, 90, 91, 92, 93, 94, 95, \
944 48, 49, 50, 51, 52, 53, 54, 55, \
945 56, 57, 58, 59, 60, 61, 62, 63, \
946 64, 65, 66, 67, 68, 69, 70, 71, \
947 72, 73, 74, 75, 76, 77, 78, 79, \
950 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31}
952 #define REG_LEAF_ALLOC_ORDER \
953 { 2, 3, 24, 25, 26, 27, 28, 29, \
954 15, 8, 9, 10, 11, 12, 13, \
955 16, 17, 18, 19, 20, 21, 22, 23, \
956 34, 35, 36, 37, 38, 39, \
957 40, 41, 42, 43, 44, 45, 46, 47, \
958 48, 49, 50, 51, 52, 53, 54, 55, \
959 56, 57, 58, 59, 60, 61, 62, 63, \
961 1, 4, 5, 6, 7, 0, 14, 30, 31}
964 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
966 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
967 -mflat is used. Function only_leaf_regs_used will return 0 if a global
968 register is used and is not permitted in a leaf function. We make %g7
969 a global reg if -mflat and voila. Since %g7 is a system register and is
970 fixed it won't be used by gcc anyway. */
972 #define LEAF_REGISTERS \
973 { 1, 1, 1, 1, 1, 1, 1, 0, \
974 0, 0, 0, 0, 0, 0, 1, 0, \
975 0, 0, 0, 0, 0, 0, 0, 0, \
976 1, 1, 1, 1, 1, 1, 0, 1, \
977 1, 1, 1, 1, 1, 1, 1, 1, \
978 1, 1, 1, 1, 1, 1, 1, 1, \
979 1, 1, 1, 1, 1, 1, 1, 1, \
980 1, 1, 1, 1, 1, 1, 1, 1, \
981 1, 1, 1, 1, 1, 1, 1, 1, \
982 1, 1, 1, 1, 1, 1, 1, 1, \
983 1, 1, 1, 1, 1, 1, 1, 1, \
984 1, 1, 1, 1, 1, 1, 1, 1, \
987 #define LEAF_REGISTERS \
988 { 1, 1, 1, 1, 1, 1, 1, 0, \
989 0, 0, 0, 0, 0, 0, 1, 0, \
990 0, 0, 0, 0, 0, 0, 0, 0, \
991 1, 1, 1, 1, 1, 1, 0, 1, \
992 1, 1, 1, 1, 1, 1, 1, 1, \
993 1, 1, 1, 1, 1, 1, 1, 1, \
994 1, 1, 1, 1, 1, 1, 1, 1, \
995 1, 1, 1, 1, 1, 1, 1, 1}
998 extern char leaf_reg_remap[];
999 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1001 /* The class value for index registers, and the one for base regs. */
1002 #define INDEX_REG_CLASS GENERAL_REGS
1003 #define BASE_REG_CLASS GENERAL_REGS
1005 /* Local macro to handle the two v9 classes of FP regs. */
1007 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1009 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS)
1012 /* Get reg_class from a letter such as appears in the machine description. */
1015 #define REG_CLASS_FROM_LETTER(C) \
1016 ((C) == 'f' ? FP_REGS \
1017 : (C) == 'e' ? EXTRA_FP_REGS \
1018 : (C) == 'c' ? FPCC_REGS \
1021 /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for
1023 #define REG_CLASS_FROM_LETTER(C) \
1024 ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS)
1027 /* The letters I, J, K, L and M in a register constraint string
1028 can be used to stand for particular ranges of immediate operands.
1029 This macro defines what the ranges are.
1030 C is the letter, and VALUE is a constant value.
1031 Return 1 if VALUE is in the range specified by C.
1033 For SPARC, `I' is used for the range of constants an insn
1034 can actually contain.
1035 `J' is used for the range which is just zero (since that is R0).
1036 `K' is used for constants which can be loaded with a single sethi insn. */
1038 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
1040 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1041 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
1042 : (C) == 'J' ? (VALUE) == 0 \
1043 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
1046 /* Similar, but for floating constants, and defining letters G and H.
1047 Here VALUE is the CONST_DOUBLE rtx itself. */
1049 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1050 ((C) == 'G' ? fp_zero_operand (VALUE) \
1051 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1054 /* Given an rtx X being reloaded into a reg required to be
1055 in class CLASS, return the class of reg to actually use.
1056 In general this is just CLASS; but on some machines
1057 in some cases it is preferable to use a more restrictive class. */
1058 /* We can't load constants into FP registers. We can't load any FP constant
1059 if an 'E' constraint fails to match it. */
1060 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1062 && (FP_REG_CLASS_P (CLASS) \
1063 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1064 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1065 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1066 ? NO_REGS : (CLASS))
1068 /* Return the register class of a scratch register needed to load IN into
1069 a register of class CLASS in MODE.
1071 On the SPARC, when PIC, we need a temporary when loading some addresses
1074 Also, we need a temporary when loading/storing a HImode/QImode value
1075 between memory and the FPU registers. This can happen when combine puts
1076 a paradoxical subreg in a float/fix conversion insn. */
1078 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1079 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1080 && (GET_CODE (IN) == MEM \
1081 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1082 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1084 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1085 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1086 && (GET_CODE (IN) == MEM \
1087 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1088 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1090 /* On SPARC it is not possible to directly move data between
1091 GENERAL_REGS and FP_REGS. */
1092 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1093 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1095 /* Return the stack location to use for secondary memory needed reloads.
1096 We want to use the reserved location just below the frame pointer.
1097 However, we must ensure that there is a frame, so use assign_stack_local
1098 if the frame size is zero. */
1099 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1100 (get_frame_size () == 0 \
1101 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1102 : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1103 GEN_INT (STARTING_FRAME_OFFSET))))
1105 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1106 because the movsi and movsf patterns don't handle r/f moves.
1107 For v8 we copy the default definition. */
1108 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1110 ? (GET_MODE_BITSIZE (MODE) < 32 \
1111 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1113 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1114 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1117 /* Return the maximum number of consecutive registers
1118 needed to represent mode MODE in a register of class CLASS. */
1119 /* On SPARC, this is the size of MODE in words. */
1120 #define CLASS_MAX_NREGS(CLASS, MODE) \
1121 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1122 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1124 /* Stack layout; function entry, exit and calling. */
1126 /* Define the number of register that can hold parameters.
1127 These two macros are used only in other macro definitions below.
1128 MODE is the mode of the argument.
1129 !v9: All args are passed in %o0-%o5.
1130 v9: Non-float args are passed in %o0-5 and float args are passed in
1132 #define NPARM_REGS(MODE) \
1133 (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6)
1135 /* Define this if pushing a word on the stack
1136 makes the stack pointer a smaller address. */
1137 #define STACK_GROWS_DOWNWARD
1139 /* Define this if the nominal address of the stack frame
1140 is at the high-address end of the local variables;
1141 that is, each additional local variable allocated
1142 goes at a more negative offset in the frame. */
1143 #define FRAME_GROWS_DOWNWARD
1145 /* Offset within stack frame to start allocating local variables at.
1146 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1147 first local allocated. Otherwise, it is the offset to the BEGINNING
1148 of the first local allocated. */
1149 /* This allows space for one TFmode floating point value. */
1150 #define STARTING_FRAME_OFFSET \
1151 (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \
1152 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1154 /* If we generate an insn to push BYTES bytes,
1155 this says how many the stack pointer really advances by.
1156 On SPARC, don't define this because there are no push insns. */
1157 /* #define PUSH_ROUNDING(BYTES) */
1159 /* Offset of first parameter from the argument pointer register value.
1160 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1161 even if this function isn't going to use it.
1162 v9: This is 128 for the ins and locals, plus a reserved space of 8. */
1163 #define FIRST_PARM_OFFSET(FNDECL) \
1164 (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \
1165 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1167 /* When a parameter is passed in a register, stack space is still
1168 allocated for it. */
1170 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD)
1173 /* Keep the stack pointer constant throughout the function.
1174 This is both an optimization and a necessity: longjmp
1175 doesn't behave itself when the stack pointer moves within
1177 #define ACCUMULATE_OUTGOING_ARGS
1179 /* Value is the number of bytes of arguments automatically
1180 popped when returning from a subroutine call.
1181 FUNDECL is the declaration node of the function (as a tree),
1182 FUNTYPE is the data type of the function (as a tree),
1183 or for a library call it is an identifier node for the subroutine name.
1184 SIZE is the number of bytes of arguments passed on the stack. */
1186 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1188 /* Some subroutine macros specific to this machine.
1189 When !TARGET_FPU, put float return values in the general registers,
1190 since we don't have any fp registers. */
1191 #define BASE_RETURN_VALUE_REG(MODE) \
1192 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1193 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1194 #define BASE_OUTGOING_VALUE_REG(MODE) \
1195 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1196 : TARGET_FRW ? 8 : 24) \
1197 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1198 : (TARGET_FRW ? 8 : 24)))
1199 #define BASE_PASSING_ARG_REG(MODE) \
1200 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1202 #define BASE_INCOMING_ARG_REG(MODE) \
1203 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1204 : TARGET_FRW ? 8 : 24) \
1205 : (TARGET_FRW ? 8 : 24))
1207 /* Define this macro if the target machine has "register windows". This
1208 C expression returns the register number as seen by the called function
1209 corresponding to register number OUT as seen by the calling function.
1210 Return OUT if register number OUT is not an outbound register. */
1212 #define INCOMING_REGNO(OUT) \
1213 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1215 /* Define this macro if the target machine has "register windows". This
1216 C expression returns the register number as seen by the calling function
1217 corresponding to register number IN as seen by the called function.
1218 Return IN if register number IN is not an inbound register. */
1220 #define OUTGOING_REGNO(IN) \
1221 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1223 /* Define how to find the value returned by a function.
1224 VALTYPE is the data type of the value (as a tree).
1225 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1226 otherwise, FUNC is 0. */
1228 /* On SPARC the value is found in the first "output" register. */
1230 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1231 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1233 /* But the called function leaves it in the first "input" register. */
1235 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1236 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1238 /* Define how to find the value returned by a library function
1239 assuming the value has mode MODE. */
1241 #define LIBCALL_VALUE(MODE) \
1242 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1244 /* 1 if N is a possible register number for a function value
1245 as seen by the caller.
1246 On SPARC, the first "output" reg is used for integer values,
1247 and the first floating point register is used for floating point values. */
1249 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1251 /* Define the size of space to allocate for the return value of an
1254 #define APPLY_RESULT_SIZE 16
1256 /* 1 if N is a possible register number for function argument passing.
1257 On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */
1259 #define FUNCTION_ARG_REGNO_P(N) \
1260 (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \
1261 : ((N) < 14 && (N) > 7))
1263 /* Define a data type for recording info about an argument list
1264 during the scan of that argument list. This data type should
1265 hold all necessary information about the function itself
1266 and about the args processed so far, enough to enable macros
1267 such as FUNCTION_ARG to determine where the next arg should go.
1269 On SPARC (!v9), this is a single integer, which is a number of words
1270 of arguments scanned so far (including the invisible argument,
1271 if any, which holds the structure-value-address).
1272 Thus 7 or more means all following args should go on the stack.
1274 For v9, we record how many of each type has been passed. Different
1275 types get passed differently.
1277 - Float args are passed in %f0-15, after which they go to the stack
1278 where floats and doubles are passed 8 byte aligned and long doubles
1279 are passed 16 byte aligned.
1280 - All aggregates are passed by reference. The callee copies
1281 the structure if necessary, except if stdarg/varargs and the struct
1282 matches the ellipse in which case the caller makes a copy.
1283 - Any non-float argument might be split between memory and reg %o5.
1284 ??? I don't think this can ever happen now that structs are no
1285 longer passed in regs.
1287 For v9 return values:
1289 - For all aggregates, the caller allocates space for the return value,
1290 and passes the pointer as an implicit first argument, which is
1291 allocated like all other arguments.
1292 - The unimp instruction stuff for structure returns is gone. */
1295 enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 };
1297 int arg_count[2]; /* must be int! (for __builtin_args_info) */
1299 #define CUMULATIVE_ARGS struct sparc_args
1301 /* Return index into CUMULATIVE_ARGS. */
1303 #define GET_SPARC_ARG_CLASS(MODE) \
1304 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT)
1306 /* Round a register number up to a proper boundary for an arg of mode MODE.
1307 This macro is only used in this file.
1309 The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */
1311 #define ROUND_REG(CUM, MODE) \
1312 (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1313 ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1314 : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1315 + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \
1316 & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4))
1318 #define ROUND_ADVANCE(SIZE) \
1319 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1321 #else /* ! SPARCV9 */
1322 #define CUMULATIVE_ARGS int
1324 #define ROUND_REG(CUM, MODE) (CUM)
1326 #define ROUND_ADVANCE(SIZE) \
1327 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1328 #endif /* ! SPARCV9 */
1330 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1331 for a call to a function whose data type is FNTYPE.
1332 For a library call, FNTYPE is 0.
1334 On SPARC, the offset always starts at 0: the first parm reg is always
1338 extern int sparc_arg_count,sparc_n_named_args;
1339 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
1341 (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \
1342 (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \
1343 sparc_arg_count = 0; \
1344 sparc_n_named_args = \
1345 ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \
1346 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \
1347 + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \
1348 || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \
1349 /* Can't tell, treat 'em all as named. */ \
1353 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
1356 /* Update the data in CUM to advance over an argument
1357 of mode MODE and data type TYPE.
1358 (TYPE is null for libcalls where that information may not be available.) */
1361 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1363 (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \
1364 ROUND_REG ((CUM), (MODE)) \
1365 + (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1366 ? GET_MODE_SIZE (MODE) / 4 \
1367 : ROUND_ADVANCE ((MODE) == BLKmode \
1368 ? GET_MODE_SIZE (Pmode) \
1369 : GET_MODE_SIZE (MODE))); \
1370 sparc_arg_count++; \
1373 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1374 ((CUM) += ((MODE) != BLKmode \
1375 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1376 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
1379 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1380 This macro is only used in this file. */
1383 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1384 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
1385 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1386 && ((TYPE)==0 || (MODE) != BLKmode))
1388 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1389 ((CUM) < NPARM_REGS (SImode) \
1390 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1391 && ((TYPE)==0 || (MODE) != BLKmode \
1392 || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0)))
1395 /* Determine where to put an argument to a function.
1396 Value is zero to push the argument on the stack,
1397 or a hard register in which to store the argument.
1399 MODE is the argument's machine mode.
1400 TYPE is the data type of the argument (as a tree).
1401 This is null for libcalls where that information may
1403 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1404 the preceding args and about the function being called.
1405 NAMED is nonzero if this argument is a named parameter
1406 (otherwise it is an extra parameter matching an ellipsis). */
1408 /* On SPARC the first six args are normally in registers
1409 and the rest are pushed. Any arg that starts within the first 6 words
1410 is at least partially passed in a register unless its data type forbids.
1411 For v9, the first 6 int args are passed in regs and the first N
1412 float args are passed in regs (where N is such that %f0-15 are filled).
1413 The rest are pushed. Any arg that starts within the first 6 words
1414 is at least partially passed in a register unless its data type forbids. */
1416 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1417 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1418 ? gen_rtx (REG, (MODE), \
1419 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1422 /* Define where a function finds its arguments.
1423 This is different from FUNCTION_ARG because of register windows. */
1425 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1426 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1427 ? gen_rtx (REG, (MODE), \
1428 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1431 /* For an arg passed partly in registers and partly in memory,
1432 this is the number of registers used.
1433 For args passed entirely in registers or entirely in memory, zero.
1434 Any arg that starts in the first 6 regs but won't entirely fit in them
1435 needs partial registers on the Sparc (!v9). On v9, there are no arguments
1436 that are passed partially in registers (??? complex values?). */
1439 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1440 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1441 && ((CUM) + ((MODE) == BLKmode \
1442 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1443 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\
1444 ? (NPARM_REGS (SImode) - (CUM)) \
1448 /* The SPARC ABI stipulates passing struct arguments (of any size) and
1449 (!v9) quad-precision floats by invisible reference.
1450 For Pascal, also pass arrays by reference. */
1451 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1452 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
1453 || TREE_CODE (TYPE) == UNION_TYPE \
1454 || TREE_CODE (TYPE) == ARRAY_TYPE)) \
1455 || (!TARGET_V9 && MODE == TFmode))
1457 /* A C expression that indicates when it is the called function's
1458 responsibility to make copies of arguments passed by reference.
1459 If the callee can determine that the argument won't be modified, it can
1461 /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't
1462 include the last named argument so we keep track of the args ourselves. */
1465 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1466 (sparc_arg_count < sparc_n_named_args)
1469 /* Initialize data used by insn expanders. This is called from
1470 init_emit, once for each function, before code is generated.
1471 For v9, clear the temp slot used by float/int DImode conversions.
1472 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1473 space at some point.
1474 ??? Use assign_stack_temp? */
1476 extern void sparc64_init_expanders ();
1477 extern struct rtx_def *sparc64_fpconv_stack_temp ();
1479 #define INIT_EXPANDERS sparc64_init_expanders ()
1482 /* Define the information needed to generate branch and scc insns. This is
1483 stored from the compare operation. Note that we can't use "rtx" here
1484 since it hasn't been defined! */
1486 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1488 /* Define the function that build the compare insn for scc and bcc. */
1490 extern struct rtx_def *gen_compare_reg ();
1492 /* This function handles all v9 scc insns */
1494 extern int gen_v9_scc ();
1496 /* Generate the special assembly code needed to tell the assembler whatever
1497 it might need to know about the return value of a function.
1499 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1500 information to the assembler relating to peephole optimization (done in
1503 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1504 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1506 /* Output the label for a function definition. */
1508 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1510 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1511 ASM_OUTPUT_LABEL (FILE, NAME); \
1514 /* This macro generates the assembly code for function entry.
1515 FILE is a stdio stream to output the code to.
1516 SIZE is an int: how many units of temporary storage to allocate.
1517 Refer to the array `regs_ever_live' to determine which registers
1518 to save; `regs_ever_live[I]' is nonzero if register number I
1519 is ever used in the function. This macro is responsible for
1520 knowing which registers should not be saved even if used. */
1522 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1523 of memory. If any fpu reg is used in the function, we allocate
1524 such a block here, at the bottom of the frame, just in case it's needed.
1526 If this function is a leaf procedure, then we may choose not
1527 to do a "save" insn. The decision about whether or not
1528 to do this is made in regclass.c. */
1530 extern int leaf_function;
1531 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1532 (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \
1533 : output_function_prologue (FILE, SIZE, leaf_function))
1535 /* Output assembler code to FILE to increment profiler label # LABELNO
1536 for profiling a function entry. */
1538 #define FUNCTION_PROFILER(FILE, LABELNO) \
1540 fputs ("\tsethi %hi(", (FILE)); \
1541 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1542 fputs ("),%o0\n", (FILE)); \
1543 if (TARGET_MEDANY) \
1544 fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \
1546 fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \
1547 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1548 fputs ("),%o0,%o0\n", (FILE)); \
1552 /* There are three profiling modes for basic blocks available.
1553 The modes are selected at compile time by using the options
1554 -a or -ax of the gnu compiler.
1555 The variable `profile_block_flag' will be set according to the
1558 profile_block_flag == 0, no option used:
1562 profile_block_flag == 1, -a option used.
1564 Count frequency of execution of every basic block.
1566 profile_block_flag == 2, -ax option used.
1568 Generate code to allow several different profiling modes at run time.
1569 Available modes are:
1570 Produce a trace of all basic blocks.
1571 Count frequency of jump instructions executed.
1572 In every mode it is possible to start profiling upon entering
1573 certain functions and to disable profiling of some other functions.
1575 The result of basic-block profiling will be written to a file `bb.out'.
1576 If the -ax option is used parameters for the profiling will be read
1581 /* The following macro shall output assembler code to FILE
1582 to initialize basic-block profiling.
1584 If profile_block_flag == 2
1586 Output code to call the subroutine `__bb_init_trace_func'
1587 and pass two parameters to it. The first parameter is
1588 the address of a block allocated in the object module.
1589 The second parameter is the number of the first basic block
1592 The name of the block is a local symbol made with this statement:
1594 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1596 Of course, since you are writing the definition of
1597 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1598 can take a short cut in the definition of this macro and use the
1599 name that you know will result.
1601 The number of the first basic block of the function is
1602 passed to the macro in BLOCK_OR_LABEL.
1604 If described in a virtual assembler language the code to be
1608 parameter2 <- BLOCK_OR_LABEL
1609 call __bb_init_trace_func
1611 else if profile_block_flag != 0
1613 Output code to call the subroutine `__bb_init_func'
1614 and pass one single parameter to it, which is the same
1615 as the first parameter to `__bb_init_trace_func'.
1617 The first word of this parameter is a flag which will be nonzero if
1618 the object module has already been initialized. So test this word
1619 first, and do not call `__bb_init_func' if the flag is nonzero.
1620 Note: When profile_block_flag == 2 the test need not be done
1621 but `__bb_init_trace_func' *must* be called.
1623 BLOCK_OR_LABEL may be used to generate a label number as a
1624 branch destination in case `__bb_init_func' will not be called.
1626 If described in a virtual assembler language the code to be
1637 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1640 int bol = (BLOCK_OR_LABEL); \
1641 switch (profile_block_flag) \
1644 if (TARGET_MEDANY) \
1645 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
1646 MEDANY_BASE_REG, bol, bol); \
1648 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
1652 if (TARGET_MEDANY) \
1653 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1654 MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
1656 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1663 /* The following macro shall output assembler code to FILE
1664 to increment a counter associated with basic block number BLOCKNO.
1666 If profile_block_flag == 2
1668 Output code to initialize the global structure `__bb' and
1669 call the function `__bb_trace_func' which will increment the
1672 `__bb' consists of two words. In the first word the number
1673 of the basic block has to be stored. In the second word
1674 the address of a block allocated in the object module
1677 The basic block number is given by BLOCKNO.
1679 The address of the block is given by the label created with
1681 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1683 by FUNCTION_BLOCK_PROFILER.
1685 Of course, since you are writing the definition of
1686 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1687 can take a short cut in the definition of this macro and use the
1688 name that you know will result.
1690 If described in a virtual assembler language the code to be
1693 move BLOCKNO -> (__bb)
1694 move LPBX0 -> (__bb+4)
1695 call __bb_trace_func
1697 Note that function `__bb_trace_func' must not change the
1698 machine state, especially the flag register. To grant
1699 this, you must output code to save and restore registers
1700 either in this macro or in the macros MACHINE_STATE_SAVE
1701 and MACHINE_STATE_RESTORE. The last two macros will be
1702 used in the function `__bb_trace_func', so you must make
1703 sure that the function prologue does not change any
1704 register prior to saving it with MACHINE_STATE_SAVE.
1706 else if profile_block_flag != 0
1708 Output code to increment the counter directly.
1709 Basic blocks are numbered separately from zero within each
1710 compiled object module. The count associated with block number
1711 BLOCKNO is at index BLOCKNO in an array of words; the name of
1712 this array is a local symbol made with this statement:
1714 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
1716 Of course, since you are writing the definition of
1717 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1718 can take a short cut in the definition of this macro and use the
1719 name that you know will result.
1721 If described in a virtual assembler language, the code to be
1724 inc (LPBX2+4*BLOCKNO)
1728 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1731 int blockn = (BLOCKNO); \
1732 switch (profile_block_flag) \
1735 if (TARGET_MEDANY) \
1736 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1737 blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1739 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1743 if (TARGET_MEDANY) \
1744 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1745 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1747 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1748 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1749 4 * blockn, 4 * blockn, 4 * blockn); \
1755 /* The following macro shall output assembler code to FILE
1756 to indicate a return from function during basic-block profiling.
1758 If profiling_block_flag == 2:
1760 Output assembler code to call function `__bb_trace_ret'.
1762 Note that function `__bb_trace_ret' must not change the
1763 machine state, especially the flag register. To grant
1764 this, you must output code to save and restore registers
1765 either in this macro or in the macros MACHINE_STATE_SAVE_RET
1766 and MACHINE_STATE_RESTORE_RET. The last two macros will be
1767 used in the function `__bb_trace_ret', so you must make
1768 sure that the function prologue does not change any
1769 register prior to saving it with MACHINE_STATE_SAVE_RET.
1771 else if profiling_block_flag != 0:
1773 The macro will not be used, so it need not distinguish
1777 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1778 fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
1780 /* The function `__bb_trace_func' is called in every basic block
1781 and is not allowed to change the machine state. Saving (restoring)
1782 the state can either be done in the BLOCK_PROFILER macro,
1783 before calling function (rsp. after returning from function)
1784 `__bb_trace_func', or it can be done inside the function by
1785 defining the macros:
1787 MACHINE_STATE_SAVE(ID)
1788 MACHINE_STATE_RESTORE(ID)
1790 In the latter case care must be taken, that the prologue code
1791 of function `__bb_trace_func' does not already change the
1792 state prior to saving it with MACHINE_STATE_SAVE.
1794 The parameter `ID' is a string identifying a unique macro use.
1796 On sparc it is sufficient to save the psw register to memory.
1797 Unfortunately the psw register can be read in supervisor mode only,
1798 so we read only the condition codes by using branch instructions
1799 and hope that this is enough. */
1801 #define MACHINE_STATE_SAVE(ID) \
1802 asm (" mov %g0,%l0");\
1803 asm (" be,a LFLGNZ" ID);\
1804 asm (" or %l0,4,%l0");\
1805 asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\
1806 asm (" or %l0,1,%l0");\
1807 asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\
1808 asm (" or %l0,2,%l0");\
1809 asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\
1810 asm (" or %l0,8,%l0");\
1811 asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\
1812 asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \
1813 asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]");
1815 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1816 The psw register can be written in supervisor mode only,
1817 which is true even for simple condition codes.
1818 We use some combination of instructions to produce the
1819 proper condition codes, but some flag combinations can not
1820 be generated in this way. If this happens an unimplemented
1821 instruction will be executed to abort the program. */
1823 #define MACHINE_STATE_RESTORE(ID) \
1824 asm (" sethi %hi(LFLGTAB" ID "),%l1");\
1825 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\
1826 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\
1827 asm (" sll %l0,2,%l0");\
1828 asm (" add %l0,%l1,%l0");\
1829 asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\
1834 asm ("LFLAGS" ID ":");\
1836 asm ("LSAVRET" ID ":");\
1838 asm ("LFLGTAB" ID ": ");\
1839 asm (" .word LSFLG0" ID);\
1840 asm (" .word LSFLGC" ID);\
1841 asm (" .word LSFLGV" ID);\
1842 asm (" .word LSFLGVC" ID);\
1843 asm (" .word LSFLGZ" ID);\
1844 asm (" .word LSFLGZC" ID);\
1845 asm (" .word LSFLGZV" ID);\
1846 asm (" .word LSFLGZVC" ID);\
1847 asm (" .word LSFLGN" ID);\
1848 asm (" .word LSFLGNC" ID);\
1849 asm (" .word LSFLGNV" ID);\
1850 asm (" .word LSFLGNVC" ID);\
1851 asm (" .word LSFLGNZ" ID);\
1852 asm (" .word LSFLGNZC" ID);\
1853 asm (" .word LSFLGNZV" ID);\
1854 asm (" .word LSFLGNZVC" ID);\
1856 asm ("LSFLGVC" ID ": mov -1,%l0");\
1857 asm (" addcc 2,%l0,%g0");\
1858 asm (" sethi %hi(0x80000000),%l0");\
1859 asm (" mov %l0,%l1");\
1860 asm (" ba LFLGRET" ID);\
1861 asm (" addxcc %l0,%l1,%l0");\
1862 asm ("LSFLGC" ID ": mov -1,%l0");\
1863 asm (" ba LFLGRET" ID);\
1864 asm (" addcc 2,%l0,%g0");\
1865 asm ("LSFLGZC" ID ": mov -1,%l0");\
1866 asm (" ba LFLGRET" ID);\
1867 asm (" addcc 1,%l0,%l0");\
1868 asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\
1869 asm (" mov %l0,%l1");\
1870 asm (" ba LFLGRET" ID);\
1871 asm (" addcc %l0,%l1,%l0");\
1872 asm ("LSFLGZ" ID ": ba LFLGRET" ID);\
1873 asm (" subcc %g0,%g0,%g0");\
1874 asm ("LSFLGNC" ID ": add %g0,1,%l0");\
1875 asm (" ba LFLGRET" ID);\
1876 asm (" subcc %g0,%l0,%g0");\
1877 asm ("LSFLG0" ID ": ba LFLGRET" ID);\
1878 asm (" orcc 1,%g0,%g0");\
1879 asm ("LSFLGN" ID ": ba LFLGRET" ID);\
1880 asm (" orcc -1,%g0,%g0");\
1881 asm ("LSFLGV" ID ":");\
1882 asm ("LSFLGZV" ID ":");\
1883 asm ("LSFLGNV" ID ":");\
1884 asm ("LSFLGNVC" ID ":");\
1885 asm ("LSFLGNZ" ID ":");\
1886 asm ("LSFLGNZC" ID ":");\
1887 asm ("LSFLGNZV" ID ":");\
1888 asm ("LSFLGNZVC" ID ":");\
1890 asm ("LFLGRET" ID ":");
1892 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1893 the stack pointer does not matter. The value is tested only in
1894 functions that have frame pointers.
1895 No definition is equivalent to always zero. */
1897 extern int current_function_calls_alloca;
1898 extern int current_function_outgoing_args_size;
1900 #define EXIT_IGNORE_STACK \
1901 (get_frame_size () != 0 \
1902 || current_function_calls_alloca || current_function_outgoing_args_size)
1904 /* This macro generates the assembly code for function exit,
1905 on machines that need it. If FUNCTION_EPILOGUE is not defined
1906 then individual return instructions are generated for each
1907 return statement. Args are same as for FUNCTION_PROLOGUE.
1909 The function epilogue should not depend on the current stack pointer!
1910 It should use the frame pointer only. This is mandatory because
1911 of alloca; we also take advantage of it to omit stack adjustments
1912 before returning. */
1914 /* This declaration is needed due to traditional/ANSI
1915 incompatibilities which cannot be #ifdefed away
1916 because they occur inside of macros. Sigh. */
1917 extern union tree_node *current_function_decl;
1919 #define FUNCTION_EPILOGUE(FILE, SIZE) \
1920 (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \
1921 : output_function_epilogue (FILE, SIZE, leaf_function))
1923 #define DELAY_SLOTS_FOR_EPILOGUE \
1924 (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1)
1925 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1926 (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1927 : eligible_for_epilogue_delay (trial, slots_filled))
1929 /* Output assembler code for a block containing the constant parts
1930 of a trampoline, leaving space for the variable parts. */
1932 /* On 32 bit sparcs, the trampoline contains five instructions:
1933 sethi #TOP_OF_FUNCTION,%g1
1934 or #BOTTOM_OF_FUNCTION,%g1,%g1
1935 sethi #TOP_OF_STATIC,%g2
1937 or #BOTTOM_OF_STATIC,%g2,%g2
1939 On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate
1940 constants (plus some padding):
1950 #define TRAMPOLINE_TEMPLATE(FILE) \
1954 fprintf (FILE, "\trd %%pc,%%g1\n"); \
1955 fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \
1956 fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \
1957 fprintf (FILE, "\tjmp %%g1\n"); \
1958 fprintf (FILE, "\tnop\n"); \
1959 fprintf (FILE, "\tnop\n"); \
1960 /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \
1961 fprintf (FILE, "\t.word 0,0,0,0\n"); \
1965 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1966 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1967 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1968 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
1969 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1973 /* Length in units of the trampoline for entering a nested function. */
1975 #define TRAMPOLINE_SIZE (TARGET_V9 ? 40 : 20)
1977 /* Emit RTL insns to initialize the variable parts of a trampoline.
1978 FNADDR is an RTX for the address of the function's pure code.
1979 CXT is an RTX for the static chain value for the function. */
1981 void sparc_initialize_trampoline ();
1982 void sparc64_initialize_trampoline ();
1983 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1986 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1988 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
1991 /* Generate necessary RTL for __builtin_saveregs().
1992 ARGLIST is the argument list; see expr.c. */
1993 extern struct rtx_def *sparc_builtin_saveregs ();
1994 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1996 /* Generate RTL to flush the register windows so as to make arbitrary frames
1998 #define SETUP_FRAME_ADDRESSES() \
1999 emit_insn (gen_flush_register_windows ())
2001 /* Given an rtx for the address of a frame,
2002 return an rtx for the address of the word in the frame
2003 that holds the dynamic chain--the previous frame's address.
2004 ??? -mflat support? */
2005 #define DYNAMIC_CHAIN_ADDRESS(frame) \
2006 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
2008 /* The return address isn't on the stack, it is in a register, so we can't
2009 access it from the current frame pointer. We can access it from the
2010 previous frame pointer though by reading a value from the register window
2012 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2014 /* This is the offset of the return address to the true next instruction to be
2015 executed for the current function. */
2016 #define RETURN_ADDR_OFFSET (8 + 4*(! TARGET_V9 && current_function_returns_struct))
2018 /* The current return address is in %i7. The return address of anything
2019 farther back is in the register window save area at [%fp+60]. */
2020 /* ??? This ignores the fact that the actual return address is +8 for normal
2021 returns, and +12 for structure returns. */
2022 #define RETURN_ADDR_RTX(count, frame) \
2024 ? gen_rtx (REG, Pmode, 31) \
2025 : gen_rtx (MEM, Pmode, \
2026 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
2028 /* Addressing modes, and classification of registers for them. */
2030 /* #define HAVE_POST_INCREMENT */
2031 /* #define HAVE_POST_DECREMENT */
2033 /* #define HAVE_PRE_DECREMENT */
2034 /* #define HAVE_PRE_INCREMENT */
2036 /* Macros to check register numbers against specific register classes. */
2038 /* These assume that REGNO is a hard or pseudo reg number.
2039 They give nonzero only if REGNO is a hard reg of the suitable class
2040 or a pseudo reg currently allocated to a suitable hard reg.
2041 Since they use reg_renumber, they are safe only once reg_renumber
2042 has been allocated, which happens in local-alloc.c. */
2044 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2045 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
2046 #define REGNO_OK_FOR_BASE_P(REGNO) \
2047 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
2048 #define REGNO_OK_FOR_FP_P(REGNO) \
2049 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
2050 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
2051 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2053 && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4))
2055 /* Now macros that check whether X is a register and also,
2056 strictly, whether it is in a specified class.
2058 These macros are specific to the SPARC, and may be used only
2059 in code for printing assembler insns and in conditions for
2060 define_optimization. */
2062 /* 1 if X is an fp register. */
2064 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2066 /* Maximum number of registers that can appear in a valid memory address. */
2068 #define MAX_REGS_PER_ADDRESS 2
2070 /* Recognize any constant value that is a valid address.
2071 When PIC, we do not accept an address that would require a scratch reg
2072 to load into a register. */
2074 #define CONSTANT_ADDRESS_P(X) \
2075 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2076 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2077 || (GET_CODE (X) == CONST \
2078 && ! (flag_pic && pic_address_needs_scratch (X))))
2080 /* Define this, so that when PIC, reload won't try to reload invalid
2081 addresses which require two reload registers. */
2083 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2085 /* Nonzero if the constant value X is a legitimate general operand.
2086 Anything can be made to work except floating point constants. */
2088 #define LEGITIMATE_CONSTANT_P(X) \
2089 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
2091 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2092 and check its validity for a certain class.
2093 We have two alternate definitions for each of them.
2094 The usual definition accepts all pseudo regs; the other rejects
2095 them unless they have been allocated suitable hard regs.
2096 The symbol REG_OK_STRICT causes the latter definition to be used.
2098 Most source files want to accept pseudo regs in the hope that
2099 they will get allocated to the class that the insn wants them to be in.
2100 Source files for reload pass need to be strict.
2101 After reload, it makes no difference, since pseudo regs have
2102 been eliminated by then. */
2104 /* Optional extra constraints for this machine. Borrowed from romp.h.
2106 For the SPARC, `Q' means that this is a memory operand but not a
2107 symbolic memory operand. Note that an unassigned pseudo register
2108 is such a memory operand. Needed because reload will generate
2109 these things in insns and then not re-recognize the insns, causing
2110 constrain_operands to fail.
2112 `S' handles constraints for calls. ??? So where is it? */
2114 #ifndef REG_OK_STRICT
2116 /* Nonzero if X is a hard reg that can be used as an index
2117 or if it is a pseudo reg. */
2118 #define REG_OK_FOR_INDEX_P(X) \
2119 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0)
2120 /* Nonzero if X is a hard reg that can be used as a base reg
2121 or if it is a pseudo reg. */
2122 #define REG_OK_FOR_BASE_P(X) \
2123 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0)
2125 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
2127 #define EXTRA_CONSTRAINT(OP, C) \
2129 ? ((GET_CODE (OP) == MEM \
2130 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
2131 && ! symbolic_memory_operand (OP, VOIDmode)) \
2132 || (reload_in_progress && GET_CODE (OP) == REG \
2133 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
2134 : ! TARGET_V9 && (C) == 'T' \
2135 ? (mem_aligned_8 (OP)) \
2136 : ! TARGET_V9 && (C) == 'U' \
2137 ? (register_ok_for_ldd (OP)) \
2142 /* Nonzero if X is a hard reg that can be used as an index. */
2143 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2144 /* Nonzero if X is a hard reg that can be used as a base reg. */
2145 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2147 #define EXTRA_CONSTRAINT(OP, C) \
2149 ? (GET_CODE (OP) == REG \
2150 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
2151 && reg_renumber[REGNO (OP)] < 0) \
2152 : GET_CODE (OP) == MEM) \
2153 : ! TARGET_V9 && (C) == 'T' \
2154 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2155 : ! TARGET_V9 && (C) == 'U' \
2156 ? (GET_CODE (OP) == REG \
2157 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2158 || reg_renumber[REGNO (OP)] > 0) \
2159 && register_ok_for_ldd (OP)) : 0)
2162 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2163 that is a valid memory address for an instruction.
2164 The MODE argument is the machine mode for the MEM expression
2165 that wants to use this address.
2167 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2168 ordinarily. This changes a bit when generating PIC.
2170 If you change this, execute "rm explow.o recog.o reload.o". */
2172 #define RTX_OK_FOR_BASE_P(X) \
2173 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2174 || (GET_CODE (X) == SUBREG \
2175 && GET_CODE (SUBREG_REG (X)) == REG \
2176 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2178 #define RTX_OK_FOR_INDEX_P(X) \
2179 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2180 || (GET_CODE (X) == SUBREG \
2181 && GET_CODE (SUBREG_REG (X)) == REG \
2182 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2184 #define RTX_OK_FOR_OFFSET_P(X) \
2185 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
2187 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2188 { if (RTX_OK_FOR_BASE_P (X)) \
2190 else if (GET_CODE (X) == PLUS) \
2192 register rtx op0 = XEXP (X, 0); \
2193 register rtx op1 = XEXP (X, 1); \
2194 if (flag_pic && op0 == pic_offset_table_rtx) \
2196 if (RTX_OK_FOR_BASE_P (op1)) \
2198 else if (flag_pic == 1 \
2199 && GET_CODE (op1) != REG \
2200 && GET_CODE (op1) != LO_SUM \
2201 && GET_CODE (op1) != MEM \
2202 && (GET_CODE (op1) != CONST_INT \
2203 || SMALL_INT (op1))) \
2206 else if (RTX_OK_FOR_BASE_P (op0)) \
2208 if (RTX_OK_FOR_INDEX_P (op1) \
2209 || RTX_OK_FOR_OFFSET_P (op1)) \
2212 else if (RTX_OK_FOR_BASE_P (op1)) \
2214 if (RTX_OK_FOR_INDEX_P (op0) \
2215 || RTX_OK_FOR_OFFSET_P (op0)) \
2219 else if (GET_CODE (X) == LO_SUM) \
2221 register rtx op0 = XEXP (X, 0); \
2222 register rtx op1 = XEXP (X, 1); \
2223 if (RTX_OK_FOR_BASE_P (op0) \
2224 && CONSTANT_P (op1) \
2225 /* We can't allow TFmode, because an offset \
2226 greater than or equal to the alignment (8) \
2227 may cause the LO_SUM to overflow. */ \
2228 && MODE != TFmode) \
2231 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2235 /* Try machine-dependent ways of modifying an illegitimate address
2236 to be legitimate. If we find one, return the new, valid address.
2237 This macro is used in only one place: `memory_address' in explow.c.
2239 OLDX is the address as it was before break_out_memory_refs was called.
2240 In some cases it is useful to look at this to decide what needs to be done.
2242 MODE and WIN are passed so that this macro can use
2243 GO_IF_LEGITIMATE_ADDRESS.
2245 It is always safe for this macro to do nothing. It exists to recognize
2246 opportunities to optimize the output. */
2248 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2249 extern struct rtx_def *legitimize_pic_address ();
2250 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2251 { rtx sparc_x = (X); \
2252 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2253 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2254 force_operand (XEXP (X, 0), NULL_RTX)); \
2255 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2256 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2257 force_operand (XEXP (X, 1), NULL_RTX)); \
2258 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2259 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2261 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2262 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2263 force_operand (XEXP (X, 1), NULL_RTX)); \
2264 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2266 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2267 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2268 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2269 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2270 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2271 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2272 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2273 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2274 || GET_CODE (X) == LABEL_REF) \
2275 (X) = gen_rtx (LO_SUM, Pmode, \
2276 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2277 if (memory_address_p (MODE, X)) \
2280 /* Go to LABEL if ADDR (a legitimate address expression)
2281 has an effect that depends on the machine mode it is used for.
2282 On the SPARC this is never true. */
2284 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2286 /* If we are referencing a function make the SYMBOL_REF special.
2287 In the Medium/Anywhere code model, %g4 points to the data segment so we
2288 must not add it to function addresses. */
2290 #define ENCODE_SECTION_INFO(DECL) \
2292 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2293 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2296 /* Specify the machine mode that this machine uses
2297 for the index in the tablejump instruction. */
2298 #define CASE_VECTOR_MODE Pmode
2300 /* Define this if the tablejump instruction expects the table
2301 to contain offsets from the address of the table.
2302 Do not define this if the table should contain absolute addresses. */
2303 /* #define CASE_VECTOR_PC_RELATIVE */
2305 /* Specify the tree operation to be used to convert reals to integers. */
2306 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2308 /* This is the kind of divide that is easiest to do in the general case. */
2309 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2311 /* Define this as 1 if `char' should by default be signed; else as 0. */
2312 #define DEFAULT_SIGNED_CHAR 1
2314 /* Max number of bytes we can move from memory to memory
2315 in one reasonably fast instruction. */
2318 #if 0 /* Sun 4 has matherr, so this is no good. */
2319 /* This is the value of the error code EDOM for this machine,
2320 used by the sqrt instruction. */
2321 #define TARGET_EDOM 33
2323 /* This is how to refer to the variable errno. */
2324 #define GEN_ERRNO_RTX \
2325 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
2328 /* Define if operations between registers always perform the operation
2329 on the full register even if a narrower mode is specified. */
2330 #define WORD_REGISTER_OPERATIONS
2332 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2333 will either zero-extend or sign-extend. The value of this macro should
2334 be the code that says which one of the two operations is implicitly
2335 done, NIL if none. */
2336 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2338 /* Nonzero if access to memory by bytes is slow and undesirable.
2339 For RISC chips, it means that access to memory by bytes is no
2340 better than access by words when possible, so grab a whole word
2341 and maybe make use of that. */
2342 #define SLOW_BYTE_ACCESS 1
2344 /* We assume that the store-condition-codes instructions store 0 for false
2345 and some other value for true. This is the value stored for true. */
2347 #define STORE_FLAG_VALUE 1
2349 /* When a prototype says `char' or `short', really pass an `int'. */
2350 #define PROMOTE_PROTOTYPES
2352 /* Define this to be nonzero if shift instructions ignore all but the low-order
2354 #define SHIFT_COUNT_TRUNCATED 1
2356 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2357 is done just by pretending it is already truncated. */
2358 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2360 /* Specify the machine mode that pointers have.
2361 After generation of rtl, the compiler makes no further distinction
2362 between pointers and any other objects of this machine mode. */
2363 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2365 /* Generate calls to memcpy, memcmp and memset. */
2366 #define TARGET_MEM_FUNCTIONS
2368 /* Add any extra modes needed to represent the condition code.
2370 On the Sparc, we have a "no-overflow" mode which is used when an add or
2371 subtract insn is used to set the condition code. Different branches are
2372 used in this case for some operations.
2374 We also have two modes to indicate that the relevant condition code is
2375 in the floating-point condition code register. One for comparisons which
2376 will generate an exception if the result is unordered (CCFPEmode) and
2377 one for comparisons which will never trap (CCFPmode). This really should
2378 be a separate register, but we don't want to go to 65 registers.
2380 CCXmode and CCX_NOOVmode are only used by v9. */
2382 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2384 /* Define the names for the modes specified above. */
2386 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2388 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2389 return the mode to be used for the comparison. For floating-point,
2390 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2391 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2392 processing is needed. */
2393 #define SELECT_CC_MODE(OP,X,Y) \
2394 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2395 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2396 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2397 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2398 ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2399 : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2401 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2402 floating point inequality comparison. */
2404 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2406 /* A function address in a call instruction
2407 is a byte address (for indexing purposes)
2408 so give the MEM rtx a byte's mode. */
2409 #define FUNCTION_MODE SImode
2411 /* Define this if addresses of constant functions
2412 shouldn't be put through pseudo regs where they can be cse'd.
2413 Desirable on machines where ordinary constants are expensive
2414 but a CALL with constant address is cheap. */
2415 #define NO_FUNCTION_CSE
2417 /* alloca should avoid clobbering the old register save area. */
2418 #define SETJMP_VIA_SAVE_AREA
2420 /* Define subroutines to call to handle multiply and divide.
2421 Use the subroutines that Sun's library provides.
2422 The `*' prevents an underscore from being prepended by the compiler. */
2424 #define DIVSI3_LIBCALL "*.div"
2425 #define UDIVSI3_LIBCALL "*.udiv"
2426 #define MODSI3_LIBCALL "*.rem"
2427 #define UMODSI3_LIBCALL "*.urem"
2428 /* .umul is a little faster than .mul. */
2429 #define MULSI3_LIBCALL "*.umul"
2431 /* Define library calls for quad FP operations. These are all part of the
2433 #define ADDTF3_LIBCALL "_Q_add"
2434 #define SUBTF3_LIBCALL "_Q_sub"
2435 #define NEGTF2_LIBCALL "_Q_neg"
2436 #define MULTF3_LIBCALL "_Q_mul"
2437 #define DIVTF3_LIBCALL "_Q_div"
2438 #define FLOATSITF2_LIBCALL "_Q_itoq"
2439 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2440 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2441 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2442 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2443 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2444 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2445 #define EQTF2_LIBCALL "_Q_feq"
2446 #define NETF2_LIBCALL "_Q_fne"
2447 #define GTTF2_LIBCALL "_Q_fgt"
2448 #define GETF2_LIBCALL "_Q_fge"
2449 #define LTTF2_LIBCALL "_Q_flt"
2450 #define LETF2_LIBCALL "_Q_fle"
2452 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2453 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2454 and the compiler will notice and try to use the TFmode sqrt instruction
2455 for calls to the builtin function sqrt, but this fails. */
2456 #define INIT_TARGET_OPTABS \
2458 add_optab->handlers[(int) TFmode].libfunc \
2459 = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \
2460 sub_optab->handlers[(int) TFmode].libfunc \
2461 = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \
2462 neg_optab->handlers[(int) TFmode].libfunc \
2463 = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \
2464 smul_optab->handlers[(int) TFmode].libfunc \
2465 = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \
2466 flodiv_optab->handlers[(int) TFmode].libfunc \
2467 = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \
2468 eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \
2469 netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \
2470 gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \
2471 getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \
2472 lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \
2473 letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \
2474 trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \
2475 trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \
2476 extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \
2477 extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \
2478 floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \
2479 fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \
2480 fixunstfsi_libfunc \
2481 = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \
2483 sqrt_optab->handlers[(int) TFmode].libfunc \
2484 = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \
2485 INIT_SUBTARGET_OPTABS; \
2488 /* This is meant to be redefined in the host dependent files */
2489 #define INIT_SUBTARGET_OPTABS
2491 /* Compute the cost of computing a constant rtl expression RTX
2492 whose rtx-code is CODE. The body of this macro is a portion
2493 of a switch statement. If the code is computed here,
2494 return it with a return statement. Otherwise, break from the switch. */
2496 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2498 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2506 case CONST_DOUBLE: \
2507 if (GET_MODE (RTX) == DImode) \
2508 if ((XINT (RTX, 3) == 0 \
2509 && (unsigned) XINT (RTX, 2) < 0x1000) \
2510 || (XINT (RTX, 3) == -1 \
2511 && XINT (RTX, 2) < 0 \
2512 && XINT (RTX, 2) >= -0x1000)) \
2516 /* Compute the cost of an address. For the sparc, all valid addresses are
2518 ??? Is this true for v9? */
2520 #define ADDRESS_COST(RTX) 1
2522 /* Compute extra cost of moving data between one register class
2524 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2525 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2526 (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \
2527 || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2)
2529 /* Provide the costs of a rtl expression. This is in the body of a
2530 switch on CODE. The purpose for the cost of MULT is to encourage
2531 `synth_mult' to find a synthetic multiply when reasonable.
2533 If we need more than 12 insns to do a multiply, then go out-of-line,
2534 since the call overhead will be < 10% of the cost of the multiply. */
2536 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2538 return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2543 return COSTS_N_INSNS (25); \
2544 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2545 so that cse will favor the latter. */ \
2550 /* Adjust the cost of dependencies. */
2551 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2552 if (TARGET_SUPERSPARC) \
2553 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2555 /* Conditional branches with empty delay slots have a length of two. */
2556 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2557 if (GET_CODE (INSN) == CALL_INSN \
2558 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2561 /* Control the assembler format that we output. */
2563 /* Output at beginning of assembler file. */
2565 #define ASM_FILE_START(file)
2567 /* Output to assembler file text saying following lines
2568 may contain character constants, extra white space, comments, etc. */
2570 #define ASM_APP_ON ""
2572 /* Output to assembler file text saying following lines
2573 no longer contain unusual constructs. */
2575 #define ASM_APP_OFF ""
2577 /* ??? Try to make the style consistent here (_OP?). */
2579 #define ASM_LONGLONG ".xword"
2580 #define ASM_LONG ".word"
2581 #define ASM_SHORT ".half"
2582 #define ASM_BYTE_OP ".byte"
2583 #define ASM_FLOAT ".single"
2584 #define ASM_DOUBLE ".double"
2585 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2587 /* Output before read-only data. */
2589 #define TEXT_SECTION_ASM_OP ".text"
2591 /* Output before writable data. */
2593 #define DATA_SECTION_ASM_OP ".data"
2595 /* How to refer to registers in assembler output.
2596 This sequence is indexed by compiler's hard-register-number (see above). */
2599 #define REGISTER_NAMES \
2600 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2601 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2602 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2603 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2604 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2605 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2606 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2607 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2608 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2609 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2610 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2611 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2612 "%fcc0", "%fcc1", "%fcc2", "%fcc3"}
2614 #define REGISTER_NAMES \
2615 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2616 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2617 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2618 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2619 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2620 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2621 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2622 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
2625 /* Define additional names for use in asm clobbers and asm declarations.
2627 We define the fake Condition Code register as an alias for reg 0 (which
2628 is our `condition code' register), so that condition codes can easily
2629 be clobbered by an asm. No such register actually exists. Condition
2630 codes are partly stored in the PSR and partly in the FSR. */
2632 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
2634 /* How to renumber registers for dbx and gdb. */
2636 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2638 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
2639 since the length can run past this up to a continuation point. */
2640 #define DBX_CONTIN_LENGTH 1500
2642 /* This is how to output a note to DBX telling it the line number
2643 to which the following sequence of instructions corresponds.
2645 This is needed for SunOS 4.0, and should not hurt for 3.2
2647 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2648 { static int sym_lineno = 1; \
2649 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2650 line, sym_lineno, sym_lineno); \
2653 /* This is how to output the definition of a user-level label named NAME,
2654 such as the label on a static function or variable NAME. */
2656 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2657 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2659 /* This is how to output a command to make the user-level label named NAME
2660 defined for reference from other files. */
2662 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2663 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2665 /* This is how to output a reference to a user-level label named NAME.
2666 `assemble_name' uses this. */
2668 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2669 fprintf (FILE, "_%s", NAME)
2671 /* This is how to output a definition of an internal numbered label where
2672 PREFIX is the class of label and NUM is the number within the class. */
2674 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2675 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2677 /* This is how to output a reference to an internal numbered label where
2678 PREFIX is the class of label and NUM is the number within the class. */
2679 /* FIXME: This should be used throughout gcc, and documented in the texinfo
2680 files. There is no reason you should have to allocate a buffer and
2681 `sprintf' to reference an internal label (as opposed to defining it). */
2683 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
2684 fprintf (FILE, "%s%d", PREFIX, NUM)
2686 /* This is how to store into the string LABEL
2687 the symbol_ref name of an internal numbered label where
2688 PREFIX is the class of label and NUM is the number within the class.
2689 This is suitable for output with `assemble_name'. */
2691 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2692 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2694 /* This is how to output an assembler line defining a `double' constant. */
2696 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2699 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2700 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2701 ASM_LONG, t[0], ASM_LONG, t[1]); \
2704 /* This is how to output an assembler line defining a `float' constant. */
2706 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2709 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2710 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
2713 /* This is how to output an assembler line defining a `long double'
2716 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2719 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2720 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2721 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
2724 /* This is how to output an assembler line defining an `int' constant. */
2726 #define ASM_OUTPUT_INT(FILE,VALUE) \
2727 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2728 output_addr_const (FILE, (VALUE)), \
2729 fprintf (FILE, "\n"))
2731 /* This is how to output an assembler line defining a DImode constant. */
2732 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2733 output_double_int (FILE, VALUE)
2735 /* Likewise for `char' and `short' constants. */
2737 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2738 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2739 output_addr_const (FILE, (VALUE)), \
2740 fprintf (FILE, "\n"))
2742 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2743 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2744 output_addr_const (FILE, (VALUE)), \
2745 fprintf (FILE, "\n"))
2747 /* This is how to output an assembler line for a numeric constant byte. */
2749 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2750 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2752 /* This is how to output an element of a case-vector that is absolute. */
2754 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2757 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2758 if (Pmode == SImode) \
2759 fprintf (FILE, "\t.word\t"); \
2760 else if (TARGET_ENV32) \
2761 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2763 fprintf (FILE, "\t.xword\t"); \
2764 assemble_name (FILE, label); \
2765 fprintf (FILE, "\n"); \
2768 /* This is how to output an element of a case-vector that is relative.
2769 (SPARC uses such vectors only when generating PIC.) */
2771 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2774 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2775 if (Pmode == SImode) \
2776 fprintf (FILE, "\t.word\t"); \
2777 else if (TARGET_ENV32) \
2778 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2780 fprintf (FILE, "\t.xword\t"); \
2781 assemble_name (FILE, label); \
2782 fprintf (FILE, "-1b\n"); \
2785 /* This is how to output an assembler line
2786 that says to advance the location counter
2787 to a multiple of 2**LOG bytes. */
2789 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2791 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2793 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2794 fprintf (FILE, "\t.skip %u\n", (SIZE))
2796 /* This says how to output an assembler line
2797 to define a global common symbol. */
2799 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2800 ( fputs ("\t.common ", (FILE)), \
2801 assemble_name ((FILE), (NAME)), \
2802 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2804 /* This says how to output an assembler line to define a local common
2807 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2808 ( fputs ("\t.reserve ", (FILE)), \
2809 assemble_name ((FILE), (NAME)), \
2810 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2811 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2813 /* Store in OUTPUT a string (made with alloca) containing
2814 an assembler-name for a local static variable named NAME.
2815 LABELNO is an integer which is different for each call. */
2817 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2818 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2819 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2821 #define IDENT_ASM_OP ".ident"
2823 /* Output #ident as a .ident. */
2825 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2826 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
2828 /* Define the parentheses used to group arithmetic operations
2829 in assembler code. */
2831 #define ASM_OPEN_PAREN "("
2832 #define ASM_CLOSE_PAREN ")"
2834 /* Define results of standard character escape sequences. */
2835 #define TARGET_BELL 007
2836 #define TARGET_BS 010
2837 #define TARGET_TAB 011
2838 #define TARGET_NEWLINE 012
2839 #define TARGET_VT 013
2840 #define TARGET_FF 014
2841 #define TARGET_CR 015
2843 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2844 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
2846 /* Print operand X (an rtx) in assembler syntax to file FILE.
2847 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2848 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2850 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2852 /* Print a memory address as an operand to reference that memory location. */
2854 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2855 { register rtx base, index = 0; \
2857 register rtx addr = ADDR; \
2858 if (GET_CODE (addr) == REG) \
2859 fputs (reg_names[REGNO (addr)], FILE); \
2860 else if (GET_CODE (addr) == PLUS) \
2862 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2863 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2864 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2865 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2867 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2868 fputs (reg_names[REGNO (base)], FILE); \
2870 fprintf (FILE, "%+d", offset); \
2871 else if (GET_CODE (index) == REG) \
2872 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2873 else if (GET_CODE (index) == SYMBOL_REF \
2874 || GET_CODE (index) == CONST) \
2875 fputc ('+', FILE), output_addr_const (FILE, index); \
2878 else if (GET_CODE (addr) == MINUS \
2879 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2881 output_addr_const (FILE, XEXP (addr, 0)); \
2882 fputs ("-(", FILE); \
2883 output_addr_const (FILE, XEXP (addr, 1)); \
2884 fputs ("-.)", FILE); \
2886 else if (GET_CODE (addr) == LO_SUM) \
2888 output_operand (XEXP (addr, 0), 0); \
2889 fputs ("+%lo(", FILE); \
2890 output_address (XEXP (addr, 1)); \
2891 fputc (')', FILE); \
2893 else if (flag_pic && GET_CODE (addr) == CONST \
2894 && GET_CODE (XEXP (addr, 0)) == MINUS \
2895 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2896 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2897 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2899 addr = XEXP (addr, 0); \
2900 output_addr_const (FILE, XEXP (addr, 0)); \
2901 /* Group the args of the second CONST in parenthesis. */ \
2902 fputs ("-(", FILE); \
2903 /* Skip past the second CONST--it does nothing for us. */\
2904 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2905 /* Close the parenthesis. */ \
2906 fputc (')', FILE); \
2910 output_addr_const (FILE, addr); \
2914 /* Declare functions defined in sparc.c and used in templates. */
2916 extern char *singlemove_string ();
2917 extern char *output_move_double ();
2918 extern char *output_move_quad ();
2919 extern char *output_fp_move_double ();
2920 extern char *output_fp_move_quad ();
2921 extern char *output_block_move ();
2922 extern char *output_scc_insn ();
2923 extern char *output_cbranch ();
2924 extern char *output_v9branch ();
2925 extern char *output_return ();
2927 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
2929 extern int flag_pic;
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