1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \
25 %{a:/usr/lib/bb_link.o}"
27 /* Provide required defaults for linker -e and -d switches. */
30 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
32 /* Special flags to the Sun-4 assembler when using pipe for input. */
34 #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}"
36 /* Define macros to distinguish architectures. */
37 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
39 /* Prevent error on `-sun4' and `-target sun4' options. */
40 /* This used to translate -dalign to -malign, but that is no good
41 because it can't turn off the usual meaning of making debugging dumps. */
43 #define CC1_SPEC "%{sun4:} %{target:}"
45 #define PTRDIFF_TYPE "int"
46 /* In 2.4 it should work to delete this.
47 #define SIZE_TYPE "int" */
48 #define WCHAR_TYPE "short unsigned int"
49 #define WCHAR_TYPE_SIZE 16
51 /* Omit frame pointer at high optimization levels. */
53 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
57 flag_omit_frame_pointer = 1; \
61 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
62 code into the rtl. Also, if we are profiling, we cannot eliminate
63 the frame pointer (because the return address will get smashed). */
65 #define OVERRIDE_OPTIONS \
67 if (profile_flag || profile_block_flag) \
68 flag_omit_frame_pointer = 0, flag_pic = 0; \
69 SUBTARGET_OVERRIDE_OPTIONS \
72 /* This is meant to be redefined in the host dependent files */
73 #define SUBTARGET_OVERRIDE_OPTIONS
75 /* These compiler options take an argument. We ignore -target for now. */
77 #define WORD_SWITCH_TAKES_ARG(STR) \
78 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
79 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
81 /* Names to predefine in the preprocessor for this target machine. */
83 /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile
84 new versions, which have an incompatible va-sparc.h file. This matters
85 because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the
86 wrong varargs file when it is compiled with a different version of gcc. */
88 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__"
90 /* Print subsidiary information on the compiler version in use. */
92 #define TARGET_VERSION fprintf (stderr, " (sparc)");
94 /* Generate DBX debugging information. */
96 #define DBX_DEBUGGING_INFO
98 /* Run-time compilation parameters selecting different hardware subsets. */
100 extern int target_flags;
102 /* Nonzero if we should generate code to use the fpu. */
103 #define TARGET_FPU (target_flags & 1)
105 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
106 use fast return insns, but lose some generality. */
107 #define TARGET_EPILOGUE (target_flags & 2)
109 /* Nonzero if we should assume that double pointers might be unaligned.
110 This can happen when linking gcc compiled code with other compilers,
111 because the ABI only guarantees 4 byte alignment. */
112 #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
114 /* Nonzero means that we should generate code for a v8 sparc. */
115 #define TARGET_V8 (target_flags & 64)
117 /* Nonzero means that we should generate code for a sparclite. */
118 #define TARGET_SPARCLITE (target_flags & 128)
120 /* Nonzero means that we should generate code using a flat register window
121 model, i.e. no save/restore instructions are generated, in the most
122 efficient manner. This code is not compatible with normal sparc code. */
123 /* This is not a user selectable option yet, because it requires changes
124 that are not yet switchable via command line arguments. */
125 #define TARGET_FRW (target_flags & 256)
127 /* Nonzero means that we should generate code using a flat register window
128 model, i.e. no save/restore instructions are generated, but which is
129 compatible with normal sparc code. This is the same as above, except
130 that the frame pointer is %l6 instead of %fp. This code is not as efficient
131 as TARGET_FRW, because it has one less allocatable register. */
132 /* This is not a user selectable option yet, because it requires changes
133 that are not yet switchable via command line arguments. */
134 #define TARGET_FRW_COMPAT (target_flags & 512)
136 /* Macro to define tables used to set the flags.
137 This is a list in braces of pairs in braces,
138 each pair being { "NAME", VALUE }
139 where VALUE is the bits to set or minus the bits to clear.
140 An empty string NAME is used to identify the default VALUE. */
142 #define TARGET_SWITCHES \
146 {"soft-float", -1}, \
148 {"no-epilogue", -2}, \
149 {"unaligned-doubles", 4}, \
150 {"no-unaligned-doubles", -4},\
153 {"sparclite", 128}, \
155 {"no-sparclite", -128}, \
156 {"no-sparclite", 1}, \
157 /* {"frw", 256}, */ \
158 /* {"no-frw", -256}, */ \
159 /* {"frw-compat", 256+512}, */ \
160 /* {"no-frw-compat", -(256+512)}, */ \
162 { "", TARGET_DEFAULT}}
164 #define TARGET_DEFAULT 3
166 /* This is meant to be redefined in the host dependent files */
167 #define SUBTARGET_SWITCHES
169 /* target machine storage layout */
172 /* ??? This fails because REAL_VALUE_TYPE is `double' making it impossible to
173 represent and output `long double' constants. This causes problems during
174 a bootstrap with enquire/float.h, and hence must be disabled for now.
175 To fix, we need to implement code for TFmode just like the existing XFmode
176 support in real.[ch]. */
177 /* Define for support of TFmode long double and REAL_ARITHMETIC.
178 Sparc ABI says that long double is 4 words. */
179 #define LONG_DOUBLE_TYPE_SIZE 128
182 /* Define for cross-compilation to a sparc target with no TFmode from a host
183 with a different float format (e.g. VAX). */
184 #define REAL_ARITHMETIC
186 /* Define this if most significant bit is lowest numbered
187 in instructions that operate on numbered bit-fields. */
188 #define BITS_BIG_ENDIAN 1
190 /* Define this if most significant byte of a word is the lowest numbered. */
191 /* This is true on the SPARC. */
192 #define BYTES_BIG_ENDIAN 1
194 /* Define this if most significant word of a multiword number is the lowest
196 /* Doubles are stored in memory with the high order word first. This
197 matters when cross-compiling. */
198 #define WORDS_BIG_ENDIAN 1
200 /* number of bits in an addressable storage unit */
201 #define BITS_PER_UNIT 8
203 /* Width in bits of a "word", which is the contents of a machine register.
204 Note that this is not necessarily the width of data type `int';
205 if using 16-bit ints on a 68000, this would still be 32.
206 But on a machine with 16-bit registers, this would be 16. */
207 #define BITS_PER_WORD 32
208 #define MAX_BITS_PER_WORD 32
210 /* Width of a word, in units (bytes). */
211 #define UNITS_PER_WORD 4
213 /* Width in bits of a pointer.
214 See also the macro `Pmode' defined below. */
215 #define POINTER_SIZE 32
217 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
218 #define PARM_BOUNDARY 32
220 /* Boundary (in *bits*) on which stack pointer should be aligned. */
221 #define STACK_BOUNDARY 64
223 /* ALIGN FRAMES on double word boundaries */
225 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
227 /* Allocation boundary (in *bits*) for the code of a function. */
228 #define FUNCTION_BOUNDARY 32
230 /* Alignment of field after `int : 0' in a structure. */
231 #define EMPTY_FIELD_BOUNDARY 32
233 /* Every structure's size must be a multiple of this. */
234 #define STRUCTURE_SIZE_BOUNDARY 8
236 /* A bitfield declared as `int' forces `int' alignment for the struct. */
237 #define PCC_BITFIELD_TYPE_MATTERS 1
239 /* No data type wants to be aligned rounder than this. */
240 #define BIGGEST_ALIGNMENT 64
242 /* The best alignment to use in cases where we have a choice. */
243 #define FASTEST_ALIGNMENT 64
245 /* Make strings word-aligned so strcpy from constants will be faster. */
246 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
247 ((TREE_CODE (EXP) == STRING_CST \
248 && (ALIGN) < FASTEST_ALIGNMENT) \
249 ? FASTEST_ALIGNMENT : (ALIGN))
251 /* Make arrays of chars word-aligned for the same reasons. */
252 #define DATA_ALIGNMENT(TYPE, ALIGN) \
253 (TREE_CODE (TYPE) == ARRAY_TYPE \
254 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
255 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
257 /* Set this nonzero if move instructions will actually fail to work
258 when given unaligned data. */
259 #define STRICT_ALIGNMENT 1
261 /* Things that must be doubleword aligned cannot go in the text section,
262 because the linker fails to align the text section enough!
263 Put them in the data section. */
264 #define MAX_TEXT_ALIGN 32
266 #define SELECT_SECTION(T,RELOC) \
268 if (TREE_CODE (T) == VAR_DECL) \
270 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
271 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
272 && ! (flag_pic && (RELOC))) \
277 else if (TREE_CODE (T) == CONSTRUCTOR) \
279 if (flag_pic != 0 && (RELOC) != 0) \
282 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
284 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
285 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
292 /* Use text section for a constant
293 unless we need more alignment than that offers. */
294 #define SELECT_RTX_SECTION(MODE, X) \
296 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
297 && ! (flag_pic && symbolic_operand (X))) \
303 /* Standard register usage. */
305 /* Number of actual hardware registers.
306 The hardware registers are assigned numbers for the compiler
307 from 0 to just below FIRST_PSEUDO_REGISTER.
308 All registers that the compiler knows about must be given numbers,
309 even those that are not normally considered general registers.
311 SPARC has 32 integer registers and 32 floating point registers. */
313 #define FIRST_PSEUDO_REGISTER 64
315 /* 1 for registers that have pervasive standard uses
316 and are not available for the register allocator.
317 g0 is used for the condition code and not to represent %g0, which is
318 hardwired to 0, so reg 0 is *not* fixed.
319 g1 through g4 are free to use as temporaries.
320 g5 through g7 are reserved for the operating system. */
321 #define FIXED_REGISTERS \
322 {0, 0, 0, 0, 0, 1, 1, 1, \
323 0, 0, 0, 0, 0, 0, 1, 0, \
324 0, 0, 0, 0, 0, 0, 0, 0, \
325 0, 0, 0, 0, 0, 0, 1, 1, \
327 0, 0, 0, 0, 0, 0, 0, 0, \
328 0, 0, 0, 0, 0, 0, 0, 0, \
329 0, 0, 0, 0, 0, 0, 0, 0, \
330 0, 0, 0, 0, 0, 0, 0, 0}
332 /* 1 for registers not available across function calls.
333 These must include the FIXED_REGISTERS and also any
334 registers that can be used without being saved.
335 The latter must include the registers where values are returned
336 and the register where structure-value addresses are passed.
337 Aside from that, you can include as many other registers as you like. */
338 #define CALL_USED_REGISTERS \
339 {1, 1, 1, 1, 1, 1, 1, 1, \
340 1, 1, 1, 1, 1, 1, 1, 1, \
341 0, 0, 0, 0, 0, 0, 0, 0, \
342 0, 0, 0, 0, 0, 0, 1, 1, \
344 1, 1, 1, 1, 1, 1, 1, 1, \
345 1, 1, 1, 1, 1, 1, 1, 1, \
346 1, 1, 1, 1, 1, 1, 1, 1, \
347 1, 1, 1, 1, 1, 1, 1, 1}
349 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
352 #define CONDITIONAL_REGISTER_USAGE \
358 for (regno = 32; regno < 64; regno++) \
359 fixed_regs[regno] = 1; \
364 /* Return number of consecutive hard regs needed starting at reg REGNO
365 to hold something of mode MODE.
366 This is ordinarily the length in words of a value of mode MODE
367 but can be less for certain modes in special long registers.
369 On SPARC, ordinary registers hold 32 bits worth;
370 this means both integer and floating point registers.
372 We use vectors to keep this information about registers. */
374 /* How many hard registers it takes to make a register of this mode. */
375 extern int hard_regno_nregs[];
377 #define HARD_REGNO_NREGS(REGNO, MODE) \
378 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
380 /* Value is 1 if register/mode pair is acceptable on sparc. */
381 extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
383 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
384 On SPARC, the cpu registers can hold any mode but the float registers
385 can only hold SFmode or DFmode. See sparc.c for how we
387 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
388 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
390 /* Value is 1 if it is a good idea to tie two pseudo registers
391 when one has mode MODE1 and one has mode MODE2.
392 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
393 for any hard reg, then this must be 0 for correct output. */
394 #define MODES_TIEABLE_P(MODE1, MODE2) \
395 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
397 /* Specify the registers used for certain standard purposes.
398 The values of these macros are register numbers. */
400 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
401 /* #define PC_REGNUM */
403 /* Register to use for pushing function arguments. */
404 #define STACK_POINTER_REGNUM 14
406 /* Actual top-of-stack address is 92 greater than the contents
407 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
408 for the ins and local registers, 4 byte for structure return address, and
409 24 bytes for the 6 register parameters. */
410 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
412 /* Base register for access to local variables of the function. */
413 #define FRAME_POINTER_REGNUM 30
416 /* Register that is used for the return address. */
417 #define RETURN_ADDR_REGNUM 15
420 /* Value should be nonzero if functions must have frame pointers.
421 Zero means the frame pointer need not be set up (and parms
422 may be accessed via the stack pointer) in functions that seem suitable.
423 This is computed in `reload', in reload1.c.
425 Used in flow.c, global.c, and reload1.c. */
426 extern int leaf_function;
428 #define FRAME_POINTER_REQUIRED \
429 (! (leaf_function_p () && only_leaf_regs_used ()))
431 /* C statement to store the difference between the frame pointer
432 and the stack pointer values immediately after the function prologue.
434 Note, we always pretend that this is a leaf function because if
435 it's not, there's no point in trying to eliminate the
436 frame pointer. If it is a leaf function, we guessed right! */
437 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
438 ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \
439 : compute_frame_size (get_frame_size (), 1)))
441 /* Base register for access to arguments of the function. */
442 #define ARG_POINTER_REGNUM 30
444 /* Register in which static-chain is passed to a function. */
446 #define STATIC_CHAIN_REGNUM 1
448 /* Register which holds offset table for position-independent
451 #define PIC_OFFSET_TABLE_REGNUM 23
453 #define INITIALIZE_PIC initialize_pic ()
454 #define FINALIZE_PIC finalize_pic ()
456 /* Sparc ABI says that quad-precision floats and all structures are returned
458 #define RETURN_IN_MEMORY(TYPE) \
459 (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
461 /* Functions which return large structures get the address
462 to place the wanted value at offset 64 from the frame.
463 Must reserve 64 bytes for the in and local registers. */
464 /* Used only in other #defines in this file. */
465 #define STRUCT_VALUE_OFFSET 64
467 #define STRUCT_VALUE \
468 gen_rtx (MEM, Pmode, \
469 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
470 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
471 #define STRUCT_VALUE_INCOMING \
472 gen_rtx (MEM, Pmode, \
473 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
474 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
476 /* Define the classes of registers for register constraints in the
477 machine description. Also define ranges of constants.
479 One of the classes must always be named ALL_REGS and include all hard regs.
480 If there is more than one class, another class must be named NO_REGS
481 and contain no registers.
483 The name GENERAL_REGS must be the name of a class (or an alias for
484 another name such as ALL_REGS). This is the class of registers
485 that is allowed by "g" or "r" in a register constraint.
486 Also, registers outside this class are allocated only when
487 instructions express preferences for them.
489 The classes must be numbered in nondecreasing order; that is,
490 a larger-numbered class must never be contained completely
491 in a smaller-numbered class.
493 For any two classes, it is very desirable that there be another
494 class that represents their union. */
496 /* The SPARC has two kinds of registers, general and floating point. */
498 enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
500 #define N_REG_CLASSES (int) LIM_REG_CLASSES
502 /* Give names of register classes as strings for dump file. */
504 #define REG_CLASS_NAMES \
505 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
507 /* Define which registers fit in which classes.
508 This is an initializer for a vector of HARD_REG_SET
509 of length N_REG_CLASSES. */
511 #if 0 && defined (__GNUC__)
512 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
514 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
517 /* The same information, inverted:
518 Return the class number of the smallest class containing
519 reg number REGNO. This could be a conditional expression
520 or could index an array. */
522 #define REGNO_REG_CLASS(REGNO) \
523 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
525 /* This is the order in which to allocate registers
528 We put %f0/%f1 last among the float registers, so as to make it more
529 likely that a pseduo-register which dies in the float return register
530 will get allocated to the float return register, thus saving a move
531 instruction at the end of the function. */
532 #define REG_ALLOC_ORDER \
533 { 8, 9, 10, 11, 12, 13, 2, 3, \
534 15, 16, 17, 18, 19, 20, 21, 22, \
535 23, 24, 25, 26, 27, 28, 29, 31, \
536 34, 35, 36, 37, 38, 39, \
537 40, 41, 42, 43, 44, 45, 46, 47, \
538 48, 49, 50, 51, 52, 53, 54, 55, \
539 56, 57, 58, 59, 60, 61, 62, 63, \
541 1, 4, 5, 6, 7, 0, 14, 30}
543 /* This is the order in which to allocate registers for
544 leaf functions. If all registers can fit in the "i" registers,
545 then we have the possibility of having a leaf function. */
546 #define REG_LEAF_ALLOC_ORDER \
547 { 2, 3, 24, 25, 26, 27, 28, 29, \
548 15, 8, 9, 10, 11, 12, 13, \
549 16, 17, 18, 19, 20, 21, 22, 23, \
550 34, 35, 36, 37, 38, 39, \
551 40, 41, 42, 43, 44, 45, 46, 47, \
552 48, 49, 50, 51, 52, 53, 54, 55, \
553 56, 57, 58, 59, 60, 61, 62, 63, \
555 1, 4, 5, 6, 7, 0, 14, 30, 31}
557 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
559 #define LEAF_REGISTERS \
560 { 1, 1, 1, 1, 1, 1, 1, 1, \
561 0, 0, 0, 0, 0, 0, 1, 0, \
562 0, 0, 0, 0, 0, 0, 0, 0, \
563 1, 1, 1, 1, 1, 1, 0, 1, \
564 1, 1, 1, 1, 1, 1, 1, 1, \
565 1, 1, 1, 1, 1, 1, 1, 1, \
566 1, 1, 1, 1, 1, 1, 1, 1, \
567 1, 1, 1, 1, 1, 1, 1, 1}
569 extern char leaf_reg_remap[];
570 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
571 extern char leaf_reg_backmap[];
572 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
574 /* The class value for index registers, and the one for base regs. */
575 #define INDEX_REG_CLASS GENERAL_REGS
576 #define BASE_REG_CLASS GENERAL_REGS
578 /* Get reg_class from a letter such as appears in the machine description. */
580 #define REG_CLASS_FROM_LETTER(C) \
581 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
583 /* The letters I, J, K, L and M in a register constraint string
584 can be used to stand for particular ranges of immediate operands.
585 This macro defines what the ranges are.
586 C is the letter, and VALUE is a constant value.
587 Return 1 if VALUE is in the range specified by C.
589 For SPARC, `I' is used for the range of constants an insn
590 can actually contain.
591 `J' is used for the range which is just zero (since that is R0).
592 `K' is used for constants which can be loaded with a single sethi insn. */
594 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
596 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
597 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
598 : (C) == 'J' ? (VALUE) == 0 \
599 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
602 /* Similar, but for floating constants, and defining letters G and H.
603 Here VALUE is the CONST_DOUBLE rtx itself. */
605 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
606 ((C) == 'G' ? fp_zero_operand (VALUE) \
607 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
610 /* Given an rtx X being reloaded into a reg required to be
611 in class CLASS, return the class of reg to actually use.
612 In general this is just CLASS; but on some machines
613 in some cases it is preferable to use a more restrictive class. */
614 /* We can't load constants into FP registers. We can't load any FP constant
615 if an 'E' constraint fails to match it. */
616 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
618 && ((CLASS) == FP_REGS \
619 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
620 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
621 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
624 /* Return the register class of a scratch register needed to load IN into
625 a register of class CLASS in MODE.
627 On the SPARC, when PIC, we need a temporary when loading some addresses
630 Also, we need a temporary when loading/storing a HImode/QImode value
631 between memory and the FPU registers. This can happen when combine puts
632 a paradoxical subreg in a float/fix conversion insn. */
634 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
635 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS \
636 : ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
637 && (GET_CODE (IN) == MEM \
638 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
639 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
641 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
642 ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
643 && (GET_CODE (IN) == MEM \
644 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
645 && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
647 /* On SPARC it is not possible to directly move data between
648 GENERAL_REGS and FP_REGS. */
649 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
650 (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
651 || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
653 /* Return the stack location to use for secondary memory needed reloads. */
654 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
655 gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
656 GEN_INT (STARTING_FRAME_OFFSET)))
658 /* Return the maximum number of consecutive registers
659 needed to represent mode MODE in a register of class CLASS. */
660 /* On SPARC, this is the size of MODE in words. */
661 #define CLASS_MAX_NREGS(CLASS, MODE) \
662 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
664 /* Stack layout; function entry, exit and calling. */
666 /* Define the number of register that can hold parameters.
667 These two macros are used only in other macro definitions below. */
670 /* Define this if pushing a word on the stack
671 makes the stack pointer a smaller address. */
672 #define STACK_GROWS_DOWNWARD
674 /* Define this if the nominal address of the stack frame
675 is at the high-address end of the local variables;
676 that is, each additional local variable allocated
677 goes at a more negative offset in the frame. */
678 #define FRAME_GROWS_DOWNWARD
680 /* Offset within stack frame to start allocating local variables at.
681 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
682 first local allocated. Otherwise, it is the offset to the BEGINNING
683 of the first local allocated. */
684 /* This is 16 to allow space for one TFmode floating point value. */
685 #define STARTING_FRAME_OFFSET (-16)
687 /* If we generate an insn to push BYTES bytes,
688 this says how many the stack pointer really advances by.
689 On SPARC, don't define this because there are no push insns. */
690 /* #define PUSH_ROUNDING(BYTES) */
692 /* Offset of first parameter from the argument pointer register value.
693 This is 64 for the ins and locals, plus 4 for the struct-return reg
694 even if this function isn't going to use it. */
695 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
697 /* When a parameter is passed in a register, stack space is still
699 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
701 /* Keep the stack pointer constant throughout the function.
702 This is both an optimization and a necessity: longjmp
703 doesn't behave itself when the stack pointer moves within
705 #define ACCUMULATE_OUTGOING_ARGS
707 /* Value is the number of bytes of arguments automatically
708 popped when returning from a subroutine call.
709 FUNTYPE is the data type of the function (as a tree),
710 or for a library call it is an identifier node for the subroutine name.
711 SIZE is the number of bytes of arguments passed on the stack. */
713 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
715 /* Some subroutine macros specific to this machine.
716 When !TARGET_FPU, put float return values in the general registers,
717 since we don't have any fp registers. */
718 #define BASE_RETURN_VALUE_REG(MODE) \
719 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
720 #define BASE_OUTGOING_VALUE_REG(MODE) \
721 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
722 : (TARGET_FRW ? 8 : 24))
723 #define BASE_PASSING_ARG_REG(MODE) (8)
724 #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
726 /* Define this macro if the target machine has "register windows". This
727 C expression returns the register number as seen by the called function
728 corresponding to register number OUT as seen by the calling function.
729 Return OUT if register number OUT is not an outbound register. */
731 #define INCOMING_REGNO(OUT) \
732 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
734 /* Define this macro if the target machine has "register windows". This
735 C expression returns the register number as seen by the calling function
736 corresponding to register number IN as seen by the called function.
737 Return IN if register number IN is not an inbound register. */
739 #define OUTGOING_REGNO(IN) \
740 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
742 /* Define how to find the value returned by a function.
743 VALTYPE is the data type of the value (as a tree).
744 If the precise function being called is known, FUNC is its FUNCTION_DECL;
745 otherwise, FUNC is 0. */
747 /* On SPARC the value is found in the first "output" register. */
749 #define FUNCTION_VALUE(VALTYPE, FUNC) \
750 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
752 /* But the called function leaves it in the first "input" register. */
754 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
755 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
757 /* Define how to find the value returned by a library function
758 assuming the value has mode MODE. */
760 #define LIBCALL_VALUE(MODE) \
761 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
763 /* 1 if N is a possible register number for a function value
764 as seen by the caller.
765 On SPARC, the first "output" reg is used for integer values,
766 and the first floating point register is used for floating point values. */
768 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
770 /* 1 if N is a possible register number for function argument passing.
771 On SPARC, these are the "output" registers. */
773 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
775 /* Define a data type for recording info about an argument list
776 during the scan of that argument list. This data type should
777 hold all necessary information about the function itself
778 and about the args processed so far, enough to enable macros
779 such as FUNCTION_ARG to determine where the next arg should go.
781 On SPARC, this is a single integer, which is a number of words
782 of arguments scanned so far (including the invisible argument,
783 if any, which holds the structure-value-address).
784 Thus 7 or more means all following args should go on the stack. */
786 #define CUMULATIVE_ARGS int
788 #define ROUND_ADVANCE(SIZE) \
789 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
791 /* Initialize a variable CUM of type CUMULATIVE_ARGS
792 for a call to a function whose data type is FNTYPE.
793 For a library call, FNTYPE is 0.
795 On SPARC, the offset always starts at 0: the first parm reg is always
798 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
800 /* Update the data in CUM to advance over an argument
801 of mode MODE and data type TYPE.
802 (TYPE is null for libcalls where that information may not be available.) */
804 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
805 ((CUM) += ((MODE) != BLKmode \
806 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
807 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
809 /* Determine where to put an argument to a function.
810 Value is zero to push the argument on the stack,
811 or a hard register in which to store the argument.
813 MODE is the argument's machine mode.
814 TYPE is the data type of the argument (as a tree).
815 This is null for libcalls where that information may
817 CUM is a variable of type CUMULATIVE_ARGS which gives info about
818 the preceding args and about the function being called.
819 NAMED is nonzero if this argument is a named parameter
820 (otherwise it is an extra parameter matching an ellipsis). */
822 /* On SPARC the first six args are normally in registers
823 and the rest are pushed. Any arg that starts within the first 6 words
824 is at least partially passed in a register unless its data type forbids. */
826 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
827 ((CUM) < NPARM_REGS \
828 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
829 && ((TYPE)==0 || (MODE) != BLKmode \
830 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
831 ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
834 /* Define where a function finds its arguments.
835 This is different from FUNCTION_ARG because of register windows. */
837 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
838 ((CUM) < NPARM_REGS \
839 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
840 && ((TYPE)==0 || (MODE) != BLKmode \
841 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
842 ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
845 /* For an arg passed partly in registers and partly in memory,
846 this is the number of registers used.
847 For args passed entirely in registers or entirely in memory, zero.
848 Any arg that starts in the first 6 regs but won't entirely fit in them
849 needs partial registers on the Sparc. */
851 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
852 ((CUM) < NPARM_REGS \
853 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
854 && ((TYPE)==0 || (MODE) != BLKmode \
855 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
856 && ((CUM) + ((MODE) == BLKmode \
857 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
858 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
859 ? (NPARM_REGS - (CUM)) \
862 /* The SPARC ABI stipulates passing struct arguments (of any size) and
863 quad-precision floats by invisible reference. */
864 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
865 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
866 || TREE_CODE (TYPE) == UNION_TYPE)) \
869 /* Define the information needed to generate branch and scc insns. This is
870 stored from the compare operation. Note that we can't use "rtx" here
871 since it hasn't been defined! */
873 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
875 /* Define the function that build the compare insn for scc and bcc. */
877 extern struct rtx_def *gen_compare_reg ();
879 /* Generate the special assembly code needed to tell the assembler whatever
880 it might need to know about the return value of a function.
882 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
883 information to the assembler relating to peephole optimization (done in
886 #define ASM_DECLARE_RESULT(FILE, RESULT) \
887 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
889 /* Output the label for a function definition. */
891 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
893 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
894 ASM_OUTPUT_LABEL (FILE, NAME); \
897 /* Two views of the size of the current frame. */
898 extern int actual_fsize;
899 extern int apparent_fsize;
901 /* This macro generates the assembly code for function entry.
902 FILE is a stdio stream to output the code to.
903 SIZE is an int: how many units of temporary storage to allocate.
904 Refer to the array `regs_ever_live' to determine which registers
905 to save; `regs_ever_live[I]' is nonzero if register number I
906 is ever used in the function. This macro is responsible for
907 knowing which registers should not be saved even if used. */
909 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
910 of memory. If any fpu reg is used in the function, we allocate
911 such a block here, at the bottom of the frame, just in case it's needed.
913 If this function is a leaf procedure, then we may choose not
914 to do a "save" insn. The decision about whether or not
915 to do this is made in regclass.c. */
917 #define FUNCTION_PROLOGUE(FILE, SIZE) \
918 (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\
919 : output_function_prologue (FILE, SIZE, leaf_function))
921 /* Output assembler code to FILE to increment profiler label # LABELNO
922 for profiling a function entry. */
924 #define FUNCTION_PROFILER(FILE, LABELNO) \
926 fputs ("\tsethi %hi(", (FILE)); \
927 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
928 fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
929 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
930 fputs ("),%o0,%o0\n", (FILE)); \
933 /* Output assembler code to FILE to initialize this source file's
934 basic block profiling info, if that has not already been done. */
935 /* FIXME -- this does not parameterize how it generates labels (like the
936 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
938 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
939 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
940 (LABELNO), (LABELNO))
942 /* Output assembler code to FILE to increment the entry-count for
943 the BLOCKNO'th basic block in this source file. */
945 #define BLOCK_PROFILER(FILE, BLOCKNO) \
947 int blockn = (BLOCKNO); \
948 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
949 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
950 4 * blockn, 4 * blockn, 4 * blockn); \
953 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
954 the stack pointer does not matter. The value is tested only in
955 functions that have frame pointers.
956 No definition is equivalent to always zero. */
958 extern int current_function_calls_alloca;
959 extern int current_function_outgoing_args_size;
961 #define EXIT_IGNORE_STACK \
962 (get_frame_size () != 0 \
963 || current_function_calls_alloca || current_function_outgoing_args_size)
965 /* This macro generates the assembly code for function exit,
966 on machines that need it. If FUNCTION_EPILOGUE is not defined
967 then individual return instructions are generated for each
968 return statement. Args are same as for FUNCTION_PROLOGUE.
970 The function epilogue should not depend on the current stack pointer!
971 It should use the frame pointer only. This is mandatory because
972 of alloca; we also take advantage of it to omit stack adjustments
975 /* This declaration is needed due to traditional/ANSI
976 incompatibilities which cannot be #ifdefed away
977 because they occur inside of macros. Sigh. */
978 extern union tree_node *current_function_decl;
980 #define FUNCTION_EPILOGUE(FILE, SIZE) \
981 (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\
982 : output_function_epilogue (FILE, SIZE, leaf_function))
984 #define DELAY_SLOTS_FOR_EPILOGUE \
985 (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1)
986 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
987 (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
988 : eligible_for_epilogue_delay (trial, slots_filled))
990 /* Output assembler code for a block containing the constant parts
991 of a trampoline, leaving space for the variable parts. */
993 /* On the sparc, the trampoline contains five instructions:
994 sethi #TOP_OF_FUNCTION,%g2
995 or #BOTTOM_OF_FUNCTION,%g2,%g2
996 sethi #TOP_OF_STATIC,%g1
998 or #BOTTOM_OF_STATIC,%g1,%g1 */
999 #define TRAMPOLINE_TEMPLATE(FILE) \
1001 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1002 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1003 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1004 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
1005 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1008 /* Length in units of the trampoline for entering a nested function. */
1010 #define TRAMPOLINE_SIZE 20
1012 /* Emit RTL insns to initialize the variable parts of a trampoline.
1013 FNADDR is an RTX for the address of the function's pure code.
1014 CXT is an RTX for the static chain value for the function.
1016 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
1017 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
1018 (to store insns). This is a bit excessive. Perhaps a different
1019 mechanism would be better here. */
1021 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1023 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1024 size_int (10), 0, 1); \
1025 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1026 size_int (10), 0, 1); \
1027 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1028 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1029 rtx g1_sethi = gen_rtx (HIGH, SImode, \
1030 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1031 rtx g2_sethi = gen_rtx (HIGH, SImode, \
1032 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1033 rtx g1_ori = gen_rtx (HIGH, SImode, \
1034 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1035 rtx g2_ori = gen_rtx (HIGH, SImode, \
1036 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1037 rtx tem = gen_reg_rtx (SImode); \
1038 emit_move_insn (tem, g2_sethi); \
1039 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1040 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1041 emit_move_insn (tem, g2_ori); \
1042 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1043 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1044 emit_move_insn (tem, g1_sethi); \
1045 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1046 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1047 emit_move_insn (tem, g1_ori); \
1048 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1049 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1052 /* Generate necessary RTL for __builtin_saveregs().
1053 ARGLIST is the argument list; see expr.c. */
1054 extern struct rtx_def *sparc_builtin_saveregs ();
1055 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1057 /* Generate RTL to flush the register windows so as to make arbitrary frames
1059 #define SETUP_FRAME_ADDRESSES() \
1060 emit_insn (gen_flush_register_windows ())
1062 /* Given an rtx for the address of a frame,
1063 return an rtx for the address of the word in the frame
1064 that holds the dynamic chain--the previous frame's address. */
1065 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1066 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1068 /* The return address isn't on the stack, it is in a register, so we can't
1069 access it from the current frame pointer. We can access it from the
1070 previous frame pointer though by reading a value from the register window
1072 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1074 /* The current return address is in %i7. The return address of anything
1075 farther back is in the register window save area at [%fp+60]. */
1076 /* ??? This ignores the fact that the actual return address is +8 for normal
1077 returns, and +12 for structure returns. */
1078 #define RETURN_ADDR_RTX(count, frame) \
1080 ? gen_rtx (REG, Pmode, 31) \
1081 : copy_to_reg (gen_rtx (MEM, Pmode, \
1082 memory_address (Pmode, plus_constant (frame, 60)))))
1084 /* Addressing modes, and classification of registers for them. */
1086 /* #define HAVE_POST_INCREMENT */
1087 /* #define HAVE_POST_DECREMENT */
1089 /* #define HAVE_PRE_DECREMENT */
1090 /* #define HAVE_PRE_INCREMENT */
1092 /* Macros to check register numbers against specific register classes. */
1094 /* These assume that REGNO is a hard or pseudo reg number.
1095 They give nonzero only if REGNO is a hard reg of the suitable class
1096 or a pseudo reg currently allocated to a suitable hard reg.
1097 Since they use reg_renumber, they are safe only once reg_renumber
1098 has been allocated, which happens in local-alloc.c. */
1100 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1101 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1102 #define REGNO_OK_FOR_BASE_P(REGNO) \
1103 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1104 #define REGNO_OK_FOR_FP_P(REGNO) \
1105 (((REGNO) ^ 0x20) < 32 \
1106 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1108 /* Now macros that check whether X is a register and also,
1109 strictly, whether it is in a specified class.
1111 These macros are specific to the SPARC, and may be used only
1112 in code for printing assembler insns and in conditions for
1113 define_optimization. */
1115 /* 1 if X is an fp register. */
1117 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1119 /* Maximum number of registers that can appear in a valid memory address. */
1121 #define MAX_REGS_PER_ADDRESS 2
1123 /* Recognize any constant value that is a valid address. */
1125 #define CONSTANT_ADDRESS_P(X) \
1126 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1127 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1128 || GET_CODE (X) == HIGH)
1130 /* Nonzero if the constant value X is a legitimate general operand.
1131 Anything can be made to work except floating point constants. */
1133 #define LEGITIMATE_CONSTANT_P(X) \
1134 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1136 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1137 and check its validity for a certain class.
1138 We have two alternate definitions for each of them.
1139 The usual definition accepts all pseudo regs; the other rejects
1140 them unless they have been allocated suitable hard regs.
1141 The symbol REG_OK_STRICT causes the latter definition to be used.
1143 Most source files want to accept pseudo regs in the hope that
1144 they will get allocated to the class that the insn wants them to be in.
1145 Source files for reload pass need to be strict.
1146 After reload, it makes no difference, since pseudo regs have
1147 been eliminated by then. */
1149 /* Optional extra constraints for this machine. Borrowed from romp.h.
1151 For the SPARC, `Q' means that this is a memory operand but not a
1152 symbolic memory operand. Note that an unassigned pseudo register
1153 is such a memory operand. Needed because reload will generate
1154 these things in insns and then not re-recognize the insns, causing
1155 constrain_operands to fail.
1157 `S' handles constraints for calls. */
1159 #ifndef REG_OK_STRICT
1161 /* Nonzero if X is a hard reg that can be used as an index
1162 or if it is a pseudo reg. */
1163 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1164 /* Nonzero if X is a hard reg that can be used as a base reg
1165 or if it is a pseudo reg. */
1166 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1168 #define EXTRA_CONSTRAINT(OP, C) \
1170 ? ((GET_CODE (OP) == MEM \
1171 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1172 && ! symbolic_memory_operand (OP, VOIDmode)) \
1173 || (reload_in_progress && GET_CODE (OP) == REG \
1174 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1176 ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1178 ? (mem_aligned_8 (OP)) \
1180 ? (register_ok_for_ldd (OP)) \
1185 /* Nonzero if X is a hard reg that can be used as an index. */
1186 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1187 /* Nonzero if X is a hard reg that can be used as a base reg. */
1188 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1190 #define EXTRA_CONSTRAINT(OP, C) \
1192 ? (GET_CODE (OP) == REG \
1193 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1194 && reg_renumber[REGNO (OP)] < 0) \
1195 : GET_CODE (OP) == MEM) \
1197 ? (CONSTANT_P (OP) \
1198 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0) \
1199 || strict_memory_address_p (Pmode, OP)) \
1201 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
1203 ? (GET_CODE (OP) == REG \
1204 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
1205 || reg_renumber[REGNO (OP)] > 0) \
1206 && register_ok_for_ldd (OP)) : 0)
1209 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1210 that is a valid memory address for an instruction.
1211 The MODE argument is the machine mode for the MEM expression
1212 that wants to use this address.
1214 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1215 ordinarily. This changes a bit when generating PIC.
1217 If you change this, execute "rm explow.o recog.o reload.o". */
1219 #define RTX_OK_FOR_BASE_P(X) \
1220 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1221 || (GET_CODE (X) == SUBREG \
1222 && GET_CODE (SUBREG_REG (X)) == REG \
1223 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1225 #define RTX_OK_FOR_INDEX_P(X) \
1226 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1227 || (GET_CODE (X) == SUBREG \
1228 && GET_CODE (SUBREG_REG (X)) == REG \
1229 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1231 #define RTX_OK_FOR_OFFSET_P(X) \
1232 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1234 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1235 { if (RTX_OK_FOR_BASE_P (X)) \
1237 else if (GET_CODE (X) == PLUS) \
1239 register rtx op0 = XEXP (X, 0); \
1240 register rtx op1 = XEXP (X, 1); \
1241 if (flag_pic && op0 == pic_offset_table_rtx) \
1243 if (RTX_OK_FOR_BASE_P (op1)) \
1245 else if (flag_pic == 1 \
1246 && GET_CODE (op1) != REG \
1247 && GET_CODE (op1) != LO_SUM \
1248 && GET_CODE (op1) != MEM) \
1251 else if (RTX_OK_FOR_BASE_P (op0)) \
1253 if (RTX_OK_FOR_INDEX_P (op1) \
1254 || RTX_OK_FOR_OFFSET_P (op1)) \
1257 else if (RTX_OK_FOR_BASE_P (op1)) \
1259 if (RTX_OK_FOR_INDEX_P (op0) \
1260 || RTX_OK_FOR_OFFSET_P (op0)) \
1264 else if (GET_CODE (X) == LO_SUM) \
1266 register rtx op0 = XEXP (X, 0); \
1267 register rtx op1 = XEXP (X, 1); \
1268 if (RTX_OK_FOR_BASE_P (op0) \
1269 && CONSTANT_P (op1)) \
1272 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1276 /* Try machine-dependent ways of modifying an illegitimate address
1277 to be legitimate. If we find one, return the new, valid address.
1278 This macro is used in only one place: `memory_address' in explow.c.
1280 OLDX is the address as it was before break_out_memory_refs was called.
1281 In some cases it is useful to look at this to decide what needs to be done.
1283 MODE and WIN are passed so that this macro can use
1284 GO_IF_LEGITIMATE_ADDRESS.
1286 It is always safe for this macro to do nothing. It exists to recognize
1287 opportunities to optimize the output. */
1289 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1290 extern struct rtx_def *legitimize_pic_address ();
1291 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1292 { rtx sparc_x = (X); \
1293 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1294 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1295 force_operand (XEXP (X, 0), NULL_RTX)); \
1296 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1297 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1298 force_operand (XEXP (X, 1), NULL_RTX)); \
1299 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1300 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1302 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1303 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1304 force_operand (XEXP (X, 1), NULL_RTX)); \
1305 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1307 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1308 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1309 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1310 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1311 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1312 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1313 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1314 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1315 || GET_CODE (X) == LABEL_REF) \
1316 (X) = gen_rtx (LO_SUM, Pmode, \
1317 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1318 if (memory_address_p (MODE, X)) \
1321 /* Go to LABEL if ADDR (a legitimate address expression)
1322 has an effect that depends on the machine mode it is used for.
1323 On the SPARC this is never true. */
1325 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1327 /* Specify the machine mode that this machine uses
1328 for the index in the tablejump instruction. */
1329 #define CASE_VECTOR_MODE SImode
1331 /* Define this if the tablejump instruction expects the table
1332 to contain offsets from the address of the table.
1333 Do not define this if the table should contain absolute addresses. */
1334 /* #define CASE_VECTOR_PC_RELATIVE */
1336 /* Specify the tree operation to be used to convert reals to integers. */
1337 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1339 /* This is the kind of divide that is easiest to do in the general case. */
1340 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1342 /* Define this as 1 if `char' should by default be signed; else as 0. */
1343 #define DEFAULT_SIGNED_CHAR 1
1345 /* Max number of bytes we can move from memory to memory
1346 in one reasonably fast instruction. */
1349 #if 0 /* Sun 4 has matherr, so this is no good. */
1350 /* This is the value of the error code EDOM for this machine,
1351 used by the sqrt instruction. */
1352 #define TARGET_EDOM 33
1354 /* This is how to refer to the variable errno. */
1355 #define GEN_ERRNO_RTX \
1356 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1359 /* Define if normal loads of shorter-than-word items from memory clears
1360 the rest of the bigs in the register. */
1361 #define BYTE_LOADS_ZERO_EXTEND
1363 /* Nonzero if access to memory by bytes is slow and undesirable.
1364 For RISC chips, it means that access to memory by bytes is no
1365 better than access by words when possible, so grab a whole word
1366 and maybe make use of that. */
1367 #define SLOW_BYTE_ACCESS 1
1369 /* We assume that the store-condition-codes instructions store 0 for false
1370 and some other value for true. This is the value stored for true. */
1372 #define STORE_FLAG_VALUE 1
1374 /* When a prototype says `char' or `short', really pass an `int'. */
1375 #define PROMOTE_PROTOTYPES
1377 /* Define if shifts truncate the shift count
1378 which implies one can omit a sign-extension or zero-extension
1379 of a shift count. */
1380 #define SHIFT_COUNT_TRUNCATED
1382 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1383 is done just by pretending it is already truncated. */
1384 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1386 /* Specify the machine mode that pointers have.
1387 After generation of rtl, the compiler makes no further distinction
1388 between pointers and any other objects of this machine mode. */
1389 #define Pmode SImode
1391 /* Generate calls to memcpy, memcmp and memset. */
1392 #define TARGET_MEM_FUNCTIONS
1394 /* Add any extra modes needed to represent the condition code.
1396 On the Sparc, we have a "no-overflow" mode which is used when an add or
1397 subtract insn is used to set the condition code. Different branches are
1398 used in this case for some operations.
1400 We also have two modes to indicate that the relevant condition code is
1401 in the floating-point condition code register. One for comparisons which
1402 will generate an exception if the result is unordered (CCFPEmode) and
1403 one for comparisons which will never trap (CCFPmode). This really should
1404 be a separate register, but we don't want to go to 65 registers. */
1405 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1407 /* Define the names for the modes specified above. */
1408 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1410 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1411 return the mode to be used for the comparison. For floating-point,
1412 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1413 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1415 #define SELECT_CC_MODE(OP,X,Y) \
1416 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1417 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1418 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1419 ? CC_NOOVmode : CCmode))
1421 /* A function address in a call instruction
1422 is a byte address (for indexing purposes)
1423 so give the MEM rtx a byte's mode. */
1424 #define FUNCTION_MODE SImode
1426 /* Define this if addresses of constant functions
1427 shouldn't be put through pseudo regs where they can be cse'd.
1428 Desirable on machines where ordinary constants are expensive
1429 but a CALL with constant address is cheap. */
1430 #define NO_FUNCTION_CSE
1432 /* alloca should avoid clobbering the old register save area. */
1433 #define SETJMP_VIA_SAVE_AREA
1435 /* Define subroutines to call to handle multiply and divide.
1436 Use the subroutines that Sun's library provides.
1437 The `*' prevents an underscore from being prepended by the compiler. */
1439 #define DIVSI3_LIBCALL "*.div"
1440 #define UDIVSI3_LIBCALL "*.udiv"
1441 #define MODSI3_LIBCALL "*.rem"
1442 #define UMODSI3_LIBCALL "*.urem"
1443 /* .umul is a little faster than .mul. */
1444 #define MULSI3_LIBCALL "*.umul"
1446 /* Compute the cost of computing a constant rtl expression RTX
1447 whose rtx-code is CODE. The body of this macro is a portion
1448 of a switch statement. If the code is computed here,
1449 return it with a return statement. Otherwise, break from the switch. */
1451 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1453 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1461 case CONST_DOUBLE: \
1462 if (GET_MODE (RTX) == DImode) \
1463 if ((XINT (RTX, 3) == 0 \
1464 && (unsigned) XINT (RTX, 2) < 0x1000) \
1465 || (XINT (RTX, 3) == -1 \
1466 && XINT (RTX, 2) < 0 \
1467 && XINT (RTX, 2) >= -0x1000)) \
1471 /* SPARC offers addressing modes which are "as cheap as a register".
1472 See sparc.c (or gcc.texinfo) for details. */
1474 #define ADDRESS_COST(RTX) \
1475 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1477 /* Compute extra cost of moving data between one register class
1479 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1480 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1481 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1483 /* Provide the costs of a rtl expression. This is in the body of a
1484 switch on CODE. The purpose for the cost of MULT is to encourage
1485 `synth_mult' to find a synthetic multiply when reasonable.
1487 If we need more than 12 insns to do a multiply, then go out-of-line,
1488 since the call overhead will be < 10% of the cost of the multiply. */
1490 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1492 return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
1497 return COSTS_N_INSNS (25); \
1498 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1499 so that cse will favor the latter. */ \
1504 /* Conditional branches with empty delay slots have a length of two. */
1505 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1506 if (GET_CODE (INSN) == CALL_INSN \
1507 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1510 /* Control the assembler format that we output. */
1512 /* Output at beginning of assembler file. */
1514 #define ASM_FILE_START(file)
1516 /* Output to assembler file text saying following lines
1517 may contain character constants, extra white space, comments, etc. */
1519 #define ASM_APP_ON ""
1521 /* Output to assembler file text saying following lines
1522 no longer contain unusual constructs. */
1524 #define ASM_APP_OFF ""
1526 #define ASM_LONG ".word"
1527 #define ASM_SHORT ".half"
1528 #define ASM_BYTE_OP ".byte"
1530 /* Output before read-only data. */
1532 #define TEXT_SECTION_ASM_OP ".text"
1534 /* Output before writable data. */
1536 #define DATA_SECTION_ASM_OP ".data"
1538 /* How to refer to registers in assembler output.
1539 This sequence is indexed by compiler's hard-register-number (see above). */
1541 #define REGISTER_NAMES \
1542 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1543 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1544 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1545 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1546 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1547 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1548 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1549 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1551 /* Define additional names for use in asm clobbers and asm declarations.
1553 We define the fake Condition Code register as an alias for reg 0 (which
1554 is our `condition code' register), so that condition codes can easily
1555 be clobbered by an asm. No such register actually exists. Condition
1556 codes are partly stored in the PSR and partly in the FSR. */
1558 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1560 /* How to renumber registers for dbx and gdb. */
1562 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1564 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1565 since the length can run past this up to a continuation point. */
1566 #define DBX_CONTIN_LENGTH 1500
1568 /* This is how to output a note to DBX telling it the line number
1569 to which the following sequence of instructions corresponds.
1571 This is needed for SunOS 4.0, and should not hurt for 3.2
1573 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1574 { static int sym_lineno = 1; \
1575 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1576 line, sym_lineno, sym_lineno); \
1579 /* This is how to output the definition of a user-level label named NAME,
1580 such as the label on a static function or variable NAME. */
1582 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1583 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1585 /* This is how to output a command to make the user-level label named NAME
1586 defined for reference from other files. */
1588 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1589 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1591 /* This is how to output a reference to a user-level label named NAME.
1592 `assemble_name' uses this. */
1594 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1595 fprintf (FILE, "_%s", NAME)
1597 /* This is how to output a definition of an internal numbered label where
1598 PREFIX is the class of label and NUM is the number within the class. */
1600 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1601 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1603 /* This is how to output a reference to an internal numbered label where
1604 PREFIX is the class of label and NUM is the number within the class. */
1605 /* FIXME: This should be used throughout gcc, and documented in the texinfo
1606 files. There is no reason you should have to allocate a buffer and
1607 `sprintf' to reference an internal label (as opposed to defining it). */
1609 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1610 fprintf (FILE, "%s%d", PREFIX, NUM)
1612 /* This is how to store into the string LABEL
1613 the symbol_ref name of an internal numbered label where
1614 PREFIX is the class of label and NUM is the number within the class.
1615 This is suitable for output with `assemble_name'. */
1617 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1618 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1620 /* This is how to output an assembler line defining a `double' constant. */
1622 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1625 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1626 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1627 ASM_LONG, t[0], ASM_LONG, t[1]); \
1630 /* This is how to output an assembler line defining a `float' constant. */
1632 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1635 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1636 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1639 /* This is how to output an assembler line defining a `long double'
1642 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1645 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1646 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1647 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1650 /* This is how to output an assembler line defining an `int' constant. */
1652 #define ASM_OUTPUT_INT(FILE,VALUE) \
1653 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1654 output_addr_const (FILE, (VALUE)), \
1655 fprintf (FILE, "\n"))
1657 /* This is how to output an assembler line defining a DImode constant. */
1658 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1659 output_double_int (FILE, VALUE)
1661 /* Likewise for `char' and `short' constants. */
1663 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1664 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1665 output_addr_const (FILE, (VALUE)), \
1666 fprintf (FILE, "\n"))
1668 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1669 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1670 output_addr_const (FILE, (VALUE)), \
1671 fprintf (FILE, "\n"))
1673 /* This is how to output an assembler line for a numeric constant byte. */
1675 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1676 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1678 /* This is how to output an element of a case-vector that is absolute. */
1680 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1683 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1684 fprintf (FILE, "\t.word\t"); \
1685 assemble_name (FILE, label); \
1686 fprintf (FILE, "\n"); \
1689 /* This is how to output an element of a case-vector that is relative.
1690 (SPARC uses such vectors only when generating PIC.) */
1692 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1695 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1696 fprintf (FILE, "\t.word\t"); \
1697 assemble_name (FILE, label); \
1698 fprintf (FILE, "-1b\n"); \
1701 /* This is how to output an assembler line
1702 that says to advance the location counter
1703 to a multiple of 2**LOG bytes. */
1705 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1707 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1709 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1710 fprintf (FILE, "\t.skip %u\n", (SIZE))
1712 /* This says how to output an assembler line
1713 to define a global common symbol. */
1715 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1716 ( fputs ("\t.global ", (FILE)), \
1717 assemble_name ((FILE), (NAME)), \
1718 fputs ("\n\t.common ", (FILE)), \
1719 assemble_name ((FILE), (NAME)), \
1720 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1722 /* This says how to output an assembler line
1723 to define a local common symbol. */
1725 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1726 ( fputs ("\n\t.reserve ", (FILE)), \
1727 assemble_name ((FILE), (NAME)), \
1728 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1730 /* Store in OUTPUT a string (made with alloca) containing
1731 an assembler-name for a local static variable named NAME.
1732 LABELNO is an integer which is different for each call. */
1734 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1735 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1736 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1738 #define IDENT_ASM_OP ".ident"
1740 /* Output #ident as a .ident. */
1742 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1743 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1745 /* Define the parentheses used to group arithmetic operations
1746 in assembler code. */
1748 #define ASM_OPEN_PAREN "("
1749 #define ASM_CLOSE_PAREN ")"
1751 /* Define results of standard character escape sequences. */
1752 #define TARGET_BELL 007
1753 #define TARGET_BS 010
1754 #define TARGET_TAB 011
1755 #define TARGET_NEWLINE 012
1756 #define TARGET_VT 013
1757 #define TARGET_FF 014
1758 #define TARGET_CR 015
1760 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1761 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1763 /* Print operand X (an rtx) in assembler syntax to file FILE.
1764 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1765 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1767 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1769 /* Print a memory address as an operand to reference that memory location. */
1771 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1772 { register rtx base, index = 0; \
1774 register rtx addr = ADDR; \
1775 if (GET_CODE (addr) == REG) \
1776 fputs (reg_names[REGNO (addr)], FILE); \
1777 else if (GET_CODE (addr) == PLUS) \
1779 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1780 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1781 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1782 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1784 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1785 fputs (reg_names[REGNO (base)], FILE); \
1787 fprintf (FILE, "%+d", offset); \
1788 else if (GET_CODE (index) == REG) \
1789 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1790 else if (GET_CODE (index) == SYMBOL_REF) \
1791 fputc ('+', FILE), output_addr_const (FILE, index); \
1794 else if (GET_CODE (addr) == MINUS \
1795 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1797 output_addr_const (FILE, XEXP (addr, 0)); \
1798 fputs ("-(", FILE); \
1799 output_addr_const (FILE, XEXP (addr, 1)); \
1800 fputs ("-.)", FILE); \
1802 else if (GET_CODE (addr) == LO_SUM) \
1804 output_operand (XEXP (addr, 0), 0); \
1805 fputs ("+%lo(", FILE); \
1806 output_address (XEXP (addr, 1)); \
1807 fputc (')', FILE); \
1809 else if (flag_pic && GET_CODE (addr) == CONST \
1810 && GET_CODE (XEXP (addr, 0)) == MINUS \
1811 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1812 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1813 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1815 addr = XEXP (addr, 0); \
1816 output_addr_const (FILE, XEXP (addr, 0)); \
1817 /* Group the args of the second CONST in parenthesis. */ \
1818 fputs ("-(", FILE); \
1819 /* Skip past the second CONST--it does nothing for us. */\
1820 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1821 /* Close the parenthesis. */ \
1822 fputc (')', FILE); \
1826 output_addr_const (FILE, addr); \
1830 /* Declare functions defined in sparc.c and used in templates. */
1832 extern char *singlemove_string ();
1833 extern char *output_move_double ();
1834 extern char *output_move_quad ();
1835 extern char *output_fp_move_double ();
1836 extern char *output_fp_move_quad ();
1837 extern char *output_block_move ();
1838 extern char *output_scc_insn ();
1839 extern char *output_cbranch ();
1840 extern char *output_return ();
1842 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1844 extern int flag_pic;