1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Define macros to distinguish architectures. */
215 /* Common CPP definitions used by CPP_SPEC amongst the various targets
216 for handling -mcpu=xxx switches. */
217 #define CPP_CPU_SPEC "\
218 %{msoft-float:-D_SOFT_FLOAT} \
220 %{msparclite:-D__sparclite__} \
221 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
222 %{mv8:-D__sparc_v8__} \
223 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
224 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
225 %{mcpu=sparclite:-D__sparclite__} \
226 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
227 %{mcpu=v8:-D__sparc_v8__} \
228 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
229 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclite86x:-D__sparclite86x__} \
231 %{mcpu=v9:-D__sparc_v9__} \
232 %{mcpu=ultrasparc:-D__sparc_v9__} \
233 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
236 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
237 the right varags.h file when bootstrapping. */
238 /* ??? It's not clear what value we want to use for -Acpu/machine for
239 sparc64 in 32 bit environments, so for now we only use `sparc64' in
240 64 bit environments. */
244 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
245 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
246 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
247 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
251 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
252 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
256 #define CPP_ARCH_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
259 #define CPP_ARCH_SPEC "\
260 %{m32:%(cpp_arch32)} \
261 %{m64:%(cpp_arch64)} \
262 %{!m32:%{!m64:%(cpp_arch_default)}} \
265 /* Macros to distinguish endianness. */
266 #define CPP_ENDIAN_SPEC "\
267 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
268 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
270 /* Macros to distinguish the particular subtarget. */
271 #define CPP_SUBTARGET_SPEC ""
273 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
275 /* Prevent error on `-sun4' and `-target sun4' options. */
276 /* This used to translate -dalign to -malign, but that is no good
277 because it can't turn off the usual meaning of making debugging dumps. */
278 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
279 ??? Delete support for -m<cpu> for 2.9. */
282 %{sun4:} %{target:} \
283 %{mcypress:-mcpu=cypress} \
284 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
285 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
288 /* Override in target specific files. */
289 #define ASM_CPU_SPEC "\
290 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
291 %{msparclite:-Asparclite} \
292 %{mf930:-Asparclite} %{mf934:-Asparclite} \
293 %{mcpu=sparclite:-Asparclite} \
294 %{mcpu=sparclite86x:-Asparclite} \
295 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
296 %{mv8plus:-Av8plus} \
298 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
299 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
302 /* Word size selection, among other things.
303 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
305 #define ASM_ARCH32_SPEC "-32"
306 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
307 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
309 #define ASM_ARCH64_SPEC "-64"
311 #define ASM_ARCH_DEFAULT_SPEC \
312 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
314 #define ASM_ARCH_SPEC "\
315 %{m32:%(asm_arch32)} \
316 %{m64:%(asm_arch64)} \
317 %{!m32:%{!m64:%(asm_arch_default)}} \
320 #ifdef HAVE_AS_RELAX_OPTION
321 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
323 #define ASM_RELAX_SPEC ""
326 /* Special flags to the Sun-4 assembler when using pipe for input. */
329 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
330 %(asm_cpu) %(asm_relax)"
332 /* This macro defines names of additional specifications to put in the specs
333 that can be used in various specifications like CC1_SPEC. Its definition
334 is an initializer with a subgrouping for each command option.
336 Each subgrouping contains a string constant, that defines the
337 specification name, and a string constant that used by the GNU CC driver
340 Do not define this macro if it does not need to do anything. */
342 #define EXTRA_SPECS \
343 { "cpp_cpu", CPP_CPU_SPEC }, \
344 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
345 { "cpp_arch32", CPP_ARCH32_SPEC }, \
346 { "cpp_arch64", CPP_ARCH64_SPEC }, \
347 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
348 { "cpp_arch", CPP_ARCH_SPEC }, \
349 { "cpp_endian", CPP_ENDIAN_SPEC }, \
350 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
351 { "asm_cpu", ASM_CPU_SPEC }, \
352 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
353 { "asm_arch32", ASM_ARCH32_SPEC }, \
354 { "asm_arch64", ASM_ARCH64_SPEC }, \
355 { "asm_relax", ASM_RELAX_SPEC }, \
356 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
357 { "asm_arch", ASM_ARCH_SPEC }, \
358 SUBTARGET_EXTRA_SPECS
360 #define SUBTARGET_EXTRA_SPECS
362 /* Because libgcc can generate references back to libc (via .umul etc.) we have
363 to list libc again after the second libgcc. */
364 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
368 #define NO_BUILTIN_PTRDIFF_TYPE
369 #define NO_BUILTIN_SIZE_TYPE
371 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
372 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
374 /* ??? This should be 32 bits for v9 but what can we do? */
375 #define WCHAR_TYPE "short unsigned int"
376 #define WCHAR_TYPE_SIZE 16
378 /* Show we can debug even without a frame pointer. */
379 #define CAN_DEBUG_WITHOUT_FP
381 #define OVERRIDE_OPTIONS sparc_override_options ()
383 /* Generate DBX debugging information. */
385 #define DBX_DEBUGGING_INFO
387 /* Run-time compilation parameters selecting different hardware subsets. */
389 extern int target_flags;
391 /* Nonzero if we should generate code to use the fpu. */
393 #define TARGET_FPU (target_flags & MASK_FPU)
395 /* Nonzero if we should assume that double pointers might be unaligned.
396 This can happen when linking gcc compiled code with other compilers,
397 because the ABI only guarantees 4 byte alignment. */
398 #define MASK_UNALIGNED_DOUBLES 4
399 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
401 /* Nonzero means that we should generate code for a v8 sparc. */
403 #define TARGET_V8 (target_flags & MASK_V8)
405 /* Nonzero means that we should generate code for a sparclite.
406 This enables the sparclite specific instructions, but does not affect
407 whether FPU instructions are emitted. */
408 #define MASK_SPARCLITE 0x10
409 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
411 /* Nonzero if we're compiling for the sparclet. */
412 #define MASK_SPARCLET 0x20
413 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
415 /* Nonzero if we're compiling for v9 sparc.
416 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
417 the word size is 64. */
419 #define TARGET_V9 (target_flags & MASK_V9)
421 /* Non-zero to generate code that uses the instructions deprecated in
422 the v9 architecture. This option only applies to v9 systems. */
423 /* ??? This isn't user selectable yet. It's used to enable such insns
424 on 32 bit v9 systems and for the moment they're permanently disabled
425 on 64 bit v9 systems. */
426 #define MASK_DEPRECATED_V8_INSNS 0x80
427 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
429 /* Mask of all CPU selection flags. */
431 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
433 /* Non-zero means don't pass `-assert pure-text' to the linker. */
434 #define MASK_IMPURE_TEXT 0x100
435 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
437 /* Nonzero means that we should generate code using a flat register window
438 model, i.e. no save/restore instructions are generated, which is
439 compatible with normal sparc code.
440 The frame pointer is %i7 instead of %fp. */
441 #define MASK_FLAT 0x200
442 #define TARGET_FLAT (target_flags & MASK_FLAT)
444 /* Nonzero means use the registers that the Sparc ABI reserves for
445 application software. This must be the default to coincide with the
446 setting in FIXED_REGISTERS. */
447 #define MASK_APP_REGS 0x400
448 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
450 /* Option to select how quad word floating point is implemented.
451 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
452 Otherwise, we use the SPARC ABI quad library functions. */
453 #define MASK_HARD_QUAD 0x800
454 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
456 /* Non-zero on little-endian machines. */
457 /* ??? Little endian support currently only exists for sparclet-aout and
458 sparc64-elf configurations. May eventually want to expand the support
459 to all targets, but for now it's kept local to only those two. */
460 #define MASK_LITTLE_ENDIAN 0x1000
461 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
463 /* 0x2000, 0x4000 are unused */
465 /* Nonzero if pointers are 64 bits. */
466 #define MASK_PTR64 0x8000
467 #define TARGET_PTR64 (target_flags & MASK_PTR64)
469 /* Nonzero if generating code to run in a 64 bit environment.
470 This is intended to only be used by TARGET_ARCH{32,64} as they are the
471 mechanism used to control compile time or run time selection. */
472 #define MASK_64BIT 0x10000
473 #define TARGET_64BIT (target_flags & MASK_64BIT)
475 /* 0x20000,0x40000 unused */
477 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
478 adding 2047 to %sp. This option is for v9 only and is the default. */
479 #define MASK_STACK_BIAS 0x80000
480 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
482 /* 0x100000,0x200000 unused */
484 /* Non-zero means -m{,no-}fpu was passed on the command line. */
485 #define MASK_FPU_SET 0x400000
486 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
488 /* Use the UltraSPARC Visual Instruction Set extensions. */
489 #define MASK_VIS 0x1000000
490 #define TARGET_VIS (target_flags & MASK_VIS)
492 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
493 the current out and global registers and Linux 2.2+ as well. */
494 #define MASK_V8PLUS 0x2000000
495 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
497 /* Force a the fastest alignment on structures to take advantage of
499 #define MASK_FASTER_STRUCTS 0x4000000
500 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
502 /* Use IEEE quad long double. */
503 #define MASK_LONG_DOUBLE_128 0x8000000
504 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
506 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
507 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
508 to get high 32 bits. False in V8+ or V9 because multiply stores
509 a 64 bit result in a register. */
511 #define TARGET_HARD_MUL32 \
512 ((TARGET_V8 || TARGET_SPARCLITE \
513 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
514 && ! TARGET_V8PLUS && TARGET_ARCH32)
516 #define TARGET_HARD_MUL \
517 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
518 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
521 /* Macro to define tables used to set the flags.
522 This is a list in braces of pairs in braces,
523 each pair being { "NAME", VALUE }
524 where VALUE is the bits to set or minus the bits to clear.
525 An empty string NAME is used to identify the default VALUE. */
527 #define TARGET_SWITCHES \
528 { {"fpu", MASK_FPU | MASK_FPU_SET, \
529 N_("Use hardware fp") }, \
530 {"no-fpu", -MASK_FPU, \
531 N_("Do not use hardware fp") }, \
532 {"no-fpu", MASK_FPU_SET, NULL, }, \
533 {"hard-float", MASK_FPU | MASK_FPU_SET, \
534 N_("Use hardware fp") }, \
535 {"soft-float", -MASK_FPU, \
536 N_("Do not use hardware fp") }, \
537 {"soft-float", MASK_FPU_SET, NULL }, \
538 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
539 N_("Assume possible double misalignment") }, \
540 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
541 N_("Assume all doubles are aligned") }, \
542 {"impure-text", MASK_IMPURE_TEXT, \
543 N_("Pass -assert pure-text to linker") }, \
544 {"no-impure-text", -MASK_IMPURE_TEXT, \
545 N_("Do not pass -assert pure-text to linker") }, \
546 {"flat", MASK_FLAT, \
547 N_("Use flat register window model") }, \
548 {"no-flat", -MASK_FLAT, \
549 N_("Do not use flat register window model") }, \
550 {"app-regs", MASK_APP_REGS, \
551 N_("Use ABI reserved registers") }, \
552 {"no-app-regs", -MASK_APP_REGS, \
553 N_("Do not use ABI reserved registers") }, \
554 {"hard-quad-float", MASK_HARD_QUAD, \
555 N_("Use hardware quad fp instructions") }, \
556 {"soft-quad-float", -MASK_HARD_QUAD, \
557 N_("Do not use hardware quad fp instructions") }, \
558 {"v8plus", MASK_V8PLUS, \
559 N_("Compile for v8plus ABI") }, \
560 {"no-v8plus", -MASK_V8PLUS, \
561 N_("Do not compile for v8plus ABI") }, \
563 N_("Utilize Visual Instruction Set") }, \
564 {"no-vis", -MASK_VIS, \
565 N_("Do not utilize Visual Instruction Set") }, \
566 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
568 N_("Optimize for Cypress processors") }, \
570 N_("Optimize for SparcLite processors") }, \
572 N_("Optimize for F930 processors") }, \
574 N_("Optimize for F934 processors") }, \
576 N_("Use V8 Sparc ISA") }, \
578 N_("Optimize for SuperSparc processors") }, \
579 /* End of deprecated options. */ \
580 {"ptr64", MASK_PTR64, \
581 N_("Pointers are 64-bit") }, \
582 {"ptr32", -MASK_PTR64, \
583 N_("Pointers are 32-bit") }, \
584 {"32", -MASK_64BIT, \
585 N_("Use 32-bit ABI") }, \
587 N_("Use 64-bit ABI") }, \
588 {"stack-bias", MASK_STACK_BIAS, \
589 N_("Use stack bias") }, \
590 {"no-stack-bias", -MASK_STACK_BIAS, \
591 N_("Do not use stack bias") }, \
592 {"faster-structs", MASK_FASTER_STRUCTS, \
593 N_("Use structs on stronger alignment for double-word copies") }, \
594 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
595 N_("Do not use structs on stronger alignment for double-word copies") }, \
597 N_("Optimize tail call instructions in assembler and linker") }, \
599 N_("Do not optimize tail call instructions in assembler or linker") }, \
601 { "", TARGET_DEFAULT, ""}}
603 /* MASK_APP_REGS must always be the default because that's what
604 FIXED_REGISTERS is set to and -ffixed- is processed before
605 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
606 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
608 /* This is meant to be redefined in target specific files. */
609 #define SUBTARGET_SWITCHES
612 These must match the values for the cpu attribute in sparc.md. */
613 enum processor_type {
617 PROCESSOR_SUPERSPARC,
621 PROCESSOR_HYPERSPARC,
622 PROCESSOR_SPARCLITE86X,
629 /* This is set from -m{cpu,tune}=xxx. */
630 extern enum processor_type sparc_cpu;
632 /* Recast the cpu class to be the cpu attribute.
633 Every file includes us, but not every file includes insn-attr.h. */
634 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
636 #define TARGET_OPTIONS \
638 { "cpu=", &sparc_select[1].string, \
639 N_("Use features of and schedule code for given CPU") }, \
640 { "tune=", &sparc_select[2].string, \
641 N_("Schedule code for given CPU") }, \
642 { "cmodel=", &sparc_cmodel_string, \
643 N_("Use given Sparc code model") }, \
647 /* This is meant to be redefined in target specific files. */
648 #define SUBTARGET_OPTIONS
650 /* sparc_select[0] is reserved for the default cpu. */
651 struct sparc_cpu_select
654 const char *const name;
655 const int set_tune_p;
656 const int set_arch_p;
659 extern struct sparc_cpu_select sparc_select[];
661 /* target machine storage layout */
663 /* Define this if most significant bit is lowest numbered
664 in instructions that operate on numbered bit-fields. */
665 #define BITS_BIG_ENDIAN 1
667 /* Define this if most significant byte of a word is the lowest numbered. */
668 #define BYTES_BIG_ENDIAN 1
670 /* Define this if most significant word of a multiword number is the lowest
672 #define WORDS_BIG_ENDIAN 1
674 /* Define this to set the endianness to use in libgcc2.c, which can
675 not depend on target_flags. */
676 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
677 #define LIBGCC2_WORDS_BIG_ENDIAN 0
679 #define LIBGCC2_WORDS_BIG_ENDIAN 1
682 #define MAX_BITS_PER_WORD 64
684 /* Width of a word, in units (bytes). */
685 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
687 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
689 #define MIN_UNITS_PER_WORD 4
692 /* Now define the sizes of the C data types. */
694 #define SHORT_TYPE_SIZE 16
695 #define INT_TYPE_SIZE 32
696 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
697 #define LONG_LONG_TYPE_SIZE 64
698 #define FLOAT_TYPE_SIZE 32
699 #define DOUBLE_TYPE_SIZE 64
702 #define MAX_LONG_TYPE_SIZE 64
706 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
707 Instead, it is enabled in sol2.h, because it does work under Solaris. */
708 /* Define for support of TFmode long double.
709 Sparc ABI says that long double is 4 words. */
710 #define LONG_DOUBLE_TYPE_SIZE 128
713 /* Width in bits of a pointer.
714 See also the macro `Pmode' defined below. */
715 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
717 /* If we have to extend pointers (only when TARGET_ARCH64 and not
718 TARGET_PTR64), we want to do it unsigned. This macro does nothing
719 if ptr_mode and Pmode are the same. */
720 #define POINTERS_EXTEND_UNSIGNED 1
722 /* A macro to update MODE and UNSIGNEDP when an object whose type
723 is TYPE and which has the specified mode and signedness is to be
724 stored in a register. This macro is only called when TYPE is a
726 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
728 && GET_MODE_CLASS (MODE) == MODE_INT \
729 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
732 /* Define this macro if the promotion described by PROMOTE_MODE
733 should also be done for outgoing function arguments. */
734 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
735 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
737 #define PROMOTE_FUNCTION_ARGS
739 /* Define this macro if the promotion described by PROMOTE_MODE
740 should also be done for the return value of functions.
741 If this macro is defined, FUNCTION_VALUE must perform the same
742 promotions done by PROMOTE_MODE. */
743 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
744 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
746 #define PROMOTE_FUNCTION_RETURN
748 /* Define this macro if the promotion described by PROMOTE_MODE
749 should _only_ be performed for outgoing function arguments or
750 function return values, as specified by PROMOTE_FUNCTION_ARGS
751 and PROMOTE_FUNCTION_RETURN, respectively. */
752 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
753 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
754 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
755 for arithmetic operations which do zero/sign extension at the same time,
756 so without this we end up with a srl/sra after every assignment to an
757 user variable, which means very very bad code. */
758 #define PROMOTE_FOR_CALL_ONLY
760 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
761 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
763 /* Boundary (in *bits*) on which stack pointer should be aligned. */
764 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
766 /* ALIGN FRAMES on double word boundaries */
768 #define SPARC_STACK_ALIGN(LOC) \
769 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
771 /* Allocation boundary (in *bits*) for the code of a function. */
772 #define FUNCTION_BOUNDARY 32
774 /* Alignment of field after `int : 0' in a structure. */
775 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
777 /* Every structure's size must be a multiple of this. */
778 #define STRUCTURE_SIZE_BOUNDARY 8
780 /* A bitfield declared as `int' forces `int' alignment for the struct. */
781 #define PCC_BITFIELD_TYPE_MATTERS 1
783 /* No data type wants to be aligned rounder than this. */
784 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
786 /* The best alignment to use in cases where we have a choice. */
787 #define FASTEST_ALIGNMENT 64
789 /* Define this macro as an expression for the alignment of a structure
790 (given by STRUCT as a tree node) if the alignment computed in the
791 usual way is COMPUTED and the alignment explicitly specified was
794 The default is to use SPECIFIED if it is larger; otherwise, use
795 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
796 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
797 (TARGET_FASTER_STRUCTS ? \
798 ((TREE_CODE (STRUCT) == RECORD_TYPE \
799 || TREE_CODE (STRUCT) == UNION_TYPE \
800 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
801 && TYPE_FIELDS (STRUCT) != 0 \
802 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
803 : MAX ((COMPUTED), (SPECIFIED))) \
804 : MAX ((COMPUTED), (SPECIFIED)))
806 /* Make strings word-aligned so strcpy from constants will be faster. */
807 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
808 ((TREE_CODE (EXP) == STRING_CST \
809 && (ALIGN) < FASTEST_ALIGNMENT) \
810 ? FASTEST_ALIGNMENT : (ALIGN))
812 /* Make arrays of chars word-aligned for the same reasons. */
813 #define DATA_ALIGNMENT(TYPE, ALIGN) \
814 (TREE_CODE (TYPE) == ARRAY_TYPE \
815 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
816 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
818 /* Set this nonzero if move instructions will actually fail to work
819 when given unaligned data. */
820 #define STRICT_ALIGNMENT 1
822 /* Things that must be doubleword aligned cannot go in the text section,
823 because the linker fails to align the text section enough!
824 Put them in the data section. This macro is only used in this file. */
825 #define MAX_TEXT_ALIGN 32
827 /* This forces all variables and constants to the data section when PIC.
828 This is because the SunOS 4 shared library scheme thinks everything in
829 text is a function, and patches the address to point to a loader stub. */
830 /* This is defined to zero for every system which doesn't use the a.out object
832 #ifndef SUNOS4_SHARED_LIBRARIES
833 #define SUNOS4_SHARED_LIBRARIES 0
837 /* Use text section for a constant
838 unless we need more alignment than that offers. */
839 /* This is defined differently for v9 in a cover file. */
840 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
842 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
843 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
849 /* Standard register usage. */
851 /* Number of actual hardware registers.
852 The hardware registers are assigned numbers for the compiler
853 from 0 to just below FIRST_PSEUDO_REGISTER.
854 All registers that the compiler knows about must be given numbers,
855 even those that are not normally considered general registers.
857 SPARC has 32 integer registers and 32 floating point registers.
858 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
859 accessible. We still account for them to simplify register computations
860 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
862 Register 100 is used as the integer condition code register.
863 Register 101 is used as the soft frame pointer register. */
865 #define FIRST_PSEUDO_REGISTER 102
867 #define SPARC_FIRST_FP_REG 32
868 /* Additional V9 fp regs. */
869 #define SPARC_FIRST_V9_FP_REG 64
870 #define SPARC_LAST_V9_FP_REG 95
871 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
872 #define SPARC_FIRST_V9_FCC_REG 96
873 #define SPARC_LAST_V9_FCC_REG 99
875 #define SPARC_FCC_REG 96
876 /* Integer CC reg. We don't distinguish %icc from %xcc. */
877 #define SPARC_ICC_REG 100
879 /* Nonzero if REGNO is an fp reg. */
880 #define SPARC_FP_REG_P(REGNO) \
881 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
883 /* Argument passing regs. */
884 #define SPARC_OUTGOING_INT_ARG_FIRST 8
885 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
886 #define SPARC_FP_ARG_FIRST 32
888 /* 1 for registers that have pervasive standard uses
889 and are not available for the register allocator.
892 g1 is free to use as temporary.
893 g2-g4 are reserved for applications. Gcc normally uses them as
894 temporaries, but this can be disabled via the -mno-app-regs option.
895 g5 through g7 are reserved for the operating system.
898 g1,g5 are free to use as temporaries, and are free to use between calls
899 if the call is to an external function via the PLT.
900 g4 is free to use as a temporary in the non-embedded case.
901 g4 is reserved in the embedded case.
902 g2-g3 are reserved for applications. Gcc normally uses them as
903 temporaries, but this can be disabled via the -mno-app-regs option.
904 g6-g7 are reserved for the operating system (or application in
906 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
907 currently be a fixed register until this pattern is rewritten.
908 Register 1 is also used when restoring call-preserved registers in large
911 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
912 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
915 #define FIXED_REGISTERS \
916 {1, 0, 2, 2, 2, 2, 1, 1, \
917 0, 0, 0, 0, 0, 0, 1, 0, \
918 0, 0, 0, 0, 0, 0, 0, 0, \
919 0, 0, 0, 0, 0, 0, 1, 1, \
921 0, 0, 0, 0, 0, 0, 0, 0, \
922 0, 0, 0, 0, 0, 0, 0, 0, \
923 0, 0, 0, 0, 0, 0, 0, 0, \
924 0, 0, 0, 0, 0, 0, 0, 0, \
926 0, 0, 0, 0, 0, 0, 0, 0, \
927 0, 0, 0, 0, 0, 0, 0, 0, \
928 0, 0, 0, 0, 0, 0, 0, 0, \
929 0, 0, 0, 0, 0, 0, 0, 0, \
933 /* 1 for registers not available across function calls.
934 These must include the FIXED_REGISTERS and also any
935 registers that can be used without being saved.
936 The latter must include the registers where values are returned
937 and the register where structure-value addresses are passed.
938 Aside from that, you can include as many other registers as you like. */
940 #define CALL_USED_REGISTERS \
941 {1, 1, 1, 1, 1, 1, 1, 1, \
942 1, 1, 1, 1, 1, 1, 1, 1, \
943 0, 0, 0, 0, 0, 0, 0, 0, \
944 0, 0, 0, 0, 0, 0, 1, 1, \
946 1, 1, 1, 1, 1, 1, 1, 1, \
947 1, 1, 1, 1, 1, 1, 1, 1, \
948 1, 1, 1, 1, 1, 1, 1, 1, \
949 1, 1, 1, 1, 1, 1, 1, 1, \
951 1, 1, 1, 1, 1, 1, 1, 1, \
952 1, 1, 1, 1, 1, 1, 1, 1, \
953 1, 1, 1, 1, 1, 1, 1, 1, \
954 1, 1, 1, 1, 1, 1, 1, 1, \
958 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
959 they won't be allocated. */
961 #define CONDITIONAL_REGISTER_USAGE \
964 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
966 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
967 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
969 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
970 /* then honour it. */ \
971 if (TARGET_ARCH32 && fixed_regs[5]) \
973 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
978 for (regno = SPARC_FIRST_V9_FP_REG; \
979 regno <= SPARC_LAST_V9_FP_REG; \
981 fixed_regs[regno] = 1; \
982 /* %fcc0 is used by v8 and v9. */ \
983 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
984 regno <= SPARC_LAST_V9_FCC_REG; \
986 fixed_regs[regno] = 1; \
991 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
992 fixed_regs[regno] = 1; \
994 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
995 /* then honour it. Likewise with g3 and g4. */ \
996 if (fixed_regs[2] == 2) \
997 fixed_regs[2] = ! TARGET_APP_REGS; \
998 if (fixed_regs[3] == 2) \
999 fixed_regs[3] = ! TARGET_APP_REGS; \
1000 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1001 fixed_regs[4] = ! TARGET_APP_REGS; \
1002 else if (TARGET_CM_EMBMEDANY) \
1003 fixed_regs[4] = 1; \
1004 else if (fixed_regs[4] == 2) \
1005 fixed_regs[4] = 0; \
1008 /* Let the compiler believe the frame pointer is still \
1009 %fp, but output it as %i7. */ \
1010 fixed_regs[31] = 1; \
1011 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1012 /* Disable leaf functions */ \
1013 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1018 /* Return number of consecutive hard regs needed starting at reg REGNO
1019 to hold something of mode MODE.
1020 This is ordinarily the length in words of a value of mode MODE
1021 but can be less for certain modes in special long registers.
1023 On SPARC, ordinary registers hold 32 bits worth;
1024 this means both integer and floating point registers.
1025 On v9, integer regs hold 64 bits worth; floating point regs hold
1026 32 bits worth (this includes the new fp regs as even the odd ones are
1027 included in the hard register count). */
1029 #define HARD_REGNO_NREGS(REGNO, MODE) \
1031 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1032 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1033 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1034 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1036 /* Due to the ARCH64 descrepancy above we must override this next
1038 #define REGMODE_NATURAL_SIZE(MODE) \
1039 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1041 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1042 See sparc.c for how we initialize this. */
1043 extern const int *hard_regno_mode_classes;
1044 extern int sparc_mode_class[];
1046 /* ??? Because of the funny way we pass parameters we should allow certain
1047 ??? types of float/complex values to be in integer registers during
1048 ??? RTL generation. This only matters on arch32. */
1049 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1050 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1052 /* Value is 1 if it is a good idea to tie two pseudo registers
1053 when one has mode MODE1 and one has mode MODE2.
1054 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1055 for any hard reg, then this must be 0 for correct output.
1057 For V9: SFmode can't be combined with other float modes, because they can't
1058 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1059 registers, but SFmode will. */
1060 #define MODES_TIEABLE_P(MODE1, MODE2) \
1061 ((MODE1) == (MODE2) \
1062 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1064 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1065 || (MODE1 != SFmode && MODE2 != SFmode)))))
1067 /* Specify the registers used for certain standard purposes.
1068 The values of these macros are register numbers. */
1070 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1071 /* #define PC_REGNUM */
1073 /* Register to use for pushing function arguments. */
1074 #define STACK_POINTER_REGNUM 14
1076 /* The stack bias (amount by which the hardware register is offset by). */
1077 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1079 /* Actual top-of-stack address is 92/176 greater than the contents of the
1080 stack pointer register for !v9/v9. That is:
1081 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1082 address, and 6*4 bytes for the 6 register parameters.
1083 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1085 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1087 /* Base register for access to local variables of the function. */
1088 #define HARD_FRAME_POINTER_REGNUM 30
1090 /* The soft frame pointer does not have the stack bias applied. */
1091 #define FRAME_POINTER_REGNUM 101
1093 /* Given the stack bias, the stack pointer isn't actually aligned. */
1094 #define INIT_EXPANDERS \
1096 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1098 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1099 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1103 /* Value should be nonzero if functions must have frame pointers.
1104 Zero means the frame pointer need not be set up (and parms
1105 may be accessed via the stack pointer) in functions that seem suitable.
1106 This is computed in `reload', in reload1.c.
1107 Used in flow.c, global.c, and reload1.c.
1109 Being a non-leaf function does not mean a frame pointer is needed in the
1110 flat window model. However, the debugger won't be able to backtrace through
1112 #define FRAME_POINTER_REQUIRED \
1114 ? (current_function_calls_alloca \
1115 || current_function_varargs \
1116 || !leaf_function_p ()) \
1117 : ! (leaf_function_p () && only_leaf_regs_used ()))
1119 /* Base register for access to arguments of the function. */
1120 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1122 /* Register in which static-chain is passed to a function. This must
1123 not be a register used by the prologue. */
1124 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1126 /* Register which holds offset table for position-independent
1129 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1131 /* Pick a default value we can notice from override_options:
1133 v9: Default is off. */
1135 #define DEFAULT_PCC_STRUCT_RETURN -1
1137 /* Sparc ABI says that quad-precision floats and all structures are returned
1139 For v9: unions <= 32 bytes in size are returned in int regs,
1140 structures up to 32 bytes are returned in int and fp regs. */
1142 #define RETURN_IN_MEMORY(TYPE) \
1144 ? (TYPE_MODE (TYPE) == BLKmode \
1145 || TYPE_MODE (TYPE) == TFmode \
1146 || TYPE_MODE (TYPE) == TCmode) \
1147 : (TYPE_MODE (TYPE) == BLKmode \
1148 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1150 /* Functions which return large structures get the address
1151 to place the wanted value at offset 64 from the frame.
1152 Must reserve 64 bytes for the in and local registers.
1153 v9: Functions which return large structures get the address to place the
1154 wanted value from an invisible first argument. */
1155 /* Used only in other #defines in this file. */
1156 #define STRUCT_VALUE_OFFSET 64
1158 #define STRUCT_VALUE \
1161 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1162 STRUCT_VALUE_OFFSET)))
1164 #define STRUCT_VALUE_INCOMING \
1167 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1168 STRUCT_VALUE_OFFSET)))
1170 /* Define the classes of registers for register constraints in the
1171 machine description. Also define ranges of constants.
1173 One of the classes must always be named ALL_REGS and include all hard regs.
1174 If there is more than one class, another class must be named NO_REGS
1175 and contain no registers.
1177 The name GENERAL_REGS must be the name of a class (or an alias for
1178 another name such as ALL_REGS). This is the class of registers
1179 that is allowed by "g" or "r" in a register constraint.
1180 Also, registers outside this class are allocated only when
1181 instructions express preferences for them.
1183 The classes must be numbered in nondecreasing order; that is,
1184 a larger-numbered class must never be contained completely
1185 in a smaller-numbered class.
1187 For any two classes, it is very desirable that there be another
1188 class that represents their union. */
1190 /* The SPARC has various kinds of registers: general, floating point,
1191 and condition codes [well, it has others as well, but none that we
1192 care directly about].
1194 For v9 we must distinguish between the upper and lower floating point
1195 registers because the upper ones can't hold SFmode values.
1196 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1197 satisfying a group need for a class will also satisfy a single need for
1198 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1201 It is important that one class contains all the general and all the standard
1202 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1203 because reg_class_record() will bias the selection in favor of fp regs,
1204 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1205 because FP_REGS > GENERAL_REGS.
1207 It is also important that one class contain all the general and all the
1208 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1209 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1210 allocate_reload_reg() to bypass it causing an abort because the compiler
1211 thinks it doesn't have a spill reg when in fact it does.
1213 v9 also has 4 floating point condition code registers. Since we don't
1214 have a class that is the union of FPCC_REGS with either of the others,
1215 it is important that it appear first. Otherwise the compiler will die
1216 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1219 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1220 may try to use it to hold an SImode value. See register_operand.
1221 ??? Should %fcc[0123] be handled similarly?
1224 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1225 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1226 ALL_REGS, LIM_REG_CLASSES };
1228 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1230 /* Give names of register classes as strings for dump file. */
1232 #define REG_CLASS_NAMES \
1233 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1234 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1237 /* Define which registers fit in which classes.
1238 This is an initializer for a vector of HARD_REG_SET
1239 of length N_REG_CLASSES. */
1241 #define REG_CLASS_CONTENTS \
1242 {{0, 0, 0, 0}, /* NO_REGS */ \
1243 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1244 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1245 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1246 {0, -1, 0, 0}, /* FP_REGS */ \
1247 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1248 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1249 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1250 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1252 /* The same information, inverted:
1253 Return the class number of the smallest class containing
1254 reg number REGNO. This could be a conditional expression
1255 or could index an array. */
1257 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1259 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1261 /* This is the order in which to allocate registers normally.
1263 We put %f0/%f1 last among the float registers, so as to make it more
1264 likely that a pseudo-register which dies in the float return register
1265 will get allocated to the float return register, thus saving a move
1266 instruction at the end of the function. */
1268 #define REG_ALLOC_ORDER \
1269 { 8, 9, 10, 11, 12, 13, 2, 3, \
1270 15, 16, 17, 18, 19, 20, 21, 22, \
1271 23, 24, 25, 26, 27, 28, 29, 31, \
1272 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1273 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1274 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1275 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1276 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1277 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1278 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1279 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1280 32, 33, /* %f0,%f1 */ \
1281 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1282 1, 4, 5, 6, 7, 0, 14, 30, 101}
1284 /* This is the order in which to allocate registers for
1285 leaf functions. If all registers can fit in the "gi" registers,
1286 then we have the possibility of having a leaf function. */
1288 #define REG_LEAF_ALLOC_ORDER \
1289 { 2, 3, 24, 25, 26, 27, 28, 29, \
1291 15, 8, 9, 10, 11, 12, 13, \
1292 16, 17, 18, 19, 20, 21, 22, 23, \
1293 34, 35, 36, 37, 38, 39, \
1294 40, 41, 42, 43, 44, 45, 46, 47, \
1295 48, 49, 50, 51, 52, 53, 54, 55, \
1296 56, 57, 58, 59, 60, 61, 62, 63, \
1297 64, 65, 66, 67, 68, 69, 70, 71, \
1298 72, 73, 74, 75, 76, 77, 78, 79, \
1299 80, 81, 82, 83, 84, 85, 86, 87, \
1300 88, 89, 90, 91, 92, 93, 94, 95, \
1302 96, 97, 98, 99, 100, \
1305 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1307 extern char sparc_leaf_regs[];
1308 #define LEAF_REGISTERS sparc_leaf_regs
1310 extern const char leaf_reg_remap[];
1311 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1313 /* The class value for index registers, and the one for base regs. */
1314 #define INDEX_REG_CLASS GENERAL_REGS
1315 #define BASE_REG_CLASS GENERAL_REGS
1317 /* Local macro to handle the two v9 classes of FP regs. */
1318 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1320 /* Get reg_class from a letter such as appears in the machine description.
1321 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1322 .md file for v8 and v9.
1323 'd' and 'b' are used for single and double precision VIS operations,
1325 'h' is used for V8+ 64 bit global and out registers. */
1327 #define REG_CLASS_FROM_LETTER(C) \
1329 ? ((C) == 'f' ? FP_REGS \
1330 : (C) == 'e' ? EXTRA_FP_REGS \
1331 : (C) == 'c' ? FPCC_REGS \
1332 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1333 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1334 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1336 : ((C) == 'f' ? FP_REGS \
1337 : (C) == 'e' ? FP_REGS \
1338 : (C) == 'c' ? FPCC_REGS \
1341 /* The letters I, J, K, L and M in a register constraint string
1342 can be used to stand for particular ranges of immediate operands.
1343 This macro defines what the ranges are.
1344 C is the letter, and VALUE is a constant value.
1345 Return 1 if VALUE is in the range specified by C.
1347 `I' is used for the range of constants an insn can actually contain.
1348 `J' is used for the range which is just zero (since that is R0).
1349 `K' is used for constants which can be loaded with a single sethi insn.
1350 `L' is used for the range of constants supported by the movcc insns.
1351 `M' is used for the range of constants supported by the movrcc insns.
1352 `N' is like K, but for constants wider than 32 bits. */
1354 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1355 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1356 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1357 /* 10 and 11 bit immediates are only used for a few specific insns.
1358 SMALL_INT is used throughout the port so we continue to use it. */
1359 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1360 /* 13 bit immediate, considering only the low 32 bits */
1361 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1362 (INTVAL (X), SImode)))
1363 #define SPARC_SETHI_P(X) \
1364 (((unsigned HOST_WIDE_INT) (X) \
1365 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1366 #define SPARC_SETHI32_P(X) \
1367 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1369 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1370 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1371 : (C) == 'J' ? (VALUE) == 0 \
1372 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1373 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1374 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1375 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1378 /* Similar, but for floating constants, and defining letters G and H.
1379 Here VALUE is the CONST_DOUBLE rtx itself. */
1381 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1382 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1383 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1386 /* Given an rtx X being reloaded into a reg required to be
1387 in class CLASS, return the class of reg to actually use.
1388 In general this is just CLASS; but on some machines
1389 in some cases it is preferable to use a more restrictive class. */
1390 /* - We can't load constants into FP registers.
1391 - We can't load FP constants into integer registers when soft-float,
1392 because there is no soft-float pattern with a r/F constraint.
1393 - We can't load FP constants into integer registers for TFmode unless
1394 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1395 - Try and reload integer constants (symbolic or otherwise) back into
1396 registers directly, rather than having them dumped to memory. */
1398 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1400 ? ((FP_REG_CLASS_P (CLASS) \
1401 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1403 || (GET_MODE (X) == TFmode \
1404 && ! fp_zero_operand (X, TFmode))) \
1406 : (!FP_REG_CLASS_P (CLASS) \
1407 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1412 /* Return the register class of a scratch register needed to load IN into
1413 a register of class CLASS in MODE.
1415 We need a temporary when loading/storing a HImode/QImode value
1416 between memory and the FPU registers. This can happen when combine puts
1417 a paradoxical subreg in a float/fix conversion insn. */
1419 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1420 ((FP_REG_CLASS_P (CLASS) \
1421 && ((MODE) == HImode || (MODE) == QImode) \
1422 && (GET_CODE (IN) == MEM \
1423 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1424 && true_regnum (IN) == -1))) \
1426 : (((TARGET_CM_MEDANY \
1427 && symbolic_operand ((IN), (MODE))) \
1428 || (TARGET_CM_EMBMEDANY \
1429 && text_segment_operand ((IN), (MODE)))) \
1434 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1435 ((FP_REG_CLASS_P (CLASS) \
1436 && ((MODE) == HImode || (MODE) == QImode) \
1437 && (GET_CODE (IN) == MEM \
1438 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1439 && true_regnum (IN) == -1))) \
1441 : (((TARGET_CM_MEDANY \
1442 && symbolic_operand ((IN), (MODE))) \
1443 || (TARGET_CM_EMBMEDANY \
1444 && text_segment_operand ((IN), (MODE)))) \
1449 /* On SPARC it is not possible to directly move data between
1450 GENERAL_REGS and FP_REGS. */
1451 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1452 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1454 /* Return the stack location to use for secondary memory needed reloads.
1455 We want to use the reserved location just below the frame pointer.
1456 However, we must ensure that there is a frame, so use assign_stack_local
1457 if the frame size is zero. */
1458 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1459 (get_frame_size () == 0 \
1460 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1461 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1462 STARTING_FRAME_OFFSET)))
1464 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1465 because the movsi and movsf patterns don't handle r/f moves.
1466 For v8 we copy the default definition. */
1467 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1469 ? (GET_MODE_BITSIZE (MODE) < 32 \
1470 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1472 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1473 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1476 /* Return the maximum number of consecutive registers
1477 needed to represent mode MODE in a register of class CLASS. */
1478 /* On SPARC, this is the size of MODE in words. */
1479 #define CLASS_MAX_NREGS(CLASS, MODE) \
1480 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1481 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1483 /* Stack layout; function entry, exit and calling. */
1485 /* Define the number of register that can hold parameters.
1486 This macro is only used in other macro definitions below and in sparc.c.
1487 MODE is the mode of the argument.
1488 !v9: All args are passed in %o0-%o5.
1489 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1490 See the description in sparc.c. */
1491 #define NPARM_REGS(MODE) \
1493 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1496 /* Define this if pushing a word on the stack
1497 makes the stack pointer a smaller address. */
1498 #define STACK_GROWS_DOWNWARD
1500 /* Define this if the nominal address of the stack frame
1501 is at the high-address end of the local variables;
1502 that is, each additional local variable allocated
1503 goes at a more negative offset in the frame. */
1504 #define FRAME_GROWS_DOWNWARD
1506 /* Offset within stack frame to start allocating local variables at.
1507 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1508 first local allocated. Otherwise, it is the offset to the BEGINNING
1509 of the first local allocated. */
1510 /* This allows space for one TFmode floating point value. */
1511 #define STARTING_FRAME_OFFSET \
1512 (TARGET_ARCH64 ? -16 \
1513 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1515 /* If we generate an insn to push BYTES bytes,
1516 this says how many the stack pointer really advances by.
1517 On SPARC, don't define this because there are no push insns. */
1518 /* #define PUSH_ROUNDING(BYTES) */
1520 /* Offset of first parameter from the argument pointer register value.
1521 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1522 even if this function isn't going to use it.
1523 v9: This is 128 for the ins and locals. */
1524 #define FIRST_PARM_OFFSET(FNDECL) \
1525 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1527 /* Offset from the argument pointer register value to the CFA.
1528 This is different from FIRST_PARM_OFFSET because the register window
1529 comes between the CFA and the arguments. */
1530 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1532 /* When a parameter is passed in a register, stack space is still
1534 !v9: All 6 possible integer registers have backing store allocated.
1535 v9: Only space for the arguments passed is allocated. */
1536 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1537 meaning to the backend. Further, we need to be able to detect if a
1538 varargs/unprototyped function is called, as they may want to spill more
1539 registers than we've provided space. Ugly, ugly. So for now we retain
1540 all 6 slots even for v9. */
1541 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1543 /* Definitions for register elimination. */
1544 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1546 #define ELIMINABLE_REGS \
1547 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1548 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1550 /* The way this is structured, we can't eliminate SFP in favor of SP
1551 if the frame pointer is required: we want to use the SFP->HFP elimination
1552 in that case. But the test in update_eliminables doesn't know we are
1553 assuming below that we only do the former elimination. */
1554 #define CAN_ELIMINATE(FROM, TO) \
1555 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1557 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1560 if ((TO) == STACK_POINTER_REGNUM) \
1562 /* Note, we always pretend that this is a leaf function \
1563 because if it's not, there's no point in trying to \
1564 eliminate the frame pointer. If it is a leaf \
1565 function, we guessed right! */ \
1568 sparc_flat_compute_frame_size (get_frame_size ()); \
1570 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1572 (OFFSET) += SPARC_STACK_BIAS; \
1575 /* Keep the stack pointer constant throughout the function.
1576 This is both an optimization and a necessity: longjmp
1577 doesn't behave itself when the stack pointer moves within
1579 #define ACCUMULATE_OUTGOING_ARGS 1
1581 /* Value is the number of bytes of arguments automatically
1582 popped when returning from a subroutine call.
1583 FUNDECL is the declaration node of the function (as a tree),
1584 FUNTYPE is the data type of the function (as a tree),
1585 or for a library call it is an identifier node for the subroutine name.
1586 SIZE is the number of bytes of arguments passed on the stack. */
1588 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1590 /* Some subroutine macros specific to this machine.
1591 When !TARGET_FPU, put float return values in the general registers,
1592 since we don't have any fp registers. */
1593 #define BASE_RETURN_VALUE_REG(MODE) \
1595 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1596 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1598 #define BASE_OUTGOING_VALUE_REG(MODE) \
1600 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1601 : TARGET_FLAT ? 8 : 24) \
1602 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1603 : (TARGET_FLAT ? 8 : 24)))
1605 #define BASE_PASSING_ARG_REG(MODE) \
1607 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1610 /* ??? FIXME -- seems wrong for v9 structure passing... */
1611 #define BASE_INCOMING_ARG_REG(MODE) \
1613 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1614 : TARGET_FLAT ? 8 : 24) \
1615 : (TARGET_FLAT ? 8 : 24))
1617 /* Define this macro if the target machine has "register windows". This
1618 C expression returns the register number as seen by the called function
1619 corresponding to register number OUT as seen by the calling function.
1620 Return OUT if register number OUT is not an outbound register. */
1622 #define INCOMING_REGNO(OUT) \
1623 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1625 /* Define this macro if the target machine has "register windows". This
1626 C expression returns the register number as seen by the calling function
1627 corresponding to register number IN as seen by the called function.
1628 Return IN if register number IN is not an inbound register. */
1630 #define OUTGOING_REGNO(IN) \
1631 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1633 /* Define this macro if the target machine has register windows. This
1634 C expression returns true if the register is call-saved but is in the
1637 #define LOCAL_REGNO(REGNO) \
1638 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1640 /* Define how to find the value returned by a function.
1641 VALTYPE is the data type of the value (as a tree).
1642 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1643 otherwise, FUNC is 0. */
1645 /* On SPARC the value is found in the first "output" register. */
1647 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1648 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1650 /* But the called function leaves it in the first "input" register. */
1652 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1653 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1655 /* Define how to find the value returned by a library function
1656 assuming the value has mode MODE. */
1658 #define LIBCALL_VALUE(MODE) \
1659 function_value (NULL_TREE, (MODE), 1)
1661 /* 1 if N is a possible register number for a function value
1662 as seen by the caller.
1663 On SPARC, the first "output" reg is used for integer values,
1664 and the first floating point register is used for floating point values. */
1666 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1668 /* Define the size of space to allocate for the return value of an
1671 #define APPLY_RESULT_SIZE 16
1673 /* 1 if N is a possible register number for function argument passing.
1674 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1676 #define FUNCTION_ARG_REGNO_P(N) \
1678 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1679 : ((N) >= 8 && (N) <= 13))
1681 /* Define a data type for recording info about an argument list
1682 during the scan of that argument list. This data type should
1683 hold all necessary information about the function itself
1684 and about the args processed so far, enough to enable macros
1685 such as FUNCTION_ARG to determine where the next arg should go.
1687 On SPARC (!v9), this is a single integer, which is a number of words
1688 of arguments scanned so far (including the invisible argument,
1689 if any, which holds the structure-value-address).
1690 Thus 7 or more means all following args should go on the stack.
1692 For v9, we also need to know whether a prototype is present. */
1695 int words; /* number of words passed so far */
1696 int prototype_p; /* non-zero if a prototype is present */
1697 int libcall_p; /* non-zero if a library call */
1699 #define CUMULATIVE_ARGS struct sparc_args
1701 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1702 for a call to a function whose data type is FNTYPE.
1703 For a library call, FNTYPE is 0. */
1705 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1706 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1708 /* Update the data in CUM to advance over an argument
1709 of mode MODE and data type TYPE.
1710 TYPE is null for libcalls where that information may not be available. */
1712 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1713 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1715 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1717 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1719 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1720 || TREE_ADDRESSABLE (TYPE)))
1722 /* Determine where to put an argument to a function.
1723 Value is zero to push the argument on the stack,
1724 or a hard register in which to store the argument.
1726 MODE is the argument's machine mode.
1727 TYPE is the data type of the argument (as a tree).
1728 This is null for libcalls where that information may
1730 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1731 the preceding args and about the function being called.
1732 NAMED is nonzero if this argument is a named parameter
1733 (otherwise it is an extra parameter matching an ellipsis). */
1735 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1736 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1738 /* Define where a function finds its arguments.
1739 This is different from FUNCTION_ARG because of register windows. */
1741 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1742 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1744 /* For an arg passed partly in registers and partly in memory,
1745 this is the number of registers used.
1746 For args passed entirely in registers or entirely in memory, zero. */
1748 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1749 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1751 /* A C expression that indicates when an argument must be passed by reference.
1752 If nonzero for an argument, a copy of that argument is made in memory and a
1753 pointer to the argument is passed instead of the argument itself.
1754 The pointer is passed in whatever way is appropriate for passing a pointer
1757 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1758 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1760 /* If defined, a C expression which determines whether, and in which direction,
1761 to pad out an argument with extra space. The value should be of type
1762 `enum direction': either `upward' to pad above the argument,
1763 `downward' to pad below, or `none' to inhibit padding. */
1765 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1766 function_arg_padding ((MODE), (TYPE))
1768 /* If defined, a C expression that gives the alignment boundary, in bits,
1769 of an argument with the specified mode and type. If it is not defined,
1770 PARM_BOUNDARY is used for all arguments.
1771 For sparc64, objects requiring 16 byte alignment are passed that way. */
1773 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1775 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1776 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1777 ? 128 : PARM_BOUNDARY)
1779 /* Define the information needed to generate branch and scc insns. This is
1780 stored from the compare operation. Note that we can't use "rtx" here
1781 since it hasn't been defined! */
1783 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1786 /* Generate the special assembly code needed to tell the assembler whatever
1787 it might need to know about the return value of a function.
1789 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1790 information to the assembler relating to peephole optimization (done in
1793 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1794 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1796 /* Output the special assembly code needed to tell the assembler some
1797 register is used as global register variable.
1799 SPARC 64bit psABI declares registers %g2 and %g3 as application
1800 registers and %g6 and %g7 as OS registers. Any object using them
1801 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1802 and how they are used (scratch or some global variable).
1803 Linker will then refuse to link together objects which use those
1804 registers incompatibly.
1806 Unless the registers are used for scratch, two different global
1807 registers cannot be declared to the same name, so in the unlikely
1808 case of a global register variable occupying more than one register
1809 we prefix the second and following registers with .gnu.part1. etc. */
1811 extern char sparc_hard_reg_printed[8];
1813 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1814 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1816 if (TARGET_ARCH64) \
1818 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1820 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1821 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1823 if (reg == (REGNO)) \
1824 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1826 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1827 reg, reg - (REGNO), (NAME)); \
1828 sparc_hard_reg_printed[reg] = 1; \
1835 /* Emit rtl for profiling. */
1836 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1838 /* All the work done in PROFILE_HOOK, but still required. */
1839 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1841 /* Set the name of the mcount function for the system. */
1842 #define MCOUNT_FUNCTION "*mcount"
1844 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1845 the stack pointer does not matter. The value is tested only in
1846 functions that have frame pointers.
1847 No definition is equivalent to always zero. */
1849 #define EXIT_IGNORE_STACK \
1850 (get_frame_size () != 0 \
1851 || current_function_calls_alloca || current_function_outgoing_args_size)
1853 #define DELAY_SLOTS_FOR_EPILOGUE \
1854 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1855 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1856 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1857 : eligible_for_epilogue_delay (trial, slots_filled))
1859 /* Define registers used by the epilogue and return instruction. */
1860 #define EPILOGUE_USES(REGNO) \
1861 (!TARGET_FLAT && REGNO == 31)
1863 /* Length in units of the trampoline for entering a nested function. */
1865 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1867 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1869 /* Emit RTL insns to initialize the variable parts of a trampoline.
1870 FNADDR is an RTX for the address of the function's pure code.
1871 CXT is an RTX for the static chain value for the function. */
1873 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1874 if (TARGET_ARCH64) \
1875 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1877 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1879 /* Generate necessary RTL for __builtin_saveregs(). */
1881 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1883 /* Implement `va_start' for varargs and stdarg. */
1884 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1885 sparc_va_start (stdarg, valist, nextarg)
1887 /* Implement `va_arg'. */
1888 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1889 sparc_va_arg (valist, type)
1891 /* Define this macro if the location where a function argument is passed
1892 depends on whether or not it is a named argument.
1894 This macro controls how the NAMED argument to FUNCTION_ARG
1895 is set for varargs and stdarg functions. With this macro defined,
1896 the NAMED argument is always true for named arguments, and false for
1897 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1898 is defined, then all arguments are treated as named. Otherwise, all named
1899 arguments except the last are treated as named.
1900 For the v9 we want NAMED to mean what it says it means. */
1902 #define STRICT_ARGUMENT_NAMING TARGET_V9
1904 /* We do not allow sibling calls if -mflat, nor
1905 we do not allow indirect calls to be optimized into sibling calls.
1907 Also, on sparc 32-bit we cannot emit a sibling call when the
1908 current function returns a structure. This is because the "unimp
1909 after call" convention would cause the callee to return to the
1910 wrong place. The generic code already disallows cases where the
1911 function being called returns a structure.
1913 It may seem strange how this last case could occur. Usually there
1914 is code after the call which jumps to epilogue code which dumps the
1915 return value into the struct return area. That ought to invalidate
1916 the sibling call right? Well, in the c++ case we can end up passing
1917 the pointer to the struct return area to a constructor (which returns
1918 void) and then nothing else happens. Such a sibling call would look
1919 valid without the added check here. */
1920 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1923 && (TARGET_ARCH64 || ! current_function_returns_struct))
1925 /* Generate RTL to flush the register windows so as to make arbitrary frames
1927 #define SETUP_FRAME_ADDRESSES() \
1928 emit_insn (gen_flush_register_windows ())
1930 /* Given an rtx for the address of a frame,
1931 return an rtx for the address of the word in the frame
1932 that holds the dynamic chain--the previous frame's address.
1933 ??? -mflat support? */
1934 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
1936 /* The return address isn't on the stack, it is in a register, so we can't
1937 access it from the current frame pointer. We can access it from the
1938 previous frame pointer though by reading a value from the register window
1940 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1942 /* This is the offset of the return address to the true next instruction to be
1943 executed for the current function. */
1944 #define RETURN_ADDR_OFFSET \
1945 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1947 /* The current return address is in %i7. The return address of anything
1948 farther back is in the register window save area at [%fp+60]. */
1949 /* ??? This ignores the fact that the actual return address is +8 for normal
1950 returns, and +12 for structure returns. */
1951 #define RETURN_ADDR_RTX(count, frame) \
1953 ? gen_rtx_REG (Pmode, 31) \
1954 : gen_rtx_MEM (Pmode, \
1955 memory_address (Pmode, plus_constant (frame, \
1956 15 * UNITS_PER_WORD \
1957 + SPARC_STACK_BIAS))))
1959 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1960 +12, but always using +8 is close enough for frame unwind purposes.
1961 Actually, just using %o7 is close enough for unwinding, but %o7+8
1962 is something you can return to. */
1963 #define INCOMING_RETURN_ADDR_RTX \
1964 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1965 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1967 /* The offset from the incoming value of %sp to the top of the stack frame
1968 for the current function. On sparc64, we have to account for the stack
1970 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1972 /* Describe how we implement __builtin_eh_return. */
1973 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1974 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1975 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1977 /* Select a format to encode pointers in exception handling data. CODE
1978 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1979 true if the symbol may be affected by dynamic relocations.
1981 If assembler and linker properly support .uaword %r_disp32(foo),
1982 then use PC relative 32-bit relocations instead of absolute relocs
1983 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1984 for binaries, to save memory.
1986 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1987 symbol %r_disp32() is against was not local, but .hidden. In that
1988 case, we have to use DW_EH_PE_absptr for pic personality. */
1989 #ifdef HAVE_AS_SPARC_UA_PCREL
1990 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1991 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1993 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1994 : ((TARGET_ARCH64 && ! GLOBAL) \
1995 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1998 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2000 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
2001 : ((TARGET_ARCH64 && ! GLOBAL) \
2002 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2006 /* Emit a PC-relative relocation. */
2007 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2009 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2010 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2011 assemble_name (FILE, LABEL); \
2012 fputc (')', FILE); \
2016 /* Addressing modes, and classification of registers for them. */
2018 /* #define HAVE_POST_INCREMENT 0 */
2019 /* #define HAVE_POST_DECREMENT 0 */
2021 /* #define HAVE_PRE_DECREMENT 0 */
2022 /* #define HAVE_PRE_INCREMENT 0 */
2024 /* Macros to check register numbers against specific register classes. */
2026 /* These assume that REGNO is a hard or pseudo reg number.
2027 They give nonzero only if REGNO is a hard reg of the suitable class
2028 or a pseudo reg currently allocated to a suitable hard reg.
2029 Since they use reg_renumber, they are safe only once reg_renumber
2030 has been allocated, which happens in local-alloc.c. */
2032 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2033 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2034 || (REGNO) == FRAME_POINTER_REGNUM \
2035 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2037 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2039 #define REGNO_OK_FOR_FP_P(REGNO) \
2040 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2041 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2042 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2044 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2045 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2047 /* Now macros that check whether X is a register and also,
2048 strictly, whether it is in a specified class.
2050 These macros are specific to the SPARC, and may be used only
2051 in code for printing assembler insns and in conditions for
2052 define_optimization. */
2054 /* 1 if X is an fp register. */
2056 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2058 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2059 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2061 /* Maximum number of registers that can appear in a valid memory address. */
2063 #define MAX_REGS_PER_ADDRESS 2
2065 /* Recognize any constant value that is a valid address.
2066 When PIC, we do not accept an address that would require a scratch reg
2067 to load into a register. */
2069 #define CONSTANT_ADDRESS_P(X) \
2070 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2071 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2072 || (GET_CODE (X) == CONST \
2073 && ! (flag_pic && pic_address_needs_scratch (X))))
2075 /* Define this, so that when PIC, reload won't try to reload invalid
2076 addresses which require two reload registers. */
2078 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2080 /* Nonzero if the constant value X is a legitimate general operand.
2081 Anything can be made to work except floating point constants.
2082 If TARGET_VIS, 0.0 can be made to work as well. */
2084 #define LEGITIMATE_CONSTANT_P(X) \
2085 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2087 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2088 GET_MODE (X) == TFmode) && \
2089 fp_zero_operand (X, GET_MODE (X))))
2091 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2092 and check its validity for a certain class.
2093 We have two alternate definitions for each of them.
2094 The usual definition accepts all pseudo regs; the other rejects
2095 them unless they have been allocated suitable hard regs.
2096 The symbol REG_OK_STRICT causes the latter definition to be used.
2098 Most source files want to accept pseudo regs in the hope that
2099 they will get allocated to the class that the insn wants them to be in.
2100 Source files for reload pass need to be strict.
2101 After reload, it makes no difference, since pseudo regs have
2102 been eliminated by then. */
2104 /* Optional extra constraints for this machine.
2106 'Q' handles floating point constants which can be moved into
2107 an integer register with a single sethi instruction.
2109 'R' handles floating point constants which can be moved into
2110 an integer register with a single mov instruction.
2112 'S' handles floating point constants which can be moved into
2113 an integer register using a high/lo_sum sequence.
2115 'T' handles memory addresses where the alignment is known to
2116 be at least 8 bytes.
2118 `U' handles all pseudo registers or a hard even numbered
2119 integer register, needed for ldd/std instructions.
2121 'W' handles the memory operand when moving operands in/out
2122 of 'e' constraint floating point registers. */
2124 #ifndef REG_OK_STRICT
2126 /* Nonzero if X is a hard reg that can be used as an index
2127 or if it is a pseudo reg. */
2128 #define REG_OK_FOR_INDEX_P(X) \
2130 || REGNO (X) == FRAME_POINTER_REGNUM \
2131 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2133 /* Nonzero if X is a hard reg that can be used as a base reg
2134 or if it is a pseudo reg. */
2135 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2137 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2138 'W' is like 'T' but is assumed true on arch64.
2140 Remember to accept pseudo-registers for memory constraints if reload is
2143 #define EXTRA_CONSTRAINT(OP, C) \
2144 sparc_extra_constraint_check(OP, C, 0)
2148 /* Nonzero if X is a hard reg that can be used as an index. */
2149 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2150 /* Nonzero if X is a hard reg that can be used as a base reg. */
2151 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2153 #define EXTRA_CONSTRAINT(OP, C) \
2154 sparc_extra_constraint_check(OP, C, 1)
2158 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2160 #ifdef HAVE_AS_OFFSETABLE_LO10
2161 #define USE_AS_OFFSETABLE_LO10 1
2163 #define USE_AS_OFFSETABLE_LO10 0
2166 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2167 that is a valid memory address for an instruction.
2168 The MODE argument is the machine mode for the MEM expression
2169 that wants to use this address.
2171 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2172 ordinarily. This changes a bit when generating PIC.
2174 If you change this, execute "rm explow.o recog.o reload.o". */
2176 #define RTX_OK_FOR_BASE_P(X) \
2177 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2178 || (GET_CODE (X) == SUBREG \
2179 && GET_CODE (SUBREG_REG (X)) == REG \
2180 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2182 #define RTX_OK_FOR_INDEX_P(X) \
2183 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2184 || (GET_CODE (X) == SUBREG \
2185 && GET_CODE (SUBREG_REG (X)) == REG \
2186 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2188 #define RTX_OK_FOR_OFFSET_P(X) \
2189 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2191 #define RTX_OK_FOR_OLO10_P(X) \
2192 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2194 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2195 { if (RTX_OK_FOR_BASE_P (X)) \
2197 else if (GET_CODE (X) == PLUS) \
2199 register rtx op0 = XEXP (X, 0); \
2200 register rtx op1 = XEXP (X, 1); \
2201 if (flag_pic && op0 == pic_offset_table_rtx) \
2203 if (RTX_OK_FOR_BASE_P (op1)) \
2205 else if (flag_pic == 1 \
2206 && GET_CODE (op1) != REG \
2207 && GET_CODE (op1) != LO_SUM \
2208 && GET_CODE (op1) != MEM \
2209 && (GET_CODE (op1) != CONST_INT \
2210 || SMALL_INT (op1))) \
2213 else if (RTX_OK_FOR_BASE_P (op0)) \
2215 if ((RTX_OK_FOR_INDEX_P (op1) \
2216 /* We prohibit REG + REG for TFmode when \
2217 there are no instructions which accept \
2218 REG+REG instructions. We do this \
2219 because REG+REG is not an offsetable \
2220 address. If we get the situation \
2221 in reload where source and destination \
2222 of a movtf pattern are both MEMs with \
2223 REG+REG address, then only one of them \
2224 gets converted to an offsetable \
2226 && (MODE != TFmode \
2227 || (TARGET_FPU && TARGET_ARCH64 \
2229 && TARGET_HARD_QUAD)) \
2230 /* We prohibit REG + REG on ARCH32 if \
2231 not optimizing for DFmode/DImode \
2232 because then mem_min_alignment is \
2233 likely to be zero after reload and the \
2234 forced split would lack a matching \
2235 splitter pattern. */ \
2236 && (TARGET_ARCH64 || optimize \
2237 || (MODE != DFmode \
2238 && MODE != DImode))) \
2239 || RTX_OK_FOR_OFFSET_P (op1)) \
2242 else if (RTX_OK_FOR_BASE_P (op1)) \
2244 if ((RTX_OK_FOR_INDEX_P (op0) \
2245 /* See the previous comment. */ \
2246 && (MODE != TFmode \
2247 || (TARGET_FPU && TARGET_ARCH64 \
2249 && TARGET_HARD_QUAD)) \
2250 && (TARGET_ARCH64 || optimize \
2251 || (MODE != DFmode \
2252 && MODE != DImode))) \
2253 || RTX_OK_FOR_OFFSET_P (op0)) \
2256 else if (USE_AS_OFFSETABLE_LO10 \
2257 && GET_CODE (op0) == LO_SUM \
2259 && ! TARGET_CM_MEDMID \
2260 && RTX_OK_FOR_OLO10_P (op1)) \
2262 register rtx op00 = XEXP (op0, 0); \
2263 register rtx op01 = XEXP (op0, 1); \
2264 if (RTX_OK_FOR_BASE_P (op00) \
2265 && CONSTANT_P (op01)) \
2268 else if (USE_AS_OFFSETABLE_LO10 \
2269 && GET_CODE (op1) == LO_SUM \
2271 && ! TARGET_CM_MEDMID \
2272 && RTX_OK_FOR_OLO10_P (op0)) \
2274 register rtx op10 = XEXP (op1, 0); \
2275 register rtx op11 = XEXP (op1, 1); \
2276 if (RTX_OK_FOR_BASE_P (op10) \
2277 && CONSTANT_P (op11)) \
2281 else if (GET_CODE (X) == LO_SUM) \
2283 register rtx op0 = XEXP (X, 0); \
2284 register rtx op1 = XEXP (X, 1); \
2285 if (RTX_OK_FOR_BASE_P (op0) \
2286 && CONSTANT_P (op1) \
2287 /* We can't allow TFmode, because an offset \
2288 greater than or equal to the alignment (8) \
2289 may cause the LO_SUM to overflow if !v9. */\
2290 && (MODE != TFmode || TARGET_V9)) \
2293 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2297 /* Try machine-dependent ways of modifying an illegitimate address
2298 to be legitimate. If we find one, return the new, valid address.
2299 This macro is used in only one place: `memory_address' in explow.c.
2301 OLDX is the address as it was before break_out_memory_refs was called.
2302 In some cases it is useful to look at this to decide what needs to be done.
2304 MODE and WIN are passed so that this macro can use
2305 GO_IF_LEGITIMATE_ADDRESS.
2307 It is always safe for this macro to do nothing. It exists to recognize
2308 opportunities to optimize the output. */
2310 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2311 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2312 { rtx sparc_x = (X); \
2313 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2314 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2315 force_operand (XEXP (X, 0), NULL_RTX)); \
2316 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2317 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2318 force_operand (XEXP (X, 1), NULL_RTX)); \
2319 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2320 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2322 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2323 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2324 force_operand (XEXP (X, 1), NULL_RTX)); \
2325 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2327 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2328 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2329 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2330 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2331 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2332 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2333 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2334 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2335 || GET_CODE (X) == LABEL_REF) \
2336 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2337 if (memory_address_p (MODE, X)) \
2340 /* Try a machine-dependent way of reloading an illegitimate address
2341 operand. If we find one, push the reload and jump to WIN. This
2342 macro is used in only one place: `find_reloads_address' in reload.c.
2344 For Sparc 32, we wish to handle addresses by splitting them into
2345 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2346 This cuts the number of extra insns by one.
2348 Do nothing when generating PIC code and the address is a
2349 symbolic operand or requires a scratch register. */
2351 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2353 /* Decompose SImode constants into hi+lo_sum. We do have to \
2354 rerecognize what we produce, so be careful. */ \
2355 if (CONSTANT_P (X) \
2356 && (MODE != TFmode || TARGET_ARCH64) \
2357 && GET_MODE (X) == SImode \
2358 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2360 && (symbolic_operand (X, Pmode) \
2361 || pic_address_needs_scratch (X))) \
2362 && sparc_cmodel <= CM_MEDLOW) \
2364 X = gen_rtx_LO_SUM (GET_MODE (X), \
2365 gen_rtx_HIGH (GET_MODE (X), X), X); \
2366 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2367 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2371 /* ??? 64-bit reloads. */ \
2374 /* Go to LABEL if ADDR (a legitimate address expression)
2375 has an effect that depends on the machine mode it is used for.
2376 On the SPARC this is never true. */
2378 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2380 /* If we are referencing a function make the SYMBOL_REF special.
2381 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2382 so we must not add it to function addresses. */
2384 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2386 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2387 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2390 /* Specify the machine mode that this machine uses
2391 for the index in the tablejump instruction. */
2392 /* If we ever implement any of the full models (such as CM_FULLANY),
2393 this has to be DImode in that case */
2394 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2395 #define CASE_VECTOR_MODE \
2396 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2398 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2399 we have to sign extend which slows things down. */
2400 #define CASE_VECTOR_MODE \
2401 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2404 /* Define as C expression which evaluates to nonzero if the tablejump
2405 instruction expects the table to contain offsets from the address of the
2407 Do not define this if the table should contain absolute addresses. */
2408 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2410 /* Define this as 1 if `char' should by default be signed; else as 0. */
2411 #define DEFAULT_SIGNED_CHAR 1
2413 /* Max number of bytes we can move from memory to memory
2414 in one reasonably fast instruction. */
2417 #if 0 /* Sun 4 has matherr, so this is no good. */
2418 /* This is the value of the error code EDOM for this machine,
2419 used by the sqrt instruction. */
2420 #define TARGET_EDOM 33
2422 /* This is how to refer to the variable errno. */
2423 #define GEN_ERRNO_RTX \
2424 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2427 /* Define if operations between registers always perform the operation
2428 on the full register even if a narrower mode is specified. */
2429 #define WORD_REGISTER_OPERATIONS
2431 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2432 will either zero-extend or sign-extend. The value of this macro should
2433 be the code that says which one of the two operations is implicitly
2434 done, NIL if none. */
2435 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2437 /* Nonzero if access to memory by bytes is slow and undesirable.
2438 For RISC chips, it means that access to memory by bytes is no
2439 better than access by words when possible, so grab a whole word
2440 and maybe make use of that. */
2441 #define SLOW_BYTE_ACCESS 1
2443 /* We assume that the store-condition-codes instructions store 0 for false
2444 and some other value for true. This is the value stored for true. */
2446 #define STORE_FLAG_VALUE 1
2448 /* When a prototype says `char' or `short', really pass an `int'. */
2449 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2451 /* Define this to be nonzero if shift instructions ignore all but the low-order
2453 #define SHIFT_COUNT_TRUNCATED 1
2455 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2456 is done just by pretending it is already truncated. */
2457 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2459 /* Specify the machine mode that pointers have.
2460 After generation of rtl, the compiler makes no further distinction
2461 between pointers and any other objects of this machine mode. */
2462 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2464 /* Generate calls to memcpy, memcmp and memset. */
2465 #define TARGET_MEM_FUNCTIONS
2467 /* Add any extra modes needed to represent the condition code.
2469 On the Sparc, we have a "no-overflow" mode which is used when an add or
2470 subtract insn is used to set the condition code. Different branches are
2471 used in this case for some operations.
2473 We also have two modes to indicate that the relevant condition code is
2474 in the floating-point condition code register. One for comparisons which
2475 will generate an exception if the result is unordered (CCFPEmode) and
2476 one for comparisons which will never trap (CCFPmode).
2478 CCXmode and CCX_NOOVmode are only used by v9. */
2480 #define EXTRA_CC_MODES \
2481 CC(CCXmode, "CCX") \
2482 CC(CC_NOOVmode, "CC_NOOV") \
2483 CC(CCX_NOOVmode, "CCX_NOOV") \
2484 CC(CCFPmode, "CCFP") \
2485 CC(CCFPEmode, "CCFPE")
2487 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2488 return the mode to be used for the comparison. For floating-point,
2489 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2490 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2491 processing is needed. */
2492 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2494 /* Return non-zero if MODE implies a floating point inequality can be
2495 reversed. For Sparc this is always true because we have a full
2496 compliment of ordered and unordered comparisons, but until generic
2497 code knows how to reverse it correctly we keep the old definition. */
2498 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2500 /* A function address in a call instruction for indexing purposes. */
2501 #define FUNCTION_MODE Pmode
2503 /* Define this if addresses of constant functions
2504 shouldn't be put through pseudo regs where they can be cse'd.
2505 Desirable on machines where ordinary constants are expensive
2506 but a CALL with constant address is cheap. */
2507 #define NO_FUNCTION_CSE
2509 /* alloca should avoid clobbering the old register save area. */
2510 #define SETJMP_VIA_SAVE_AREA
2512 /* Define subroutines to call to handle multiply and divide.
2513 Use the subroutines that Sun's library provides.
2514 The `*' prevents an underscore from being prepended by the compiler. */
2516 #define DIVSI3_LIBCALL "*.div"
2517 #define UDIVSI3_LIBCALL "*.udiv"
2518 #define MODSI3_LIBCALL "*.rem"
2519 #define UMODSI3_LIBCALL "*.urem"
2520 /* .umul is a little faster than .mul. */
2521 #define MULSI3_LIBCALL "*.umul"
2523 /* Define library calls for quad FP operations. These are all part of the
2525 #define ADDTF3_LIBCALL "_Q_add"
2526 #define SUBTF3_LIBCALL "_Q_sub"
2527 #define NEGTF2_LIBCALL "_Q_neg"
2528 #define MULTF3_LIBCALL "_Q_mul"
2529 #define DIVTF3_LIBCALL "_Q_div"
2530 #define FLOATSITF2_LIBCALL "_Q_itoq"
2531 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2532 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2533 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2534 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2535 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2536 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2537 #define EQTF2_LIBCALL "_Q_feq"
2538 #define NETF2_LIBCALL "_Q_fne"
2539 #define GTTF2_LIBCALL "_Q_fgt"
2540 #define GETF2_LIBCALL "_Q_fge"
2541 #define LTTF2_LIBCALL "_Q_flt"
2542 #define LETF2_LIBCALL "_Q_fle"
2544 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2545 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2546 and the compiler will notice and try to use the TFmode sqrt instruction
2547 for calls to the builtin function sqrt, but this fails. */
2548 #define INIT_TARGET_OPTABS \
2550 if (TARGET_ARCH32) \
2552 add_optab->handlers[(int) TFmode].libfunc \
2553 = init_one_libfunc (ADDTF3_LIBCALL); \
2554 sub_optab->handlers[(int) TFmode].libfunc \
2555 = init_one_libfunc (SUBTF3_LIBCALL); \
2556 neg_optab->handlers[(int) TFmode].libfunc \
2557 = init_one_libfunc (NEGTF2_LIBCALL); \
2558 smul_optab->handlers[(int) TFmode].libfunc \
2559 = init_one_libfunc (MULTF3_LIBCALL); \
2560 sdiv_optab->handlers[(int) TFmode].libfunc \
2561 = init_one_libfunc (DIVTF3_LIBCALL); \
2562 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2563 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2564 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2565 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2566 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2567 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2568 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2569 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2570 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2571 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2572 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2573 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2574 fixunstfsi_libfunc \
2575 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2577 sqrt_optab->handlers[(int) TFmode].libfunc \
2578 = init_one_libfunc ("_Q_sqrt"); \
2580 INIT_SUBTARGET_OPTABS; \
2583 /* This is meant to be redefined in the host dependent files */
2584 #define INIT_SUBTARGET_OPTABS
2586 /* Nonzero if a floating point comparison library call for
2587 mode MODE that will return a boolean value. Zero if one
2588 of the libgcc2 functions is used. */
2589 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2591 /* Compute the cost of computing a constant rtl expression RTX
2592 whose rtx-code is CODE. The body of this macro is a portion
2593 of a switch statement. If the code is computed here,
2594 return it with a return statement. Otherwise, break from the switch. */
2596 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2598 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2606 case CONST_DOUBLE: \
2607 if (GET_MODE (RTX) == DImode) \
2608 if ((XINT (RTX, 3) == 0 \
2609 && (unsigned) XINT (RTX, 2) < 0x1000) \
2610 || (XINT (RTX, 3) == -1 \
2611 && XINT (RTX, 2) < 0 \
2612 && XINT (RTX, 2) >= -0x1000)) \
2616 #define ADDRESS_COST(RTX) 1
2618 /* Compute extra cost of moving data between one register class
2620 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2621 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2622 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2623 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2624 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2625 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2627 /* Provide the cost of a branch. For pre-v9 processors we use
2628 a value of 3 to take into account the potential annulling of
2629 the delay slot (which ends up being a bubble in the pipeline slot)
2630 plus a cycle to take into consideration the instruction cache
2633 On v9 and later, which have branch prediction facilities, we set
2634 it to the depth of the pipeline as that is the cost of a
2635 mispredicted branch.
2637 ??? Set to 9 when PROCESSOR_ULTRASPARC3 is added */
2639 #define BRANCH_COST \
2640 ((sparc_cpu == PROCESSOR_V9 \
2641 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2644 /* Provide the costs of a rtl expression. This is in the body of a
2645 switch on CODE. The purpose for the cost of MULT is to encourage
2646 `synth_mult' to find a synthetic multiply when reasonable.
2648 If we need more than 12 insns to do a multiply, then go out-of-line,
2649 since the call overhead will be < 10% of the cost of the multiply. */
2651 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2653 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2654 return (GET_MODE (X) == DImode ? \
2655 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2656 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2661 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2662 return (GET_MODE (X) == DImode ? \
2663 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2664 return COSTS_N_INSNS (25); \
2665 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2666 so that cse will favor the latter. */ \
2671 #define PREFETCH_BLOCK \
2672 ((sparc_cpu == PROCESSOR_ULTRASPARC) ? 64 : 32)
2674 /* ??? UltraSPARC-III note: Can set this to 8 for ultra3. */
2675 #define SIMULTANEOUS_PREFETCHES \
2676 ((sparc_cpu == PROCESSOR_ULTRASPARC) ? 2 : 3)
2678 /* Control the assembler format that we output. */
2680 /* Output at beginning of assembler file. */
2682 #define ASM_FILE_START(file)
2684 /* A C string constant describing how to begin a comment in the target
2685 assembler language. The compiler assumes that the comment will end at
2686 the end of the line. */
2688 #define ASM_COMMENT_START "!"
2690 /* Output to assembler file text saying following lines
2691 may contain character constants, extra white space, comments, etc. */
2693 #define ASM_APP_ON ""
2695 /* Output to assembler file text saying following lines
2696 no longer contain unusual constructs. */
2698 #define ASM_APP_OFF ""
2700 /* ??? Try to make the style consistent here (_OP?). */
2702 #define ASM_FLOAT ".single"
2703 #define ASM_DOUBLE ".double"
2704 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2706 /* How to refer to registers in assembler output.
2707 This sequence is indexed by compiler's hard-register-number (see above). */
2709 #define REGISTER_NAMES \
2710 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2711 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2712 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2713 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2714 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2715 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2716 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2717 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2718 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2719 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2720 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2721 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2722 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2724 /* Define additional names for use in asm clobbers and asm declarations. */
2726 #define ADDITIONAL_REGISTER_NAMES \
2727 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2729 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2730 can run past this up to a continuation point. Once we used 1500, but
2731 a single entry in C++ can run more than 500 bytes, due to the length of
2732 mangled symbol names. dbxout.c should really be fixed to do
2733 continuations when they are actually needed instead of trying to
2735 #define DBX_CONTIN_LENGTH 1000
2737 /* This is how to output the definition of a user-level label named NAME,
2738 such as the label on a static function or variable NAME. */
2740 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2741 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2743 /* This is how to output a command to make the user-level label named NAME
2744 defined for reference from other files. */
2746 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2747 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2749 /* The prefix to add to user-visible assembler symbols. */
2751 #define USER_LABEL_PREFIX "_"
2753 /* This is how to output a definition of an internal numbered label where
2754 PREFIX is the class of label and NUM is the number within the class. */
2756 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2757 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2759 /* This is how to store into the string LABEL
2760 the symbol_ref name of an internal numbered label where
2761 PREFIX is the class of label and NUM is the number within the class.
2762 This is suitable for output with `assemble_name'. */
2764 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2765 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2767 /* This is how we hook in and defer the case-vector until the end of
2769 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2770 sparc_defer_case_vector ((LAB),(VEC), 0)
2772 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2773 sparc_defer_case_vector ((LAB),(VEC), 1)
2775 /* This is how to output an element of a case-vector that is absolute. */
2777 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2780 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2781 if (CASE_VECTOR_MODE == SImode) \
2782 fprintf (FILE, "\t.word\t"); \
2784 fprintf (FILE, "\t.xword\t"); \
2785 assemble_name (FILE, label); \
2786 fputc ('\n', FILE); \
2789 /* This is how to output an element of a case-vector that is relative.
2790 (SPARC uses such vectors only when generating PIC.) */
2792 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2795 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2796 if (CASE_VECTOR_MODE == SImode) \
2797 fprintf (FILE, "\t.word\t"); \
2799 fprintf (FILE, "\t.xword\t"); \
2800 assemble_name (FILE, label); \
2801 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2802 fputc ('-', FILE); \
2803 assemble_name (FILE, label); \
2804 fputc ('\n', FILE); \
2807 /* This is what to output before and after case-vector (both
2808 relative and absolute). If .subsection -1 works, we put case-vectors
2809 at the beginning of the current section. */
2811 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2813 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2814 fprintf(FILE, "\t.subsection\t-1\n")
2816 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2817 fprintf(FILE, "\t.previous\n")
2821 /* This is how to output an assembler line
2822 that says to advance the location counter
2823 to a multiple of 2**LOG bytes. */
2825 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2827 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2829 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2830 fprintf (FILE, "\t.skip %u\n", (SIZE))
2832 /* This says how to output an assembler line
2833 to define a global common symbol. */
2835 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2836 ( fputs ("\t.common ", (FILE)), \
2837 assemble_name ((FILE), (NAME)), \
2838 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2840 /* This says how to output an assembler line to define a local common
2843 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2844 ( fputs ("\t.reserve ", (FILE)), \
2845 assemble_name ((FILE), (NAME)), \
2846 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2847 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2849 /* A C statement (sans semicolon) to output to the stdio stream
2850 FILE the assembler definition of uninitialized global DECL named
2851 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2852 Try to use asm_output_aligned_bss to implement this macro. */
2854 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2856 fputs (".globl ", (FILE)); \
2857 assemble_name ((FILE), (NAME)); \
2858 fputs ("\n", (FILE)); \
2859 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2862 /* Store in OUTPUT a string (made with alloca) containing
2863 an assembler-name for a local static variable named NAME.
2864 LABELNO is an integer which is different for each call. */
2866 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2867 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2868 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2870 #define IDENT_ASM_OP "\t.ident\t"
2872 /* Output #ident as a .ident. */
2874 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2875 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2877 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2878 Used for C++ multiple inheritance. */
2879 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2884 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
2886 if ((DELTA) >= 4096 || (DELTA) < -4096) \
2887 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
2888 (int)(DELTA), reg, reg); \
2890 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
2891 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
2892 fprintf (FILE, "\tcall\t"); \
2893 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2894 fprintf (FILE, ", 0\n"); \
2895 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
2898 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2899 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2901 /* Print operand X (an rtx) in assembler syntax to file FILE.
2902 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2903 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2905 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2907 /* Print a memory address as an operand to reference that memory location. */
2909 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2910 { register rtx base, index = 0; \
2912 register rtx addr = ADDR; \
2913 if (GET_CODE (addr) == REG) \
2914 fputs (reg_names[REGNO (addr)], FILE); \
2915 else if (GET_CODE (addr) == PLUS) \
2917 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2918 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2919 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2920 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2922 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2923 if (GET_CODE (base) == LO_SUM) \
2925 if (! USE_AS_OFFSETABLE_LO10 \
2927 || TARGET_CM_MEDMID) \
2929 output_operand (XEXP (base, 0), 0); \
2930 fputs ("+%lo(", FILE); \
2931 output_address (XEXP (base, 1)); \
2932 fprintf (FILE, ")+%d", offset); \
2936 fputs (reg_names[REGNO (base)], FILE); \
2938 fprintf (FILE, "%+d", offset); \
2939 else if (GET_CODE (index) == REG) \
2940 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2941 else if (GET_CODE (index) == SYMBOL_REF \
2942 || GET_CODE (index) == CONST) \
2943 fputc ('+', FILE), output_addr_const (FILE, index); \
2947 else if (GET_CODE (addr) == MINUS \
2948 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2950 output_addr_const (FILE, XEXP (addr, 0)); \
2951 fputs ("-(", FILE); \
2952 output_addr_const (FILE, XEXP (addr, 1)); \
2953 fputs ("-.)", FILE); \
2955 else if (GET_CODE (addr) == LO_SUM) \
2957 output_operand (XEXP (addr, 0), 0); \
2958 if (TARGET_CM_MEDMID) \
2959 fputs ("+%l44(", FILE); \
2961 fputs ("+%lo(", FILE); \
2962 output_address (XEXP (addr, 1)); \
2963 fputc (')', FILE); \
2965 else if (flag_pic && GET_CODE (addr) == CONST \
2966 && GET_CODE (XEXP (addr, 0)) == MINUS \
2967 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2968 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2969 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2971 addr = XEXP (addr, 0); \
2972 output_addr_const (FILE, XEXP (addr, 0)); \
2973 /* Group the args of the second CONST in parenthesis. */ \
2974 fputs ("-(", FILE); \
2975 /* Skip past the second CONST--it does nothing for us. */\
2976 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2977 /* Close the parenthesis. */ \
2978 fputc (')', FILE); \
2982 output_addr_const (FILE, addr); \
2986 /* Define the codes that are matched by predicates in sparc.c. */
2988 #define PREDICATE_CODES \
2989 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2990 {"fp_zero_operand", {CONST_DOUBLE}}, \
2991 {"fp_register_operand", {SUBREG, REG}}, \
2992 {"intreg_operand", {SUBREG, REG}}, \
2993 {"fcc_reg_operand", {REG}}, \
2994 {"fcc0_reg_operand", {REG}}, \
2995 {"icc_or_fcc_reg_operand", {REG}}, \
2996 {"restore_operand", {REG}}, \
2997 {"call_operand", {MEM}}, \
2998 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2999 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
3000 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3001 {"symbolic_memory_operand", {SUBREG, MEM}}, \
3002 {"label_ref_operand", {LABEL_REF}}, \
3003 {"sp64_medium_pic_operand", {CONST}}, \
3004 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
3005 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
3006 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
3007 {"splittable_symbolic_memory_operand", {MEM}}, \
3008 {"splittable_immediate_memory_operand", {MEM}}, \
3009 {"eq_or_neq", {EQ, NE}}, \
3010 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
3011 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3012 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3013 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3014 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3015 {"cc_arithop", {AND, IOR, XOR}}, \
3016 {"cc_arithopn", {AND, IOR}}, \
3017 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3018 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3019 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3020 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3021 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3022 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3023 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3024 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3025 {"small_int", {CONST_INT}}, \
3026 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3027 {"uns_small_int", {CONST_INT}}, \
3028 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3029 {"clobbered_register", {REG}}, \
3030 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3031 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3032 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3034 /* The number of Pmode words for the setjmp buffer. */
3035 #define JMP_BUF_SIZE 12
3037 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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