1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Define macros to distinguish architectures. */
215 /* Common CPP definitions used by CPP_SPEC amongst the various targets
216 for handling -mcpu=xxx switches. */
217 #define CPP_CPU_SPEC "\
218 %{msoft-float:-D_SOFT_FLOAT} \
220 %{msparclite:-D__sparclite__} \
221 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
222 %{mv8:-D__sparc_v8__} \
223 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
224 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
225 %{mcpu=sparclite:-D__sparclite__} \
226 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
227 %{mcpu=v8:-D__sparc_v8__} \
228 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
229 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclite86x:-D__sparclite86x__} \
231 %{mcpu=v9:-D__sparc_v9__} \
232 %{mcpu=ultrasparc:-D__sparc_v9__} \
233 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
236 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
237 the right varags.h file when bootstrapping. */
238 /* ??? It's not clear what value we want to use for -Acpu/machine for
239 sparc64 in 32 bit environments, so for now we only use `sparc64' in
240 64 bit environments. */
244 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
245 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
246 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
247 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
251 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
252 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
256 #define CPP_ARCH_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
259 #define CPP_ARCH_SPEC "\
260 %{m32:%(cpp_arch32)} \
261 %{m64:%(cpp_arch64)} \
262 %{!m32:%{!m64:%(cpp_arch_default)}} \
265 /* Macros to distinguish endianness. */
266 #define CPP_ENDIAN_SPEC "\
267 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
268 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
270 /* Macros to distinguish the particular subtarget. */
271 #define CPP_SUBTARGET_SPEC ""
273 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
275 /* Prevent error on `-sun4' and `-target sun4' options. */
276 /* This used to translate -dalign to -malign, but that is no good
277 because it can't turn off the usual meaning of making debugging dumps. */
278 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
279 ??? Delete support for -m<cpu> for 2.9. */
282 %{sun4:} %{target:} \
283 %{mcypress:-mcpu=cypress} \
284 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
285 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
288 /* Override in target specific files. */
289 #define ASM_CPU_SPEC "\
290 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
291 %{msparclite:-Asparclite} \
292 %{mf930:-Asparclite} %{mf934:-Asparclite} \
293 %{mcpu=sparclite:-Asparclite} \
294 %{mcpu=sparclite86x:-Asparclite} \
295 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
296 %{mv8plus:-Av8plus} \
298 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
299 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
302 /* Word size selection, among other things.
303 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
305 #define ASM_ARCH32_SPEC "-32"
306 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
307 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
309 #define ASM_ARCH64_SPEC "-64"
311 #define ASM_ARCH_DEFAULT_SPEC \
312 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
314 #define ASM_ARCH_SPEC "\
315 %{m32:%(asm_arch32)} \
316 %{m64:%(asm_arch64)} \
317 %{!m32:%{!m64:%(asm_arch_default)}} \
320 #ifdef HAVE_AS_RELAX_OPTION
321 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
323 #define ASM_RELAX_SPEC ""
326 /* Special flags to the Sun-4 assembler when using pipe for input. */
329 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
330 %(asm_cpu) %(asm_relax)"
332 /* This macro defines names of additional specifications to put in the specs
333 that can be used in various specifications like CC1_SPEC. Its definition
334 is an initializer with a subgrouping for each command option.
336 Each subgrouping contains a string constant, that defines the
337 specification name, and a string constant that used by the GNU CC driver
340 Do not define this macro if it does not need to do anything. */
342 #define EXTRA_SPECS \
343 { "cpp_cpu", CPP_CPU_SPEC }, \
344 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
345 { "cpp_arch32", CPP_ARCH32_SPEC }, \
346 { "cpp_arch64", CPP_ARCH64_SPEC }, \
347 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
348 { "cpp_arch", CPP_ARCH_SPEC }, \
349 { "cpp_endian", CPP_ENDIAN_SPEC }, \
350 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
351 { "asm_cpu", ASM_CPU_SPEC }, \
352 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
353 { "asm_arch32", ASM_ARCH32_SPEC }, \
354 { "asm_arch64", ASM_ARCH64_SPEC }, \
355 { "asm_relax", ASM_RELAX_SPEC }, \
356 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
357 { "asm_arch", ASM_ARCH_SPEC }, \
358 SUBTARGET_EXTRA_SPECS
360 #define SUBTARGET_EXTRA_SPECS
363 #define NO_BUILTIN_PTRDIFF_TYPE
364 #define NO_BUILTIN_SIZE_TYPE
366 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
367 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
369 /* ??? This should be 32 bits for v9 but what can we do? */
370 #define WCHAR_TYPE "short unsigned int"
371 #define WCHAR_TYPE_SIZE 16
373 /* Show we can debug even without a frame pointer. */
374 #define CAN_DEBUG_WITHOUT_FP
376 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
377 code into the rtl. Also, if we are profiling, we cannot eliminate
378 the frame pointer (because the return address will get smashed). */
380 #define OVERRIDE_OPTIONS \
382 if (profile_flag || profile_arc_flag) \
386 const char *const pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
387 warning ("%s and profiling conflict: disabling %s", \
388 pic_string, pic_string); \
391 flag_omit_frame_pointer = 0; \
393 sparc_override_options (); \
394 SUBTARGET_OVERRIDE_OPTIONS; \
397 /* This is meant to be redefined in the host dependent files. */
398 #define SUBTARGET_OVERRIDE_OPTIONS
400 /* Generate DBX debugging information. */
402 #define DBX_DEBUGGING_INFO
404 /* Run-time compilation parameters selecting different hardware subsets. */
406 extern int target_flags;
408 /* Nonzero if we should generate code to use the fpu. */
410 #define TARGET_FPU (target_flags & MASK_FPU)
412 /* Nonzero if we should use function_epilogue(). Otherwise, we
413 use fast return insns, but lose some generality. */
414 #define MASK_EPILOGUE 2
415 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
417 /* Nonzero if we should assume that double pointers might be unaligned.
418 This can happen when linking gcc compiled code with other compilers,
419 because the ABI only guarantees 4 byte alignment. */
420 #define MASK_UNALIGNED_DOUBLES 4
421 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
423 /* Nonzero means that we should generate code for a v8 sparc. */
425 #define TARGET_V8 (target_flags & MASK_V8)
427 /* Nonzero means that we should generate code for a sparclite.
428 This enables the sparclite specific instructions, but does not affect
429 whether FPU instructions are emitted. */
430 #define MASK_SPARCLITE 0x10
431 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
433 /* Nonzero if we're compiling for the sparclet. */
434 #define MASK_SPARCLET 0x20
435 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
437 /* Nonzero if we're compiling for v9 sparc.
438 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
439 the word size is 64. */
441 #define TARGET_V9 (target_flags & MASK_V9)
443 /* Non-zero to generate code that uses the instructions deprecated in
444 the v9 architecture. This option only applies to v9 systems. */
445 /* ??? This isn't user selectable yet. It's used to enable such insns
446 on 32 bit v9 systems and for the moment they're permanently disabled
447 on 64 bit v9 systems. */
448 #define MASK_DEPRECATED_V8_INSNS 0x80
449 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
451 /* Mask of all CPU selection flags. */
453 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
455 /* Non-zero means don't pass `-assert pure-text' to the linker. */
456 #define MASK_IMPURE_TEXT 0x100
457 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
459 /* Nonzero means that we should generate code using a flat register window
460 model, i.e. no save/restore instructions are generated, which is
461 compatible with normal sparc code.
462 The frame pointer is %i7 instead of %fp. */
463 #define MASK_FLAT 0x200
464 #define TARGET_FLAT (target_flags & MASK_FLAT)
466 /* Nonzero means use the registers that the Sparc ABI reserves for
467 application software. This must be the default to coincide with the
468 setting in FIXED_REGISTERS. */
469 #define MASK_APP_REGS 0x400
470 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
472 /* Option to select how quad word floating point is implemented.
473 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
474 Otherwise, we use the SPARC ABI quad library functions. */
475 #define MASK_HARD_QUAD 0x800
476 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
478 /* Non-zero on little-endian machines. */
479 /* ??? Little endian support currently only exists for sparclet-aout and
480 sparc64-elf configurations. May eventually want to expand the support
481 to all targets, but for now it's kept local to only those two. */
482 #define MASK_LITTLE_ENDIAN 0x1000
483 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
485 /* 0x2000, 0x4000 are unused */
487 /* Nonzero if pointers are 64 bits. */
488 #define MASK_PTR64 0x8000
489 #define TARGET_PTR64 (target_flags & MASK_PTR64)
491 /* Nonzero if generating code to run in a 64 bit environment.
492 This is intended to only be used by TARGET_ARCH{32,64} as they are the
493 mechanism used to control compile time or run time selection. */
494 #define MASK_64BIT 0x10000
495 #define TARGET_64BIT (target_flags & MASK_64BIT)
497 /* 0x20000,0x40000 unused */
499 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
500 adding 2047 to %sp. This option is for v9 only and is the default. */
501 #define MASK_STACK_BIAS 0x80000
502 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
504 /* 0x100000,0x200000 unused */
506 /* Non-zero means -m{,no-}fpu was passed on the command line. */
507 #define MASK_FPU_SET 0x400000
508 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
510 /* Use the UltraSPARC Visual Instruction Set extensions. */
511 #define MASK_VIS 0x1000000
512 #define TARGET_VIS (target_flags & MASK_VIS)
514 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
515 the current out and global registers and Linux 2.2+ as well. */
516 #define MASK_V8PLUS 0x2000000
517 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
519 /* Force a the fastest alignment on structures to take advantage of
521 #define MASK_FASTER_STRUCTS 0x4000000
522 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
524 /* Use IEEE quad long double. */
525 #define MASK_LONG_DOUBLE_128 0x8000000
526 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
528 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
529 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
530 to get high 32 bits. False in V8+ or V9 because multiply stores
531 a 64 bit result in a register. */
533 #define TARGET_HARD_MUL32 \
534 ((TARGET_V8 || TARGET_SPARCLITE \
535 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
536 && ! TARGET_V8PLUS && TARGET_ARCH32)
538 #define TARGET_HARD_MUL \
539 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
540 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
543 /* Macro to define tables used to set the flags.
544 This is a list in braces of pairs in braces,
545 each pair being { "NAME", VALUE }
546 where VALUE is the bits to set or minus the bits to clear.
547 An empty string NAME is used to identify the default VALUE. */
549 #define TARGET_SWITCHES \
550 { {"fpu", MASK_FPU | MASK_FPU_SET, \
551 N_("Use hardware fp") }, \
552 {"no-fpu", -MASK_FPU, \
553 N_("Do not use hardware fp") }, \
554 {"no-fpu", MASK_FPU_SET, NULL, }, \
555 {"hard-float", MASK_FPU | MASK_FPU_SET, \
556 N_("Use hardware fp") }, \
557 {"soft-float", -MASK_FPU, \
558 N_("Do not use hardware fp") }, \
559 {"soft-float", MASK_FPU_SET, NULL }, \
560 {"epilogue", MASK_EPILOGUE, \
561 N_("Use function_epilogue()") }, \
562 {"no-epilogue", -MASK_EPILOGUE, \
563 N_("Do not use function_epilogue()") }, \
564 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
565 N_("Assume possible double misalignment") }, \
566 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
567 N_("Assume all doubles are aligned") }, \
568 {"impure-text", MASK_IMPURE_TEXT, \
569 N_("Pass -assert pure-text to linker") }, \
570 {"no-impure-text", -MASK_IMPURE_TEXT, \
571 N_("Do not pass -assert pure-text to linker") }, \
572 {"flat", MASK_FLAT, \
573 N_("Use flat register window model") }, \
574 {"no-flat", -MASK_FLAT, \
575 N_("Do not use flat register window model") }, \
576 {"app-regs", MASK_APP_REGS, \
577 N_("Use ABI reserved registers") }, \
578 {"no-app-regs", -MASK_APP_REGS, \
579 N_("Do not use ABI reserved registers") }, \
580 {"hard-quad-float", MASK_HARD_QUAD, \
581 N_("Use hardware quad fp instructions") }, \
582 {"soft-quad-float", -MASK_HARD_QUAD, \
583 N_("Do not use hardware quad fp instructions") }, \
584 {"v8plus", MASK_V8PLUS, \
585 N_("Compile for v8plus ABI") }, \
586 {"no-v8plus", -MASK_V8PLUS, \
587 N_("Do not compile for v8plus ABI") }, \
589 N_("Utilize Visual Instruction Set") }, \
590 {"no-vis", -MASK_VIS, \
591 N_("Do not utilize Visual Instruction Set") }, \
592 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
594 N_("Optimize for Cypress processors") }, \
596 N_("Optimize for SparcLite processors") }, \
598 N_("Optimize for F930 processors") }, \
600 N_("Optimize for F934 processors") }, \
602 N_("Use V8 Sparc ISA") }, \
604 N_("Optimize for SuperSparc processors") }, \
605 /* End of deprecated options. */ \
606 {"ptr64", MASK_PTR64, \
607 N_("Pointers are 64-bit") }, \
608 {"ptr32", -MASK_PTR64, \
609 N_("Pointers are 32-bit") }, \
610 {"32", -MASK_64BIT, \
611 N_("Use 32-bit ABI") }, \
613 N_("Use 64-bit ABI") }, \
614 {"stack-bias", MASK_STACK_BIAS, \
615 N_("Use stack bias") }, \
616 {"no-stack-bias", -MASK_STACK_BIAS, \
617 N_("Do not use stack bias") }, \
618 {"faster-structs", MASK_FASTER_STRUCTS, \
619 N_("Use structs on stronger alignment for double-word copies") }, \
620 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
621 N_("Do not use structs on stronger alignment for double-word copies") }, \
623 N_("Optimize tail call instructions in assembler and linker") }, \
625 N_("Do not optimize tail call instructions in assembler or linker") }, \
627 { "", TARGET_DEFAULT, ""}}
629 /* MASK_APP_REGS must always be the default because that's what
630 FIXED_REGISTERS is set to and -ffixed- is processed before
631 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
632 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
634 /* This is meant to be redefined in target specific files. */
635 #define SUBTARGET_SWITCHES
638 These must match the values for the cpu attribute in sparc.md. */
639 enum processor_type {
643 PROCESSOR_SUPERSPARC,
647 PROCESSOR_HYPERSPARC,
648 PROCESSOR_SPARCLITE86X,
655 /* This is set from -m{cpu,tune}=xxx. */
656 extern enum processor_type sparc_cpu;
658 /* Recast the cpu class to be the cpu attribute.
659 Every file includes us, but not every file includes insn-attr.h. */
660 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
662 #define TARGET_OPTIONS \
664 { "cpu=", &sparc_select[1].string, \
665 N_("Use features of and schedule code for given CPU") }, \
666 { "tune=", &sparc_select[2].string, \
667 N_("Schedule code for given CPU") }, \
668 { "cmodel=", &sparc_cmodel_string, \
669 N_("Use given Sparc code model") }, \
673 /* This is meant to be redefined in target specific files. */
674 #define SUBTARGET_OPTIONS
676 /* sparc_select[0] is reserved for the default cpu. */
677 struct sparc_cpu_select
680 const char *const name;
681 const int set_tune_p;
682 const int set_arch_p;
685 extern struct sparc_cpu_select sparc_select[];
687 /* target machine storage layout */
689 /* Define this if most significant bit is lowest numbered
690 in instructions that operate on numbered bit-fields. */
691 #define BITS_BIG_ENDIAN 1
693 /* Define this if most significant byte of a word is the lowest numbered. */
694 #define BYTES_BIG_ENDIAN 1
696 /* Define this if most significant word of a multiword number is the lowest
698 #define WORDS_BIG_ENDIAN 1
700 /* Define this to set the endianness to use in libgcc2.c, which can
701 not depend on target_flags. */
702 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
703 #define LIBGCC2_WORDS_BIG_ENDIAN 0
705 #define LIBGCC2_WORDS_BIG_ENDIAN 1
708 #define MAX_BITS_PER_WORD 64
710 /* Width of a word, in units (bytes). */
711 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
712 #define MIN_UNITS_PER_WORD 4
714 /* Now define the sizes of the C data types. */
716 #define SHORT_TYPE_SIZE 16
717 #define INT_TYPE_SIZE 32
718 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
719 #define LONG_LONG_TYPE_SIZE 64
720 #define FLOAT_TYPE_SIZE 32
721 #define DOUBLE_TYPE_SIZE 64
724 #define MAX_LONG_TYPE_SIZE 64
728 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
729 Instead, it is enabled in sol2.h, because it does work under Solaris. */
730 /* Define for support of TFmode long double.
731 Sparc ABI says that long double is 4 words. */
732 #define LONG_DOUBLE_TYPE_SIZE 128
735 /* Width in bits of a pointer.
736 See also the macro `Pmode' defined below. */
737 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
739 /* If we have to extend pointers (only when TARGET_ARCH64 and not
740 TARGET_PTR64), we want to do it unsigned. This macro does nothing
741 if ptr_mode and Pmode are the same. */
742 #define POINTERS_EXTEND_UNSIGNED 1
744 /* A macro to update MODE and UNSIGNEDP when an object whose type
745 is TYPE and which has the specified mode and signedness is to be
746 stored in a register. This macro is only called when TYPE is a
748 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
750 && GET_MODE_CLASS (MODE) == MODE_INT \
751 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
754 /* Define this macro if the promotion described by PROMOTE_MODE
755 should also be done for outgoing function arguments. */
756 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
757 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
759 #define PROMOTE_FUNCTION_ARGS
761 /* Define this macro if the promotion described by PROMOTE_MODE
762 should also be done for the return value of functions.
763 If this macro is defined, FUNCTION_VALUE must perform the same
764 promotions done by PROMOTE_MODE. */
765 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
766 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
768 #define PROMOTE_FUNCTION_RETURN
770 /* Define this macro if the promotion described by PROMOTE_MODE
771 should _only_ be performed for outgoing function arguments or
772 function return values, as specified by PROMOTE_FUNCTION_ARGS
773 and PROMOTE_FUNCTION_RETURN, respectively. */
774 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
775 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
776 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
777 for arithmetic operations which do zero/sign extension at the same time,
778 so without this we end up with a srl/sra after every assignment to an
779 user variable, which means very very bad code. */
780 #define PROMOTE_FOR_CALL_ONLY
782 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
783 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
785 /* Boundary (in *bits*) on which stack pointer should be aligned. */
786 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
788 /* ALIGN FRAMES on double word boundaries */
790 #define SPARC_STACK_ALIGN(LOC) \
791 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
793 /* Allocation boundary (in *bits*) for the code of a function. */
794 #define FUNCTION_BOUNDARY 32
796 /* Alignment of field after `int : 0' in a structure. */
797 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
799 /* Every structure's size must be a multiple of this. */
800 #define STRUCTURE_SIZE_BOUNDARY 8
802 /* A bitfield declared as `int' forces `int' alignment for the struct. */
803 #define PCC_BITFIELD_TYPE_MATTERS 1
805 /* No data type wants to be aligned rounder than this. */
806 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
808 /* The best alignment to use in cases where we have a choice. */
809 #define FASTEST_ALIGNMENT 64
811 /* Define this macro as an expression for the alignment of a structure
812 (given by STRUCT as a tree node) if the alignment computed in the
813 usual way is COMPUTED and the alignment explicitly specified was
816 The default is to use SPECIFIED if it is larger; otherwise, use
817 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
818 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
819 (TARGET_FASTER_STRUCTS ? \
820 ((TREE_CODE (STRUCT) == RECORD_TYPE \
821 || TREE_CODE (STRUCT) == UNION_TYPE \
822 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
823 && TYPE_FIELDS (STRUCT) != 0 \
824 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
825 : MAX ((COMPUTED), (SPECIFIED))) \
826 : MAX ((COMPUTED), (SPECIFIED)))
828 /* Make strings word-aligned so strcpy from constants will be faster. */
829 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
830 ((TREE_CODE (EXP) == STRING_CST \
831 && (ALIGN) < FASTEST_ALIGNMENT) \
832 ? FASTEST_ALIGNMENT : (ALIGN))
834 /* Make arrays of chars word-aligned for the same reasons. */
835 #define DATA_ALIGNMENT(TYPE, ALIGN) \
836 (TREE_CODE (TYPE) == ARRAY_TYPE \
837 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
838 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
840 /* Set this nonzero if move instructions will actually fail to work
841 when given unaligned data. */
842 #define STRICT_ALIGNMENT 1
844 /* Things that must be doubleword aligned cannot go in the text section,
845 because the linker fails to align the text section enough!
846 Put them in the data section. This macro is only used in this file. */
847 #define MAX_TEXT_ALIGN 32
849 /* This forces all variables and constants to the data section when PIC.
850 This is because the SunOS 4 shared library scheme thinks everything in
851 text is a function, and patches the address to point to a loader stub. */
852 /* This is defined to zero for every system which doesn't use the a.out object
854 #ifndef SUNOS4_SHARED_LIBRARIES
855 #define SUNOS4_SHARED_LIBRARIES 0
859 /* Use text section for a constant
860 unless we need more alignment than that offers. */
861 /* This is defined differently for v9 in a cover file. */
862 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
864 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
865 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
871 /* Standard register usage. */
873 /* Number of actual hardware registers.
874 The hardware registers are assigned numbers for the compiler
875 from 0 to just below FIRST_PSEUDO_REGISTER.
876 All registers that the compiler knows about must be given numbers,
877 even those that are not normally considered general registers.
879 SPARC has 32 integer registers and 32 floating point registers.
880 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
881 accessible. We still account for them to simplify register computations
882 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
884 Register 100 is used as the integer condition code register.
885 Register 101 is used as the soft frame pointer register. */
887 #define FIRST_PSEUDO_REGISTER 102
889 #define SPARC_FIRST_FP_REG 32
890 /* Additional V9 fp regs. */
891 #define SPARC_FIRST_V9_FP_REG 64
892 #define SPARC_LAST_V9_FP_REG 95
893 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
894 #define SPARC_FIRST_V9_FCC_REG 96
895 #define SPARC_LAST_V9_FCC_REG 99
897 #define SPARC_FCC_REG 96
898 /* Integer CC reg. We don't distinguish %icc from %xcc. */
899 #define SPARC_ICC_REG 100
901 /* Nonzero if REGNO is an fp reg. */
902 #define SPARC_FP_REG_P(REGNO) \
903 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
905 /* Argument passing regs. */
906 #define SPARC_OUTGOING_INT_ARG_FIRST 8
907 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
908 #define SPARC_FP_ARG_FIRST 32
910 /* 1 for registers that have pervasive standard uses
911 and are not available for the register allocator.
914 g1 is free to use as temporary.
915 g2-g4 are reserved for applications. Gcc normally uses them as
916 temporaries, but this can be disabled via the -mno-app-regs option.
917 g5 through g7 are reserved for the operating system.
920 g1,g5 are free to use as temporaries, and are free to use between calls
921 if the call is to an external function via the PLT.
922 g4 is free to use as a temporary in the non-embedded case.
923 g4 is reserved in the embedded case.
924 g2-g3 are reserved for applications. Gcc normally uses them as
925 temporaries, but this can be disabled via the -mno-app-regs option.
926 g6-g7 are reserved for the operating system (or application in
928 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
929 currently be a fixed register until this pattern is rewritten.
930 Register 1 is also used when restoring call-preserved registers in large
933 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
934 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
937 #define FIXED_REGISTERS \
938 {1, 0, 2, 2, 2, 2, 1, 1, \
939 0, 0, 0, 0, 0, 0, 1, 0, \
940 0, 0, 0, 0, 0, 0, 0, 0, \
941 0, 0, 0, 0, 0, 0, 1, 1, \
943 0, 0, 0, 0, 0, 0, 0, 0, \
944 0, 0, 0, 0, 0, 0, 0, 0, \
945 0, 0, 0, 0, 0, 0, 0, 0, \
946 0, 0, 0, 0, 0, 0, 0, 0, \
948 0, 0, 0, 0, 0, 0, 0, 0, \
949 0, 0, 0, 0, 0, 0, 0, 0, \
950 0, 0, 0, 0, 0, 0, 0, 0, \
951 0, 0, 0, 0, 0, 0, 0, 0, \
955 /* 1 for registers not available across function calls.
956 These must include the FIXED_REGISTERS and also any
957 registers that can be used without being saved.
958 The latter must include the registers where values are returned
959 and the register where structure-value addresses are passed.
960 Aside from that, you can include as many other registers as you like. */
962 #define CALL_USED_REGISTERS \
963 {1, 1, 1, 1, 1, 1, 1, 1, \
964 1, 1, 1, 1, 1, 1, 1, 1, \
965 0, 0, 0, 0, 0, 0, 0, 0, \
966 0, 0, 0, 0, 0, 0, 1, 1, \
968 1, 1, 1, 1, 1, 1, 1, 1, \
969 1, 1, 1, 1, 1, 1, 1, 1, \
970 1, 1, 1, 1, 1, 1, 1, 1, \
971 1, 1, 1, 1, 1, 1, 1, 1, \
973 1, 1, 1, 1, 1, 1, 1, 1, \
974 1, 1, 1, 1, 1, 1, 1, 1, \
975 1, 1, 1, 1, 1, 1, 1, 1, \
976 1, 1, 1, 1, 1, 1, 1, 1, \
980 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
981 they won't be allocated. */
983 #define CONDITIONAL_REGISTER_USAGE \
986 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
988 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
989 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
991 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
992 /* then honour it. */ \
993 if (TARGET_ARCH32 && fixed_regs[5]) \
995 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1000 for (regno = SPARC_FIRST_V9_FP_REG; \
1001 regno <= SPARC_LAST_V9_FP_REG; \
1003 fixed_regs[regno] = 1; \
1004 /* %fcc0 is used by v8 and v9. */ \
1005 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1006 regno <= SPARC_LAST_V9_FCC_REG; \
1008 fixed_regs[regno] = 1; \
1013 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1014 fixed_regs[regno] = 1; \
1016 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1017 /* then honour it. Likewise with g3 and g4. */ \
1018 if (fixed_regs[2] == 2) \
1019 fixed_regs[2] = ! TARGET_APP_REGS; \
1020 if (fixed_regs[3] == 2) \
1021 fixed_regs[3] = ! TARGET_APP_REGS; \
1022 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1023 fixed_regs[4] = ! TARGET_APP_REGS; \
1024 else if (TARGET_CM_EMBMEDANY) \
1025 fixed_regs[4] = 1; \
1026 else if (fixed_regs[4] == 2) \
1027 fixed_regs[4] = 0; \
1030 /* Let the compiler believe the frame pointer is still \
1031 %fp, but output it as %i7. */ \
1032 fixed_regs[31] = 1; \
1033 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1034 /* Disable leaf functions */ \
1035 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1040 /* Return number of consecutive hard regs needed starting at reg REGNO
1041 to hold something of mode MODE.
1042 This is ordinarily the length in words of a value of mode MODE
1043 but can be less for certain modes in special long registers.
1045 On SPARC, ordinary registers hold 32 bits worth;
1046 this means both integer and floating point registers.
1047 On v9, integer regs hold 64 bits worth; floating point regs hold
1048 32 bits worth (this includes the new fp regs as even the odd ones are
1049 included in the hard register count). */
1051 #define HARD_REGNO_NREGS(REGNO, MODE) \
1053 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1054 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1055 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1056 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1058 /* Due to the ARCH64 descrepancy above we must override this next
1060 #define REGMODE_NATURAL_SIZE(MODE) \
1061 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1063 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1064 See sparc.c for how we initialize this. */
1065 extern const int *hard_regno_mode_classes;
1066 extern int sparc_mode_class[];
1068 /* ??? Because of the funny way we pass parameters we should allow certain
1069 ??? types of float/complex values to be in integer registers during
1070 ??? RTL generation. This only matters on arch32. */
1071 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1072 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1074 /* Value is 1 if it is a good idea to tie two pseudo registers
1075 when one has mode MODE1 and one has mode MODE2.
1076 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1077 for any hard reg, then this must be 0 for correct output.
1079 For V9: SFmode can't be combined with other float modes, because they can't
1080 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1081 registers, but SFmode will. */
1082 #define MODES_TIEABLE_P(MODE1, MODE2) \
1083 ((MODE1) == (MODE2) \
1084 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1086 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1087 || (MODE1 != SFmode && MODE2 != SFmode)))))
1089 /* Specify the registers used for certain standard purposes.
1090 The values of these macros are register numbers. */
1092 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1093 /* #define PC_REGNUM */
1095 /* Register to use for pushing function arguments. */
1096 #define STACK_POINTER_REGNUM 14
1098 /* The stack bias (amount by which the hardware register is offset by). */
1099 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1101 /* Actual top-of-stack address is 92/176 greater than the contents of the
1102 stack pointer register for !v9/v9. That is:
1103 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1104 address, and 6*4 bytes for the 6 register parameters.
1105 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1107 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1109 /* Base register for access to local variables of the function. */
1110 #define HARD_FRAME_POINTER_REGNUM 30
1112 /* The soft frame pointer does not have the stack bias applied. */
1113 #define FRAME_POINTER_REGNUM 101
1115 /* Given the stack bias, the stack pointer isn't actually aligned. */
1116 #define INIT_EXPANDERS \
1118 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1120 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1121 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1125 /* Value should be nonzero if functions must have frame pointers.
1126 Zero means the frame pointer need not be set up (and parms
1127 may be accessed via the stack pointer) in functions that seem suitable.
1128 This is computed in `reload', in reload1.c.
1129 Used in flow.c, global.c, and reload1.c.
1131 Being a non-leaf function does not mean a frame pointer is needed in the
1132 flat window model. However, the debugger won't be able to backtrace through
1134 #define FRAME_POINTER_REQUIRED \
1136 ? (current_function_calls_alloca \
1137 || current_function_varargs \
1138 || !leaf_function_p ()) \
1139 : ! (leaf_function_p () && only_leaf_regs_used ()))
1141 /* Base register for access to arguments of the function. */
1142 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1144 /* Register in which static-chain is passed to a function. This must
1145 not be a register used by the prologue. */
1146 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1148 /* Register which holds offset table for position-independent
1151 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1153 /* Pick a default value we can notice from override_options:
1155 v9: Default is off. */
1157 #define DEFAULT_PCC_STRUCT_RETURN -1
1159 /* Sparc ABI says that quad-precision floats and all structures are returned
1161 For v9: unions <= 32 bytes in size are returned in int regs,
1162 structures up to 32 bytes are returned in int and fp regs. */
1164 #define RETURN_IN_MEMORY(TYPE) \
1166 ? (TYPE_MODE (TYPE) == BLKmode \
1167 || TYPE_MODE (TYPE) == TFmode \
1168 || TYPE_MODE (TYPE) == TCmode) \
1169 : (TYPE_MODE (TYPE) == BLKmode \
1170 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1172 /* Functions which return large structures get the address
1173 to place the wanted value at offset 64 from the frame.
1174 Must reserve 64 bytes for the in and local registers.
1175 v9: Functions which return large structures get the address to place the
1176 wanted value from an invisible first argument. */
1177 /* Used only in other #defines in this file. */
1178 #define STRUCT_VALUE_OFFSET 64
1180 #define STRUCT_VALUE \
1183 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1184 STRUCT_VALUE_OFFSET)))
1186 #define STRUCT_VALUE_INCOMING \
1189 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1190 STRUCT_VALUE_OFFSET)))
1192 /* Define the classes of registers for register constraints in the
1193 machine description. Also define ranges of constants.
1195 One of the classes must always be named ALL_REGS and include all hard regs.
1196 If there is more than one class, another class must be named NO_REGS
1197 and contain no registers.
1199 The name GENERAL_REGS must be the name of a class (or an alias for
1200 another name such as ALL_REGS). This is the class of registers
1201 that is allowed by "g" or "r" in a register constraint.
1202 Also, registers outside this class are allocated only when
1203 instructions express preferences for them.
1205 The classes must be numbered in nondecreasing order; that is,
1206 a larger-numbered class must never be contained completely
1207 in a smaller-numbered class.
1209 For any two classes, it is very desirable that there be another
1210 class that represents their union. */
1212 /* The SPARC has various kinds of registers: general, floating point,
1213 and condition codes [well, it has others as well, but none that we
1214 care directly about].
1216 For v9 we must distinguish between the upper and lower floating point
1217 registers because the upper ones can't hold SFmode values.
1218 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1219 satisfying a group need for a class will also satisfy a single need for
1220 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1223 It is important that one class contains all the general and all the standard
1224 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1225 because reg_class_record() will bias the selection in favor of fp regs,
1226 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1227 because FP_REGS > GENERAL_REGS.
1229 It is also important that one class contain all the general and all the
1230 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1231 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1232 allocate_reload_reg() to bypass it causing an abort because the compiler
1233 thinks it doesn't have a spill reg when in fact it does.
1235 v9 also has 4 floating point condition code registers. Since we don't
1236 have a class that is the union of FPCC_REGS with either of the others,
1237 it is important that it appear first. Otherwise the compiler will die
1238 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1241 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1242 may try to use it to hold an SImode value. See register_operand.
1243 ??? Should %fcc[0123] be handled similarly?
1246 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1247 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1248 ALL_REGS, LIM_REG_CLASSES };
1250 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1252 /* Give names of register classes as strings for dump file. */
1254 #define REG_CLASS_NAMES \
1255 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1256 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1259 /* Define which registers fit in which classes.
1260 This is an initializer for a vector of HARD_REG_SET
1261 of length N_REG_CLASSES. */
1263 #define REG_CLASS_CONTENTS \
1264 {{0, 0, 0, 0}, /* NO_REGS */ \
1265 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1266 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1267 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1268 {0, -1, 0, 0}, /* FP_REGS */ \
1269 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1270 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1271 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1272 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1274 /* The same information, inverted:
1275 Return the class number of the smallest class containing
1276 reg number REGNO. This could be a conditional expression
1277 or could index an array. */
1279 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1281 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1283 /* This is the order in which to allocate registers normally.
1285 We put %f0/%f1 last among the float registers, so as to make it more
1286 likely that a pseudo-register which dies in the float return register
1287 will get allocated to the float return register, thus saving a move
1288 instruction at the end of the function. */
1290 #define REG_ALLOC_ORDER \
1291 { 8, 9, 10, 11, 12, 13, 2, 3, \
1292 15, 16, 17, 18, 19, 20, 21, 22, \
1293 23, 24, 25, 26, 27, 28, 29, 31, \
1294 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1295 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1296 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1297 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1298 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1299 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1300 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1301 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1302 32, 33, /* %f0,%f1 */ \
1303 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1304 1, 4, 5, 6, 7, 0, 14, 30, 101}
1306 /* This is the order in which to allocate registers for
1307 leaf functions. If all registers can fit in the "gi" registers,
1308 then we have the possibility of having a leaf function. */
1310 #define REG_LEAF_ALLOC_ORDER \
1311 { 2, 3, 24, 25, 26, 27, 28, 29, \
1313 15, 8, 9, 10, 11, 12, 13, \
1314 16, 17, 18, 19, 20, 21, 22, 23, \
1315 34, 35, 36, 37, 38, 39, \
1316 40, 41, 42, 43, 44, 45, 46, 47, \
1317 48, 49, 50, 51, 52, 53, 54, 55, \
1318 56, 57, 58, 59, 60, 61, 62, 63, \
1319 64, 65, 66, 67, 68, 69, 70, 71, \
1320 72, 73, 74, 75, 76, 77, 78, 79, \
1321 80, 81, 82, 83, 84, 85, 86, 87, \
1322 88, 89, 90, 91, 92, 93, 94, 95, \
1324 96, 97, 98, 99, 100, \
1327 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1329 extern char sparc_leaf_regs[];
1330 #define LEAF_REGISTERS sparc_leaf_regs
1332 extern const char leaf_reg_remap[];
1333 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1335 /* The class value for index registers, and the one for base regs. */
1336 #define INDEX_REG_CLASS GENERAL_REGS
1337 #define BASE_REG_CLASS GENERAL_REGS
1339 /* Local macro to handle the two v9 classes of FP regs. */
1340 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1342 /* Get reg_class from a letter such as appears in the machine description.
1343 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1344 .md file for v8 and v9.
1345 'd' and 'b' are used for single and double precision VIS operations,
1347 'h' is used for V8+ 64 bit global and out registers. */
1349 #define REG_CLASS_FROM_LETTER(C) \
1351 ? ((C) == 'f' ? FP_REGS \
1352 : (C) == 'e' ? EXTRA_FP_REGS \
1353 : (C) == 'c' ? FPCC_REGS \
1354 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1355 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1356 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1358 : ((C) == 'f' ? FP_REGS \
1359 : (C) == 'e' ? FP_REGS \
1360 : (C) == 'c' ? FPCC_REGS \
1363 /* The letters I, J, K, L and M in a register constraint string
1364 can be used to stand for particular ranges of immediate operands.
1365 This macro defines what the ranges are.
1366 C is the letter, and VALUE is a constant value.
1367 Return 1 if VALUE is in the range specified by C.
1369 `I' is used for the range of constants an insn can actually contain.
1370 `J' is used for the range which is just zero (since that is R0).
1371 `K' is used for constants which can be loaded with a single sethi insn.
1372 `L' is used for the range of constants supported by the movcc insns.
1373 `M' is used for the range of constants supported by the movrcc insns.
1374 `N' is like K, but for constants wider than 32 bits. */
1376 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1377 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1378 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1379 /* 10 and 11 bit immediates are only used for a few specific insns.
1380 SMALL_INT is used throughout the port so we continue to use it. */
1381 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1382 /* 13 bit immediate, considering only the low 32 bits */
1383 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1384 (INTVAL (X), SImode)))
1385 #define SPARC_SETHI_P(X) \
1386 (((unsigned HOST_WIDE_INT) (X) \
1387 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1388 #define SPARC_SETHI32_P(X) \
1389 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1391 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1392 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1393 : (C) == 'J' ? (VALUE) == 0 \
1394 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1395 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1396 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1397 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1400 /* Similar, but for floating constants, and defining letters G and H.
1401 Here VALUE is the CONST_DOUBLE rtx itself. */
1403 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1404 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1405 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1408 /* Given an rtx X being reloaded into a reg required to be
1409 in class CLASS, return the class of reg to actually use.
1410 In general this is just CLASS; but on some machines
1411 in some cases it is preferable to use a more restrictive class. */
1412 /* - We can't load constants into FP registers.
1413 - We can't load FP constants into integer registers when soft-float,
1414 because there is no soft-float pattern with a r/F constraint.
1415 - We can't load FP constants into integer registers for TFmode unless
1416 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1417 - Try and reload integer constants (symbolic or otherwise) back into
1418 registers directly, rather than having them dumped to memory. */
1420 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1422 ? ((FP_REG_CLASS_P (CLASS) \
1423 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1425 || (GET_MODE (X) == TFmode \
1426 && ! fp_zero_operand (X, TFmode))) \
1428 : (!FP_REG_CLASS_P (CLASS) \
1429 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1434 /* Return the register class of a scratch register needed to load IN into
1435 a register of class CLASS in MODE.
1437 We need a temporary when loading/storing a HImode/QImode value
1438 between memory and the FPU registers. This can happen when combine puts
1439 a paradoxical subreg in a float/fix conversion insn. */
1441 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1442 ((FP_REG_CLASS_P (CLASS) \
1443 && ((MODE) == HImode || (MODE) == QImode) \
1444 && (GET_CODE (IN) == MEM \
1445 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1446 && true_regnum (IN) == -1))) \
1448 : (((TARGET_CM_MEDANY \
1449 && symbolic_operand ((IN), (MODE))) \
1450 || (TARGET_CM_EMBMEDANY \
1451 && text_segment_operand ((IN), (MODE)))) \
1456 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1457 ((FP_REG_CLASS_P (CLASS) \
1458 && ((MODE) == HImode || (MODE) == QImode) \
1459 && (GET_CODE (IN) == MEM \
1460 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1461 && true_regnum (IN) == -1))) \
1463 : (((TARGET_CM_MEDANY \
1464 && symbolic_operand ((IN), (MODE))) \
1465 || (TARGET_CM_EMBMEDANY \
1466 && text_segment_operand ((IN), (MODE)))) \
1471 /* On SPARC it is not possible to directly move data between
1472 GENERAL_REGS and FP_REGS. */
1473 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1474 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1476 /* Return the stack location to use for secondary memory needed reloads.
1477 We want to use the reserved location just below the frame pointer.
1478 However, we must ensure that there is a frame, so use assign_stack_local
1479 if the frame size is zero. */
1480 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1481 (get_frame_size () == 0 \
1482 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1483 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1484 STARTING_FRAME_OFFSET)))
1486 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1487 because the movsi and movsf patterns don't handle r/f moves.
1488 For v8 we copy the default definition. */
1489 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1491 ? (GET_MODE_BITSIZE (MODE) < 32 \
1492 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1494 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1495 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1498 /* Return the maximum number of consecutive registers
1499 needed to represent mode MODE in a register of class CLASS. */
1500 /* On SPARC, this is the size of MODE in words. */
1501 #define CLASS_MAX_NREGS(CLASS, MODE) \
1502 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1503 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1505 /* Stack layout; function entry, exit and calling. */
1507 /* Define the number of register that can hold parameters.
1508 This macro is only used in other macro definitions below and in sparc.c.
1509 MODE is the mode of the argument.
1510 !v9: All args are passed in %o0-%o5.
1511 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1512 See the description in sparc.c. */
1513 #define NPARM_REGS(MODE) \
1515 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1518 /* Define this if pushing a word on the stack
1519 makes the stack pointer a smaller address. */
1520 #define STACK_GROWS_DOWNWARD
1522 /* Define this if the nominal address of the stack frame
1523 is at the high-address end of the local variables;
1524 that is, each additional local variable allocated
1525 goes at a more negative offset in the frame. */
1526 #define FRAME_GROWS_DOWNWARD
1528 /* Offset within stack frame to start allocating local variables at.
1529 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1530 first local allocated. Otherwise, it is the offset to the BEGINNING
1531 of the first local allocated. */
1532 /* This allows space for one TFmode floating point value. */
1533 #define STARTING_FRAME_OFFSET \
1534 (TARGET_ARCH64 ? -16 \
1535 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1537 /* If we generate an insn to push BYTES bytes,
1538 this says how many the stack pointer really advances by.
1539 On SPARC, don't define this because there are no push insns. */
1540 /* #define PUSH_ROUNDING(BYTES) */
1542 /* Offset of first parameter from the argument pointer register value.
1543 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1544 even if this function isn't going to use it.
1545 v9: This is 128 for the ins and locals. */
1546 #define FIRST_PARM_OFFSET(FNDECL) \
1547 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1549 /* Offset from the argument pointer register value to the CFA.
1550 This is different from FIRST_PARM_OFFSET because the register window
1551 comes between the CFA and the arguments. */
1552 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1554 /* When a parameter is passed in a register, stack space is still
1556 !v9: All 6 possible integer registers have backing store allocated.
1557 v9: Only space for the arguments passed is allocated. */
1558 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1559 meaning to the backend. Further, we need to be able to detect if a
1560 varargs/unprototyped function is called, as they may want to spill more
1561 registers than we've provided space. Ugly, ugly. So for now we retain
1562 all 6 slots even for v9. */
1563 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1565 /* Definitions for register elimination. */
1566 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1568 #define ELIMINABLE_REGS \
1569 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1570 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1572 /* The way this is structured, we can't eliminate SFP in favor of SP
1573 if the frame pointer is required: we want to use the SFP->HFP elimination
1574 in that case. But the test in update_eliminables doesn't know we are
1575 assuming below that we only do the former elimination. */
1576 #define CAN_ELIMINATE(FROM, TO) \
1577 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1579 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1582 if ((TO) == STACK_POINTER_REGNUM) \
1584 /* Note, we always pretend that this is a leaf function \
1585 because if it's not, there's no point in trying to \
1586 eliminate the frame pointer. If it is a leaf \
1587 function, we guessed right! */ \
1590 sparc_flat_compute_frame_size (get_frame_size ()); \
1592 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1594 (OFFSET) += SPARC_STACK_BIAS; \
1597 /* Keep the stack pointer constant throughout the function.
1598 This is both an optimization and a necessity: longjmp
1599 doesn't behave itself when the stack pointer moves within
1601 #define ACCUMULATE_OUTGOING_ARGS 1
1603 /* Value is the number of bytes of arguments automatically
1604 popped when returning from a subroutine call.
1605 FUNDECL is the declaration node of the function (as a tree),
1606 FUNTYPE is the data type of the function (as a tree),
1607 or for a library call it is an identifier node for the subroutine name.
1608 SIZE is the number of bytes of arguments passed on the stack. */
1610 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1612 /* Some subroutine macros specific to this machine.
1613 When !TARGET_FPU, put float return values in the general registers,
1614 since we don't have any fp registers. */
1615 #define BASE_RETURN_VALUE_REG(MODE) \
1617 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1618 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1620 #define BASE_OUTGOING_VALUE_REG(MODE) \
1622 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1623 : TARGET_FLAT ? 8 : 24) \
1624 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1625 : (TARGET_FLAT ? 8 : 24)))
1627 #define BASE_PASSING_ARG_REG(MODE) \
1629 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1632 /* ??? FIXME -- seems wrong for v9 structure passing... */
1633 #define BASE_INCOMING_ARG_REG(MODE) \
1635 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1636 : TARGET_FLAT ? 8 : 24) \
1637 : (TARGET_FLAT ? 8 : 24))
1639 /* Define this macro if the target machine has "register windows". This
1640 C expression returns the register number as seen by the called function
1641 corresponding to register number OUT as seen by the calling function.
1642 Return OUT if register number OUT is not an outbound register. */
1644 #define INCOMING_REGNO(OUT) \
1645 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1647 /* Define this macro if the target machine has "register windows". This
1648 C expression returns the register number as seen by the calling function
1649 corresponding to register number IN as seen by the called function.
1650 Return IN if register number IN is not an inbound register. */
1652 #define OUTGOING_REGNO(IN) \
1653 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1655 /* Define this macro if the target machine has register windows. This
1656 C expression returns true if the register is call-saved but is in the
1659 #define LOCAL_REGNO(REGNO) \
1660 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1662 /* Define how to find the value returned by a function.
1663 VALTYPE is the data type of the value (as a tree).
1664 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1665 otherwise, FUNC is 0. */
1667 /* On SPARC the value is found in the first "output" register. */
1669 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1670 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1672 /* But the called function leaves it in the first "input" register. */
1674 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1675 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1677 /* Define how to find the value returned by a library function
1678 assuming the value has mode MODE. */
1680 #define LIBCALL_VALUE(MODE) \
1681 function_value (NULL_TREE, (MODE), 1)
1683 /* 1 if N is a possible register number for a function value
1684 as seen by the caller.
1685 On SPARC, the first "output" reg is used for integer values,
1686 and the first floating point register is used for floating point values. */
1688 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1690 /* Define the size of space to allocate for the return value of an
1693 #define APPLY_RESULT_SIZE 16
1695 /* 1 if N is a possible register number for function argument passing.
1696 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1698 #define FUNCTION_ARG_REGNO_P(N) \
1700 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1701 : ((N) >= 8 && (N) <= 13))
1703 /* Define a data type for recording info about an argument list
1704 during the scan of that argument list. This data type should
1705 hold all necessary information about the function itself
1706 and about the args processed so far, enough to enable macros
1707 such as FUNCTION_ARG to determine where the next arg should go.
1709 On SPARC (!v9), this is a single integer, which is a number of words
1710 of arguments scanned so far (including the invisible argument,
1711 if any, which holds the structure-value-address).
1712 Thus 7 or more means all following args should go on the stack.
1714 For v9, we also need to know whether a prototype is present. */
1717 int words; /* number of words passed so far */
1718 int prototype_p; /* non-zero if a prototype is present */
1719 int libcall_p; /* non-zero if a library call */
1721 #define CUMULATIVE_ARGS struct sparc_args
1723 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1724 for a call to a function whose data type is FNTYPE.
1725 For a library call, FNTYPE is 0. */
1727 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1728 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1730 /* Update the data in CUM to advance over an argument
1731 of mode MODE and data type TYPE.
1732 TYPE is null for libcalls where that information may not be available. */
1734 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1735 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1737 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1739 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1741 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1742 || TREE_ADDRESSABLE (TYPE)))
1744 /* Determine where to put an argument to a function.
1745 Value is zero to push the argument on the stack,
1746 or a hard register in which to store the argument.
1748 MODE is the argument's machine mode.
1749 TYPE is the data type of the argument (as a tree).
1750 This is null for libcalls where that information may
1752 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1753 the preceding args and about the function being called.
1754 NAMED is nonzero if this argument is a named parameter
1755 (otherwise it is an extra parameter matching an ellipsis). */
1757 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1758 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1760 /* Define where a function finds its arguments.
1761 This is different from FUNCTION_ARG because of register windows. */
1763 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1764 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1766 /* For an arg passed partly in registers and partly in memory,
1767 this is the number of registers used.
1768 For args passed entirely in registers or entirely in memory, zero. */
1770 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1771 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1773 /* A C expression that indicates when an argument must be passed by reference.
1774 If nonzero for an argument, a copy of that argument is made in memory and a
1775 pointer to the argument is passed instead of the argument itself.
1776 The pointer is passed in whatever way is appropriate for passing a pointer
1779 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1780 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1782 /* If defined, a C expression which determines whether, and in which direction,
1783 to pad out an argument with extra space. The value should be of type
1784 `enum direction': either `upward' to pad above the argument,
1785 `downward' to pad below, or `none' to inhibit padding. */
1787 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1788 function_arg_padding ((MODE), (TYPE))
1790 /* If defined, a C expression that gives the alignment boundary, in bits,
1791 of an argument with the specified mode and type. If it is not defined,
1792 PARM_BOUNDARY is used for all arguments.
1793 For sparc64, objects requiring 16 byte alignment are passed that way. */
1795 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1797 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1798 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1799 ? 128 : PARM_BOUNDARY)
1801 /* Define the information needed to generate branch and scc insns. This is
1802 stored from the compare operation. Note that we can't use "rtx" here
1803 since it hasn't been defined! */
1805 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1808 /* Generate the special assembly code needed to tell the assembler whatever
1809 it might need to know about the return value of a function.
1811 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1812 information to the assembler relating to peephole optimization (done in
1815 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1816 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1818 /* Output the special assembly code needed to tell the assembler some
1819 register is used as global register variable.
1821 SPARC 64bit psABI declares registers %g2 and %g3 as application
1822 registers and %g6 and %g7 as OS registers. Any object using them
1823 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1824 and how they are used (scratch or some global variable).
1825 Linker will then refuse to link together objects which use those
1826 registers incompatibly.
1828 Unless the registers are used for scratch, two different global
1829 registers cannot be declared to the same name, so in the unlikely
1830 case of a global register variable occupying more than one register
1831 we prefix the second and following registers with .gnu.part1. etc. */
1833 extern char sparc_hard_reg_printed[8];
1835 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1836 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1838 if (TARGET_ARCH64) \
1840 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1842 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1843 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1845 if (reg == (REGNO)) \
1846 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1848 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1849 reg, reg - (REGNO), (NAME)); \
1850 sparc_hard_reg_printed[reg] = 1; \
1857 /* Output assembler code to FILE to increment profiler label # LABELNO
1858 for profiling a function entry. */
1860 #define FUNCTION_PROFILER(FILE, LABELNO) \
1861 sparc_function_profiler(FILE, LABELNO)
1863 /* Set the name of the mcount function for the system. */
1865 #define MCOUNT_FUNCTION "*mcount"
1867 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1868 the stack pointer does not matter. The value is tested only in
1869 functions that have frame pointers.
1870 No definition is equivalent to always zero. */
1872 #define EXIT_IGNORE_STACK \
1873 (get_frame_size () != 0 \
1874 || current_function_calls_alloca || current_function_outgoing_args_size)
1876 #define DELAY_SLOTS_FOR_EPILOGUE \
1877 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1878 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1879 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1880 : eligible_for_epilogue_delay (trial, slots_filled))
1882 /* Define registers used by the epilogue and return instruction. */
1883 #define EPILOGUE_USES(REGNO) \
1884 (!TARGET_FLAT && REGNO == 31)
1886 /* Length in units of the trampoline for entering a nested function. */
1888 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1890 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1892 /* Emit RTL insns to initialize the variable parts of a trampoline.
1893 FNADDR is an RTX for the address of the function's pure code.
1894 CXT is an RTX for the static chain value for the function. */
1896 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1897 if (TARGET_ARCH64) \
1898 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1900 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1902 /* Generate necessary RTL for __builtin_saveregs(). */
1904 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1906 /* Implement `va_start' for varargs and stdarg. */
1907 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1908 sparc_va_start (stdarg, valist, nextarg)
1910 /* Implement `va_arg'. */
1911 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1912 sparc_va_arg (valist, type)
1914 /* Define this macro if the location where a function argument is passed
1915 depends on whether or not it is a named argument.
1917 This macro controls how the NAMED argument to FUNCTION_ARG
1918 is set for varargs and stdarg functions. With this macro defined,
1919 the NAMED argument is always true for named arguments, and false for
1920 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1921 is defined, then all arguments are treated as named. Otherwise, all named
1922 arguments except the last are treated as named.
1923 For the v9 we want NAMED to mean what it says it means. */
1925 #define STRICT_ARGUMENT_NAMING TARGET_V9
1927 /* We do not allow sibling calls if -mflat, nor
1928 we do not allow indirect calls to be optimized into sibling calls. */
1929 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
1931 /* Generate RTL to flush the register windows so as to make arbitrary frames
1933 #define SETUP_FRAME_ADDRESSES() \
1934 emit_insn (gen_flush_register_windows ())
1936 /* Given an rtx for the address of a frame,
1937 return an rtx for the address of the word in the frame
1938 that holds the dynamic chain--the previous frame's address.
1939 ??? -mflat support? */
1940 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
1942 /* The return address isn't on the stack, it is in a register, so we can't
1943 access it from the current frame pointer. We can access it from the
1944 previous frame pointer though by reading a value from the register window
1946 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1948 /* This is the offset of the return address to the true next instruction to be
1949 executed for the current function. */
1950 #define RETURN_ADDR_OFFSET \
1951 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1953 /* The current return address is in %i7. The return address of anything
1954 farther back is in the register window save area at [%fp+60]. */
1955 /* ??? This ignores the fact that the actual return address is +8 for normal
1956 returns, and +12 for structure returns. */
1957 #define RETURN_ADDR_RTX(count, frame) \
1959 ? gen_rtx_REG (Pmode, 31) \
1960 : gen_rtx_MEM (Pmode, \
1961 memory_address (Pmode, plus_constant (frame, \
1962 15 * UNITS_PER_WORD \
1963 + SPARC_STACK_BIAS))))
1965 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1966 +12, but always using +8 is close enough for frame unwind purposes.
1967 Actually, just using %o7 is close enough for unwinding, but %o7+8
1968 is something you can return to. */
1969 #define INCOMING_RETURN_ADDR_RTX \
1970 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1971 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1973 /* The offset from the incoming value of %sp to the top of the stack frame
1974 for the current function. On sparc64, we have to account for the stack
1976 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1978 /* Describe how we implement __builtin_eh_return. */
1979 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1980 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1981 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1983 /* Select a format to encode pointers in exception handling data. CODE
1984 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1985 true if the symbol may be affected by dynamic relocations.
1987 If assembler and linker properly support .uaword %r_disp32(foo),
1988 then use PC relative 32-bit relocations instead of absolute relocs
1989 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1990 for binaries, to save memory. */
1991 #ifdef HAVE_AS_SPARC_UA_PCREL
1992 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1994 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1995 : ((TARGET_ARCH64 && ! GLOBAL) \
1996 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1999 /* Emit a PC-relative relocation. */
2000 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2002 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2003 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2004 assemble_name (FILE, LABEL); \
2005 fputc (')', FILE); \
2009 /* Addressing modes, and classification of registers for them. */
2011 /* #define HAVE_POST_INCREMENT 0 */
2012 /* #define HAVE_POST_DECREMENT 0 */
2014 /* #define HAVE_PRE_DECREMENT 0 */
2015 /* #define HAVE_PRE_INCREMENT 0 */
2017 /* Macros to check register numbers against specific register classes. */
2019 /* These assume that REGNO is a hard or pseudo reg number.
2020 They give nonzero only if REGNO is a hard reg of the suitable class
2021 or a pseudo reg currently allocated to a suitable hard reg.
2022 Since they use reg_renumber, they are safe only once reg_renumber
2023 has been allocated, which happens in local-alloc.c. */
2025 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2026 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2027 || (REGNO) == FRAME_POINTER_REGNUM \
2028 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2030 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2032 #define REGNO_OK_FOR_FP_P(REGNO) \
2033 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2034 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2035 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2037 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2038 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2040 /* Now macros that check whether X is a register and also,
2041 strictly, whether it is in a specified class.
2043 These macros are specific to the SPARC, and may be used only
2044 in code for printing assembler insns and in conditions for
2045 define_optimization. */
2047 /* 1 if X is an fp register. */
2049 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2051 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2052 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2054 /* Maximum number of registers that can appear in a valid memory address. */
2056 #define MAX_REGS_PER_ADDRESS 2
2058 /* Recognize any constant value that is a valid address.
2059 When PIC, we do not accept an address that would require a scratch reg
2060 to load into a register. */
2062 #define CONSTANT_ADDRESS_P(X) \
2063 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2064 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2065 || (GET_CODE (X) == CONST \
2066 && ! (flag_pic && pic_address_needs_scratch (X))))
2068 /* Define this, so that when PIC, reload won't try to reload invalid
2069 addresses which require two reload registers. */
2071 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2073 /* Nonzero if the constant value X is a legitimate general operand.
2074 Anything can be made to work except floating point constants.
2075 If TARGET_VIS, 0.0 can be made to work as well. */
2077 #define LEGITIMATE_CONSTANT_P(X) \
2078 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2080 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2081 GET_MODE (X) == TFmode) && \
2082 fp_zero_operand (X, GET_MODE (X))))
2084 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2085 and check its validity for a certain class.
2086 We have two alternate definitions for each of them.
2087 The usual definition accepts all pseudo regs; the other rejects
2088 them unless they have been allocated suitable hard regs.
2089 The symbol REG_OK_STRICT causes the latter definition to be used.
2091 Most source files want to accept pseudo regs in the hope that
2092 they will get allocated to the class that the insn wants them to be in.
2093 Source files for reload pass need to be strict.
2094 After reload, it makes no difference, since pseudo regs have
2095 been eliminated by then. */
2097 /* Optional extra constraints for this machine.
2099 'Q' handles floating point constants which can be moved into
2100 an integer register with a single sethi instruction.
2102 'R' handles floating point constants which can be moved into
2103 an integer register with a single mov instruction.
2105 'S' handles floating point constants which can be moved into
2106 an integer register using a high/lo_sum sequence.
2108 'T' handles memory addresses where the alignment is known to
2109 be at least 8 bytes.
2111 `U' handles all pseudo registers or a hard even numbered
2112 integer register, needed for ldd/std instructions. */
2114 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2115 ((C) == 'Q' ? fp_sethi_p(OP) \
2116 : (C) == 'R' ? fp_mov_p(OP) \
2117 : (C) == 'S' ? fp_high_losum_p(OP) \
2120 #ifndef REG_OK_STRICT
2122 /* Nonzero if X is a hard reg that can be used as an index
2123 or if it is a pseudo reg. */
2124 #define REG_OK_FOR_INDEX_P(X) \
2126 || REGNO (X) == FRAME_POINTER_REGNUM \
2127 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2129 /* Nonzero if X is a hard reg that can be used as a base reg
2130 or if it is a pseudo reg. */
2131 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2133 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2135 #define EXTRA_CONSTRAINT(OP, C) \
2136 (EXTRA_CONSTRAINT_BASE(OP, C) \
2137 || ((! TARGET_ARCH64 && (C) == 'T') \
2138 ? (mem_min_alignment (OP, 8)) \
2139 : ((! TARGET_ARCH64 && (C) == 'U') \
2140 ? (register_ok_for_ldd (OP)) \
2145 /* Nonzero if X is a hard reg that can be used as an index. */
2146 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2147 /* Nonzero if X is a hard reg that can be used as a base reg. */
2148 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2150 #define EXTRA_CONSTRAINT(OP, C) \
2151 (EXTRA_CONSTRAINT_BASE(OP, C) \
2152 || ((! TARGET_ARCH64 && (C) == 'T') \
2153 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2154 : ((! TARGET_ARCH64 && (C) == 'U') \
2155 ? (GET_CODE (OP) == REG \
2156 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2157 || reg_renumber[REGNO (OP)] >= 0) \
2158 && register_ok_for_ldd (OP)) \
2163 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2165 #ifdef HAVE_AS_OFFSETABLE_LO10
2166 #define USE_AS_OFFSETABLE_LO10 1
2168 #define USE_AS_OFFSETABLE_LO10 0
2171 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2172 that is a valid memory address for an instruction.
2173 The MODE argument is the machine mode for the MEM expression
2174 that wants to use this address.
2176 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2177 ordinarily. This changes a bit when generating PIC.
2179 If you change this, execute "rm explow.o recog.o reload.o". */
2181 #define RTX_OK_FOR_BASE_P(X) \
2182 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2183 || (GET_CODE (X) == SUBREG \
2184 && GET_CODE (SUBREG_REG (X)) == REG \
2185 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2187 #define RTX_OK_FOR_INDEX_P(X) \
2188 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2189 || (GET_CODE (X) == SUBREG \
2190 && GET_CODE (SUBREG_REG (X)) == REG \
2191 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2193 #define RTX_OK_FOR_OFFSET_P(X) \
2194 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2196 #define RTX_OK_FOR_OLO10_P(X) \
2197 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2199 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2200 { if (RTX_OK_FOR_BASE_P (X)) \
2202 else if (GET_CODE (X) == PLUS) \
2204 register rtx op0 = XEXP (X, 0); \
2205 register rtx op1 = XEXP (X, 1); \
2206 if (flag_pic && op0 == pic_offset_table_rtx) \
2208 if (RTX_OK_FOR_BASE_P (op1)) \
2210 else if (flag_pic == 1 \
2211 && GET_CODE (op1) != REG \
2212 && GET_CODE (op1) != LO_SUM \
2213 && GET_CODE (op1) != MEM \
2214 && (GET_CODE (op1) != CONST_INT \
2215 || SMALL_INT (op1))) \
2218 else if (RTX_OK_FOR_BASE_P (op0)) \
2220 if ((RTX_OK_FOR_INDEX_P (op1) \
2221 /* We prohibit REG + REG for TFmode when \
2222 there are no instructions which accept \
2223 REG+REG instructions. We do this \
2224 because REG+REG is not an offsetable \
2225 address. If we get the situation \
2226 in reload where source and destination \
2227 of a movtf pattern are both MEMs with \
2228 REG+REG address, then only one of them \
2229 gets converted to an offsetable \
2231 && (MODE != TFmode \
2232 || (TARGET_FPU && TARGET_ARCH64 \
2234 && TARGET_HARD_QUAD)) \
2235 /* We prohibit REG + REG on ARCH32 if \
2236 not optimizing for DFmode/DImode \
2237 because then mem_min_alignment is \
2238 likely to be zero after reload and the \
2239 forced split would lack a matching \
2240 splitter pattern. */ \
2241 && (TARGET_ARCH64 || optimize \
2242 || (MODE != DFmode \
2243 && MODE != DImode))) \
2244 || RTX_OK_FOR_OFFSET_P (op1)) \
2247 else if (RTX_OK_FOR_BASE_P (op1)) \
2249 if ((RTX_OK_FOR_INDEX_P (op0) \
2250 /* See the previous comment. */ \
2251 && (MODE != TFmode \
2252 || (TARGET_FPU && TARGET_ARCH64 \
2254 && TARGET_HARD_QUAD)) \
2255 && (TARGET_ARCH64 || optimize \
2256 || (MODE != DFmode \
2257 && MODE != DImode))) \
2258 || RTX_OK_FOR_OFFSET_P (op0)) \
2261 else if (USE_AS_OFFSETABLE_LO10 \
2262 && GET_CODE (op0) == LO_SUM \
2264 && ! TARGET_CM_MEDMID \
2265 && RTX_OK_FOR_OLO10_P (op1)) \
2267 register rtx op00 = XEXP (op0, 0); \
2268 register rtx op01 = XEXP (op0, 1); \
2269 if (RTX_OK_FOR_BASE_P (op00) \
2270 && CONSTANT_P (op01)) \
2273 else if (USE_AS_OFFSETABLE_LO10 \
2274 && GET_CODE (op1) == LO_SUM \
2276 && ! TARGET_CM_MEDMID \
2277 && RTX_OK_FOR_OLO10_P (op0)) \
2279 register rtx op10 = XEXP (op1, 0); \
2280 register rtx op11 = XEXP (op1, 1); \
2281 if (RTX_OK_FOR_BASE_P (op10) \
2282 && CONSTANT_P (op11)) \
2286 else if (GET_CODE (X) == LO_SUM) \
2288 register rtx op0 = XEXP (X, 0); \
2289 register rtx op1 = XEXP (X, 1); \
2290 if (RTX_OK_FOR_BASE_P (op0) \
2291 && CONSTANT_P (op1) \
2292 /* We can't allow TFmode, because an offset \
2293 greater than or equal to the alignment (8) \
2294 may cause the LO_SUM to overflow if !v9. */\
2295 && (MODE != TFmode || TARGET_V9)) \
2298 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2302 /* Try machine-dependent ways of modifying an illegitimate address
2303 to be legitimate. If we find one, return the new, valid address.
2304 This macro is used in only one place: `memory_address' in explow.c.
2306 OLDX is the address as it was before break_out_memory_refs was called.
2307 In some cases it is useful to look at this to decide what needs to be done.
2309 MODE and WIN are passed so that this macro can use
2310 GO_IF_LEGITIMATE_ADDRESS.
2312 It is always safe for this macro to do nothing. It exists to recognize
2313 opportunities to optimize the output. */
2315 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2316 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2317 { rtx sparc_x = (X); \
2318 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2319 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2320 force_operand (XEXP (X, 0), NULL_RTX)); \
2321 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2322 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2323 force_operand (XEXP (X, 1), NULL_RTX)); \
2324 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2325 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2327 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2328 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2329 force_operand (XEXP (X, 1), NULL_RTX)); \
2330 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2332 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2333 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2334 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2335 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2336 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2337 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2338 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2339 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2340 || GET_CODE (X) == LABEL_REF) \
2341 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2342 if (memory_address_p (MODE, X)) \
2345 /* Try a machine-dependent way of reloading an illegitimate address
2346 operand. If we find one, push the reload and jump to WIN. This
2347 macro is used in only one place: `find_reloads_address' in reload.c.
2349 For Sparc 32, we wish to handle addresses by splitting them into
2350 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2351 This cuts the number of extra insns by one.
2353 Do nothing when generating PIC code and the address is a
2354 symbolic operand or requires a scratch register. */
2356 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2358 /* Decompose SImode constants into hi+lo_sum. We do have to \
2359 rerecognize what we produce, so be careful. */ \
2360 if (CONSTANT_P (X) \
2361 && (MODE != TFmode || TARGET_V9) \
2362 && GET_MODE (X) == SImode \
2363 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2365 && (symbolic_operand (X, Pmode) \
2366 || pic_address_needs_scratch (X)))) \
2368 X = gen_rtx_LO_SUM (GET_MODE (X), \
2369 gen_rtx_HIGH (GET_MODE (X), X), X); \
2370 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2371 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2375 /* ??? 64-bit reloads. */ \
2378 /* Go to LABEL if ADDR (a legitimate address expression)
2379 has an effect that depends on the machine mode it is used for.
2380 On the SPARC this is never true. */
2382 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2384 /* If we are referencing a function make the SYMBOL_REF special.
2385 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2386 so we must not add it to function addresses. */
2388 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2390 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2391 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2394 /* Specify the machine mode that this machine uses
2395 for the index in the tablejump instruction. */
2396 /* If we ever implement any of the full models (such as CM_FULLANY),
2397 this has to be DImode in that case */
2398 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2399 #define CASE_VECTOR_MODE \
2400 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2402 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2403 we have to sign extend which slows things down. */
2404 #define CASE_VECTOR_MODE \
2405 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2408 /* Define as C expression which evaluates to nonzero if the tablejump
2409 instruction expects the table to contain offsets from the address of the
2411 Do not define this if the table should contain absolute addresses. */
2412 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2414 /* Define this as 1 if `char' should by default be signed; else as 0. */
2415 #define DEFAULT_SIGNED_CHAR 1
2417 /* Max number of bytes we can move from memory to memory
2418 in one reasonably fast instruction. */
2421 #if 0 /* Sun 4 has matherr, so this is no good. */
2422 /* This is the value of the error code EDOM for this machine,
2423 used by the sqrt instruction. */
2424 #define TARGET_EDOM 33
2426 /* This is how to refer to the variable errno. */
2427 #define GEN_ERRNO_RTX \
2428 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2431 /* Define if operations between registers always perform the operation
2432 on the full register even if a narrower mode is specified. */
2433 #define WORD_REGISTER_OPERATIONS
2435 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2436 will either zero-extend or sign-extend. The value of this macro should
2437 be the code that says which one of the two operations is implicitly
2438 done, NIL if none. */
2439 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2441 /* Nonzero if access to memory by bytes is slow and undesirable.
2442 For RISC chips, it means that access to memory by bytes is no
2443 better than access by words when possible, so grab a whole word
2444 and maybe make use of that. */
2445 #define SLOW_BYTE_ACCESS 1
2447 /* We assume that the store-condition-codes instructions store 0 for false
2448 and some other value for true. This is the value stored for true. */
2450 #define STORE_FLAG_VALUE 1
2452 /* When a prototype says `char' or `short', really pass an `int'. */
2453 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2455 /* Define this to be nonzero if shift instructions ignore all but the low-order
2457 #define SHIFT_COUNT_TRUNCATED 1
2459 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2460 is done just by pretending it is already truncated. */
2461 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2463 /* Specify the machine mode that pointers have.
2464 After generation of rtl, the compiler makes no further distinction
2465 between pointers and any other objects of this machine mode. */
2466 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2468 /* Generate calls to memcpy, memcmp and memset. */
2469 #define TARGET_MEM_FUNCTIONS
2471 /* Add any extra modes needed to represent the condition code.
2473 On the Sparc, we have a "no-overflow" mode which is used when an add or
2474 subtract insn is used to set the condition code. Different branches are
2475 used in this case for some operations.
2477 We also have two modes to indicate that the relevant condition code is
2478 in the floating-point condition code register. One for comparisons which
2479 will generate an exception if the result is unordered (CCFPEmode) and
2480 one for comparisons which will never trap (CCFPmode).
2482 CCXmode and CCX_NOOVmode are only used by v9. */
2484 #define EXTRA_CC_MODES \
2485 CC(CCXmode, "CCX") \
2486 CC(CC_NOOVmode, "CC_NOOV") \
2487 CC(CCX_NOOVmode, "CCX_NOOV") \
2488 CC(CCFPmode, "CCFP") \
2489 CC(CCFPEmode, "CCFPE")
2491 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2492 return the mode to be used for the comparison. For floating-point,
2493 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2494 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2495 processing is needed. */
2496 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2498 /* Return non-zero if MODE implies a floating point inequality can be
2499 reversed. For Sparc this is always true because we have a full
2500 compliment of ordered and unordered comparisons, but until generic
2501 code knows how to reverse it correctly we keep the old definition. */
2502 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2504 /* A function address in a call instruction for indexing purposes. */
2505 #define FUNCTION_MODE Pmode
2507 /* Define this if addresses of constant functions
2508 shouldn't be put through pseudo regs where they can be cse'd.
2509 Desirable on machines where ordinary constants are expensive
2510 but a CALL with constant address is cheap. */
2511 #define NO_FUNCTION_CSE
2513 /* alloca should avoid clobbering the old register save area. */
2514 #define SETJMP_VIA_SAVE_AREA
2516 /* Define subroutines to call to handle multiply and divide.
2517 Use the subroutines that Sun's library provides.
2518 The `*' prevents an underscore from being prepended by the compiler. */
2520 #define DIVSI3_LIBCALL "*.div"
2521 #define UDIVSI3_LIBCALL "*.udiv"
2522 #define MODSI3_LIBCALL "*.rem"
2523 #define UMODSI3_LIBCALL "*.urem"
2524 /* .umul is a little faster than .mul. */
2525 #define MULSI3_LIBCALL "*.umul"
2527 /* Define library calls for quad FP operations. These are all part of the
2529 #define ADDTF3_LIBCALL "_Q_add"
2530 #define SUBTF3_LIBCALL "_Q_sub"
2531 #define NEGTF2_LIBCALL "_Q_neg"
2532 #define MULTF3_LIBCALL "_Q_mul"
2533 #define DIVTF3_LIBCALL "_Q_div"
2534 #define FLOATSITF2_LIBCALL "_Q_itoq"
2535 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2536 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2537 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2538 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2539 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2540 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2541 #define EQTF2_LIBCALL "_Q_feq"
2542 #define NETF2_LIBCALL "_Q_fne"
2543 #define GTTF2_LIBCALL "_Q_fgt"
2544 #define GETF2_LIBCALL "_Q_fge"
2545 #define LTTF2_LIBCALL "_Q_flt"
2546 #define LETF2_LIBCALL "_Q_fle"
2548 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2549 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2550 and the compiler will notice and try to use the TFmode sqrt instruction
2551 for calls to the builtin function sqrt, but this fails. */
2552 #define INIT_TARGET_OPTABS \
2554 if (TARGET_ARCH32) \
2556 add_optab->handlers[(int) TFmode].libfunc \
2557 = init_one_libfunc (ADDTF3_LIBCALL); \
2558 sub_optab->handlers[(int) TFmode].libfunc \
2559 = init_one_libfunc (SUBTF3_LIBCALL); \
2560 neg_optab->handlers[(int) TFmode].libfunc \
2561 = init_one_libfunc (NEGTF2_LIBCALL); \
2562 smul_optab->handlers[(int) TFmode].libfunc \
2563 = init_one_libfunc (MULTF3_LIBCALL); \
2564 sdiv_optab->handlers[(int) TFmode].libfunc \
2565 = init_one_libfunc (DIVTF3_LIBCALL); \
2566 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2567 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2568 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2569 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2570 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2571 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2572 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2573 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2574 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2575 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2576 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2577 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2578 fixunstfsi_libfunc \
2579 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2581 sqrt_optab->handlers[(int) TFmode].libfunc \
2582 = init_one_libfunc ("_Q_sqrt"); \
2584 INIT_SUBTARGET_OPTABS; \
2587 /* This is meant to be redefined in the host dependent files */
2588 #define INIT_SUBTARGET_OPTABS
2590 /* Nonzero if a floating point comparison library call for
2591 mode MODE that will return a boolean value. Zero if one
2592 of the libgcc2 functions is used. */
2593 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2595 /* Compute the cost of computing a constant rtl expression RTX
2596 whose rtx-code is CODE. The body of this macro is a portion
2597 of a switch statement. If the code is computed here,
2598 return it with a return statement. Otherwise, break from the switch. */
2600 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2602 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2610 case CONST_DOUBLE: \
2611 if (GET_MODE (RTX) == DImode) \
2612 if ((XINT (RTX, 3) == 0 \
2613 && (unsigned) XINT (RTX, 2) < 0x1000) \
2614 || (XINT (RTX, 3) == -1 \
2615 && XINT (RTX, 2) < 0 \
2616 && XINT (RTX, 2) >= -0x1000)) \
2620 #define ADDRESS_COST(RTX) 1
2622 /* Compute extra cost of moving data between one register class
2624 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2625 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2626 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2627 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2628 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2629 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2631 /* Provide the costs of a rtl expression. This is in the body of a
2632 switch on CODE. The purpose for the cost of MULT is to encourage
2633 `synth_mult' to find a synthetic multiply when reasonable.
2635 If we need more than 12 insns to do a multiply, then go out-of-line,
2636 since the call overhead will be < 10% of the cost of the multiply. */
2638 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2640 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2641 return (GET_MODE (X) == DImode ? \
2642 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2643 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2648 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2649 return (GET_MODE (X) == DImode ? \
2650 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2651 return COSTS_N_INSNS (25); \
2652 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2653 so that cse will favor the latter. */ \
2658 /* Control the assembler format that we output. */
2660 /* Output at beginning of assembler file. */
2662 #define ASM_FILE_START(file)
2664 /* A C string constant describing how to begin a comment in the target
2665 assembler language. The compiler assumes that the comment will end at
2666 the end of the line. */
2668 #define ASM_COMMENT_START "!"
2670 /* Output to assembler file text saying following lines
2671 may contain character constants, extra white space, comments, etc. */
2673 #define ASM_APP_ON ""
2675 /* Output to assembler file text saying following lines
2676 no longer contain unusual constructs. */
2678 #define ASM_APP_OFF ""
2680 /* ??? Try to make the style consistent here (_OP?). */
2682 #define ASM_FLOAT ".single"
2683 #define ASM_DOUBLE ".double"
2684 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2686 /* How to refer to registers in assembler output.
2687 This sequence is indexed by compiler's hard-register-number (see above). */
2689 #define REGISTER_NAMES \
2690 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2691 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2692 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2693 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2694 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2695 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2696 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2697 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2698 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2699 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2700 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2701 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2702 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2704 /* Define additional names for use in asm clobbers and asm declarations. */
2706 #define ADDITIONAL_REGISTER_NAMES \
2707 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2709 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2710 can run past this up to a continuation point. Once we used 1500, but
2711 a single entry in C++ can run more than 500 bytes, due to the length of
2712 mangled symbol names. dbxout.c should really be fixed to do
2713 continuations when they are actually needed instead of trying to
2715 #define DBX_CONTIN_LENGTH 1000
2717 /* This is how to output the definition of a user-level label named NAME,
2718 such as the label on a static function or variable NAME. */
2720 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2721 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2723 /* This is how to output a command to make the user-level label named NAME
2724 defined for reference from other files. */
2726 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2727 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2729 /* The prefix to add to user-visible assembler symbols. */
2731 #define USER_LABEL_PREFIX "_"
2733 /* This is how to output a definition of an internal numbered label where
2734 PREFIX is the class of label and NUM is the number within the class. */
2736 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2737 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2739 /* This is how to store into the string LABEL
2740 the symbol_ref name of an internal numbered label where
2741 PREFIX is the class of label and NUM is the number within the class.
2742 This is suitable for output with `assemble_name'. */
2744 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2745 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2747 /* This is how we hook in and defer the case-vector until the end of
2749 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2750 sparc_defer_case_vector ((LAB),(VEC), 0)
2752 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2753 sparc_defer_case_vector ((LAB),(VEC), 1)
2755 /* This is how to output an element of a case-vector that is absolute. */
2757 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2760 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2761 if (CASE_VECTOR_MODE == SImode) \
2762 fprintf (FILE, "\t.word\t"); \
2764 fprintf (FILE, "\t.xword\t"); \
2765 assemble_name (FILE, label); \
2766 fputc ('\n', FILE); \
2769 /* This is how to output an element of a case-vector that is relative.
2770 (SPARC uses such vectors only when generating PIC.) */
2772 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2775 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2776 if (CASE_VECTOR_MODE == SImode) \
2777 fprintf (FILE, "\t.word\t"); \
2779 fprintf (FILE, "\t.xword\t"); \
2780 assemble_name (FILE, label); \
2781 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2782 fputc ('-', FILE); \
2783 assemble_name (FILE, label); \
2784 fputc ('\n', FILE); \
2787 /* This is what to output before and after case-vector (both
2788 relative and absolute). If .subsection -1 works, we put case-vectors
2789 at the beginning of the current section. */
2791 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2793 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2794 fprintf(FILE, "\t.subsection\t-1\n")
2796 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2797 fprintf(FILE, "\t.previous\n")
2801 /* This is how to output an assembler line
2802 that says to advance the location counter
2803 to a multiple of 2**LOG bytes. */
2805 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2807 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2809 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2810 fprintf (FILE, "\t.skip %u\n", (SIZE))
2812 /* This says how to output an assembler line
2813 to define a global common symbol. */
2815 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2816 ( fputs ("\t.common ", (FILE)), \
2817 assemble_name ((FILE), (NAME)), \
2818 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2820 /* This says how to output an assembler line to define a local common
2823 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2824 ( fputs ("\t.reserve ", (FILE)), \
2825 assemble_name ((FILE), (NAME)), \
2826 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2827 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2829 /* A C statement (sans semicolon) to output to the stdio stream
2830 FILE the assembler definition of uninitialized global DECL named
2831 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2832 Try to use asm_output_aligned_bss to implement this macro. */
2834 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2836 fputs (".globl ", (FILE)); \
2837 assemble_name ((FILE), (NAME)); \
2838 fputs ("\n", (FILE)); \
2839 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2842 /* Store in OUTPUT a string (made with alloca) containing
2843 an assembler-name for a local static variable named NAME.
2844 LABELNO is an integer which is different for each call. */
2846 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2847 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2848 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2850 #define IDENT_ASM_OP "\t.ident\t"
2852 /* Output #ident as a .ident. */
2854 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2855 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2857 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2858 Used for C++ multiple inheritance. */
2859 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2864 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
2866 if ((DELTA) >= 4096 || (DELTA) < -4096) \
2867 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
2868 (int)(DELTA), reg, reg); \
2870 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
2871 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
2872 fprintf (FILE, "\tcall\t"); \
2873 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2874 fprintf (FILE, ", 0\n"); \
2875 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
2878 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2879 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2881 /* Print operand X (an rtx) in assembler syntax to file FILE.
2882 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2883 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2885 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2887 /* Print a memory address as an operand to reference that memory location. */
2889 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2890 { register rtx base, index = 0; \
2892 register rtx addr = ADDR; \
2893 if (GET_CODE (addr) == REG) \
2894 fputs (reg_names[REGNO (addr)], FILE); \
2895 else if (GET_CODE (addr) == PLUS) \
2897 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2898 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2899 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2900 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2902 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2903 if (GET_CODE (base) == LO_SUM) \
2905 if (! USE_AS_OFFSETABLE_LO10 \
2907 || TARGET_CM_MEDMID) \
2909 output_operand (XEXP (base, 0), 0); \
2910 fputs ("+%lo(", FILE); \
2911 output_address (XEXP (base, 1)); \
2912 fprintf (FILE, ")+%d", offset); \
2916 fputs (reg_names[REGNO (base)], FILE); \
2918 fprintf (FILE, "%+d", offset); \
2919 else if (GET_CODE (index) == REG) \
2920 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2921 else if (GET_CODE (index) == SYMBOL_REF \
2922 || GET_CODE (index) == CONST) \
2923 fputc ('+', FILE), output_addr_const (FILE, index); \
2927 else if (GET_CODE (addr) == MINUS \
2928 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2930 output_addr_const (FILE, XEXP (addr, 0)); \
2931 fputs ("-(", FILE); \
2932 output_addr_const (FILE, XEXP (addr, 1)); \
2933 fputs ("-.)", FILE); \
2935 else if (GET_CODE (addr) == LO_SUM) \
2937 output_operand (XEXP (addr, 0), 0); \
2938 if (TARGET_CM_MEDMID) \
2939 fputs ("+%l44(", FILE); \
2941 fputs ("+%lo(", FILE); \
2942 output_address (XEXP (addr, 1)); \
2943 fputc (')', FILE); \
2945 else if (flag_pic && GET_CODE (addr) == CONST \
2946 && GET_CODE (XEXP (addr, 0)) == MINUS \
2947 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2948 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2949 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2951 addr = XEXP (addr, 0); \
2952 output_addr_const (FILE, XEXP (addr, 0)); \
2953 /* Group the args of the second CONST in parenthesis. */ \
2954 fputs ("-(", FILE); \
2955 /* Skip past the second CONST--it does nothing for us. */\
2956 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2957 /* Close the parenthesis. */ \
2958 fputc (')', FILE); \
2962 output_addr_const (FILE, addr); \
2966 /* Define the codes that are matched by predicates in sparc.c. */
2968 #define PREDICATE_CODES \
2969 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2970 {"fp_zero_operand", {CONST_DOUBLE}}, \
2971 {"intreg_operand", {SUBREG, REG}}, \
2972 {"fcc_reg_operand", {REG}}, \
2973 {"fcc0_reg_operand", {REG}}, \
2974 {"icc_or_fcc_reg_operand", {REG}}, \
2975 {"restore_operand", {REG}}, \
2976 {"call_operand", {MEM}}, \
2977 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2978 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2979 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2980 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2981 {"label_ref_operand", {LABEL_REF}}, \
2982 {"sp64_medium_pic_operand", {CONST}}, \
2983 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2984 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2985 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2986 {"splittable_symbolic_memory_operand", {MEM}}, \
2987 {"splittable_immediate_memory_operand", {MEM}}, \
2988 {"eq_or_neq", {EQ, NE}}, \
2989 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2990 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2991 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2992 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2993 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2994 {"cc_arithop", {AND, IOR, XOR}}, \
2995 {"cc_arithopn", {AND, IOR}}, \
2996 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2997 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2998 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2999 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3000 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3001 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3002 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3003 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3004 {"small_int", {CONST_INT}}, \
3005 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3006 {"uns_small_int", {CONST_INT}}, \
3007 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3008 {"clobbered_register", {REG}}, \
3009 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3010 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3011 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3013 /* The number of Pmode words for the setjmp buffer. */
3014 #define JMP_BUF_SIZE 12
3016 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)