1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 94, 95, 1996 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Sparc64 support has been added by trying to allow for a day when one
28 compiler can handle both v8 and v9. There are a few cases where this
29 isn't doable, but keep them to a minimum!
31 TARGET_V9 is used to select at runtime the sparc64 chip.
32 TARGET_ARCH64 is used to select at runtime a 64 bit environment.
33 SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside
34 #define's), and says whether the cpu is a sparc64 chip (which may be
35 running in a 32 or 64 bit environment).
36 SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit
39 In places where it is possible to choose at runtime, use TARGET_V9 and
40 TARGET_ARCH64. In places where it is currently not possible to select
41 between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of
42 SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8
43 and v9 in the v9 compiler.
45 ??? All uses of SPARC_V9 have been removed. Try not to add new ones.
52 #define SPARC_ARCH64 0
55 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */
56 #define TARGET_CPU_sparc 0
57 #define TARGET_CPU_sparclet 1
58 #define TARGET_CPU_sparclite 2
59 #define TARGET_CPU_sparc64 3
61 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc
62 #define CPP_DEFAULT_SPEC ""
63 #define ASM_DEFAULT_SPEC ""
65 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
66 #define CPP_DEFAULT_SPEC "-D__sparclet__"
67 #define ASM_DEFAULT_SPEC "-Asparclet"
69 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
70 #define CPP_DEFAULT_SPEC "-D__sparclite__"
71 #define ASM_DEFAULT_SPEC "-Asparclite"
73 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
74 /* ??? What does Sun's CC pass? */
75 #define CPP_DEFAULT_SPEC "-D__sparc_v9__"
76 /* ??? It's not clear how other assemblers will handle this, so by default
77 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
78 is handled in sol2.h. */
79 #define ASM_DEFAULT_SPEC "-Av9"
81 Unrecognized value in TARGET_CPU_DEFAULT.
87 /* Names to predefine in the preprocessor for this target machine. */
89 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
90 the right varags.h file when bootstrapping. */
91 /* ??? It's not clear what value we want to use for -Acpu/machine for
92 sparc64 in 32 bit environments, so for now we only use `sparc64' in
93 64 bit environments. */
94 /* ??? __arch64__ is subject to change. */
97 #define CPP_PREDEFINES \
98 "-Dsparc -Dsun -Dunix -D__arch64__ \
99 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
101 #define CPP_PREDEFINES \
102 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
103 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
106 /* Define macros to distinguish architectures. */
110 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
111 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
114 #define CPP_SPEC "%(cpp_cpu)"
117 /* Common CPP definitions used by CPP_SPEC amongst the various targets
118 for handling -mcpu=xxx switches. */
119 #define CPP_CPU_SPEC "\
121 %{msparclite:-D__sparclite__} \
122 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
123 %{mv8:-D__sparc_v8__} \
124 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
125 %{mcpu=sparclite:-D__sparclite__} \
126 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
127 %{mcpu=v8:-D__sparc_v8__} \
128 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
129 %{mcpu=v9:-D__sparc_v9__} \
130 %{mcpu=ultrasparc:-D__sparc_v9__} \
131 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \
134 /* Prevent error on `-sun4' and `-target sun4' options. */
135 /* This used to translate -dalign to -malign, but that is no good
136 because it can't turn off the usual meaning of making debugging dumps. */
137 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
138 At some point support for -m<cpu> will be deleted. */
141 %{sun4:} %{target:} \
142 %{mcypress:-mcpu=cypress} \
143 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
144 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
147 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
149 /* Provide required defaults for linker -e and -d switches. */
152 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
153 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
155 /* Special flags to the Sun-4 assembler when using pipe for input. */
158 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
162 /* Override in target specific files. */
163 #define ASM_CPU_SPEC "\
164 %{msparclite:-Asparclite} \
165 %{mf930:-Asparclite} %{mf934:-Asparclite} \
166 %{mcpu=sparclite:-Asparclite} \
167 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
169 %{mcpu=ultrasparc:-Av9} \
170 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \
173 /* This macro defines names of additional specifications to put in the specs
174 that can be used in various specifications like CC1_SPEC. Its definition
175 is an initializer with a subgrouping for each command option.
177 Each subgrouping contains a string constant, that defines the
178 specification name, and a string constant that used by the GNU CC driver
181 Do not define this macro if it does not need to do anything. */
183 #define EXTRA_SPECS \
184 { "cpp_cpu", CPP_CPU_SPEC }, \
185 { "cpp_default", CPP_DEFAULT_SPEC }, \
186 { "asm_cpu", ASM_CPU_SPEC }, \
187 { "asm_default", ASM_DEFAULT_SPEC }, \
188 SUBTARGET_EXTRA_SPECS
190 #define SUBTARGET_EXTRA_SPECS
193 #define PTRDIFF_TYPE "long long int"
194 #define SIZE_TYPE "long long unsigned int"
196 #define PTRDIFF_TYPE "int"
197 /* The default value for SIZE_TYPE is "unsigned int" which is what we want. */
200 /* ??? This should be 32 bits for v9 but what can we do? */
201 #define WCHAR_TYPE "short unsigned int"
202 #define WCHAR_TYPE_SIZE 16
203 #define MAX_WCHAR_TYPE_SIZE 16
205 /* Show we can debug even without a frame pointer. */
206 #define CAN_DEBUG_WITHOUT_FP
208 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
209 code into the rtl. Also, if we are profiling, we cannot eliminate
210 the frame pointer (because the return address will get smashed). */
212 void sparc_override_options ();
214 #define OVERRIDE_OPTIONS \
216 if (profile_flag || profile_block_flag) \
220 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
221 warning ("%s and profiling conflict: disabling %s", \
222 pic_string, pic_string); \
225 flag_omit_frame_pointer = 0; \
227 sparc_override_options (); \
228 SUBTARGET_OVERRIDE_OPTIONS; \
231 /* This is meant to be redefined in the host dependent files. */
232 #define SUBTARGET_OVERRIDE_OPTIONS
234 /* These compiler options take an argument. We ignore -target for now. */
236 #define WORD_SWITCH_TAKES_ARG(STR) \
237 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
238 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
240 /* Print subsidiary information on the compiler version in use. */
242 #define TARGET_VERSION fprintf (stderr, " (sparc)");
244 /* Generate DBX debugging information. */
246 #define DBX_DEBUGGING_INFO
248 /* Run-time compilation parameters selecting different hardware subsets. */
250 extern int target_flags;
252 /* Nonzero if we should generate code to use the fpu. */
254 #define TARGET_FPU (target_flags & MASK_FPU)
256 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
257 use fast return insns, but lose some generality. */
258 #define MASK_EPILOGUE 2
259 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
261 /* Nonzero if we should assume that double pointers might be unaligned.
262 This can happen when linking gcc compiled code with other compilers,
263 because the ABI only guarantees 4 byte alignment. */
264 #define MASK_UNALIGNED_DOUBLES 4
265 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
267 /* Nonzero means that we should generate code for a v8 sparc. */
269 #define TARGET_V8 (target_flags & MASK_V8)
271 /* Nonzero means that we should generate code for a sparclite.
272 This enables the sparclite specific instructions, but does not affect
273 whether FPU instructions are emitted. */
274 #define MASK_SPARCLITE 0x10
275 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
277 /* Nonzero if we're compiling for the sparclet. */
278 #define MASK_SPARCLET 0x20
279 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
281 /* Nonzero if we're compiling for v9 sparc.
282 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
283 the word size is 64. */
285 #define TARGET_V9 (target_flags & MASK_V9)
287 /* Non-zero to generate code that uses the instructions deprecated in
288 the v9 architecture. This option only applies to v9 systems. */
289 /* ??? This isn't user selectable yet. It's used to enable such insns
290 on 32 bit v9 systems and for the moment they're permanently disabled
291 on 64 bit v9 systems. */
292 #define MASK_DEPRECATED_V8_INSNS 0x80
293 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
295 /* Mask of all CPU selection flags. */
297 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
299 /* Non-zero means don't pass `-assert pure-text' to the linker. */
300 #define MASK_IMPURE_TEXT 0x100
301 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
303 /* Nonzero means that we should generate code using a flat register window
304 model, i.e. no save/restore instructions are generated, which is
305 compatible with normal sparc code.
306 The frame pointer is %i7 instead of %fp. */
307 #define MASK_FLAT 0x200
308 #define TARGET_FLAT (target_flags & MASK_FLAT)
310 /* Nonzero means use the registers that the Sparc ABI reserves for
311 application software. This must be the default to coincide with the
312 setting in FIXED_REGISTERS. */
313 #define MASK_APP_REGS 0x400
314 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
316 /* Option to select how quad word floating point is implemented.
317 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
318 Otherwise, we use the SPARC ABI quad library functions. */
319 #define MASK_HARD_QUAD 0x800
320 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
322 /* Bit 0x1000 currently unused. */
324 /* Nonzero if ints are 64 bits.
325 This automatically implies longs are 64 bits too.
326 This option is for v9 only. */
327 #define MASK_INT64 0x2000
328 #define TARGET_INT64 (target_flags & MASK_INT64)
330 /* Nonzero if longs are 64 bits.
331 This option is for v9 only. */
332 #define MASK_LONG64 0x4000
333 #define TARGET_LONG64 (target_flags & MASK_LONG64)
335 /* Nonzero if pointers are 64 bits.
336 This is not a user selectable option, though it may be one day -
337 so it is used to determine pointer size instead of an architecture flag. */
338 #define MASK_PTR64 0x8000
339 #define TARGET_PTR64 (target_flags & MASK_PTR64)
341 /* Nonzero if generating code to run in a 64 bit environment. */
342 #define MASK_ARCH64 0x10000
343 #define TARGET_ARCH64 (target_flags & MASK_ARCH64)
344 #define TARGET_ARCH32 (! TARGET_ARCH64)
346 /* SPARC64 memory models.
347 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0,
348 avoid generating %uhi and %ulo terms.
349 (pointers can be 32 or 64 bits)
350 TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but
351 can be loaded anywhere (use %g4 as offset).
352 TARGET_FULLANY: 64 bit address space, no restrictions.
353 This option is not fully supported yet.
354 These options are for v9 only. All mask values are nonzero so the v8
355 compiler can assume this stuff won't interfere. */
356 #define MASK_MEDLOW 0x20000
357 #define MASK_MEDANY 0x40000
358 #define MASK_FULLANY 0x60000
359 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
360 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
361 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
362 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
364 /* ??? There are hardcoded references to this reg in the .md file. */
365 #define MEDANY_BASE_REG "%g4"
367 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
368 adding 2047 to %sp. This option is for v9 only and is the default. */
369 #define MASK_STACK_BIAS 0x80000
370 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
372 /* Non-zero means %g0 is a normal register.
373 We still clobber it as necessary, but we can't rely on it always having
375 We don't bother to support this in true 64 bit mode. */
376 #define MASK_LIVE_G0 0x100000
377 #define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
379 /* Macro to define tables used to set the flags.
380 This is a list in braces of pairs in braces,
381 each pair being { "NAME", VALUE }
382 where VALUE is the bits to set or minus the bits to clear.
383 An empty string NAME is used to identify the default VALUE. */
385 #define TARGET_SWITCHES \
386 { {"fpu", MASK_FPU}, \
387 {"no-fpu", -MASK_FPU}, \
388 {"hard-float", MASK_FPU}, \
389 {"soft-float", -MASK_FPU}, \
390 {"epilogue", MASK_EPILOGUE}, \
391 {"no-epilogue", -MASK_EPILOGUE}, \
392 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
393 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
394 {"impure-text", MASK_IMPURE_TEXT}, \
395 {"no-impure-text", -MASK_IMPURE_TEXT}, \
396 {"flat", MASK_FLAT}, \
397 {"no-flat", -MASK_FLAT}, \
398 {"app-regs", MASK_APP_REGS}, \
399 {"no-app-regs", -MASK_APP_REGS}, \
400 {"hard-quad-float", MASK_HARD_QUAD}, \
401 {"soft-quad-float", -MASK_HARD_QUAD}, \
402 /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \
411 { "", TARGET_DEFAULT}}
413 /* MASK_APP_REGS must always be the default because that's what
414 FIXED_REGISTERS is set to and -ffixed- is processed before
415 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
416 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
418 /* This is meant to be redefined in target specific files. */
419 #define SUBTARGET_SWITCHES
421 /* ??? Until we support a combination 32/64 bit compiler, these options
422 are only defined for the v9 compiler in a true 64 bit environment. */
424 #define ARCH64_SWITCHES \
425 /* {"arch32", -MASK_ARCH64}, */ \
426 /* {"arch64", MASK_ARCH64}, */ \
427 {"int64", MASK_INT64+MASK_LONG64}, \
428 {"int32", -MASK_INT64}, \
429 {"int32", MASK_LONG64}, \
430 {"long64", -MASK_INT64}, \
431 {"long64", MASK_LONG64}, \
432 {"long32", -(MASK_INT64+MASK_LONG64)}, \
433 /* {"ptr64", MASK_PTR64}, */ \
434 /* {"ptr32", -MASK_PTR64}, */ \
435 {"stack-bias", MASK_STACK_BIAS}, \
436 {"no-stack-bias", -MASK_STACK_BIAS}, \
437 {"medlow", -MASK_CODE_MODEL}, \
438 {"medlow", MASK_MEDLOW}, \
439 {"medany", -MASK_CODE_MODEL}, \
440 {"medany", MASK_MEDANY}, \
441 {"fullany", -MASK_CODE_MODEL}, \
442 {"fullany", MASK_FULLANY},
444 #define ARCH64_SWITCHES
448 These must match the values for the cpu attribute in sparc.md. */
449 enum processor_type {
453 PROCESSOR_SUPERSPARC,
464 /* This is set from -m{cpu,tune}=xxx. */
465 extern enum processor_type sparc_cpu;
467 /* Recast the cpu class to be the cpu attribute.
468 Every file includes us, but not every file includes insn-attr.h. */
469 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
471 /* This macro is similar to `TARGET_SWITCHES' but defines names of
472 command options that have values. Its definition is an
473 initializer with a subgrouping for each command option.
475 Each subgrouping contains a string constant, that defines the
476 fixed part of the option name, and the address of a variable.
477 The variable, type `char *', is set to the variable part of the
478 given option if the fixed part matches. The actual option name
479 is made by appending `-m' to the specified name.
481 Here is an example which defines `-mshort-data-NUMBER'. If the
482 given option is `-mshort-data-512', the variable `m88k_short_data'
483 will be set to the string `"512"'.
485 extern char *m88k_short_data;
486 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
488 #define TARGET_OPTIONS \
490 {"cpu=", &sparc_select[1].string}, \
491 {"tune=", &sparc_select[2].string}, \
495 /* This is meant to be redefined in target specific files. */
496 #define SUBTARGET_OPTIONS
498 /* sparc_select[0] is reserved for the default cpu. */
499 struct sparc_cpu_select
507 extern struct sparc_cpu_select sparc_select[];
509 /* target machine storage layout */
511 /* Define for cross-compilation to a sparc target with no TFmode from a host
512 with a different float format (e.g. VAX). */
513 #define REAL_ARITHMETIC
515 /* Define this if most significant bit is lowest numbered
516 in instructions that operate on numbered bit-fields. */
517 #define BITS_BIG_ENDIAN 1
519 /* Define this if most significant byte of a word is the lowest numbered. */
520 /* This is true on the SPARC. */
521 #define BYTES_BIG_ENDIAN 1
523 /* Define this if most significant word of a multiword number is the lowest
525 /* Doubles are stored in memory with the high order word first. This
526 matters when cross-compiling. */
527 #define WORDS_BIG_ENDIAN 1
529 /* number of bits in an addressable storage unit */
530 #define BITS_PER_UNIT 8
532 /* Width in bits of a "word", which is the contents of a machine register.
533 Note that this is not necessarily the width of data type `int';
534 if using 16-bit ints on a 68000, this would still be 32.
535 But on a machine with 16-bit registers, this would be 16. */
536 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
537 #define MAX_BITS_PER_WORD 64
539 /* Width of a word, in units (bytes). */
540 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
541 #define MIN_UNITS_PER_WORD 4
543 /* Now define the sizes of the C data types. */
545 #define SHORT_TYPE_SIZE 16
546 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
547 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
548 #define LONG_LONG_TYPE_SIZE 64
549 #define FLOAT_TYPE_SIZE 32
550 #define DOUBLE_TYPE_SIZE 64
552 #define MAX_INT_TYPE_SIZE 64
553 #define MAX_LONG_TYPE_SIZE 64
556 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
557 Instead, it is enabled in sol2.h, because it does work under Solaris. */
558 /* Define for support of TFmode long double and REAL_ARITHMETIC.
559 Sparc ABI says that long double is 4 words. */
560 #define LONG_DOUBLE_TYPE_SIZE 128
563 /* Width in bits of a pointer.
564 See also the macro `Pmode' defined below. */
565 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
567 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
568 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
570 /* Boundary (in *bits*) on which stack pointer should be aligned. */
571 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
573 /* ALIGN FRAMES on double word boundaries */
575 #define SPARC_STACK_ALIGN(LOC) \
576 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
578 /* Allocation boundary (in *bits*) for the code of a function. */
579 #define FUNCTION_BOUNDARY 32
581 /* Alignment of field after `int : 0' in a structure. */
582 /* ??? Should this be based on TARGET_INT64? */
583 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
585 /* Every structure's size must be a multiple of this. */
586 #define STRUCTURE_SIZE_BOUNDARY 8
588 /* A bitfield declared as `int' forces `int' alignment for the struct. */
589 #define PCC_BITFIELD_TYPE_MATTERS 1
591 /* No data type wants to be aligned rounder than this. */
592 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
594 /* The best alignment to use in cases where we have a choice. */
595 #define FASTEST_ALIGNMENT 64
597 /* Make strings word-aligned so strcpy from constants will be faster. */
598 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
599 ((TREE_CODE (EXP) == STRING_CST \
600 && (ALIGN) < FASTEST_ALIGNMENT) \
601 ? FASTEST_ALIGNMENT : (ALIGN))
603 /* Make arrays of chars word-aligned for the same reasons. */
604 #define DATA_ALIGNMENT(TYPE, ALIGN) \
605 (TREE_CODE (TYPE) == ARRAY_TYPE \
606 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
607 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
609 /* Set this nonzero if move instructions will actually fail to work
610 when given unaligned data. */
611 #define STRICT_ALIGNMENT 1
613 /* Things that must be doubleword aligned cannot go in the text section,
614 because the linker fails to align the text section enough!
615 Put them in the data section. This macro is only used in this file. */
616 #define MAX_TEXT_ALIGN 32
618 /* This forces all variables and constants to the data section when PIC.
619 This is because the SunOS 4 shared library scheme thinks everything in
620 text is a function, and patches the address to point to a loader stub. */
621 /* This is defined to zero for every system which doesn't use the a.out object
623 #ifndef SUNOS4_SHARED_LIBRARIES
624 #define SUNOS4_SHARED_LIBRARIES 0
627 /* This is defined differently for v9 in a cover file. */
628 #define SELECT_SECTION(T,RELOC) \
630 if (TREE_CODE (T) == VAR_DECL) \
632 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
633 && DECL_INITIAL (T) \
634 && (DECL_INITIAL (T) == error_mark_node \
635 || TREE_CONSTANT (DECL_INITIAL (T))) \
636 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
637 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
642 else if (TREE_CODE (T) == CONSTRUCTOR) \
644 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
647 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
649 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
650 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
651 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
658 /* Use text section for a constant
659 unless we need more alignment than that offers. */
660 /* This is defined differently for v9 in a cover file. */
661 #define SELECT_RTX_SECTION(MODE, X) \
663 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
664 && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \
670 /* Standard register usage. */
672 /* Number of actual hardware registers.
673 The hardware registers are assigned numbers for the compiler
674 from 0 to just below FIRST_PSEUDO_REGISTER.
675 All registers that the compiler knows about must be given numbers,
676 even those that are not normally considered general registers.
678 SPARC has 32 integer registers and 32 floating point registers.
679 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
680 accessible. We still account for them to simplify register computations
681 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
683 Register 100 is used as the integer condition code register. */
685 #define FIRST_PSEUDO_REGISTER 101
687 /* Additional V9 fp regs. */
688 #define SPARC_FIRST_V9_FP_REG 64
689 #define SPARC_LAST_V9_FP_REG 95
690 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
691 #define SPARC_FIRST_V9_FCC_REG 96
692 #define SPARC_LAST_V9_FCC_REG 99
694 #define SPARC_FCC_REG 96
695 /* Integer CC reg. We don't distinguish %icc from %xcc. */
696 #define SPARC_ICC_REG 100
698 /* 1 for registers that have pervasive standard uses
699 and are not available for the register allocator.
701 g1 is free to use as temporary.
702 g2-g4 are reserved for applications. Gcc normally uses them as
703 temporaries, but this can be disabled via the -mno-app-regs option.
704 g5 through g7 are reserved for the operating system.
706 g1 and g5 are free to use as temporaries.
707 g2-g4 are reserved for applications. Gcc normally uses them as
708 temporaries, but this can be disabled via the -mno-app-regs option.
709 g6-g7 are reserved for the operating system.
710 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
711 currently be a fixed register until this pattern is rewritten.
712 Register 1 is also used when restoring call-preserved registers in large
715 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
716 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
719 #define FIXED_REGISTERS \
720 {1, 0, 0, 0, 0, 0, 1, 1, \
721 0, 0, 0, 0, 0, 0, 1, 0, \
722 0, 0, 0, 0, 0, 0, 0, 0, \
723 0, 0, 0, 0, 0, 0, 1, 1, \
725 0, 0, 0, 0, 0, 0, 0, 0, \
726 0, 0, 0, 0, 0, 0, 0, 0, \
727 0, 0, 0, 0, 0, 0, 0, 0, \
728 0, 0, 0, 0, 0, 0, 0, 0, \
730 0, 0, 0, 0, 0, 0, 0, 0, \
731 0, 0, 0, 0, 0, 0, 0, 0, \
732 0, 0, 0, 0, 0, 0, 0, 0, \
733 0, 0, 0, 0, 0, 0, 0, 0, \
737 /* 1 for registers not available across function calls.
738 These must include the FIXED_REGISTERS and also any
739 registers that can be used without being saved.
740 The latter must include the registers where values are returned
741 and the register where structure-value addresses are passed.
742 Aside from that, you can include as many other registers as you like. */
744 #define CALL_USED_REGISTERS \
745 {1, 1, 1, 1, 1, 1, 1, 1, \
746 1, 1, 1, 1, 1, 1, 1, 1, \
747 0, 0, 0, 0, 0, 0, 0, 0, \
748 0, 0, 0, 0, 0, 0, 1, 1, \
750 1, 1, 1, 1, 1, 1, 1, 1, \
751 1, 1, 1, 1, 1, 1, 1, 1, \
752 1, 1, 1, 1, 1, 1, 1, 1, \
753 1, 1, 1, 1, 1, 1, 1, 1, \
755 1, 1, 1, 1, 1, 1, 1, 1, \
756 1, 1, 1, 1, 1, 1, 1, 1, \
757 1, 1, 1, 1, 1, 1, 1, 1, \
758 1, 1, 1, 1, 1, 1, 1, 1, \
762 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
763 they won't be allocated. */
765 #define CONDITIONAL_REGISTER_USAGE \
768 if (! SPARC_ARCH64) \
776 /* ??? We need to scan argv for -fcall-used-. */ \
777 for (regno = 48; regno < 80; regno++) \
778 call_used_regs[regno] = 0; \
783 for (regno = SPARC_FIRST_V9_FP_REG; \
784 regno <= SPARC_LAST_V9_FP_REG; \
786 fixed_regs[regno] = 1; \
787 /* %fcc0 is used by v8 and v9. */ \
788 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
789 regno <= SPARC_LAST_V9_FCC_REG; \
791 fixed_regs[regno] = 1; \
796 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
797 fixed_regs[regno] = 1; \
799 /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
800 fixed_regs[2] |= ! TARGET_APP_REGS; \
801 fixed_regs[3] |= ! TARGET_APP_REGS; \
802 fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
805 /* Let the compiler believe the frame pointer is still \
806 %fp, but output it as %i7. */ \
807 fixed_regs[31] = 1; \
808 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
809 /* ??? This is a hack to disable leaf functions. */ \
810 global_regs[7] = 1; \
812 if (profile_block_flag) \
814 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
822 /* Return number of consecutive hard regs needed starting at reg REGNO
823 to hold something of mode MODE.
824 This is ordinarily the length in words of a value of mode MODE
825 but can be less for certain modes in special long registers.
827 On SPARC, ordinary registers hold 32 bits worth;
828 this means both integer and floating point registers.
829 On v9, integer regs hold 64 bits worth; floating point regs hold
830 32 bits worth (this includes the new fp regs as even the odd ones are
831 included in the hard register count). */
833 #define HARD_REGNO_NREGS(REGNO, MODE) \
836 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
837 : (GET_MODE_SIZE (MODE) + 3) / 4) \
838 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
840 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
841 See sparc.c for how we initialize this. */
842 extern int *hard_regno_mode_classes;
843 extern int sparc_mode_class[];
844 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
845 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
847 /* Value is 1 if it is a good idea to tie two pseudo registers
848 when one has mode MODE1 and one has mode MODE2.
849 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
850 for any hard reg, then this must be 0 for correct output.
852 For V9: SFmode can't be combined with other float modes, because they can't
853 be allocated to the %d registers. Also, DFmode won't fit in odd %f
854 registers, but SFmode will. */
855 #define MODES_TIEABLE_P(MODE1, MODE2) \
856 ((MODE1) == (MODE2) \
857 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
859 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
860 || (MODE1 != SFmode && MODE2 != SFmode)))))
862 /* Specify the registers used for certain standard purposes.
863 The values of these macros are register numbers. */
865 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
866 /* #define PC_REGNUM */
868 /* Register to use for pushing function arguments. */
869 #define STACK_POINTER_REGNUM 14
871 /* Actual top-of-stack address is 92/136 greater than the contents of the
872 stack pointer register for !v9/v9. That is:
873 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
874 address, and 24 bytes for the 6 register parameters.
875 - v9: 128 bytes for the in and local registers + 8 bytes reserved. */
876 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
878 /* The stack bias (amount by which the hardware register is offset by). */
879 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
881 /* Base register for access to local variables of the function. */
882 #define FRAME_POINTER_REGNUM 30
885 /* Register that is used for the return address. */
886 #define RETURN_ADDR_REGNUM 15
889 /* Value should be nonzero if functions must have frame pointers.
890 Zero means the frame pointer need not be set up (and parms
891 may be accessed via the stack pointer) in functions that seem suitable.
892 This is computed in `reload', in reload1.c.
893 Used in flow.c, global.c, and reload1.c.
895 Being a non-leaf function does not mean a frame pointer is needed in the
896 flat window model. However, the debugger won't be able to backtrace through
898 #define FRAME_POINTER_REQUIRED \
899 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
900 || !leaf_function_p ()) \
901 : ! (leaf_function_p () && only_leaf_regs_used ()))
903 /* C statement to store the difference between the frame pointer
904 and the stack pointer values immediately after the function prologue.
906 Note, we always pretend that this is a leaf function because if
907 it's not, there's no point in trying to eliminate the
908 frame pointer. If it is a leaf function, we guessed right! */
909 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
910 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
911 : compute_frame_size (get_frame_size (), 1)))
913 /* Base register for access to arguments of the function. */
914 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
916 /* Register in which static-chain is passed to a function. This must
917 not be a register used by the prologue. */
918 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
920 /* Register which holds offset table for position-independent
923 #define PIC_OFFSET_TABLE_REGNUM 23
925 #define INITIALIZE_PIC initialize_pic ()
926 #define FINALIZE_PIC finalize_pic ()
928 /* Sparc ABI says that quad-precision floats and all structures are returned
930 For v9, all aggregates are returned in memory. */
931 #define RETURN_IN_MEMORY(TYPE) \
932 (TYPE_MODE (TYPE) == BLKmode \
933 || (! TARGET_ARCH64 && (TYPE_MODE (TYPE) == TFmode \
934 || TYPE_MODE (TYPE) == TCmode)))
936 /* Functions which return large structures get the address
937 to place the wanted value at offset 64 from the frame.
938 Must reserve 64 bytes for the in and local registers.
939 v9: Functions which return large structures get the address to place the
940 wanted value from an invisible first argument. */
941 /* Used only in other #defines in this file. */
942 #define STRUCT_VALUE_OFFSET 64
944 #define STRUCT_VALUE \
947 : gen_rtx (MEM, Pmode, \
948 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
949 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
950 #define STRUCT_VALUE_INCOMING \
953 : gen_rtx (MEM, Pmode, \
954 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
955 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
957 /* Define the classes of registers for register constraints in the
958 machine description. Also define ranges of constants.
960 One of the classes must always be named ALL_REGS and include all hard regs.
961 If there is more than one class, another class must be named NO_REGS
962 and contain no registers.
964 The name GENERAL_REGS must be the name of a class (or an alias for
965 another name such as ALL_REGS). This is the class of registers
966 that is allowed by "g" or "r" in a register constraint.
967 Also, registers outside this class are allocated only when
968 instructions express preferences for them.
970 The classes must be numbered in nondecreasing order; that is,
971 a larger-numbered class must never be contained completely
972 in a smaller-numbered class.
974 For any two classes, it is very desirable that there be another
975 class that represents their union. */
977 /* The SPARC has two kinds of registers, general and floating point.
979 For v9 we must distinguish between the upper and lower floating point
980 registers because the upper ones can't hold SFmode values.
981 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
982 satisfying a group need for a class will also satisfy a single need for
983 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
986 It is important that one class contains all the general and all the standard
987 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
988 because reg_class_record() will bias the selection in favor of fp regs,
989 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
990 because FP_REGS > GENERAL_REGS.
992 It is also important that one class contain all the general and all the
993 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
994 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
995 allocate_reload_reg() to bypass it causing an abort because the compiler
996 thinks it doesn't have a spill reg when in fact it does.
998 v9 also has 4 floating point condition code registers. Since we don't
999 have a class that is the union of FPCC_REGS with either of the others,
1000 it is important that it appear first. Otherwise the compiler will die
1001 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1004 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1005 may try to use it to hold an SImode value. See register_operand.
1006 ??? Should %fcc[0123] be handled similarily?
1009 enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
1010 GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1011 ALL_REGS, LIM_REG_CLASSES };
1013 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1015 /* Give names of register classes as strings for dump file. */
1017 #define REG_CLASS_NAMES \
1018 { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \
1019 "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" }
1021 /* Define which registers fit in which classes.
1022 This is an initializer for a vector of HARD_REG_SET
1023 of length N_REG_CLASSES. */
1025 #define REG_CLASS_CONTENTS \
1026 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, \
1027 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1028 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1030 /* The same information, inverted:
1031 Return the class number of the smallest class containing
1032 reg number REGNO. This could be a conditional expression
1033 or could index an array. */
1035 extern enum reg_class sparc_regno_reg_class[];
1037 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1039 /* This is the order in which to allocate registers normally.
1041 We put %f0/%f1 last among the float registers, so as to make it more
1042 likely that a pseudo-register which dies in the float return register
1043 will get allocated to the float return register, thus saving a move
1044 instruction at the end of the function.
1046 The float registers are ordered a little "funny" because in the 64 bit
1047 architecture, some of them (%f16-%f47) are call-preserved. */
1049 #define REG_ALLOC_ORDER \
1050 { 8, 9, 10, 11, 12, 13, 2, 3, \
1051 15, 16, 17, 18, 19, 20, 21, 22, \
1052 23, 24, 25, 26, 27, 28, 29, 31, \
1053 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1054 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1055 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1056 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1057 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1058 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1059 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1060 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1061 32, 33, /* %f0,%f1 */ \
1062 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1063 1, 4, 5, 6, 7, 0, 14, 30}
1065 /* This is the order in which to allocate registers for
1066 leaf functions. If all registers can fit in the "i" registers,
1067 then we have the possibility of having a leaf function.
1068 The floating point registers are ordered a little "funny" because in the
1069 64 bit architecture some of them (%f16-%f47) are call-preserved. */
1071 #define REG_LEAF_ALLOC_ORDER \
1072 { 2, 3, 24, 25, 26, 27, 28, 29, \
1073 15, 8, 9, 10, 11, 12, 13, \
1074 16, 17, 18, 19, 20, 21, 22, 23, \
1075 34, 35, 36, 37, 38, 39, \
1076 40, 41, 42, 43, 44, 45, 46, 47, \
1077 80, 81, 82, 83, 84, 85, 86, 87, \
1078 88, 89, 90, 91, 92, 93, 94, 95, \
1079 48, 49, 50, 51, 52, 53, 54, 55, \
1080 56, 57, 58, 59, 60, 61, 62, 63, \
1081 64, 65, 66, 67, 68, 69, 70, 71, \
1082 72, 73, 74, 75, 76, 77, 78, 79, \
1084 96, 97, 98, 99, 100, \
1085 1, 4, 5, 6, 7, 0, 14, 30, 31}
1087 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1089 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
1090 -mflat is used. Function only_leaf_regs_used will return 0 if a global
1091 register is used and is not permitted in a leaf function. We make %g7
1092 a global reg if -mflat and voila. Since %g7 is a system register and is
1093 fixed it won't be used by gcc anyway. */
1095 #define LEAF_REGISTERS \
1096 { 1, 1, 1, 1, 1, 1, 1, 0, \
1097 0, 0, 0, 0, 0, 0, 1, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 0, \
1099 1, 1, 1, 1, 1, 1, 0, 1, \
1100 1, 1, 1, 1, 1, 1, 1, 1, \
1101 1, 1, 1, 1, 1, 1, 1, 1, \
1102 1, 1, 1, 1, 1, 1, 1, 1, \
1103 1, 1, 1, 1, 1, 1, 1, 1, \
1104 1, 1, 1, 1, 1, 1, 1, 1, \
1105 1, 1, 1, 1, 1, 1, 1, 1, \
1106 1, 1, 1, 1, 1, 1, 1, 1, \
1107 1, 1, 1, 1, 1, 1, 1, 1, \
1110 extern char leaf_reg_remap[];
1111 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1113 /* The class value for index registers, and the one for base regs. */
1114 #define INDEX_REG_CLASS GENERAL_REGS
1115 #define BASE_REG_CLASS GENERAL_REGS
1117 /* Local macro to handle the two v9 classes of FP regs. */
1118 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1120 /* Get reg_class from a letter such as appears in the machine description.
1121 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1122 .md file for v8 and v9. */
1124 #define REG_CLASS_FROM_LETTER(C) \
1126 ? ((C) == 'f' ? FP_REGS \
1127 : (C) == 'e' ? EXTRA_FP_REGS \
1128 : (C) == 'c' ? FPCC_REGS \
1130 : ((C) == 'f' ? FP_REGS \
1131 : (C) == 'e' ? FP_REGS \
1132 : (C) == 'c' ? FPCC_REGS \
1135 /* The letters I, J, K, L and M in a register constraint string
1136 can be used to stand for particular ranges of immediate operands.
1137 This macro defines what the ranges are.
1138 C is the letter, and VALUE is a constant value.
1139 Return 1 if VALUE is in the range specified by C.
1141 For SPARC, `I' is used for the range of constants an insn
1142 can actually contain.
1143 `J' is used for the range which is just zero (since that is R0).
1144 `K' is used for constants which can be loaded with a single sethi insn. */
1146 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
1148 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1149 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
1150 : (C) == 'J' ? (VALUE) == 0 \
1151 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
1154 /* Similar, but for floating constants, and defining letters G and H.
1155 Here VALUE is the CONST_DOUBLE rtx itself. */
1157 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1158 ((C) == 'G' ? fp_zero_operand (VALUE) \
1159 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1162 /* Given an rtx X being reloaded into a reg required to be
1163 in class CLASS, return the class of reg to actually use.
1164 In general this is just CLASS; but on some machines
1165 in some cases it is preferable to use a more restrictive class. */
1166 /* We can't load constants into FP registers. We can't load any FP constant
1167 if an 'E' constraint fails to match it. */
1168 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1170 && (FP_REG_CLASS_P (CLASS) \
1171 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1172 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1173 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1174 ? NO_REGS : (CLASS))
1176 /* Return the register class of a scratch register needed to load IN into
1177 a register of class CLASS in MODE.
1179 On the SPARC, when PIC, we need a temporary when loading some addresses
1182 Also, we need a temporary when loading/storing a HImode/QImode value
1183 between memory and the FPU registers. This can happen when combine puts
1184 a paradoxical subreg in a float/fix conversion insn. */
1186 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1187 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1188 && (GET_CODE (IN) == MEM \
1189 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1190 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1192 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1193 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1194 && (GET_CODE (IN) == MEM \
1195 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1196 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1198 /* On SPARC it is not possible to directly move data between
1199 GENERAL_REGS and FP_REGS. */
1200 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1201 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1203 /* Return the stack location to use for secondary memory needed reloads.
1204 We want to use the reserved location just below the frame pointer.
1205 However, we must ensure that there is a frame, so use assign_stack_local
1206 if the frame size is zero. */
1207 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1208 (get_frame_size () == 0 \
1209 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1210 : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1211 GEN_INT (STARTING_FRAME_OFFSET))))
1213 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1214 because the movsi and movsf patterns don't handle r/f moves.
1215 For v8 we copy the default definition. */
1216 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1218 ? (GET_MODE_BITSIZE (MODE) < 32 \
1219 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1221 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1222 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1225 /* Return the maximum number of consecutive registers
1226 needed to represent mode MODE in a register of class CLASS. */
1227 /* On SPARC, this is the size of MODE in words. */
1228 #define CLASS_MAX_NREGS(CLASS, MODE) \
1229 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1230 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1232 /* Stack layout; function entry, exit and calling. */
1234 /* Define the number of register that can hold parameters.
1235 These two macros are used only in other macro definitions below.
1236 MODE is the mode of the argument.
1237 !v9: All args are passed in %o0-%o5.
1238 v9: Non-float args are passed in %o0-5 and float args are passed in
1240 #define NPARM_REGS(MODE) \
1241 (TARGET_ARCH64 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6)
1243 /* Define this if pushing a word on the stack
1244 makes the stack pointer a smaller address. */
1245 #define STACK_GROWS_DOWNWARD
1247 /* Define this if the nominal address of the stack frame
1248 is at the high-address end of the local variables;
1249 that is, each additional local variable allocated
1250 goes at a more negative offset in the frame. */
1251 #define FRAME_GROWS_DOWNWARD
1253 /* Offset within stack frame to start allocating local variables at.
1254 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1255 first local allocated. Otherwise, it is the offset to the BEGINNING
1256 of the first local allocated. */
1257 /* This allows space for one TFmode floating point value. */
1258 #define STARTING_FRAME_OFFSET \
1259 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1260 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1262 /* If we generate an insn to push BYTES bytes,
1263 this says how many the stack pointer really advances by.
1264 On SPARC, don't define this because there are no push insns. */
1265 /* #define PUSH_ROUNDING(BYTES) */
1267 /* Offset of first parameter from the argument pointer register value.
1268 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1269 even if this function isn't going to use it.
1270 v9: This is 128 for the ins and locals, plus a reserved space of 8. */
1271 #define FIRST_PARM_OFFSET(FNDECL) \
1272 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 136) \
1273 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1275 /* When a parameter is passed in a register, stack space is still
1276 allocated for it. */
1278 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD)
1281 /* Keep the stack pointer constant throughout the function.
1282 This is both an optimization and a necessity: longjmp
1283 doesn't behave itself when the stack pointer moves within
1285 #define ACCUMULATE_OUTGOING_ARGS
1287 /* Value is the number of bytes of arguments automatically
1288 popped when returning from a subroutine call.
1289 FUNDECL is the declaration node of the function (as a tree),
1290 FUNTYPE is the data type of the function (as a tree),
1291 or for a library call it is an identifier node for the subroutine name.
1292 SIZE is the number of bytes of arguments passed on the stack. */
1294 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1296 /* Some subroutine macros specific to this machine.
1297 When !TARGET_FPU, put float return values in the general registers,
1298 since we don't have any fp registers. */
1299 #define BASE_RETURN_VALUE_REG(MODE) \
1301 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1302 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1303 #define BASE_OUTGOING_VALUE_REG(MODE) \
1305 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1306 : TARGET_FLAT ? 8 : 24) \
1307 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1308 : (TARGET_FLAT ? 8 : 24)))
1309 #define BASE_PASSING_ARG_REG(MODE) \
1311 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1313 #define BASE_INCOMING_ARG_REG(MODE) \
1315 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1316 : TARGET_FLAT ? 8 : 24) \
1317 : (TARGET_FLAT ? 8 : 24))
1319 /* Define this macro if the target machine has "register windows". This
1320 C expression returns the register number as seen by the called function
1321 corresponding to register number OUT as seen by the calling function.
1322 Return OUT if register number OUT is not an outbound register. */
1324 #define INCOMING_REGNO(OUT) \
1325 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1327 /* Define this macro if the target machine has "register windows". This
1328 C expression returns the register number as seen by the calling function
1329 corresponding to register number IN as seen by the called function.
1330 Return IN if register number IN is not an inbound register. */
1332 #define OUTGOING_REGNO(IN) \
1333 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1335 /* Define how to find the value returned by a function.
1336 VALTYPE is the data type of the value (as a tree).
1337 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1338 otherwise, FUNC is 0. */
1340 /* On SPARC the value is found in the first "output" register. */
1342 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1343 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1345 /* But the called function leaves it in the first "input" register. */
1347 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1348 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1350 /* Define how to find the value returned by a library function
1351 assuming the value has mode MODE. */
1353 #define LIBCALL_VALUE(MODE) \
1354 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1356 /* 1 if N is a possible register number for a function value
1357 as seen by the caller.
1358 On SPARC, the first "output" reg is used for integer values,
1359 and the first floating point register is used for floating point values. */
1361 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1363 /* Define the size of space to allocate for the return value of an
1366 #define APPLY_RESULT_SIZE 16
1368 /* 1 if N is a possible register number for function argument passing.
1369 On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */
1371 #define FUNCTION_ARG_REGNO_P(N) \
1372 (TARGET_ARCH64 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \
1373 : ((N) < 14 && (N) > 7))
1375 /* Define a data type for recording info about an argument list
1376 during the scan of that argument list. This data type should
1377 hold all necessary information about the function itself
1378 and about the args processed so far, enough to enable macros
1379 such as FUNCTION_ARG to determine where the next arg should go.
1381 On SPARC (!v9), this is a single integer, which is a number of words
1382 of arguments scanned so far (including the invisible argument,
1383 if any, which holds the structure-value-address).
1384 Thus 7 or more means all following args should go on the stack.
1386 For v9, we record how many of each type has been passed. Different
1387 types get passed differently.
1389 - Float args are passed in %f0-15, after which they go to the stack
1390 where floats and doubles are passed 8 byte aligned and long doubles
1391 are passed 16 byte aligned.
1392 - All aggregates are passed by reference. The callee copies
1393 the structure if necessary, except if stdarg/varargs and the struct
1394 matches the ellipse in which case the caller makes a copy.
1395 - Any non-float argument might be split between memory and reg %o5.
1396 ??? I don't think this can ever happen now that structs are no
1397 longer passed in regs.
1399 For v9 return values:
1401 - For all aggregates, the caller allocates space for the return value,
1402 and passes the pointer as an implicit first argument, which is
1403 allocated like all other arguments.
1404 - The unimp instruction stuff for structure returns is gone. */
1407 enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 };
1409 int arg_count[2]; /* must be int! (for __builtin_args_info) */
1411 #define CUMULATIVE_ARGS struct sparc_args
1413 /* Return index into CUMULATIVE_ARGS. */
1415 #define GET_SPARC_ARG_CLASS(MODE) \
1416 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT)
1418 /* Round a register number up to a proper boundary for an arg of mode MODE.
1419 This macro is only used in this file.
1421 The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */
1423 #define ROUND_REG(CUM, MODE) \
1424 (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1425 ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1426 : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1427 + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \
1428 & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4))
1430 #define ROUND_ADVANCE(SIZE) \
1431 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1433 #else /* ! SPARC_ARCH64 */
1435 #define CUMULATIVE_ARGS int
1437 #define ROUND_REG(CUM, MODE) (CUM)
1439 #define ROUND_ADVANCE(SIZE) \
1440 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1441 #endif /* ! SPARC_ARCH64 */
1443 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1444 for a call to a function whose data type is FNTYPE.
1445 For a library call, FNTYPE is 0.
1447 On SPARC, the offset always starts at 0: the first parm reg is always
1451 extern int sparc_arg_count,sparc_n_named_args;
1452 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
1454 (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \
1455 (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \
1456 sparc_arg_count = 0; \
1457 sparc_n_named_args = \
1458 ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \
1459 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \
1460 + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \
1461 || TREE_CODE (TREE_TYPE (FNTYPE)) == QUAL_UNION_TYPE\
1462 || TREE_CODE (TREE_TYPE (FNTYPE)) == SET_TYPE \
1463 || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \
1464 /* Can't tell, treat 'em all as named. */ \
1468 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
1471 /* Update the data in CUM to advance over an argument
1472 of mode MODE and data type TYPE.
1473 (TYPE is null for libcalls where that information may not be available.) */
1476 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1478 (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \
1479 ROUND_REG ((CUM), (MODE)) \
1480 + (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1481 ? GET_MODE_SIZE (MODE) / 4 \
1482 : ROUND_ADVANCE ((MODE) == BLKmode \
1483 ? GET_MODE_SIZE (Pmode) \
1484 : GET_MODE_SIZE (MODE))); \
1485 sparc_arg_count++; \
1488 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1489 ((CUM) += ((MODE) != BLKmode \
1490 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1491 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
1494 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1495 This macro is only used in this file. */
1498 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1499 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
1500 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1501 && ((TYPE)==0 || (MODE) != BLKmode))
1503 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1504 ((CUM) < NPARM_REGS (SImode) \
1505 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1506 && ((TYPE)==0 || (MODE) != BLKmode \
1507 || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0)))
1510 /* Determine where to put an argument to a function.
1511 Value is zero to push the argument on the stack,
1512 or a hard register in which to store the argument.
1514 MODE is the argument's machine mode.
1515 TYPE is the data type of the argument (as a tree).
1516 This is null for libcalls where that information may
1518 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1519 the preceding args and about the function being called.
1520 NAMED is nonzero if this argument is a named parameter
1521 (otherwise it is an extra parameter matching an ellipsis). */
1523 /* On SPARC the first six args are normally in registers
1524 and the rest are pushed. Any arg that starts within the first 6 words
1525 is at least partially passed in a register unless its data type forbids.
1526 For v9, the first 6 int args are passed in regs and the first N
1527 float args are passed in regs (where N is such that %f0-15 are filled).
1528 The rest are pushed. Any arg that starts within the first 6 words
1529 is at least partially passed in a register unless its data type forbids. */
1531 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1532 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1533 ? gen_rtx (REG, (MODE), \
1534 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1537 /* Define where a function finds its arguments.
1538 This is different from FUNCTION_ARG because of register windows. */
1540 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1541 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1542 ? gen_rtx (REG, (MODE), \
1543 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1546 /* For an arg passed partly in registers and partly in memory,
1547 this is the number of registers used.
1548 For args passed entirely in registers or entirely in memory, zero.
1549 Any arg that starts in the first 6 regs but won't entirely fit in them
1550 needs partial registers on the Sparc (!v9). On v9, there are no arguments
1551 that are passed partially in registers (??? complex values?). */
1554 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1555 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1556 && ((CUM) + ((MODE) == BLKmode \
1557 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1558 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\
1559 ? (NPARM_REGS (SImode) - (CUM)) \
1563 /* The SPARC ABI stipulates passing struct arguments (of any size) and
1564 (!v9) quad-precision floats by invisible reference.
1565 For Pascal, also pass arrays by reference. */
1566 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1567 ((TYPE && AGGREGATE_TYPE_P (TYPE)) \
1568 || (!TARGET_ARCH64 && MODE == TFmode))
1570 /* A C expression that indicates when it is the called function's
1571 responsibility to make copies of arguments passed by reference.
1572 If the callee can determine that the argument won't be modified, it can
1574 /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't
1575 include the last named argument so we keep track of the args ourselves. */
1578 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1579 (sparc_arg_count < sparc_n_named_args)
1582 /* Initialize data used by insn expanders. This is called from
1583 init_emit, once for each function, before code is generated.
1584 For v9, clear the temp slot used by float/int DImode conversions.
1585 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1586 space at some point.
1587 ??? Use assign_stack_temp? */
1589 extern void sparc64_init_expanders ();
1590 extern struct rtx_def *sparc64_fpconv_stack_temp ();
1592 #define INIT_EXPANDERS sparc64_init_expanders ()
1595 /* Define the information needed to generate branch and scc insns. This is
1596 stored from the compare operation. Note that we can't use "rtx" here
1597 since it hasn't been defined! */
1599 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1601 /* Define the function that build the compare insn for scc and bcc. */
1603 extern struct rtx_def *gen_compare_reg ();
1605 /* This function handles all v9 scc insns */
1607 extern int gen_v9_scc ();
1609 /* Generate the special assembly code needed to tell the assembler whatever
1610 it might need to know about the return value of a function.
1612 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1613 information to the assembler relating to peephole optimization (done in
1616 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1617 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1619 /* Output the label for a function definition. */
1621 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1623 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1624 ASM_OUTPUT_LABEL (FILE, NAME); \
1627 /* This macro generates the assembly code for function entry.
1628 FILE is a stdio stream to output the code to.
1629 SIZE is an int: how many units of temporary storage to allocate.
1630 Refer to the array `regs_ever_live' to determine which registers
1631 to save; `regs_ever_live[I]' is nonzero if register number I
1632 is ever used in the function. This macro is responsible for
1633 knowing which registers should not be saved even if used. */
1635 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1636 of memory. If any fpu reg is used in the function, we allocate
1637 such a block here, at the bottom of the frame, just in case it's needed.
1639 If this function is a leaf procedure, then we may choose not
1640 to do a "save" insn. The decision about whether or not
1641 to do this is made in regclass.c. */
1643 extern int leaf_function;
1644 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1645 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, SIZE) \
1646 : output_function_prologue (FILE, SIZE, leaf_function))
1648 /* Output assembler code to FILE to increment profiler label # LABELNO
1649 for profiling a function entry. */
1651 #define FUNCTION_PROFILER(FILE, LABELNO) \
1653 fputs ("\tsethi %hi(", (FILE)); \
1654 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1655 fputs ("),%o0\n", (FILE)); \
1656 if (TARGET_MEDANY) \
1657 fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \
1659 fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \
1660 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1661 fputs ("),%o0,%o0\n", (FILE)); \
1665 /* There are three profiling modes for basic blocks available.
1666 The modes are selected at compile time by using the options
1667 -a or -ax of the gnu compiler.
1668 The variable `profile_block_flag' will be set according to the
1671 profile_block_flag == 0, no option used:
1675 profile_block_flag == 1, -a option used.
1677 Count frequency of execution of every basic block.
1679 profile_block_flag == 2, -ax option used.
1681 Generate code to allow several different profiling modes at run time.
1682 Available modes are:
1683 Produce a trace of all basic blocks.
1684 Count frequency of jump instructions executed.
1685 In every mode it is possible to start profiling upon entering
1686 certain functions and to disable profiling of some other functions.
1688 The result of basic-block profiling will be written to a file `bb.out'.
1689 If the -ax option is used parameters for the profiling will be read
1694 /* The following macro shall output assembler code to FILE
1695 to initialize basic-block profiling.
1697 If profile_block_flag == 2
1699 Output code to call the subroutine `__bb_init_trace_func'
1700 and pass two parameters to it. The first parameter is
1701 the address of a block allocated in the object module.
1702 The second parameter is the number of the first basic block
1705 The name of the block is a local symbol made with this statement:
1707 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1709 Of course, since you are writing the definition of
1710 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1711 can take a short cut in the definition of this macro and use the
1712 name that you know will result.
1714 The number of the first basic block of the function is
1715 passed to the macro in BLOCK_OR_LABEL.
1717 If described in a virtual assembler language the code to be
1721 parameter2 <- BLOCK_OR_LABEL
1722 call __bb_init_trace_func
1724 else if profile_block_flag != 0
1726 Output code to call the subroutine `__bb_init_func'
1727 and pass one single parameter to it, which is the same
1728 as the first parameter to `__bb_init_trace_func'.
1730 The first word of this parameter is a flag which will be nonzero if
1731 the object module has already been initialized. So test this word
1732 first, and do not call `__bb_init_func' if the flag is nonzero.
1733 Note: When profile_block_flag == 2 the test need not be done
1734 but `__bb_init_trace_func' *must* be called.
1736 BLOCK_OR_LABEL may be used to generate a label number as a
1737 branch destination in case `__bb_init_func' will not be called.
1739 If described in a virtual assembler language the code to be
1750 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1753 int bol = (BLOCK_OR_LABEL); \
1754 switch (profile_block_flag) \
1757 if (TARGET_MEDANY) \
1758 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
1759 MEDANY_BASE_REG, bol, bol); \
1761 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
1765 if (TARGET_MEDANY) \
1766 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1767 MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
1769 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1776 /* The following macro shall output assembler code to FILE
1777 to increment a counter associated with basic block number BLOCKNO.
1779 If profile_block_flag == 2
1781 Output code to initialize the global structure `__bb' and
1782 call the function `__bb_trace_func' which will increment the
1785 `__bb' consists of two words. In the first word the number
1786 of the basic block has to be stored. In the second word
1787 the address of a block allocated in the object module
1790 The basic block number is given by BLOCKNO.
1792 The address of the block is given by the label created with
1794 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1796 by FUNCTION_BLOCK_PROFILER.
1798 Of course, since you are writing the definition of
1799 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1800 can take a short cut in the definition of this macro and use the
1801 name that you know will result.
1803 If described in a virtual assembler language the code to be
1806 move BLOCKNO -> (__bb)
1807 move LPBX0 -> (__bb+4)
1808 call __bb_trace_func
1810 Note that function `__bb_trace_func' must not change the
1811 machine state, especially the flag register. To grant
1812 this, you must output code to save and restore registers
1813 either in this macro or in the macros MACHINE_STATE_SAVE
1814 and MACHINE_STATE_RESTORE. The last two macros will be
1815 used in the function `__bb_trace_func', so you must make
1816 sure that the function prologue does not change any
1817 register prior to saving it with MACHINE_STATE_SAVE.
1819 else if profile_block_flag != 0
1821 Output code to increment the counter directly.
1822 Basic blocks are numbered separately from zero within each
1823 compiled object module. The count associated with block number
1824 BLOCKNO is at index BLOCKNO in an array of words; the name of
1825 this array is a local symbol made with this statement:
1827 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
1829 Of course, since you are writing the definition of
1830 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1831 can take a short cut in the definition of this macro and use the
1832 name that you know will result.
1834 If described in a virtual assembler language, the code to be
1837 inc (LPBX2+4*BLOCKNO)
1841 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1844 int blockn = (BLOCKNO); \
1845 switch (profile_block_flag) \
1848 if (TARGET_MEDANY) \
1849 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1850 blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1852 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1856 if (TARGET_MEDANY) \
1857 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1858 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1860 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1861 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1862 4 * blockn, 4 * blockn, 4 * blockn); \
1868 /* The following macro shall output assembler code to FILE
1869 to indicate a return from function during basic-block profiling.
1871 If profiling_block_flag == 2:
1873 Output assembler code to call function `__bb_trace_ret'.
1875 Note that function `__bb_trace_ret' must not change the
1876 machine state, especially the flag register. To grant
1877 this, you must output code to save and restore registers
1878 either in this macro or in the macros MACHINE_STATE_SAVE_RET
1879 and MACHINE_STATE_RESTORE_RET. The last two macros will be
1880 used in the function `__bb_trace_ret', so you must make
1881 sure that the function prologue does not change any
1882 register prior to saving it with MACHINE_STATE_SAVE_RET.
1884 else if profiling_block_flag != 0:
1886 The macro will not be used, so it need not distinguish
1890 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1891 fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
1893 /* The function `__bb_trace_func' is called in every basic block
1894 and is not allowed to change the machine state. Saving (restoring)
1895 the state can either be done in the BLOCK_PROFILER macro,
1896 before calling function (rsp. after returning from function)
1897 `__bb_trace_func', or it can be done inside the function by
1898 defining the macros:
1900 MACHINE_STATE_SAVE(ID)
1901 MACHINE_STATE_RESTORE(ID)
1903 In the latter case care must be taken, that the prologue code
1904 of function `__bb_trace_func' does not already change the
1905 state prior to saving it with MACHINE_STATE_SAVE.
1907 The parameter `ID' is a string identifying a unique macro use.
1909 On sparc it is sufficient to save the psw register to memory.
1910 Unfortunately the psw register can be read in supervisor mode only,
1911 so we read only the condition codes by using branch instructions
1912 and hope that this is enough. */
1914 #define MACHINE_STATE_SAVE(ID) \
1915 asm (" mov %g0,%l0");\
1916 asm (" be,a LFLGNZ" ID);\
1917 asm (" or %l0,4,%l0");\
1918 asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\
1919 asm (" or %l0,1,%l0");\
1920 asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\
1921 asm (" or %l0,2,%l0");\
1922 asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\
1923 asm (" or %l0,8,%l0");\
1924 asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\
1925 asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \
1926 asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]");
1928 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1929 The psw register can be written in supervisor mode only,
1930 which is true even for simple condition codes.
1931 We use some combination of instructions to produce the
1932 proper condition codes, but some flag combinations can not
1933 be generated in this way. If this happens an unimplemented
1934 instruction will be executed to abort the program. */
1936 #define MACHINE_STATE_RESTORE(ID) \
1937 asm (" sethi %hi(LFLGTAB" ID "),%l1");\
1938 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\
1939 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\
1940 asm (" sll %l0,2,%l0");\
1941 asm (" add %l0,%l1,%l0");\
1942 asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\
1947 asm ("LFLAGS" ID ":");\
1949 asm ("LSAVRET" ID ":");\
1951 asm ("LFLGTAB" ID ": ");\
1952 asm (" .word LSFLG0" ID);\
1953 asm (" .word LSFLGC" ID);\
1954 asm (" .word LSFLGV" ID);\
1955 asm (" .word LSFLGVC" ID);\
1956 asm (" .word LSFLGZ" ID);\
1957 asm (" .word LSFLGZC" ID);\
1958 asm (" .word LSFLGZV" ID);\
1959 asm (" .word LSFLGZVC" ID);\
1960 asm (" .word LSFLGN" ID);\
1961 asm (" .word LSFLGNC" ID);\
1962 asm (" .word LSFLGNV" ID);\
1963 asm (" .word LSFLGNVC" ID);\
1964 asm (" .word LSFLGNZ" ID);\
1965 asm (" .word LSFLGNZC" ID);\
1966 asm (" .word LSFLGNZV" ID);\
1967 asm (" .word LSFLGNZVC" ID);\
1969 asm ("LSFLGVC" ID ": mov -1,%l0");\
1970 asm (" addcc 2,%l0,%g0");\
1971 asm (" sethi %hi(0x80000000),%l0");\
1972 asm (" mov %l0,%l1");\
1973 asm (" ba LFLGRET" ID);\
1974 asm (" addxcc %l0,%l1,%l0");\
1975 asm ("LSFLGC" ID ": mov -1,%l0");\
1976 asm (" ba LFLGRET" ID);\
1977 asm (" addcc 2,%l0,%g0");\
1978 asm ("LSFLGZC" ID ": mov -1,%l0");\
1979 asm (" ba LFLGRET" ID);\
1980 asm (" addcc 1,%l0,%l0");\
1981 asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\
1982 asm (" mov %l0,%l1");\
1983 asm (" ba LFLGRET" ID);\
1984 asm (" addcc %l0,%l1,%l0");\
1985 asm ("LSFLGZ" ID ": ba LFLGRET" ID);\
1986 asm (" subcc %g0,%g0,%g0");\
1987 asm ("LSFLGNC" ID ": add %g0,1,%l0");\
1988 asm (" ba LFLGRET" ID);\
1989 asm (" subcc %g0,%l0,%g0");\
1990 asm ("LSFLG0" ID ": ba LFLGRET" ID);\
1991 asm (" orcc 1,%g0,%g0");\
1992 asm ("LSFLGN" ID ": ba LFLGRET" ID);\
1993 asm (" orcc -1,%g0,%g0");\
1994 asm ("LSFLGV" ID ":");\
1995 asm ("LSFLGZV" ID ":");\
1996 asm ("LSFLGNV" ID ":");\
1997 asm ("LSFLGNVC" ID ":");\
1998 asm ("LSFLGNZ" ID ":");\
1999 asm ("LSFLGNZC" ID ":");\
2000 asm ("LSFLGNZV" ID ":");\
2001 asm ("LSFLGNZVC" ID ":");\
2003 asm ("LFLGRET" ID ":");
2005 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2006 the stack pointer does not matter. The value is tested only in
2007 functions that have frame pointers.
2008 No definition is equivalent to always zero. */
2010 extern int current_function_calls_alloca;
2011 extern int current_function_outgoing_args_size;
2013 #define EXIT_IGNORE_STACK \
2014 (get_frame_size () != 0 \
2015 || current_function_calls_alloca || current_function_outgoing_args_size)
2017 /* This macro generates the assembly code for function exit,
2018 on machines that need it. If FUNCTION_EPILOGUE is not defined
2019 then individual return instructions are generated for each
2020 return statement. Args are same as for FUNCTION_PROLOGUE.
2022 The function epilogue should not depend on the current stack pointer!
2023 It should use the frame pointer only. This is mandatory because
2024 of alloca; we also take advantage of it to omit stack adjustments
2025 before returning. */
2027 /* This declaration is needed due to traditional/ANSI
2028 incompatibilities which cannot be #ifdefed away
2029 because they occur inside of macros. Sigh. */
2030 extern union tree_node *current_function_decl;
2032 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2033 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, SIZE) \
2034 : output_function_epilogue (FILE, SIZE, leaf_function))
2036 #define DELAY_SLOTS_FOR_EPILOGUE \
2037 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2038 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2039 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2040 : eligible_for_epilogue_delay (trial, slots_filled))
2042 /* Output assembler code for a block containing the constant parts
2043 of a trampoline, leaving space for the variable parts. */
2045 /* On 32 bit sparcs, the trampoline contains five instructions:
2046 sethi #TOP_OF_FUNCTION,%g1
2047 or #BOTTOM_OF_FUNCTION,%g1,%g1
2048 sethi #TOP_OF_STATIC,%g2
2050 or #BOTTOM_OF_STATIC,%g2,%g2
2052 On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate
2053 constants (plus some padding):
2063 #define TRAMPOLINE_TEMPLATE(FILE) \
2065 if (TARGET_ARCH64) \
2067 fprintf (FILE, "\trd %%pc,%%g1\n"); \
2068 fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \
2069 fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \
2070 fprintf (FILE, "\tjmp %%g1\n"); \
2071 fprintf (FILE, "\tnop\n"); \
2072 fprintf (FILE, "\tnop\n"); \
2073 /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \
2074 fprintf (FILE, "\t.word 0,0,0,0\n"); \
2078 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2079 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2080 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2081 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
2082 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2086 /* Length in units of the trampoline for entering a nested function. */
2088 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 40 : 20)
2090 /* Emit RTL insns to initialize the variable parts of a trampoline.
2091 FNADDR is an RTX for the address of the function's pure code.
2092 CXT is an RTX for the static chain value for the function. */
2094 void sparc_initialize_trampoline ();
2095 void sparc64_initialize_trampoline ();
2096 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2098 if (TARGET_ARCH64) \
2099 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2101 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
2104 /* Generate necessary RTL for __builtin_saveregs().
2105 ARGLIST is the argument list; see expr.c. */
2106 extern struct rtx_def *sparc_builtin_saveregs ();
2107 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
2109 /* Generate RTL to flush the register windows so as to make arbitrary frames
2111 #define SETUP_FRAME_ADDRESSES() \
2112 emit_insn (gen_flush_register_windows ())
2114 /* Given an rtx for the address of a frame,
2115 return an rtx for the address of the word in the frame
2116 that holds the dynamic chain--the previous frame's address.
2117 ??? -mflat support? */
2118 #define DYNAMIC_CHAIN_ADDRESS(frame) \
2119 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
2121 /* The return address isn't on the stack, it is in a register, so we can't
2122 access it from the current frame pointer. We can access it from the
2123 previous frame pointer though by reading a value from the register window
2125 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2127 /* This is the offset of the return address to the true next instruction to be
2128 executed for the current function. */
2129 #define RETURN_ADDR_OFFSET \
2130 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2132 /* The current return address is in %i7. The return address of anything
2133 farther back is in the register window save area at [%fp+60]. */
2134 /* ??? This ignores the fact that the actual return address is +8 for normal
2135 returns, and +12 for structure returns. */
2136 #define RETURN_ADDR_RTX(count, frame) \
2138 ? gen_rtx (REG, Pmode, 31) \
2139 : gen_rtx (MEM, Pmode, \
2140 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
2142 /* Addressing modes, and classification of registers for them. */
2144 /* #define HAVE_POST_INCREMENT */
2145 /* #define HAVE_POST_DECREMENT */
2147 /* #define HAVE_PRE_DECREMENT */
2148 /* #define HAVE_PRE_INCREMENT */
2150 /* Macros to check register numbers against specific register classes. */
2152 /* These assume that REGNO is a hard or pseudo reg number.
2153 They give nonzero only if REGNO is a hard reg of the suitable class
2154 or a pseudo reg currently allocated to a suitable hard reg.
2155 Since they use reg_renumber, they are safe only once reg_renumber
2156 has been allocated, which happens in local-alloc.c. */
2158 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2159 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2160 #define REGNO_OK_FOR_BASE_P(REGNO) \
2161 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2162 #define REGNO_OK_FOR_FP_P(REGNO) \
2163 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
2164 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
2165 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2167 && (((unsigned) (REGNO) - 96 < 4) \
2168 || ((unsigned) reg_renumber[REGNO] - 96 < 4)))
2170 /* Now macros that check whether X is a register and also,
2171 strictly, whether it is in a specified class.
2173 These macros are specific to the SPARC, and may be used only
2174 in code for printing assembler insns and in conditions for
2175 define_optimization. */
2177 /* 1 if X is an fp register. */
2179 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2181 /* Maximum number of registers that can appear in a valid memory address. */
2183 #define MAX_REGS_PER_ADDRESS 2
2185 /* Recognize any constant value that is a valid address.
2186 When PIC, we do not accept an address that would require a scratch reg
2187 to load into a register. */
2189 #define CONSTANT_ADDRESS_P(X) \
2190 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2191 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2192 || (GET_CODE (X) == CONST \
2193 && ! (flag_pic && pic_address_needs_scratch (X))))
2195 /* Define this, so that when PIC, reload won't try to reload invalid
2196 addresses which require two reload registers. */
2198 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2200 /* Nonzero if the constant value X is a legitimate general operand.
2201 Anything can be made to work except floating point constants. */
2203 #define LEGITIMATE_CONSTANT_P(X) \
2204 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
2206 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2207 and check its validity for a certain class.
2208 We have two alternate definitions for each of them.
2209 The usual definition accepts all pseudo regs; the other rejects
2210 them unless they have been allocated suitable hard regs.
2211 The symbol REG_OK_STRICT causes the latter definition to be used.
2213 Most source files want to accept pseudo regs in the hope that
2214 they will get allocated to the class that the insn wants them to be in.
2215 Source files for reload pass need to be strict.
2216 After reload, it makes no difference, since pseudo regs have
2217 been eliminated by then. */
2219 /* Optional extra constraints for this machine. Borrowed from romp.h.
2221 For the SPARC, `Q' means that this is a memory operand but not a
2222 symbolic memory operand. Note that an unassigned pseudo register
2223 is such a memory operand. Needed because reload will generate
2224 these things in insns and then not re-recognize the insns, causing
2225 constrain_operands to fail.
2227 `S' handles constraints for calls. ??? So where is it? */
2229 #ifndef REG_OK_STRICT
2231 /* Nonzero if X is a hard reg that can be used as an index
2232 or if it is a pseudo reg. */
2233 #define REG_OK_FOR_INDEX_P(X) \
2234 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2235 /* Nonzero if X is a hard reg that can be used as a base reg
2236 or if it is a pseudo reg. */
2237 #define REG_OK_FOR_BASE_P(X) \
2238 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2240 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
2242 #define EXTRA_CONSTRAINT(OP, C) \
2244 ? ((GET_CODE (OP) == MEM \
2245 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
2246 && ! symbolic_memory_operand (OP, VOIDmode)) \
2247 || (reload_in_progress && GET_CODE (OP) == REG \
2248 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
2249 : (! TARGET_ARCH64 && (C) == 'T') \
2250 ? (mem_aligned_8 (OP)) \
2251 : (! TARGET_ARCH64 && (C) == 'U') \
2252 ? (register_ok_for_ldd (OP)) \
2257 /* Nonzero if X is a hard reg that can be used as an index. */
2258 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2259 /* Nonzero if X is a hard reg that can be used as a base reg. */
2260 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2262 #define EXTRA_CONSTRAINT(OP, C) \
2264 ? (GET_CODE (OP) == REG \
2265 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
2266 && reg_renumber[REGNO (OP)] < 0) \
2267 : GET_CODE (OP) == MEM) \
2268 : (! TARGET_ARCH64 && (C) == 'T') \
2269 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2270 : (! TARGET_ARCH64 && (C) == 'U') \
2271 ? (GET_CODE (OP) == REG \
2272 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2273 || reg_renumber[REGNO (OP)] >= 0) \
2274 && register_ok_for_ldd (OP)) \
2278 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2279 that is a valid memory address for an instruction.
2280 The MODE argument is the machine mode for the MEM expression
2281 that wants to use this address.
2283 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2284 ordinarily. This changes a bit when generating PIC.
2286 If you change this, execute "rm explow.o recog.o reload.o". */
2288 #define RTX_OK_FOR_BASE_P(X) \
2289 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2290 || (GET_CODE (X) == SUBREG \
2291 && GET_CODE (SUBREG_REG (X)) == REG \
2292 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2294 #define RTX_OK_FOR_INDEX_P(X) \
2295 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2296 || (GET_CODE (X) == SUBREG \
2297 && GET_CODE (SUBREG_REG (X)) == REG \
2298 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2300 #define RTX_OK_FOR_OFFSET_P(X) \
2301 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
2303 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2304 { if (RTX_OK_FOR_BASE_P (X)) \
2306 else if (GET_CODE (X) == PLUS) \
2308 register rtx op0 = XEXP (X, 0); \
2309 register rtx op1 = XEXP (X, 1); \
2310 if (flag_pic && op0 == pic_offset_table_rtx) \
2312 if (RTX_OK_FOR_BASE_P (op1)) \
2314 else if (flag_pic == 1 \
2315 && GET_CODE (op1) != REG \
2316 && GET_CODE (op1) != LO_SUM \
2317 && GET_CODE (op1) != MEM \
2318 && (GET_CODE (op1) != CONST_INT \
2319 || SMALL_INT (op1))) \
2322 else if (RTX_OK_FOR_BASE_P (op0)) \
2324 if (RTX_OK_FOR_INDEX_P (op1) \
2325 || RTX_OK_FOR_OFFSET_P (op1)) \
2328 else if (RTX_OK_FOR_BASE_P (op1)) \
2330 if (RTX_OK_FOR_INDEX_P (op0) \
2331 || RTX_OK_FOR_OFFSET_P (op0)) \
2335 else if (GET_CODE (X) == LO_SUM) \
2337 register rtx op0 = XEXP (X, 0); \
2338 register rtx op1 = XEXP (X, 1); \
2339 if (RTX_OK_FOR_BASE_P (op0) \
2340 && CONSTANT_P (op1) \
2341 /* We can't allow TFmode, because an offset \
2342 greater than or equal to the alignment (8) \
2343 may cause the LO_SUM to overflow. */ \
2344 && MODE != TFmode) \
2347 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2351 /* Try machine-dependent ways of modifying an illegitimate address
2352 to be legitimate. If we find one, return the new, valid address.
2353 This macro is used in only one place: `memory_address' in explow.c.
2355 OLDX is the address as it was before break_out_memory_refs was called.
2356 In some cases it is useful to look at this to decide what needs to be done.
2358 MODE and WIN are passed so that this macro can use
2359 GO_IF_LEGITIMATE_ADDRESS.
2361 It is always safe for this macro to do nothing. It exists to recognize
2362 opportunities to optimize the output. */
2364 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2365 extern struct rtx_def *legitimize_pic_address ();
2366 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2367 { rtx sparc_x = (X); \
2368 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2369 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2370 force_operand (XEXP (X, 0), NULL_RTX)); \
2371 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2372 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2373 force_operand (XEXP (X, 1), NULL_RTX)); \
2374 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2375 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2377 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2378 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2379 force_operand (XEXP (X, 1), NULL_RTX)); \
2380 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2382 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2383 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2384 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2385 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2386 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2387 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2388 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2389 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2390 || GET_CODE (X) == LABEL_REF) \
2391 (X) = gen_rtx (LO_SUM, Pmode, \
2392 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2393 if (memory_address_p (MODE, X)) \
2396 /* Go to LABEL if ADDR (a legitimate address expression)
2397 has an effect that depends on the machine mode it is used for.
2398 On the SPARC this is never true. */
2400 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2402 /* If we are referencing a function make the SYMBOL_REF special.
2403 In the Medium/Anywhere code model, %g4 points to the data segment so we
2404 must not add it to function addresses. */
2406 #define ENCODE_SECTION_INFO(DECL) \
2408 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2409 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2412 /* Specify the machine mode that this machine uses
2413 for the index in the tablejump instruction. */
2414 #define CASE_VECTOR_MODE Pmode
2416 /* Define this if the tablejump instruction expects the table
2417 to contain offsets from the address of the table.
2418 Do not define this if the table should contain absolute addresses. */
2419 /* #define CASE_VECTOR_PC_RELATIVE */
2421 /* Specify the tree operation to be used to convert reals to integers. */
2422 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2424 /* This is the kind of divide that is easiest to do in the general case. */
2425 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2427 /* Define this as 1 if `char' should by default be signed; else as 0. */
2428 #define DEFAULT_SIGNED_CHAR 1
2430 /* Max number of bytes we can move from memory to memory
2431 in one reasonably fast instruction. */
2434 #if 0 /* Sun 4 has matherr, so this is no good. */
2435 /* This is the value of the error code EDOM for this machine,
2436 used by the sqrt instruction. */
2437 #define TARGET_EDOM 33
2439 /* This is how to refer to the variable errno. */
2440 #define GEN_ERRNO_RTX \
2441 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
2444 /* Define if operations between registers always perform the operation
2445 on the full register even if a narrower mode is specified. */
2446 #define WORD_REGISTER_OPERATIONS
2448 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2449 will either zero-extend or sign-extend. The value of this macro should
2450 be the code that says which one of the two operations is implicitly
2451 done, NIL if none. */
2452 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2454 /* Nonzero if access to memory by bytes is slow and undesirable.
2455 For RISC chips, it means that access to memory by bytes is no
2456 better than access by words when possible, so grab a whole word
2457 and maybe make use of that. */
2458 #define SLOW_BYTE_ACCESS 1
2460 /* We assume that the store-condition-codes instructions store 0 for false
2461 and some other value for true. This is the value stored for true. */
2463 #define STORE_FLAG_VALUE 1
2465 /* When a prototype says `char' or `short', really pass an `int'. */
2466 #define PROMOTE_PROTOTYPES
2468 /* Define this to be nonzero if shift instructions ignore all but the low-order
2470 #define SHIFT_COUNT_TRUNCATED 1
2472 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2473 is done just by pretending it is already truncated. */
2474 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2476 /* Specify the machine mode that pointers have.
2477 After generation of rtl, the compiler makes no further distinction
2478 between pointers and any other objects of this machine mode. */
2479 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2481 /* Generate calls to memcpy, memcmp and memset. */
2482 #define TARGET_MEM_FUNCTIONS
2484 /* Add any extra modes needed to represent the condition code.
2486 On the Sparc, we have a "no-overflow" mode which is used when an add or
2487 subtract insn is used to set the condition code. Different branches are
2488 used in this case for some operations.
2490 We also have two modes to indicate that the relevant condition code is
2491 in the floating-point condition code register. One for comparisons which
2492 will generate an exception if the result is unordered (CCFPEmode) and
2493 one for comparisons which will never trap (CCFPmode).
2495 CCXmode and CCX_NOOVmode are only used by v9. */
2497 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2499 /* Define the names for the modes specified above. */
2501 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2503 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2504 return the mode to be used for the comparison. For floating-point,
2505 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2506 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2507 processing is needed. */
2508 #define SELECT_CC_MODE(OP,X,Y) \
2509 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2510 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2511 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2512 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2513 ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2514 : (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2516 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2517 floating point inequality comparison. */
2519 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2521 /* A function address in a call instruction
2522 is a byte address (for indexing purposes)
2523 so give the MEM rtx a byte's mode. */
2524 #define FUNCTION_MODE SImode
2526 /* Define this if addresses of constant functions
2527 shouldn't be put through pseudo regs where they can be cse'd.
2528 Desirable on machines where ordinary constants are expensive
2529 but a CALL with constant address is cheap. */
2530 #define NO_FUNCTION_CSE
2532 /* alloca should avoid clobbering the old register save area. */
2533 #define SETJMP_VIA_SAVE_AREA
2535 /* Define subroutines to call to handle multiply and divide.
2536 Use the subroutines that Sun's library provides.
2537 The `*' prevents an underscore from being prepended by the compiler. */
2539 #define DIVSI3_LIBCALL "*.div"
2540 #define UDIVSI3_LIBCALL "*.udiv"
2541 #define MODSI3_LIBCALL "*.rem"
2542 #define UMODSI3_LIBCALL "*.urem"
2543 /* .umul is a little faster than .mul. */
2544 #define MULSI3_LIBCALL "*.umul"
2546 /* Define library calls for quad FP operations. These are all part of the
2548 #define ADDTF3_LIBCALL "_Q_add"
2549 #define SUBTF3_LIBCALL "_Q_sub"
2550 #define NEGTF2_LIBCALL "_Q_neg"
2551 #define MULTF3_LIBCALL "_Q_mul"
2552 #define DIVTF3_LIBCALL "_Q_div"
2553 #define FLOATSITF2_LIBCALL "_Q_itoq"
2554 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2555 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2556 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2557 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2558 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2559 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2560 #define EQTF2_LIBCALL "_Q_feq"
2561 #define NETF2_LIBCALL "_Q_fne"
2562 #define GTTF2_LIBCALL "_Q_fgt"
2563 #define GETF2_LIBCALL "_Q_fge"
2564 #define LTTF2_LIBCALL "_Q_flt"
2565 #define LETF2_LIBCALL "_Q_fle"
2567 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2568 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2569 and the compiler will notice and try to use the TFmode sqrt instruction
2570 for calls to the builtin function sqrt, but this fails. */
2571 #define INIT_TARGET_OPTABS \
2573 add_optab->handlers[(int) TFmode].libfunc \
2574 = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \
2575 sub_optab->handlers[(int) TFmode].libfunc \
2576 = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \
2577 neg_optab->handlers[(int) TFmode].libfunc \
2578 = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \
2579 smul_optab->handlers[(int) TFmode].libfunc \
2580 = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \
2581 flodiv_optab->handlers[(int) TFmode].libfunc \
2582 = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \
2583 eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \
2584 netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \
2585 gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \
2586 getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \
2587 lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \
2588 letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \
2589 trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \
2590 trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \
2591 extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \
2592 extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \
2593 floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \
2594 fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \
2595 fixunstfsi_libfunc \
2596 = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \
2598 sqrt_optab->handlers[(int) TFmode].libfunc \
2599 = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \
2600 INIT_SUBTARGET_OPTABS; \
2603 /* This is meant to be redefined in the host dependent files */
2604 #define INIT_SUBTARGET_OPTABS
2606 /* Compute the cost of computing a constant rtl expression RTX
2607 whose rtx-code is CODE. The body of this macro is a portion
2608 of a switch statement. If the code is computed here,
2609 return it with a return statement. Otherwise, break from the switch. */
2611 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2613 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2621 case CONST_DOUBLE: \
2622 if (GET_MODE (RTX) == DImode) \
2623 if ((XINT (RTX, 3) == 0 \
2624 && (unsigned) XINT (RTX, 2) < 0x1000) \
2625 || (XINT (RTX, 3) == -1 \
2626 && XINT (RTX, 2) < 0 \
2627 && XINT (RTX, 2) >= -0x1000)) \
2631 /* Compute the cost of an address. For the sparc, all valid addresses are
2633 ??? Is this true for v9? */
2635 #define ADDRESS_COST(RTX) 1
2637 /* Compute extra cost of moving data between one register class
2639 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2640 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2641 (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \
2642 || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2)
2644 /* Provide the costs of a rtl expression. This is in the body of a
2645 switch on CODE. The purpose for the cost of MULT is to encourage
2646 `synth_mult' to find a synthetic multiply when reasonable.
2648 If we need more than 12 insns to do a multiply, then go out-of-line,
2649 since the call overhead will be < 10% of the cost of the multiply. */
2651 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2653 return (TARGET_V8 || TARGET_SPARCLITE || TARGET_V9) \
2654 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2659 return COSTS_N_INSNS (25); \
2660 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2661 so that cse will favor the latter. */ \
2666 /* Adjust the cost of dependencies. */
2667 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2668 if (sparc_cpu == PROCESSOR_SUPERSPARC) \
2669 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2671 /* Conditional branches with empty delay slots have a length of two. */
2672 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2673 if (GET_CODE (INSN) == CALL_INSN \
2674 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2677 /* Control the assembler format that we output. */
2679 /* Output at beginning of assembler file. */
2681 #define ASM_FILE_START(file)
2683 /* Output to assembler file text saying following lines
2684 may contain character constants, extra white space, comments, etc. */
2686 #define ASM_APP_ON ""
2688 /* Output to assembler file text saying following lines
2689 no longer contain unusual constructs. */
2691 #define ASM_APP_OFF ""
2693 /* ??? Try to make the style consistent here (_OP?). */
2695 #define ASM_LONGLONG ".xword"
2696 #define ASM_LONG ".word"
2697 #define ASM_SHORT ".half"
2698 #define ASM_BYTE_OP ".byte"
2699 #define ASM_FLOAT ".single"
2700 #define ASM_DOUBLE ".double"
2701 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2703 /* Output before read-only data. */
2705 #define TEXT_SECTION_ASM_OP ".text"
2707 /* Output before writable data. */
2709 #define DATA_SECTION_ASM_OP ".data"
2711 /* How to refer to registers in assembler output.
2712 This sequence is indexed by compiler's hard-register-number (see above). */
2714 #define REGISTER_NAMES \
2715 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2716 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2717 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2718 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2719 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2720 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2721 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2722 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2723 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2724 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2725 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2726 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2727 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2729 /* Define additional names for use in asm clobbers and asm declarations. */
2731 #define ADDITIONAL_REGISTER_NAMES \
2732 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2734 /* How to renumber registers for dbx and gdb. */
2736 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2738 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
2739 since the length can run past this up to a continuation point. */
2740 #define DBX_CONTIN_LENGTH 1500
2742 /* This is how to output a note to DBX telling it the line number
2743 to which the following sequence of instructions corresponds.
2745 This is needed for SunOS 4.0, and should not hurt for 3.2
2747 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2748 { static int sym_lineno = 1; \
2749 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2750 line, sym_lineno, sym_lineno); \
2753 /* This is how to output the definition of a user-level label named NAME,
2754 such as the label on a static function or variable NAME. */
2756 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2757 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2759 /* This is how to output a command to make the user-level label named NAME
2760 defined for reference from other files. */
2762 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2763 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2765 /* This is how to output a reference to a user-level label named NAME.
2766 `assemble_name' uses this. */
2768 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2769 fprintf (FILE, "_%s", NAME)
2771 /* This is how to output a definition of an internal numbered label where
2772 PREFIX is the class of label and NUM is the number within the class. */
2774 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2775 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2777 /* This is how to output a reference to an internal numbered label where
2778 PREFIX is the class of label and NUM is the number within the class. */
2779 /* FIXME: This should be used throughout gcc, and documented in the texinfo
2780 files. There is no reason you should have to allocate a buffer and
2781 `sprintf' to reference an internal label (as opposed to defining it). */
2783 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
2784 fprintf (FILE, "%s%d", PREFIX, NUM)
2786 /* This is how to store into the string LABEL
2787 the symbol_ref name of an internal numbered label where
2788 PREFIX is the class of label and NUM is the number within the class.
2789 This is suitable for output with `assemble_name'. */
2791 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2792 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2794 /* This is how to output an assembler line defining a `double' constant. */
2796 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2799 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2800 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2801 ASM_LONG, t[0], ASM_LONG, t[1]); \
2804 /* This is how to output an assembler line defining a `float' constant. */
2806 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2809 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2810 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
2813 /* This is how to output an assembler line defining a `long double'
2816 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2819 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2820 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2821 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
2824 /* This is how to output an assembler line defining an `int' constant. */
2826 #define ASM_OUTPUT_INT(FILE,VALUE) \
2827 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2828 output_addr_const (FILE, (VALUE)), \
2829 fprintf (FILE, "\n"))
2831 /* This is how to output an assembler line defining a DImode constant. */
2832 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2833 output_double_int (FILE, VALUE)
2835 /* Likewise for `char' and `short' constants. */
2837 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2838 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2839 output_addr_const (FILE, (VALUE)), \
2840 fprintf (FILE, "\n"))
2842 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2843 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2844 output_addr_const (FILE, (VALUE)), \
2845 fprintf (FILE, "\n"))
2847 /* This is how to output an assembler line for a numeric constant byte. */
2849 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2850 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2852 /* This is how to output an element of a case-vector that is absolute. */
2854 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2857 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2858 if (Pmode == SImode) \
2859 fprintf (FILE, "\t.word\t"); \
2860 else if (TARGET_MEDLOW) \
2861 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2863 fprintf (FILE, "\t.xword\t"); \
2864 assemble_name (FILE, label); \
2865 fprintf (FILE, "\n"); \
2868 /* This is how to output an element of a case-vector that is relative.
2869 (SPARC uses such vectors only when generating PIC.) */
2871 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2874 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2875 if (Pmode == SImode) \
2876 fprintf (FILE, "\t.word\t"); \
2877 else if (TARGET_MEDLOW) \
2878 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2880 fprintf (FILE, "\t.xword\t"); \
2881 assemble_name (FILE, label); \
2882 fprintf (FILE, "-1b\n"); \
2885 /* This is how to output an assembler line
2886 that says to advance the location counter
2887 to a multiple of 2**LOG bytes. */
2889 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2891 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2893 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2894 fprintf (FILE, "\t.skip %u\n", (SIZE))
2896 /* This says how to output an assembler line
2897 to define a global common symbol. */
2899 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2900 ( fputs ("\t.common ", (FILE)), \
2901 assemble_name ((FILE), (NAME)), \
2902 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2904 /* This says how to output an assembler line to define a local common
2907 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2908 ( fputs ("\t.reserve ", (FILE)), \
2909 assemble_name ((FILE), (NAME)), \
2910 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2911 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2913 /* Store in OUTPUT a string (made with alloca) containing
2914 an assembler-name for a local static variable named NAME.
2915 LABELNO is an integer which is different for each call. */
2917 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2918 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2919 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2921 #define IDENT_ASM_OP ".ident"
2923 /* Output #ident as a .ident. */
2925 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2926 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
2928 /* Define the parentheses used to group arithmetic operations
2929 in assembler code. */
2931 #define ASM_OPEN_PAREN "("
2932 #define ASM_CLOSE_PAREN ")"
2934 /* Define results of standard character escape sequences. */
2935 #define TARGET_BELL 007
2936 #define TARGET_BS 010
2937 #define TARGET_TAB 011
2938 #define TARGET_NEWLINE 012
2939 #define TARGET_VT 013
2940 #define TARGET_FF 014
2941 #define TARGET_CR 015
2943 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2944 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
2946 /* Print operand X (an rtx) in assembler syntax to file FILE.
2947 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2948 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2950 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2952 /* Print a memory address as an operand to reference that memory location. */
2954 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2955 { register rtx base, index = 0; \
2957 register rtx addr = ADDR; \
2958 if (GET_CODE (addr) == REG) \
2959 fputs (reg_names[REGNO (addr)], FILE); \
2960 else if (GET_CODE (addr) == PLUS) \
2962 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2963 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2964 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2965 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2967 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2968 fputs (reg_names[REGNO (base)], FILE); \
2970 fprintf (FILE, "%+d", offset); \
2971 else if (GET_CODE (index) == REG) \
2972 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2973 else if (GET_CODE (index) == SYMBOL_REF \
2974 || GET_CODE (index) == CONST) \
2975 fputc ('+', FILE), output_addr_const (FILE, index); \
2978 else if (GET_CODE (addr) == MINUS \
2979 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2981 output_addr_const (FILE, XEXP (addr, 0)); \
2982 fputs ("-(", FILE); \
2983 output_addr_const (FILE, XEXP (addr, 1)); \
2984 fputs ("-.)", FILE); \
2986 else if (GET_CODE (addr) == LO_SUM) \
2988 output_operand (XEXP (addr, 0), 0); \
2989 fputs ("+%lo(", FILE); \
2990 output_address (XEXP (addr, 1)); \
2991 fputc (')', FILE); \
2993 else if (flag_pic && GET_CODE (addr) == CONST \
2994 && GET_CODE (XEXP (addr, 0)) == MINUS \
2995 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2996 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2997 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2999 addr = XEXP (addr, 0); \
3000 output_addr_const (FILE, XEXP (addr, 0)); \
3001 /* Group the args of the second CONST in parenthesis. */ \
3002 fputs ("-(", FILE); \
3003 /* Skip past the second CONST--it does nothing for us. */\
3004 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3005 /* Close the parenthesis. */ \
3006 fputc (')', FILE); \
3010 output_addr_const (FILE, addr); \
3014 /* Declare functions defined in sparc.c and used in templates. */
3016 extern char *singlemove_string ();
3017 extern char *output_move_double ();
3018 extern char *output_move_quad ();
3019 extern char *output_fp_move_double ();
3020 extern char *output_fp_move_quad ();
3021 extern char *output_block_move ();
3022 extern char *output_scc_insn ();
3023 extern char *output_cbranch ();
3024 extern char *output_v9branch ();
3025 extern char *output_return ();
3027 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3029 extern int flag_pic;
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