1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 94, 95, 96, 1997 Free Software Foundation,
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 many of the definitions that relate to assembler syntax. */
28 /* Sparc64 support has been added by trying to allow for a day when one
29 compiler can handle both v8 and v9. There are a few cases where this
30 isn't doable, but keep them to a minimum!
32 TARGET_V9 is used to select at runtime the sparc64 chip.
33 TARGET_ARCH64 is used to select at runtime a 64 bit environment.
34 SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside
35 #define's), and says whether the cpu is a sparc64 chip (which may be
36 running in a 32 or 64 bit environment).
37 SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit
40 In places where it is possible to choose at runtime, use TARGET_V9 and
41 TARGET_ARCH64. In places where it is currently not possible to select
42 between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of
43 SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8
44 and v9 in the v9 compiler.
46 ??? All uses of SPARC_V9 have been removed. Try not to add new ones.
53 #define SPARC_ARCH64 0
56 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */
57 #define TARGET_CPU_sparc 0
58 #define TARGET_CPU_v7 0 /* alias for previous */
59 #define TARGET_CPU_sparclet 1
60 #define TARGET_CPU_sparclite 2
61 #define TARGET_CPU_v8 3
62 #define TARGET_CPU_supersparc 4
63 #define TARGET_CPU_ultrasparc 5
64 #define TARGET_CPU_sparc64 5 /* alias for ultrasparc */
66 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc || TARGET_CPU_DEFAULT == TARGET_CPU_v8 || TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
67 #define CPP_DEFAULT_SPEC ""
68 #define ASM_DEFAULT_SPEC ""
70 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
71 #define CPP_DEFAULT_SPEC "-D__sparclet__"
72 #define ASM_DEFAULT_SPEC "-Asparclet"
74 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
75 #define CPP_DEFAULT_SPEC "-D__sparclite__"
76 #define ASM_DEFAULT_SPEC "-Asparclite"
78 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
79 /* ??? What does Sun's CC pass? */
80 #define CPP_DEFAULT_SPEC "-D__sparc_v9__"
81 /* ??? It's not clear how other assemblers will handle this, so by default
82 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
83 is handled in sol2.h. */
84 #define ASM_DEFAULT_SPEC "-Av9"
86 Unrecognized value in TARGET_CPU_DEFAULT.
92 /* Names to predefine in the preprocessor for this target machine. */
94 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
95 the right varags.h file when bootstrapping. */
96 /* ??? It's not clear what value we want to use for -Acpu/machine for
97 sparc64 in 32 bit environments, so for now we only use `sparc64' in
98 64 bit environments. */
99 /* ??? __arch64__ is subject to change. */
102 #define CPP_PREDEFINES \
103 "-Dsparc -Dsun -Dunix -D__arch64__ \
104 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
106 #define CPP_PREDEFINES \
107 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
108 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
111 /* Define macros to distinguish architectures. */
115 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
116 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
119 #define CPP_SPEC "%(cpp_cpu)"
122 /* Common CPP definitions used by CPP_SPEC amongst the various targets
123 for handling -mcpu=xxx switches. */
124 /* ??? v8plus/v9/ultrasparc handling is tentative */
125 #define CPP_CPU_SPEC "\
127 %{msparclite:-D__sparclite__} \
128 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
129 %{mv8:-D__sparc_v8__} \
130 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
131 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
132 %{mcpu=sparclite:-D__sparclite__} \
133 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
134 %{mcpu=v8:-D__sparc_v8__} \
135 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
136 %{mcpu=v8plus:-D__sparc_v9__} \
137 %{mcpu=v9:-D__sparc_v9__} \
138 %{mcpu=ultrasparc:-D__sparc_v9__} \
139 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \
142 /* Prevent error on `-sun4' and `-target sun4' options. */
143 /* This used to translate -dalign to -malign, but that is no good
144 because it can't turn off the usual meaning of making debugging dumps. */
145 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
146 ??? Delete support for -m<cpu> for 2.9. */
149 %{sun4:} %{target:} \
150 %{mcypress:-mcpu=cypress} \
151 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
152 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
155 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
157 /* Provide required defaults for linker -e and -d switches. */
160 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
161 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
163 /* Special flags to the Sun-4 assembler when using pipe for input. */
166 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
170 /* Override in target specific files. */
171 #define ASM_CPU_SPEC "\
172 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
173 %{msparclite:-Asparclite} \
174 %{mf930:-Asparclite} %{mf934:-Asparclite} \
175 %{mcpu=sparclite:-Asparclite} \
176 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
177 %{mcpu=v8plus:-Av9} \
179 %{mcpu=ultrasparc:-Av9} \
180 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \
183 /* This macro defines names of additional specifications to put in the specs
184 that can be used in various specifications like CC1_SPEC. Its definition
185 is an initializer with a subgrouping for each command option.
187 Each subgrouping contains a string constant, that defines the
188 specification name, and a string constant that used by the GNU CC driver
191 Do not define this macro if it does not need to do anything. */
193 #define EXTRA_SPECS \
194 { "cpp_cpu", CPP_CPU_SPEC }, \
195 { "cpp_default", CPP_DEFAULT_SPEC }, \
196 { "asm_cpu", ASM_CPU_SPEC }, \
197 { "asm_default", ASM_DEFAULT_SPEC }, \
198 SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
203 #define PTRDIFF_TYPE "long long int"
204 #define SIZE_TYPE "long long unsigned int"
206 #define PTRDIFF_TYPE "int"
207 /* The default value for SIZE_TYPE is "unsigned int" which is what we want. */
210 /* ??? This should be 32 bits for v9 but what can we do? */
211 #define WCHAR_TYPE "short unsigned int"
212 #define WCHAR_TYPE_SIZE 16
213 #define MAX_WCHAR_TYPE_SIZE 16
215 /* Show we can debug even without a frame pointer. */
216 #define CAN_DEBUG_WITHOUT_FP
218 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
219 code into the rtl. Also, if we are profiling, we cannot eliminate
220 the frame pointer (because the return address will get smashed). */
222 void sparc_override_options ();
224 #define OVERRIDE_OPTIONS \
226 if (profile_flag || profile_block_flag || profile_arc_flag) \
230 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
231 warning ("%s and profiling conflict: disabling %s", \
232 pic_string, pic_string); \
235 flag_omit_frame_pointer = 0; \
237 sparc_override_options (); \
238 SUBTARGET_OVERRIDE_OPTIONS; \
241 /* This is meant to be redefined in the host dependent files. */
242 #define SUBTARGET_OVERRIDE_OPTIONS
244 /* These compiler options take an argument. We ignore -target for now. */
246 #define WORD_SWITCH_TAKES_ARG(STR) \
247 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
248 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
250 /* Print subsidiary information on the compiler version in use. */
252 #define TARGET_VERSION fprintf (stderr, " (sparc)");
254 /* Generate DBX debugging information. */
256 #define DBX_DEBUGGING_INFO
258 /* Run-time compilation parameters selecting different hardware subsets. */
260 extern int target_flags;
262 /* Nonzero if we should generate code to use the fpu. */
264 #define TARGET_FPU (target_flags & MASK_FPU)
266 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
267 use fast return insns, but lose some generality. */
268 #define MASK_EPILOGUE 2
269 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
271 /* Nonzero if we should assume that double pointers might be unaligned.
272 This can happen when linking gcc compiled code with other compilers,
273 because the ABI only guarantees 4 byte alignment. */
274 #define MASK_UNALIGNED_DOUBLES 4
275 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
277 /* Nonzero means that we should generate code for a v8 sparc. */
279 #define TARGET_V8 (target_flags & MASK_V8)
281 /* Nonzero means that we should generate code for a sparclite.
282 This enables the sparclite specific instructions, but does not affect
283 whether FPU instructions are emitted. */
284 #define MASK_SPARCLITE 0x10
285 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
287 /* Nonzero if we're compiling for the sparclet. */
288 #define MASK_SPARCLET 0x20
289 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
291 /* Nonzero if we're compiling for v9 sparc.
292 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
293 the word size is 64. */
295 #define TARGET_V9 (target_flags & MASK_V9)
297 /* Non-zero to generate code that uses the instructions deprecated in
298 the v9 architecture. This option only applies to v9 systems. */
299 /* ??? This isn't user selectable yet. It's used to enable such insns
300 on 32 bit v9 systems and for the moment they're permanently disabled
301 on 64 bit v9 systems. */
302 #define MASK_DEPRECATED_V8_INSNS 0x80
303 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
305 /* Mask of all CPU selection flags. */
307 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
309 /* Non-zero means don't pass `-assert pure-text' to the linker. */
310 #define MASK_IMPURE_TEXT 0x100
311 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
313 /* Nonzero means that we should generate code using a flat register window
314 model, i.e. no save/restore instructions are generated, which is
315 compatible with normal sparc code.
316 The frame pointer is %i7 instead of %fp. */
317 #define MASK_FLAT 0x200
318 #define TARGET_FLAT (target_flags & MASK_FLAT)
320 /* Nonzero means use the registers that the Sparc ABI reserves for
321 application software. This must be the default to coincide with the
322 setting in FIXED_REGISTERS. */
323 #define MASK_APP_REGS 0x400
324 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
326 /* Option to select how quad word floating point is implemented.
327 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
328 Otherwise, we use the SPARC ABI quad library functions. */
329 #define MASK_HARD_QUAD 0x800
330 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
332 /* Non-zero on little-endian machines. */
333 /* ??? Little endian support currently only exists for sparclet-aout and
334 sparc64-elf configurations. May eventually want to expand the support
335 to all targets, but for now it's kept local to only those two. */
336 #define MASK_LITTLE_ENDIAN 0x1000
337 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
339 /* Nonzero if ints are 64 bits.
340 This automatically implies longs are 64 bits too.
341 This option is for v9 only. */
342 #define MASK_INT64 0x2000
343 #define TARGET_INT64 (target_flags & MASK_INT64)
345 /* Nonzero if longs are 64 bits.
346 This option is for v9 only. */
347 #define MASK_LONG64 0x4000
348 #define TARGET_LONG64 (target_flags & MASK_LONG64)
350 /* Nonzero if pointers are 64 bits.
351 This is not a user selectable option, though it may be one day -
352 so it is used to determine pointer size instead of an architecture flag. */
353 #define MASK_PTR64 0x8000
354 #define TARGET_PTR64 (target_flags & MASK_PTR64)
356 /* Nonzero if generating code to run in a 64 bit environment. */
357 #define MASK_ARCH64 0x10000
358 #define TARGET_ARCH64 (target_flags & MASK_ARCH64)
359 #define TARGET_ARCH32 (! TARGET_ARCH64)
361 /* SPARC64 memory models.
362 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0,
363 avoid generating %uhi and %ulo terms.
364 (pointers can be 32 or 64 bits)
365 TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but
366 can be loaded anywhere (use %g4 as offset).
367 TARGET_FULLANY: 64 bit address space, no restrictions.
368 This option is not fully supported yet.
369 These options are for v9 only. All mask values are nonzero so the v8
370 compiler can assume this stuff won't interfere. */
371 #define MASK_MEDLOW 0x20000
372 #define MASK_MEDANY 0x40000
373 #define MASK_FULLANY 0x60000
374 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
375 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
376 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
377 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
379 /* ??? There are hardcoded references to this reg in the .md file. */
380 #define MEDANY_BASE_REG "%g4"
382 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
383 adding 2047 to %sp. This option is for v9 only and is the default. */
384 #define MASK_STACK_BIAS 0x80000
385 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
387 /* Non-zero means %g0 is a normal register.
388 We still clobber it as necessary, but we can't rely on it always having
390 We don't bother to support this in true 64 bit mode. */
391 #define MASK_LIVE_G0 0x100000
392 #define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
394 /* Non-zero means the cpu has broken `save' and `restore' insns, only
395 the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
396 We assume the environment will properly handle or otherwise avoid
397 trouble associated with an interrupt occuring after the `save' or trap
398 occuring during it. */
399 #define MASK_BROKEN_SAVERESTORE 0x200000
400 #define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
402 /* Non-zero means -m{,no-}fpu was passed on the command line. */
403 #define MASK_FPU_SET 0x400000
404 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
406 /* Macro to define tables used to set the flags.
407 This is a list in braces of pairs in braces,
408 each pair being { "NAME", VALUE }
409 where VALUE is the bits to set or minus the bits to clear.
410 An empty string NAME is used to identify the default VALUE. */
412 #define TARGET_SWITCHES \
413 { {"fpu", MASK_FPU | MASK_FPU_SET}, \
414 {"no-fpu", -MASK_FPU}, \
415 {"no-fpu", MASK_FPU_SET}, \
416 {"hard-float", MASK_FPU | MASK_FPU_SET}, \
417 {"soft-float", -MASK_FPU}, \
418 {"soft-float", MASK_FPU_SET}, \
419 {"epilogue", MASK_EPILOGUE}, \
420 {"no-epilogue", -MASK_EPILOGUE}, \
421 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
422 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
423 {"impure-text", MASK_IMPURE_TEXT}, \
424 {"no-impure-text", -MASK_IMPURE_TEXT}, \
425 {"flat", MASK_FLAT}, \
426 {"no-flat", -MASK_FLAT}, \
427 {"app-regs", MASK_APP_REGS}, \
428 {"no-app-regs", -MASK_APP_REGS}, \
429 {"hard-quad-float", MASK_HARD_QUAD}, \
430 {"soft-quad-float", -MASK_HARD_QUAD}, \
431 /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \
440 { "", TARGET_DEFAULT}}
442 /* MASK_APP_REGS must always be the default because that's what
443 FIXED_REGISTERS is set to and -ffixed- is processed before
444 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
445 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
447 /* This is meant to be redefined in target specific files. */
448 #define SUBTARGET_SWITCHES
450 /* ??? Until we support a combination 32/64 bit compiler, these options
451 are only defined for the v9 compiler in a true 64 bit environment. */
453 #define ARCH64_SWITCHES \
454 /* {"arch32", -MASK_ARCH64}, */ \
455 /* {"arch64", MASK_ARCH64}, */ \
456 {"int64", MASK_INT64+MASK_LONG64}, \
457 {"int32", -MASK_INT64}, \
458 {"int32", MASK_LONG64}, \
459 {"long64", -MASK_INT64}, \
460 {"long64", MASK_LONG64}, \
461 {"long32", -(MASK_INT64+MASK_LONG64)}, \
462 /* {"ptr64", MASK_PTR64}, */ \
463 /* {"ptr32", -MASK_PTR64}, */ \
464 {"stack-bias", MASK_STACK_BIAS}, \
465 {"no-stack-bias", -MASK_STACK_BIAS}, \
466 {"medlow", -MASK_CODE_MODEL}, \
467 {"medlow", MASK_MEDLOW}, \
468 {"medany", -MASK_CODE_MODEL}, \
469 {"medany", MASK_MEDANY}, \
470 {"fullany", -MASK_CODE_MODEL}, \
471 {"fullany", MASK_FULLANY},
473 #define ARCH64_SWITCHES
477 These must match the values for the cpu attribute in sparc.md. */
478 enum processor_type {
482 PROCESSOR_SUPERSPARC,
493 /* This is set from -m{cpu,tune}=xxx. */
494 extern enum processor_type sparc_cpu;
496 /* Recast the cpu class to be the cpu attribute.
497 Every file includes us, but not every file includes insn-attr.h. */
498 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
500 /* This macro is similar to `TARGET_SWITCHES' but defines names of
501 command options that have values. Its definition is an
502 initializer with a subgrouping for each command option.
504 Each subgrouping contains a string constant, that defines the
505 fixed part of the option name, and the address of a variable.
506 The variable, type `char *', is set to the variable part of the
507 given option if the fixed part matches. The actual option name
508 is made by appending `-m' to the specified name.
510 Here is an example which defines `-mshort-data-NUMBER'. If the
511 given option is `-mshort-data-512', the variable `m88k_short_data'
512 will be set to the string `"512"'.
514 extern char *m88k_short_data;
515 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
517 #define TARGET_OPTIONS \
519 {"cpu=", &sparc_select[1].string}, \
520 {"tune=", &sparc_select[2].string}, \
524 /* This is meant to be redefined in target specific files. */
525 #define SUBTARGET_OPTIONS
527 /* sparc_select[0] is reserved for the default cpu. */
528 struct sparc_cpu_select
536 extern struct sparc_cpu_select sparc_select[];
538 /* target machine storage layout */
540 /* Define for cross-compilation to a sparc target with no TFmode from a host
541 with a different float format (e.g. VAX). */
542 #define REAL_ARITHMETIC
544 /* Define this if most significant bit is lowest numbered
545 in instructions that operate on numbered bit-fields. */
546 #define BITS_BIG_ENDIAN 1
548 /* Define this if most significant byte of a word is the lowest numbered. */
549 #define BYTES_BIG_ENDIAN 1
551 /* Define this if most significant word of a multiword number is the lowest
553 #define WORDS_BIG_ENDIAN 1
555 /* Define this to set the endianness to use in libgcc2.c, which can
556 not depend on target_flags. */
557 #if defined (__LITTLE_ENDIAN__)
558 #define LIBGCC2_WORDS_BIG_ENDIAN 0
560 #define LIBGCC2_WORDS_BIG_ENDIAN 1
563 /* number of bits in an addressable storage unit */
564 #define BITS_PER_UNIT 8
566 /* Width in bits of a "word", which is the contents of a machine register.
567 Note that this is not necessarily the width of data type `int';
568 if using 16-bit ints on a 68000, this would still be 32.
569 But on a machine with 16-bit registers, this would be 16. */
570 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
571 #define MAX_BITS_PER_WORD 64
573 /* Width of a word, in units (bytes). */
574 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
575 #define MIN_UNITS_PER_WORD 4
577 /* Now define the sizes of the C data types. */
579 #define SHORT_TYPE_SIZE 16
580 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
581 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
582 #define LONG_LONG_TYPE_SIZE 64
583 #define FLOAT_TYPE_SIZE 32
584 #define DOUBLE_TYPE_SIZE 64
586 #define MAX_INT_TYPE_SIZE 64
587 #define MAX_LONG_TYPE_SIZE 64
590 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
591 Instead, it is enabled in sol2.h, because it does work under Solaris. */
592 /* Define for support of TFmode long double and REAL_ARITHMETIC.
593 Sparc ABI says that long double is 4 words. */
594 #define LONG_DOUBLE_TYPE_SIZE 128
597 /* Width in bits of a pointer.
598 See also the macro `Pmode' defined below. */
599 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
601 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
602 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
604 /* Boundary (in *bits*) on which stack pointer should be aligned. */
605 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
607 /* ALIGN FRAMES on double word boundaries */
609 #define SPARC_STACK_ALIGN(LOC) \
610 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
612 /* Allocation boundary (in *bits*) for the code of a function. */
613 #define FUNCTION_BOUNDARY 32
615 /* Alignment of field after `int : 0' in a structure. */
616 /* ??? Should this be based on TARGET_INT64? */
617 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
619 /* Every structure's size must be a multiple of this. */
620 #define STRUCTURE_SIZE_BOUNDARY 8
622 /* A bitfield declared as `int' forces `int' alignment for the struct. */
623 #define PCC_BITFIELD_TYPE_MATTERS 1
625 /* No data type wants to be aligned rounder than this. */
626 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
628 /* The best alignment to use in cases where we have a choice. */
629 #define FASTEST_ALIGNMENT 64
631 /* Make strings word-aligned so strcpy from constants will be faster. */
632 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
633 ((TREE_CODE (EXP) == STRING_CST \
634 && (ALIGN) < FASTEST_ALIGNMENT) \
635 ? FASTEST_ALIGNMENT : (ALIGN))
637 /* Make arrays of chars word-aligned for the same reasons. */
638 #define DATA_ALIGNMENT(TYPE, ALIGN) \
639 (TREE_CODE (TYPE) == ARRAY_TYPE \
640 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
641 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
643 /* Set this nonzero if move instructions will actually fail to work
644 when given unaligned data. */
645 #define STRICT_ALIGNMENT 1
647 /* Things that must be doubleword aligned cannot go in the text section,
648 because the linker fails to align the text section enough!
649 Put them in the data section. This macro is only used in this file. */
650 #define MAX_TEXT_ALIGN 32
652 /* This forces all variables and constants to the data section when PIC.
653 This is because the SunOS 4 shared library scheme thinks everything in
654 text is a function, and patches the address to point to a loader stub. */
655 /* This is defined to zero for every system which doesn't use the a.out object
657 #ifndef SUNOS4_SHARED_LIBRARIES
658 #define SUNOS4_SHARED_LIBRARIES 0
661 /* This is defined differently for v9 in a cover file. */
662 #define SELECT_SECTION(T,RELOC) \
664 if (TREE_CODE (T) == VAR_DECL) \
666 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
667 && DECL_INITIAL (T) \
668 && (DECL_INITIAL (T) == error_mark_node \
669 || TREE_CONSTANT (DECL_INITIAL (T))) \
670 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
671 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
676 else if (TREE_CODE (T) == CONSTRUCTOR) \
678 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
681 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
683 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
684 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
685 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
692 /* Use text section for a constant
693 unless we need more alignment than that offers. */
694 /* This is defined differently for v9 in a cover file. */
695 #define SELECT_RTX_SECTION(MODE, X) \
697 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
698 && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \
704 /* Standard register usage. */
706 /* Number of actual hardware registers.
707 The hardware registers are assigned numbers for the compiler
708 from 0 to just below FIRST_PSEUDO_REGISTER.
709 All registers that the compiler knows about must be given numbers,
710 even those that are not normally considered general registers.
712 SPARC has 32 integer registers and 32 floating point registers.
713 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
714 accessible. We still account for them to simplify register computations
715 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
717 Register 100 is used as the integer condition code register. */
719 #define FIRST_PSEUDO_REGISTER 101
721 /* Additional V9 fp regs. */
722 #define SPARC_FIRST_V9_FP_REG 64
723 #define SPARC_LAST_V9_FP_REG 95
724 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
725 #define SPARC_FIRST_V9_FCC_REG 96
726 #define SPARC_LAST_V9_FCC_REG 99
728 #define SPARC_FCC_REG 96
729 /* Integer CC reg. We don't distinguish %icc from %xcc. */
730 #define SPARC_ICC_REG 100
732 /* 1 for registers that have pervasive standard uses
733 and are not available for the register allocator.
735 g1 is free to use as temporary.
736 g2-g4 are reserved for applications. Gcc normally uses them as
737 temporaries, but this can be disabled via the -mno-app-regs option.
738 g5 through g7 are reserved for the operating system.
740 g1 and g5 are free to use as temporaries.
741 g2-g4 are reserved for applications. Gcc normally uses them as
742 temporaries, but this can be disabled via the -mno-app-regs option.
743 g6-g7 are reserved for the operating system.
744 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
745 currently be a fixed register until this pattern is rewritten.
746 Register 1 is also used when restoring call-preserved registers in large
749 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
750 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
753 #define FIXED_REGISTERS \
754 {1, 0, 0, 0, 0, 0, 1, 1, \
755 0, 0, 0, 0, 0, 0, 1, 0, \
756 0, 0, 0, 0, 0, 0, 0, 0, \
757 0, 0, 0, 0, 0, 0, 1, 1, \
759 0, 0, 0, 0, 0, 0, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 0, 0, 0, 0, 0, 0, 0, 0, \
762 0, 0, 0, 0, 0, 0, 0, 0, \
764 0, 0, 0, 0, 0, 0, 0, 0, \
765 0, 0, 0, 0, 0, 0, 0, 0, \
766 0, 0, 0, 0, 0, 0, 0, 0, \
767 0, 0, 0, 0, 0, 0, 0, 0, \
771 /* 1 for registers not available across function calls.
772 These must include the FIXED_REGISTERS and also any
773 registers that can be used without being saved.
774 The latter must include the registers where values are returned
775 and the register where structure-value addresses are passed.
776 Aside from that, you can include as many other registers as you like. */
778 #define CALL_USED_REGISTERS \
779 {1, 1, 1, 1, 1, 1, 1, 1, \
780 1, 1, 1, 1, 1, 1, 1, 1, \
781 0, 0, 0, 0, 0, 0, 0, 0, \
782 0, 0, 0, 0, 0, 0, 1, 1, \
784 1, 1, 1, 1, 1, 1, 1, 1, \
785 1, 1, 1, 1, 1, 1, 1, 1, \
786 1, 1, 1, 1, 1, 1, 1, 1, \
787 1, 1, 1, 1, 1, 1, 1, 1, \
789 1, 1, 1, 1, 1, 1, 1, 1, \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791 1, 1, 1, 1, 1, 1, 1, 1, \
792 1, 1, 1, 1, 1, 1, 1, 1, \
796 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
797 they won't be allocated. */
799 #define CONDITIONAL_REGISTER_USAGE \
802 if (! SPARC_ARCH64) \
810 /* ??? We need to scan argv for -fcall-used-. */ \
811 for (regno = 48; regno < 80; regno++) \
812 call_used_regs[regno] = 0; \
817 for (regno = SPARC_FIRST_V9_FP_REG; \
818 regno <= SPARC_LAST_V9_FP_REG; \
820 fixed_regs[regno] = 1; \
821 /* %fcc0 is used by v8 and v9. */ \
822 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
823 regno <= SPARC_LAST_V9_FCC_REG; \
825 fixed_regs[regno] = 1; \
830 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
831 fixed_regs[regno] = 1; \
833 /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
834 fixed_regs[2] |= ! TARGET_APP_REGS; \
835 fixed_regs[3] |= ! TARGET_APP_REGS; \
836 fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
839 /* Let the compiler believe the frame pointer is still \
840 %fp, but output it as %i7. */ \
841 fixed_regs[31] = 1; \
842 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
843 /* ??? This is a hack to disable leaf functions. */ \
844 global_regs[7] = 1; \
846 if (profile_block_flag) \
848 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
856 /* Return number of consecutive hard regs needed starting at reg REGNO
857 to hold something of mode MODE.
858 This is ordinarily the length in words of a value of mode MODE
859 but can be less for certain modes in special long registers.
861 On SPARC, ordinary registers hold 32 bits worth;
862 this means both integer and floating point registers.
863 On v9, integer regs hold 64 bits worth; floating point regs hold
864 32 bits worth (this includes the new fp regs as even the odd ones are
865 included in the hard register count). */
867 #define HARD_REGNO_NREGS(REGNO, MODE) \
870 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
871 : (GET_MODE_SIZE (MODE) + 3) / 4) \
872 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
874 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
875 See sparc.c for how we initialize this. */
876 extern int *hard_regno_mode_classes;
877 extern int sparc_mode_class[];
878 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
879 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
881 /* Value is 1 if it is a good idea to tie two pseudo registers
882 when one has mode MODE1 and one has mode MODE2.
883 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
884 for any hard reg, then this must be 0 for correct output.
886 For V9: SFmode can't be combined with other float modes, because they can't
887 be allocated to the %d registers. Also, DFmode won't fit in odd %f
888 registers, but SFmode will. */
889 #define MODES_TIEABLE_P(MODE1, MODE2) \
890 ((MODE1) == (MODE2) \
891 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
893 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
894 || (MODE1 != SFmode && MODE2 != SFmode)))))
896 /* Specify the registers used for certain standard purposes.
897 The values of these macros are register numbers. */
899 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
900 /* #define PC_REGNUM */
902 /* Register to use for pushing function arguments. */
903 #define STACK_POINTER_REGNUM 14
905 /* Actual top-of-stack address is 92/136 greater than the contents of the
906 stack pointer register for !v9/v9. That is:
907 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
908 address, and 24 bytes for the 6 register parameters.
909 - v9: 128 bytes for the in and local registers + 8 bytes reserved. */
910 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
912 /* The stack bias (amount by which the hardware register is offset by). */
913 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
915 /* Base register for access to local variables of the function. */
916 #define FRAME_POINTER_REGNUM 30
919 /* Register that is used for the return address for the flat model. */
920 #define RETURN_ADDR_REGNUM 15
923 /* Value should be nonzero if functions must have frame pointers.
924 Zero means the frame pointer need not be set up (and parms
925 may be accessed via the stack pointer) in functions that seem suitable.
926 This is computed in `reload', in reload1.c.
927 Used in flow.c, global.c, and reload1.c.
929 Being a non-leaf function does not mean a frame pointer is needed in the
930 flat window model. However, the debugger won't be able to backtrace through
932 #define FRAME_POINTER_REQUIRED \
933 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
934 || !leaf_function_p ()) \
935 : ! (leaf_function_p () && only_leaf_regs_used ()))
937 /* C statement to store the difference between the frame pointer
938 and the stack pointer values immediately after the function prologue.
940 Note, we always pretend that this is a leaf function because if
941 it's not, there's no point in trying to eliminate the
942 frame pointer. If it is a leaf function, we guessed right! */
943 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
944 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
945 : compute_frame_size (get_frame_size (), 1)))
947 /* Base register for access to arguments of the function. */
948 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
950 /* Register in which static-chain is passed to a function. This must
951 not be a register used by the prologue. */
952 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
954 /* Register which holds offset table for position-independent
957 #define PIC_OFFSET_TABLE_REGNUM 23
959 #define INITIALIZE_PIC initialize_pic ()
960 #define FINALIZE_PIC finalize_pic ()
962 /* Sparc ABI says that quad-precision floats and all structures are returned
964 For v9, all aggregates are returned in memory. */
965 #define RETURN_IN_MEMORY(TYPE) \
966 (TYPE_MODE (TYPE) == BLKmode \
967 || (! TARGET_ARCH64 && (TYPE_MODE (TYPE) == TFmode \
968 || TYPE_MODE (TYPE) == TCmode)))
970 /* Functions which return large structures get the address
971 to place the wanted value at offset 64 from the frame.
972 Must reserve 64 bytes for the in and local registers.
973 v9: Functions which return large structures get the address to place the
974 wanted value from an invisible first argument. */
975 /* Used only in other #defines in this file. */
976 #define STRUCT_VALUE_OFFSET 64
978 #define STRUCT_VALUE \
981 : gen_rtx (MEM, Pmode, \
982 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
983 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
984 #define STRUCT_VALUE_INCOMING \
987 : gen_rtx (MEM, Pmode, \
988 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
989 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
991 /* Define the classes of registers for register constraints in the
992 machine description. Also define ranges of constants.
994 One of the classes must always be named ALL_REGS and include all hard regs.
995 If there is more than one class, another class must be named NO_REGS
996 and contain no registers.
998 The name GENERAL_REGS must be the name of a class (or an alias for
999 another name such as ALL_REGS). This is the class of registers
1000 that is allowed by "g" or "r" in a register constraint.
1001 Also, registers outside this class are allocated only when
1002 instructions express preferences for them.
1004 The classes must be numbered in nondecreasing order; that is,
1005 a larger-numbered class must never be contained completely
1006 in a smaller-numbered class.
1008 For any two classes, it is very desirable that there be another
1009 class that represents their union. */
1011 /* The SPARC has two kinds of registers, general and floating point.
1013 For v9 we must distinguish between the upper and lower floating point
1014 registers because the upper ones can't hold SFmode values.
1015 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1016 satisfying a group need for a class will also satisfy a single need for
1017 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1020 It is important that one class contains all the general and all the standard
1021 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1022 because reg_class_record() will bias the selection in favor of fp regs,
1023 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1024 because FP_REGS > GENERAL_REGS.
1026 It is also important that one class contain all the general and all the
1027 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1028 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1029 allocate_reload_reg() to bypass it causing an abort because the compiler
1030 thinks it doesn't have a spill reg when in fact it does.
1032 v9 also has 4 floating point condition code registers. Since we don't
1033 have a class that is the union of FPCC_REGS with either of the others,
1034 it is important that it appear first. Otherwise the compiler will die
1035 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1038 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1039 may try to use it to hold an SImode value. See register_operand.
1040 ??? Should %fcc[0123] be handled similarily?
1043 enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
1044 GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1045 ALL_REGS, LIM_REG_CLASSES };
1047 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1049 /* Give names of register classes as strings for dump file. */
1051 #define REG_CLASS_NAMES \
1052 { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \
1053 "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" }
1055 /* Define which registers fit in which classes.
1056 This is an initializer for a vector of HARD_REG_SET
1057 of length N_REG_CLASSES. */
1059 #define REG_CLASS_CONTENTS \
1060 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, \
1061 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1062 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1064 /* The same information, inverted:
1065 Return the class number of the smallest class containing
1066 reg number REGNO. This could be a conditional expression
1067 or could index an array. */
1069 extern enum reg_class sparc_regno_reg_class[];
1071 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1073 /* This is the order in which to allocate registers normally.
1075 We put %f0/%f1 last among the float registers, so as to make it more
1076 likely that a pseudo-register which dies in the float return register
1077 will get allocated to the float return register, thus saving a move
1078 instruction at the end of the function.
1080 The float registers are ordered a little "funny" because in the 64 bit
1081 architecture, some of them (%f16-%f47) are call-preserved. */
1083 #define REG_ALLOC_ORDER \
1084 { 8, 9, 10, 11, 12, 13, 2, 3, \
1085 15, 16, 17, 18, 19, 20, 21, 22, \
1086 23, 24, 25, 26, 27, 28, 29, 31, \
1087 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1088 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1089 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1090 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1091 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1092 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1093 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1094 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1095 32, 33, /* %f0,%f1 */ \
1096 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1097 1, 4, 5, 6, 7, 0, 14, 30}
1099 /* This is the order in which to allocate registers for
1100 leaf functions. If all registers can fit in the "i" registers,
1101 then we have the possibility of having a leaf function.
1102 The floating point registers are ordered a little "funny" because in the
1103 64 bit architecture some of them (%f16-%f47) are call-preserved. */
1105 #define REG_LEAF_ALLOC_ORDER \
1106 { 2, 3, 24, 25, 26, 27, 28, 29, \
1107 15, 8, 9, 10, 11, 12, 13, \
1108 16, 17, 18, 19, 20, 21, 22, 23, \
1109 34, 35, 36, 37, 38, 39, \
1110 40, 41, 42, 43, 44, 45, 46, 47, \
1111 80, 81, 82, 83, 84, 85, 86, 87, \
1112 88, 89, 90, 91, 92, 93, 94, 95, \
1113 48, 49, 50, 51, 52, 53, 54, 55, \
1114 56, 57, 58, 59, 60, 61, 62, 63, \
1115 64, 65, 66, 67, 68, 69, 70, 71, \
1116 72, 73, 74, 75, 76, 77, 78, 79, \
1118 96, 97, 98, 99, 100, \
1119 1, 4, 5, 6, 7, 0, 14, 30, 31}
1121 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1123 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
1124 -mflat is used. Function only_leaf_regs_used will return 0 if a global
1125 register is used and is not permitted in a leaf function. We make %g7
1126 a global reg if -mflat and voila. Since %g7 is a system register and is
1127 fixed it won't be used by gcc anyway. */
1129 #define LEAF_REGISTERS \
1130 { 1, 1, 1, 1, 1, 1, 1, 0, \
1131 0, 0, 0, 0, 0, 0, 1, 0, \
1132 0, 0, 0, 0, 0, 0, 0, 0, \
1133 1, 1, 1, 1, 1, 1, 0, 1, \
1134 1, 1, 1, 1, 1, 1, 1, 1, \
1135 1, 1, 1, 1, 1, 1, 1, 1, \
1136 1, 1, 1, 1, 1, 1, 1, 1, \
1137 1, 1, 1, 1, 1, 1, 1, 1, \
1138 1, 1, 1, 1, 1, 1, 1, 1, \
1139 1, 1, 1, 1, 1, 1, 1, 1, \
1140 1, 1, 1, 1, 1, 1, 1, 1, \
1141 1, 1, 1, 1, 1, 1, 1, 1, \
1144 extern char leaf_reg_remap[];
1145 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1147 /* The class value for index registers, and the one for base regs. */
1148 #define INDEX_REG_CLASS GENERAL_REGS
1149 #define BASE_REG_CLASS GENERAL_REGS
1151 /* Local macro to handle the two v9 classes of FP regs. */
1152 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1154 /* Get reg_class from a letter such as appears in the machine description.
1155 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1156 .md file for v8 and v9. */
1158 #define REG_CLASS_FROM_LETTER(C) \
1160 ? ((C) == 'f' ? FP_REGS \
1161 : (C) == 'e' ? EXTRA_FP_REGS \
1162 : (C) == 'c' ? FPCC_REGS \
1164 : ((C) == 'f' ? FP_REGS \
1165 : (C) == 'e' ? FP_REGS \
1166 : (C) == 'c' ? FPCC_REGS \
1169 /* The letters I, J, K, L and M in a register constraint string
1170 can be used to stand for particular ranges of immediate operands.
1171 This macro defines what the ranges are.
1172 C is the letter, and VALUE is a constant value.
1173 Return 1 if VALUE is in the range specified by C.
1175 `I' is used for the range of constants an insn can actually contain.
1176 `J' is used for the range which is just zero (since that is R0).
1177 `K' is used for constants which can be loaded with a single sethi insn.
1178 `L' is used for the range of constants supported by the movcc insns.
1179 `M' is used for the range of constants supported by the movrcc insns. */
1181 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x200) < 0x400)
1182 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x400) < 0x800)
1183 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) ((X) + 0x1000) < 0x2000)
1184 /* 10 and 11 bit immediates are only used for a few specific insns.
1185 SMALL_INT is used throughout the port so we continue to use it. */
1186 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1188 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1189 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1190 : (C) == 'J' ? (VALUE) == 0 \
1191 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
1192 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1193 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1196 /* Similar, but for floating constants, and defining letters G and H.
1197 Here VALUE is the CONST_DOUBLE rtx itself. */
1199 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1200 ((C) == 'G' ? fp_zero_operand (VALUE) \
1201 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1204 /* Given an rtx X being reloaded into a reg required to be
1205 in class CLASS, return the class of reg to actually use.
1206 In general this is just CLASS; but on some machines
1207 in some cases it is preferable to use a more restrictive class. */
1208 /* We can't load constants into FP registers. We can't load any FP constant
1209 if an 'E' constraint fails to match it. */
1210 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1212 && (FP_REG_CLASS_P (CLASS) \
1213 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1214 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1215 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1216 ? NO_REGS : (CLASS))
1218 /* Return the register class of a scratch register needed to load IN into
1219 a register of class CLASS in MODE.
1221 On the SPARC, when PIC, we need a temporary when loading some addresses
1224 Also, we need a temporary when loading/storing a HImode/QImode value
1225 between memory and the FPU registers. This can happen when combine puts
1226 a paradoxical subreg in a float/fix conversion insn. */
1228 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1229 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1230 && (GET_CODE (IN) == MEM \
1231 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1232 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1234 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1235 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1236 && (GET_CODE (IN) == MEM \
1237 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1238 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1240 /* On SPARC it is not possible to directly move data between
1241 GENERAL_REGS and FP_REGS. */
1242 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1243 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1245 /* Return the stack location to use for secondary memory needed reloads.
1246 We want to use the reserved location just below the frame pointer.
1247 However, we must ensure that there is a frame, so use assign_stack_local
1248 if the frame size is zero. */
1249 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1250 (get_frame_size () == 0 \
1251 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1252 : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1253 GEN_INT (STARTING_FRAME_OFFSET))))
1255 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1256 because the movsi and movsf patterns don't handle r/f moves.
1257 For v8 we copy the default definition. */
1258 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1260 ? (GET_MODE_BITSIZE (MODE) < 32 \
1261 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1263 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1264 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1267 /* Return the maximum number of consecutive registers
1268 needed to represent mode MODE in a register of class CLASS. */
1269 /* On SPARC, this is the size of MODE in words. */
1270 #define CLASS_MAX_NREGS(CLASS, MODE) \
1271 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1272 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1274 /* Stack layout; function entry, exit and calling. */
1276 /* Define the number of register that can hold parameters.
1277 These two macros are used only in other macro definitions below.
1278 MODE is the mode of the argument.
1279 !v9: All args are passed in %o0-%o5.
1280 v9: Non-float args are passed in %o0-5 and float args are passed in
1282 #define NPARM_REGS(MODE) \
1283 (TARGET_ARCH64 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6)
1285 /* Define this if pushing a word on the stack
1286 makes the stack pointer a smaller address. */
1287 #define STACK_GROWS_DOWNWARD
1289 /* Define this if the nominal address of the stack frame
1290 is at the high-address end of the local variables;
1291 that is, each additional local variable allocated
1292 goes at a more negative offset in the frame. */
1293 #define FRAME_GROWS_DOWNWARD
1295 /* Offset within stack frame to start allocating local variables at.
1296 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1297 first local allocated. Otherwise, it is the offset to the BEGINNING
1298 of the first local allocated. */
1299 /* This allows space for one TFmode floating point value. */
1300 #define STARTING_FRAME_OFFSET \
1301 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1302 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1304 /* If we generate an insn to push BYTES bytes,
1305 this says how many the stack pointer really advances by.
1306 On SPARC, don't define this because there are no push insns. */
1307 /* #define PUSH_ROUNDING(BYTES) */
1309 /* Offset of first parameter from the argument pointer register value.
1310 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1311 even if this function isn't going to use it.
1312 v9: This is 128 for the ins and locals, plus a reserved space of 8. */
1313 #define FIRST_PARM_OFFSET(FNDECL) \
1314 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 136) \
1315 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1317 /* When a parameter is passed in a register, stack space is still
1318 allocated for it. */
1320 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD)
1323 /* Keep the stack pointer constant throughout the function.
1324 This is both an optimization and a necessity: longjmp
1325 doesn't behave itself when the stack pointer moves within
1327 #define ACCUMULATE_OUTGOING_ARGS
1329 /* Value is the number of bytes of arguments automatically
1330 popped when returning from a subroutine call.
1331 FUNDECL is the declaration node of the function (as a tree),
1332 FUNTYPE is the data type of the function (as a tree),
1333 or for a library call it is an identifier node for the subroutine name.
1334 SIZE is the number of bytes of arguments passed on the stack. */
1336 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1338 /* Some subroutine macros specific to this machine.
1339 When !TARGET_FPU, put float return values in the general registers,
1340 since we don't have any fp registers. */
1341 #define BASE_RETURN_VALUE_REG(MODE) \
1343 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1344 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1345 #define BASE_OUTGOING_VALUE_REG(MODE) \
1347 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1348 : TARGET_FLAT ? 8 : 24) \
1349 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1350 : (TARGET_FLAT ? 8 : 24)))
1351 #define BASE_PASSING_ARG_REG(MODE) \
1353 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1355 #define BASE_INCOMING_ARG_REG(MODE) \
1357 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1358 : TARGET_FLAT ? 8 : 24) \
1359 : (TARGET_FLAT ? 8 : 24))
1361 /* Define this macro if the target machine has "register windows". This
1362 C expression returns the register number as seen by the called function
1363 corresponding to register number OUT as seen by the calling function.
1364 Return OUT if register number OUT is not an outbound register. */
1366 #define INCOMING_REGNO(OUT) \
1367 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1369 /* Define this macro if the target machine has "register windows". This
1370 C expression returns the register number as seen by the calling function
1371 corresponding to register number IN as seen by the called function.
1372 Return IN if register number IN is not an inbound register. */
1374 #define OUTGOING_REGNO(IN) \
1375 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1377 /* Define how to find the value returned by a function.
1378 VALTYPE is the data type of the value (as a tree).
1379 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1380 otherwise, FUNC is 0. */
1382 /* On SPARC the value is found in the first "output" register. */
1384 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1385 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1387 /* But the called function leaves it in the first "input" register. */
1389 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1390 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1392 /* Define how to find the value returned by a library function
1393 assuming the value has mode MODE. */
1395 #define LIBCALL_VALUE(MODE) \
1396 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1398 /* 1 if N is a possible register number for a function value
1399 as seen by the caller.
1400 On SPARC, the first "output" reg is used for integer values,
1401 and the first floating point register is used for floating point values. */
1403 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1405 /* Define the size of space to allocate for the return value of an
1408 #define APPLY_RESULT_SIZE 16
1410 /* 1 if N is a possible register number for function argument passing.
1411 On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */
1413 #define FUNCTION_ARG_REGNO_P(N) \
1414 (TARGET_ARCH64 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \
1415 : ((N) < 14 && (N) > 7))
1417 /* Define a data type for recording info about an argument list
1418 during the scan of that argument list. This data type should
1419 hold all necessary information about the function itself
1420 and about the args processed so far, enough to enable macros
1421 such as FUNCTION_ARG to determine where the next arg should go.
1423 On SPARC (!v9), this is a single integer, which is a number of words
1424 of arguments scanned so far (including the invisible argument,
1425 if any, which holds the structure-value-address).
1426 Thus 7 or more means all following args should go on the stack.
1428 For v9, we record how many of each type has been passed. Different
1429 types get passed differently.
1431 - Float args are passed in %f0-15, after which they go to the stack
1432 where floats and doubles are passed 8 byte aligned and long doubles
1433 are passed 16 byte aligned.
1434 - All aggregates are passed by reference. The callee copies
1435 the structure if necessary, except if stdarg/varargs and the struct
1436 matches the ellipse in which case the caller makes a copy.
1437 - Any non-float argument might be split between memory and reg %o5.
1438 ??? I don't think this can ever happen now that structs are no
1439 longer passed in regs.
1441 For v9 return values:
1443 - For all aggregates, the caller allocates space for the return value,
1444 and passes the pointer as an implicit first argument, which is
1445 allocated like all other arguments.
1446 - The unimp instruction stuff for structure returns is gone. */
1449 enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 };
1451 int arg_count[2]; /* must be int! (for __builtin_args_info) */
1453 #define CUMULATIVE_ARGS struct sparc_args
1455 /* Return index into CUMULATIVE_ARGS. */
1457 #define GET_SPARC_ARG_CLASS(MODE) \
1458 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT)
1460 /* Round a register number up to a proper boundary for an arg of mode MODE.
1461 This macro is only used in this file.
1463 The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */
1465 #define ROUND_REG(CUM, MODE) \
1466 (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1467 ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1468 : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1469 + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \
1470 & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4))
1472 #define ROUND_ADVANCE(SIZE) \
1473 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1475 #else /* ! SPARC_ARCH64 */
1477 #define CUMULATIVE_ARGS int
1479 #define ROUND_REG(CUM, MODE) (CUM)
1481 #define ROUND_ADVANCE(SIZE) \
1482 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1483 #endif /* ! SPARC_ARCH64 */
1485 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1486 for a call to a function whose data type is FNTYPE.
1487 For a library call, FNTYPE is 0.
1489 On SPARC, the offset always starts at 0: the first parm reg is always
1493 extern int sparc_arg_count,sparc_n_named_args;
1494 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1496 (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \
1497 (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \
1498 sparc_arg_count = 0; \
1499 sparc_n_named_args = \
1500 ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \
1501 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \
1502 + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \
1503 || TREE_CODE (TREE_TYPE (FNTYPE)) == QUAL_UNION_TYPE\
1504 || TREE_CODE (TREE_TYPE (FNTYPE)) == SET_TYPE \
1505 || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \
1506 /* Can't tell, treat 'em all as named. */ \
1510 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0)
1513 /* Update the data in CUM to advance over an argument
1514 of mode MODE and data type TYPE.
1515 (TYPE is null for libcalls where that information may not be available.) */
1518 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1520 (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \
1521 ROUND_REG ((CUM), (MODE)) \
1522 + (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1523 ? GET_MODE_SIZE (MODE) / 4 \
1524 : ROUND_ADVANCE ((MODE) == BLKmode \
1525 ? GET_MODE_SIZE (Pmode) \
1526 : GET_MODE_SIZE (MODE))); \
1527 sparc_arg_count++; \
1530 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1531 ((CUM) += ((MODE) != BLKmode \
1532 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1533 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
1536 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1537 This macro is only used in this file. */
1540 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1541 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
1542 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1543 && ((TYPE)==0 || (MODE) != BLKmode))
1545 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1546 ((CUM) < NPARM_REGS (SImode) \
1547 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1548 && ((TYPE)==0 || (MODE) != BLKmode \
1549 || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0)))
1552 /* Determine where to put an argument to a function.
1553 Value is zero to push the argument on the stack,
1554 or a hard register in which to store the argument.
1556 MODE is the argument's machine mode.
1557 TYPE is the data type of the argument (as a tree).
1558 This is null for libcalls where that information may
1560 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1561 the preceding args and about the function being called.
1562 NAMED is nonzero if this argument is a named parameter
1563 (otherwise it is an extra parameter matching an ellipsis). */
1565 /* On SPARC the first six args are normally in registers
1566 and the rest are pushed. Any arg that starts within the first 6 words
1567 is at least partially passed in a register unless its data type forbids.
1568 For v9, the first 6 int args are passed in regs and the first N
1569 float args are passed in regs (where N is such that %f0-15 are filled).
1570 The rest are pushed. Any arg that starts within the first 6 words
1571 is at least partially passed in a register unless its data type forbids. */
1573 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1574 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1575 ? gen_rtx (REG, (MODE), \
1576 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1579 /* Define where a function finds its arguments.
1580 This is different from FUNCTION_ARG because of register windows. */
1582 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1583 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1584 ? gen_rtx (REG, (MODE), \
1585 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1588 /* For an arg passed partly in registers and partly in memory,
1589 this is the number of registers used.
1590 For args passed entirely in registers or entirely in memory, zero.
1591 Any arg that starts in the first 6 regs but won't entirely fit in them
1592 needs partial registers on the Sparc (!v9). On v9, there are no arguments
1593 that are passed partially in registers (??? complex values?). */
1596 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1597 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1598 && ((CUM) + ((MODE) == BLKmode \
1599 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1600 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\
1601 ? (NPARM_REGS (SImode) - (CUM)) \
1605 /* The SPARC ABI stipulates passing struct arguments (of any size) and
1606 (!v9) quad-precision floats by invisible reference.
1607 For Pascal, also pass arrays by reference. */
1608 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1609 ((TYPE && AGGREGATE_TYPE_P (TYPE)) \
1610 || (!TARGET_ARCH64 && MODE == TFmode))
1612 /* A C expression that indicates when it is the called function's
1613 responsibility to make copies of arguments passed by reference.
1614 If the callee can determine that the argument won't be modified, it can
1616 /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't
1617 include the last named argument so we keep track of the args ourselves. */
1620 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1621 (sparc_arg_count < sparc_n_named_args)
1624 /* Initialize data used by insn expanders. This is called from
1625 init_emit, once for each function, before code is generated.
1626 For v9, clear the temp slot used by float/int DImode conversions.
1627 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1628 space at some point.
1629 ??? Use assign_stack_temp? */
1631 extern void sparc64_init_expanders ();
1632 extern struct rtx_def *sparc64_fpconv_stack_temp ();
1634 #define INIT_EXPANDERS sparc64_init_expanders ()
1637 /* Define the information needed to generate branch and scc insns. This is
1638 stored from the compare operation. Note that we can't use "rtx" here
1639 since it hasn't been defined! */
1641 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1643 /* Define the function that build the compare insn for scc and bcc. */
1645 extern struct rtx_def *gen_compare_reg ();
1647 /* This function handles all v9 scc insns */
1649 extern int gen_v9_scc ();
1651 /* Generate the special assembly code needed to tell the assembler whatever
1652 it might need to know about the return value of a function.
1654 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1655 information to the assembler relating to peephole optimization (done in
1658 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1659 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1661 /* Output the label for a function definition. */
1663 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1665 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1666 ASM_OUTPUT_LABEL (FILE, NAME); \
1669 /* This macro generates the assembly code for function entry.
1670 FILE is a stdio stream to output the code to.
1671 SIZE is an int: how many units of temporary storage to allocate.
1672 Refer to the array `regs_ever_live' to determine which registers
1673 to save; `regs_ever_live[I]' is nonzero if register number I
1674 is ever used in the function. This macro is responsible for
1675 knowing which registers should not be saved even if used. */
1677 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1678 of memory. If any fpu reg is used in the function, we allocate
1679 such a block here, at the bottom of the frame, just in case it's needed.
1681 If this function is a leaf procedure, then we may choose not
1682 to do a "save" insn. The decision about whether or not
1683 to do this is made in regclass.c. */
1685 extern int leaf_function;
1686 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1687 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, SIZE) \
1688 : output_function_prologue (FILE, SIZE, leaf_function))
1690 /* Output assembler code to FILE to increment profiler label # LABELNO
1691 for profiling a function entry.
1693 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
1694 during profiling so we need to save/restore it around the call to mcount.
1695 We're guaranteed that a save has just been done, and we use the space
1696 allocated for intreg/fpreg value passing. */
1698 #define FUNCTION_PROFILER(FILE, LABELNO) \
1701 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", (LABELNO)); \
1702 if (! TARGET_ARCH64) \
1703 fputs ("\tst %g2,[%fp-4]\n", FILE); \
1704 fputs ("\tsethi %hi(", FILE); \
1705 assemble_name (FILE, buf); \
1706 fputs ("),%o0\n", FILE); \
1707 if (TARGET_MEDANY) \
1708 fprintf (FILE, "\tadd %o0,%s,%o0\n", MEDANY_BASE_REG); \
1709 fputs ("\tcall mcount\n\tadd %o0,%lo(", FILE); \
1710 assemble_name (FILE, buf); \
1711 fputs ("),%o0\n", FILE); \
1712 if (! TARGET_ARCH64) \
1713 fputs ("\tld [%fp-4],%g2\n", FILE); \
1716 /* There are three profiling modes for basic blocks available.
1717 The modes are selected at compile time by using the options
1718 -a or -ax of the gnu compiler.
1719 The variable `profile_block_flag' will be set according to the
1722 profile_block_flag == 0, no option used:
1726 profile_block_flag == 1, -a option used.
1728 Count frequency of execution of every basic block.
1730 profile_block_flag == 2, -ax option used.
1732 Generate code to allow several different profiling modes at run time.
1733 Available modes are:
1734 Produce a trace of all basic blocks.
1735 Count frequency of jump instructions executed.
1736 In every mode it is possible to start profiling upon entering
1737 certain functions and to disable profiling of some other functions.
1739 The result of basic-block profiling will be written to a file `bb.out'.
1740 If the -ax option is used parameters for the profiling will be read
1745 /* The following macro shall output assembler code to FILE
1746 to initialize basic-block profiling.
1748 If profile_block_flag == 2
1750 Output code to call the subroutine `__bb_init_trace_func'
1751 and pass two parameters to it. The first parameter is
1752 the address of a block allocated in the object module.
1753 The second parameter is the number of the first basic block
1756 The name of the block is a local symbol made with this statement:
1758 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1760 Of course, since you are writing the definition of
1761 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1762 can take a short cut in the definition of this macro and use the
1763 name that you know will result.
1765 The number of the first basic block of the function is
1766 passed to the macro in BLOCK_OR_LABEL.
1768 If described in a virtual assembler language the code to be
1772 parameter2 <- BLOCK_OR_LABEL
1773 call __bb_init_trace_func
1775 else if profile_block_flag != 0
1777 Output code to call the subroutine `__bb_init_func'
1778 and pass one single parameter to it, which is the same
1779 as the first parameter to `__bb_init_trace_func'.
1781 The first word of this parameter is a flag which will be nonzero if
1782 the object module has already been initialized. So test this word
1783 first, and do not call `__bb_init_func' if the flag is nonzero.
1784 Note: When profile_block_flag == 2 the test need not be done
1785 but `__bb_init_trace_func' *must* be called.
1787 BLOCK_OR_LABEL may be used to generate a label number as a
1788 branch destination in case `__bb_init_func' will not be called.
1790 If described in a virtual assembler language the code to be
1801 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1804 int bol = (BLOCK_OR_LABEL); \
1805 switch (profile_block_flag) \
1808 if (TARGET_MEDANY) \
1809 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
1810 MEDANY_BASE_REG, bol, bol); \
1812 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
1816 if (TARGET_MEDANY) \
1817 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1818 MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
1820 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1827 /* The following macro shall output assembler code to FILE
1828 to increment a counter associated with basic block number BLOCKNO.
1830 If profile_block_flag == 2
1832 Output code to initialize the global structure `__bb' and
1833 call the function `__bb_trace_func' which will increment the
1836 `__bb' consists of two words. In the first word the number
1837 of the basic block has to be stored. In the second word
1838 the address of a block allocated in the object module
1841 The basic block number is given by BLOCKNO.
1843 The address of the block is given by the label created with
1845 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1847 by FUNCTION_BLOCK_PROFILER.
1849 Of course, since you are writing the definition of
1850 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1851 can take a short cut in the definition of this macro and use the
1852 name that you know will result.
1854 If described in a virtual assembler language the code to be
1857 move BLOCKNO -> (__bb)
1858 move LPBX0 -> (__bb+4)
1859 call __bb_trace_func
1861 Note that function `__bb_trace_func' must not change the
1862 machine state, especially the flag register. To grant
1863 this, you must output code to save and restore registers
1864 either in this macro or in the macros MACHINE_STATE_SAVE
1865 and MACHINE_STATE_RESTORE. The last two macros will be
1866 used in the function `__bb_trace_func', so you must make
1867 sure that the function prologue does not change any
1868 register prior to saving it with MACHINE_STATE_SAVE.
1870 else if profile_block_flag != 0
1872 Output code to increment the counter directly.
1873 Basic blocks are numbered separately from zero within each
1874 compiled object module. The count associated with block number
1875 BLOCKNO is at index BLOCKNO in an array of words; the name of
1876 this array is a local symbol made with this statement:
1878 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
1880 Of course, since you are writing the definition of
1881 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1882 can take a short cut in the definition of this macro and use the
1883 name that you know will result.
1885 If described in a virtual assembler language, the code to be
1888 inc (LPBX2+4*BLOCKNO)
1892 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1895 int blockn = (BLOCKNO); \
1896 switch (profile_block_flag) \
1899 if (TARGET_MEDANY) \
1900 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1901 blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1903 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1907 if (TARGET_MEDANY) \
1908 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1909 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1911 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1912 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1913 4 * blockn, 4 * blockn, 4 * blockn); \
1919 /* The following macro shall output assembler code to FILE
1920 to indicate a return from function during basic-block profiling.
1922 If profiling_block_flag == 2:
1924 Output assembler code to call function `__bb_trace_ret'.
1926 Note that function `__bb_trace_ret' must not change the
1927 machine state, especially the flag register. To grant
1928 this, you must output code to save and restore registers
1929 either in this macro or in the macros MACHINE_STATE_SAVE_RET
1930 and MACHINE_STATE_RESTORE_RET. The last two macros will be
1931 used in the function `__bb_trace_ret', so you must make
1932 sure that the function prologue does not change any
1933 register prior to saving it with MACHINE_STATE_SAVE_RET.
1935 else if profiling_block_flag != 0:
1937 The macro will not be used, so it need not distinguish
1941 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1942 fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
1944 /* The function `__bb_trace_func' is called in every basic block
1945 and is not allowed to change the machine state. Saving (restoring)
1946 the state can either be done in the BLOCK_PROFILER macro,
1947 before calling function (rsp. after returning from function)
1948 `__bb_trace_func', or it can be done inside the function by
1949 defining the macros:
1951 MACHINE_STATE_SAVE(ID)
1952 MACHINE_STATE_RESTORE(ID)
1954 In the latter case care must be taken, that the prologue code
1955 of function `__bb_trace_func' does not already change the
1956 state prior to saving it with MACHINE_STATE_SAVE.
1958 The parameter `ID' is a string identifying a unique macro use.
1960 On sparc it is sufficient to save the psw register to memory.
1961 Unfortunately the psw register can be read in supervisor mode only,
1962 so we read only the condition codes by using branch instructions
1963 and hope that this is enough. */
1965 #define MACHINE_STATE_SAVE(ID) \
1966 asm (" mov %g0,%l0");\
1967 asm (" be,a LFLGNZ" ID);\
1968 asm (" or %l0,4,%l0");\
1969 asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\
1970 asm (" or %l0,1,%l0");\
1971 asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\
1972 asm (" or %l0,2,%l0");\
1973 asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\
1974 asm (" or %l0,8,%l0");\
1975 asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\
1976 asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \
1977 asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]");
1979 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1980 The psw register can be written in supervisor mode only,
1981 which is true even for simple condition codes.
1982 We use some combination of instructions to produce the
1983 proper condition codes, but some flag combinations can not
1984 be generated in this way. If this happens an unimplemented
1985 instruction will be executed to abort the program. */
1987 #define MACHINE_STATE_RESTORE(ID) \
1988 asm (" sethi %hi(LFLGTAB" ID "),%l1");\
1989 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\
1990 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\
1991 asm (" sll %l0,2,%l0");\
1992 asm (" add %l0,%l1,%l0");\
1993 asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\
1998 asm ("LFLAGS" ID ":");\
2000 asm ("LSAVRET" ID ":");\
2002 asm ("LFLGTAB" ID ": ");\
2003 asm (" .word LSFLG0" ID);\
2004 asm (" .word LSFLGC" ID);\
2005 asm (" .word LSFLGV" ID);\
2006 asm (" .word LSFLGVC" ID);\
2007 asm (" .word LSFLGZ" ID);\
2008 asm (" .word LSFLGZC" ID);\
2009 asm (" .word LSFLGZV" ID);\
2010 asm (" .word LSFLGZVC" ID);\
2011 asm (" .word LSFLGN" ID);\
2012 asm (" .word LSFLGNC" ID);\
2013 asm (" .word LSFLGNV" ID);\
2014 asm (" .word LSFLGNVC" ID);\
2015 asm (" .word LSFLGNZ" ID);\
2016 asm (" .word LSFLGNZC" ID);\
2017 asm (" .word LSFLGNZV" ID);\
2018 asm (" .word LSFLGNZVC" ID);\
2020 asm ("LSFLGVC" ID ": mov -1,%l0");\
2021 asm (" addcc 2,%l0,%g0");\
2022 asm (" sethi %hi(0x80000000),%l0");\
2023 asm (" mov %l0,%l1");\
2024 asm (" ba LFLGRET" ID);\
2025 asm (" addxcc %l0,%l1,%l0");\
2026 asm ("LSFLGC" ID ": mov -1,%l0");\
2027 asm (" ba LFLGRET" ID);\
2028 asm (" addcc 2,%l0,%g0");\
2029 asm ("LSFLGZC" ID ": mov -1,%l0");\
2030 asm (" ba LFLGRET" ID);\
2031 asm (" addcc 1,%l0,%l0");\
2032 asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\
2033 asm (" mov %l0,%l1");\
2034 asm (" ba LFLGRET" ID);\
2035 asm (" addcc %l0,%l1,%l0");\
2036 asm ("LSFLGZ" ID ": ba LFLGRET" ID);\
2037 asm (" subcc %g0,%g0,%g0");\
2038 asm ("LSFLGNC" ID ": add %g0,1,%l0");\
2039 asm (" ba LFLGRET" ID);\
2040 asm (" subcc %g0,%l0,%g0");\
2041 asm ("LSFLG0" ID ": ba LFLGRET" ID);\
2042 asm (" orcc 1,%g0,%g0");\
2043 asm ("LSFLGN" ID ": ba LFLGRET" ID);\
2044 asm (" orcc -1,%g0,%g0");\
2045 asm ("LSFLGV" ID ":");\
2046 asm ("LSFLGZV" ID ":");\
2047 asm ("LSFLGNV" ID ":");\
2048 asm ("LSFLGNVC" ID ":");\
2049 asm ("LSFLGNZ" ID ":");\
2050 asm ("LSFLGNZC" ID ":");\
2051 asm ("LSFLGNZV" ID ":");\
2052 asm ("LSFLGNZVC" ID ":");\
2054 asm ("LFLGRET" ID ":");
2056 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2057 the stack pointer does not matter. The value is tested only in
2058 functions that have frame pointers.
2059 No definition is equivalent to always zero. */
2061 extern int current_function_calls_alloca;
2062 extern int current_function_outgoing_args_size;
2064 #define EXIT_IGNORE_STACK \
2065 (get_frame_size () != 0 \
2066 || current_function_calls_alloca || current_function_outgoing_args_size)
2068 /* This macro generates the assembly code for function exit,
2069 on machines that need it. If FUNCTION_EPILOGUE is not defined
2070 then individual return instructions are generated for each
2071 return statement. Args are same as for FUNCTION_PROLOGUE.
2073 The function epilogue should not depend on the current stack pointer!
2074 It should use the frame pointer only. This is mandatory because
2075 of alloca; we also take advantage of it to omit stack adjustments
2076 before returning. */
2078 /* This declaration is needed due to traditional/ANSI
2079 incompatibilities which cannot be #ifdefed away
2080 because they occur inside of macros. Sigh. */
2081 extern union tree_node *current_function_decl;
2083 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2084 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, SIZE) \
2085 : output_function_epilogue (FILE, SIZE, leaf_function))
2087 #define DELAY_SLOTS_FOR_EPILOGUE \
2088 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2089 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2090 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2091 : eligible_for_epilogue_delay (trial, slots_filled))
2093 /* Define registers used by the epilogue and return instruction. */
2094 #define EPILOGUE_USES(REGNO) \
2095 (!TARGET_FLAT && REGNO == 31)
2097 /* Output assembler code for a block containing the constant parts
2098 of a trampoline, leaving space for the variable parts. */
2100 /* On 32 bit sparcs, the trampoline contains five instructions:
2101 sethi #TOP_OF_FUNCTION,%g1
2102 or #BOTTOM_OF_FUNCTION,%g1,%g1
2103 sethi #TOP_OF_STATIC,%g2
2105 or #BOTTOM_OF_STATIC,%g2,%g2
2107 On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate
2108 constants (plus some padding):
2118 #define TRAMPOLINE_TEMPLATE(FILE) \
2120 if (TARGET_ARCH64) \
2122 fprintf (FILE, "\trd %%pc,%%g1\n"); \
2123 fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \
2124 fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \
2125 fprintf (FILE, "\tjmp %%g1\n"); \
2126 fprintf (FILE, "\tnop\n"); \
2127 fprintf (FILE, "\tnop\n"); \
2128 /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \
2129 fprintf (FILE, "\t.word 0,0,0,0\n"); \
2133 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2134 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2135 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2136 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
2137 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2141 /* Length in units of the trampoline for entering a nested function. */
2143 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 40 : 20)
2145 /* Emit RTL insns to initialize the variable parts of a trampoline.
2146 FNADDR is an RTX for the address of the function's pure code.
2147 CXT is an RTX for the static chain value for the function. */
2149 void sparc_initialize_trampoline ();
2150 void sparc64_initialize_trampoline ();
2151 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2153 if (TARGET_ARCH64) \
2154 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2156 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
2159 /* Generate necessary RTL for __builtin_saveregs().
2160 ARGLIST is the argument list; see expr.c. */
2161 extern struct rtx_def *sparc_builtin_saveregs ();
2162 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
2164 /* Generate RTL to flush the register windows so as to make arbitrary frames
2166 #define SETUP_FRAME_ADDRESSES() \
2167 emit_insn (gen_flush_register_windows ())
2169 /* Given an rtx for the address of a frame,
2170 return an rtx for the address of the word in the frame
2171 that holds the dynamic chain--the previous frame's address.
2172 ??? -mflat support? */
2173 #define DYNAMIC_CHAIN_ADDRESS(frame) \
2174 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
2176 /* The return address isn't on the stack, it is in a register, so we can't
2177 access it from the current frame pointer. We can access it from the
2178 previous frame pointer though by reading a value from the register window
2180 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2182 /* This is the offset of the return address to the true next instruction to be
2183 executed for the current function. */
2184 #define RETURN_ADDR_OFFSET \
2185 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2187 /* The current return address is in %i7. The return address of anything
2188 farther back is in the register window save area at [%fp+60]. */
2189 /* ??? This ignores the fact that the actual return address is +8 for normal
2190 returns, and +12 for structure returns. */
2191 #define RETURN_ADDR_RTX(count, frame) \
2193 ? gen_rtx (REG, Pmode, 31) \
2194 : gen_rtx (MEM, Pmode, \
2195 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
2197 #define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
2199 /* Addressing modes, and classification of registers for them. */
2201 /* #define HAVE_POST_INCREMENT */
2202 /* #define HAVE_POST_DECREMENT */
2204 /* #define HAVE_PRE_DECREMENT */
2205 /* #define HAVE_PRE_INCREMENT */
2207 /* Macros to check register numbers against specific register classes. */
2209 /* These assume that REGNO is a hard or pseudo reg number.
2210 They give nonzero only if REGNO is a hard reg of the suitable class
2211 or a pseudo reg currently allocated to a suitable hard reg.
2212 Since they use reg_renumber, they are safe only once reg_renumber
2213 has been allocated, which happens in local-alloc.c. */
2215 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2216 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2217 #define REGNO_OK_FOR_BASE_P(REGNO) \
2218 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2219 #define REGNO_OK_FOR_FP_P(REGNO) \
2220 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
2221 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
2222 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2224 && (((unsigned) (REGNO) - 96 < 4) \
2225 || ((unsigned) reg_renumber[REGNO] - 96 < 4)))
2227 /* Now macros that check whether X is a register and also,
2228 strictly, whether it is in a specified class.
2230 These macros are specific to the SPARC, and may be used only
2231 in code for printing assembler insns and in conditions for
2232 define_optimization. */
2234 /* 1 if X is an fp register. */
2236 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2238 /* Maximum number of registers that can appear in a valid memory address. */
2240 #define MAX_REGS_PER_ADDRESS 2
2242 /* Recognize any constant value that is a valid address.
2243 When PIC, we do not accept an address that would require a scratch reg
2244 to load into a register. */
2246 #define CONSTANT_ADDRESS_P(X) \
2247 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2248 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2249 || (GET_CODE (X) == CONST \
2250 && ! (flag_pic && pic_address_needs_scratch (X))))
2252 /* Define this, so that when PIC, reload won't try to reload invalid
2253 addresses which require two reload registers. */
2255 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2257 /* Nonzero if the constant value X is a legitimate general operand.
2258 Anything can be made to work except floating point constants. */
2260 #define LEGITIMATE_CONSTANT_P(X) \
2261 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
2263 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2264 and check its validity for a certain class.
2265 We have two alternate definitions for each of them.
2266 The usual definition accepts all pseudo regs; the other rejects
2267 them unless they have been allocated suitable hard regs.
2268 The symbol REG_OK_STRICT causes the latter definition to be used.
2270 Most source files want to accept pseudo regs in the hope that
2271 they will get allocated to the class that the insn wants them to be in.
2272 Source files for reload pass need to be strict.
2273 After reload, it makes no difference, since pseudo regs have
2274 been eliminated by then. */
2276 /* Optional extra constraints for this machine. Borrowed from romp.h.
2278 For the SPARC, `Q' means that this is a memory operand but not a
2279 symbolic memory operand. Note that an unassigned pseudo register
2280 is such a memory operand. Needed because reload will generate
2281 these things in insns and then not re-recognize the insns, causing
2282 constrain_operands to fail.
2284 `S' handles constraints for calls. ??? So where is it? */
2286 #ifndef REG_OK_STRICT
2288 /* Nonzero if X is a hard reg that can be used as an index
2289 or if it is a pseudo reg. */
2290 #define REG_OK_FOR_INDEX_P(X) \
2291 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2292 /* Nonzero if X is a hard reg that can be used as a base reg
2293 or if it is a pseudo reg. */
2294 #define REG_OK_FOR_BASE_P(X) \
2295 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2297 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
2299 #define EXTRA_CONSTRAINT(OP, C) \
2301 ? ((GET_CODE (OP) == MEM \
2302 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
2303 && ! symbolic_memory_operand (OP, VOIDmode)) \
2304 || (reload_in_progress && GET_CODE (OP) == REG \
2305 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
2306 : (! TARGET_ARCH64 && (C) == 'T') \
2307 ? (mem_aligned_8 (OP)) \
2308 : (! TARGET_ARCH64 && (C) == 'U') \
2309 ? (register_ok_for_ldd (OP)) \
2314 /* Nonzero if X is a hard reg that can be used as an index. */
2315 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2316 /* Nonzero if X is a hard reg that can be used as a base reg. */
2317 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2319 #define EXTRA_CONSTRAINT(OP, C) \
2321 ? (GET_CODE (OP) == REG \
2322 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
2323 && reg_renumber[REGNO (OP)] < 0) \
2324 : GET_CODE (OP) == MEM) \
2325 : (! TARGET_ARCH64 && (C) == 'T') \
2326 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2327 : (! TARGET_ARCH64 && (C) == 'U') \
2328 ? (GET_CODE (OP) == REG \
2329 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2330 || reg_renumber[REGNO (OP)] >= 0) \
2331 && register_ok_for_ldd (OP)) \
2335 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2336 that is a valid memory address for an instruction.
2337 The MODE argument is the machine mode for the MEM expression
2338 that wants to use this address.
2340 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2341 ordinarily. This changes a bit when generating PIC.
2343 If you change this, execute "rm explow.o recog.o reload.o". */
2345 #define RTX_OK_FOR_BASE_P(X) \
2346 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2347 || (GET_CODE (X) == SUBREG \
2348 && GET_CODE (SUBREG_REG (X)) == REG \
2349 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2351 #define RTX_OK_FOR_INDEX_P(X) \
2352 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2353 || (GET_CODE (X) == SUBREG \
2354 && GET_CODE (SUBREG_REG (X)) == REG \
2355 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2357 #define RTX_OK_FOR_OFFSET_P(X) \
2358 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
2360 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2361 { if (RTX_OK_FOR_BASE_P (X)) \
2363 else if (GET_CODE (X) == PLUS) \
2365 register rtx op0 = XEXP (X, 0); \
2366 register rtx op1 = XEXP (X, 1); \
2367 if (flag_pic && op0 == pic_offset_table_rtx) \
2369 if (RTX_OK_FOR_BASE_P (op1)) \
2371 else if (flag_pic == 1 \
2372 && GET_CODE (op1) != REG \
2373 && GET_CODE (op1) != LO_SUM \
2374 && GET_CODE (op1) != MEM \
2375 && (GET_CODE (op1) != CONST_INT \
2376 || SMALL_INT (op1))) \
2379 else if (RTX_OK_FOR_BASE_P (op0)) \
2381 if (RTX_OK_FOR_INDEX_P (op1) \
2382 || RTX_OK_FOR_OFFSET_P (op1)) \
2385 else if (RTX_OK_FOR_BASE_P (op1)) \
2387 if (RTX_OK_FOR_INDEX_P (op0) \
2388 || RTX_OK_FOR_OFFSET_P (op0)) \
2392 else if (GET_CODE (X) == LO_SUM) \
2394 register rtx op0 = XEXP (X, 0); \
2395 register rtx op1 = XEXP (X, 1); \
2396 if (RTX_OK_FOR_BASE_P (op0) \
2397 && CONSTANT_P (op1) \
2398 /* We can't allow TFmode, because an offset \
2399 greater than or equal to the alignment (8) \
2400 may cause the LO_SUM to overflow. */ \
2401 && MODE != TFmode) \
2404 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2408 /* Try machine-dependent ways of modifying an illegitimate address
2409 to be legitimate. If we find one, return the new, valid address.
2410 This macro is used in only one place: `memory_address' in explow.c.
2412 OLDX is the address as it was before break_out_memory_refs was called.
2413 In some cases it is useful to look at this to decide what needs to be done.
2415 MODE and WIN are passed so that this macro can use
2416 GO_IF_LEGITIMATE_ADDRESS.
2418 It is always safe for this macro to do nothing. It exists to recognize
2419 opportunities to optimize the output. */
2421 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2422 extern struct rtx_def *legitimize_pic_address ();
2423 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2424 { rtx sparc_x = (X); \
2425 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2426 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2427 force_operand (XEXP (X, 0), NULL_RTX)); \
2428 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2429 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2430 force_operand (XEXP (X, 1), NULL_RTX)); \
2431 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2432 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2434 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2435 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2436 force_operand (XEXP (X, 1), NULL_RTX)); \
2437 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2439 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2440 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2441 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2442 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2443 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2444 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2445 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2446 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2447 || GET_CODE (X) == LABEL_REF) \
2448 (X) = gen_rtx (LO_SUM, Pmode, \
2449 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2450 if (memory_address_p (MODE, X)) \
2453 /* Go to LABEL if ADDR (a legitimate address expression)
2454 has an effect that depends on the machine mode it is used for.
2455 On the SPARC this is never true. */
2457 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2459 /* If we are referencing a function make the SYMBOL_REF special.
2460 In the Medium/Anywhere code model, %g4 points to the data segment so we
2461 must not add it to function addresses. */
2463 #define ENCODE_SECTION_INFO(DECL) \
2465 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2466 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2469 /* Specify the machine mode that this machine uses
2470 for the index in the tablejump instruction. */
2471 #define CASE_VECTOR_MODE Pmode
2473 /* Define this if the tablejump instruction expects the table
2474 to contain offsets from the address of the table.
2475 Do not define this if the table should contain absolute addresses. */
2476 /* #define CASE_VECTOR_PC_RELATIVE */
2478 /* Specify the tree operation to be used to convert reals to integers. */
2479 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2481 /* This is the kind of divide that is easiest to do in the general case. */
2482 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2484 /* Define this as 1 if `char' should by default be signed; else as 0. */
2485 #define DEFAULT_SIGNED_CHAR 1
2487 /* Max number of bytes we can move from memory to memory
2488 in one reasonably fast instruction. */
2491 #if 0 /* Sun 4 has matherr, so this is no good. */
2492 /* This is the value of the error code EDOM for this machine,
2493 used by the sqrt instruction. */
2494 #define TARGET_EDOM 33
2496 /* This is how to refer to the variable errno. */
2497 #define GEN_ERRNO_RTX \
2498 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
2501 /* Define if operations between registers always perform the operation
2502 on the full register even if a narrower mode is specified. */
2503 #define WORD_REGISTER_OPERATIONS
2505 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2506 will either zero-extend or sign-extend. The value of this macro should
2507 be the code that says which one of the two operations is implicitly
2508 done, NIL if none. */
2509 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2511 /* Nonzero if access to memory by bytes is slow and undesirable.
2512 For RISC chips, it means that access to memory by bytes is no
2513 better than access by words when possible, so grab a whole word
2514 and maybe make use of that. */
2515 #define SLOW_BYTE_ACCESS 1
2517 /* We assume that the store-condition-codes instructions store 0 for false
2518 and some other value for true. This is the value stored for true. */
2520 #define STORE_FLAG_VALUE 1
2522 /* When a prototype says `char' or `short', really pass an `int'. */
2523 #define PROMOTE_PROTOTYPES
2525 /* Define this to be nonzero if shift instructions ignore all but the low-order
2527 #define SHIFT_COUNT_TRUNCATED 1
2529 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2530 is done just by pretending it is already truncated. */
2531 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2533 /* Specify the machine mode that pointers have.
2534 After generation of rtl, the compiler makes no further distinction
2535 between pointers and any other objects of this machine mode. */
2536 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2538 /* Generate calls to memcpy, memcmp and memset. */
2539 #define TARGET_MEM_FUNCTIONS
2541 /* Add any extra modes needed to represent the condition code.
2543 On the Sparc, we have a "no-overflow" mode which is used when an add or
2544 subtract insn is used to set the condition code. Different branches are
2545 used in this case for some operations.
2547 We also have two modes to indicate that the relevant condition code is
2548 in the floating-point condition code register. One for comparisons which
2549 will generate an exception if the result is unordered (CCFPEmode) and
2550 one for comparisons which will never trap (CCFPmode).
2552 CCXmode and CCX_NOOVmode are only used by v9. */
2554 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2556 /* Define the names for the modes specified above. */
2558 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2560 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2561 return the mode to be used for the comparison. For floating-point,
2562 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2563 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2564 processing is needed. */
2565 #define SELECT_CC_MODE(OP,X,Y) \
2566 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2567 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2568 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2569 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2570 ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2571 : (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2573 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2574 floating point inequality comparison. */
2576 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2578 /* A function address in a call instruction
2579 is a byte address (for indexing purposes)
2580 so give the MEM rtx a byte's mode. */
2581 #define FUNCTION_MODE SImode
2583 /* Define this if addresses of constant functions
2584 shouldn't be put through pseudo regs where they can be cse'd.
2585 Desirable on machines where ordinary constants are expensive
2586 but a CALL with constant address is cheap. */
2587 #define NO_FUNCTION_CSE
2589 /* alloca should avoid clobbering the old register save area. */
2590 #define SETJMP_VIA_SAVE_AREA
2592 /* Define subroutines to call to handle multiply and divide.
2593 Use the subroutines that Sun's library provides.
2594 The `*' prevents an underscore from being prepended by the compiler. */
2596 #define DIVSI3_LIBCALL "*.div"
2597 #define UDIVSI3_LIBCALL "*.udiv"
2598 #define MODSI3_LIBCALL "*.rem"
2599 #define UMODSI3_LIBCALL "*.urem"
2600 /* .umul is a little faster than .mul. */
2601 #define MULSI3_LIBCALL "*.umul"
2603 /* Define library calls for quad FP operations. These are all part of the
2605 #define ADDTF3_LIBCALL "_Q_add"
2606 #define SUBTF3_LIBCALL "_Q_sub"
2607 #define NEGTF2_LIBCALL "_Q_neg"
2608 #define MULTF3_LIBCALL "_Q_mul"
2609 #define DIVTF3_LIBCALL "_Q_div"
2610 #define FLOATSITF2_LIBCALL "_Q_itoq"
2611 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2612 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2613 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2614 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2615 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2616 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2617 #define EQTF2_LIBCALL "_Q_feq"
2618 #define NETF2_LIBCALL "_Q_fne"
2619 #define GTTF2_LIBCALL "_Q_fgt"
2620 #define GETF2_LIBCALL "_Q_fge"
2621 #define LTTF2_LIBCALL "_Q_flt"
2622 #define LETF2_LIBCALL "_Q_fle"
2624 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2625 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2626 and the compiler will notice and try to use the TFmode sqrt instruction
2627 for calls to the builtin function sqrt, but this fails. */
2628 #define INIT_TARGET_OPTABS \
2630 add_optab->handlers[(int) TFmode].libfunc \
2631 = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \
2632 sub_optab->handlers[(int) TFmode].libfunc \
2633 = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \
2634 neg_optab->handlers[(int) TFmode].libfunc \
2635 = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \
2636 smul_optab->handlers[(int) TFmode].libfunc \
2637 = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \
2638 flodiv_optab->handlers[(int) TFmode].libfunc \
2639 = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \
2640 eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \
2641 netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \
2642 gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \
2643 getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \
2644 lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \
2645 letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \
2646 trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \
2647 trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \
2648 extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \
2649 extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \
2650 floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \
2651 fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \
2652 fixunstfsi_libfunc \
2653 = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \
2655 sqrt_optab->handlers[(int) TFmode].libfunc \
2656 = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \
2657 INIT_SUBTARGET_OPTABS; \
2660 /* This is meant to be redefined in the host dependent files */
2661 #define INIT_SUBTARGET_OPTABS
2663 /* Compute the cost of computing a constant rtl expression RTX
2664 whose rtx-code is CODE. The body of this macro is a portion
2665 of a switch statement. If the code is computed here,
2666 return it with a return statement. Otherwise, break from the switch. */
2668 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2670 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2678 case CONST_DOUBLE: \
2679 if (GET_MODE (RTX) == DImode) \
2680 if ((XINT (RTX, 3) == 0 \
2681 && (unsigned) XINT (RTX, 2) < 0x1000) \
2682 || (XINT (RTX, 3) == -1 \
2683 && XINT (RTX, 2) < 0 \
2684 && XINT (RTX, 2) >= -0x1000)) \
2688 /* Compute the cost of an address. For the sparc, all valid addresses are
2690 ??? Is this true for v9? */
2692 #define ADDRESS_COST(RTX) 1
2694 /* Compute extra cost of moving data between one register class
2696 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2697 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2698 (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \
2699 || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2)
2701 /* Provide the costs of a rtl expression. This is in the body of a
2702 switch on CODE. The purpose for the cost of MULT is to encourage
2703 `synth_mult' to find a synthetic multiply when reasonable.
2705 If we need more than 12 insns to do a multiply, then go out-of-line,
2706 since the call overhead will be < 10% of the cost of the multiply. */
2708 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2710 return (TARGET_V8 || TARGET_SPARCLITE) \
2711 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2716 return COSTS_N_INSNS (25); \
2717 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2718 so that cse will favor the latter. */ \
2723 /* Adjust the cost of dependencies. */
2724 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2725 if (sparc_cpu == PROCESSOR_SUPERSPARC) \
2726 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2728 /* Conditional branches with empty delay slots have a length of two. */
2729 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2730 if (GET_CODE (INSN) == CALL_INSN \
2731 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2734 /* Control the assembler format that we output. */
2736 /* Output at beginning of assembler file. */
2738 #define ASM_FILE_START(file)
2740 /* Output to assembler file text saying following lines
2741 may contain character constants, extra white space, comments, etc. */
2743 #define ASM_APP_ON ""
2745 /* Output to assembler file text saying following lines
2746 no longer contain unusual constructs. */
2748 #define ASM_APP_OFF ""
2750 /* ??? Try to make the style consistent here (_OP?). */
2752 #define ASM_LONGLONG ".xword"
2753 #define ASM_LONG ".word"
2754 #define ASM_SHORT ".half"
2755 #define ASM_BYTE_OP ".byte"
2756 #define ASM_FLOAT ".single"
2757 #define ASM_DOUBLE ".double"
2758 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2760 /* Output before read-only data. */
2762 #define TEXT_SECTION_ASM_OP ".text"
2764 /* Output before writable data. */
2766 #define DATA_SECTION_ASM_OP ".data"
2768 /* How to refer to registers in assembler output.
2769 This sequence is indexed by compiler's hard-register-number (see above). */
2771 #define REGISTER_NAMES \
2772 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2773 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2774 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2775 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2776 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2777 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2778 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2779 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2780 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2781 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2782 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2783 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2784 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2786 /* Define additional names for use in asm clobbers and asm declarations. */
2788 #define ADDITIONAL_REGISTER_NAMES \
2789 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2791 /* How to renumber registers for dbx and gdb. In the flat model, the frame
2792 pointer is really %i7. */
2794 #define DBX_REGISTER_NUMBER(REGNO) \
2795 (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
2797 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2798 can run past this up to a continuation point. Once we used 1500, but
2799 a single entry in C++ can run more than 500 bytes, due to the length of
2800 mangled symbol names. dbxout.c should really be fixed to do
2801 continuations when they are actually needed instead of trying to
2803 #define DBX_CONTIN_LENGTH 1000
2805 /* This is how to output a note to DBX telling it the line number
2806 to which the following sequence of instructions corresponds.
2808 This is needed for SunOS 4.0, and should not hurt for 3.2
2810 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2811 { static int sym_lineno = 1; \
2812 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2813 line, sym_lineno, sym_lineno); \
2816 /* This is how to output the definition of a user-level label named NAME,
2817 such as the label on a static function or variable NAME. */
2819 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2820 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2822 /* This is how to output a command to make the user-level label named NAME
2823 defined for reference from other files. */
2825 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2826 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2828 /* The prefix to add to user-visible assembler symbols. */
2830 #define USER_LABEL_PREFIX "_"
2832 /* This is how to output a definition of an internal numbered label where
2833 PREFIX is the class of label and NUM is the number within the class. */
2835 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2836 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2838 /* This is how to store into the string LABEL
2839 the symbol_ref name of an internal numbered label where
2840 PREFIX is the class of label and NUM is the number within the class.
2841 This is suitable for output with `assemble_name'. */
2843 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2844 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2846 /* This is how to output an assembler line defining a `double' constant. */
2848 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2851 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2852 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2853 ASM_LONG, t[0], ASM_LONG, t[1]); \
2856 /* This is how to output an assembler line defining a `float' constant. */
2858 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2861 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2862 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
2865 /* This is how to output an assembler line defining a `long double'
2868 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2871 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2872 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2873 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
2876 /* This is how to output an assembler line defining an `int' constant. */
2878 #define ASM_OUTPUT_INT(FILE,VALUE) \
2879 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2880 output_addr_const (FILE, (VALUE)), \
2881 fprintf (FILE, "\n"))
2883 /* This is how to output an assembler line defining a DImode constant. */
2884 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2885 output_double_int (FILE, VALUE)
2887 /* Likewise for `char' and `short' constants. */
2889 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2890 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2891 output_addr_const (FILE, (VALUE)), \
2892 fprintf (FILE, "\n"))
2894 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2895 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2896 output_addr_const (FILE, (VALUE)), \
2897 fprintf (FILE, "\n"))
2899 /* This is how to output an assembler line for a numeric constant byte. */
2901 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2902 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2904 /* This is how to output an element of a case-vector that is absolute. */
2906 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2909 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2910 if (Pmode == SImode) \
2911 fprintf (FILE, "\t.word\t"); \
2912 else if (TARGET_MEDLOW) \
2913 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2915 fprintf (FILE, "\t.xword\t"); \
2916 assemble_name (FILE, label); \
2917 fprintf (FILE, "\n"); \
2920 /* This is how to output an element of a case-vector that is relative.
2921 (SPARC uses such vectors only when generating PIC.) */
2923 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2926 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2927 if (Pmode == SImode) \
2928 fprintf (FILE, "\t.word\t"); \
2929 else if (TARGET_MEDLOW) \
2930 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2932 fprintf (FILE, "\t.xword\t"); \
2933 assemble_name (FILE, label); \
2934 fprintf (FILE, "-1b\n"); \
2937 /* This is how to output an assembler line
2938 that says to advance the location counter
2939 to a multiple of 2**LOG bytes. */
2941 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2943 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2945 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2946 fprintf (FILE, "\t.skip %u\n", (SIZE))
2948 /* This says how to output an assembler line
2949 to define a global common symbol. */
2951 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2952 ( fputs ("\t.common ", (FILE)), \
2953 assemble_name ((FILE), (NAME)), \
2954 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2956 /* This says how to output an assembler line to define a local common
2959 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2960 ( fputs ("\t.reserve ", (FILE)), \
2961 assemble_name ((FILE), (NAME)), \
2962 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2963 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2965 /* A C statement (sans semicolon) to output to the stdio stream
2966 FILE the assembler definition of uninitialized global DECL named
2967 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2968 Try to use asm_output_aligned_bss to implement this macro. */
2970 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2972 fputs (".globl ", (FILE)); \
2973 assemble_name ((FILE), (NAME)); \
2974 fputs ("\n", (FILE)); \
2975 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2978 /* Store in OUTPUT a string (made with alloca) containing
2979 an assembler-name for a local static variable named NAME.
2980 LABELNO is an integer which is different for each call. */
2982 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2983 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2984 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2986 #define IDENT_ASM_OP ".ident"
2988 /* Output #ident as a .ident. */
2990 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2991 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
2993 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2994 Used for C++ multiple inheritance. */
2995 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2997 int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \
2999 fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \
3003 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3004 fprintf (FILE, "\tsave %%sp,-112,%%sp\n"); \
3005 fprintf (FILE, "\tcall "); \
3007 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3008 fprintf (FILE, ",0\n"); \
3010 else if (TARGET_MEDANY || TARGET_FULLANY) \
3012 fprintf (FILE, "\tsetx "); \
3014 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3015 fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \
3019 fprintf (FILE, "\tsethi %%hi("); \
3021 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3022 fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \
3024 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3025 fprintf (FILE, ")\n"); \
3028 fprintf (FILE, "\tnop\n"); \
3029 else if (flag_pic) \
3030 fprintf (FILE, "\trestore\n"); \
3032 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3035 /* Define the parentheses used to group arithmetic operations
3036 in assembler code. */
3038 #define ASM_OPEN_PAREN "("
3039 #define ASM_CLOSE_PAREN ")"
3041 /* Define results of standard character escape sequences. */
3042 #define TARGET_BELL 007
3043 #define TARGET_BS 010
3044 #define TARGET_TAB 011
3045 #define TARGET_NEWLINE 012
3046 #define TARGET_VT 013
3047 #define TARGET_FF 014
3048 #define TARGET_CR 015
3050 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3051 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
3053 /* Print operand X (an rtx) in assembler syntax to file FILE.
3054 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3055 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3057 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3059 /* Print a memory address as an operand to reference that memory location. */
3061 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3062 { register rtx base, index = 0; \
3064 register rtx addr = ADDR; \
3065 if (GET_CODE (addr) == REG) \
3066 fputs (reg_names[REGNO (addr)], FILE); \
3067 else if (GET_CODE (addr) == PLUS) \
3069 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
3070 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
3071 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
3072 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
3074 base = XEXP (addr, 0), index = XEXP (addr, 1); \
3075 fputs (reg_names[REGNO (base)], FILE); \
3077 fprintf (FILE, "%+d", offset); \
3078 else if (GET_CODE (index) == REG) \
3079 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3080 else if (GET_CODE (index) == SYMBOL_REF \
3081 || GET_CODE (index) == CONST) \
3082 fputc ('+', FILE), output_addr_const (FILE, index); \
3085 else if (GET_CODE (addr) == MINUS \
3086 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3088 output_addr_const (FILE, XEXP (addr, 0)); \
3089 fputs ("-(", FILE); \
3090 output_addr_const (FILE, XEXP (addr, 1)); \
3091 fputs ("-.)", FILE); \
3093 else if (GET_CODE (addr) == LO_SUM) \
3095 output_operand (XEXP (addr, 0), 0); \
3096 fputs ("+%lo(", FILE); \
3097 output_address (XEXP (addr, 1)); \
3098 fputc (')', FILE); \
3100 else if (flag_pic && GET_CODE (addr) == CONST \
3101 && GET_CODE (XEXP (addr, 0)) == MINUS \
3102 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3103 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3104 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3106 addr = XEXP (addr, 0); \
3107 output_addr_const (FILE, XEXP (addr, 0)); \
3108 /* Group the args of the second CONST in parenthesis. */ \
3109 fputs ("-(", FILE); \
3110 /* Skip past the second CONST--it does nothing for us. */\
3111 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3112 /* Close the parenthesis. */ \
3113 fputc (')', FILE); \
3117 output_addr_const (FILE, addr); \
3121 /* The number of Pmode words for the setjmp buffer. */
3122 #define JMP_BUF_SIZE 12
3124 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
3126 /* Declare functions defined in sparc.c and used in templates. */
3128 extern char *singlemove_string ();
3129 extern char *output_move_double ();
3130 extern char *output_move_quad ();
3131 extern char *output_fp_move_double ();
3132 extern char *output_fp_move_quad ();
3133 extern char *output_block_move ();
3134 extern char *output_scc_insn ();
3135 extern char *output_cbranch ();
3136 extern char *output_v9branch ();
3137 extern char *output_return ();
3139 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3141 extern int flag_pic;
3143 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
3144 +12, but always using +8 is close enough for frame unwind purposes.
3145 Actually, just using %o7 is close enough for unwinding, but %o7+8
3146 is something you can return to. */
3147 #define INCOMING_RETURN_ADDR_RTX \
3148 gen_rtx (PLUS, word_mode, gen_rtx (REG, word_mode, 15), GEN_INT (8))
3150 /* The offset from the incoming value of %sp to the top of the stack frame
3151 for the current function. On sparc64, we have to account for the stack
3154 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
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