1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
24 #include "config/vxworks-dummy.h"
26 /* Note that some other tm.h files include this one and then override
27 whatever definitions are necessary. */
29 /* Define the specific costs for a given cpu */
31 struct processor_costs {
35 /* Integer signed load */
38 /* Integer zeroed load */
44 /* fmov, fneg, fabs */
48 const int float_plusminus;
54 const int float_cmove;
60 const int float_div_sf;
63 const int float_div_df;
66 const int float_sqrt_sf;
69 const int float_sqrt_df;
77 /* integer multiply cost for each bit set past the most
78 significant 3, so the formula for multiply cost becomes:
81 highest_bit = highest_clear_bit(rs1);
83 highest_bit = highest_set_bit(rs1);
86 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
88 A value of zero indicates that the multiply costs is fixed,
90 const int int_mul_bit_factor;
101 /* penalty for shifts, due to scheduling rules etc. */
102 const int shift_penalty;
105 extern const struct processor_costs *sparc_costs;
107 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
108 Solaris only; otherwise just define __sparc__. Sadly the headers
109 are such a mess there is no Solaris-specific header. */
110 #define TARGET_CPU_CPP_BUILTINS() \
113 builtin_define_std ("sparc"); \
116 builtin_assert ("cpu=sparc64"); \
117 builtin_assert ("machine=sparc64"); \
121 builtin_assert ("cpu=sparc"); \
122 builtin_assert ("machine=sparc"); \
127 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
128 /* #define SPARC_BI_ARCH */
130 /* Macro used later in this file to determine default architecture. */
131 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
133 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
134 architectures to compile for. We allow targets to choose compile time or
135 runtime selection. */
137 #if defined(__sparcv9) || defined(__arch64__)
138 #define TARGET_ARCH32 0
140 #define TARGET_ARCH32 1
144 #define TARGET_ARCH32 (! TARGET_64BIT)
146 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
147 #endif /* SPARC_BI_ARCH */
148 #endif /* IN_LIBGCC2 */
149 #define TARGET_ARCH64 (! TARGET_ARCH32)
151 /* Code model selection in 64-bit environment.
153 The machine mode used for addresses is 32-bit wide:
155 TARGET_CM_32: 32-bit address space.
156 It is the code model used when generating 32-bit code.
158 The machine mode used for addresses is 64-bit wide:
160 TARGET_CM_MEDLOW: 32-bit address space.
161 The executable must be in the low 32 bits of memory.
162 This avoids generating %uhi and %ulo terms. Programs
163 can be statically or dynamically linked.
165 TARGET_CM_MEDMID: 44-bit address space.
166 The executable must be in the low 44 bits of memory,
167 and the %[hml]44 terms are used. The text and data
168 segments have a maximum size of 2GB (31-bit span).
169 The maximum offset from any instruction to the label
170 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
172 TARGET_CM_MEDANY: 64-bit address space.
173 The text and data segments have a maximum size of 2GB
174 (31-bit span) and may be located anywhere in memory.
175 The maximum offset from any instruction to the label
176 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
178 TARGET_CM_EMBMEDANY: 64-bit address space.
179 The text and data segments have a maximum size of 2GB
180 (31-bit span) and may be located anywhere in memory.
181 The global register %g4 contains the start address of
182 the data segment. Programs are statically linked and
183 PIC is not supported.
185 Different code models are not supported in 32-bit environment. */
196 extern enum cmodel sparc_cmodel;
198 /* V9 code model selection. */
199 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
200 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
201 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
202 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
204 #define SPARC_DEFAULT_CMODEL CM_32
206 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
207 which requires the following macro to be true if enabled. Prior to V9,
208 there are no instructions to even talk about memory synchronization.
209 Note that the UltraSPARC III processors don't implement RMO, unlike the
210 UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
213 Default to false; for example, Solaris never enables RMO, only ever uses
214 total memory ordering (TMO). */
215 #define SPARC_RELAXED_ORDERING false
217 /* Do not use the .note.GNU-stack convention by default. */
218 #define NEED_INDICATE_EXEC_STACK 0
220 /* This is call-clobbered in the normal ABI, but is reserved in the
221 home grown (aka upward compatible) embedded ABI. */
222 #define EMBMEDANY_BASE_REG "%g4"
224 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
225 and specified by the user via --with-cpu=foo.
226 This specifies the cpu implementation, not the architecture size. */
227 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
229 #define TARGET_CPU_sparc 0
230 #define TARGET_CPU_v7 0 /* alias for previous */
231 #define TARGET_CPU_sparclet 1
232 #define TARGET_CPU_sparclite 2
233 #define TARGET_CPU_v8 3 /* generic v8 implementation */
234 #define TARGET_CPU_supersparc 4
235 #define TARGET_CPU_hypersparc 5
236 #define TARGET_CPU_sparc86x 6
237 #define TARGET_CPU_sparclite86x 6
238 #define TARGET_CPU_v9 7 /* generic v9 implementation */
239 #define TARGET_CPU_sparcv9 7 /* alias */
240 #define TARGET_CPU_sparc64 7 /* alias */
241 #define TARGET_CPU_ultrasparc 8
242 #define TARGET_CPU_ultrasparc3 9
243 #define TARGET_CPU_niagara 10
244 #define TARGET_CPU_niagara2 11
246 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
247 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
248 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
249 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
250 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
252 #define CPP_CPU32_DEFAULT_SPEC ""
253 #define ASM_CPU32_DEFAULT_SPEC ""
255 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
256 /* ??? What does Sun's CC pass? */
257 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
258 /* ??? It's not clear how other assemblers will handle this, so by default
259 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
260 is handled in sol2.h. */
261 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
265 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
267 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
268 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
269 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
271 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
272 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
273 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
275 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
276 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
277 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
282 #define CPP_CPU64_DEFAULT_SPEC ""
283 #define ASM_CPU64_DEFAULT_SPEC ""
285 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
286 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
287 #define CPP_CPU32_DEFAULT_SPEC ""
288 #define ASM_CPU32_DEFAULT_SPEC ""
291 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
292 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
293 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
296 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
297 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
298 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
301 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
302 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
303 #define ASM_CPU32_DEFAULT_SPEC ""
306 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
307 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
308 #define ASM_CPU32_DEFAULT_SPEC ""
311 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
312 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
313 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
318 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
319 #error Unrecognized value in TARGET_CPU_DEFAULT.
324 #define CPP_CPU_DEFAULT_SPEC \
325 (DEFAULT_ARCH32_P ? "\
326 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
327 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
329 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
330 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
332 #define ASM_CPU_DEFAULT_SPEC \
333 (DEFAULT_ARCH32_P ? "\
334 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
335 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
337 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
338 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
341 #else /* !SPARC_BI_ARCH */
343 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
344 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
346 #endif /* !SPARC_BI_ARCH */
348 /* Define macros to distinguish architectures. */
350 /* Common CPP definitions used by CPP_SPEC amongst the various targets
351 for handling -mcpu=xxx switches. */
352 #define CPP_CPU_SPEC "\
353 %{msoft-float:-D_SOFT_FLOAT} \
355 %{msparclite:-D__sparclite__} \
356 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
357 %{mv8:-D__sparc_v8__} \
358 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
359 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
360 %{mcpu=sparclite:-D__sparclite__} \
361 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
362 %{mcpu=v8:-D__sparc_v8__} \
363 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
364 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
365 %{mcpu=sparclite86x:-D__sparclite86x__} \
366 %{mcpu=v9:-D__sparc_v9__} \
367 %{mcpu=ultrasparc:-D__sparc_v9__} \
368 %{mcpu=ultrasparc3:-D__sparc_v9__} \
369 %{mcpu=niagara:-D__sparc_v9__} \
370 %{mcpu=niagara2:-D__sparc_v9__} \
371 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
373 #define CPP_ARCH32_SPEC ""
374 #define CPP_ARCH64_SPEC "-D__arch64__"
376 #define CPP_ARCH_DEFAULT_SPEC \
377 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
379 #define CPP_ARCH_SPEC "\
380 %{m32:%(cpp_arch32)} \
381 %{m64:%(cpp_arch64)} \
382 %{!m32:%{!m64:%(cpp_arch_default)}} \
385 /* Macros to distinguish endianness. */
386 #define CPP_ENDIAN_SPEC "\
387 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
388 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
390 /* Macros to distinguish the particular subtarget. */
391 #define CPP_SUBTARGET_SPEC ""
393 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
395 /* Prevent error on `-sun4' and `-target sun4' options. */
396 /* This used to translate -dalign to -malign, but that is no good
397 because it can't turn off the usual meaning of making debugging dumps. */
398 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
399 ??? Delete support for -m<cpu> for 2.9. */
402 %{sun4:} %{target:} \
403 %{mcypress:-mcpu=cypress} \
404 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
405 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
408 /* Override in target specific files. */
409 #define ASM_CPU_SPEC "\
410 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
411 %{msparclite:-Asparclite} \
412 %{mf930:-Asparclite} %{mf934:-Asparclite} \
413 %{mcpu=sparclite:-Asparclite} \
414 %{mcpu=sparclite86x:-Asparclite} \
415 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
416 %{mv8plus:-Av8plus} \
418 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
419 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
420 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
421 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
422 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
425 /* Word size selection, among other things.
426 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
428 #define ASM_ARCH32_SPEC "-32"
429 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
430 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
432 #define ASM_ARCH64_SPEC "-64"
434 #define ASM_ARCH_DEFAULT_SPEC \
435 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
437 #define ASM_ARCH_SPEC "\
438 %{m32:%(asm_arch32)} \
439 %{m64:%(asm_arch64)} \
440 %{!m32:%{!m64:%(asm_arch_default)}} \
443 #ifdef HAVE_AS_RELAX_OPTION
444 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
446 #define ASM_RELAX_SPEC ""
449 /* Special flags to the Sun-4 assembler when using pipe for input. */
452 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
453 %(asm_cpu) %(asm_relax)"
455 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
457 /* This macro defines names of additional specifications to put in the specs
458 that can be used in various specifications like CC1_SPEC. Its definition
459 is an initializer with a subgrouping for each command option.
461 Each subgrouping contains a string constant, that defines the
462 specification name, and a string constant that used by the GCC driver
465 Do not define this macro if it does not need to do anything. */
467 #define EXTRA_SPECS \
468 { "cpp_cpu", CPP_CPU_SPEC }, \
469 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
470 { "cpp_arch32", CPP_ARCH32_SPEC }, \
471 { "cpp_arch64", CPP_ARCH64_SPEC }, \
472 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
473 { "cpp_arch", CPP_ARCH_SPEC }, \
474 { "cpp_endian", CPP_ENDIAN_SPEC }, \
475 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
476 { "asm_cpu", ASM_CPU_SPEC }, \
477 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
478 { "asm_arch32", ASM_ARCH32_SPEC }, \
479 { "asm_arch64", ASM_ARCH64_SPEC }, \
480 { "asm_relax", ASM_RELAX_SPEC }, \
481 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
482 { "asm_arch", ASM_ARCH_SPEC }, \
483 SUBTARGET_EXTRA_SPECS
485 #define SUBTARGET_EXTRA_SPECS
487 /* Because libgcc can generate references back to libc (via .umul etc.) we have
488 to list libc again after the second libgcc. */
489 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
492 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
493 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
495 /* ??? This should be 32 bits for v9 but what can we do? */
496 #define WCHAR_TYPE "short unsigned int"
497 #define WCHAR_TYPE_SIZE 16
499 /* Show we can debug even without a frame pointer. */
500 #define CAN_DEBUG_WITHOUT_FP
502 /* Option handling. */
504 #define OVERRIDE_OPTIONS sparc_override_options ()
506 /* Mask of all CPU selection flags. */
508 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
510 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
511 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
512 to get high 32 bits. False in V8+ or V9 because multiply stores
513 a 64-bit result in a register. */
515 #define TARGET_HARD_MUL32 \
516 ((TARGET_V8 || TARGET_SPARCLITE \
517 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
518 && ! TARGET_V8PLUS && TARGET_ARCH32)
520 #define TARGET_HARD_MUL \
521 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
522 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
524 /* MASK_APP_REGS must always be the default because that's what
525 FIXED_REGISTERS is set to and -ffixed- is processed before
526 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
527 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
530 These must match the values for the cpu attribute in sparc.md. */
531 enum processor_type {
535 PROCESSOR_SUPERSPARC,
539 PROCESSOR_HYPERSPARC,
540 PROCESSOR_SPARCLITE86X,
544 PROCESSOR_ULTRASPARC,
545 PROCESSOR_ULTRASPARC3,
550 /* This is set from -m{cpu,tune}=xxx. */
551 extern enum processor_type sparc_cpu;
553 /* Recast the cpu class to be the cpu attribute.
554 Every file includes us, but not every file includes insn-attr.h. */
555 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
557 /* Support for a compile-time default CPU, et cetera. The rules are:
558 --with-cpu is ignored if -mcpu is specified.
559 --with-tune is ignored if -mtune is specified.
560 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
562 #define OPTION_DEFAULT_SPECS \
563 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
564 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
565 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
567 /* sparc_select[0] is reserved for the default cpu. */
568 struct sparc_cpu_select
571 const char *const name;
572 const int set_tune_p;
573 const int set_arch_p;
576 extern struct sparc_cpu_select sparc_select[];
578 /* target machine storage layout */
580 /* Define this if most significant bit is lowest numbered
581 in instructions that operate on numbered bit-fields. */
582 #define BITS_BIG_ENDIAN 1
584 /* Define this if most significant byte of a word is the lowest numbered. */
585 #define BYTES_BIG_ENDIAN 1
587 /* Define this if most significant word of a multiword number is the lowest
589 #define WORDS_BIG_ENDIAN 1
591 /* Define this to set the endianness to use in libgcc2.c, which can
592 not depend on target_flags. */
593 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
594 #define LIBGCC2_WORDS_BIG_ENDIAN 0
596 #define LIBGCC2_WORDS_BIG_ENDIAN 1
599 #define MAX_BITS_PER_WORD 64
601 /* Width of a word, in units (bytes). */
602 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
604 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
606 #define MIN_UNITS_PER_WORD 4
609 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD)
611 /* Now define the sizes of the C data types. */
613 #define SHORT_TYPE_SIZE 16
614 #define INT_TYPE_SIZE 32
615 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
616 #define LONG_LONG_TYPE_SIZE 64
617 #define FLOAT_TYPE_SIZE 32
618 #define DOUBLE_TYPE_SIZE 64
619 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
620 SPARC ABI says that it is 128-bit wide. */
621 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
623 /* Width in bits of a pointer.
624 See also the macro `Pmode' defined below. */
625 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
627 /* If we have to extend pointers (only when TARGET_ARCH64 and not
628 TARGET_PTR64), we want to do it unsigned. This macro does nothing
629 if ptr_mode and Pmode are the same. */
630 #define POINTERS_EXTEND_UNSIGNED 1
632 /* For TARGET_ARCH64 we need this, as we don't have instructions
633 for arithmetic operations which do zero/sign extension at the same time,
634 so without this we end up with a srl/sra after every assignment to an
635 user variable, which means very very bad code. */
636 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
638 && GET_MODE_CLASS (MODE) == MODE_INT \
639 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
642 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
643 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
645 /* Boundary (in *bits*) on which stack pointer should be aligned. */
646 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
647 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
648 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
649 /* Temporary hack until the FIXME above is fixed. */
650 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
652 /* ALIGN FRAMES on double word boundaries */
654 #define SPARC_STACK_ALIGN(LOC) \
655 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
657 /* Allocation boundary (in *bits*) for the code of a function. */
658 #define FUNCTION_BOUNDARY 32
660 /* Alignment of field after `int : 0' in a structure. */
661 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
663 /* Every structure's size must be a multiple of this. */
664 #define STRUCTURE_SIZE_BOUNDARY 8
666 /* A bit-field declared as `int' forces `int' alignment for the struct. */
667 #define PCC_BITFIELD_TYPE_MATTERS 1
669 /* No data type wants to be aligned rounder than this. */
670 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
672 /* The best alignment to use in cases where we have a choice. */
673 #define FASTEST_ALIGNMENT 64
675 /* Define this macro as an expression for the alignment of a structure
676 (given by STRUCT as a tree node) if the alignment computed in the
677 usual way is COMPUTED and the alignment explicitly specified was
680 The default is to use SPECIFIED if it is larger; otherwise, use
681 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
682 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
683 (TARGET_FASTER_STRUCTS ? \
684 ((TREE_CODE (STRUCT) == RECORD_TYPE \
685 || TREE_CODE (STRUCT) == UNION_TYPE \
686 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
687 && TYPE_FIELDS (STRUCT) != 0 \
688 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
689 : MAX ((COMPUTED), (SPECIFIED))) \
690 : MAX ((COMPUTED), (SPECIFIED)))
692 /* Make strings word-aligned so strcpy from constants will be faster. */
693 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
694 ((TREE_CODE (EXP) == STRING_CST \
695 && (ALIGN) < FASTEST_ALIGNMENT) \
696 ? FASTEST_ALIGNMENT : (ALIGN))
698 /* Make arrays of chars word-aligned for the same reasons. */
699 #define DATA_ALIGNMENT(TYPE, ALIGN) \
700 (TREE_CODE (TYPE) == ARRAY_TYPE \
701 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
702 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
704 /* Make local arrays of chars word-aligned for the same reasons. */
705 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
707 /* Set this nonzero if move instructions will actually fail to work
708 when given unaligned data. */
709 #define STRICT_ALIGNMENT 1
711 /* Things that must be doubleword aligned cannot go in the text section,
712 because the linker fails to align the text section enough!
713 Put them in the data section. This macro is only used in this file. */
714 #define MAX_TEXT_ALIGN 32
716 /* Standard register usage. */
718 /* Number of actual hardware registers.
719 The hardware registers are assigned numbers for the compiler
720 from 0 to just below FIRST_PSEUDO_REGISTER.
721 All registers that the compiler knows about must be given numbers,
722 even those that are not normally considered general registers.
724 SPARC has 32 integer registers and 32 floating point registers.
725 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
726 accessible. We still account for them to simplify register computations
727 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
729 Register 100 is used as the integer condition code register.
730 Register 101 is used as the soft frame pointer register. */
732 #define FIRST_PSEUDO_REGISTER 102
734 #define SPARC_FIRST_FP_REG 32
735 /* Additional V9 fp regs. */
736 #define SPARC_FIRST_V9_FP_REG 64
737 #define SPARC_LAST_V9_FP_REG 95
738 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
739 #define SPARC_FIRST_V9_FCC_REG 96
740 #define SPARC_LAST_V9_FCC_REG 99
742 #define SPARC_FCC_REG 96
743 /* Integer CC reg. We don't distinguish %icc from %xcc. */
744 #define SPARC_ICC_REG 100
746 /* Nonzero if REGNO is an fp reg. */
747 #define SPARC_FP_REG_P(REGNO) \
748 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
750 /* Argument passing regs. */
751 #define SPARC_OUTGOING_INT_ARG_FIRST 8
752 #define SPARC_INCOMING_INT_ARG_FIRST 24
753 #define SPARC_FP_ARG_FIRST 32
755 /* 1 for registers that have pervasive standard uses
756 and are not available for the register allocator.
759 g1 is free to use as temporary.
760 g2-g4 are reserved for applications. Gcc normally uses them as
761 temporaries, but this can be disabled via the -mno-app-regs option.
762 g5 through g7 are reserved for the operating system.
765 g1,g5 are free to use as temporaries, and are free to use between calls
766 if the call is to an external function via the PLT.
767 g4 is free to use as a temporary in the non-embedded case.
768 g4 is reserved in the embedded case.
769 g2-g3 are reserved for applications. Gcc normally uses them as
770 temporaries, but this can be disabled via the -mno-app-regs option.
771 g6-g7 are reserved for the operating system (or application in
773 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
774 currently be a fixed register until this pattern is rewritten.
775 Register 1 is also used when restoring call-preserved registers in large
778 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
779 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
782 #define FIXED_REGISTERS \
783 {1, 0, 2, 2, 2, 2, 1, 1, \
784 0, 0, 0, 0, 0, 0, 1, 0, \
785 0, 0, 0, 0, 0, 0, 0, 0, \
786 0, 0, 0, 0, 0, 0, 1, 1, \
788 0, 0, 0, 0, 0, 0, 0, 0, \
789 0, 0, 0, 0, 0, 0, 0, 0, \
790 0, 0, 0, 0, 0, 0, 0, 0, \
791 0, 0, 0, 0, 0, 0, 0, 0, \
793 0, 0, 0, 0, 0, 0, 0, 0, \
794 0, 0, 0, 0, 0, 0, 0, 0, \
795 0, 0, 0, 0, 0, 0, 0, 0, \
796 0, 0, 0, 0, 0, 0, 0, 0, \
800 /* 1 for registers not available across function calls.
801 These must include the FIXED_REGISTERS and also any
802 registers that can be used without being saved.
803 The latter must include the registers where values are returned
804 and the register where structure-value addresses are passed.
805 Aside from that, you can include as many other registers as you like. */
807 #define CALL_USED_REGISTERS \
808 {1, 1, 1, 1, 1, 1, 1, 1, \
809 1, 1, 1, 1, 1, 1, 1, 1, \
810 0, 0, 0, 0, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 1, 1, \
813 1, 1, 1, 1, 1, 1, 1, 1, \
814 1, 1, 1, 1, 1, 1, 1, 1, \
815 1, 1, 1, 1, 1, 1, 1, 1, \
816 1, 1, 1, 1, 1, 1, 1, 1, \
818 1, 1, 1, 1, 1, 1, 1, 1, \
819 1, 1, 1, 1, 1, 1, 1, 1, \
820 1, 1, 1, 1, 1, 1, 1, 1, \
821 1, 1, 1, 1, 1, 1, 1, 1, \
825 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
826 they won't be allocated. */
828 #define CONDITIONAL_REGISTER_USAGE \
831 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
833 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
834 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
836 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
837 /* then honor it. */ \
838 if (TARGET_ARCH32 && fixed_regs[5]) \
840 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
845 for (regno = SPARC_FIRST_V9_FP_REG; \
846 regno <= SPARC_LAST_V9_FP_REG; \
848 fixed_regs[regno] = 1; \
849 /* %fcc0 is used by v8 and v9. */ \
850 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
851 regno <= SPARC_LAST_V9_FCC_REG; \
853 fixed_regs[regno] = 1; \
858 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
859 fixed_regs[regno] = 1; \
861 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
862 /* then honor it. Likewise with g3 and g4. */ \
863 if (fixed_regs[2] == 2) \
864 fixed_regs[2] = ! TARGET_APP_REGS; \
865 if (fixed_regs[3] == 2) \
866 fixed_regs[3] = ! TARGET_APP_REGS; \
867 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
868 fixed_regs[4] = ! TARGET_APP_REGS; \
869 else if (TARGET_CM_EMBMEDANY) \
871 else if (fixed_regs[4] == 2) \
876 /* Return number of consecutive hard regs needed starting at reg REGNO
877 to hold something of mode MODE.
878 This is ordinarily the length in words of a value of mode MODE
879 but can be less for certain modes in special long registers.
881 On SPARC, ordinary registers hold 32 bits worth;
882 this means both integer and floating point registers.
883 On v9, integer regs hold 64 bits worth; floating point regs hold
884 32 bits worth (this includes the new fp regs as even the odd ones are
885 included in the hard register count). */
887 #define HARD_REGNO_NREGS(REGNO, MODE) \
889 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
890 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
891 : (GET_MODE_SIZE (MODE) + 3) / 4) \
892 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
894 /* Due to the ARCH64 discrepancy above we must override this next
896 #define REGMODE_NATURAL_SIZE(MODE) \
897 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
899 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
900 See sparc.c for how we initialize this. */
901 extern const int *hard_regno_mode_classes;
902 extern int sparc_mode_class[];
904 /* ??? Because of the funny way we pass parameters we should allow certain
905 ??? types of float/complex values to be in integer registers during
906 ??? RTL generation. This only matters on arch32. */
907 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
908 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
910 /* Value is 1 if it is OK to rename a hard register FROM to another hard
911 register TO. We cannot rename %g1 as it may be used before the save
912 register window instruction in the prologue. */
913 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
915 /* Value is 1 if it is a good idea to tie two pseudo registers
916 when one has mode MODE1 and one has mode MODE2.
917 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
918 for any hard reg, then this must be 0 for correct output.
920 For V9: SFmode can't be combined with other float modes, because they can't
921 be allocated to the %d registers. Also, DFmode won't fit in odd %f
922 registers, but SFmode will. */
923 #define MODES_TIEABLE_P(MODE1, MODE2) \
924 ((MODE1) == (MODE2) \
925 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
927 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
928 || (MODE1 != SFmode && MODE2 != SFmode)))))
930 /* Specify the registers used for certain standard purposes.
931 The values of these macros are register numbers. */
933 /* Register to use for pushing function arguments. */
934 #define STACK_POINTER_REGNUM 14
936 /* The stack bias (amount by which the hardware register is offset by). */
937 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
939 /* Actual top-of-stack address is 92/176 greater than the contents of the
940 stack pointer register for !v9/v9. That is:
941 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
942 address, and 6*4 bytes for the 6 register parameters.
943 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
945 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
947 /* Base register for access to local variables of the function. */
948 #define HARD_FRAME_POINTER_REGNUM 30
950 /* The soft frame pointer does not have the stack bias applied. */
951 #define FRAME_POINTER_REGNUM 101
953 /* Given the stack bias, the stack pointer isn't actually aligned. */
954 #define INIT_EXPANDERS \
956 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
958 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
959 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
963 /* Value should be nonzero if functions must have frame pointers.
964 Zero means the frame pointer need not be set up (and parms
965 may be accessed via the stack pointer) in functions that seem suitable.
966 Used in flow.c, global.c, ra.c and reload1.c. */
967 #define FRAME_POINTER_REQUIRED \
968 (! (leaf_function_p () && only_leaf_regs_used ()))
970 /* Base register for access to arguments of the function. */
971 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
973 /* Register in which static-chain is passed to a function. This must
974 not be a register used by the prologue. */
975 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
977 /* Register which holds offset table for position-independent
980 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
982 /* Pick a default value we can notice from override_options:
985 Originally it was -1, but later on the container of options changed to
986 unsigned byte, so we decided to pick 127 as default value, which does
987 reflect an undefined default value in case of 0/1. */
989 #define DEFAULT_PCC_STRUCT_RETURN 127
991 /* Functions which return large structures get the address
992 to place the wanted value at offset 64 from the frame.
993 Must reserve 64 bytes for the in and local registers.
994 v9: Functions which return large structures get the address to place the
995 wanted value from an invisible first argument. */
996 #define STRUCT_VALUE_OFFSET 64
998 /* Define the classes of registers for register constraints in the
999 machine description. Also define ranges of constants.
1001 One of the classes must always be named ALL_REGS and include all hard regs.
1002 If there is more than one class, another class must be named NO_REGS
1003 and contain no registers.
1005 The name GENERAL_REGS must be the name of a class (or an alias for
1006 another name such as ALL_REGS). This is the class of registers
1007 that is allowed by "g" or "r" in a register constraint.
1008 Also, registers outside this class are allocated only when
1009 instructions express preferences for them.
1011 The classes must be numbered in nondecreasing order; that is,
1012 a larger-numbered class must never be contained completely
1013 in a smaller-numbered class.
1015 For any two classes, it is very desirable that there be another
1016 class that represents their union. */
1018 /* The SPARC has various kinds of registers: general, floating point,
1019 and condition codes [well, it has others as well, but none that we
1020 care directly about].
1022 For v9 we must distinguish between the upper and lower floating point
1023 registers because the upper ones can't hold SFmode values.
1024 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1025 satisfying a group need for a class will also satisfy a single need for
1026 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1029 It is important that one class contains all the general and all the standard
1030 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1031 because reg_class_record() will bias the selection in favor of fp regs,
1032 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1033 because FP_REGS > GENERAL_REGS.
1035 It is also important that one class contain all the general and all
1036 the fp regs. Otherwise when spilling a DFmode reg, it may be from
1037 EXTRA_FP_REGS but find_reloads() may use class
1038 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
1039 because the compiler thinks it doesn't have a spill reg when in
1042 v9 also has 4 floating point condition code registers. Since we don't
1043 have a class that is the union of FPCC_REGS with either of the others,
1044 it is important that it appear first. Otherwise the compiler will die
1045 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1048 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1049 may try to use it to hold an SImode value. See register_operand.
1050 ??? Should %fcc[0123] be handled similarly?
1053 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1054 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1055 ALL_REGS, LIM_REG_CLASSES };
1057 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1059 /* Give names of register classes as strings for dump file. */
1061 #define REG_CLASS_NAMES \
1062 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1063 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1066 /* Define which registers fit in which classes.
1067 This is an initializer for a vector of HARD_REG_SET
1068 of length N_REG_CLASSES. */
1070 #define REG_CLASS_CONTENTS \
1071 {{0, 0, 0, 0}, /* NO_REGS */ \
1072 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1073 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1074 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1075 {0, -1, 0, 0}, /* FP_REGS */ \
1076 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1077 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1078 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1079 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1081 /* The following macro defines cover classes for Integrated Register
1082 Allocator. Cover classes is a set of non-intersected register
1083 classes covering all hard registers used for register allocation
1084 purpose. Any move between two registers of a cover class should be
1085 cheaper than load or store of the registers. The macro value is
1086 array of register classes with LIM_REG_CLASSES used as the end
1089 #define IRA_COVER_CLASSES \
1091 GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \
1094 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1096 SImode loads to floating-point registers are not zero-extended.
1097 The definition for LOAD_EXTEND_OP specifies that integer loads
1098 narrower than BITS_PER_WORD will be zero-extended. As a result,
1099 we inhibit changes from SImode unless they are to a mode that is
1100 identical in size. */
1102 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1104 && (FROM) == SImode \
1105 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1106 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1108 /* The same information, inverted:
1109 Return the class number of the smallest class containing
1110 reg number REGNO. This could be a conditional expression
1111 or could index an array. */
1113 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1115 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1117 /* This is the order in which to allocate registers normally.
1119 We put %f0-%f7 last among the float registers, so as to make it more
1120 likely that a pseudo-register which dies in the float return register
1121 area will get allocated to the float return register, thus saving a move
1122 instruction at the end of the function.
1124 Similarly for integer return value registers.
1126 We know in this case that we will not end up with a leaf function.
1128 The register allocator is given the global and out registers first
1129 because these registers are call clobbered and thus less useful to
1130 global register allocation.
1132 Next we list the local and in registers. They are not call clobbered
1133 and thus very useful for global register allocation. We list the input
1134 registers before the locals so that it is more likely the incoming
1135 arguments received in those registers can just stay there and not be
1138 #define REG_ALLOC_ORDER \
1139 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1140 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1142 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1143 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1144 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1145 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1146 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1147 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1148 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1149 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1150 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1151 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1152 96, 97, 98, 99, /* %fcc0-3 */ \
1153 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1155 /* This is the order in which to allocate registers for
1156 leaf functions. If all registers can fit in the global and
1157 output registers, then we have the possibility of having a leaf
1160 The macro actually mentioned the input registers first,
1161 because they get renumbered into the output registers once
1162 we know really do have a leaf function.
1164 To be more precise, this register allocation order is used
1165 when %o7 is found to not be clobbered right before register
1166 allocation. Normally, the reason %o7 would be clobbered is
1167 due to a call which could not be transformed into a sibling
1170 As a consequence, it is possible to use the leaf register
1171 allocation order and not end up with a leaf function. We will
1172 not get suboptimal register allocation in that case because by
1173 definition of being potentially leaf, there were no function
1174 calls. Therefore, allocation order within the local register
1175 window is not critical like it is when we do have function calls. */
1177 #define REG_LEAF_ALLOC_ORDER \
1178 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1179 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1181 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1182 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1183 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1184 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1185 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1186 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1187 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1188 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1189 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1190 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1191 96, 97, 98, 99, /* %fcc0-3 */ \
1192 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1194 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1196 extern char sparc_leaf_regs[];
1197 #define LEAF_REGISTERS sparc_leaf_regs
1199 extern char leaf_reg_remap[];
1200 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1202 /* The class value for index registers, and the one for base regs. */
1203 #define INDEX_REG_CLASS GENERAL_REGS
1204 #define BASE_REG_CLASS GENERAL_REGS
1206 /* Local macro to handle the two v9 classes of FP regs. */
1207 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1209 /* Get reg_class from a letter such as appears in the machine description.
1210 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1211 .md file for v8 and v9.
1212 'd' and 'b' are used for single and double precision VIS operations,
1214 'h' is used for V8+ 64 bit global and out registers. */
1216 #define REG_CLASS_FROM_LETTER(C) \
1218 ? ((C) == 'f' ? FP_REGS \
1219 : (C) == 'e' ? EXTRA_FP_REGS \
1220 : (C) == 'c' ? FPCC_REGS \
1221 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1222 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1223 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1225 : ((C) == 'f' ? FP_REGS \
1226 : (C) == 'e' ? FP_REGS \
1227 : (C) == 'c' ? FPCC_REGS \
1230 /* The letters I, J, K, L, M, N, O, P in a register constraint string
1231 can be used to stand for particular ranges of CONST_INTs.
1232 This macro defines what the ranges are.
1233 C is the letter, and VALUE is a constant value.
1234 Return 1 if VALUE is in the range specified by C.
1236 `I' is used for the range of constants an insn can actually contain.
1237 `J' is used for the range which is just zero (since that is R0).
1238 `K' is used for constants which can be loaded with a single sethi insn.
1239 `L' is used for the range of constants supported by the movcc insns.
1240 `M' is used for the range of constants supported by the movrcc insns.
1241 `N' is like K, but for constants wider than 32 bits.
1242 `O' is used for the range which is just 4096.
1245 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
1246 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1247 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1248 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1250 /* 10- and 11-bit immediates are only used for a few specific insns.
1251 SMALL_INT is used throughout the port so we continue to use it. */
1252 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1254 /* Predicate for constants that can be loaded with a sethi instruction.
1255 This is the general, 64-bit aware, bitwise version that ensures that
1256 only constants whose representation fits in the mask
1260 are accepted. It will reject, for example, negative SImode constants
1261 on 64-bit hosts, so correct handling is to mask the value beforehand
1262 according to the mode of the instruction. */
1263 #define SPARC_SETHI_P(X) \
1264 (((unsigned HOST_WIDE_INT) (X) \
1265 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1267 /* Version of the above predicate for SImode constants and below. */
1268 #define SPARC_SETHI32_P(X) \
1269 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1271 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1272 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1273 : (C) == 'J' ? (VALUE) == 0 \
1274 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1275 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1276 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1277 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1278 : (C) == 'O' ? (VALUE) == 4096 \
1281 /* Similar, but for CONST_DOUBLEs, and defining letters G and H.
1282 Here VALUE is the CONST_DOUBLE rtx itself. */
1284 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1285 ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
1286 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1289 /* Given an rtx X being reloaded into a reg required to be
1290 in class CLASS, return the class of reg to actually use.
1291 In general this is just CLASS; but on some machines
1292 in some cases it is preferable to use a more restrictive class. */
1293 /* - We can't load constants into FP registers.
1294 - We can't load FP constants into integer registers when soft-float,
1295 because there is no soft-float pattern with a r/F constraint.
1296 - We can't load FP constants into integer registers for TFmode unless
1297 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1298 - Try and reload integer constants (symbolic or otherwise) back into
1299 registers directly, rather than having them dumped to memory. */
1301 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1303 ? ((FP_REG_CLASS_P (CLASS) \
1304 || (CLASS) == GENERAL_OR_FP_REGS \
1305 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1306 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1308 || (GET_MODE (X) == TFmode \
1309 && ! const_zero_operand (X, TFmode))) \
1311 : (!FP_REG_CLASS_P (CLASS) \
1312 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1317 /* Return the register class of a scratch register needed to load IN into
1318 a register of class CLASS in MODE.
1320 We need a temporary when loading/storing a HImode/QImode value
1321 between memory and the FPU registers. This can happen when combine puts
1322 a paradoxical subreg in a float/fix conversion insn.
1324 We need a temporary when loading/storing a DFmode value between
1325 unaligned memory and the upper FPU registers. */
1327 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1328 ((FP_REG_CLASS_P (CLASS) \
1329 && ((MODE) == HImode || (MODE) == QImode) \
1330 && (GET_CODE (IN) == MEM \
1331 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1332 && true_regnum (IN) == -1))) \
1334 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1335 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1336 && ! mem_min_alignment ((IN), 8)) \
1338 : (((TARGET_CM_MEDANY \
1339 && symbolic_operand ((IN), (MODE))) \
1340 || (TARGET_CM_EMBMEDANY \
1341 && text_segment_operand ((IN), (MODE)))) \
1346 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1347 ((FP_REG_CLASS_P (CLASS) \
1348 && ((MODE) == HImode || (MODE) == QImode) \
1349 && (GET_CODE (IN) == MEM \
1350 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1351 && true_regnum (IN) == -1))) \
1353 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1354 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1355 && ! mem_min_alignment ((IN), 8)) \
1357 : (((TARGET_CM_MEDANY \
1358 && symbolic_operand ((IN), (MODE))) \
1359 || (TARGET_CM_EMBMEDANY \
1360 && text_segment_operand ((IN), (MODE)))) \
1365 /* On SPARC it is not possible to directly move data between
1366 GENERAL_REGS and FP_REGS. */
1367 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1368 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1370 /* Return the stack location to use for secondary memory needed reloads.
1371 We want to use the reserved location just below the frame pointer.
1372 However, we must ensure that there is a frame, so use assign_stack_local
1373 if the frame size is zero. */
1374 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1375 (get_frame_size () == 0 \
1376 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1377 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1378 STARTING_FRAME_OFFSET)))
1380 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1381 because the movsi and movsf patterns don't handle r/f moves.
1382 For v8 we copy the default definition. */
1383 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1385 ? (GET_MODE_BITSIZE (MODE) < 32 \
1386 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1388 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1389 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1392 /* Return the maximum number of consecutive registers
1393 needed to represent mode MODE in a register of class CLASS. */
1394 /* On SPARC, this is the size of MODE in words. */
1395 #define CLASS_MAX_NREGS(CLASS, MODE) \
1396 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1397 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1399 /* Stack layout; function entry, exit and calling. */
1401 /* Define this if pushing a word on the stack
1402 makes the stack pointer a smaller address. */
1403 #define STACK_GROWS_DOWNWARD
1405 /* Define this to nonzero if the nominal address of the stack frame
1406 is at the high-address end of the local variables;
1407 that is, each additional local variable allocated
1408 goes at a more negative offset in the frame. */
1409 #define FRAME_GROWS_DOWNWARD 1
1411 /* Offset within stack frame to start allocating local variables at.
1412 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1413 first local allocated. Otherwise, it is the offset to the BEGINNING
1414 of the first local allocated. */
1415 /* This allows space for one TFmode floating point value, which is used
1416 by SECONDARY_MEMORY_NEEDED_RTX. */
1417 #define STARTING_FRAME_OFFSET \
1418 (TARGET_ARCH64 ? -16 \
1419 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1421 /* Offset of first parameter from the argument pointer register value.
1422 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1423 even if this function isn't going to use it.
1424 v9: This is 128 for the ins and locals. */
1425 #define FIRST_PARM_OFFSET(FNDECL) \
1426 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1428 /* Offset from the argument pointer register value to the CFA.
1429 This is different from FIRST_PARM_OFFSET because the register window
1430 comes between the CFA and the arguments. */
1431 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1433 /* When a parameter is passed in a register, stack space is still
1435 !v9: All 6 possible integer registers have backing store allocated.
1436 v9: Only space for the arguments passed is allocated. */
1437 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1438 meaning to the backend. Further, we need to be able to detect if a
1439 varargs/unprototyped function is called, as they may want to spill more
1440 registers than we've provided space. Ugly, ugly. So for now we retain
1441 all 6 slots even for v9. */
1442 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1444 /* Definitions for register elimination. */
1446 #define ELIMINABLE_REGS \
1447 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1448 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1450 /* The way this is structured, we can't eliminate SFP in favor of SP
1451 if the frame pointer is required: we want to use the SFP->HFP elimination
1452 in that case. But the test in update_eliminables doesn't know we are
1453 assuming below that we only do the former elimination. */
1454 #define CAN_ELIMINATE(FROM, TO) \
1455 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1457 /* We always pretend that this is a leaf function because if it's not,
1458 there's no point in trying to eliminate the frame pointer. If it
1459 is a leaf function, we guessed right! */
1460 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1462 if ((TO) == STACK_POINTER_REGNUM) \
1463 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1466 (OFFSET) += SPARC_STACK_BIAS; \
1469 /* Keep the stack pointer constant throughout the function.
1470 This is both an optimization and a necessity: longjmp
1471 doesn't behave itself when the stack pointer moves within
1473 #define ACCUMULATE_OUTGOING_ARGS 1
1475 /* Value is the number of bytes of arguments automatically
1476 popped when returning from a subroutine call.
1477 FUNDECL is the declaration node of the function (as a tree),
1478 FUNTYPE is the data type of the function (as a tree),
1479 or for a library call it is an identifier node for the subroutine name.
1480 SIZE is the number of bytes of arguments passed on the stack. */
1482 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1484 /* Define this macro if the target machine has "register windows". This
1485 C expression returns the register number as seen by the called function
1486 corresponding to register number OUT as seen by the calling function.
1487 Return OUT if register number OUT is not an outbound register. */
1489 #define INCOMING_REGNO(OUT) \
1490 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1492 /* Define this macro if the target machine has "register windows". This
1493 C expression returns the register number as seen by the calling function
1494 corresponding to register number IN as seen by the called function.
1495 Return IN if register number IN is not an inbound register. */
1497 #define OUTGOING_REGNO(IN) \
1498 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1500 /* Define this macro if the target machine has register windows. This
1501 C expression returns true if the register is call-saved but is in the
1504 #define LOCAL_REGNO(REGNO) \
1505 ((REGNO) >= 16 && (REGNO) <= 31)
1507 /* Define how to find the value returned by a function.
1508 VALTYPE is the data type of the value (as a tree).
1509 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1510 otherwise, FUNC is 0. */
1512 /* On SPARC the value is found in the first "output" register. */
1514 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1515 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1517 /* But the called function leaves it in the first "input" register. */
1519 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1520 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1522 /* Define how to find the value returned by a library function
1523 assuming the value has mode MODE. */
1525 #define LIBCALL_VALUE(MODE) \
1526 function_value (NULL_TREE, (MODE), 1)
1528 /* 1 if N is a possible register number for a function value
1529 as seen by the caller.
1530 On SPARC, the first "output" reg is used for integer values,
1531 and the first floating point register is used for floating point values. */
1533 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1535 /* Define the size of space to allocate for the return value of an
1538 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1540 /* 1 if N is a possible register number for function argument passing.
1541 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1543 #define FUNCTION_ARG_REGNO_P(N) \
1545 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1546 : ((N) >= 8 && (N) <= 13))
1548 /* Define a data type for recording info about an argument list
1549 during the scan of that argument list. This data type should
1550 hold all necessary information about the function itself
1551 and about the args processed so far, enough to enable macros
1552 such as FUNCTION_ARG to determine where the next arg should go.
1554 On SPARC (!v9), this is a single integer, which is a number of words
1555 of arguments scanned so far (including the invisible argument,
1556 if any, which holds the structure-value-address).
1557 Thus 7 or more means all following args should go on the stack.
1559 For v9, we also need to know whether a prototype is present. */
1562 int words; /* number of words passed so far */
1563 int prototype_p; /* nonzero if a prototype is present */
1564 int libcall_p; /* nonzero if a library call */
1566 #define CUMULATIVE_ARGS struct sparc_args
1568 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1569 for a call to a function whose data type is FNTYPE.
1570 For a library call, FNTYPE is 0. */
1572 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1573 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1575 /* Update the data in CUM to advance over an argument
1576 of mode MODE and data type TYPE.
1577 TYPE is null for libcalls where that information may not be available. */
1579 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1580 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1582 /* Determine where to put an argument to a function.
1583 Value is zero to push the argument on the stack,
1584 or a hard register in which to store the argument.
1586 MODE is the argument's machine mode.
1587 TYPE is the data type of the argument (as a tree).
1588 This is null for libcalls where that information may
1590 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1591 the preceding args and about the function being called.
1592 NAMED is nonzero if this argument is a named parameter
1593 (otherwise it is an extra parameter matching an ellipsis). */
1595 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1596 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1598 /* Define where a function finds its arguments.
1599 This is different from FUNCTION_ARG because of register windows. */
1601 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1602 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1604 /* If defined, a C expression which determines whether, and in which direction,
1605 to pad out an argument with extra space. The value should be of type
1606 `enum direction': either `upward' to pad above the argument,
1607 `downward' to pad below, or `none' to inhibit padding. */
1609 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1610 function_arg_padding ((MODE), (TYPE))
1612 /* If defined, a C expression that gives the alignment boundary, in bits,
1613 of an argument with the specified mode and type. If it is not defined,
1614 PARM_BOUNDARY is used for all arguments.
1615 For sparc64, objects requiring 16 byte alignment are passed that way. */
1617 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1619 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1620 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1621 ? 128 : PARM_BOUNDARY)
1623 /* Define the information needed to generate branch and scc insns. This is
1624 stored from the compare operation. Note that we can't use "rtx" here
1625 since it hasn't been defined! */
1627 extern GTY(()) rtx sparc_compare_op0;
1628 extern GTY(()) rtx sparc_compare_op1;
1629 extern GTY(()) rtx sparc_compare_emitted;
1632 /* Generate the special assembly code needed to tell the assembler whatever
1633 it might need to know about the return value of a function.
1635 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1636 information to the assembler relating to peephole optimization (done in
1639 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1640 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1642 /* Output the special assembly code needed to tell the assembler some
1643 register is used as global register variable.
1645 SPARC 64bit psABI declares registers %g2 and %g3 as application
1646 registers and %g6 and %g7 as OS registers. Any object using them
1647 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1648 and how they are used (scratch or some global variable).
1649 Linker will then refuse to link together objects which use those
1650 registers incompatibly.
1652 Unless the registers are used for scratch, two different global
1653 registers cannot be declared to the same name, so in the unlikely
1654 case of a global register variable occupying more than one register
1655 we prefix the second and following registers with .gnu.part1. etc. */
1657 extern GTY(()) char sparc_hard_reg_printed[8];
1659 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1660 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1662 if (TARGET_ARCH64) \
1664 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1666 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1667 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1669 if (reg == (REGNO)) \
1670 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1672 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1673 reg, reg - (REGNO), (NAME)); \
1674 sparc_hard_reg_printed[reg] = 1; \
1681 /* Emit rtl for profiling. */
1682 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1684 /* All the work done in PROFILE_HOOK, but still required. */
1685 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1687 /* Set the name of the mcount function for the system. */
1688 #define MCOUNT_FUNCTION "*mcount"
1690 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1691 the stack pointer does not matter. The value is tested only in
1692 functions that have frame pointers.
1693 No definition is equivalent to always zero. */
1695 #define EXIT_IGNORE_STACK \
1696 (get_frame_size () != 0 \
1697 || cfun->calls_alloca || crtl->outgoing_args_size)
1699 /* Define registers used by the epilogue and return instruction. */
1700 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1701 || (crtl->calls_eh_return && (REGNO) == 1))
1703 /* Length in units of the trampoline for entering a nested function. */
1705 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1707 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1709 /* Emit RTL insns to initialize the variable parts of a trampoline.
1710 FNADDR is an RTX for the address of the function's pure code.
1711 CXT is an RTX for the static chain value for the function. */
1713 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1714 if (TARGET_ARCH64) \
1715 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1717 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1719 /* Generate RTL to flush the register windows so as to make arbitrary frames
1721 #define SETUP_FRAME_ADDRESSES() \
1722 emit_insn (gen_flush_register_windows ())
1724 /* Given an rtx for the address of a frame,
1725 return an rtx for the address of the word in the frame
1726 that holds the dynamic chain--the previous frame's address. */
1727 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1728 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1730 /* Given an rtx for the frame pointer,
1731 return an rtx for the address of the frame. */
1732 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS)
1734 /* The return address isn't on the stack, it is in a register, so we can't
1735 access it from the current frame pointer. We can access it from the
1736 previous frame pointer though by reading a value from the register window
1738 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1740 /* This is the offset of the return address to the true next instruction to be
1741 executed for the current function. */
1742 #define RETURN_ADDR_OFFSET \
1743 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1745 /* The current return address is in %i7. The return address of anything
1746 farther back is in the register window save area at [%fp+60]. */
1747 /* ??? This ignores the fact that the actual return address is +8 for normal
1748 returns, and +12 for structure returns. */
1749 #define RETURN_ADDR_RTX(count, frame) \
1751 ? gen_rtx_REG (Pmode, 31) \
1752 : gen_rtx_MEM (Pmode, \
1753 memory_address (Pmode, plus_constant (frame, \
1754 15 * UNITS_PER_WORD \
1755 + SPARC_STACK_BIAS))))
1757 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1758 +12, but always using +8 is close enough for frame unwind purposes.
1759 Actually, just using %o7 is close enough for unwinding, but %o7+8
1760 is something you can return to. */
1761 #define INCOMING_RETURN_ADDR_RTX \
1762 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1763 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1765 /* The offset from the incoming value of %sp to the top of the stack frame
1766 for the current function. On sparc64, we have to account for the stack
1768 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1770 /* Describe how we implement __builtin_eh_return. */
1771 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1772 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1773 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1775 /* Select a format to encode pointers in exception handling data. CODE
1776 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1777 true if the symbol may be affected by dynamic relocations.
1779 If assembler and linker properly support .uaword %r_disp32(foo),
1780 then use PC relative 32-bit relocations instead of absolute relocs
1781 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1782 for binaries, to save memory.
1784 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1785 symbol %r_disp32() is against was not local, but .hidden. In that
1786 case, we have to use DW_EH_PE_absptr for pic personality. */
1787 #ifdef HAVE_AS_SPARC_UA_PCREL
1788 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1789 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1791 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1792 : ((TARGET_ARCH64 && ! GLOBAL) \
1793 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1796 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1798 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1799 : ((TARGET_ARCH64 && ! GLOBAL) \
1800 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1804 /* Emit a PC-relative relocation. */
1805 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1807 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1808 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1809 assemble_name (FILE, LABEL); \
1810 fputc (')', FILE); \
1814 /* Addressing modes, and classification of registers for them. */
1816 /* Macros to check register numbers against specific register classes. */
1818 /* These assume that REGNO is a hard or pseudo reg number.
1819 They give nonzero only if REGNO is a hard reg of the suitable class
1820 or a pseudo reg currently allocated to a suitable hard reg.
1821 Since they use reg_renumber, they are safe only once reg_renumber
1822 has been allocated, which happens in local-alloc.c. */
1824 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1825 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1826 || (REGNO) == FRAME_POINTER_REGNUM \
1827 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1829 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1831 #define REGNO_OK_FOR_FP_P(REGNO) \
1832 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1833 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1834 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1836 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1837 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1839 /* Now macros that check whether X is a register and also,
1840 strictly, whether it is in a specified class.
1842 These macros are specific to the SPARC, and may be used only
1843 in code for printing assembler insns and in conditions for
1844 define_optimization. */
1846 /* 1 if X is an fp register. */
1848 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1850 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1851 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1853 /* Maximum number of registers that can appear in a valid memory address. */
1855 #define MAX_REGS_PER_ADDRESS 2
1857 /* Recognize any constant value that is a valid address.
1858 When PIC, we do not accept an address that would require a scratch reg
1859 to load into a register. */
1861 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1863 /* Define this, so that when PIC, reload won't try to reload invalid
1864 addresses which require two reload registers. */
1866 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1868 /* Nonzero if the constant value X is a legitimate general operand.
1869 Anything can be made to work except floating point constants.
1870 If TARGET_VIS, 0.0 can be made to work as well. */
1872 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1874 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1875 and check its validity for a certain class.
1876 We have two alternate definitions for each of them.
1877 The usual definition accepts all pseudo regs; the other rejects
1878 them unless they have been allocated suitable hard regs.
1879 The symbol REG_OK_STRICT causes the latter definition to be used.
1881 Most source files want to accept pseudo regs in the hope that
1882 they will get allocated to the class that the insn wants them to be in.
1883 Source files for reload pass need to be strict.
1884 After reload, it makes no difference, since pseudo regs have
1885 been eliminated by then. */
1887 /* Optional extra constraints for this machine.
1889 'Q' handles floating point constants which can be moved into
1890 an integer register with a single sethi instruction.
1892 'R' handles floating point constants which can be moved into
1893 an integer register with a single mov instruction.
1895 'S' handles floating point constants which can be moved into
1896 an integer register using a high/lo_sum sequence.
1898 'T' handles memory addresses where the alignment is known to
1899 be at least 8 bytes.
1901 `U' handles all pseudo registers or a hard even numbered
1902 integer register, needed for ldd/std instructions.
1904 'W' handles the memory operand when moving operands in/out
1905 of 'e' constraint floating point registers.
1907 'Y' handles the zero vector constant. */
1909 #ifndef REG_OK_STRICT
1911 /* Nonzero if X is a hard reg that can be used as an index
1912 or if it is a pseudo reg. */
1913 #define REG_OK_FOR_INDEX_P(X) \
1915 || REGNO (X) == FRAME_POINTER_REGNUM \
1916 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1918 /* Nonzero if X is a hard reg that can be used as a base reg
1919 or if it is a pseudo reg. */
1920 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1922 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
1923 'W' is like 'T' but is assumed true on arch64.
1925 Remember to accept pseudo-registers for memory constraints if reload is
1928 #define EXTRA_CONSTRAINT(OP, C) \
1929 sparc_extra_constraint_check(OP, C, 0)
1933 /* Nonzero if X is a hard reg that can be used as an index. */
1934 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1935 /* Nonzero if X is a hard reg that can be used as a base reg. */
1936 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1938 #define EXTRA_CONSTRAINT(OP, C) \
1939 sparc_extra_constraint_check(OP, C, 1)
1943 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1945 #ifdef HAVE_AS_OFFSETABLE_LO10
1946 #define USE_AS_OFFSETABLE_LO10 1
1948 #define USE_AS_OFFSETABLE_LO10 0
1951 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1952 that is a valid memory address for an instruction.
1953 The MODE argument is the machine mode for the MEM expression
1954 that wants to use this address.
1956 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1957 ordinarily. This changes a bit when generating PIC.
1959 If you change this, execute "rm explow.o recog.o reload.o". */
1961 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1963 #define RTX_OK_FOR_BASE_P(X) \
1964 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1965 || (GET_CODE (X) == SUBREG \
1966 && GET_CODE (SUBREG_REG (X)) == REG \
1967 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1969 #define RTX_OK_FOR_INDEX_P(X) \
1970 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1971 || (GET_CODE (X) == SUBREG \
1972 && GET_CODE (SUBREG_REG (X)) == REG \
1973 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1975 #define RTX_OK_FOR_OFFSET_P(X) \
1976 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1978 #define RTX_OK_FOR_OLO10_P(X) \
1979 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1981 #ifdef REG_OK_STRICT
1982 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1984 if (legitimate_address_p (MODE, X, 1)) \
1988 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1990 if (legitimate_address_p (MODE, X, 0)) \
1995 /* Go to LABEL if ADDR (a legitimate address expression)
1996 has an effect that depends on the machine mode it is used for.
2002 is not equivalent to
2004 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2006 because [%l7+a+1] is interpreted as the address of (a+1). */
2008 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2010 if (flag_pic == 1) \
2012 if (GET_CODE (ADDR) == PLUS) \
2014 rtx op0 = XEXP (ADDR, 0); \
2015 rtx op1 = XEXP (ADDR, 1); \
2016 if (op0 == pic_offset_table_rtx \
2017 && SYMBOLIC_CONST (op1)) \
2023 /* Try machine-dependent ways of modifying an illegitimate address
2024 to be legitimate. If we find one, return the new, valid address.
2025 This macro is used in only one place: `memory_address' in explow.c.
2027 OLDX is the address as it was before break_out_memory_refs was called.
2028 In some cases it is useful to look at this to decide what needs to be done.
2030 MODE and WIN are passed so that this macro can use
2031 GO_IF_LEGITIMATE_ADDRESS.
2033 It is always safe for this macro to do nothing. It exists to recognize
2034 opportunities to optimize the output. */
2036 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2037 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2039 (X) = legitimize_address (X, OLDX, MODE); \
2040 if (memory_address_p (MODE, X)) \
2044 /* Try a machine-dependent way of reloading an illegitimate address
2045 operand. If we find one, push the reload and jump to WIN. This
2046 macro is used in only one place: `find_reloads_address' in reload.c.
2048 For SPARC 32, we wish to handle addresses by splitting them into
2049 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2050 This cuts the number of extra insns by one.
2052 Do nothing when generating PIC code and the address is a
2053 symbolic operand or requires a scratch register. */
2055 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2057 /* Decompose SImode constants into hi+lo_sum. We do have to \
2058 rerecognize what we produce, so be careful. */ \
2059 if (CONSTANT_P (X) \
2060 && (MODE != TFmode || TARGET_ARCH64) \
2061 && GET_MODE (X) == SImode \
2062 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2064 && (symbolic_operand (X, Pmode) \
2065 || pic_address_needs_scratch (X))) \
2066 && sparc_cmodel <= CM_MEDLOW) \
2068 X = gen_rtx_LO_SUM (GET_MODE (X), \
2069 gen_rtx_HIGH (GET_MODE (X), X), X); \
2070 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2071 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2075 /* ??? 64-bit reloads. */ \
2078 /* Specify the machine mode that this machine uses
2079 for the index in the tablejump instruction. */
2080 /* If we ever implement any of the full models (such as CM_FULLANY),
2081 this has to be DImode in that case */
2082 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2083 #define CASE_VECTOR_MODE \
2084 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2086 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2087 we have to sign extend which slows things down. */
2088 #define CASE_VECTOR_MODE \
2089 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2092 /* Define this as 1 if `char' should by default be signed; else as 0. */
2093 #define DEFAULT_SIGNED_CHAR 1
2095 /* Max number of bytes we can move from memory to memory
2096 in one reasonably fast instruction. */
2099 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2100 move-instruction pairs, we will do a movmem or libcall instead. */
2102 #define MOVE_RATIO (optimize_size ? 3 : 8)
2104 /* Define if operations between registers always perform the operation
2105 on the full register even if a narrower mode is specified. */
2106 #define WORD_REGISTER_OPERATIONS
2108 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2109 will either zero-extend or sign-extend. The value of this macro should
2110 be the code that says which one of the two operations is implicitly
2111 done, UNKNOWN if none. */
2112 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2114 /* Nonzero if access to memory by bytes is slow and undesirable.
2115 For RISC chips, it means that access to memory by bytes is no
2116 better than access by words when possible, so grab a whole word
2117 and maybe make use of that. */
2118 #define SLOW_BYTE_ACCESS 1
2120 /* Define this to be nonzero if shift instructions ignore all but the low-order
2122 #define SHIFT_COUNT_TRUNCATED 1
2124 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2125 is done just by pretending it is already truncated. */
2126 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2128 /* Specify the machine mode used for addresses. */
2129 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2131 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2132 return the mode to be used for the comparison. For floating-point,
2133 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2134 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2135 processing is needed. */
2136 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2138 /* Return nonzero if MODE implies a floating point inequality can be
2139 reversed. For SPARC this is always true because we have a full
2140 compliment of ordered and unordered comparisons, but until generic
2141 code knows how to reverse it correctly we keep the old definition. */
2142 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2144 /* A function address in a call instruction for indexing purposes. */
2145 #define FUNCTION_MODE Pmode
2147 /* Define this if addresses of constant functions
2148 shouldn't be put through pseudo regs where they can be cse'd.
2149 Desirable on machines where ordinary constants are expensive
2150 but a CALL with constant address is cheap. */
2151 #define NO_FUNCTION_CSE
2153 /* alloca should avoid clobbering the old register save area. */
2154 #define SETJMP_VIA_SAVE_AREA
2156 /* The _Q_* comparison libcalls return booleans. */
2157 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2159 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2160 that the inputs are fully consumed before the output memory is clobbered. */
2162 #define TARGET_BUGGY_QP_LIB 0
2164 /* Assume by default that we do not have the Solaris-specific conversion
2165 routines nor 64-bit integer multiply and divide routines. */
2167 #define SUN_CONVERSION_LIBFUNCS 0
2168 #define DITF_CONVERSION_LIBFUNCS 0
2169 #define SUN_INTEGER_MULTIPLY_64 0
2171 /* Compute extra cost of moving data between one register class
2173 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2174 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2175 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2176 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2177 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2178 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2179 || sparc_cpu == PROCESSOR_ULTRASPARC3 \
2180 || sparc_cpu == PROCESSOR_NIAGARA \
2181 || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
2183 /* Provide the cost of a branch. For pre-v9 processors we use
2184 a value of 3 to take into account the potential annulling of
2185 the delay slot (which ends up being a bubble in the pipeline slot)
2186 plus a cycle to take into consideration the instruction cache
2189 On v9 and later, which have branch prediction facilities, we set
2190 it to the depth of the pipeline as that is the cost of a
2191 mispredicted branch.
2193 On Niagara, normal branches insert 3 bubbles into the pipe
2194 and annulled branches insert 4 bubbles.
2196 On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
2197 branch costs 6 cycles. */
2199 #define BRANCH_COST \
2200 ((sparc_cpu == PROCESSOR_V9 \
2201 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2203 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2205 : (sparc_cpu == PROCESSOR_NIAGARA \
2207 : (sparc_cpu == PROCESSOR_NIAGARA2 \
2211 /* Control the assembler format that we output. */
2213 /* A C string constant describing how to begin a comment in the target
2214 assembler language. The compiler assumes that the comment will end at
2215 the end of the line. */
2217 #define ASM_COMMENT_START "!"
2219 /* Output to assembler file text saying following lines
2220 may contain character constants, extra white space, comments, etc. */
2222 #define ASM_APP_ON ""
2224 /* Output to assembler file text saying following lines
2225 no longer contain unusual constructs. */
2227 #define ASM_APP_OFF ""
2229 /* How to refer to registers in assembler output.
2230 This sequence is indexed by compiler's hard-register-number (see above). */
2232 #define REGISTER_NAMES \
2233 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2234 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2235 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2236 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2237 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2238 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2239 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2240 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2241 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2242 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2243 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2244 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2245 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2247 /* Define additional names for use in asm clobbers and asm declarations. */
2249 #define ADDITIONAL_REGISTER_NAMES \
2250 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2252 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2253 can run past this up to a continuation point. Once we used 1500, but
2254 a single entry in C++ can run more than 500 bytes, due to the length of
2255 mangled symbol names. dbxout.c should really be fixed to do
2256 continuations when they are actually needed instead of trying to
2258 #define DBX_CONTIN_LENGTH 1000
2260 /* This is how to output a command to make the user-level label named NAME
2261 defined for reference from other files. */
2263 /* Globalizing directive for a label. */
2264 #define GLOBAL_ASM_OP "\t.global "
2266 /* The prefix to add to user-visible assembler symbols. */
2268 #define USER_LABEL_PREFIX "_"
2270 /* This is how to store into the string LABEL
2271 the symbol_ref name of an internal numbered label where
2272 PREFIX is the class of label and NUM is the number within the class.
2273 This is suitable for output with `assemble_name'. */
2275 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2276 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2278 /* This is how we hook in and defer the case-vector until the end of
2280 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2281 sparc_defer_case_vector ((LAB),(VEC), 0)
2283 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2284 sparc_defer_case_vector ((LAB),(VEC), 1)
2286 /* This is how to output an element of a case-vector that is absolute. */
2288 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2291 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2292 if (CASE_VECTOR_MODE == SImode) \
2293 fprintf (FILE, "\t.word\t"); \
2295 fprintf (FILE, "\t.xword\t"); \
2296 assemble_name (FILE, label); \
2297 fputc ('\n', FILE); \
2300 /* This is how to output an element of a case-vector that is relative.
2301 (SPARC uses such vectors only when generating PIC.) */
2303 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2306 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2307 if (CASE_VECTOR_MODE == SImode) \
2308 fprintf (FILE, "\t.word\t"); \
2310 fprintf (FILE, "\t.xword\t"); \
2311 assemble_name (FILE, label); \
2312 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2313 fputc ('-', FILE); \
2314 assemble_name (FILE, label); \
2315 fputc ('\n', FILE); \
2318 /* This is what to output before and after case-vector (both
2319 relative and absolute). If .subsection -1 works, we put case-vectors
2320 at the beginning of the current section. */
2322 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2324 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2325 fprintf(FILE, "\t.subsection\t-1\n")
2327 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2328 fprintf(FILE, "\t.previous\n")
2332 /* This is how to output an assembler line
2333 that says to advance the location counter
2334 to a multiple of 2**LOG bytes. */
2336 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2338 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2340 /* This is how to output an assembler line that says to advance
2341 the location counter to a multiple of 2**LOG bytes using the
2342 "nop" instruction as padding. */
2343 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2345 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2347 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2348 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2350 /* This says how to output an assembler line
2351 to define a global common symbol. */
2353 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2354 ( fputs ("\t.common ", (FILE)), \
2355 assemble_name ((FILE), (NAME)), \
2356 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2358 /* This says how to output an assembler line to define a local common
2361 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2362 ( fputs ("\t.reserve ", (FILE)), \
2363 assemble_name ((FILE), (NAME)), \
2364 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2365 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2367 /* A C statement (sans semicolon) to output to the stdio stream
2368 FILE the assembler definition of uninitialized global DECL named
2369 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2370 Try to use asm_output_aligned_bss to implement this macro. */
2372 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2374 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2377 #define IDENT_ASM_OP "\t.ident\t"
2379 /* Output #ident as a .ident. */
2381 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2382 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2384 /* Prettify the assembly. */
2386 extern int sparc_indent_opcode;
2388 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2390 if (sparc_indent_opcode) \
2393 sparc_indent_opcode = 0; \
2397 #define SPARC_SYMBOL_REF_TLS_P(RTX) \
2398 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
2400 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2401 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2402 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2404 /* Print operand X (an rtx) in assembler syntax to file FILE.
2405 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2406 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2408 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2410 /* Print a memory address as an operand to reference that memory location. */
2412 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2413 { register rtx base, index = 0; \
2415 register rtx addr = ADDR; \
2416 if (GET_CODE (addr) == REG) \
2417 fputs (reg_names[REGNO (addr)], FILE); \
2418 else if (GET_CODE (addr) == PLUS) \
2420 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2421 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2422 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2423 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2425 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2426 if (GET_CODE (base) == LO_SUM) \
2428 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2430 && ! TARGET_CM_MEDMID); \
2431 output_operand (XEXP (base, 0), 0); \
2432 fputs ("+%lo(", FILE); \
2433 output_address (XEXP (base, 1)); \
2434 fprintf (FILE, ")+%d", offset); \
2438 fputs (reg_names[REGNO (base)], FILE); \
2440 fprintf (FILE, "%+d", offset); \
2441 else if (GET_CODE (index) == REG) \
2442 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2443 else if (GET_CODE (index) == SYMBOL_REF \
2444 || GET_CODE (index) == LABEL_REF \
2445 || GET_CODE (index) == CONST) \
2446 fputc ('+', FILE), output_addr_const (FILE, index); \
2447 else gcc_unreachable (); \
2450 else if (GET_CODE (addr) == MINUS \
2451 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2453 output_addr_const (FILE, XEXP (addr, 0)); \
2454 fputs ("-(", FILE); \
2455 output_addr_const (FILE, XEXP (addr, 1)); \
2456 fputs ("-.)", FILE); \
2458 else if (GET_CODE (addr) == LO_SUM) \
2460 output_operand (XEXP (addr, 0), 0); \
2461 if (TARGET_CM_MEDMID) \
2462 fputs ("+%l44(", FILE); \
2464 fputs ("+%lo(", FILE); \
2465 output_address (XEXP (addr, 1)); \
2466 fputc (')', FILE); \
2468 else if (flag_pic && GET_CODE (addr) == CONST \
2469 && GET_CODE (XEXP (addr, 0)) == MINUS \
2470 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2471 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2472 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2474 addr = XEXP (addr, 0); \
2475 output_addr_const (FILE, XEXP (addr, 0)); \
2476 /* Group the args of the second CONST in parenthesis. */ \
2477 fputs ("-(", FILE); \
2478 /* Skip past the second CONST--it does nothing for us. */\
2479 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2480 /* Close the parenthesis. */ \
2481 fputc (')', FILE); \
2485 output_addr_const (FILE, addr); \
2489 /* TLS support defaulting to original Sun flavor. GNU extensions
2490 must be activated in separate configuration files. */
2492 #define TARGET_TLS 1
2494 #define TARGET_TLS 0
2497 #define TARGET_SUN_TLS TARGET_TLS
2498 #define TARGET_GNU_TLS 0
2500 /* The number of Pmode words for the setjmp buffer. */
2501 #define JMP_BUF_SIZE 12
2503 /* We use gcc _mcount for profiling. */
2504 #define NO_PROFILE_COUNTERS 0