1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 94-6, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Sparc64 support has been added by trying to allow for a day when one
28 compiler can handle both v8 and v9. There are a few cases where this
29 isn't doable, but keep them to a minimum!
31 TARGET_V9 is used to select at runtime the sparc64 chip.
32 TARGET_ARCH64 is used to select at runtime a 64 bit environment.
33 SPARC_V9 is defined as 0 or 1 (so it may be used inside and outside
34 #define's), and says whether the cpu is a sparc64 chip (which may be
35 running in a 32 or 64 bit environment).
36 SPARC_ARCH64 is defined as 0 for a 32 bit environment and 1 for a 64 bit
39 In places where it is possible to choose at runtime, use TARGET_V9 and
40 TARGET_ARCH64. In places where it is currently not possible to select
41 between the two at runtime use SPARC_{V9,ARCH64}. Again, keep uses of
42 SPARC_{V9,ARCH64} to a minimum. No attempt is made to support both v8
43 and v9 in the v9 compiler.
45 ??? All uses of SPARC_V9 have been removed. Try not to add new ones.
52 #define SPARC_ARCH64 0
55 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile. */
56 #define TARGET_CPU_sparc 0
57 #define TARGET_CPU_v7 0 /* alias for previous */
58 #define TARGET_CPU_sparclet 1
59 #define TARGET_CPU_sparclite 2
60 #define TARGET_CPU_v8 3
61 #define TARGET_CPU_supersparc 4
62 #define TARGET_CPU_ultrasparc 5
63 #define TARGET_CPU_sparc64 5 /* alias for ultrasparc */
65 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc || TARGET_CPU_DEFAULT == TARGET_CPU_v8 || TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
66 #define CPP_DEFAULT_SPEC ""
67 #define ASM_DEFAULT_SPEC ""
69 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
70 #define CPP_DEFAULT_SPEC "-D__sparclet__"
71 #define ASM_DEFAULT_SPEC "-Asparclet"
73 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
74 #define CPP_DEFAULT_SPEC "-D__sparclite__"
75 #define ASM_DEFAULT_SPEC "-Asparclite"
77 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc64
78 /* ??? What does Sun's CC pass? */
79 #define CPP_DEFAULT_SPEC "-D__sparc_v9__"
80 /* ??? It's not clear how other assemblers will handle this, so by default
81 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
82 is handled in sol2.h. */
83 #define ASM_DEFAULT_SPEC "-Av9"
85 Unrecognized value in TARGET_CPU_DEFAULT.
91 /* Names to predefine in the preprocessor for this target machine. */
93 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
94 the right varags.h file when bootstrapping. */
95 /* ??? It's not clear what value we want to use for -Acpu/machine for
96 sparc64 in 32 bit environments, so for now we only use `sparc64' in
97 64 bit environments. */
98 /* ??? __arch64__ is subject to change. */
101 #define CPP_PREDEFINES \
102 "-Dsparc -Dsun -Dunix -D__arch64__ \
103 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
105 #define CPP_PREDEFINES \
106 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
107 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
110 /* Define macros to distinguish architectures. */
114 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
115 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
118 #define CPP_SPEC "%(cpp_cpu)"
121 /* Common CPP definitions used by CPP_SPEC amongst the various targets
122 for handling -mcpu=xxx switches. */
123 /* ??? v8plus/v9/ultrasparc handling is tentative */
124 #define CPP_CPU_SPEC "\
126 %{msparclite:-D__sparclite__} \
127 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
128 %{mv8:-D__sparc_v8__} \
129 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
130 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
131 %{mcpu=sparclite:-D__sparclite__} \
132 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
133 %{mcpu=v8:-D__sparc_v8__} \
134 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
135 %{mcpu=v8plus:-D__sparc_v9__} \
136 %{mcpu=v9:-D__sparc_v9__} \
137 %{mcpu=ultrasparc:-D__sparc_v9__} \
138 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_default)}}}}}}} \
141 /* Prevent error on `-sun4' and `-target sun4' options. */
142 /* This used to translate -dalign to -malign, but that is no good
143 because it can't turn off the usual meaning of making debugging dumps. */
144 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
145 ??? Delete support for -m<cpu> for 2.9. */
148 %{sun4:} %{target:} \
149 %{mcypress:-mcpu=cypress} \
150 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
151 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
154 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
156 /* Provide required defaults for linker -e and -d switches. */
159 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
160 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
162 /* Special flags to the Sun-4 assembler when using pipe for input. */
165 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
169 /* Override in target specific files. */
170 #define ASM_CPU_SPEC "\
171 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
172 %{msparclite:-Asparclite} \
173 %{mf930:-Asparclite} %{mf934:-Asparclite} \
174 %{mcpu=sparclite:-Asparclite} \
175 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
176 %{mcpu=v8plus:-Av9a} \
178 %{mcpu=ultrasparc:-Av9a} \
179 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_default)}}}}}}} \
182 /* This macro defines names of additional specifications to put in the specs
183 that can be used in various specifications like CC1_SPEC. Its definition
184 is an initializer with a subgrouping for each command option.
186 Each subgrouping contains a string constant, that defines the
187 specification name, and a string constant that used by the GNU CC driver
190 Do not define this macro if it does not need to do anything. */
192 #define EXTRA_SPECS \
193 { "cpp_cpu", CPP_CPU_SPEC }, \
194 { "cpp_default", CPP_DEFAULT_SPEC }, \
195 { "asm_cpu", ASM_CPU_SPEC }, \
196 { "asm_default", ASM_DEFAULT_SPEC }, \
197 SUBTARGET_EXTRA_SPECS
199 #define SUBTARGET_EXTRA_SPECS
202 #define PTRDIFF_TYPE "long long int"
203 #define SIZE_TYPE "long long unsigned int"
205 #define PTRDIFF_TYPE "int"
206 /* The default value for SIZE_TYPE is "unsigned int" which is what we want. */
209 /* ??? This should be 32 bits for v9 but what can we do? */
210 #define WCHAR_TYPE "short unsigned int"
211 #define WCHAR_TYPE_SIZE 16
212 #define MAX_WCHAR_TYPE_SIZE 16
214 /* Show we can debug even without a frame pointer. */
215 #define CAN_DEBUG_WITHOUT_FP
217 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
218 code into the rtl. Also, if we are profiling, we cannot eliminate
219 the frame pointer (because the return address will get smashed). */
221 void sparc_override_options ();
223 #define OVERRIDE_OPTIONS \
225 if (profile_flag || profile_block_flag || profile_arc_flag) \
229 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
230 warning ("%s and profiling conflict: disabling %s", \
231 pic_string, pic_string); \
234 flag_omit_frame_pointer = 0; \
236 sparc_override_options (); \
237 SUBTARGET_OVERRIDE_OPTIONS; \
240 /* This is meant to be redefined in the host dependent files. */
241 #define SUBTARGET_OVERRIDE_OPTIONS
243 /* These compiler options take an argument. We ignore -target for now. */
245 #define WORD_SWITCH_TAKES_ARG(STR) \
246 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
247 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
249 /* Print subsidiary information on the compiler version in use. */
251 #define TARGET_VERSION fprintf (stderr, " (sparc)");
253 /* Generate DBX debugging information. */
255 #define DBX_DEBUGGING_INFO
257 /* Run-time compilation parameters selecting different hardware subsets. */
259 extern int target_flags;
261 /* Nonzero if we should generate code to use the fpu. */
263 #define TARGET_FPU (target_flags & MASK_FPU)
265 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
266 use fast return insns, but lose some generality. */
267 #define MASK_EPILOGUE 2
268 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
270 /* Nonzero if we should assume that double pointers might be unaligned.
271 This can happen when linking gcc compiled code with other compilers,
272 because the ABI only guarantees 4 byte alignment. */
273 #define MASK_UNALIGNED_DOUBLES 4
274 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
276 /* Nonzero means that we should generate code for a v8 sparc. */
278 #define TARGET_V8 (target_flags & MASK_V8)
280 /* Nonzero means that we should generate code for a sparclite.
281 This enables the sparclite specific instructions, but does not affect
282 whether FPU instructions are emitted. */
283 #define MASK_SPARCLITE 0x10
284 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
286 /* Nonzero if we're compiling for the sparclet. */
287 #define MASK_SPARCLET 0x20
288 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
290 /* Nonzero if we're compiling for v9 sparc.
291 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
292 the word size is 64. */
294 #define TARGET_V9 (target_flags & MASK_V9)
296 /* Non-zero to generate code that uses the instructions deprecated in
297 the v9 architecture. This option only applies to v9 systems. */
298 /* ??? This isn't user selectable yet. It's used to enable such insns
299 on 32 bit v9 systems and for the moment they're permanently disabled
300 on 64 bit v9 systems. */
301 #define MASK_DEPRECATED_V8_INSNS 0x80
302 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
304 /* Mask of all CPU selection flags. */
306 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
308 /* Non-zero means don't pass `-assert pure-text' to the linker. */
309 #define MASK_IMPURE_TEXT 0x100
310 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
312 /* Nonzero means that we should generate code using a flat register window
313 model, i.e. no save/restore instructions are generated, which is
314 compatible with normal sparc code.
315 The frame pointer is %i7 instead of %fp. */
316 #define MASK_FLAT 0x200
317 #define TARGET_FLAT (target_flags & MASK_FLAT)
319 /* Nonzero means use the registers that the Sparc ABI reserves for
320 application software. This must be the default to coincide with the
321 setting in FIXED_REGISTERS. */
322 #define MASK_APP_REGS 0x400
323 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
325 /* Option to select how quad word floating point is implemented.
326 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
327 Otherwise, we use the SPARC ABI quad library functions. */
328 #define MASK_HARD_QUAD 0x800
329 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
331 /* Non-zero on little-endian machines. */
332 /* ??? Little endian support currently only exists for sparclet-aout and
333 sparc64-elf configurations. May eventually want to expand the support
334 to all targets, but for now it's kept local to only those two. */
335 #define MASK_LITTLE_ENDIAN 0x1000
336 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
338 /* Nonzero if ints are 64 bits.
339 This automatically implies longs are 64 bits too.
340 This option is for v9 only. */
341 #define MASK_INT64 0x2000
342 #define TARGET_INT64 (target_flags & MASK_INT64)
344 /* Nonzero if longs are 64 bits.
345 This option is for v9 only. */
346 #define MASK_LONG64 0x4000
347 #define TARGET_LONG64 (target_flags & MASK_LONG64)
349 /* Nonzero if pointers are 64 bits.
350 This is not a user selectable option, though it may be one day -
351 so it is used to determine pointer size instead of an architecture flag. */
352 #define MASK_PTR64 0x8000
353 #define TARGET_PTR64 (target_flags & MASK_PTR64)
355 /* Nonzero if generating code to run in a 64 bit environment. */
356 #define MASK_ARCH64 0x10000
357 #define TARGET_ARCH64 (target_flags & MASK_ARCH64)
358 #define TARGET_ARCH32 (! TARGET_ARCH64)
360 /* SPARC64 memory models.
361 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0,
362 avoid generating %uhi and %ulo terms.
363 (pointers can be 32 or 64 bits)
364 TARGET_MEDANY: 64 bit address space, data segment restricted to 4G, but
365 can be loaded anywhere (use %g4 as offset).
366 TARGET_FULLANY: 64 bit address space, no restrictions.
367 This option is not fully supported yet.
368 These options are for v9 only. All mask values are nonzero so the v8
369 compiler can assume this stuff won't interfere. */
370 #define MASK_MEDLOW 0x20000
371 #define MASK_MEDANY 0x40000
372 #define MASK_FULLANY 0x60000
373 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
374 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
375 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
376 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
378 /* ??? There are hardcoded references to this reg in the .md file. */
379 #define MEDANY_BASE_REG "%g4"
381 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
382 adding 2047 to %sp. This option is for v9 only and is the default. */
383 #define MASK_STACK_BIAS 0x80000
384 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
386 /* Non-zero means %g0 is a normal register.
387 We still clobber it as necessary, but we can't rely on it always having
389 We don't bother to support this in true 64 bit mode. */
390 #define MASK_LIVE_G0 0x100000
391 #define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
393 /* Non-zero means the cpu has broken `save' and `restore' insns, only
394 the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
395 We assume the environment will properly handle or otherwise avoid
396 trouble associated with an interrupt occuring after the `save' or trap
397 occuring during it. */
398 #define MASK_BROKEN_SAVERESTORE 0x200000
399 #define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
401 /* Non-zero means -m{,no-}fpu was passed on the command line. */
402 #define MASK_FPU_SET 0x400000
403 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
405 /* Macro to define tables used to set the flags.
406 This is a list in braces of pairs in braces,
407 each pair being { "NAME", VALUE }
408 where VALUE is the bits to set or minus the bits to clear.
409 An empty string NAME is used to identify the default VALUE. */
411 #define TARGET_SWITCHES \
412 { {"fpu", MASK_FPU | MASK_FPU_SET}, \
413 {"no-fpu", -MASK_FPU}, \
414 {"no-fpu", MASK_FPU_SET}, \
415 {"hard-float", MASK_FPU | MASK_FPU_SET}, \
416 {"soft-float", -MASK_FPU}, \
417 {"soft-float", MASK_FPU_SET}, \
418 {"epilogue", MASK_EPILOGUE}, \
419 {"no-epilogue", -MASK_EPILOGUE}, \
420 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
421 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
422 {"impure-text", MASK_IMPURE_TEXT}, \
423 {"no-impure-text", -MASK_IMPURE_TEXT}, \
424 {"flat", MASK_FLAT}, \
425 {"no-flat", -MASK_FLAT}, \
426 {"app-regs", MASK_APP_REGS}, \
427 {"no-app-regs", -MASK_APP_REGS}, \
428 {"hard-quad-float", MASK_HARD_QUAD}, \
429 {"soft-quad-float", -MASK_HARD_QUAD}, \
430 /* ??? These are coerced to -mcpu=. Delete in 2.9. */ \
439 { "", TARGET_DEFAULT}}
441 /* MASK_APP_REGS must always be the default because that's what
442 FIXED_REGISTERS is set to and -ffixed- is processed before
443 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
444 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
446 /* This is meant to be redefined in target specific files. */
447 #define SUBTARGET_SWITCHES
449 /* ??? Until we support a combination 32/64 bit compiler, these options
450 are only defined for the v9 compiler in a true 64 bit environment. */
452 #define ARCH64_SWITCHES \
453 /* {"arch32", -MASK_ARCH64}, */ \
454 /* {"arch64", MASK_ARCH64}, */ \
455 {"int64", MASK_INT64+MASK_LONG64}, \
456 {"int32", -MASK_INT64}, \
457 {"int32", MASK_LONG64}, \
458 {"long64", -MASK_INT64}, \
459 {"long64", MASK_LONG64}, \
460 {"long32", -(MASK_INT64+MASK_LONG64)}, \
461 /* {"ptr64", MASK_PTR64}, */ \
462 /* {"ptr32", -MASK_PTR64}, */ \
463 {"stack-bias", MASK_STACK_BIAS}, \
464 {"no-stack-bias", -MASK_STACK_BIAS}, \
465 {"medlow", -MASK_CODE_MODEL}, \
466 {"medlow", MASK_MEDLOW}, \
467 {"medany", -MASK_CODE_MODEL}, \
468 {"medany", MASK_MEDANY}, \
469 {"fullany", -MASK_CODE_MODEL}, \
470 {"fullany", MASK_FULLANY},
472 #define ARCH64_SWITCHES
476 These must match the values for the cpu attribute in sparc.md. */
477 enum processor_type {
481 PROCESSOR_SUPERSPARC,
492 /* This is set from -m{cpu,tune}=xxx. */
493 extern enum processor_type sparc_cpu;
495 /* Recast the cpu class to be the cpu attribute.
496 Every file includes us, but not every file includes insn-attr.h. */
497 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
499 /* This macro is similar to `TARGET_SWITCHES' but defines names of
500 command options that have values. Its definition is an
501 initializer with a subgrouping for each command option.
503 Each subgrouping contains a string constant, that defines the
504 fixed part of the option name, and the address of a variable.
505 The variable, type `char *', is set to the variable part of the
506 given option if the fixed part matches. The actual option name
507 is made by appending `-m' to the specified name.
509 Here is an example which defines `-mshort-data-NUMBER'. If the
510 given option is `-mshort-data-512', the variable `m88k_short_data'
511 will be set to the string `"512"'.
513 extern char *m88k_short_data;
514 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
516 #define TARGET_OPTIONS \
518 {"cpu=", &sparc_select[1].string}, \
519 {"tune=", &sparc_select[2].string}, \
520 {"align-loops=", &sparc_align_loops_string }, \
521 {"align-jumps=", &sparc_align_jumps_string }, \
522 {"align-functions=", &sparc_align_funcs_string }, \
526 /* This is meant to be redefined in target specific files. */
527 #define SUBTARGET_OPTIONS
529 /* sparc_select[0] is reserved for the default cpu. */
530 struct sparc_cpu_select
538 extern struct sparc_cpu_select sparc_select[];
540 /* Variables to record values the user passes. */
541 extern char *sparc_align_loops_string;
542 extern char *sparc_align_jumps_string;
543 extern char *sparc_align_funcs_string;
544 /* Parsed values as a power of two. */
545 extern int sparc_align_loops;
546 extern int sparc_align_jumps;
547 extern int sparc_align_funcs;
549 #define DEFAULT_SPARC_ALIGN_FUNCS \
550 (sparc_cpu == PROCESSOR_ULTRASPARC ? 5 : 2)
552 /* target machine storage layout */
554 /* Define for cross-compilation to a sparc target with no TFmode from a host
555 with a different float format (e.g. VAX). */
556 #define REAL_ARITHMETIC
558 /* Define this if most significant bit is lowest numbered
559 in instructions that operate on numbered bit-fields. */
560 #define BITS_BIG_ENDIAN 1
562 /* Define this if most significant byte of a word is the lowest numbered. */
563 #define BYTES_BIG_ENDIAN 1
565 /* Define this if most significant word of a multiword number is the lowest
567 #define WORDS_BIG_ENDIAN 1
569 /* Define this to set the endianness to use in libgcc2.c, which can
570 not depend on target_flags. */
571 #if defined (__LITTLE_ENDIAN__)
572 #define LIBGCC2_WORDS_BIG_ENDIAN 0
574 #define LIBGCC2_WORDS_BIG_ENDIAN 1
577 /* number of bits in an addressable storage unit */
578 #define BITS_PER_UNIT 8
580 /* Width in bits of a "word", which is the contents of a machine register.
581 Note that this is not necessarily the width of data type `int';
582 if using 16-bit ints on a 68000, this would still be 32.
583 But on a machine with 16-bit registers, this would be 16. */
584 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
585 #define MAX_BITS_PER_WORD 64
587 /* Width of a word, in units (bytes). */
588 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
589 #define MIN_UNITS_PER_WORD 4
591 /* Now define the sizes of the C data types. */
593 #define SHORT_TYPE_SIZE 16
594 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
595 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
596 #define LONG_LONG_TYPE_SIZE 64
597 #define FLOAT_TYPE_SIZE 32
598 #define DOUBLE_TYPE_SIZE 64
600 #define MAX_INT_TYPE_SIZE 64
601 #define MAX_LONG_TYPE_SIZE 64
604 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
605 Instead, it is enabled in sol2.h, because it does work under Solaris. */
606 /* Define for support of TFmode long double and REAL_ARITHMETIC.
607 Sparc ABI says that long double is 4 words. */
608 #define LONG_DOUBLE_TYPE_SIZE 128
611 /* Width in bits of a pointer.
612 See also the macro `Pmode' defined below. */
613 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
615 /* A macro to update MODE and UNSIGNEDP when an object whose type
616 is TYPE and which has the specified mode and signedness is to be
617 stored in a register. This macro is only called when TYPE is a
619 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
621 && GET_MODE_CLASS (MODE) == MODE_INT \
622 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
627 /* Define this macro if the promotion described by PROMOTE_MODE
628 should also be done for outgoing function arguments. */
629 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
630 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
632 #define PROMOTE_FUNCTION_ARGS
634 /* Define this macro if the promotion described by PROMOTE_MODE
635 should also be done for the return value of functions.
636 If this macro is defined, FUNCTION_VALUE must perform the same
637 promotions done by PROMOTE_MODE. */
638 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
639 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
641 #define PROMOTE_FUNCTION_RETURN
643 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
644 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
646 /* Boundary (in *bits*) on which stack pointer should be aligned. */
647 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
649 /* ALIGN FRAMES on double word boundaries */
651 #define SPARC_STACK_ALIGN(LOC) \
652 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
654 /* Allocation boundary (in *bits*) for the code of a function. */
655 #define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3))
657 /* Alignment of field after `int : 0' in a structure. */
658 /* ??? Should this be based on TARGET_INT64? */
659 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
661 /* Every structure's size must be a multiple of this. */
662 #define STRUCTURE_SIZE_BOUNDARY 8
664 /* A bitfield declared as `int' forces `int' alignment for the struct. */
665 #define PCC_BITFIELD_TYPE_MATTERS 1
667 /* No data type wants to be aligned rounder than this. */
668 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
670 /* The best alignment to use in cases where we have a choice. */
671 #define FASTEST_ALIGNMENT 64
673 /* Make strings word-aligned so strcpy from constants will be faster. */
674 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
675 ((TREE_CODE (EXP) == STRING_CST \
676 && (ALIGN) < FASTEST_ALIGNMENT) \
677 ? FASTEST_ALIGNMENT : (ALIGN))
679 /* Make arrays of chars word-aligned for the same reasons. */
680 #define DATA_ALIGNMENT(TYPE, ALIGN) \
681 (TREE_CODE (TYPE) == ARRAY_TYPE \
682 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
683 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
685 /* Set this nonzero if move instructions will actually fail to work
686 when given unaligned data. */
687 #define STRICT_ALIGNMENT 1
689 /* Things that must be doubleword aligned cannot go in the text section,
690 because the linker fails to align the text section enough!
691 Put them in the data section. This macro is only used in this file. */
692 #define MAX_TEXT_ALIGN 32
694 /* This forces all variables and constants to the data section when PIC.
695 This is because the SunOS 4 shared library scheme thinks everything in
696 text is a function, and patches the address to point to a loader stub. */
697 /* This is defined to zero for every system which doesn't use the a.out object
699 #ifndef SUNOS4_SHARED_LIBRARIES
700 #define SUNOS4_SHARED_LIBRARIES 0
703 /* This is defined differently for v9 in a cover file. */
704 #define SELECT_SECTION(T,RELOC) \
706 if (TREE_CODE (T) == VAR_DECL) \
708 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
709 && DECL_INITIAL (T) \
710 && (DECL_INITIAL (T) == error_mark_node \
711 || TREE_CONSTANT (DECL_INITIAL (T))) \
712 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
713 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
718 else if (TREE_CODE (T) == CONSTRUCTOR) \
720 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
723 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
725 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
726 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
727 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
734 /* Use text section for a constant
735 unless we need more alignment than that offers. */
736 /* This is defined differently for v9 in a cover file. */
737 #define SELECT_RTX_SECTION(MODE, X) \
739 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
740 && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \
746 /* Standard register usage. */
748 /* Number of actual hardware registers.
749 The hardware registers are assigned numbers for the compiler
750 from 0 to just below FIRST_PSEUDO_REGISTER.
751 All registers that the compiler knows about must be given numbers,
752 even those that are not normally considered general registers.
754 SPARC has 32 integer registers and 32 floating point registers.
755 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
756 accessible. We still account for them to simplify register computations
757 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
759 Register 100 is used as the integer condition code register. */
761 #define FIRST_PSEUDO_REGISTER 101
763 #define SPARC_FIRST_FP_REG 32
764 /* Additional V9 fp regs. */
765 #define SPARC_FIRST_V9_FP_REG 64
766 #define SPARC_LAST_V9_FP_REG 95
767 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
768 #define SPARC_FIRST_V9_FCC_REG 96
769 #define SPARC_LAST_V9_FCC_REG 99
771 #define SPARC_FCC_REG 96
772 /* Integer CC reg. We don't distinguish %icc from %xcc. */
773 #define SPARC_ICC_REG 100
775 /* Nonzero if REGNO is an fp reg. */
776 #define SPARC_FP_REG_P(REGNO) \
777 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
779 /* Argument passing regs. */
780 #define SPARC_OUTGOING_INT_ARG_FIRST 8
781 #define SPARC_INCOMING_INT_ARG_FIRST 24
782 #define SPARC_FP_ARG_FIRST 32
784 /* 1 for registers that have pervasive standard uses
785 and are not available for the register allocator.
788 g1 is free to use as temporary.
789 g2-g4 are reserved for applications. Gcc normally uses them as
790 temporaries, but this can be disabled via the -mno-app-regs option.
791 g5 through g7 are reserved for the operating system.
794 g1,g4,g5 are free to use as temporaries.
795 g1,g5 are free to use between calls if call is to external function via PLT.
796 g2-g3 are reserved for applications. Gcc normally uses them as
797 temporaries, but this can be disabled via the -mno-app-regs option.
798 g6-g7 are reserved for the operating system.
799 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
800 currently be a fixed register until this pattern is rewritten.
801 Register 1 is also used when restoring call-preserved registers in large
804 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
805 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
808 #define FIXED_REGISTERS \
809 {1, 0, 0, 0, 0, 0, 1, 1, \
810 0, 0, 0, 0, 0, 0, 1, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 1, 1, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 0, \
817 0, 0, 0, 0, 0, 0, 0, 0, \
819 0, 0, 0, 0, 0, 0, 0, 0, \
820 0, 0, 0, 0, 0, 0, 0, 0, \
821 0, 0, 0, 0, 0, 0, 0, 0, \
822 0, 0, 0, 0, 0, 0, 0, 0, \
826 /* 1 for registers not available across function calls.
827 These must include the FIXED_REGISTERS and also any
828 registers that can be used without being saved.
829 The latter must include the registers where values are returned
830 and the register where structure-value addresses are passed.
831 Aside from that, you can include as many other registers as you like. */
833 #define CALL_USED_REGISTERS \
834 {1, 1, 1, 1, 1, 1, 1, 1, \
835 1, 1, 1, 1, 1, 1, 1, 1, \
836 0, 0, 0, 0, 0, 0, 0, 0, \
837 0, 0, 0, 0, 0, 0, 1, 1, \
839 1, 1, 1, 1, 1, 1, 1, 1, \
840 1, 1, 1, 1, 1, 1, 1, 1, \
841 1, 1, 1, 1, 1, 1, 1, 1, \
842 1, 1, 1, 1, 1, 1, 1, 1, \
844 1, 1, 1, 1, 1, 1, 1, 1, \
845 1, 1, 1, 1, 1, 1, 1, 1, \
846 1, 1, 1, 1, 1, 1, 1, 1, \
847 1, 1, 1, 1, 1, 1, 1, 1, \
851 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
852 they won't be allocated. */
854 #define CONDITIONAL_REGISTER_USAGE \
857 if (! SPARC_ARCH64) \
868 for (regno = SPARC_FIRST_V9_FP_REG; \
869 regno <= SPARC_LAST_V9_FP_REG; \
871 fixed_regs[regno] = 1; \
872 /* %fcc0 is used by v8 and v9. */ \
873 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
874 regno <= SPARC_LAST_V9_FCC_REG; \
876 fixed_regs[regno] = 1; \
881 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
882 fixed_regs[regno] = 1; \
884 /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \
885 fixed_regs[2] |= ! TARGET_APP_REGS; \
886 fixed_regs[3] |= ! TARGET_APP_REGS; \
887 fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_MEDANY; \
890 /* Let the compiler believe the frame pointer is still \
891 %fp, but output it as %i7. */ \
892 fixed_regs[31] = 1; \
893 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
894 /* ??? This is a hack to disable leaf functions. */ \
895 global_regs[7] = 1; \
897 if (profile_block_flag) \
899 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
907 /* Return number of consecutive hard regs needed starting at reg REGNO
908 to hold something of mode MODE.
909 This is ordinarily the length in words of a value of mode MODE
910 but can be less for certain modes in special long registers.
912 On SPARC, ordinary registers hold 32 bits worth;
913 this means both integer and floating point registers.
914 On v9, integer regs hold 64 bits worth; floating point regs hold
915 32 bits worth (this includes the new fp regs as even the odd ones are
916 included in the hard register count). */
918 #define HARD_REGNO_NREGS(REGNO, MODE) \
921 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
922 : (GET_MODE_SIZE (MODE) + 3) / 4) \
923 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
925 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
926 See sparc.c for how we initialize this. */
927 extern int *hard_regno_mode_classes;
928 extern int sparc_mode_class[];
929 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
930 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
932 /* Value is 1 if it is a good idea to tie two pseudo registers
933 when one has mode MODE1 and one has mode MODE2.
934 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
935 for any hard reg, then this must be 0 for correct output.
937 For V9: SFmode can't be combined with other float modes, because they can't
938 be allocated to the %d registers. Also, DFmode won't fit in odd %f
939 registers, but SFmode will. */
940 #define MODES_TIEABLE_P(MODE1, MODE2) \
941 ((MODE1) == (MODE2) \
942 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
944 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
945 || (MODE1 != SFmode && MODE2 != SFmode)))))
947 /* Specify the registers used for certain standard purposes.
948 The values of these macros are register numbers. */
950 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
951 /* #define PC_REGNUM */
953 /* Register to use for pushing function arguments. */
954 #define STACK_POINTER_REGNUM 14
956 /* Actual top-of-stack address is 92/176 greater than the contents of the
957 stack pointer register for !v9/v9. That is:
958 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
959 address, and 6*4 bytes for the 6 register parameters.
960 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
962 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
964 /* The stack bias (amount by which the hardware register is offset by). */
965 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
967 /* Is stack biased? */
968 #define STACK_BIAS SPARC_STACK_BIAS
970 /* Base register for access to local variables of the function. */
971 #define FRAME_POINTER_REGNUM 30
974 /* Register that is used for the return address for the flat model. */
975 #define RETURN_ADDR_REGNUM 15
978 /* Value should be nonzero if functions must have frame pointers.
979 Zero means the frame pointer need not be set up (and parms
980 may be accessed via the stack pointer) in functions that seem suitable.
981 This is computed in `reload', in reload1.c.
982 Used in flow.c, global.c, and reload1.c.
984 Being a non-leaf function does not mean a frame pointer is needed in the
985 flat window model. However, the debugger won't be able to backtrace through
987 #define FRAME_POINTER_REQUIRED \
988 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
989 || !leaf_function_p ()) \
990 : ! (leaf_function_p () && only_leaf_regs_used ()))
992 /* C statement to store the difference between the frame pointer
993 and the stack pointer values immediately after the function prologue.
995 Note, we always pretend that this is a leaf function because if
996 it's not, there's no point in trying to eliminate the
997 frame pointer. If it is a leaf function, we guessed right! */
998 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
999 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1000 : compute_frame_size (get_frame_size (), 1)))
1002 /* Base register for access to arguments of the function. */
1003 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1005 /* Register in which static-chain is passed to a function. This must
1006 not be a register used by the prologue. */
1007 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1009 /* Register which holds offset table for position-independent
1012 #define PIC_OFFSET_TABLE_REGNUM 23
1014 #define INITIALIZE_PIC initialize_pic ()
1015 #define FINALIZE_PIC finalize_pic ()
1017 /* Sparc ABI says that quad-precision floats and all structures are returned
1019 For v9: unions <= 32 bytes in size are returned in int regs,
1020 structures up to 32 bytes are returned in int and fp regs.
1023 #define RETURN_IN_MEMORY(TYPE) \
1025 ? (TYPE_MODE (TYPE) == BLKmode \
1026 || TYPE_MODE (TYPE) == TFmode \
1027 || TYPE_MODE (TYPE) == TCmode) \
1028 : TYPE_MODE (TYPE) == BLKmode)
1030 /* Functions which return large structures get the address
1031 to place the wanted value at offset 64 from the frame.
1032 Must reserve 64 bytes for the in and local registers.
1033 v9: Functions which return large structures get the address to place the
1034 wanted value from an invisible first argument. */
1035 /* Used only in other #defines in this file. */
1036 #define STRUCT_VALUE_OFFSET 64
1038 #define STRUCT_VALUE \
1041 : gen_rtx (MEM, Pmode, \
1042 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
1043 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
1044 #define STRUCT_VALUE_INCOMING \
1047 : gen_rtx (MEM, Pmode, \
1048 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1049 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
1051 /* Define the classes of registers for register constraints in the
1052 machine description. Also define ranges of constants.
1054 One of the classes must always be named ALL_REGS and include all hard regs.
1055 If there is more than one class, another class must be named NO_REGS
1056 and contain no registers.
1058 The name GENERAL_REGS must be the name of a class (or an alias for
1059 another name such as ALL_REGS). This is the class of registers
1060 that is allowed by "g" or "r" in a register constraint.
1061 Also, registers outside this class are allocated only when
1062 instructions express preferences for them.
1064 The classes must be numbered in nondecreasing order; that is,
1065 a larger-numbered class must never be contained completely
1066 in a smaller-numbered class.
1068 For any two classes, it is very desirable that there be another
1069 class that represents their union. */
1071 /* The SPARC has various kinds of registers: general, floating point,
1072 and condition codes [well, it has others as well, but none that we
1073 care directly about].
1075 For v9 we must distinguish between the upper and lower floating point
1076 registers because the upper ones can't hold SFmode values.
1077 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1078 satisfying a group need for a class will also satisfy a single need for
1079 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1082 It is important that one class contains all the general and all the standard
1083 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1084 because reg_class_record() will bias the selection in favor of fp regs,
1085 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1086 because FP_REGS > GENERAL_REGS.
1088 It is also important that one class contain all the general and all the
1089 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1090 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1091 allocate_reload_reg() to bypass it causing an abort because the compiler
1092 thinks it doesn't have a spill reg when in fact it does.
1094 v9 also has 4 floating point condition code registers. Since we don't
1095 have a class that is the union of FPCC_REGS with either of the others,
1096 it is important that it appear first. Otherwise the compiler will die
1097 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1100 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1101 may try to use it to hold an SImode value. See register_operand.
1102 ??? Should %fcc[0123] be handled similarily?
1105 enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
1106 GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1107 ALL_REGS, LIM_REG_CLASSES };
1109 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1111 /* Give names of register classes as strings for dump file. */
1113 #define REG_CLASS_NAMES \
1114 { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \
1115 "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" }
1117 /* Define which registers fit in which classes.
1118 This is an initializer for a vector of HARD_REG_SET
1119 of length N_REG_CLASSES. */
1121 #define REG_CLASS_CONTENTS \
1122 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, \
1123 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1124 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1126 /* The same information, inverted:
1127 Return the class number of the smallest class containing
1128 reg number REGNO. This could be a conditional expression
1129 or could index an array. */
1131 extern enum reg_class sparc_regno_reg_class[];
1133 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1135 /* This is the order in which to allocate registers normally.
1137 We put %f0/%f1 last among the float registers, so as to make it more
1138 likely that a pseudo-register which dies in the float return register
1139 will get allocated to the float return register, thus saving a move
1140 instruction at the end of the function. */
1142 #define REG_ALLOC_ORDER \
1143 { 8, 9, 10, 11, 12, 13, 2, 3, \
1144 15, 16, 17, 18, 19, 20, 21, 22, \
1145 23, 24, 25, 26, 27, 28, 29, 31, \
1146 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1147 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1148 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1149 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1150 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1151 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1152 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1153 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1154 32, 33, /* %f0,%f1 */ \
1155 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1156 1, 4, 5, 6, 7, 0, 14, 30}
1158 /* This is the order in which to allocate registers for
1159 leaf functions. If all registers can fit in the "i" registers,
1160 then we have the possibility of having a leaf function. */
1162 #define REG_LEAF_ALLOC_ORDER \
1163 { 2, 3, 24, 25, 26, 27, 28, 29, \
1164 15, 8, 9, 10, 11, 12, 13, \
1165 16, 17, 18, 19, 20, 21, 22, 23, \
1166 34, 35, 36, 37, 38, 39, \
1167 40, 41, 42, 43, 44, 45, 46, 47, \
1168 48, 49, 50, 51, 52, 53, 54, 55, \
1169 56, 57, 58, 59, 60, 61, 62, 63, \
1170 64, 65, 66, 67, 68, 69, 70, 71, \
1171 72, 73, 74, 75, 76, 77, 78, 79, \
1172 80, 81, 82, 83, 84, 85, 86, 87, \
1173 88, 89, 90, 91, 92, 93, 94, 95, \
1175 96, 97, 98, 99, 100, \
1176 1, 4, 5, 6, 7, 0, 14, 30, 31}
1178 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1180 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
1181 -mflat is used. Function only_leaf_regs_used will return 0 if a global
1182 register is used and is not permitted in a leaf function. We make %g7
1183 a global reg if -mflat and voila. Since %g7 is a system register and is
1184 fixed it won't be used by gcc anyway. */
1186 #define LEAF_REGISTERS \
1187 { 1, 1, 1, 1, 1, 1, 1, 0, \
1188 0, 0, 0, 0, 0, 0, 1, 0, \
1189 0, 0, 0, 0, 0, 0, 0, 0, \
1190 1, 1, 1, 1, 1, 1, 0, 1, \
1191 1, 1, 1, 1, 1, 1, 1, 1, \
1192 1, 1, 1, 1, 1, 1, 1, 1, \
1193 1, 1, 1, 1, 1, 1, 1, 1, \
1194 1, 1, 1, 1, 1, 1, 1, 1, \
1195 1, 1, 1, 1, 1, 1, 1, 1, \
1196 1, 1, 1, 1, 1, 1, 1, 1, \
1197 1, 1, 1, 1, 1, 1, 1, 1, \
1198 1, 1, 1, 1, 1, 1, 1, 1, \
1201 extern char leaf_reg_remap[];
1202 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1204 /* The class value for index registers, and the one for base regs. */
1205 #define INDEX_REG_CLASS GENERAL_REGS
1206 #define BASE_REG_CLASS GENERAL_REGS
1208 /* Local macro to handle the two v9 classes of FP regs. */
1209 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1211 /* Get reg_class from a letter such as appears in the machine description.
1212 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1213 .md file for v8 and v9. */
1215 #define REG_CLASS_FROM_LETTER(C) \
1217 ? ((C) == 'f' ? FP_REGS \
1218 : (C) == 'e' ? EXTRA_FP_REGS \
1219 : (C) == 'c' ? FPCC_REGS \
1221 : ((C) == 'f' ? FP_REGS \
1222 : (C) == 'e' ? FP_REGS \
1223 : (C) == 'c' ? FPCC_REGS \
1226 /* The letters I, J, K, L and M in a register constraint string
1227 can be used to stand for particular ranges of immediate operands.
1228 This macro defines what the ranges are.
1229 C is the letter, and VALUE is a constant value.
1230 Return 1 if VALUE is in the range specified by C.
1232 `I' is used for the range of constants an insn can actually contain.
1233 `J' is used for the range which is just zero (since that is R0).
1234 `K' is used for constants which can be loaded with a single sethi insn.
1235 `L' is used for the range of constants supported by the movcc insns.
1236 `M' is used for the range of constants supported by the movrcc insns. */
1238 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1239 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1240 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1241 /* 10 and 11 bit immediates are only used for a few specific insns.
1242 SMALL_INT is used throughout the port so we continue to use it. */
1243 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1244 #define SPARC_SETHI_P(X) \
1245 (((unsigned HOST_WIDE_INT) (X) & ~(unsigned HOST_WIDE_INT) 0xfffffc00) == 0)
1247 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1248 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1249 : (C) == 'J' ? (VALUE) == 0 \
1250 : (C) == 'K' ? SPARC_SETHI_P (VALUE) \
1251 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1252 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1255 /* Similar, but for floating constants, and defining letters G and H.
1256 Here VALUE is the CONST_DOUBLE rtx itself. */
1258 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1259 ((C) == 'G' ? fp_zero_operand (VALUE) \
1260 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1263 /* Given an rtx X being reloaded into a reg required to be
1264 in class CLASS, return the class of reg to actually use.
1265 In general this is just CLASS; but on some machines
1266 in some cases it is preferable to use a more restrictive class. */
1267 /* We can't load constants into FP registers. We can't load any FP constant
1268 if an 'E' constraint fails to match it. */
1269 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1271 && (FP_REG_CLASS_P (CLASS) \
1272 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1273 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1274 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1275 ? NO_REGS : (CLASS))
1277 /* Return the register class of a scratch register needed to load IN into
1278 a register of class CLASS in MODE.
1280 On the SPARC, when PIC, we need a temporary when loading some addresses
1283 Also, we need a temporary when loading/storing a HImode/QImode value
1284 between memory and the FPU registers. This can happen when combine puts
1285 a paradoxical subreg in a float/fix conversion insn. */
1287 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1288 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1289 && (GET_CODE (IN) == MEM \
1290 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1291 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1293 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1294 ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \
1295 && (GET_CODE (IN) == MEM \
1296 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1297 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1299 /* On SPARC it is not possible to directly move data between
1300 GENERAL_REGS and FP_REGS. */
1301 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1302 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1304 /* Return the stack location to use for secondary memory needed reloads.
1305 We want to use the reserved location just below the frame pointer.
1306 However, we must ensure that there is a frame, so use assign_stack_local
1307 if the frame size is zero. */
1308 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1309 (get_frame_size () == 0 \
1310 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1311 : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1312 GEN_INT (STARTING_FRAME_OFFSET))))
1314 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1315 because the movsi and movsf patterns don't handle r/f moves.
1316 For v8 we copy the default definition. */
1317 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1319 ? (GET_MODE_BITSIZE (MODE) < 32 \
1320 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1322 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1323 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1326 /* Return the maximum number of consecutive registers
1327 needed to represent mode MODE in a register of class CLASS. */
1328 /* On SPARC, this is the size of MODE in words. */
1329 #define CLASS_MAX_NREGS(CLASS, MODE) \
1330 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1331 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1333 /* Stack layout; function entry, exit and calling. */
1335 /* Define the number of register that can hold parameters.
1336 This macro is only used in other macro definitions below and in sparc.c.
1337 MODE is the mode of the argument.
1338 !v9: All args are passed in %o0-%o5.
1339 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1340 See the description in sparc.c. */
1341 #define NPARM_REGS(MODE) \
1343 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1346 /* Define this if pushing a word on the stack
1347 makes the stack pointer a smaller address. */
1348 #define STACK_GROWS_DOWNWARD
1350 /* Define this if the nominal address of the stack frame
1351 is at the high-address end of the local variables;
1352 that is, each additional local variable allocated
1353 goes at a more negative offset in the frame. */
1354 #define FRAME_GROWS_DOWNWARD
1356 /* Offset within stack frame to start allocating local variables at.
1357 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1358 first local allocated. Otherwise, it is the offset to the BEGINNING
1359 of the first local allocated. */
1360 /* This allows space for one TFmode floating point value. */
1361 #define STARTING_FRAME_OFFSET \
1362 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1363 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1365 /* If we generate an insn to push BYTES bytes,
1366 this says how many the stack pointer really advances by.
1367 On SPARC, don't define this because there are no push insns. */
1368 /* #define PUSH_ROUNDING(BYTES) */
1370 /* Offset of first parameter from the argument pointer register value.
1371 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1372 even if this function isn't going to use it.
1373 v9: This is 128 for the ins and locals. */
1374 #define FIRST_PARM_OFFSET(FNDECL) \
1375 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
1376 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1378 /* When a parameter is passed in a register, stack space is still
1379 allocated for it. */
1380 /* This only takes into account the int regs.
1381 fp regs are handled elsewhere. */
1382 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1384 /* Keep the stack pointer constant throughout the function.
1385 This is both an optimization and a necessity: longjmp
1386 doesn't behave itself when the stack pointer moves within
1388 #define ACCUMULATE_OUTGOING_ARGS
1390 /* Value is the number of bytes of arguments automatically
1391 popped when returning from a subroutine call.
1392 FUNDECL is the declaration node of the function (as a tree),
1393 FUNTYPE is the data type of the function (as a tree),
1394 or for a library call it is an identifier node for the subroutine name.
1395 SIZE is the number of bytes of arguments passed on the stack. */
1397 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1399 /* Some subroutine macros specific to this machine.
1400 When !TARGET_FPU, put float return values in the general registers,
1401 since we don't have any fp registers. */
1402 #define BASE_RETURN_VALUE_REG(MODE) \
1404 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1405 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1406 #define BASE_OUTGOING_VALUE_REG(MODE) \
1408 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1409 : TARGET_FLAT ? 8 : 24) \
1410 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1411 : (TARGET_FLAT ? 8 : 24)))
1412 #define BASE_PASSING_ARG_REG(MODE) \
1414 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1416 #define BASE_INCOMING_ARG_REG(MODE) \
1418 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1419 : TARGET_FLAT ? 8 : 24) \
1420 : (TARGET_FLAT ? 8 : 24))
1422 /* Define this macro if the target machine has "register windows". This
1423 C expression returns the register number as seen by the called function
1424 corresponding to register number OUT as seen by the calling function.
1425 Return OUT if register number OUT is not an outbound register. */
1427 #define INCOMING_REGNO(OUT) \
1428 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1430 /* Define this macro if the target machine has "register windows". This
1431 C expression returns the register number as seen by the calling function
1432 corresponding to register number IN as seen by the called function.
1433 Return IN if register number IN is not an inbound register. */
1435 #define OUTGOING_REGNO(IN) \
1436 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1438 /* Define how to find the value returned by a function.
1439 VALTYPE is the data type of the value (as a tree).
1440 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1441 otherwise, FUNC is 0. */
1443 /* On SPARC the value is found in the first "output" register. */
1445 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1446 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1448 /* But the called function leaves it in the first "input" register. */
1450 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1451 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1453 /* Define how to find the value returned by a library function
1454 assuming the value has mode MODE. */
1456 #define LIBCALL_VALUE(MODE) \
1457 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1459 /* 1 if N is a possible register number for a function value
1460 as seen by the caller.
1461 On SPARC, the first "output" reg is used for integer values,
1462 and the first floating point register is used for floating point values. */
1464 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1466 /* Define the size of space to allocate for the return value of an
1469 #define APPLY_RESULT_SIZE 16
1471 /* 1 if N is a possible register number for function argument passing.
1472 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1474 #define FUNCTION_ARG_REGNO_P(N) \
1476 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1477 : ((N) >= 8 && (N) <= 13))
1479 /* Define a data type for recording info about an argument list
1480 during the scan of that argument list. This data type should
1481 hold all necessary information about the function itself
1482 and about the args processed so far, enough to enable macros
1483 such as FUNCTION_ARG to determine where the next arg should go.
1485 On SPARC (!v9), this is a single integer, which is a number of words
1486 of arguments scanned so far (including the invisible argument,
1487 if any, which holds the structure-value-address).
1488 Thus 7 or more means all following args should go on the stack.
1490 For v9, we also need to know whether a prototype is present. */
1493 int words; /* number of words passed so far */
1494 int prototype_p; /* non-zero if a prototype is present */
1495 int libcall_p; /* non-zero if a library call */
1497 #define CUMULATIVE_ARGS struct sparc_args
1499 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1500 for a call to a function whose data type is FNTYPE.
1501 For a library call, FNTYPE is 0. */
1503 extern void init_cumulative_args ();
1504 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1505 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1507 /* Update the data in CUM to advance over an argument
1508 of mode MODE and data type TYPE.
1509 TYPE is null for libcalls where that information may not be available. */
1511 extern void function_arg_advance ();
1512 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1513 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1515 /* Determine where to put an argument to a function.
1516 Value is zero to push the argument on the stack,
1517 or a hard register in which to store the argument.
1519 MODE is the argument's machine mode.
1520 TYPE is the data type of the argument (as a tree).
1521 This is null for libcalls where that information may
1523 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1524 the preceding args and about the function being called.
1525 NAMED is nonzero if this argument is a named parameter
1526 (otherwise it is an extra parameter matching an ellipsis). */
1528 extern struct rtx_def *function_arg ();
1529 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1530 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1532 /* Define where a function finds its arguments.
1533 This is different from FUNCTION_ARG because of register windows. */
1535 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1536 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1538 /* For an arg passed partly in registers and partly in memory,
1539 this is the number of registers used.
1540 For args passed entirely in registers or entirely in memory, zero. */
1542 extern int function_arg_partial_nregs ();
1543 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1544 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1546 /* A C expression that indicates when an argument must be passed by reference.
1547 If nonzero for an argument, a copy of that argument is made in memory and a
1548 pointer to the argument is passed instead of the argument itself.
1549 The pointer is passed in whatever way is appropriate for passing a pointer
1552 extern int function_arg_pass_by_reference ();
1553 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1554 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1556 /* If defined, a C expression which determines whether, and in which direction,
1557 to pad out an argument with extra space. The value should be of type
1558 `enum direction': either `upward' to pad above the argument,
1559 `downward' to pad below, or `none' to inhibit padding. */
1560 extern enum direction function_arg_padding ();
1561 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1562 function_arg_padding ((MODE), (TYPE))
1564 /* If defined, a C expression that gives the alignment boundary, in bits,
1565 of an argument with the specified mode and type. If it is not defined,
1566 PARM_BOUNDARY is used for all arguments.
1567 For sparc64, objects requiring 16 byte alignment are passed that way. */
1569 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1571 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1572 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1573 ? 128 : PARM_BOUNDARY)
1575 /* Initialize data used by insn expanders. This is called from
1576 init_emit, once for each function, before code is generated.
1577 For v9, clear the temp slot used by float/int DImode conversions.
1578 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1579 space at some point.
1580 ??? Use assign_stack_temp? */
1582 extern void sparc64_init_expanders ();
1583 extern struct rtx_def *sparc64_fpconv_stack_temp ();
1585 #define INIT_EXPANDERS sparc64_init_expanders ()
1588 /* Define the information needed to generate branch and scc insns. This is
1589 stored from the compare operation. Note that we can't use "rtx" here
1590 since it hasn't been defined! */
1592 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1594 /* Define the function that build the compare insn for scc and bcc. */
1596 extern struct rtx_def *gen_compare_reg ();
1598 /* This function handles all v9 scc insns */
1600 extern int gen_v9_scc ();
1602 /* Generate the special assembly code needed to tell the assembler whatever
1603 it might need to know about the return value of a function.
1605 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1606 information to the assembler relating to peephole optimization (done in
1609 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1610 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1612 /* Output the label for a function definition. */
1614 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1616 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1617 ASM_OUTPUT_LABEL (FILE, NAME); \
1620 /* This macro generates the assembly code for function entry.
1621 FILE is a stdio stream to output the code to.
1622 SIZE is an int: how many units of temporary storage to allocate.
1623 Refer to the array `regs_ever_live' to determine which registers
1624 to save; `regs_ever_live[I]' is nonzero if register number I
1625 is ever used in the function. This macro is responsible for
1626 knowing which registers should not be saved even if used. */
1628 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1629 of memory. If any fpu reg is used in the function, we allocate
1630 such a block here, at the bottom of the frame, just in case it's needed.
1632 If this function is a leaf procedure, then we may choose not
1633 to do a "save" insn. The decision about whether or not
1634 to do this is made in regclass.c. */
1636 extern int leaf_function;
1637 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1638 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, SIZE) \
1639 : output_function_prologue (FILE, SIZE, leaf_function))
1641 /* Output assembler code to FILE to increment profiler label # LABELNO
1642 for profiling a function entry.
1644 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
1645 during profiling so we need to save/restore it around the call to mcount.
1646 We're guaranteed that a save has just been done, and we use the space
1647 allocated for intreg/fpreg value passing. */
1649 #define FUNCTION_PROFILER(FILE, LABELNO) \
1652 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", (LABELNO)); \
1653 if (! TARGET_ARCH64) \
1654 fputs ("\tst %g2,[%fp-4]\n", FILE); \
1655 fputs ("\tsethi %hi(", FILE); \
1656 assemble_name (FILE, buf); \
1657 fputs ("),%o0\n", FILE); \
1658 if (TARGET_MEDANY) \
1659 fprintf (FILE, "\tadd %o0,%s,%o0\n", MEDANY_BASE_REG); \
1660 fputs ("\tcall mcount\n\tadd %o0,%lo(", FILE); \
1661 assemble_name (FILE, buf); \
1662 fputs ("),%o0\n", FILE); \
1663 if (! TARGET_ARCH64) \
1664 fputs ("\tld [%fp-4],%g2\n", FILE); \
1667 /* There are three profiling modes for basic blocks available.
1668 The modes are selected at compile time by using the options
1669 -a or -ax of the gnu compiler.
1670 The variable `profile_block_flag' will be set according to the
1673 profile_block_flag == 0, no option used:
1677 profile_block_flag == 1, -a option used.
1679 Count frequency of execution of every basic block.
1681 profile_block_flag == 2, -ax option used.
1683 Generate code to allow several different profiling modes at run time.
1684 Available modes are:
1685 Produce a trace of all basic blocks.
1686 Count frequency of jump instructions executed.
1687 In every mode it is possible to start profiling upon entering
1688 certain functions and to disable profiling of some other functions.
1690 The result of basic-block profiling will be written to a file `bb.out'.
1691 If the -ax option is used parameters for the profiling will be read
1696 /* The following macro shall output assembler code to FILE
1697 to initialize basic-block profiling.
1699 If profile_block_flag == 2
1701 Output code to call the subroutine `__bb_init_trace_func'
1702 and pass two parameters to it. The first parameter is
1703 the address of a block allocated in the object module.
1704 The second parameter is the number of the first basic block
1707 The name of the block is a local symbol made with this statement:
1709 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1711 Of course, since you are writing the definition of
1712 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1713 can take a short cut in the definition of this macro and use the
1714 name that you know will result.
1716 The number of the first basic block of the function is
1717 passed to the macro in BLOCK_OR_LABEL.
1719 If described in a virtual assembler language the code to be
1723 parameter2 <- BLOCK_OR_LABEL
1724 call __bb_init_trace_func
1726 else if profile_block_flag != 0
1728 Output code to call the subroutine `__bb_init_func'
1729 and pass one single parameter to it, which is the same
1730 as the first parameter to `__bb_init_trace_func'.
1732 The first word of this parameter is a flag which will be nonzero if
1733 the object module has already been initialized. So test this word
1734 first, and do not call `__bb_init_func' if the flag is nonzero.
1735 Note: When profile_block_flag == 2 the test need not be done
1736 but `__bb_init_trace_func' *must* be called.
1738 BLOCK_OR_LABEL may be used to generate a label number as a
1739 branch destination in case `__bb_init_func' will not be called.
1741 If described in a virtual assembler language the code to be
1752 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1755 int bol = (BLOCK_OR_LABEL); \
1756 switch (profile_block_flag) \
1759 if (TARGET_MEDANY) \
1760 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tadd %%o0,%s,%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tadd %g0,%%lo(%d),%%o1\n",\
1761 MEDANY_BASE_REG, bol, bol); \
1763 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
1767 if (TARGET_MEDANY) \
1768 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1769 MEDANY_BASE_REG, bol, MEDANY_BASE_REG, bol);\
1771 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
1778 /* The following macro shall output assembler code to FILE
1779 to increment a counter associated with basic block number BLOCKNO.
1781 If profile_block_flag == 2
1783 Output code to initialize the global structure `__bb' and
1784 call the function `__bb_trace_func' which will increment the
1787 `__bb' consists of two words. In the first word the number
1788 of the basic block has to be stored. In the second word
1789 the address of a block allocated in the object module
1792 The basic block number is given by BLOCKNO.
1794 The address of the block is given by the label created with
1796 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
1798 by FUNCTION_BLOCK_PROFILER.
1800 Of course, since you are writing the definition of
1801 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1802 can take a short cut in the definition of this macro and use the
1803 name that you know will result.
1805 If described in a virtual assembler language the code to be
1808 move BLOCKNO -> (__bb)
1809 move LPBX0 -> (__bb+4)
1810 call __bb_trace_func
1812 Note that function `__bb_trace_func' must not change the
1813 machine state, especially the flag register. To grant
1814 this, you must output code to save and restore registers
1815 either in this macro or in the macros MACHINE_STATE_SAVE
1816 and MACHINE_STATE_RESTORE. The last two macros will be
1817 used in the function `__bb_trace_func', so you must make
1818 sure that the function prologue does not change any
1819 register prior to saving it with MACHINE_STATE_SAVE.
1821 else if profile_block_flag != 0
1823 Output code to increment the counter directly.
1824 Basic blocks are numbered separately from zero within each
1825 compiled object module. The count associated with block number
1826 BLOCKNO is at index BLOCKNO in an array of words; the name of
1827 this array is a local symbol made with this statement:
1829 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
1831 Of course, since you are writing the definition of
1832 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
1833 can take a short cut in the definition of this macro and use the
1834 name that you know will result.
1836 If described in a virtual assembler language, the code to be
1839 inc (LPBX2+4*BLOCKNO)
1843 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1846 int blockn = (BLOCKNO); \
1847 switch (profile_block_flag) \
1850 if (TARGET_MEDANY) \
1851 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tor %%0,%%lo(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%s+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%0,%%lo(LPBX0),%%g2\n\tadd %%g2,%s,%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%g1+%%lo(___bb)]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1852 blockn, blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1854 fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
1858 if (TARGET_MEDANY) \
1859 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1860 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1862 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1863 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1864 4 * blockn, 4 * blockn, 4 * blockn); \
1870 /* The following macro shall output assembler code to FILE
1871 to indicate a return from function during basic-block profiling.
1873 If profiling_block_flag == 2:
1875 Output assembler code to call function `__bb_trace_ret'.
1877 Note that function `__bb_trace_ret' must not change the
1878 machine state, especially the flag register. To grant
1879 this, you must output code to save and restore registers
1880 either in this macro or in the macros MACHINE_STATE_SAVE_RET
1881 and MACHINE_STATE_RESTORE_RET. The last two macros will be
1882 used in the function `__bb_trace_ret', so you must make
1883 sure that the function prologue does not change any
1884 register prior to saving it with MACHINE_STATE_SAVE_RET.
1886 else if profiling_block_flag != 0:
1888 The macro will not be used, so it need not distinguish
1892 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1893 fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
1895 /* The function `__bb_trace_func' is called in every basic block
1896 and is not allowed to change the machine state. Saving (restoring)
1897 the state can either be done in the BLOCK_PROFILER macro,
1898 before calling function (rsp. after returning from function)
1899 `__bb_trace_func', or it can be done inside the function by
1900 defining the macros:
1902 MACHINE_STATE_SAVE(ID)
1903 MACHINE_STATE_RESTORE(ID)
1905 In the latter case care must be taken, that the prologue code
1906 of function `__bb_trace_func' does not already change the
1907 state prior to saving it with MACHINE_STATE_SAVE.
1909 The parameter `ID' is a string identifying a unique macro use.
1911 On sparc it is sufficient to save the psw register to memory.
1912 Unfortunately the psw register can be read in supervisor mode only,
1913 so we read only the condition codes by using branch instructions
1914 and hope that this is enough. */
1916 #define MACHINE_STATE_SAVE(ID) \
1917 asm (" mov %g0,%l0");\
1918 asm (" be,a LFLGNZ" ID);\
1919 asm (" or %l0,4,%l0");\
1920 asm ("LFLGNZ" ID ": bcs,a LFLGNC" ID);\
1921 asm (" or %l0,1,%l0");\
1922 asm ("LFLGNC" ID ": bvs,a LFLGNV" ID);\
1923 asm (" or %l0,2,%l0");\
1924 asm ("LFLGNV" ID ": bneg,a LFLGNN" ID);\
1925 asm (" or %l0,8,%l0");\
1926 asm ("LFLGNN" ID ": sethi %hi(LFLAGS" ID "),%l1");\
1927 asm (" st %l0,[%l1+%lo(LFLAGS" ID ")]"); \
1928 asm (" st %g2,[%l1+%lo(LSAVRET" ID ")]");
1930 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1931 The psw register can be written in supervisor mode only,
1932 which is true even for simple condition codes.
1933 We use some combination of instructions to produce the
1934 proper condition codes, but some flag combinations can not
1935 be generated in this way. If this happens an unimplemented
1936 instruction will be executed to abort the program. */
1938 #define MACHINE_STATE_RESTORE(ID) \
1939 asm (" sethi %hi(LFLGTAB" ID "),%l1");\
1940 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LFLAGS" ID "))],%l0");\
1941 asm (" ld [%l1+%lo(LFLGTAB" ID "-(LFLGTAB" ID "-LSAVRET" ID "))],%g2");\
1942 asm (" sll %l0,2,%l0");\
1943 asm (" add %l0,%l1,%l0");\
1944 asm (" ld [%l0+%lo(LFLGTAB" ID ")],%l1");\
1949 asm ("LFLAGS" ID ":");\
1951 asm ("LSAVRET" ID ":");\
1953 asm ("LFLGTAB" ID ": ");\
1954 asm (" .word LSFLG0" ID);\
1955 asm (" .word LSFLGC" ID);\
1956 asm (" .word LSFLGV" ID);\
1957 asm (" .word LSFLGVC" ID);\
1958 asm (" .word LSFLGZ" ID);\
1959 asm (" .word LSFLGZC" ID);\
1960 asm (" .word LSFLGZV" ID);\
1961 asm (" .word LSFLGZVC" ID);\
1962 asm (" .word LSFLGN" ID);\
1963 asm (" .word LSFLGNC" ID);\
1964 asm (" .word LSFLGNV" ID);\
1965 asm (" .word LSFLGNVC" ID);\
1966 asm (" .word LSFLGNZ" ID);\
1967 asm (" .word LSFLGNZC" ID);\
1968 asm (" .word LSFLGNZV" ID);\
1969 asm (" .word LSFLGNZVC" ID);\
1971 asm ("LSFLGVC" ID ": mov -1,%l0");\
1972 asm (" addcc 2,%l0,%g0");\
1973 asm (" sethi %hi(0x80000000),%l0");\
1974 asm (" mov %l0,%l1");\
1975 asm (" ba LFLGRET" ID);\
1976 asm (" addxcc %l0,%l1,%l0");\
1977 asm ("LSFLGC" ID ": mov -1,%l0");\
1978 asm (" ba LFLGRET" ID);\
1979 asm (" addcc 2,%l0,%g0");\
1980 asm ("LSFLGZC" ID ": mov -1,%l0");\
1981 asm (" ba LFLGRET" ID);\
1982 asm (" addcc 1,%l0,%l0");\
1983 asm ("LSFLGZVC" ID ": sethi %hi(0x80000000),%l0");\
1984 asm (" mov %l0,%l1");\
1985 asm (" ba LFLGRET" ID);\
1986 asm (" addcc %l0,%l1,%l0");\
1987 asm ("LSFLGZ" ID ": ba LFLGRET" ID);\
1988 asm (" subcc %g0,%g0,%g0");\
1989 asm ("LSFLGNC" ID ": add %g0,1,%l0");\
1990 asm (" ba LFLGRET" ID);\
1991 asm (" subcc %g0,%l0,%g0");\
1992 asm ("LSFLG0" ID ": ba LFLGRET" ID);\
1993 asm (" orcc 1,%g0,%g0");\
1994 asm ("LSFLGN" ID ": ba LFLGRET" ID);\
1995 asm (" orcc -1,%g0,%g0");\
1996 asm ("LSFLGV" ID ":");\
1997 asm ("LSFLGZV" ID ":");\
1998 asm ("LSFLGNV" ID ":");\
1999 asm ("LSFLGNVC" ID ":");\
2000 asm ("LSFLGNZ" ID ":");\
2001 asm ("LSFLGNZC" ID ":");\
2002 asm ("LSFLGNZV" ID ":");\
2003 asm ("LSFLGNZVC" ID ":");\
2005 asm ("LFLGRET" ID ":");
2007 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2008 the stack pointer does not matter. The value is tested only in
2009 functions that have frame pointers.
2010 No definition is equivalent to always zero. */
2012 extern int current_function_calls_alloca;
2013 extern int current_function_outgoing_args_size;
2015 #define EXIT_IGNORE_STACK \
2016 (get_frame_size () != 0 \
2017 || current_function_calls_alloca || current_function_outgoing_args_size)
2019 /* This macro generates the assembly code for function exit,
2020 on machines that need it. If FUNCTION_EPILOGUE is not defined
2021 then individual return instructions are generated for each
2022 return statement. Args are same as for FUNCTION_PROLOGUE.
2024 The function epilogue should not depend on the current stack pointer!
2025 It should use the frame pointer only. This is mandatory because
2026 of alloca; we also take advantage of it to omit stack adjustments
2027 before returning. */
2029 /* This declaration is needed due to traditional/ANSI
2030 incompatibilities which cannot be #ifdefed away
2031 because they occur inside of macros. Sigh. */
2032 extern union tree_node *current_function_decl;
2034 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2035 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, SIZE) \
2036 : output_function_epilogue (FILE, SIZE, leaf_function))
2038 #define DELAY_SLOTS_FOR_EPILOGUE \
2039 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2040 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2041 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2042 : eligible_for_epilogue_delay (trial, slots_filled))
2044 /* Define registers used by the epilogue and return instruction. */
2045 #define EPILOGUE_USES(REGNO) \
2046 (!TARGET_FLAT && REGNO == 31)
2048 /* Output assembler code for a block containing the constant parts
2049 of a trampoline, leaving space for the variable parts. */
2051 /* On 32 bit sparcs, the trampoline contains five instructions:
2052 sethi #TOP_OF_FUNCTION,%g1
2053 or #BOTTOM_OF_FUNCTION,%g1,%g1
2054 sethi #TOP_OF_STATIC,%g2
2056 or #BOTTOM_OF_STATIC,%g2,%g2
2058 On 64 bit sparcs, the trampoline contains 4 insns and two pseudo-immediate
2059 constants (plus some padding):
2068 /* ??? Stack is execute-protected in v9. */
2070 #define TRAMPOLINE_TEMPLATE(FILE) \
2072 if (TARGET_ARCH64) \
2074 fprintf (FILE, "\trd %%pc,%%g1\n"); \
2075 fprintf (FILE, "\tldx [%%g1+24],%%g5\n"); \
2076 fprintf (FILE, "\tldx [%%g1+32],%%g1\n"); \
2077 fprintf (FILE, "\tjmp %%g1\n"); \
2078 fprintf (FILE, "\tnop\n"); \
2079 fprintf (FILE, "\tnop\n"); \
2080 /* -mmedlow shouldn't generate .xwords, so don't use them at all */ \
2081 fprintf (FILE, "\t.word 0,0,0,0\n"); \
2085 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2086 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2087 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2088 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
2089 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
2093 /* Length in units of the trampoline for entering a nested function. */
2095 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 40 : 20)
2097 /* Emit RTL insns to initialize the variable parts of a trampoline.
2098 FNADDR is an RTX for the address of the function's pure code.
2099 CXT is an RTX for the static chain value for the function. */
2101 void sparc_initialize_trampoline ();
2102 void sparc64_initialize_trampoline ();
2103 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2105 if (TARGET_ARCH64) \
2106 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2108 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
2111 /* Generate necessary RTL for __builtin_saveregs().
2112 ARGLIST is the argument list; see expr.c. */
2114 extern struct rtx_def *sparc_builtin_saveregs ();
2115 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
2117 /* Define this macro if the location where a function argument is passed
2118 depends on whether or not it is a named argument.
2120 This macro controls how the NAMED argument to FUNCTION_ARG
2121 is set for varargs and stdarg functions. With this macro defined,
2122 the NAMED argument is always true for named arguments, and false for
2123 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
2124 is defined, then all arguments are treated as named. Otherwise, all named
2125 arguments except the last are treated as named.
2126 For the v9 we want NAMED to mean what it says it means. */
2127 /* ??? This needn't be set for v8, but I don't want to make this runtime
2128 selectable if I don't have to. */
2129 #define STRICT_ARGUMENT_NAMING
2131 /* Generate RTL to flush the register windows so as to make arbitrary frames
2133 #define SETUP_FRAME_ADDRESSES() \
2134 emit_insn (gen_flush_register_windows ())
2136 /* Given an rtx for the address of a frame,
2137 return an rtx for the address of the word in the frame
2138 that holds the dynamic chain--the previous frame's address.
2139 ??? -mflat support? */
2140 #define DYNAMIC_CHAIN_ADDRESS(frame) \
2141 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
2143 /* The return address isn't on the stack, it is in a register, so we can't
2144 access it from the current frame pointer. We can access it from the
2145 previous frame pointer though by reading a value from the register window
2147 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2149 /* This is the offset of the return address to the true next instruction to be
2150 executed for the current function. */
2151 #define RETURN_ADDR_OFFSET \
2152 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2154 /* The current return address is in %i7. The return address of anything
2155 farther back is in the register window save area at [%fp+60]. */
2156 /* ??? This ignores the fact that the actual return address is +8 for normal
2157 returns, and +12 for structure returns. */
2158 #define RETURN_ADDR_RTX(count, frame) \
2160 ? gen_rtx (REG, Pmode, 31) \
2161 : gen_rtx (MEM, Pmode, \
2162 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
2164 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
2165 +12, but always using +8 is close enough for frame unwind purposes.
2166 Actually, just using %o7 is close enough for unwinding, but %o7+8
2167 is something you can return to. */
2168 #define INCOMING_RETURN_ADDR_RTX \
2169 gen_rtx (PLUS, word_mode, gen_rtx (REG, word_mode, 15), GEN_INT (8))
2171 /* The offset from the incoming value of %sp to the top of the stack frame
2172 for the current function. On sparc64, we have to account for the stack
2174 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
2176 #define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
2178 /* Addressing modes, and classification of registers for them. */
2180 /* #define HAVE_POST_INCREMENT */
2181 /* #define HAVE_POST_DECREMENT */
2183 /* #define HAVE_PRE_DECREMENT */
2184 /* #define HAVE_PRE_INCREMENT */
2186 /* Macros to check register numbers against specific register classes. */
2188 /* These assume that REGNO is a hard or pseudo reg number.
2189 They give nonzero only if REGNO is a hard reg of the suitable class
2190 or a pseudo reg currently allocated to a suitable hard reg.
2191 Since they use reg_renumber, they are safe only once reg_renumber
2192 has been allocated, which happens in local-alloc.c. */
2194 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2195 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2196 #define REGNO_OK_FOR_BASE_P(REGNO) \
2197 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
2198 #define REGNO_OK_FOR_FP_P(REGNO) \
2199 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
2200 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
2201 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2203 && (((unsigned) (REGNO) - 96 < 4) \
2204 || ((unsigned) reg_renumber[REGNO] - 96 < 4)))
2206 /* Now macros that check whether X is a register and also,
2207 strictly, whether it is in a specified class.
2209 These macros are specific to the SPARC, and may be used only
2210 in code for printing assembler insns and in conditions for
2211 define_optimization. */
2213 /* 1 if X is an fp register. */
2215 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2217 /* Maximum number of registers that can appear in a valid memory address. */
2219 #define MAX_REGS_PER_ADDRESS 2
2221 /* Recognize any constant value that is a valid address.
2222 When PIC, we do not accept an address that would require a scratch reg
2223 to load into a register. */
2225 #define CONSTANT_ADDRESS_P(X) \
2226 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2227 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2228 || (GET_CODE (X) == CONST \
2229 && ! (flag_pic && pic_address_needs_scratch (X))))
2231 /* Define this, so that when PIC, reload won't try to reload invalid
2232 addresses which require two reload registers. */
2234 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2236 /* Nonzero if the constant value X is a legitimate general operand.
2237 Anything can be made to work except floating point constants. */
2239 #define LEGITIMATE_CONSTANT_P(X) \
2240 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
2242 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2243 and check its validity for a certain class.
2244 We have two alternate definitions for each of them.
2245 The usual definition accepts all pseudo regs; the other rejects
2246 them unless they have been allocated suitable hard regs.
2247 The symbol REG_OK_STRICT causes the latter definition to be used.
2249 Most source files want to accept pseudo regs in the hope that
2250 they will get allocated to the class that the insn wants them to be in.
2251 Source files for reload pass need to be strict.
2252 After reload, it makes no difference, since pseudo regs have
2253 been eliminated by then. */
2255 /* Optional extra constraints for this machine. Borrowed from romp.h.
2257 For the SPARC, `Q' means that this is a memory operand but not a
2258 symbolic memory operand. Note that an unassigned pseudo register
2259 is such a memory operand. Needed because reload will generate
2260 these things in insns and then not re-recognize the insns, causing
2261 constrain_operands to fail.
2263 `S' handles constraints for calls. ??? So where is it? */
2265 #ifndef REG_OK_STRICT
2267 /* Nonzero if X is a hard reg that can be used as an index
2268 or if it is a pseudo reg. */
2269 #define REG_OK_FOR_INDEX_P(X) \
2270 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2271 /* Nonzero if X is a hard reg that can be used as a base reg
2272 or if it is a pseudo reg. */
2273 #define REG_OK_FOR_BASE_P(X) \
2274 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2276 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
2278 #define EXTRA_CONSTRAINT(OP, C) \
2280 ? ((GET_CODE (OP) == MEM \
2281 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
2282 && ! symbolic_memory_operand (OP, VOIDmode)) \
2283 || (reload_in_progress && GET_CODE (OP) == REG \
2284 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
2285 : (! TARGET_ARCH64 && (C) == 'T') \
2286 ? (mem_aligned_8 (OP)) \
2287 : (! TARGET_ARCH64 && (C) == 'U') \
2288 ? (register_ok_for_ldd (OP)) \
2293 /* Nonzero if X is a hard reg that can be used as an index. */
2294 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2295 /* Nonzero if X is a hard reg that can be used as a base reg. */
2296 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2298 #define EXTRA_CONSTRAINT(OP, C) \
2300 ? (GET_CODE (OP) == REG \
2301 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
2302 && reg_renumber[REGNO (OP)] < 0) \
2303 : GET_CODE (OP) == MEM) \
2304 : (! TARGET_ARCH64 && (C) == 'T') \
2305 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2306 : (! TARGET_ARCH64 && (C) == 'U') \
2307 ? (GET_CODE (OP) == REG \
2308 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2309 || reg_renumber[REGNO (OP)] >= 0) \
2310 && register_ok_for_ldd (OP)) \
2314 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2315 that is a valid memory address for an instruction.
2316 The MODE argument is the machine mode for the MEM expression
2317 that wants to use this address.
2319 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2320 ordinarily. This changes a bit when generating PIC.
2322 If you change this, execute "rm explow.o recog.o reload.o". */
2324 #define RTX_OK_FOR_BASE_P(X) \
2325 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2326 || (GET_CODE (X) == SUBREG \
2327 && GET_CODE (SUBREG_REG (X)) == REG \
2328 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2330 #define RTX_OK_FOR_INDEX_P(X) \
2331 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2332 || (GET_CODE (X) == SUBREG \
2333 && GET_CODE (SUBREG_REG (X)) == REG \
2334 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2336 #define RTX_OK_FOR_OFFSET_P(X) \
2337 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
2339 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2340 { if (RTX_OK_FOR_BASE_P (X)) \
2342 else if (GET_CODE (X) == PLUS) \
2344 register rtx op0 = XEXP (X, 0); \
2345 register rtx op1 = XEXP (X, 1); \
2346 if (flag_pic && op0 == pic_offset_table_rtx) \
2348 if (RTX_OK_FOR_BASE_P (op1)) \
2350 else if (flag_pic == 1 \
2351 && GET_CODE (op1) != REG \
2352 && GET_CODE (op1) != LO_SUM \
2353 && GET_CODE (op1) != MEM \
2354 && (GET_CODE (op1) != CONST_INT \
2355 || SMALL_INT (op1))) \
2358 else if (RTX_OK_FOR_BASE_P (op0)) \
2360 if (RTX_OK_FOR_INDEX_P (op1) \
2361 || RTX_OK_FOR_OFFSET_P (op1)) \
2364 else if (RTX_OK_FOR_BASE_P (op1)) \
2366 if (RTX_OK_FOR_INDEX_P (op0) \
2367 || RTX_OK_FOR_OFFSET_P (op0)) \
2371 else if (GET_CODE (X) == LO_SUM) \
2373 register rtx op0 = XEXP (X, 0); \
2374 register rtx op1 = XEXP (X, 1); \
2375 if (RTX_OK_FOR_BASE_P (op0) \
2376 && CONSTANT_P (op1) \
2377 /* We can't allow TFmode, because an offset \
2378 greater than or equal to the alignment (8) \
2379 may cause the LO_SUM to overflow. */ \
2380 && MODE != TFmode) \
2383 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2387 /* Try machine-dependent ways of modifying an illegitimate address
2388 to be legitimate. If we find one, return the new, valid address.
2389 This macro is used in only one place: `memory_address' in explow.c.
2391 OLDX is the address as it was before break_out_memory_refs was called.
2392 In some cases it is useful to look at this to decide what needs to be done.
2394 MODE and WIN are passed so that this macro can use
2395 GO_IF_LEGITIMATE_ADDRESS.
2397 It is always safe for this macro to do nothing. It exists to recognize
2398 opportunities to optimize the output. */
2400 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2401 extern struct rtx_def *legitimize_pic_address ();
2402 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2403 { rtx sparc_x = (X); \
2404 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2405 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2406 force_operand (XEXP (X, 0), NULL_RTX)); \
2407 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2408 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2409 force_operand (XEXP (X, 1), NULL_RTX)); \
2410 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2411 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2413 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2414 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2415 force_operand (XEXP (X, 1), NULL_RTX)); \
2416 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2418 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2419 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2420 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2421 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2422 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2423 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
2424 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2425 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2426 || GET_CODE (X) == LABEL_REF) \
2427 (X) = gen_rtx (LO_SUM, Pmode, \
2428 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2429 if (memory_address_p (MODE, X)) \
2432 /* Go to LABEL if ADDR (a legitimate address expression)
2433 has an effect that depends on the machine mode it is used for.
2434 On the SPARC this is never true. */
2436 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2438 /* If we are referencing a function make the SYMBOL_REF special.
2439 In the Medium/Anywhere code model, %g4 points to the data segment so we
2440 must not add it to function addresses. */
2442 #define ENCODE_SECTION_INFO(DECL) \
2444 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2445 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2448 /* Specify the machine mode that this machine uses
2449 for the index in the tablejump instruction. */
2450 #define CASE_VECTOR_MODE Pmode
2452 /* Define this if the tablejump instruction expects the table
2453 to contain offsets from the address of the table.
2454 Do not define this if the table should contain absolute addresses. */
2455 /* #define CASE_VECTOR_PC_RELATIVE */
2457 /* Specify the tree operation to be used to convert reals to integers. */
2458 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2460 /* This is the kind of divide that is easiest to do in the general case. */
2461 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2463 /* Define this as 1 if `char' should by default be signed; else as 0. */
2464 #define DEFAULT_SIGNED_CHAR 1
2466 /* Max number of bytes we can move from memory to memory
2467 in one reasonably fast instruction. */
2470 #if 0 /* Sun 4 has matherr, so this is no good. */
2471 /* This is the value of the error code EDOM for this machine,
2472 used by the sqrt instruction. */
2473 #define TARGET_EDOM 33
2475 /* This is how to refer to the variable errno. */
2476 #define GEN_ERRNO_RTX \
2477 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
2480 /* Define if operations between registers always perform the operation
2481 on the full register even if a narrower mode is specified. */
2482 #define WORD_REGISTER_OPERATIONS
2484 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2485 will either zero-extend or sign-extend. The value of this macro should
2486 be the code that says which one of the two operations is implicitly
2487 done, NIL if none. */
2488 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2490 /* Nonzero if access to memory by bytes is slow and undesirable.
2491 For RISC chips, it means that access to memory by bytes is no
2492 better than access by words when possible, so grab a whole word
2493 and maybe make use of that. */
2494 #define SLOW_BYTE_ACCESS 1
2496 /* We assume that the store-condition-codes instructions store 0 for false
2497 and some other value for true. This is the value stored for true. */
2499 #define STORE_FLAG_VALUE 1
2501 /* When a prototype says `char' or `short', really pass an `int'. */
2502 #define PROMOTE_PROTOTYPES
2504 /* Define this to be nonzero if shift instructions ignore all but the low-order
2506 #define SHIFT_COUNT_TRUNCATED 1
2508 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2509 is done just by pretending it is already truncated. */
2510 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2512 /* Specify the machine mode that pointers have.
2513 After generation of rtl, the compiler makes no further distinction
2514 between pointers and any other objects of this machine mode. */
2515 #define Pmode (TARGET_PTR64 ? DImode : SImode)
2517 /* Generate calls to memcpy, memcmp and memset. */
2518 #define TARGET_MEM_FUNCTIONS
2520 /* Add any extra modes needed to represent the condition code.
2522 On the Sparc, we have a "no-overflow" mode which is used when an add or
2523 subtract insn is used to set the condition code. Different branches are
2524 used in this case for some operations.
2526 We also have two modes to indicate that the relevant condition code is
2527 in the floating-point condition code register. One for comparisons which
2528 will generate an exception if the result is unordered (CCFPEmode) and
2529 one for comparisons which will never trap (CCFPmode).
2531 CCXmode and CCX_NOOVmode are only used by v9. */
2533 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2535 /* Define the names for the modes specified above. */
2537 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2539 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2540 return the mode to be used for the comparison. For floating-point,
2541 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2542 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2543 processing is needed. */
2544 #define SELECT_CC_MODE(OP,X,Y) \
2545 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2546 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2547 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2548 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2549 ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2550 : (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2552 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2553 floating point inequality comparison. */
2555 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2557 /* A function address in a call instruction
2558 is a byte address (for indexing purposes)
2559 so give the MEM rtx a byte's mode. */
2560 #define FUNCTION_MODE SImode
2562 /* Define this if addresses of constant functions
2563 shouldn't be put through pseudo regs where they can be cse'd.
2564 Desirable on machines where ordinary constants are expensive
2565 but a CALL with constant address is cheap. */
2566 #define NO_FUNCTION_CSE
2568 /* alloca should avoid clobbering the old register save area. */
2569 #define SETJMP_VIA_SAVE_AREA
2571 /* Define subroutines to call to handle multiply and divide.
2572 Use the subroutines that Sun's library provides.
2573 The `*' prevents an underscore from being prepended by the compiler. */
2575 #define DIVSI3_LIBCALL "*.div"
2576 #define UDIVSI3_LIBCALL "*.udiv"
2577 #define MODSI3_LIBCALL "*.rem"
2578 #define UMODSI3_LIBCALL "*.urem"
2579 /* .umul is a little faster than .mul. */
2580 #define MULSI3_LIBCALL "*.umul"
2582 /* Define library calls for quad FP operations. These are all part of the
2584 #define ADDTF3_LIBCALL "_Q_add"
2585 #define SUBTF3_LIBCALL "_Q_sub"
2586 #define NEGTF2_LIBCALL "_Q_neg"
2587 #define MULTF3_LIBCALL "_Q_mul"
2588 #define DIVTF3_LIBCALL "_Q_div"
2589 #define FLOATSITF2_LIBCALL "_Q_itoq"
2590 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2591 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2592 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2593 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2594 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2595 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2596 #define EQTF2_LIBCALL "_Q_feq"
2597 #define NETF2_LIBCALL "_Q_fne"
2598 #define GTTF2_LIBCALL "_Q_fgt"
2599 #define GETF2_LIBCALL "_Q_fge"
2600 #define LTTF2_LIBCALL "_Q_flt"
2601 #define LETF2_LIBCALL "_Q_fle"
2603 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2604 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2605 and the compiler will notice and try to use the TFmode sqrt instruction
2606 for calls to the builtin function sqrt, but this fails. */
2607 #define INIT_TARGET_OPTABS \
2609 add_optab->handlers[(int) TFmode].libfunc \
2610 = gen_rtx (SYMBOL_REF, Pmode, ADDTF3_LIBCALL); \
2611 sub_optab->handlers[(int) TFmode].libfunc \
2612 = gen_rtx (SYMBOL_REF, Pmode, SUBTF3_LIBCALL); \
2613 neg_optab->handlers[(int) TFmode].libfunc \
2614 = gen_rtx (SYMBOL_REF, Pmode, NEGTF2_LIBCALL); \
2615 smul_optab->handlers[(int) TFmode].libfunc \
2616 = gen_rtx (SYMBOL_REF, Pmode, MULTF3_LIBCALL); \
2617 flodiv_optab->handlers[(int) TFmode].libfunc \
2618 = gen_rtx (SYMBOL_REF, Pmode, DIVTF3_LIBCALL); \
2619 eqtf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EQTF2_LIBCALL); \
2620 netf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, NETF2_LIBCALL); \
2621 gttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GTTF2_LIBCALL); \
2622 getf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, GETF2_LIBCALL); \
2623 lttf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LTTF2_LIBCALL); \
2624 letf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, LETF2_LIBCALL); \
2625 trunctfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFSF2_LIBCALL); \
2626 trunctfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, TRUNCTFDF2_LIBCALL); \
2627 extendsftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDSFTF2_LIBCALL); \
2628 extenddftf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, EXTENDDFTF2_LIBCALL); \
2629 floatsitf_libfunc = gen_rtx (SYMBOL_REF, Pmode, FLOATSITF2_LIBCALL); \
2630 fixtfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, FIX_TRUNCTFSI2_LIBCALL); \
2631 fixunstfsi_libfunc \
2632 = gen_rtx (SYMBOL_REF, Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \
2634 sqrt_optab->handlers[(int) TFmode].libfunc \
2635 = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \
2636 INIT_SUBTARGET_OPTABS; \
2639 /* This is meant to be redefined in the host dependent files */
2640 #define INIT_SUBTARGET_OPTABS
2642 /* Compute the cost of computing a constant rtl expression RTX
2643 whose rtx-code is CODE. The body of this macro is a portion
2644 of a switch statement. If the code is computed here,
2645 return it with a return statement. Otherwise, break from the switch. */
2647 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2649 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2657 case CONST_DOUBLE: \
2658 if (GET_MODE (RTX) == DImode) \
2659 if ((XINT (RTX, 3) == 0 \
2660 && (unsigned) XINT (RTX, 2) < 0x1000) \
2661 || (XINT (RTX, 3) == -1 \
2662 && XINT (RTX, 2) < 0 \
2663 && XINT (RTX, 2) >= -0x1000)) \
2667 /* Compute the cost of an address. For the sparc, all valid addresses are
2670 #define ADDRESS_COST(RTX) 1
2672 /* Compute extra cost of moving data between one register class
2674 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2675 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2676 (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \
2677 || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2)
2679 /* Provide the costs of a rtl expression. This is in the body of a
2680 switch on CODE. The purpose for the cost of MULT is to encourage
2681 `synth_mult' to find a synthetic multiply when reasonable.
2683 If we need more than 12 insns to do a multiply, then go out-of-line,
2684 since the call overhead will be < 10% of the cost of the multiply. */
2686 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2688 return (TARGET_V8 || TARGET_SPARCLITE) \
2689 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2694 return COSTS_N_INSNS (25); \
2695 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2696 so that cse will favor the latter. */ \
2701 /* Adjust the cost of dependencies. */
2702 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2703 if (sparc_cpu == PROCESSOR_SUPERSPARC) \
2704 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2706 /* Conditional branches with empty delay slots have a length of two. */
2707 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2708 if (GET_CODE (INSN) == CALL_INSN \
2709 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2712 /* Control the assembler format that we output. */
2714 /* Output at beginning of assembler file. */
2716 #define ASM_FILE_START(file)
2718 /* A C string constant describing how to begin a comment in the target
2719 assembler language. The compiler assumes that the comment will end at
2720 the end of the line. */
2722 #define ASM_COMMENT_START "!"
2724 /* Output to assembler file text saying following lines
2725 may contain character constants, extra white space, comments, etc. */
2727 #define ASM_APP_ON ""
2729 /* Output to assembler file text saying following lines
2730 no longer contain unusual constructs. */
2732 #define ASM_APP_OFF ""
2734 /* ??? Try to make the style consistent here (_OP?). */
2736 #define ASM_LONGLONG ".xword"
2737 #define ASM_LONG ".word"
2738 #define ASM_SHORT ".half"
2739 #define ASM_BYTE_OP ".byte"
2740 #define ASM_FLOAT ".single"
2741 #define ASM_DOUBLE ".double"
2742 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2744 /* Output before read-only data. */
2746 #define TEXT_SECTION_ASM_OP ".text"
2748 /* Output before writable data. */
2750 #define DATA_SECTION_ASM_OP ".data"
2752 /* How to refer to registers in assembler output.
2753 This sequence is indexed by compiler's hard-register-number (see above). */
2755 #define REGISTER_NAMES \
2756 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2757 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2758 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2759 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2760 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2761 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2762 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2763 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2764 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2765 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2766 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2767 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2768 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2770 /* Define additional names for use in asm clobbers and asm declarations. */
2772 #define ADDITIONAL_REGISTER_NAMES \
2773 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2775 /* How to renumber registers for dbx and gdb. In the flat model, the frame
2776 pointer is really %i7. */
2778 #define DBX_REGISTER_NUMBER(REGNO) \
2779 (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
2781 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2782 can run past this up to a continuation point. Once we used 1500, but
2783 a single entry in C++ can run more than 500 bytes, due to the length of
2784 mangled symbol names. dbxout.c should really be fixed to do
2785 continuations when they are actually needed instead of trying to
2787 #define DBX_CONTIN_LENGTH 1000
2789 /* This is how to output a note to DBX telling it the line number
2790 to which the following sequence of instructions corresponds.
2792 This is needed for SunOS 4.0, and should not hurt for 3.2
2794 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2795 { static int sym_lineno = 1; \
2796 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2797 line, sym_lineno, sym_lineno); \
2800 /* This is how to output the definition of a user-level label named NAME,
2801 such as the label on a static function or variable NAME. */
2803 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2804 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2806 /* This is how to output a command to make the user-level label named NAME
2807 defined for reference from other files. */
2809 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2810 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2812 /* The prefix to add to user-visible assembler symbols. */
2814 #define USER_LABEL_PREFIX "_"
2816 /* This is how to output a definition of an internal numbered label where
2817 PREFIX is the class of label and NUM is the number within the class. */
2819 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2820 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2822 /* This is how to store into the string LABEL
2823 the symbol_ref name of an internal numbered label where
2824 PREFIX is the class of label and NUM is the number within the class.
2825 This is suitable for output with `assemble_name'. */
2827 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2828 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2830 /* This is how to output an assembler line defining a `float' constant.
2831 We always have to use a .long pseudo-op to do this because the native
2832 SVR4 ELF assembler is buggy and it generates incorrect values when we
2833 try to use the .float pseudo-op instead. */
2835 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2839 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2840 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2841 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \
2842 ASM_COMMENT_START, str); \
2845 /* This is how to output an assembler line defining a `double' constant.
2846 We always have to use a .long pseudo-op to do this because the native
2847 SVR4 ELF assembler is buggy and it generates incorrect values when we
2848 try to use the .float pseudo-op instead. */
2850 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2854 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2855 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2856 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
2857 ASM_COMMENT_START, str); \
2858 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
2861 /* This is how to output an assembler line defining a `long double'
2864 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2868 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2869 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2870 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
2871 ASM_COMMENT_START, str); \
2872 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
2873 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \
2874 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \
2877 /* This is how to output an assembler line defining an `int' constant. */
2879 #define ASM_OUTPUT_INT(FILE,VALUE) \
2880 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2881 output_addr_const (FILE, (VALUE)), \
2882 fprintf (FILE, "\n"))
2884 /* This is how to output an assembler line defining a DImode constant. */
2885 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2886 output_double_int (FILE, VALUE)
2888 /* Likewise for `char' and `short' constants. */
2890 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2891 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2892 output_addr_const (FILE, (VALUE)), \
2893 fprintf (FILE, "\n"))
2895 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2896 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2897 output_addr_const (FILE, (VALUE)), \
2898 fprintf (FILE, "\n"))
2900 /* This is how to output an assembler line for a numeric constant byte. */
2902 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2903 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2905 /* This is how to output an element of a case-vector that is absolute. */
2907 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2910 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2911 if (Pmode == SImode) \
2912 fprintf (FILE, "\t.word\t"); \
2913 else if (TARGET_MEDLOW) \
2914 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2916 fprintf (FILE, "\t.xword\t"); \
2917 assemble_name (FILE, label); \
2918 fprintf (FILE, "\n"); \
2921 /* This is how to output an element of a case-vector that is relative.
2922 (SPARC uses such vectors only when generating PIC.) */
2924 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2927 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2928 if (Pmode == SImode) \
2929 fprintf (FILE, "\t.word\t"); \
2930 else if (TARGET_MEDLOW) \
2931 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2933 fprintf (FILE, "\t.xword\t"); \
2934 assemble_name (FILE, label); \
2935 fprintf (FILE, "-1b\n"); \
2938 /* This is how to output an assembler line
2939 that says to advance the location counter
2940 to a multiple of 2**LOG bytes. */
2942 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2944 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2946 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
2947 ASM_OUTPUT_ALIGN (FILE, sparc_align_jumps)
2949 #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
2950 ASM_OUTPUT_ALIGN (FILE, sparc_align_loops)
2952 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2953 fprintf (FILE, "\t.skip %u\n", (SIZE))
2955 /* This says how to output an assembler line
2956 to define a global common symbol. */
2958 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2959 ( fputs ("\t.common ", (FILE)), \
2960 assemble_name ((FILE), (NAME)), \
2961 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2963 /* This says how to output an assembler line to define a local common
2966 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2967 ( fputs ("\t.reserve ", (FILE)), \
2968 assemble_name ((FILE), (NAME)), \
2969 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2970 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2972 /* A C statement (sans semicolon) to output to the stdio stream
2973 FILE the assembler definition of uninitialized global DECL named
2974 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2975 Try to use asm_output_aligned_bss to implement this macro. */
2977 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2979 fputs (".globl ", (FILE)); \
2980 assemble_name ((FILE), (NAME)); \
2981 fputs ("\n", (FILE)); \
2982 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2985 /* Store in OUTPUT a string (made with alloca) containing
2986 an assembler-name for a local static variable named NAME.
2987 LABELNO is an integer which is different for each call. */
2989 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2990 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2991 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2993 #define IDENT_ASM_OP ".ident"
2995 /* Output #ident as a .ident. */
2997 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2998 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
3000 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
3001 Used for C++ multiple inheritance. */
3002 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
3004 int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \
3006 fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \
3010 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3011 fprintf (FILE, "\tsave %%sp,-112,%%sp\n"); \
3012 fprintf (FILE, "\tcall "); \
3014 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3015 fprintf (FILE, ",0\n"); \
3017 else if (TARGET_MEDANY || TARGET_FULLANY) \
3019 fprintf (FILE, "\tsetx "); \
3021 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3022 fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \
3026 fprintf (FILE, "\tsethi %%hi("); \
3028 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3029 fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \
3031 (FILE, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION))); \
3032 fprintf (FILE, ")\n"); \
3035 fprintf (FILE, "\tnop\n"); \
3036 else if (flag_pic) \
3037 fprintf (FILE, "\trestore\n"); \
3039 fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \
3042 /* Define the parentheses used to group arithmetic operations
3043 in assembler code. */
3045 #define ASM_OPEN_PAREN "("
3046 #define ASM_CLOSE_PAREN ")"
3048 /* Define results of standard character escape sequences. */
3049 #define TARGET_BELL 007
3050 #define TARGET_BS 010
3051 #define TARGET_TAB 011
3052 #define TARGET_NEWLINE 012
3053 #define TARGET_VT 013
3054 #define TARGET_FF 014
3055 #define TARGET_CR 015
3057 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3058 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
3060 /* Print operand X (an rtx) in assembler syntax to file FILE.
3061 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3062 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3064 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3066 /* Print a memory address as an operand to reference that memory location. */
3068 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3069 { register rtx base, index = 0; \
3071 register rtx addr = ADDR; \
3072 if (GET_CODE (addr) == REG) \
3073 fputs (reg_names[REGNO (addr)], FILE); \
3074 else if (GET_CODE (addr) == PLUS) \
3076 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
3077 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
3078 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
3079 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
3081 base = XEXP (addr, 0), index = XEXP (addr, 1); \
3082 fputs (reg_names[REGNO (base)], FILE); \
3084 fprintf (FILE, "%+d", offset); \
3085 else if (GET_CODE (index) == REG) \
3086 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3087 else if (GET_CODE (index) == SYMBOL_REF \
3088 || GET_CODE (index) == CONST) \
3089 fputc ('+', FILE), output_addr_const (FILE, index); \
3092 else if (GET_CODE (addr) == MINUS \
3093 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3095 output_addr_const (FILE, XEXP (addr, 0)); \
3096 fputs ("-(", FILE); \
3097 output_addr_const (FILE, XEXP (addr, 1)); \
3098 fputs ("-.)", FILE); \
3100 else if (GET_CODE (addr) == LO_SUM) \
3102 output_operand (XEXP (addr, 0), 0); \
3103 fputs ("+%lo(", FILE); \
3104 output_address (XEXP (addr, 1)); \
3105 fputc (')', FILE); \
3107 else if (flag_pic && GET_CODE (addr) == CONST \
3108 && GET_CODE (XEXP (addr, 0)) == MINUS \
3109 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3110 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3111 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3113 addr = XEXP (addr, 0); \
3114 output_addr_const (FILE, XEXP (addr, 0)); \
3115 /* Group the args of the second CONST in parenthesis. */ \
3116 fputs ("-(", FILE); \
3117 /* Skip past the second CONST--it does nothing for us. */\
3118 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3119 /* Close the parenthesis. */ \
3120 fputc (')', FILE); \
3124 output_addr_const (FILE, addr); \
3128 /* The number of Pmode words for the setjmp buffer. */
3129 #define JMP_BUF_SIZE 12
3131 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
3133 /* Declare functions defined in sparc.c and used in templates. */
3135 extern char *singlemove_string ();
3136 extern char *doublemove_string ();
3137 extern char *output_move_double ();
3138 extern char *output_move_quad ();
3139 extern char *output_fp_move_double ();
3140 extern char *output_fp_move_quad ();
3141 extern char *output_block_move ();
3142 extern char *output_scc_insn ();
3143 extern char *output_cbranch ();
3144 extern char *output_v9branch ();
3145 extern char *output_return ();
3147 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3149 extern int flag_pic;
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