1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Define macros to distinguish architectures. */
215 /* Common CPP definitions used by CPP_SPEC amongst the various targets
216 for handling -mcpu=xxx switches. */
217 #define CPP_CPU_SPEC "\
218 %{msoft-float:-D_SOFT_FLOAT} \
220 %{msparclite:-D__sparclite__} \
221 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
222 %{mv8:-D__sparc_v8__} \
223 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
224 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
225 %{mcpu=sparclite:-D__sparclite__} \
226 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
227 %{mcpu=v8:-D__sparc_v8__} \
228 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
229 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclite86x:-D__sparclite86x__} \
231 %{mcpu=v9:-D__sparc_v9__} \
232 %{mcpu=ultrasparc:-D__sparc_v9__} \
233 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
236 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
237 the right varags.h file when bootstrapping. */
238 /* ??? It's not clear what value we want to use for -Acpu/machine for
239 sparc64 in 32 bit environments, so for now we only use `sparc64' in
240 64 bit environments. */
244 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
245 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
246 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
247 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
251 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
252 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
256 #define CPP_ARCH_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
259 #define CPP_ARCH_SPEC "\
260 %{m32:%(cpp_arch32)} \
261 %{m64:%(cpp_arch64)} \
262 %{!m32:%{!m64:%(cpp_arch_default)}} \
265 /* Macros to distinguish endianness. */
266 #define CPP_ENDIAN_SPEC "\
267 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
268 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
270 /* Macros to distinguish the particular subtarget. */
271 #define CPP_SUBTARGET_SPEC ""
273 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
275 /* Prevent error on `-sun4' and `-target sun4' options. */
276 /* This used to translate -dalign to -malign, but that is no good
277 because it can't turn off the usual meaning of making debugging dumps. */
278 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
279 ??? Delete support for -m<cpu> for 2.9. */
282 %{sun4:} %{target:} \
283 %{mcypress:-mcpu=cypress} \
284 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
285 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
288 /* Override in target specific files. */
289 #define ASM_CPU_SPEC "\
290 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
291 %{msparclite:-Asparclite} \
292 %{mf930:-Asparclite} %{mf934:-Asparclite} \
293 %{mcpu=sparclite:-Asparclite} \
294 %{mcpu=sparclite86x:-Asparclite} \
295 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
296 %{mv8plus:-Av8plus} \
298 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
299 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
302 /* Word size selection, among other things.
303 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
305 #define ASM_ARCH32_SPEC "-32"
306 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
307 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
309 #define ASM_ARCH64_SPEC "-64"
311 #define ASM_ARCH_DEFAULT_SPEC \
312 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
314 #define ASM_ARCH_SPEC "\
315 %{m32:%(asm_arch32)} \
316 %{m64:%(asm_arch64)} \
317 %{!m32:%{!m64:%(asm_arch_default)}} \
320 #ifdef HAVE_AS_RELAX_OPTION
321 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
323 #define ASM_RELAX_SPEC ""
326 /* Special flags to the Sun-4 assembler when using pipe for input. */
329 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
330 %(asm_cpu) %(asm_relax)"
332 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
334 /* Provide required defaults for linker -e and -d switches. */
337 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
338 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
340 /* This macro defines names of additional specifications to put in the specs
341 that can be used in various specifications like CC1_SPEC. Its definition
342 is an initializer with a subgrouping for each command option.
344 Each subgrouping contains a string constant, that defines the
345 specification name, and a string constant that used by the GNU CC driver
348 Do not define this macro if it does not need to do anything. */
350 #define EXTRA_SPECS \
351 { "cpp_cpu", CPP_CPU_SPEC }, \
352 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
353 { "cpp_arch32", CPP_ARCH32_SPEC }, \
354 { "cpp_arch64", CPP_ARCH64_SPEC }, \
355 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
356 { "cpp_arch", CPP_ARCH_SPEC }, \
357 { "cpp_endian", CPP_ENDIAN_SPEC }, \
358 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
359 { "asm_cpu", ASM_CPU_SPEC }, \
360 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
361 { "asm_arch32", ASM_ARCH32_SPEC }, \
362 { "asm_arch64", ASM_ARCH64_SPEC }, \
363 { "asm_relax", ASM_RELAX_SPEC }, \
364 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
365 { "asm_arch", ASM_ARCH_SPEC }, \
366 SUBTARGET_EXTRA_SPECS
368 #define SUBTARGET_EXTRA_SPECS
371 #define NO_BUILTIN_PTRDIFF_TYPE
372 #define NO_BUILTIN_SIZE_TYPE
374 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
375 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
377 /* ??? This should be 32 bits for v9 but what can we do? */
378 #define WCHAR_TYPE "short unsigned int"
379 #define WCHAR_TYPE_SIZE 16
380 #define MAX_WCHAR_TYPE_SIZE 16
382 /* Show we can debug even without a frame pointer. */
383 #define CAN_DEBUG_WITHOUT_FP
385 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
386 code into the rtl. Also, if we are profiling, we cannot eliminate
387 the frame pointer (because the return address will get smashed). */
389 #define OVERRIDE_OPTIONS \
391 if (profile_flag || profile_block_flag || profile_arc_flag) \
395 const char *const pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
396 warning ("%s and profiling conflict: disabling %s", \
397 pic_string, pic_string); \
400 flag_omit_frame_pointer = 0; \
402 sparc_override_options (); \
403 SUBTARGET_OVERRIDE_OPTIONS; \
406 /* This is meant to be redefined in the host dependent files. */
407 #define SUBTARGET_OVERRIDE_OPTIONS
409 /* Generate DBX debugging information. */
411 #define DBX_DEBUGGING_INFO
413 /* Run-time compilation parameters selecting different hardware subsets. */
415 extern int target_flags;
417 /* Nonzero if we should generate code to use the fpu. */
419 #define TARGET_FPU (target_flags & MASK_FPU)
421 /* Nonzero if we should use function_epilogue(). Otherwise, we
422 use fast return insns, but lose some generality. */
423 #define MASK_EPILOGUE 2
424 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
426 /* Nonzero if we should assume that double pointers might be unaligned.
427 This can happen when linking gcc compiled code with other compilers,
428 because the ABI only guarantees 4 byte alignment. */
429 #define MASK_UNALIGNED_DOUBLES 4
430 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
432 /* Nonzero means that we should generate code for a v8 sparc. */
434 #define TARGET_V8 (target_flags & MASK_V8)
436 /* Nonzero means that we should generate code for a sparclite.
437 This enables the sparclite specific instructions, but does not affect
438 whether FPU instructions are emitted. */
439 #define MASK_SPARCLITE 0x10
440 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
442 /* Nonzero if we're compiling for the sparclet. */
443 #define MASK_SPARCLET 0x20
444 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
446 /* Nonzero if we're compiling for v9 sparc.
447 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
448 the word size is 64. */
450 #define TARGET_V9 (target_flags & MASK_V9)
452 /* Non-zero to generate code that uses the instructions deprecated in
453 the v9 architecture. This option only applies to v9 systems. */
454 /* ??? This isn't user selectable yet. It's used to enable such insns
455 on 32 bit v9 systems and for the moment they're permanently disabled
456 on 64 bit v9 systems. */
457 #define MASK_DEPRECATED_V8_INSNS 0x80
458 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
460 /* Mask of all CPU selection flags. */
462 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
464 /* Non-zero means don't pass `-assert pure-text' to the linker. */
465 #define MASK_IMPURE_TEXT 0x100
466 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
468 /* Nonzero means that we should generate code using a flat register window
469 model, i.e. no save/restore instructions are generated, which is
470 compatible with normal sparc code.
471 The frame pointer is %i7 instead of %fp. */
472 #define MASK_FLAT 0x200
473 #define TARGET_FLAT (target_flags & MASK_FLAT)
475 /* Nonzero means use the registers that the Sparc ABI reserves for
476 application software. This must be the default to coincide with the
477 setting in FIXED_REGISTERS. */
478 #define MASK_APP_REGS 0x400
479 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
481 /* Option to select how quad word floating point is implemented.
482 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
483 Otherwise, we use the SPARC ABI quad library functions. */
484 #define MASK_HARD_QUAD 0x800
485 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
487 /* Non-zero on little-endian machines. */
488 /* ??? Little endian support currently only exists for sparclet-aout and
489 sparc64-elf configurations. May eventually want to expand the support
490 to all targets, but for now it's kept local to only those two. */
491 #define MASK_LITTLE_ENDIAN 0x1000
492 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
494 /* 0x2000, 0x4000 are unused */
496 /* Nonzero if pointers are 64 bits. */
497 #define MASK_PTR64 0x8000
498 #define TARGET_PTR64 (target_flags & MASK_PTR64)
500 /* Nonzero if generating code to run in a 64 bit environment.
501 This is intended to only be used by TARGET_ARCH{32,64} as they are the
502 mechanism used to control compile time or run time selection. */
503 #define MASK_64BIT 0x10000
504 #define TARGET_64BIT (target_flags & MASK_64BIT)
506 /* 0x20000,0x40000 unused */
508 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
509 adding 2047 to %sp. This option is for v9 only and is the default. */
510 #define MASK_STACK_BIAS 0x80000
511 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
513 /* 0x100000,0x200000 unused */
515 /* Non-zero means -m{,no-}fpu was passed on the command line. */
516 #define MASK_FPU_SET 0x400000
517 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
519 /* Use the UltraSPARC Visual Instruction Set extensions. */
520 #define MASK_VIS 0x1000000
521 #define TARGET_VIS (target_flags & MASK_VIS)
523 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
524 the current out and global registers and Linux 2.2+ as well. */
525 #define MASK_V8PLUS 0x2000000
526 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
528 /* Force a the fastest alignment on structures to take advantage of
530 #define MASK_FASTER_STRUCTS 0x4000000
531 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
533 /* Use IEEE quad long double. */
534 #define MASK_LONG_DOUBLE_128 0x8000000
535 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
537 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
538 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
539 to get high 32 bits. False in V8+ or V9 because multiply stores
540 a 64 bit result in a register. */
542 #define TARGET_HARD_MUL32 \
543 ((TARGET_V8 || TARGET_SPARCLITE \
544 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
545 && ! TARGET_V8PLUS && TARGET_ARCH32)
547 #define TARGET_HARD_MUL \
548 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
549 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
552 /* Macro to define tables used to set the flags.
553 This is a list in braces of pairs in braces,
554 each pair being { "NAME", VALUE }
555 where VALUE is the bits to set or minus the bits to clear.
556 An empty string NAME is used to identify the default VALUE. */
558 #define TARGET_SWITCHES \
559 { {"fpu", MASK_FPU | MASK_FPU_SET, \
560 N_("Use hardware fp") }, \
561 {"no-fpu", -MASK_FPU, \
562 N_("Do not use hardware fp") }, \
563 {"no-fpu", MASK_FPU_SET, NULL, }, \
564 {"hard-float", MASK_FPU | MASK_FPU_SET, \
565 N_("Use hardware fp") }, \
566 {"soft-float", -MASK_FPU, \
567 N_("Do not use hardware fp") }, \
568 {"soft-float", MASK_FPU_SET, NULL }, \
569 {"epilogue", MASK_EPILOGUE, \
570 N_("Use function_epilogue()") }, \
571 {"no-epilogue", -MASK_EPILOGUE, \
572 N_("Do not use function_epilogue()") }, \
573 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
574 N_("Assume possible double misalignment") }, \
575 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
576 N_("Assume all doubles are aligned") }, \
577 {"impure-text", MASK_IMPURE_TEXT, \
578 N_("Pass -assert pure-text to linker") }, \
579 {"no-impure-text", -MASK_IMPURE_TEXT, \
580 N_("Do not pass -assert pure-text to linker") }, \
581 {"flat", MASK_FLAT, \
582 N_("Use flat register window model") }, \
583 {"no-flat", -MASK_FLAT, \
584 N_("Do not use flat register window model") }, \
585 {"app-regs", MASK_APP_REGS, \
586 N_("Use ABI reserved registers") }, \
587 {"no-app-regs", -MASK_APP_REGS, \
588 N_("Do not use ABI reserved registers") }, \
589 {"hard-quad-float", MASK_HARD_QUAD, \
590 N_("Use hardware quad fp instructions") }, \
591 {"soft-quad-float", -MASK_HARD_QUAD, \
592 N_("Do not use hardware quad fp instructions") }, \
593 {"v8plus", MASK_V8PLUS, \
594 N_("Compile for v8plus ABI") }, \
595 {"no-v8plus", -MASK_V8PLUS, \
596 N_("Do not compile for v8plus ABI") }, \
598 N_("Utilize Visual Instruction Set") }, \
599 {"no-vis", -MASK_VIS, \
600 N_("Do not utilize Visual Instruction Set") }, \
601 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
603 N_("Optimize for Cypress processors") }, \
605 N_("Optimize for SparcLite processors") }, \
607 N_("Optimize for F930 processors") }, \
609 N_("Optimize for F934 processors") }, \
611 N_("Use V8 Sparc ISA") }, \
613 N_("Optimize for SuperSparc processors") }, \
614 /* End of deprecated options. */ \
615 {"ptr64", MASK_PTR64, \
616 N_("Pointers are 64-bit") }, \
617 {"ptr32", -MASK_PTR64, \
618 N_("Pointers are 32-bit") }, \
619 {"32", -MASK_64BIT, \
620 N_("Use 32-bit ABI") }, \
622 N_("Use 64-bit ABI") }, \
623 {"stack-bias", MASK_STACK_BIAS, \
624 N_("Use stack bias") }, \
625 {"no-stack-bias", -MASK_STACK_BIAS, \
626 N_("Do not use stack bias") }, \
627 {"faster-structs", MASK_FASTER_STRUCTS, \
628 N_("Use structs on stronger alignment for double-word copies") }, \
629 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
630 N_("Do not use structs on stronger alignment for double-word copies") }, \
632 N_("Optimize tail call instructions in assembler and linker") }, \
634 N_("Do not optimize tail call instructions in assembler or linker") }, \
636 { "", TARGET_DEFAULT, ""}}
638 /* MASK_APP_REGS must always be the default because that's what
639 FIXED_REGISTERS is set to and -ffixed- is processed before
640 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
641 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
643 /* This is meant to be redefined in target specific files. */
644 #define SUBTARGET_SWITCHES
647 These must match the values for the cpu attribute in sparc.md. */
648 enum processor_type {
652 PROCESSOR_SUPERSPARC,
656 PROCESSOR_HYPERSPARC,
657 PROCESSOR_SPARCLITE86X,
664 /* This is set from -m{cpu,tune}=xxx. */
665 extern enum processor_type sparc_cpu;
667 /* Recast the cpu class to be the cpu attribute.
668 Every file includes us, but not every file includes insn-attr.h. */
669 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
671 /* This macro is similar to `TARGET_SWITCHES' but defines names of
672 command options that have values. Its definition is an
673 initializer with a subgrouping for each command option.
675 Each subgrouping contains a string constant, that defines the
676 fixed part of the option name, and the address of a variable.
677 The variable, type `char *', is set to the variable part of the
678 given option if the fixed part matches. The actual option name
679 is made by appending `-m' to the specified name.
681 Here is an example which defines `-mshort-data-NUMBER'. If the
682 given option is `-mshort-data-512', the variable `m88k_short_data'
683 will be set to the string `"512"'.
685 extern char *m88k_short_data;
686 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
688 #define TARGET_OPTIONS \
690 { "cpu=", &sparc_select[1].string, \
691 N_("Use features of and schedule code for given CPU") }, \
692 { "tune=", &sparc_select[2].string, \
693 N_("Schedule code for given CPU") }, \
694 { "cmodel=", &sparc_cmodel_string, \
695 N_("Use given Sparc code model") }, \
699 /* This is meant to be redefined in target specific files. */
700 #define SUBTARGET_OPTIONS
702 /* sparc_select[0] is reserved for the default cpu. */
703 struct sparc_cpu_select
706 const char *const name;
707 const int set_tune_p;
708 const int set_arch_p;
711 extern struct sparc_cpu_select sparc_select[];
713 /* target machine storage layout */
715 /* Define for cross-compilation to a sparc target with no TFmode from a host
716 with a different float format (e.g. VAX). */
717 #define REAL_ARITHMETIC
719 /* Define this if most significant bit is lowest numbered
720 in instructions that operate on numbered bit-fields. */
721 #define BITS_BIG_ENDIAN 1
723 /* Define this if most significant byte of a word is the lowest numbered. */
724 #define BYTES_BIG_ENDIAN 1
726 /* Define this if most significant word of a multiword number is the lowest
728 #define WORDS_BIG_ENDIAN 1
730 /* Define this to set the endianness to use in libgcc2.c, which can
731 not depend on target_flags. */
732 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
733 #define LIBGCC2_WORDS_BIG_ENDIAN 0
735 #define LIBGCC2_WORDS_BIG_ENDIAN 1
738 /* number of bits in an addressable storage unit */
739 #define BITS_PER_UNIT 8
741 /* Width in bits of a "word", which is the contents of a machine register.
742 Note that this is not necessarily the width of data type `int';
743 if using 16-bit ints on a 68000, this would still be 32.
744 But on a machine with 16-bit registers, this would be 16. */
745 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
746 #define MAX_BITS_PER_WORD 64
748 /* Width of a word, in units (bytes). */
749 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
750 #define MIN_UNITS_PER_WORD 4
752 /* Now define the sizes of the C data types. */
754 #define SHORT_TYPE_SIZE 16
755 #define INT_TYPE_SIZE 32
756 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
757 #define LONG_LONG_TYPE_SIZE 64
758 #define FLOAT_TYPE_SIZE 32
759 #define DOUBLE_TYPE_SIZE 64
762 #define MAX_LONG_TYPE_SIZE 64
766 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
767 Instead, it is enabled in sol2.h, because it does work under Solaris. */
768 /* Define for support of TFmode long double and REAL_ARITHMETIC.
769 Sparc ABI says that long double is 4 words. */
770 #define LONG_DOUBLE_TYPE_SIZE 128
773 /* Width in bits of a pointer.
774 See also the macro `Pmode' defined below. */
775 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
777 /* If we have to extend pointers (only when TARGET_ARCH64 and not
778 TARGET_PTR64), we want to do it unsigned. This macro does nothing
779 if ptr_mode and Pmode are the same. */
780 #define POINTERS_EXTEND_UNSIGNED 1
782 /* A macro to update MODE and UNSIGNEDP when an object whose type
783 is TYPE and which has the specified mode and signedness is to be
784 stored in a register. This macro is only called when TYPE is a
786 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
788 && GET_MODE_CLASS (MODE) == MODE_INT \
789 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
792 /* Define this macro if the promotion described by PROMOTE_MODE
793 should also be done for outgoing function arguments. */
794 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
795 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
797 #define PROMOTE_FUNCTION_ARGS
799 /* Define this macro if the promotion described by PROMOTE_MODE
800 should also be done for the return value of functions.
801 If this macro is defined, FUNCTION_VALUE must perform the same
802 promotions done by PROMOTE_MODE. */
803 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
804 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
806 #define PROMOTE_FUNCTION_RETURN
808 /* Define this macro if the promotion described by PROMOTE_MODE
809 should _only_ be performed for outgoing function arguments or
810 function return values, as specified by PROMOTE_FUNCTION_ARGS
811 and PROMOTE_FUNCTION_RETURN, respectively. */
812 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
813 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
814 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
815 for arithmetic operations which do zero/sign extension at the same time,
816 so without this we end up with a srl/sra after every assignment to an
817 user variable, which means very very bad code. */
818 #define PROMOTE_FOR_CALL_ONLY
820 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
821 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
823 /* Boundary (in *bits*) on which stack pointer should be aligned. */
824 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
826 /* ALIGN FRAMES on double word boundaries */
828 #define SPARC_STACK_ALIGN(LOC) \
829 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
831 /* Allocation boundary (in *bits*) for the code of a function. */
832 #define FUNCTION_BOUNDARY 32
834 /* Alignment of field after `int : 0' in a structure. */
835 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
837 /* Every structure's size must be a multiple of this. */
838 #define STRUCTURE_SIZE_BOUNDARY 8
840 /* A bitfield declared as `int' forces `int' alignment for the struct. */
841 #define PCC_BITFIELD_TYPE_MATTERS 1
843 /* No data type wants to be aligned rounder than this. */
844 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
846 /* The best alignment to use in cases where we have a choice. */
847 #define FASTEST_ALIGNMENT 64
849 /* Define this macro as an expression for the alignment of a structure
850 (given by STRUCT as a tree node) if the alignment computed in the
851 usual way is COMPUTED and the alignment explicitly specified was
854 The default is to use SPECIFIED if it is larger; otherwise, use
855 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
856 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
857 (TARGET_FASTER_STRUCTS ? \
858 ((TREE_CODE (STRUCT) == RECORD_TYPE \
859 || TREE_CODE (STRUCT) == UNION_TYPE \
860 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
861 && TYPE_FIELDS (STRUCT) != 0 \
862 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
863 : MAX ((COMPUTED), (SPECIFIED))) \
864 : MAX ((COMPUTED), (SPECIFIED)))
866 /* Make strings word-aligned so strcpy from constants will be faster. */
867 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
868 ((TREE_CODE (EXP) == STRING_CST \
869 && (ALIGN) < FASTEST_ALIGNMENT) \
870 ? FASTEST_ALIGNMENT : (ALIGN))
872 /* Make arrays of chars word-aligned for the same reasons. */
873 #define DATA_ALIGNMENT(TYPE, ALIGN) \
874 (TREE_CODE (TYPE) == ARRAY_TYPE \
875 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
876 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
878 /* Set this nonzero if move instructions will actually fail to work
879 when given unaligned data. */
880 #define STRICT_ALIGNMENT 1
882 /* Things that must be doubleword aligned cannot go in the text section,
883 because the linker fails to align the text section enough!
884 Put them in the data section. This macro is only used in this file. */
885 #define MAX_TEXT_ALIGN 32
887 /* This forces all variables and constants to the data section when PIC.
888 This is because the SunOS 4 shared library scheme thinks everything in
889 text is a function, and patches the address to point to a loader stub. */
890 /* This is defined to zero for every system which doesn't use the a.out object
892 #ifndef SUNOS4_SHARED_LIBRARIES
893 #define SUNOS4_SHARED_LIBRARIES 0
897 /* Use text section for a constant
898 unless we need more alignment than that offers. */
899 /* This is defined differently for v9 in a cover file. */
900 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
902 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
903 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
909 /* Standard register usage. */
911 /* Number of actual hardware registers.
912 The hardware registers are assigned numbers for the compiler
913 from 0 to just below FIRST_PSEUDO_REGISTER.
914 All registers that the compiler knows about must be given numbers,
915 even those that are not normally considered general registers.
917 SPARC has 32 integer registers and 32 floating point registers.
918 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
919 accessible. We still account for them to simplify register computations
920 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
922 Register 100 is used as the integer condition code register. */
924 #define FIRST_PSEUDO_REGISTER 101
926 #define SPARC_FIRST_FP_REG 32
927 /* Additional V9 fp regs. */
928 #define SPARC_FIRST_V9_FP_REG 64
929 #define SPARC_LAST_V9_FP_REG 95
930 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
931 #define SPARC_FIRST_V9_FCC_REG 96
932 #define SPARC_LAST_V9_FCC_REG 99
934 #define SPARC_FCC_REG 96
935 /* Integer CC reg. We don't distinguish %icc from %xcc. */
936 #define SPARC_ICC_REG 100
938 /* Nonzero if REGNO is an fp reg. */
939 #define SPARC_FP_REG_P(REGNO) \
940 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
942 /* Argument passing regs. */
943 #define SPARC_OUTGOING_INT_ARG_FIRST 8
944 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
945 #define SPARC_FP_ARG_FIRST 32
947 /* 1 for registers that have pervasive standard uses
948 and are not available for the register allocator.
951 g1 is free to use as temporary.
952 g2-g4 are reserved for applications. Gcc normally uses them as
953 temporaries, but this can be disabled via the -mno-app-regs option.
954 g5 through g7 are reserved for the operating system.
957 g1,g5 are free to use as temporaries, and are free to use between calls
958 if the call is to an external function via the PLT.
959 g4 is free to use as a temporary in the non-embedded case.
960 g4 is reserved in the embedded case.
961 g2-g3 are reserved for applications. Gcc normally uses them as
962 temporaries, but this can be disabled via the -mno-app-regs option.
963 g6-g7 are reserved for the operating system (or application in
965 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
966 currently be a fixed register until this pattern is rewritten.
967 Register 1 is also used when restoring call-preserved registers in large
970 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
971 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
974 #define FIXED_REGISTERS \
975 {1, 0, 2, 2, 2, 2, 1, 1, \
976 0, 0, 0, 0, 0, 0, 1, 0, \
977 0, 0, 0, 0, 0, 0, 0, 0, \
978 0, 0, 0, 0, 0, 0, 1, 1, \
980 0, 0, 0, 0, 0, 0, 0, 0, \
981 0, 0, 0, 0, 0, 0, 0, 0, \
982 0, 0, 0, 0, 0, 0, 0, 0, \
983 0, 0, 0, 0, 0, 0, 0, 0, \
985 0, 0, 0, 0, 0, 0, 0, 0, \
986 0, 0, 0, 0, 0, 0, 0, 0, \
987 0, 0, 0, 0, 0, 0, 0, 0, \
988 0, 0, 0, 0, 0, 0, 0, 0, \
992 /* 1 for registers not available across function calls.
993 These must include the FIXED_REGISTERS and also any
994 registers that can be used without being saved.
995 The latter must include the registers where values are returned
996 and the register where structure-value addresses are passed.
997 Aside from that, you can include as many other registers as you like. */
999 #define CALL_USED_REGISTERS \
1000 {1, 1, 1, 1, 1, 1, 1, 1, \
1001 1, 1, 1, 1, 1, 1, 1, 1, \
1002 0, 0, 0, 0, 0, 0, 0, 0, \
1003 0, 0, 0, 0, 0, 0, 1, 1, \
1005 1, 1, 1, 1, 1, 1, 1, 1, \
1006 1, 1, 1, 1, 1, 1, 1, 1, \
1007 1, 1, 1, 1, 1, 1, 1, 1, \
1008 1, 1, 1, 1, 1, 1, 1, 1, \
1010 1, 1, 1, 1, 1, 1, 1, 1, \
1011 1, 1, 1, 1, 1, 1, 1, 1, \
1012 1, 1, 1, 1, 1, 1, 1, 1, \
1013 1, 1, 1, 1, 1, 1, 1, 1, \
1017 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
1018 they won't be allocated. */
1020 #define CONDITIONAL_REGISTER_USAGE \
1025 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1026 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1028 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
1029 /* then honour it. */ \
1030 if (TARGET_ARCH32 && fixed_regs[5]) \
1031 fixed_regs[5] = 1; \
1032 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1033 fixed_regs[5] = 0; \
1037 for (regno = SPARC_FIRST_V9_FP_REG; \
1038 regno <= SPARC_LAST_V9_FP_REG; \
1040 fixed_regs[regno] = 1; \
1041 /* %fcc0 is used by v8 and v9. */ \
1042 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1043 regno <= SPARC_LAST_V9_FCC_REG; \
1045 fixed_regs[regno] = 1; \
1050 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1051 fixed_regs[regno] = 1; \
1053 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1054 /* then honour it. Likewise with g3 and g4. */ \
1055 if (fixed_regs[2] == 2) \
1056 fixed_regs[2] = ! TARGET_APP_REGS; \
1057 if (fixed_regs[3] == 2) \
1058 fixed_regs[3] = ! TARGET_APP_REGS; \
1059 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1060 fixed_regs[4] = ! TARGET_APP_REGS; \
1061 else if (TARGET_CM_EMBMEDANY) \
1062 fixed_regs[4] = 1; \
1063 else if (fixed_regs[4] == 2) \
1064 fixed_regs[4] = 0; \
1067 /* Let the compiler believe the frame pointer is still \
1068 %fp, but output it as %i7. */ \
1069 fixed_regs[31] = 1; \
1070 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
1071 /* Disable leaf functions */ \
1072 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1074 if (profile_block_flag) \
1076 /* %g1 and %g2 (sparc32) resp. %g4 (sparc64) must be \
1077 fixed, because BLOCK_PROFILER uses them. */ \
1078 fixed_regs[1] = 1; \
1079 fixed_regs[TARGET_ARCH64 ? 4 : 2] = 1; \
1084 /* Return number of consecutive hard regs needed starting at reg REGNO
1085 to hold something of mode MODE.
1086 This is ordinarily the length in words of a value of mode MODE
1087 but can be less for certain modes in special long registers.
1089 On SPARC, ordinary registers hold 32 bits worth;
1090 this means both integer and floating point registers.
1091 On v9, integer regs hold 64 bits worth; floating point regs hold
1092 32 bits worth (this includes the new fp regs as even the odd ones are
1093 included in the hard register count). */
1095 #define HARD_REGNO_NREGS(REGNO, MODE) \
1098 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1099 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1100 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1102 /* Due to the ARCH64 descrepancy above we must override these
1103 next two macros too. */
1104 #define REG_SIZE(R) \
1106 && ((GET_CODE (R) == REG \
1107 && ((REGNO (R) >= FIRST_PSEUDO_REGISTER \
1108 && FLOAT_MODE_P (GET_MODE (R))) \
1109 || (REGNO (R) < FIRST_PSEUDO_REGISTER \
1110 && REGNO (R) >= 32))) \
1111 || (GET_CODE (R) == SUBREG \
1112 && ((REGNO (SUBREG_REG (R)) >= FIRST_PSEUDO_REGISTER \
1113 && FLOAT_MODE_P (GET_MODE (SUBREG_REG (R)))) \
1114 || (REGNO (SUBREG_REG (R)) < FIRST_PSEUDO_REGISTER \
1115 && REGNO (SUBREG_REG (R)) >= 32)))) \
1116 ? (GET_MODE_SIZE (GET_MODE (R)) + 3) / 4 \
1117 : (GET_MODE_SIZE (GET_MODE (R)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1119 #define REGMODE_NATURAL_SIZE(MODE) \
1120 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1122 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1123 See sparc.c for how we initialize this. */
1124 extern int *hard_regno_mode_classes;
1125 extern int sparc_mode_class[];
1127 /* ??? Because of the funny way we pass parameters we should allow certain
1128 ??? types of float/complex values to be in integer registers during
1129 ??? RTL generation. This only matters on arch32. */
1130 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1131 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1133 /* Value is 1 if it is a good idea to tie two pseudo registers
1134 when one has mode MODE1 and one has mode MODE2.
1135 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1136 for any hard reg, then this must be 0 for correct output.
1138 For V9: SFmode can't be combined with other float modes, because they can't
1139 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1140 registers, but SFmode will. */
1141 #define MODES_TIEABLE_P(MODE1, MODE2) \
1142 ((MODE1) == (MODE2) \
1143 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1145 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1146 || (MODE1 != SFmode && MODE2 != SFmode)))))
1148 /* Specify the registers used for certain standard purposes.
1149 The values of these macros are register numbers. */
1151 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1152 /* #define PC_REGNUM */
1154 /* Register to use for pushing function arguments. */
1155 #define STACK_POINTER_REGNUM 14
1157 /* Actual top-of-stack address is 92/176 greater than the contents of the
1158 stack pointer register for !v9/v9. That is:
1159 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1160 address, and 6*4 bytes for the 6 register parameters.
1161 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1163 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
1165 /* The stack bias (amount by which the hardware register is offset by). */
1166 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1168 /* Is stack biased? */
1169 #define STACK_BIAS SPARC_STACK_BIAS
1171 /* Base register for access to local variables of the function. */
1172 #define FRAME_POINTER_REGNUM 30
1175 /* Register that is used for the return address for the flat model. */
1176 #define RETURN_ADDR_REGNUM 15
1179 /* Value should be nonzero if functions must have frame pointers.
1180 Zero means the frame pointer need not be set up (and parms
1181 may be accessed via the stack pointer) in functions that seem suitable.
1182 This is computed in `reload', in reload1.c.
1183 Used in flow.c, global.c, and reload1.c.
1185 Being a non-leaf function does not mean a frame pointer is needed in the
1186 flat window model. However, the debugger won't be able to backtrace through
1188 #define FRAME_POINTER_REQUIRED \
1189 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
1190 || !leaf_function_p ()) \
1191 : ! (leaf_function_p () && only_leaf_regs_used ()))
1193 /* C statement to store the difference between the frame pointer
1194 and the stack pointer values immediately after the function prologue.
1196 Note, we always pretend that this is a leaf function because if
1197 it's not, there's no point in trying to eliminate the
1198 frame pointer. If it is a leaf function, we guessed right! */
1199 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1200 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1201 : compute_frame_size (get_frame_size (), 1)))
1203 /* Base register for access to arguments of the function. */
1204 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1206 /* Register in which static-chain is passed to a function. This must
1207 not be a register used by the prologue. */
1208 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1210 /* Register which holds offset table for position-independent
1213 #define PIC_OFFSET_TABLE_REGNUM 23
1215 /* Pick a default value we can notice from override_options:
1217 v9: Default is off. */
1219 #define DEFAULT_PCC_STRUCT_RETURN -1
1221 /* Sparc ABI says that quad-precision floats and all structures are returned
1223 For v9: unions <= 32 bytes in size are returned in int regs,
1224 structures up to 32 bytes are returned in int and fp regs. */
1226 #define RETURN_IN_MEMORY(TYPE) \
1228 ? (TYPE_MODE (TYPE) == BLKmode \
1229 || TYPE_MODE (TYPE) == TFmode \
1230 || TYPE_MODE (TYPE) == TCmode) \
1231 : (TYPE_MODE (TYPE) == BLKmode \
1232 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1234 /* Functions which return large structures get the address
1235 to place the wanted value at offset 64 from the frame.
1236 Must reserve 64 bytes for the in and local registers.
1237 v9: Functions which return large structures get the address to place the
1238 wanted value from an invisible first argument. */
1239 /* Used only in other #defines in this file. */
1240 #define STRUCT_VALUE_OFFSET 64
1242 #define STRUCT_VALUE \
1245 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1246 STRUCT_VALUE_OFFSET)))
1248 #define STRUCT_VALUE_INCOMING \
1251 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1252 STRUCT_VALUE_OFFSET)))
1254 /* Define the classes of registers for register constraints in the
1255 machine description. Also define ranges of constants.
1257 One of the classes must always be named ALL_REGS and include all hard regs.
1258 If there is more than one class, another class must be named NO_REGS
1259 and contain no registers.
1261 The name GENERAL_REGS must be the name of a class (or an alias for
1262 another name such as ALL_REGS). This is the class of registers
1263 that is allowed by "g" or "r" in a register constraint.
1264 Also, registers outside this class are allocated only when
1265 instructions express preferences for them.
1267 The classes must be numbered in nondecreasing order; that is,
1268 a larger-numbered class must never be contained completely
1269 in a smaller-numbered class.
1271 For any two classes, it is very desirable that there be another
1272 class that represents their union. */
1274 /* The SPARC has various kinds of registers: general, floating point,
1275 and condition codes [well, it has others as well, but none that we
1276 care directly about].
1278 For v9 we must distinguish between the upper and lower floating point
1279 registers because the upper ones can't hold SFmode values.
1280 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1281 satisfying a group need for a class will also satisfy a single need for
1282 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1285 It is important that one class contains all the general and all the standard
1286 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1287 because reg_class_record() will bias the selection in favor of fp regs,
1288 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1289 because FP_REGS > GENERAL_REGS.
1291 It is also important that one class contain all the general and all the
1292 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1293 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1294 allocate_reload_reg() to bypass it causing an abort because the compiler
1295 thinks it doesn't have a spill reg when in fact it does.
1297 v9 also has 4 floating point condition code registers. Since we don't
1298 have a class that is the union of FPCC_REGS with either of the others,
1299 it is important that it appear first. Otherwise the compiler will die
1300 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1303 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1304 may try to use it to hold an SImode value. See register_operand.
1305 ??? Should %fcc[0123] be handled similarly?
1308 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1309 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1310 ALL_REGS, LIM_REG_CLASSES };
1312 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1314 /* Give names of register classes as strings for dump file. */
1316 #define REG_CLASS_NAMES \
1317 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1318 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1321 /* Define which registers fit in which classes.
1322 This is an initializer for a vector of HARD_REG_SET
1323 of length N_REG_CLASSES. */
1325 #define REG_CLASS_CONTENTS \
1326 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \
1327 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1328 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1330 /* The same information, inverted:
1331 Return the class number of the smallest class containing
1332 reg number REGNO. This could be a conditional expression
1333 or could index an array. */
1335 extern enum reg_class sparc_regno_reg_class[];
1337 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1339 /* This is the order in which to allocate registers normally.
1341 We put %f0/%f1 last among the float registers, so as to make it more
1342 likely that a pseudo-register which dies in the float return register
1343 will get allocated to the float return register, thus saving a move
1344 instruction at the end of the function. */
1346 #define REG_ALLOC_ORDER \
1347 { 8, 9, 10, 11, 12, 13, 2, 3, \
1348 15, 16, 17, 18, 19, 20, 21, 22, \
1349 23, 24, 25, 26, 27, 28, 29, 31, \
1350 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1351 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1352 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1353 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1354 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1355 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1356 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1357 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1358 32, 33, /* %f0,%f1 */ \
1359 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1360 1, 4, 5, 6, 7, 0, 14, 30}
1362 /* This is the order in which to allocate registers for
1363 leaf functions. If all registers can fit in the "gi" registers,
1364 then we have the possibility of having a leaf function. */
1366 #define REG_LEAF_ALLOC_ORDER \
1367 { 2, 3, 24, 25, 26, 27, 28, 29, \
1369 15, 8, 9, 10, 11, 12, 13, \
1370 16, 17, 18, 19, 20, 21, 22, 23, \
1371 34, 35, 36, 37, 38, 39, \
1372 40, 41, 42, 43, 44, 45, 46, 47, \
1373 48, 49, 50, 51, 52, 53, 54, 55, \
1374 56, 57, 58, 59, 60, 61, 62, 63, \
1375 64, 65, 66, 67, 68, 69, 70, 71, \
1376 72, 73, 74, 75, 76, 77, 78, 79, \
1377 80, 81, 82, 83, 84, 85, 86, 87, \
1378 88, 89, 90, 91, 92, 93, 94, 95, \
1380 96, 97, 98, 99, 100, \
1383 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1385 extern char sparc_leaf_regs[];
1386 #define LEAF_REGISTERS sparc_leaf_regs
1388 extern const char leaf_reg_remap[];
1389 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1391 /* The class value for index registers, and the one for base regs. */
1392 #define INDEX_REG_CLASS GENERAL_REGS
1393 #define BASE_REG_CLASS GENERAL_REGS
1395 /* Local macro to handle the two v9 classes of FP regs. */
1396 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1398 /* Get reg_class from a letter such as appears in the machine description.
1399 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1400 .md file for v8 and v9.
1401 'd' and 'b' are used for single and double precision VIS operations,
1403 'h' is used for V8+ 64 bit global and out registers. */
1405 #define REG_CLASS_FROM_LETTER(C) \
1407 ? ((C) == 'f' ? FP_REGS \
1408 : (C) == 'e' ? EXTRA_FP_REGS \
1409 : (C) == 'c' ? FPCC_REGS \
1410 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1411 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1412 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1414 : ((C) == 'f' ? FP_REGS \
1415 : (C) == 'e' ? FP_REGS \
1416 : (C) == 'c' ? FPCC_REGS \
1419 /* The letters I, J, K, L and M in a register constraint string
1420 can be used to stand for particular ranges of immediate operands.
1421 This macro defines what the ranges are.
1422 C is the letter, and VALUE is a constant value.
1423 Return 1 if VALUE is in the range specified by C.
1425 `I' is used for the range of constants an insn can actually contain.
1426 `J' is used for the range which is just zero (since that is R0).
1427 `K' is used for constants which can be loaded with a single sethi insn.
1428 `L' is used for the range of constants supported by the movcc insns.
1429 `M' is used for the range of constants supported by the movrcc insns. */
1431 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1432 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1433 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1434 /* 10 and 11 bit immediates are only used for a few specific insns.
1435 SMALL_INT is used throughout the port so we continue to use it. */
1436 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1437 /* 13 bit immediate, considering only the low 32 bits */
1438 #define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
1439 #define SPARC_SETHI_P(X) \
1440 (((unsigned HOST_WIDE_INT) (X) & \
1441 (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
1443 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1444 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1445 : (C) == 'J' ? (VALUE) == 0 \
1446 : (C) == 'K' ? SPARC_SETHI_P (VALUE) \
1447 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1448 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1451 /* Similar, but for floating constants, and defining letters G and H.
1452 Here VALUE is the CONST_DOUBLE rtx itself. */
1454 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1455 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1456 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1459 /* Given an rtx X being reloaded into a reg required to be
1460 in class CLASS, return the class of reg to actually use.
1461 In general this is just CLASS; but on some machines
1462 in some cases it is preferable to use a more restrictive class. */
1463 /* - We can't load constants into FP registers.
1464 - We can't load FP constants into integer registers when soft-float,
1465 because there is no soft-float pattern with a r/F constraint.
1466 - We can't load FP constants into integer registers for TFmode unless
1467 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1468 - Try and reload integer constants (symbolic or otherwise) back into
1469 registers directly, rather than having them dumped to memory. */
1471 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1473 ? ((FP_REG_CLASS_P (CLASS) \
1474 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1476 || (GET_MODE (X) == TFmode \
1477 && ! fp_zero_operand (X, TFmode))) \
1479 : (!FP_REG_CLASS_P (CLASS) \
1480 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1485 /* Return the register class of a scratch register needed to load IN into
1486 a register of class CLASS in MODE.
1488 We need a temporary when loading/storing a HImode/QImode value
1489 between memory and the FPU registers. This can happen when combine puts
1490 a paradoxical subreg in a float/fix conversion insn. */
1492 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1493 ((FP_REG_CLASS_P (CLASS) \
1494 && ((MODE) == HImode || (MODE) == QImode) \
1495 && (GET_CODE (IN) == MEM \
1496 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1497 && true_regnum (IN) == -1))) \
1499 : (((TARGET_CM_MEDANY \
1500 && symbolic_operand ((IN), (MODE))) \
1501 || (TARGET_CM_EMBMEDANY \
1502 && text_segment_operand ((IN), (MODE)))) \
1507 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1508 ((FP_REG_CLASS_P (CLASS) \
1509 && ((MODE) == HImode || (MODE) == QImode) \
1510 && (GET_CODE (IN) == MEM \
1511 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1512 && true_regnum (IN) == -1))) \
1514 : (((TARGET_CM_MEDANY \
1515 && symbolic_operand ((IN), (MODE))) \
1516 || (TARGET_CM_EMBMEDANY \
1517 && text_segment_operand ((IN), (MODE)))) \
1522 /* On SPARC it is not possible to directly move data between
1523 GENERAL_REGS and FP_REGS. */
1524 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1525 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1527 /* Return the stack location to use for secondary memory needed reloads.
1528 We want to use the reserved location just below the frame pointer.
1529 However, we must ensure that there is a frame, so use assign_stack_local
1530 if the frame size is zero. */
1531 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1532 (get_frame_size () == 0 \
1533 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1534 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1535 STARTING_FRAME_OFFSET)))
1537 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1538 because the movsi and movsf patterns don't handle r/f moves.
1539 For v8 we copy the default definition. */
1540 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1542 ? (GET_MODE_BITSIZE (MODE) < 32 \
1543 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1545 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1546 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1549 /* Return the maximum number of consecutive registers
1550 needed to represent mode MODE in a register of class CLASS. */
1551 /* On SPARC, this is the size of MODE in words. */
1552 #define CLASS_MAX_NREGS(CLASS, MODE) \
1553 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1554 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1556 /* Stack layout; function entry, exit and calling. */
1558 /* Define the number of register that can hold parameters.
1559 This macro is only used in other macro definitions below and in sparc.c.
1560 MODE is the mode of the argument.
1561 !v9: All args are passed in %o0-%o5.
1562 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1563 See the description in sparc.c. */
1564 #define NPARM_REGS(MODE) \
1566 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1569 /* Define this if pushing a word on the stack
1570 makes the stack pointer a smaller address. */
1571 #define STACK_GROWS_DOWNWARD
1573 /* Define this if the nominal address of the stack frame
1574 is at the high-address end of the local variables;
1575 that is, each additional local variable allocated
1576 goes at a more negative offset in the frame. */
1577 #define FRAME_GROWS_DOWNWARD
1579 /* Offset within stack frame to start allocating local variables at.
1580 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1581 first local allocated. Otherwise, it is the offset to the BEGINNING
1582 of the first local allocated. */
1583 /* This allows space for one TFmode floating point value. */
1584 #define STARTING_FRAME_OFFSET \
1585 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1586 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1588 /* If we generate an insn to push BYTES bytes,
1589 this says how many the stack pointer really advances by.
1590 On SPARC, don't define this because there are no push insns. */
1591 /* #define PUSH_ROUNDING(BYTES) */
1593 /* Offset of first parameter from the argument pointer register value.
1594 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1595 even if this function isn't going to use it.
1596 v9: This is 128 for the ins and locals. */
1597 #define FIRST_PARM_OFFSET(FNDECL) \
1598 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
1599 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1601 /* Offset from the argument pointer register value to the CFA.
1602 This is different from FIRST_PARM_OFFSET because the register window
1603 comes between the CFA and the arguments. */
1605 #define ARG_POINTER_CFA_OFFSET(FNDECL) SPARC_STACK_BIAS
1607 /* When a parameter is passed in a register, stack space is still
1609 !v9: All 6 possible integer registers have backing store allocated.
1610 v9: Only space for the arguments passed is allocated. */
1611 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1612 meaning to the backend. Further, we need to be able to detect if a
1613 varargs/unprototyped function is called, as they may want to spill more
1614 registers than we've provided space. Ugly, ugly. So for now we retain
1615 all 6 slots even for v9. */
1616 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1618 /* Keep the stack pointer constant throughout the function.
1619 This is both an optimization and a necessity: longjmp
1620 doesn't behave itself when the stack pointer moves within
1622 #define ACCUMULATE_OUTGOING_ARGS 1
1624 /* Value is the number of bytes of arguments automatically
1625 popped when returning from a subroutine call.
1626 FUNDECL is the declaration node of the function (as a tree),
1627 FUNTYPE is the data type of the function (as a tree),
1628 or for a library call it is an identifier node for the subroutine name.
1629 SIZE is the number of bytes of arguments passed on the stack. */
1631 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1633 /* Some subroutine macros specific to this machine.
1634 When !TARGET_FPU, put float return values in the general registers,
1635 since we don't have any fp registers. */
1636 #define BASE_RETURN_VALUE_REG(MODE) \
1638 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1639 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1641 #define BASE_OUTGOING_VALUE_REG(MODE) \
1643 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1644 : TARGET_FLAT ? 8 : 24) \
1645 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1646 : (TARGET_FLAT ? 8 : 24)))
1648 #define BASE_PASSING_ARG_REG(MODE) \
1650 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1653 /* ??? FIXME -- seems wrong for v9 structure passing... */
1654 #define BASE_INCOMING_ARG_REG(MODE) \
1656 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1657 : TARGET_FLAT ? 8 : 24) \
1658 : (TARGET_FLAT ? 8 : 24))
1660 /* Define this macro if the target machine has "register windows". This
1661 C expression returns the register number as seen by the called function
1662 corresponding to register number OUT as seen by the calling function.
1663 Return OUT if register number OUT is not an outbound register. */
1665 #define INCOMING_REGNO(OUT) \
1666 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1668 /* Define this macro if the target machine has "register windows". This
1669 C expression returns the register number as seen by the calling function
1670 corresponding to register number IN as seen by the called function.
1671 Return IN if register number IN is not an inbound register. */
1673 #define OUTGOING_REGNO(IN) \
1674 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1676 /* Define this macro if the target machine has register windows. This
1677 C expression returns true if the register is call-saved but is in the
1680 #define LOCAL_REGNO(REGNO) \
1681 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1683 /* Define how to find the value returned by a function.
1684 VALTYPE is the data type of the value (as a tree).
1685 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1686 otherwise, FUNC is 0. */
1688 /* On SPARC the value is found in the first "output" register. */
1690 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1691 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1693 /* But the called function leaves it in the first "input" register. */
1695 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1696 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1698 /* Define how to find the value returned by a library function
1699 assuming the value has mode MODE. */
1701 #define LIBCALL_VALUE(MODE) \
1702 function_value (NULL_TREE, (MODE), 1)
1704 /* 1 if N is a possible register number for a function value
1705 as seen by the caller.
1706 On SPARC, the first "output" reg is used for integer values,
1707 and the first floating point register is used for floating point values. */
1709 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1711 /* Define the size of space to allocate for the return value of an
1714 #define APPLY_RESULT_SIZE 16
1716 /* 1 if N is a possible register number for function argument passing.
1717 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1719 #define FUNCTION_ARG_REGNO_P(N) \
1721 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1722 : ((N) >= 8 && (N) <= 13))
1724 /* Define a data type for recording info about an argument list
1725 during the scan of that argument list. This data type should
1726 hold all necessary information about the function itself
1727 and about the args processed so far, enough to enable macros
1728 such as FUNCTION_ARG to determine where the next arg should go.
1730 On SPARC (!v9), this is a single integer, which is a number of words
1731 of arguments scanned so far (including the invisible argument,
1732 if any, which holds the structure-value-address).
1733 Thus 7 or more means all following args should go on the stack.
1735 For v9, we also need to know whether a prototype is present. */
1738 int words; /* number of words passed so far */
1739 int prototype_p; /* non-zero if a prototype is present */
1740 int libcall_p; /* non-zero if a library call */
1742 #define CUMULATIVE_ARGS struct sparc_args
1744 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1745 for a call to a function whose data type is FNTYPE.
1746 For a library call, FNTYPE is 0. */
1748 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1749 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1751 /* Update the data in CUM to advance over an argument
1752 of mode MODE and data type TYPE.
1753 TYPE is null for libcalls where that information may not be available. */
1755 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1756 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1758 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1760 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1762 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1763 || TREE_ADDRESSABLE (TYPE)))
1765 /* Determine where to put an argument to a function.
1766 Value is zero to push the argument on the stack,
1767 or a hard register in which to store the argument.
1769 MODE is the argument's machine mode.
1770 TYPE is the data type of the argument (as a tree).
1771 This is null for libcalls where that information may
1773 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1774 the preceding args and about the function being called.
1775 NAMED is nonzero if this argument is a named parameter
1776 (otherwise it is an extra parameter matching an ellipsis). */
1778 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1779 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1781 /* Define where a function finds its arguments.
1782 This is different from FUNCTION_ARG because of register windows. */
1784 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1785 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1787 /* For an arg passed partly in registers and partly in memory,
1788 this is the number of registers used.
1789 For args passed entirely in registers or entirely in memory, zero. */
1791 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1792 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1794 /* A C expression that indicates when an argument must be passed by reference.
1795 If nonzero for an argument, a copy of that argument is made in memory and a
1796 pointer to the argument is passed instead of the argument itself.
1797 The pointer is passed in whatever way is appropriate for passing a pointer
1800 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1801 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1803 /* If defined, a C expression which determines whether, and in which direction,
1804 to pad out an argument with extra space. The value should be of type
1805 `enum direction': either `upward' to pad above the argument,
1806 `downward' to pad below, or `none' to inhibit padding. */
1808 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1809 function_arg_padding ((MODE), (TYPE))
1811 /* If defined, a C expression that gives the alignment boundary, in bits,
1812 of an argument with the specified mode and type. If it is not defined,
1813 PARM_BOUNDARY is used for all arguments.
1814 For sparc64, objects requiring 16 byte alignment are passed that way. */
1816 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1818 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1819 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1820 ? 128 : PARM_BOUNDARY)
1822 /* Define the information needed to generate branch and scc insns. This is
1823 stored from the compare operation. Note that we can't use "rtx" here
1824 since it hasn't been defined! */
1826 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1829 /* Generate the special assembly code needed to tell the assembler whatever
1830 it might need to know about the return value of a function.
1832 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1833 information to the assembler relating to peephole optimization (done in
1836 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1837 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1839 /* Output the special assembly code needed to tell the assembler some
1840 register is used as global register variable.
1842 SPARC 64bit psABI declares registers %g2 and %g3 as application
1843 registers and %g6 and %g7 as OS registers. Any object using them
1844 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1845 and how they are used (scratch or some global variable).
1846 Linker will then refuse to link together objects which use those
1847 registers incompatibly.
1849 Unless the registers are used for scratch, two different global
1850 registers cannot be declared to the same name, so in the unlikely
1851 case of a global register variable occupying more than one register
1852 we prefix the second and following registers with .gnu.part1. etc. */
1854 extern char sparc_hard_reg_printed[8];
1856 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1857 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1859 if (TARGET_ARCH64) \
1861 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1863 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1864 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1866 if (reg == (REGNO)) \
1867 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1869 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1870 reg, reg - (REGNO), (NAME)); \
1871 sparc_hard_reg_printed[reg] = 1; \
1878 /* Output assembler code to FILE to increment profiler label # LABELNO
1879 for profiling a function entry. */
1881 #define FUNCTION_PROFILER(FILE, LABELNO) \
1882 sparc_function_profiler(FILE, LABELNO)
1884 /* Set the name of the mcount function for the system. */
1886 #define MCOUNT_FUNCTION "*mcount"
1888 /* The following macro shall output assembler code to FILE
1889 to initialize basic-block profiling. */
1891 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1892 sparc_function_block_profiler(FILE, BLOCK_OR_LABEL)
1894 /* The following macro shall output assembler code to FILE
1895 to increment a counter associated with basic block number BLOCKNO. */
1897 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1898 sparc_block_profiler (FILE, BLOCKNO)
1900 /* The following macro shall output assembler code to FILE
1901 to indicate a return from function during basic-block profiling. */
1903 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1904 sparc_function_block_profiler_exit(FILE)
1908 /* The function `__bb_trace_func' is called in every basic block
1909 and is not allowed to change the machine state. Saving (restoring)
1910 the state can either be done in the BLOCK_PROFILER macro,
1911 before calling function (rsp. after returning from function)
1912 `__bb_trace_func', or it can be done inside the function by
1913 defining the macros:
1915 MACHINE_STATE_SAVE(ID)
1916 MACHINE_STATE_RESTORE(ID)
1918 In the latter case care must be taken, that the prologue code
1919 of function `__bb_trace_func' does not already change the
1920 state prior to saving it with MACHINE_STATE_SAVE.
1922 The parameter `ID' is a string identifying a unique macro use.
1924 On sparc it is sufficient to save the psw register to memory.
1925 Unfortunately the psw register can be read in supervisor mode only,
1926 so we read only the condition codes by using branch instructions
1927 and hope that this is enough.
1929 On V9, life is much sweater: there is a user accessible %ccr
1930 register, but we use it for 64bit libraries only. */
1934 #define MACHINE_STATE_SAVE(ID) \
1935 int ms_flags, ms_saveret; \
1948 bneg,a LFLGNN"ID"\n\
1951 : "=r"(ms_flags), "=r"(ms_saveret));
1955 #define MACHINE_STATE_SAVE(ID) \
1956 unsigned long ms_flags, ms_saveret; \
1960 : "=r"(ms_flags), "=r"(ms_saveret));
1964 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
1965 The psw register can be written in supervisor mode only,
1966 which is true even for simple condition codes.
1967 We use some combination of instructions to produce the
1968 proper condition codes, but some flag combinations can not
1969 be generated in this way. If this happens an unimplemented
1970 instruction will be executed to abort the program. */
1974 #define MACHINE_STATE_RESTORE(ID) \
1975 { extern char flgtab[] __asm__("LFLGTAB"ID); \
1979 ! Do part of VC in the delay slot here, as it needs 3 insns.\n\
1996 subcc %%g0,%%g0,%%g0\n\
2005 orcc %%g0,-1,%%g0\n\
2008 addcc %%g0,%3,%%g0\n\
2030 : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \
2031 "r"(0x80000000), "r"(ms_saveret) \
2036 #define MACHINE_STATE_RESTORE(ID) \
2040 : : "r"(ms_flags), "r"(ms_saveret) \
2045 #endif /* IN_LIBGCC2 */
2047 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2048 the stack pointer does not matter. The value is tested only in
2049 functions that have frame pointers.
2050 No definition is equivalent to always zero. */
2052 #define EXIT_IGNORE_STACK \
2053 (get_frame_size () != 0 \
2054 || current_function_calls_alloca || current_function_outgoing_args_size)
2056 #define DELAY_SLOTS_FOR_EPILOGUE \
2057 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2058 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2059 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2060 : eligible_for_epilogue_delay (trial, slots_filled))
2062 /* Define registers used by the epilogue and return instruction. */
2063 #define EPILOGUE_USES(REGNO) \
2064 (!TARGET_FLAT && REGNO == 31)
2066 /* Length in units of the trampoline for entering a nested function. */
2068 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
2070 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
2072 /* Emit RTL insns to initialize the variable parts of a trampoline.
2073 FNADDR is an RTX for the address of the function's pure code.
2074 CXT is an RTX for the static chain value for the function. */
2076 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2077 if (TARGET_ARCH64) \
2078 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2080 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
2082 /* Generate necessary RTL for __builtin_saveregs(). */
2084 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
2086 /* Implement `va_start' for varargs and stdarg. */
2087 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2088 sparc_va_start (stdarg, valist, nextarg)
2090 /* Implement `va_arg'. */
2091 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2092 sparc_va_arg (valist, type)
2094 /* Define this macro if the location where a function argument is passed
2095 depends on whether or not it is a named argument.
2097 This macro controls how the NAMED argument to FUNCTION_ARG
2098 is set for varargs and stdarg functions. With this macro defined,
2099 the NAMED argument is always true for named arguments, and false for
2100 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
2101 is defined, then all arguments are treated as named. Otherwise, all named
2102 arguments except the last are treated as named.
2103 For the v9 we want NAMED to mean what it says it means. */
2105 #define STRICT_ARGUMENT_NAMING TARGET_V9
2107 /* We do not allow sibling calls if -mflat, nor
2108 we do not allow indirect calls to be optimized into sibling calls. */
2109 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
2111 /* Generate RTL to flush the register windows so as to make arbitrary frames
2113 #define SETUP_FRAME_ADDRESSES() \
2114 emit_insn (gen_flush_register_windows ())
2116 /* Given an rtx for the address of a frame,
2117 return an rtx for the address of the word in the frame
2118 that holds the dynamic chain--the previous frame's address.
2119 ??? -mflat support? */
2120 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
2122 /* The return address isn't on the stack, it is in a register, so we can't
2123 access it from the current frame pointer. We can access it from the
2124 previous frame pointer though by reading a value from the register window
2126 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2128 /* This is the offset of the return address to the true next instruction to be
2129 executed for the current function. */
2130 #define RETURN_ADDR_OFFSET \
2131 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2133 /* The current return address is in %i7. The return address of anything
2134 farther back is in the register window save area at [%fp+60]. */
2135 /* ??? This ignores the fact that the actual return address is +8 for normal
2136 returns, and +12 for structure returns. */
2137 #define RETURN_ADDR_RTX(count, frame) \
2139 ? gen_rtx_REG (Pmode, 31) \
2140 : gen_rtx_MEM (Pmode, \
2141 memory_address (Pmode, plus_constant (frame, \
2142 15 * UNITS_PER_WORD))))
2144 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
2145 +12, but always using +8 is close enough for frame unwind purposes.
2146 Actually, just using %o7 is close enough for unwinding, but %o7+8
2147 is something you can return to. */
2148 #define INCOMING_RETURN_ADDR_RTX \
2149 plus_constant (gen_rtx_REG (word_mode, 15), 8)
2150 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
2152 /* The offset from the incoming value of %sp to the top of the stack frame
2153 for the current function. On sparc64, we have to account for the stack
2155 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
2157 /* Describe how we implement __builtin_eh_return. */
2158 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
2159 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
2160 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
2162 /* Addressing modes, and classification of registers for them. */
2164 /* #define HAVE_POST_INCREMENT 0 */
2165 /* #define HAVE_POST_DECREMENT 0 */
2167 /* #define HAVE_PRE_DECREMENT 0 */
2168 /* #define HAVE_PRE_INCREMENT 0 */
2170 /* Macros to check register numbers against specific register classes. */
2172 /* These assume that REGNO is a hard or pseudo reg number.
2173 They give nonzero only if REGNO is a hard reg of the suitable class
2174 or a pseudo reg currently allocated to a suitable hard reg.
2175 Since they use reg_renumber, they are safe only once reg_renumber
2176 has been allocated, which happens in local-alloc.c. */
2178 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2179 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2180 #define REGNO_OK_FOR_BASE_P(REGNO) \
2181 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2182 #define REGNO_OK_FOR_FP_P(REGNO) \
2183 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2184 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2185 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2187 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2188 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2190 /* Now macros that check whether X is a register and also,
2191 strictly, whether it is in a specified class.
2193 These macros are specific to the SPARC, and may be used only
2194 in code for printing assembler insns and in conditions for
2195 define_optimization. */
2197 /* 1 if X is an fp register. */
2199 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2201 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2202 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2204 /* Maximum number of registers that can appear in a valid memory address. */
2206 #define MAX_REGS_PER_ADDRESS 2
2208 /* Recognize any constant value that is a valid address.
2209 When PIC, we do not accept an address that would require a scratch reg
2210 to load into a register. */
2212 #define CONSTANT_ADDRESS_P(X) \
2213 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2214 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2215 || (GET_CODE (X) == CONST \
2216 && ! (flag_pic && pic_address_needs_scratch (X))))
2218 /* Define this, so that when PIC, reload won't try to reload invalid
2219 addresses which require two reload registers. */
2221 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2223 /* Nonzero if the constant value X is a legitimate general operand.
2224 Anything can be made to work except floating point constants.
2225 If TARGET_VIS, 0.0 can be made to work as well. */
2227 #define LEGITIMATE_CONSTANT_P(X) \
2228 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2230 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2231 GET_MODE (X) == TFmode) && \
2232 fp_zero_operand (X, GET_MODE (X))))
2234 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2235 and check its validity for a certain class.
2236 We have two alternate definitions for each of them.
2237 The usual definition accepts all pseudo regs; the other rejects
2238 them unless they have been allocated suitable hard regs.
2239 The symbol REG_OK_STRICT causes the latter definition to be used.
2241 Most source files want to accept pseudo regs in the hope that
2242 they will get allocated to the class that the insn wants them to be in.
2243 Source files for reload pass need to be strict.
2244 After reload, it makes no difference, since pseudo regs have
2245 been eliminated by then. */
2247 /* Optional extra constraints for this machine.
2249 'Q' handles floating point constants which can be moved into
2250 an integer register with a single sethi instruction.
2252 'R' handles floating point constants which can be moved into
2253 an integer register with a single mov instruction.
2255 'S' handles floating point constants which can be moved into
2256 an integer register using a high/lo_sum sequence.
2258 'T' handles memory addresses where the alignment is known to
2259 be at least 8 bytes.
2261 `U' handles all pseudo registers or a hard even numbered
2262 integer register, needed for ldd/std instructions. */
2264 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2265 ((C) == 'Q' ? fp_sethi_p(OP) \
2266 : (C) == 'R' ? fp_mov_p(OP) \
2267 : (C) == 'S' ? fp_high_losum_p(OP) \
2270 #ifndef REG_OK_STRICT
2272 /* Nonzero if X is a hard reg that can be used as an index
2273 or if it is a pseudo reg. */
2274 #define REG_OK_FOR_INDEX_P(X) \
2275 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2276 /* Nonzero if X is a hard reg that can be used as a base reg
2277 or if it is a pseudo reg. */
2278 #define REG_OK_FOR_BASE_P(X) \
2279 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2281 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2283 #define EXTRA_CONSTRAINT(OP, C) \
2284 (EXTRA_CONSTRAINT_BASE(OP, C) \
2285 || ((! TARGET_ARCH64 && (C) == 'T') \
2286 ? (mem_min_alignment (OP, 8)) \
2287 : ((! TARGET_ARCH64 && (C) == 'U') \
2288 ? (register_ok_for_ldd (OP)) \
2293 /* Nonzero if X is a hard reg that can be used as an index. */
2294 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2295 /* Nonzero if X is a hard reg that can be used as a base reg. */
2296 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2298 #define EXTRA_CONSTRAINT(OP, C) \
2299 (EXTRA_CONSTRAINT_BASE(OP, C) \
2300 || ((! TARGET_ARCH64 && (C) == 'T') \
2301 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2302 : ((! TARGET_ARCH64 && (C) == 'U') \
2303 ? (GET_CODE (OP) == REG \
2304 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2305 || reg_renumber[REGNO (OP)] >= 0) \
2306 && register_ok_for_ldd (OP)) \
2311 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2313 #ifdef HAVE_AS_OFFSETABLE_LO10
2314 #define USE_AS_OFFSETABLE_LO10 1
2316 #define USE_AS_OFFSETABLE_LO10 0
2319 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2320 that is a valid memory address for an instruction.
2321 The MODE argument is the machine mode for the MEM expression
2322 that wants to use this address.
2324 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2325 ordinarily. This changes a bit when generating PIC.
2327 If you change this, execute "rm explow.o recog.o reload.o". */
2329 #define RTX_OK_FOR_BASE_P(X) \
2330 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2331 || (GET_CODE (X) == SUBREG \
2332 && GET_CODE (SUBREG_REG (X)) == REG \
2333 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2335 #define RTX_OK_FOR_INDEX_P(X) \
2336 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2337 || (GET_CODE (X) == SUBREG \
2338 && GET_CODE (SUBREG_REG (X)) == REG \
2339 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2341 #define RTX_OK_FOR_OFFSET_P(X) \
2342 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2344 #define RTX_OK_FOR_OLO10_P(X) \
2345 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2347 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2348 { if (RTX_OK_FOR_BASE_P (X)) \
2350 else if (GET_CODE (X) == PLUS) \
2352 register rtx op0 = XEXP (X, 0); \
2353 register rtx op1 = XEXP (X, 1); \
2354 if (flag_pic && op0 == pic_offset_table_rtx) \
2356 if (RTX_OK_FOR_BASE_P (op1)) \
2358 else if (flag_pic == 1 \
2359 && GET_CODE (op1) != REG \
2360 && GET_CODE (op1) != LO_SUM \
2361 && GET_CODE (op1) != MEM \
2362 && (GET_CODE (op1) != CONST_INT \
2363 || SMALL_INT (op1))) \
2366 else if (RTX_OK_FOR_BASE_P (op0)) \
2368 if ((RTX_OK_FOR_INDEX_P (op1) \
2369 /* We prohibit REG + REG for TFmode when \
2370 there are no instructions which accept \
2371 REG+REG instructions. We do this \
2372 because REG+REG is not an offsetable \
2373 address. If we get the situation \
2374 in reload where source and destination \
2375 of a movtf pattern are both MEMs with \
2376 REG+REG address, then only one of them \
2377 gets converted to an offsetable \
2379 && (MODE != TFmode \
2380 || (TARGET_FPU && TARGET_ARCH64 \
2382 && TARGET_HARD_QUAD)) \
2383 /* We prohibit REG + REG on ARCH32 if \
2384 not optimizing for DFmode/DImode \
2385 because then mem_min_alignment is \
2386 likely to be zero after reload and the \
2387 forced split would lack a matching \
2388 splitter pattern. */ \
2389 && (TARGET_ARCH64 || optimize \
2390 || (MODE != DFmode \
2391 && MODE != DImode))) \
2392 || RTX_OK_FOR_OFFSET_P (op1)) \
2395 else if (RTX_OK_FOR_BASE_P (op1)) \
2397 if ((RTX_OK_FOR_INDEX_P (op0) \
2398 /* See the previous comment. */ \
2399 && (MODE != TFmode \
2400 || (TARGET_FPU && TARGET_ARCH64 \
2402 && TARGET_HARD_QUAD)) \
2403 && (TARGET_ARCH64 || optimize \
2404 || (MODE != DFmode \
2405 && MODE != DImode))) \
2406 || RTX_OK_FOR_OFFSET_P (op0)) \
2409 else if (USE_AS_OFFSETABLE_LO10 \
2410 && GET_CODE (op0) == LO_SUM \
2412 && ! TARGET_CM_MEDMID \
2413 && RTX_OK_FOR_OLO10_P (op1)) \
2415 register rtx op00 = XEXP (op0, 0); \
2416 register rtx op01 = XEXP (op0, 1); \
2417 if (RTX_OK_FOR_BASE_P (op00) \
2418 && CONSTANT_P (op01)) \
2421 else if (USE_AS_OFFSETABLE_LO10 \
2422 && GET_CODE (op1) == LO_SUM \
2424 && ! TARGET_CM_MEDMID \
2425 && RTX_OK_FOR_OLO10_P (op0)) \
2427 register rtx op10 = XEXP (op1, 0); \
2428 register rtx op11 = XEXP (op1, 1); \
2429 if (RTX_OK_FOR_BASE_P (op10) \
2430 && CONSTANT_P (op11)) \
2434 else if (GET_CODE (X) == LO_SUM) \
2436 register rtx op0 = XEXP (X, 0); \
2437 register rtx op1 = XEXP (X, 1); \
2438 if (RTX_OK_FOR_BASE_P (op0) \
2439 && CONSTANT_P (op1) \
2440 /* We can't allow TFmode, because an offset \
2441 greater than or equal to the alignment (8) \
2442 may cause the LO_SUM to overflow if !v9. */\
2443 && (MODE != TFmode || TARGET_V9)) \
2446 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2450 /* Try machine-dependent ways of modifying an illegitimate address
2451 to be legitimate. If we find one, return the new, valid address.
2452 This macro is used in only one place: `memory_address' in explow.c.
2454 OLDX is the address as it was before break_out_memory_refs was called.
2455 In some cases it is useful to look at this to decide what needs to be done.
2457 MODE and WIN are passed so that this macro can use
2458 GO_IF_LEGITIMATE_ADDRESS.
2460 It is always safe for this macro to do nothing. It exists to recognize
2461 opportunities to optimize the output. */
2463 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2464 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2465 { rtx sparc_x = (X); \
2466 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2467 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2468 force_operand (XEXP (X, 0), NULL_RTX)); \
2469 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2470 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2471 force_operand (XEXP (X, 1), NULL_RTX)); \
2472 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2473 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2475 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2476 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2477 force_operand (XEXP (X, 1), NULL_RTX)); \
2478 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2480 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2481 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2482 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2483 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2484 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2485 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2486 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2487 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2488 || GET_CODE (X) == LABEL_REF) \
2489 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2490 if (memory_address_p (MODE, X)) \
2493 /* Try a machine-dependent way of reloading an illegitimate address
2494 operand. If we find one, push the reload and jump to WIN. This
2495 macro is used in only one place: `find_reloads_address' in reload.c.
2497 For Sparc 32, we wish to handle addresses by splitting them into
2498 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2499 This cuts the number of extra insns by one.
2501 Do nothing when generating PIC code and the address is a
2502 symbolic operand or requires a scratch register. */
2504 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2506 /* Decompose SImode constants into hi+lo_sum. We do have to \
2507 rerecognize what we produce, so be careful. */ \
2508 if (CONSTANT_P (X) \
2509 && (MODE != TFmode || TARGET_V9) \
2510 && GET_MODE (X) == SImode \
2511 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2513 && (symbolic_operand (X, Pmode) \
2514 || pic_address_needs_scratch (X)))) \
2516 X = gen_rtx_LO_SUM (GET_MODE (X), \
2517 gen_rtx_HIGH (GET_MODE (X), X), X); \
2518 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2519 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2523 /* ??? 64-bit reloads. */ \
2526 /* Go to LABEL if ADDR (a legitimate address expression)
2527 has an effect that depends on the machine mode it is used for.
2528 On the SPARC this is never true. */
2530 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2532 /* If we are referencing a function make the SYMBOL_REF special.
2533 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2534 so we must not add it to function addresses. */
2536 #define ENCODE_SECTION_INFO(DECL) \
2538 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2539 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2542 /* Specify the machine mode that this machine uses
2543 for the index in the tablejump instruction. */
2544 /* If we ever implement any of the full models (such as CM_FULLANY),
2545 this has to be DImode in that case */
2546 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2547 #define CASE_VECTOR_MODE \
2548 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2550 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2551 we have to sign extend which slows things down. */
2552 #define CASE_VECTOR_MODE \
2553 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2556 /* Define as C expression which evaluates to nonzero if the tablejump
2557 instruction expects the table to contain offsets from the address of the
2559 Do not define this if the table should contain absolute addresses. */
2560 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2562 /* Specify the tree operation to be used to convert reals to integers. */
2563 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2565 /* This is the kind of divide that is easiest to do in the general case. */
2566 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2568 /* Define this as 1 if `char' should by default be signed; else as 0. */
2569 #define DEFAULT_SIGNED_CHAR 1
2571 /* Max number of bytes we can move from memory to memory
2572 in one reasonably fast instruction. */
2575 #if 0 /* Sun 4 has matherr, so this is no good. */
2576 /* This is the value of the error code EDOM for this machine,
2577 used by the sqrt instruction. */
2578 #define TARGET_EDOM 33
2580 /* This is how to refer to the variable errno. */
2581 #define GEN_ERRNO_RTX \
2582 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2585 /* Define if operations between registers always perform the operation
2586 on the full register even if a narrower mode is specified. */
2587 #define WORD_REGISTER_OPERATIONS
2589 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2590 will either zero-extend or sign-extend. The value of this macro should
2591 be the code that says which one of the two operations is implicitly
2592 done, NIL if none. */
2593 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2595 /* Nonzero if access to memory by bytes is slow and undesirable.
2596 For RISC chips, it means that access to memory by bytes is no
2597 better than access by words when possible, so grab a whole word
2598 and maybe make use of that. */
2599 #define SLOW_BYTE_ACCESS 1
2601 /* We assume that the store-condition-codes instructions store 0 for false
2602 and some other value for true. This is the value stored for true. */
2604 #define STORE_FLAG_VALUE 1
2606 /* When a prototype says `char' or `short', really pass an `int'. */
2607 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2609 /* Define this to be nonzero if shift instructions ignore all but the low-order
2611 #define SHIFT_COUNT_TRUNCATED 1
2613 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2614 is done just by pretending it is already truncated. */
2615 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2617 /* Specify the machine mode that pointers have.
2618 After generation of rtl, the compiler makes no further distinction
2619 between pointers and any other objects of this machine mode. */
2620 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2622 /* Generate calls to memcpy, memcmp and memset. */
2623 #define TARGET_MEM_FUNCTIONS
2625 /* Add any extra modes needed to represent the condition code.
2627 On the Sparc, we have a "no-overflow" mode which is used when an add or
2628 subtract insn is used to set the condition code. Different branches are
2629 used in this case for some operations.
2631 We also have two modes to indicate that the relevant condition code is
2632 in the floating-point condition code register. One for comparisons which
2633 will generate an exception if the result is unordered (CCFPEmode) and
2634 one for comparisons which will never trap (CCFPmode).
2636 CCXmode and CCX_NOOVmode are only used by v9. */
2638 #define EXTRA_CC_MODES \
2639 CC(CCXmode, "CCX") \
2640 CC(CC_NOOVmode, "CC_NOOV") \
2641 CC(CCX_NOOVmode, "CCX_NOOV") \
2642 CC(CCFPmode, "CCFP") \
2643 CC(CCFPEmode, "CCFPE")
2645 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2646 return the mode to be used for the comparison. For floating-point,
2647 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2648 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2649 processing is needed. */
2650 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2652 /* Return non-zero if MODE implies a floating point inequality can be
2653 reversed. For Sparc this is always true because we have a full
2654 compliment of ordered and unordered comparisons, but until generic
2655 code knows how to reverse it correctly we keep the old definition. */
2656 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2658 /* A function address in a call instruction for indexing purposes. */
2659 #define FUNCTION_MODE Pmode
2661 /* Define this if addresses of constant functions
2662 shouldn't be put through pseudo regs where they can be cse'd.
2663 Desirable on machines where ordinary constants are expensive
2664 but a CALL with constant address is cheap. */
2665 #define NO_FUNCTION_CSE
2667 /* alloca should avoid clobbering the old register save area. */
2668 #define SETJMP_VIA_SAVE_AREA
2670 /* Define subroutines to call to handle multiply and divide.
2671 Use the subroutines that Sun's library provides.
2672 The `*' prevents an underscore from being prepended by the compiler. */
2674 #define DIVSI3_LIBCALL "*.div"
2675 #define UDIVSI3_LIBCALL "*.udiv"
2676 #define MODSI3_LIBCALL "*.rem"
2677 #define UMODSI3_LIBCALL "*.urem"
2678 /* .umul is a little faster than .mul. */
2679 #define MULSI3_LIBCALL "*.umul"
2681 /* Define library calls for quad FP operations. These are all part of the
2683 #define ADDTF3_LIBCALL "_Q_add"
2684 #define SUBTF3_LIBCALL "_Q_sub"
2685 #define NEGTF2_LIBCALL "_Q_neg"
2686 #define MULTF3_LIBCALL "_Q_mul"
2687 #define DIVTF3_LIBCALL "_Q_div"
2688 #define FLOATSITF2_LIBCALL "_Q_itoq"
2689 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2690 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2691 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2692 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2693 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2694 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2695 #define EQTF2_LIBCALL "_Q_feq"
2696 #define NETF2_LIBCALL "_Q_fne"
2697 #define GTTF2_LIBCALL "_Q_fgt"
2698 #define GETF2_LIBCALL "_Q_fge"
2699 #define LTTF2_LIBCALL "_Q_flt"
2700 #define LETF2_LIBCALL "_Q_fle"
2702 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2703 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2704 and the compiler will notice and try to use the TFmode sqrt instruction
2705 for calls to the builtin function sqrt, but this fails. */
2706 #define INIT_TARGET_OPTABS \
2708 if (TARGET_ARCH32) \
2710 add_optab->handlers[(int) TFmode].libfunc \
2711 = init_one_libfunc (ADDTF3_LIBCALL); \
2712 sub_optab->handlers[(int) TFmode].libfunc \
2713 = init_one_libfunc (SUBTF3_LIBCALL); \
2714 neg_optab->handlers[(int) TFmode].libfunc \
2715 = init_one_libfunc (NEGTF2_LIBCALL); \
2716 smul_optab->handlers[(int) TFmode].libfunc \
2717 = init_one_libfunc (MULTF3_LIBCALL); \
2718 sdiv_optab->handlers[(int) TFmode].libfunc \
2719 = init_one_libfunc (DIVTF3_LIBCALL); \
2720 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2721 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2722 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2723 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2724 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2725 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2726 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2727 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2728 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2729 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2730 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2731 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2732 fixunstfsi_libfunc \
2733 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2735 sqrt_optab->handlers[(int) TFmode].libfunc \
2736 = init_one_libfunc ("_Q_sqrt"); \
2738 INIT_SUBTARGET_OPTABS; \
2741 /* This is meant to be redefined in the host dependent files */
2742 #define INIT_SUBTARGET_OPTABS
2744 /* Nonzero if a floating point comparison library call for
2745 mode MODE that will return a boolean value. Zero if one
2746 of the libgcc2 functions is used. */
2747 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2749 /* Compute the cost of computing a constant rtl expression RTX
2750 whose rtx-code is CODE. The body of this macro is a portion
2751 of a switch statement. If the code is computed here,
2752 return it with a return statement. Otherwise, break from the switch. */
2754 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2756 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2764 case CONST_DOUBLE: \
2765 if (GET_MODE (RTX) == DImode) \
2766 if ((XINT (RTX, 3) == 0 \
2767 && (unsigned) XINT (RTX, 2) < 0x1000) \
2768 || (XINT (RTX, 3) == -1 \
2769 && XINT (RTX, 2) < 0 \
2770 && XINT (RTX, 2) >= -0x1000)) \
2774 #define ADDRESS_COST(RTX) 1
2776 /* Compute extra cost of moving data between one register class
2778 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2779 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2780 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2781 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2782 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2783 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2785 /* Provide the costs of a rtl expression. This is in the body of a
2786 switch on CODE. The purpose for the cost of MULT is to encourage
2787 `synth_mult' to find a synthetic multiply when reasonable.
2789 If we need more than 12 insns to do a multiply, then go out-of-line,
2790 since the call overhead will be < 10% of the cost of the multiply. */
2792 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2794 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2795 return (GET_MODE (X) == DImode ? \
2796 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2797 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2802 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2803 return (GET_MODE (X) == DImode ? \
2804 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2805 return COSTS_N_INSNS (25); \
2806 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2807 so that cse will favor the latter. */ \
2812 /* Conditional branches with empty delay slots have a length of two. */
2813 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2815 if (GET_CODE (INSN) == CALL_INSN \
2816 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2820 /* Control the assembler format that we output. */
2822 /* Output at beginning of assembler file. */
2824 #define ASM_FILE_START(file)
2826 /* A C string constant describing how to begin a comment in the target
2827 assembler language. The compiler assumes that the comment will end at
2828 the end of the line. */
2830 #define ASM_COMMENT_START "!"
2832 /* Output to assembler file text saying following lines
2833 may contain character constants, extra white space, comments, etc. */
2835 #define ASM_APP_ON ""
2837 /* Output to assembler file text saying following lines
2838 no longer contain unusual constructs. */
2840 #define ASM_APP_OFF ""
2842 /* ??? Try to make the style consistent here (_OP?). */
2844 #define ASM_LONGLONG ".xword"
2845 #define ASM_LONG ".word"
2846 #define ASM_SHORT ".half"
2847 #define ASM_BYTE_OP "\t.byte\t"
2848 #define ASM_FLOAT ".single"
2849 #define ASM_DOUBLE ".double"
2850 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2852 /* How to refer to registers in assembler output.
2853 This sequence is indexed by compiler's hard-register-number (see above). */
2855 #define REGISTER_NAMES \
2856 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2857 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2858 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2859 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2860 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2861 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2862 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2863 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2864 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2865 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2866 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2867 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2868 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2870 /* Define additional names for use in asm clobbers and asm declarations. */
2872 #define ADDITIONAL_REGISTER_NAMES \
2873 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2875 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2876 can run past this up to a continuation point. Once we used 1500, but
2877 a single entry in C++ can run more than 500 bytes, due to the length of
2878 mangled symbol names. dbxout.c should really be fixed to do
2879 continuations when they are actually needed instead of trying to
2881 #define DBX_CONTIN_LENGTH 1000
2883 /* This is how to output the definition of a user-level label named NAME,
2884 such as the label on a static function or variable NAME. */
2886 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2887 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2889 /* This is how to output a command to make the user-level label named NAME
2890 defined for reference from other files. */
2892 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2893 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2895 /* The prefix to add to user-visible assembler symbols. */
2897 #define USER_LABEL_PREFIX "_"
2899 /* This is how to output a definition of an internal numbered label where
2900 PREFIX is the class of label and NUM is the number within the class. */
2902 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2903 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2905 /* This is how to store into the string LABEL
2906 the symbol_ref name of an internal numbered label where
2907 PREFIX is the class of label and NUM is the number within the class.
2908 This is suitable for output with `assemble_name'. */
2910 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2911 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2913 /* This is how to output an assembler line defining a `float' constant.
2914 We always have to use a .long pseudo-op to do this because the native
2915 SVR4 ELF assembler is buggy and it generates incorrect values when we
2916 try to use the .float pseudo-op instead. */
2918 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2922 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2923 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2924 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \
2925 ASM_COMMENT_START, str); \
2928 /* This is how to output an assembler line defining a `double' constant.
2929 We always have to use a .long pseudo-op to do this because the native
2930 SVR4 ELF assembler is buggy and it generates incorrect values when we
2931 try to use the .float pseudo-op instead. */
2933 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2937 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2938 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2939 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
2940 ASM_COMMENT_START, str); \
2941 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
2944 /* This is how to output an assembler line defining a `long double'
2947 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2951 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2952 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
2953 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
2954 ASM_COMMENT_START, str); \
2955 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
2956 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \
2957 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \
2960 /* This is how to output an assembler line defining an `int' constant. */
2962 #define ASM_OUTPUT_INT(FILE,VALUE) \
2963 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2964 output_addr_const (FILE, (VALUE)), \
2965 fprintf (FILE, "\n"))
2967 /* This is how to output an assembler line defining a DImode constant. */
2968 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2969 output_double_int (FILE, VALUE)
2971 /* Likewise for `char' and `short' constants. */
2973 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2974 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2975 output_addr_const (FILE, (VALUE)), \
2976 fprintf (FILE, "\n"))
2978 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2979 ( fprintf (FILE, "%s", ASM_BYTE_OP), \
2980 output_addr_const (FILE, (VALUE)), \
2981 fprintf (FILE, "\n"))
2983 /* This is how to output an assembler line for a numeric constant byte. */
2985 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2986 fprintf (FILE, "%s0x%x\n", ASM_BYTE_OP, (int)(VALUE))
2988 /* This is how we hook in and defer the case-vector until the end of
2990 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2991 sparc_defer_case_vector ((LAB),(VEC), 0)
2993 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2994 sparc_defer_case_vector ((LAB),(VEC), 1)
2996 /* This is how to output an element of a case-vector that is absolute. */
2998 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3001 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
3002 if (CASE_VECTOR_MODE == SImode) \
3003 fprintf (FILE, "\t.word\t"); \
3005 fprintf (FILE, "\t.xword\t"); \
3006 assemble_name (FILE, label); \
3007 fputc ('\n', FILE); \
3010 /* This is how to output an element of a case-vector that is relative.
3011 (SPARC uses such vectors only when generating PIC.) */
3013 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3016 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
3017 if (CASE_VECTOR_MODE == SImode) \
3018 fprintf (FILE, "\t.word\t"); \
3020 fprintf (FILE, "\t.xword\t"); \
3021 assemble_name (FILE, label); \
3022 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
3023 fputc ('-', FILE); \
3024 assemble_name (FILE, label); \
3025 fputc ('\n', FILE); \
3028 /* This is what to output before and after case-vector (both
3029 relative and absolute). If .subsection -1 works, we put case-vectors
3030 at the beginning of the current section. */
3032 #ifdef HAVE_GAS_SUBSECTION_ORDERING
3034 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
3035 fprintf(FILE, "\t.subsection\t-1\n")
3037 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
3038 fprintf(FILE, "\t.previous\n")
3042 /* This is how to output an assembler line
3043 that says to advance the location counter
3044 to a multiple of 2**LOG bytes. */
3046 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3048 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
3050 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
3051 fprintf (FILE, "\t.skip %u\n", (SIZE))
3053 /* This says how to output an assembler line
3054 to define a global common symbol. */
3056 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
3057 ( fputs ("\t.common ", (FILE)), \
3058 assemble_name ((FILE), (NAME)), \
3059 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
3061 /* This says how to output an assembler line to define a local common
3064 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
3065 ( fputs ("\t.reserve ", (FILE)), \
3066 assemble_name ((FILE), (NAME)), \
3067 fprintf ((FILE), ",%u,\"bss\",%u\n", \
3068 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
3070 /* A C statement (sans semicolon) to output to the stdio stream
3071 FILE the assembler definition of uninitialized global DECL named
3072 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
3073 Try to use asm_output_aligned_bss to implement this macro. */
3075 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3077 fputs (".globl ", (FILE)); \
3078 assemble_name ((FILE), (NAME)); \
3079 fputs ("\n", (FILE)); \
3080 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
3083 /* Store in OUTPUT a string (made with alloca) containing
3084 an assembler-name for a local static variable named NAME.
3085 LABELNO is an integer which is different for each call. */
3087 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3088 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3089 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3091 #define IDENT_ASM_OP "\t.ident\t"
3093 /* Output #ident as a .ident. */
3095 #define ASM_OUTPUT_IDENT(FILE, NAME) \
3096 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
3098 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
3099 Used for C++ multiple inheritance. */
3100 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
3105 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
3107 if ((DELTA) >= 4096 || (DELTA) < -4096) \
3108 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
3109 (int)(DELTA), reg, reg); \
3111 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
3112 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
3113 fprintf (FILE, "\tcall\t"); \
3114 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3115 fprintf (FILE, ", 0\n"); \
3116 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
3119 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3120 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
3122 /* Print operand X (an rtx) in assembler syntax to file FILE.
3123 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3124 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3126 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3128 /* Print a memory address as an operand to reference that memory location. */
3130 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3131 { register rtx base, index = 0; \
3133 register rtx addr = ADDR; \
3134 if (GET_CODE (addr) == REG) \
3135 fputs (reg_names[REGNO (addr)], FILE); \
3136 else if (GET_CODE (addr) == PLUS) \
3138 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
3139 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
3140 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
3141 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
3143 base = XEXP (addr, 0), index = XEXP (addr, 1); \
3144 if (GET_CODE (base) == LO_SUM) \
3146 if (! USE_AS_OFFSETABLE_LO10 \
3148 || TARGET_CM_MEDMID) \
3150 output_operand (XEXP (base, 0), 0); \
3151 fputs ("+%lo(", FILE); \
3152 output_address (XEXP (base, 1)); \
3153 fprintf (FILE, ")+%d", offset); \
3157 fputs (reg_names[REGNO (base)], FILE); \
3159 fprintf (FILE, "%+d", offset); \
3160 else if (GET_CODE (index) == REG) \
3161 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3162 else if (GET_CODE (index) == SYMBOL_REF \
3163 || GET_CODE (index) == CONST) \
3164 fputc ('+', FILE), output_addr_const (FILE, index); \
3168 else if (GET_CODE (addr) == MINUS \
3169 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3171 output_addr_const (FILE, XEXP (addr, 0)); \
3172 fputs ("-(", FILE); \
3173 output_addr_const (FILE, XEXP (addr, 1)); \
3174 fputs ("-.)", FILE); \
3176 else if (GET_CODE (addr) == LO_SUM) \
3178 output_operand (XEXP (addr, 0), 0); \
3179 if (TARGET_CM_MEDMID) \
3180 fputs ("+%l44(", FILE); \
3182 fputs ("+%lo(", FILE); \
3183 output_address (XEXP (addr, 1)); \
3184 fputc (')', FILE); \
3186 else if (flag_pic && GET_CODE (addr) == CONST \
3187 && GET_CODE (XEXP (addr, 0)) == MINUS \
3188 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3189 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3190 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3192 addr = XEXP (addr, 0); \
3193 output_addr_const (FILE, XEXP (addr, 0)); \
3194 /* Group the args of the second CONST in parenthesis. */ \
3195 fputs ("-(", FILE); \
3196 /* Skip past the second CONST--it does nothing for us. */\
3197 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3198 /* Close the parenthesis. */ \
3199 fputc (')', FILE); \
3203 output_addr_const (FILE, addr); \
3207 /* Define the codes that are matched by predicates in sparc.c. */
3209 #define PREDICATE_CODES \
3210 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3211 {"fp_zero_operand", {CONST_DOUBLE}}, \
3212 {"intreg_operand", {SUBREG, REG}}, \
3213 {"fcc_reg_operand", {REG}}, \
3214 {"icc_or_fcc_reg_operand", {REG}}, \
3215 {"restore_operand", {REG}}, \
3216 {"call_operand", {MEM}}, \
3217 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
3218 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
3219 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3220 {"symbolic_memory_operand", {SUBREG, MEM}}, \
3221 {"label_ref_operand", {LABEL_REF}}, \
3222 {"sp64_medium_pic_operand", {CONST}}, \
3223 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
3224 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
3225 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
3226 {"splittable_symbolic_memory_operand", {MEM}}, \
3227 {"splittable_immediate_memory_operand", {MEM}}, \
3228 {"eq_or_neq", {EQ, NE}}, \
3229 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
3230 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3231 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3232 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3233 {"cc_arithop", {AND, IOR, XOR}}, \
3234 {"cc_arithopn", {AND, IOR}}, \
3235 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3236 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3237 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3238 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3239 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3240 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3241 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3242 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3243 {"small_int", {CONST_INT}}, \
3244 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3245 {"uns_small_int", {CONST_INT}}, \
3246 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3247 {"clobbered_register", {REG}}, \
3248 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3249 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3250 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3252 /* The number of Pmode words for the setjmp buffer. */
3253 #define JMP_BUF_SIZE 12
3255 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)