1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static int apparent_fsize;
71 static int actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static int frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, int);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, int, const char *);
140 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
141 tree, int, int, int *, int *);
143 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
144 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
146 static void sparc_output_addr_vec (rtx);
147 static void sparc_output_addr_diff_vec (rtx);
148 static void sparc_output_deferred_case_vectors (void);
149 static int check_return_regs (rtx);
150 static int epilogue_renumber (rtx *, int);
151 static bool sparc_assemble_integer (rtx, unsigned int, int);
152 static int set_extends (rtx);
153 static void output_restore_regs (FILE *, int);
154 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
155 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
156 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
158 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
159 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
160 #ifdef OBJECT_FORMAT_ELF
161 static void sparc_elf_asm_named_section (const char *, unsigned int);
163 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
165 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
166 unsigned HOST_WIDE_INT)
169 static int sparc_adjust_cost (rtx, rtx, rtx, int);
170 static int sparc_issue_rate (void);
171 static void sparc_sched_init (FILE *, int, int);
172 static int sparc_use_dfa_pipeline_interface (void);
173 static int sparc_use_sched_lookahead (void);
175 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
176 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
177 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
178 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
179 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
181 static bool sparc_function_ok_for_sibcall (tree, tree);
182 static void sparc_init_libfuncs (void);
183 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
184 HOST_WIDE_INT, tree);
185 static struct machine_function * sparc_init_machine_status (void);
186 static bool sparc_cannot_force_const_mem (rtx);
187 static rtx sparc_tls_get_addr (void);
188 static rtx sparc_tls_got (void);
189 static const char *get_some_local_dynamic_name (void);
190 static int get_some_local_dynamic_name_1 (rtx *, void *);
191 static bool sparc_rtx_costs (rtx, int, int, int *);
193 /* Option handling. */
195 /* Code model option as passed by user. */
196 const char *sparc_cmodel_string;
198 enum cmodel sparc_cmodel;
200 char sparc_hard_reg_printed[8];
202 struct sparc_cpu_select sparc_select[] =
204 /* switch name, tune arch */
205 { (char *)0, "default", 1, 1 },
206 { (char *)0, "-mcpu=", 1, 1 },
207 { (char *)0, "-mtune=", 1, 0 },
211 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
212 enum processor_type sparc_cpu;
214 /* Initialize the GCC target structure. */
216 /* The sparc default is to use .half rather than .short for aligned
217 HI objects. Use .word instead of .long on non-ELF systems. */
218 #undef TARGET_ASM_ALIGNED_HI_OP
219 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
220 #ifndef OBJECT_FORMAT_ELF
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
225 #undef TARGET_ASM_UNALIGNED_HI_OP
226 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
227 #undef TARGET_ASM_UNALIGNED_SI_OP
228 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
229 #undef TARGET_ASM_UNALIGNED_DI_OP
230 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
232 /* The target hook has to handle DI-mode values. */
233 #undef TARGET_ASM_INTEGER
234 #define TARGET_ASM_INTEGER sparc_assemble_integer
236 #undef TARGET_ASM_FUNCTION_PROLOGUE
237 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
238 #undef TARGET_ASM_FUNCTION_EPILOGUE
239 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
243 #undef TARGET_SCHED_ISSUE_RATE
244 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
245 #undef TARGET_SCHED_INIT
246 #define TARGET_SCHED_INIT sparc_sched_init
247 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
248 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
249 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
250 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
252 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
253 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
255 #undef TARGET_INIT_LIBFUNCS
256 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
259 #undef TARGET_HAVE_TLS
260 #define TARGET_HAVE_TLS true
262 #undef TARGET_CANNOT_FORCE_CONST_MEM
263 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
265 #undef TARGET_ASM_OUTPUT_MI_THUNK
266 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
267 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
268 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS sparc_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST hook_int_rtx_0
275 struct gcc_target targetm = TARGET_INITIALIZER;
277 /* Validate and override various options, and do some machine dependent
281 sparc_override_options (void)
283 static struct code_model {
284 const char *const name;
286 } const cmodels[] = {
288 { "medlow", CM_MEDLOW },
289 { "medmid", CM_MEDMID },
290 { "medany", CM_MEDANY },
291 { "embmedany", CM_EMBMEDANY },
294 const struct code_model *cmodel;
295 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
296 static struct cpu_default {
298 const char *const name;
299 } const cpu_default[] = {
300 /* There must be one entry here for each TARGET_CPU value. */
301 { TARGET_CPU_sparc, "cypress" },
302 { TARGET_CPU_sparclet, "tsc701" },
303 { TARGET_CPU_sparclite, "f930" },
304 { TARGET_CPU_v8, "v8" },
305 { TARGET_CPU_hypersparc, "hypersparc" },
306 { TARGET_CPU_sparclite86x, "sparclite86x" },
307 { TARGET_CPU_supersparc, "supersparc" },
308 { TARGET_CPU_v9, "v9" },
309 { TARGET_CPU_ultrasparc, "ultrasparc" },
310 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
313 const struct cpu_default *def;
314 /* Table of values for -m{cpu,tune}=. */
315 static struct cpu_table {
316 const char *const name;
317 const enum processor_type processor;
320 } const cpu_table[] = {
321 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
322 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
323 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
324 /* TI TMS390Z55 supersparc */
325 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
326 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
327 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
328 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
329 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
330 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
331 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
332 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
334 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
336 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
337 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
338 /* TI ultrasparc I, II, IIi */
339 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
340 /* Although insns using %y are deprecated, it is a clear win on current
342 |MASK_DEPRECATED_V8_INSNS},
343 /* TI ultrasparc III */
344 /* ??? Check if %y issue still holds true in ultra3. */
345 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
348 const struct cpu_table *cpu;
349 const struct sparc_cpu_select *sel;
352 #ifndef SPARC_BI_ARCH
353 /* Check for unsupported architecture size. */
354 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
355 error ("%s is not supported by this configuration",
356 DEFAULT_ARCH32_P ? "-m64" : "-m32");
359 /* We force all 64bit archs to use 128 bit long double */
360 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
362 error ("-mlong-double-64 not allowed with -m64");
363 target_flags |= MASK_LONG_DOUBLE_128;
366 /* Code model selection. */
367 sparc_cmodel = SPARC_DEFAULT_CMODEL;
371 sparc_cmodel = CM_32;
374 if (sparc_cmodel_string != NULL)
378 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
379 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
381 if (cmodel->name == NULL)
382 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
384 sparc_cmodel = cmodel->value;
387 error ("-mcmodel= is not supported on 32 bit systems");
390 fpu = TARGET_FPU; /* save current -mfpu status */
392 /* Set the default CPU. */
393 for (def = &cpu_default[0]; def->name; ++def)
394 if (def->cpu == TARGET_CPU_DEFAULT)
398 sparc_select[0].string = def->name;
400 for (sel = &sparc_select[0]; sel->name; ++sel)
404 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
405 if (! strcmp (sel->string, cpu->name))
408 sparc_cpu = cpu->processor;
412 target_flags &= ~cpu->disable;
413 target_flags |= cpu->enable;
419 error ("bad value (%s) for %s switch", sel->string, sel->name);
423 /* If -mfpu or -mno-fpu was explicitly used, don't override with
424 the processor default. Clear MASK_FPU_SET to avoid confusing
425 the reverse mapping from switch values to names. */
428 target_flags = (target_flags & ~MASK_FPU) | fpu;
429 target_flags &= ~MASK_FPU_SET;
432 /* Don't allow -mvis if FPU is disabled. */
434 target_flags &= ~MASK_VIS;
436 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
438 -m64 also implies v9. */
439 if (TARGET_VIS || TARGET_ARCH64)
441 target_flags |= MASK_V9;
442 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
445 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
446 if (TARGET_V9 && TARGET_ARCH32)
447 target_flags |= MASK_DEPRECATED_V8_INSNS;
449 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
450 if (! TARGET_V9 || TARGET_ARCH64)
451 target_flags &= ~MASK_V8PLUS;
453 /* Don't use stack biasing in 32 bit mode. */
455 target_flags &= ~MASK_STACK_BIAS;
457 /* Supply a default value for align_functions. */
458 if (align_functions == 0
459 && (sparc_cpu == PROCESSOR_ULTRASPARC
460 || sparc_cpu == PROCESSOR_ULTRASPARC3))
461 align_functions = 32;
463 /* Validate PCC_STRUCT_RETURN. */
464 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
465 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
467 /* Only use .uaxword when compiling for a 64-bit target. */
469 targetm.asm_out.unaligned_op.di = NULL;
471 /* Do various machine dependent initializations. */
474 /* Set up function hooks. */
475 init_machine_status = sparc_init_machine_status;
478 /* Miscellaneous utilities. */
480 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
481 or branch on register contents instructions. */
484 v9_regcmp_p (enum rtx_code code)
486 return (code == EQ || code == NE || code == GE || code == LT
487 || code == LE || code == GT);
491 /* Operand constraints. */
493 /* Return nonzero only if OP is a register of mode MODE,
497 reg_or_0_operand (rtx op, enum machine_mode mode)
499 if (register_operand (op, mode))
501 if (op == const0_rtx)
503 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
504 && CONST_DOUBLE_HIGH (op) == 0
505 && CONST_DOUBLE_LOW (op) == 0)
507 if (fp_zero_operand (op, mode))
512 /* Return nonzero only if OP is const1_rtx. */
515 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
517 return op == const1_rtx;
520 /* Nonzero if OP is a floating point value with value 0.0. */
523 fp_zero_operand (rtx op, enum machine_mode mode)
525 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
527 return op == CONST0_RTX (mode);
530 /* Nonzero if OP is a register operand in floating point register. */
533 fp_register_operand (rtx op, enum machine_mode mode)
535 if (! register_operand (op, mode))
537 if (GET_CODE (op) == SUBREG)
538 op = SUBREG_REG (op);
539 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
542 /* Nonzero if OP is a floating point constant which can
543 be loaded into an integer register using a single
544 sethi instruction. */
549 if (GET_CODE (op) == CONST_DOUBLE)
554 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
555 if (REAL_VALUES_EQUAL (r, dconst0) &&
556 ! REAL_VALUE_MINUS_ZERO (r))
558 REAL_VALUE_TO_TARGET_SINGLE (r, i);
559 if (SPARC_SETHI_P (i))
566 /* Nonzero if OP is a floating point constant which can
567 be loaded into an integer register using a single
573 if (GET_CODE (op) == CONST_DOUBLE)
578 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
579 if (REAL_VALUES_EQUAL (r, dconst0) &&
580 ! REAL_VALUE_MINUS_ZERO (r))
582 REAL_VALUE_TO_TARGET_SINGLE (r, i);
583 if (SPARC_SIMM13_P (i))
590 /* Nonzero if OP is a floating point constant which can
591 be loaded into an integer register using a high/losum
592 instruction sequence. */
595 fp_high_losum_p (rtx op)
597 /* The constraints calling this should only be in
598 SFmode move insns, so any constant which cannot
599 be moved using a single insn will do. */
600 if (GET_CODE (op) == CONST_DOUBLE)
605 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
606 if (REAL_VALUES_EQUAL (r, dconst0) &&
607 ! REAL_VALUE_MINUS_ZERO (r))
609 REAL_VALUE_TO_TARGET_SINGLE (r, i);
610 if (! SPARC_SETHI_P (i)
611 && ! SPARC_SIMM13_P (i))
618 /* Nonzero if OP is an integer register. */
621 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
623 return (register_operand (op, SImode)
624 || (TARGET_ARCH64 && register_operand (op, DImode)));
627 /* Nonzero if OP is a floating point condition code register. */
630 fcc_reg_operand (rtx op, enum machine_mode mode)
632 /* This can happen when recog is called from combine. Op may be a MEM.
633 Fail instead of calling abort in this case. */
634 if (GET_CODE (op) != REG)
637 if (mode != VOIDmode && mode != GET_MODE (op))
640 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
643 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
644 if (reg_renumber == 0)
645 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
646 return REGNO_OK_FOR_CCFP_P (REGNO (op));
648 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
652 /* Nonzero if OP is a floating point condition code fcc0 register. */
655 fcc0_reg_operand (rtx op, enum machine_mode mode)
657 /* This can happen when recog is called from combine. Op may be a MEM.
658 Fail instead of calling abort in this case. */
659 if (GET_CODE (op) != REG)
662 if (mode != VOIDmode && mode != GET_MODE (op))
665 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
668 return REGNO (op) == SPARC_FCC_REG;
671 /* Nonzero if OP is an integer or floating point condition code register. */
674 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
676 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
678 if (mode != VOIDmode && mode != GET_MODE (op))
681 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
686 return fcc_reg_operand (op, mode);
689 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
691 restore_operand (rtx op, enum machine_mode mode)
693 return (GET_CODE (op) == REG && GET_MODE (op) == mode
694 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
697 /* Call insn on SPARC can take a PC-relative constant address, or any regular
701 call_operand (rtx op, enum machine_mode mode)
703 if (GET_CODE (op) != MEM)
706 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
710 call_operand_address (rtx op, enum machine_mode mode)
712 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
715 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
716 otherwise return 0. */
719 tls_symbolic_operand (rtx op)
721 if (GET_CODE (op) != SYMBOL_REF)
723 return SYMBOL_REF_TLS_MODEL (op);
727 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
729 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
733 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
735 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
739 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
741 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
745 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
747 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
750 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
751 reference and a constant. */
754 symbolic_operand (register rtx op, enum machine_mode mode)
756 enum machine_mode omode = GET_MODE (op);
758 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
761 switch (GET_CODE (op))
764 return !SYMBOL_REF_TLS_MODEL (op);
771 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
772 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
773 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
774 && GET_CODE (XEXP (op, 1)) == CONST_INT);
781 /* Return truth value of statement that OP is a symbolic memory
782 operand of mode MODE. */
785 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
787 if (GET_CODE (op) == SUBREG)
788 op = SUBREG_REG (op);
789 if (GET_CODE (op) != MEM)
792 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
793 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
794 || GET_CODE (op) == LABEL_REF);
797 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
800 label_ref_operand (rtx op, enum machine_mode mode)
802 if (GET_CODE (op) != LABEL_REF)
804 if (GET_MODE (op) != mode)
809 /* Return 1 if the operand is an argument used in generating pic references
810 in either the medium/low or medium/anywhere code models of sparc64. */
813 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
815 /* Check for (const (minus (symbol_ref:GOT)
816 (const (minus (label) (pc))))). */
817 if (GET_CODE (op) != CONST)
820 if (GET_CODE (op) != MINUS)
822 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
824 /* ??? Ensure symbol is GOT. */
825 if (GET_CODE (XEXP (op, 1)) != CONST)
827 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
832 /* Return 1 if the operand is a data segment reference. This includes
833 the readonly data segment, or in other words anything but the text segment.
834 This is needed in the medium/anywhere code model on v9. These values
835 are accessed with EMBMEDANY_BASE_REG. */
838 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
840 switch (GET_CODE (op))
843 return ! SYMBOL_REF_FUNCTION_P (op);
845 /* Assume canonical format of symbol + constant.
848 return data_segment_operand (XEXP (op, 0), VOIDmode);
854 /* Return 1 if the operand is a text segment reference.
855 This is needed in the medium/anywhere code model on v9. */
858 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
860 switch (GET_CODE (op))
865 return SYMBOL_REF_FUNCTION_P (op);
867 /* Assume canonical format of symbol + constant.
870 return text_segment_operand (XEXP (op, 0), VOIDmode);
876 /* Return 1 if the operand is either a register or a memory operand that is
880 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
882 if (register_operand (op, mode))
885 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
892 splittable_symbolic_memory_operand (rtx op,
893 enum machine_mode mode ATTRIBUTE_UNUSED)
895 if (GET_CODE (op) != MEM)
897 if (! symbolic_operand (XEXP (op, 0), Pmode))
903 splittable_immediate_memory_operand (rtx op,
904 enum machine_mode mode ATTRIBUTE_UNUSED)
906 if (GET_CODE (op) != MEM)
908 if (! immediate_operand (XEXP (op, 0), Pmode))
913 /* Return truth value of whether OP is EQ or NE. */
916 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
918 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
921 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
922 or LTU for non-floating-point. We handle those specially. */
925 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
927 enum rtx_code code = GET_CODE (op);
929 if (GET_RTX_CLASS (code) != '<')
932 if (GET_MODE (XEXP (op, 0)) == CCFPmode
933 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
936 return (code != NE && code != EQ && code != GEU && code != LTU);
939 /* Return 1 if this is a comparison operator. This allows the use of
940 MATCH_OPERATOR to recognize all the branch insns. */
943 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
945 enum rtx_code code = GET_CODE (op);
947 if (GET_RTX_CLASS (code) != '<')
950 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
951 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
952 /* These are the only branches which work with CC_NOOVmode. */
953 return (code == EQ || code == NE || code == GE || code == LT);
957 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
958 MATCH_OPERATOR to recognize all the branch insns. */
961 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
963 enum rtx_code code = GET_CODE (op);
968 if (GET_RTX_CLASS (code) != '<')
971 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
972 /* These are the only branches which work with CCX_NOOVmode. */
973 return (code == EQ || code == NE || code == GE || code == LT);
974 return (GET_MODE (XEXP (op, 0)) == CCXmode);
977 /* Nonzero if OP is a comparison operator suitable for use in v9
978 conditional move or branch on register contents instructions. */
981 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
983 enum rtx_code code = GET_CODE (op);
985 if (GET_RTX_CLASS (code) != '<')
988 return v9_regcmp_p (code);
991 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
994 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
996 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
999 /* Return nonzero if OP is an operator of mode MODE which can set
1000 the condition codes explicitly. We do not include PLUS and MINUS
1001 because these require CC_NOOVmode, which we handle explicitly. */
1004 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1006 if (GET_CODE (op) == AND
1007 || GET_CODE (op) == IOR
1008 || GET_CODE (op) == XOR)
1014 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1015 complement its second operand and set the condition codes explicitly. */
1018 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1020 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1021 and (xor ... (not ...)) to (not (xor ...)). */
1022 return (GET_CODE (op) == AND
1023 || GET_CODE (op) == IOR);
1026 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1027 signed 13 bit immediate field. This is an acceptable SImode operand for
1028 most 3 address instructions. */
1031 arith_operand (rtx op, enum machine_mode mode)
1033 if (register_operand (op, mode))
1035 if (GET_CODE (op) != CONST_INT)
1037 return SMALL_INT32 (op);
1040 /* Return true if OP is a constant 4096 */
1043 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1045 if (GET_CODE (op) != CONST_INT)
1048 return INTVAL (op) == 4096;
1051 /* Return true if OP is suitable as second operand for add/sub */
1054 arith_add_operand (rtx op, enum machine_mode mode)
1056 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1059 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1060 immediate field of OR and XOR instructions. Used for 64-bit
1061 constant formation patterns. */
1063 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1065 return ((GET_CODE (op) == CONST_INT
1066 && SPARC_SIMM13_P (INTVAL (op)))
1067 #if HOST_BITS_PER_WIDE_INT != 64
1068 || (GET_CODE (op) == CONST_DOUBLE
1069 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1070 && (CONST_DOUBLE_HIGH (op) ==
1071 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1072 (HOST_WIDE_INT)-1 : 0)))
1077 /* The same, but only for sethi instructions. */
1079 const64_high_operand (rtx op, enum machine_mode mode)
1081 return ((GET_CODE (op) == CONST_INT
1082 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1083 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1085 || (GET_CODE (op) == CONST_DOUBLE
1086 && CONST_DOUBLE_HIGH (op) == 0
1087 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1088 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1091 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1092 signed 11 bit immediate field. This is an acceptable SImode operand for
1093 the movcc instructions. */
1096 arith11_operand (rtx op, enum machine_mode mode)
1098 return (register_operand (op, mode)
1099 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1102 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1103 signed 10 bit immediate field. This is an acceptable SImode operand for
1104 the movrcc instructions. */
1107 arith10_operand (rtx op, enum machine_mode mode)
1109 return (register_operand (op, mode)
1110 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1113 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1114 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1116 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1117 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1118 for most 3 address instructions. */
1121 arith_double_operand (rtx op, enum machine_mode mode)
1123 return (register_operand (op, mode)
1124 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1126 && GET_CODE (op) == CONST_DOUBLE
1127 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1128 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1130 && GET_CODE (op) == CONST_DOUBLE
1131 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1132 && ((CONST_DOUBLE_HIGH (op) == -1
1133 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1134 || (CONST_DOUBLE_HIGH (op) == 0
1135 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1138 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1141 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1143 return (TARGET_ARCH64 &&
1144 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1145 (GET_CODE (op) == CONST_DOUBLE &&
1146 CONST_DOUBLE_LOW (op) == 4096 &&
1147 CONST_DOUBLE_HIGH (op) == 0)));
1150 /* Return true if OP is suitable as second operand for add/sub in DImode */
1153 arith_double_add_operand (rtx op, enum machine_mode mode)
1155 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1158 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1159 can fit in an 11 bit immediate field. This is an acceptable DImode
1160 operand for the movcc instructions. */
1161 /* ??? Replace with arith11_operand? */
1164 arith11_double_operand (rtx op, enum machine_mode mode)
1166 return (register_operand (op, mode)
1167 || (GET_CODE (op) == CONST_DOUBLE
1168 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1169 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1170 && ((CONST_DOUBLE_HIGH (op) == -1
1171 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1172 || (CONST_DOUBLE_HIGH (op) == 0
1173 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1174 || (GET_CODE (op) == CONST_INT
1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1176 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1179 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1180 can fit in an 10 bit immediate field. This is an acceptable DImode
1181 operand for the movrcc instructions. */
1182 /* ??? Replace with arith10_operand? */
1185 arith10_double_operand (rtx op, enum machine_mode mode)
1187 return (register_operand (op, mode)
1188 || (GET_CODE (op) == CONST_DOUBLE
1189 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1190 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1191 && ((CONST_DOUBLE_HIGH (op) == -1
1192 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1193 || (CONST_DOUBLE_HIGH (op) == 0
1194 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1195 || (GET_CODE (op) == CONST_INT
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1200 /* Return truth value of whether OP is an integer which fits the
1201 range constraining immediate operands in most three-address insns,
1202 which have a 13 bit immediate field. */
1205 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1207 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1211 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1213 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1214 || (GET_CODE (op) == CONST_DOUBLE
1215 && CONST_DOUBLE_HIGH (op) == 0
1216 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1219 /* Recognize operand values for the umul instruction. That instruction sign
1220 extends immediate values just like all other sparc instructions, but
1221 interprets the extended result as an unsigned number. */
1224 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 #if HOST_BITS_PER_WIDE_INT > 32
1227 /* All allowed constants will fit a CONST_INT. */
1228 return (GET_CODE (op) == CONST_INT
1229 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1230 || (INTVAL (op) >= 0xFFFFF000
1231 && INTVAL (op) <= 0xFFFFFFFF)));
1233 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1234 || (GET_CODE (op) == CONST_DOUBLE
1235 && CONST_DOUBLE_HIGH (op) == 0
1236 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1241 uns_arith_operand (rtx op, enum machine_mode mode)
1243 return register_operand (op, mode) || uns_small_int (op, mode);
1246 /* Return truth value of statement that OP is a call-clobbered register. */
1248 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1250 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1253 /* Return 1 if OP is a valid operand for the source of a move insn. */
1256 input_operand (rtx op, enum machine_mode mode)
1258 /* If both modes are non-void they must be the same. */
1259 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1262 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1263 if (GET_CODE (op) == CONSTANT_P_RTX)
1266 /* Allow any one instruction integer constant, and all CONST_INT
1267 variants when we are working in DImode and !arch64. */
1268 if (GET_MODE_CLASS (mode) == MODE_INT
1269 && ((GET_CODE (op) == CONST_INT
1270 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1271 || SPARC_SIMM13_P (INTVAL (op))
1273 && ! TARGET_ARCH64)))
1275 && GET_CODE (op) == CONST_DOUBLE
1276 && ((CONST_DOUBLE_HIGH (op) == 0
1277 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1279 #if HOST_BITS_PER_WIDE_INT == 64
1280 (CONST_DOUBLE_HIGH (op) == 0
1281 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1283 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1284 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1285 && CONST_DOUBLE_HIGH (op) == 0)
1286 || (CONST_DOUBLE_HIGH (op) == -1
1287 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1292 /* If !arch64 and this is a DImode const, allow it so that
1293 the splits can be generated. */
1296 && GET_CODE (op) == CONST_DOUBLE)
1299 if (register_operand (op, mode))
1302 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1303 && GET_CODE (op) == CONST_DOUBLE)
1306 /* If this is a SUBREG, look inside so that we handle
1307 paradoxical ones. */
1308 if (GET_CODE (op) == SUBREG)
1309 op = SUBREG_REG (op);
1311 /* Check for valid MEM forms. */
1312 if (GET_CODE (op) == MEM)
1314 rtx inside = XEXP (op, 0);
1316 if (GET_CODE (inside) == LO_SUM)
1318 /* We can't allow these because all of the splits
1319 (eventually as they trickle down into DFmode
1320 splits) require offsettable memory references. */
1322 && GET_MODE (op) == TFmode)
1325 return (register_operand (XEXP (inside, 0), Pmode)
1326 && CONSTANT_P (XEXP (inside, 1)));
1328 return memory_address_p (mode, inside);
1335 /* We know it can't be done in one insn when we get here,
1336 the movsi expander guarantees this. */
1338 sparc_emit_set_const32 (rtx op0, rtx op1)
1340 enum machine_mode mode = GET_MODE (op0);
1343 if (GET_CODE (op1) == CONST_INT)
1345 HOST_WIDE_INT value = INTVAL (op1);
1347 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1348 || SPARC_SIMM13_P (value))
1352 /* Full 2-insn decomposition is needed. */
1353 if (reload_in_progress || reload_completed)
1356 temp = gen_reg_rtx (mode);
1358 if (GET_CODE (op1) == CONST_INT)
1360 /* Emit them as real moves instead of a HIGH/LO_SUM,
1361 this way CSE can see everything and reuse intermediate
1362 values if it wants. */
1364 && HOST_BITS_PER_WIDE_INT != 64
1365 && (INTVAL (op1) & 0x80000000) != 0)
1366 emit_insn (gen_rtx_SET
1368 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1371 emit_insn (gen_rtx_SET (VOIDmode, temp,
1372 GEN_INT (INTVAL (op1)
1373 & ~(HOST_WIDE_INT)0x3ff)));
1375 emit_insn (gen_rtx_SET (VOIDmode,
1377 gen_rtx_IOR (mode, temp,
1378 GEN_INT (INTVAL (op1) & 0x3ff))));
1382 /* A symbol, emit in the traditional way. */
1383 emit_insn (gen_rtx_SET (VOIDmode, temp,
1384 gen_rtx_HIGH (mode, op1)));
1385 emit_insn (gen_rtx_SET (VOIDmode,
1386 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1392 /* SPARC-v9 code-model support. */
1394 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1398 if (temp1 && GET_MODE (temp1) == TImode)
1401 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1404 switch (sparc_cmodel)
1407 /* The range spanned by all instructions in the object is less
1408 than 2^31 bytes (2GB) and the distance from any instruction
1409 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1410 than 2^31 bytes (2GB).
1412 The executable must be in the low 4TB of the virtual address
1415 sethi %hi(symbol), %temp
1416 or %temp, %lo(symbol), %reg */
1417 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1418 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1422 /* The range spanned by all instructions in the object is less
1423 than 2^31 bytes (2GB) and the distance from any instruction
1424 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1425 than 2^31 bytes (2GB).
1427 The executable must be in the low 16TB of the virtual address
1430 sethi %h44(symbol), %temp1
1431 or %temp1, %m44(symbol), %temp2
1432 sllx %temp2, 12, %temp3
1433 or %temp3, %l44(symbol), %reg */
1434 emit_insn (gen_seth44 (op0, op1));
1435 emit_insn (gen_setm44 (op0, op0, op1));
1436 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1437 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1438 emit_insn (gen_setl44 (op0, temp1, op1));
1442 /* The range spanned by all instructions in the object is less
1443 than 2^31 bytes (2GB) and the distance from any instruction
1444 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1445 than 2^31 bytes (2GB).
1447 The executable can be placed anywhere in the virtual address
1450 sethi %hh(symbol), %temp1
1451 sethi %lm(symbol), %temp2
1452 or %temp1, %hm(symbol), %temp3
1453 or %temp2, %lo(symbol), %temp4
1454 sllx %temp3, 32, %temp5
1455 or %temp4, %temp5, %reg */
1457 /* It is possible that one of the registers we got for operands[2]
1458 might coincide with that of operands[0] (which is why we made
1459 it TImode). Pick the other one to use as our scratch. */
1460 if (rtx_equal_p (temp1, op0))
1463 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1468 emit_insn (gen_sethh (op0, op1));
1469 emit_insn (gen_setlm (temp1, op1));
1470 emit_insn (gen_sethm (op0, op0, op1));
1471 emit_insn (gen_rtx_SET (VOIDmode, op0,
1472 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1473 emit_insn (gen_rtx_SET (VOIDmode, op0,
1474 gen_rtx_PLUS (DImode, op0, temp1)));
1475 emit_insn (gen_setlo (op0, op0, op1));
1479 /* Old old old backwards compatibility kruft here.
1480 Essentially it is MEDLOW with a fixed 64-bit
1481 virtual base added to all data segment addresses.
1482 Text-segment stuff is computed like MEDANY, we can't
1483 reuse the code above because the relocation knobs
1486 Data segment: sethi %hi(symbol), %temp1
1487 or %temp1, %lo(symbol), %temp2
1488 add %temp2, EMBMEDANY_BASE_REG, %reg
1490 Text segment: sethi %uhi(symbol), %temp1
1491 sethi %hi(symbol), %temp2
1492 or %temp1, %ulo(symbol), %temp3
1493 or %temp2, %lo(symbol), %temp4
1494 sllx %temp3, 32, %temp5
1495 or %temp4, %temp5, %reg */
1496 if (data_segment_operand (op1, GET_MODE (op1)))
1498 emit_insn (gen_embmedany_sethi (temp1, op1));
1499 emit_insn (gen_embmedany_brsum (op0, temp1));
1500 emit_insn (gen_embmedany_losum (op0, op0, op1));
1504 /* It is possible that one of the registers we got for operands[2]
1505 might coincide with that of operands[0] (which is why we made
1506 it TImode). Pick the other one to use as our scratch. */
1507 if (rtx_equal_p (temp1, op0))
1510 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1515 emit_insn (gen_embmedany_textuhi (op0, op1));
1516 emit_insn (gen_embmedany_texthi (temp1, op1));
1517 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1518 emit_insn (gen_rtx_SET (VOIDmode, op0,
1519 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1520 emit_insn (gen_rtx_SET (VOIDmode, op0,
1521 gen_rtx_PLUS (DImode, op0, temp1)));
1522 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1531 /* These avoid problems when cross compiling. If we do not
1532 go through all this hair then the optimizer will see
1533 invalid REG_EQUAL notes or in some cases none at all. */
1534 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1535 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1536 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1537 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1539 #if HOST_BITS_PER_WIDE_INT == 64
1540 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1541 #define GEN_INT64(__x) GEN_INT (__x)
1543 #define GEN_HIGHINT64(__x) \
1544 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1545 #define GEN_INT64(__x) \
1546 immed_double_const ((__x) & 0xffffffff, \
1547 ((__x) & 0x80000000 ? -1 : 0), DImode)
1550 /* The optimizer is not to assume anything about exactly
1551 which bits are set for a HIGH, they are unspecified.
1552 Unfortunately this leads to many missed optimizations
1553 during CSE. We mask out the non-HIGH bits, and matches
1554 a plain movdi, to alleviate this problem. */
1556 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1558 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1562 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1564 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1568 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1570 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1574 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1576 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1579 /* Worker routines for 64-bit constant formation on arch64.
1580 One of the key things to be doing in these emissions is
1581 to create as many temp REGs as possible. This makes it
1582 possible for half-built constants to be used later when
1583 such values are similar to something required later on.
1584 Without doing this, the optimizer cannot see such
1587 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1588 unsigned HOST_WIDE_INT, int);
1591 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1592 unsigned HOST_WIDE_INT low_bits, int is_neg)
1594 unsigned HOST_WIDE_INT high_bits;
1597 high_bits = (~low_bits) & 0xffffffff;
1599 high_bits = low_bits;
1601 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1604 emit_insn (gen_rtx_SET (VOIDmode, op0,
1605 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1609 /* If we are XOR'ing with -1, then we should emit a one's complement
1610 instead. This way the combiner will notice logical operations
1611 such as ANDN later on and substitute. */
1612 if ((low_bits & 0x3ff) == 0x3ff)
1614 emit_insn (gen_rtx_SET (VOIDmode, op0,
1615 gen_rtx_NOT (DImode, temp)));
1619 emit_insn (gen_rtx_SET (VOIDmode, op0,
1620 gen_safe_XOR64 (temp,
1621 (-(HOST_WIDE_INT)0x400
1622 | (low_bits & 0x3ff)))));
1627 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1628 unsigned HOST_WIDE_INT, int);
1631 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1632 unsigned HOST_WIDE_INT high_bits,
1633 unsigned HOST_WIDE_INT low_immediate,
1638 if ((high_bits & 0xfffffc00) != 0)
1640 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1641 if ((high_bits & ~0xfffffc00) != 0)
1642 emit_insn (gen_rtx_SET (VOIDmode, op0,
1643 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1649 emit_insn (gen_safe_SET64 (temp, high_bits));
1653 /* Now shift it up into place. */
1654 emit_insn (gen_rtx_SET (VOIDmode, op0,
1655 gen_rtx_ASHIFT (DImode, temp2,
1656 GEN_INT (shift_count))));
1658 /* If there is a low immediate part piece, finish up by
1659 putting that in as well. */
1660 if (low_immediate != 0)
1661 emit_insn (gen_rtx_SET (VOIDmode, op0,
1662 gen_safe_OR64 (op0, low_immediate)));
1665 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1666 unsigned HOST_WIDE_INT);
1668 /* Full 64-bit constant decomposition. Even though this is the
1669 'worst' case, we still optimize a few things away. */
1671 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1672 unsigned HOST_WIDE_INT high_bits,
1673 unsigned HOST_WIDE_INT low_bits)
1677 if (reload_in_progress || reload_completed)
1680 sub_temp = gen_reg_rtx (DImode);
1682 if ((high_bits & 0xfffffc00) != 0)
1684 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1685 if ((high_bits & ~0xfffffc00) != 0)
1686 emit_insn (gen_rtx_SET (VOIDmode,
1688 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1694 emit_insn (gen_safe_SET64 (temp, high_bits));
1698 if (!reload_in_progress && !reload_completed)
1700 rtx temp2 = gen_reg_rtx (DImode);
1701 rtx temp3 = gen_reg_rtx (DImode);
1702 rtx temp4 = gen_reg_rtx (DImode);
1704 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1705 gen_rtx_ASHIFT (DImode, sub_temp,
1708 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1709 if ((low_bits & ~0xfffffc00) != 0)
1711 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1712 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1713 emit_insn (gen_rtx_SET (VOIDmode, op0,
1714 gen_rtx_PLUS (DImode, temp4, temp3)));
1718 emit_insn (gen_rtx_SET (VOIDmode, op0,
1719 gen_rtx_PLUS (DImode, temp4, temp2)));
1724 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1725 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1726 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1729 /* We are in the middle of reload, so this is really
1730 painful. However we do still make an attempt to
1731 avoid emitting truly stupid code. */
1732 if (low1 != const0_rtx)
1734 emit_insn (gen_rtx_SET (VOIDmode, op0,
1735 gen_rtx_ASHIFT (DImode, sub_temp,
1736 GEN_INT (to_shift))));
1737 emit_insn (gen_rtx_SET (VOIDmode, op0,
1738 gen_rtx_IOR (DImode, op0, low1)));
1746 if (low2 != const0_rtx)
1748 emit_insn (gen_rtx_SET (VOIDmode, op0,
1749 gen_rtx_ASHIFT (DImode, sub_temp,
1750 GEN_INT (to_shift))));
1751 emit_insn (gen_rtx_SET (VOIDmode, op0,
1752 gen_rtx_IOR (DImode, op0, low2)));
1760 emit_insn (gen_rtx_SET (VOIDmode, op0,
1761 gen_rtx_ASHIFT (DImode, sub_temp,
1762 GEN_INT (to_shift))));
1763 if (low3 != const0_rtx)
1764 emit_insn (gen_rtx_SET (VOIDmode, op0,
1765 gen_rtx_IOR (DImode, op0, low3)));
1770 /* Analyze a 64-bit constant for certain properties. */
1771 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1772 unsigned HOST_WIDE_INT,
1773 int *, int *, int *);
1776 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1777 unsigned HOST_WIDE_INT low_bits,
1778 int *hbsp, int *lbsp, int *abbasp)
1780 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1783 lowest_bit_set = highest_bit_set = -1;
1787 if ((lowest_bit_set == -1)
1788 && ((low_bits >> i) & 1))
1790 if ((highest_bit_set == -1)
1791 && ((high_bits >> (32 - i - 1)) & 1))
1792 highest_bit_set = (64 - i - 1);
1795 && ((highest_bit_set == -1)
1796 || (lowest_bit_set == -1)));
1802 if ((lowest_bit_set == -1)
1803 && ((high_bits >> i) & 1))
1804 lowest_bit_set = i + 32;
1805 if ((highest_bit_set == -1)
1806 && ((low_bits >> (32 - i - 1)) & 1))
1807 highest_bit_set = 32 - i - 1;
1810 && ((highest_bit_set == -1)
1811 || (lowest_bit_set == -1)));
1813 /* If there are no bits set this should have gone out
1814 as one instruction! */
1815 if (lowest_bit_set == -1
1816 || highest_bit_set == -1)
1818 all_bits_between_are_set = 1;
1819 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1823 if ((low_bits & (1 << i)) != 0)
1828 if ((high_bits & (1 << (i - 32))) != 0)
1831 all_bits_between_are_set = 0;
1834 *hbsp = highest_bit_set;
1835 *lbsp = lowest_bit_set;
1836 *abbasp = all_bits_between_are_set;
1839 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1842 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1843 unsigned HOST_WIDE_INT low_bits)
1845 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1848 || high_bits == 0xffffffff)
1851 analyze_64bit_constant (high_bits, low_bits,
1852 &highest_bit_set, &lowest_bit_set,
1853 &all_bits_between_are_set);
1855 if ((highest_bit_set == 63
1856 || lowest_bit_set == 0)
1857 && all_bits_between_are_set != 0)
1860 if ((highest_bit_set - lowest_bit_set) < 21)
1866 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1867 unsigned HOST_WIDE_INT,
1870 static unsigned HOST_WIDE_INT
1871 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1872 unsigned HOST_WIDE_INT low_bits,
1873 int lowest_bit_set, int shift)
1875 HOST_WIDE_INT hi, lo;
1877 if (lowest_bit_set < 32)
1879 lo = (low_bits >> lowest_bit_set) << shift;
1880 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1885 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1892 /* Here we are sure to be arch64 and this is an integer constant
1893 being loaded into a register. Emit the most efficient
1894 insn sequence possible. Detection of all the 1-insn cases
1895 has been done already. */
1897 sparc_emit_set_const64 (rtx op0, rtx op1)
1899 unsigned HOST_WIDE_INT high_bits, low_bits;
1900 int lowest_bit_set, highest_bit_set;
1901 int all_bits_between_are_set;
1904 /* Sanity check that we know what we are working with. */
1905 if (! TARGET_ARCH64)
1908 if (GET_CODE (op0) != SUBREG)
1910 if (GET_CODE (op0) != REG
1911 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1912 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1916 if (reload_in_progress || reload_completed)
1919 temp = gen_reg_rtx (DImode);
1921 if (GET_CODE (op1) != CONST_DOUBLE
1922 && GET_CODE (op1) != CONST_INT)
1924 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1928 if (GET_CODE (op1) == CONST_DOUBLE)
1930 #if HOST_BITS_PER_WIDE_INT == 64
1931 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1932 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1934 high_bits = CONST_DOUBLE_HIGH (op1);
1935 low_bits = CONST_DOUBLE_LOW (op1);
1940 #if HOST_BITS_PER_WIDE_INT == 64
1941 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1942 low_bits = (INTVAL (op1) & 0xffffffff);
1944 high_bits = ((INTVAL (op1) < 0) ?
1947 low_bits = INTVAL (op1);
1951 /* low_bits bits 0 --> 31
1952 high_bits bits 32 --> 63 */
1954 analyze_64bit_constant (high_bits, low_bits,
1955 &highest_bit_set, &lowest_bit_set,
1956 &all_bits_between_are_set);
1958 /* First try for a 2-insn sequence. */
1960 /* These situations are preferred because the optimizer can
1961 * do more things with them:
1963 * sllx %reg, shift, %reg
1965 * srlx %reg, shift, %reg
1966 * 3) mov some_small_const, %reg
1967 * sllx %reg, shift, %reg
1969 if (((highest_bit_set == 63
1970 || lowest_bit_set == 0)
1971 && all_bits_between_are_set != 0)
1972 || ((highest_bit_set - lowest_bit_set) < 12))
1974 HOST_WIDE_INT the_const = -1;
1975 int shift = lowest_bit_set;
1977 if ((highest_bit_set != 63
1978 && lowest_bit_set != 0)
1979 || all_bits_between_are_set == 0)
1982 create_simple_focus_bits (high_bits, low_bits,
1985 else if (lowest_bit_set == 0)
1986 shift = -(63 - highest_bit_set);
1988 if (! SPARC_SIMM13_P (the_const))
1991 emit_insn (gen_safe_SET64 (temp, the_const));
1993 emit_insn (gen_rtx_SET (VOIDmode,
1995 gen_rtx_ASHIFT (DImode,
1999 emit_insn (gen_rtx_SET (VOIDmode,
2001 gen_rtx_LSHIFTRT (DImode,
2003 GEN_INT (-shift))));
2009 /* Now a range of 22 or less bits set somewhere.
2010 * 1) sethi %hi(focus_bits), %reg
2011 * sllx %reg, shift, %reg
2012 * 2) sethi %hi(focus_bits), %reg
2013 * srlx %reg, shift, %reg
2015 if ((highest_bit_set - lowest_bit_set) < 21)
2017 unsigned HOST_WIDE_INT focus_bits =
2018 create_simple_focus_bits (high_bits, low_bits,
2019 lowest_bit_set, 10);
2021 if (! SPARC_SETHI_P (focus_bits))
2024 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2026 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2027 if (lowest_bit_set < 10)
2028 emit_insn (gen_rtx_SET (VOIDmode,
2030 gen_rtx_LSHIFTRT (DImode, temp,
2031 GEN_INT (10 - lowest_bit_set))));
2032 else if (lowest_bit_set > 10)
2033 emit_insn (gen_rtx_SET (VOIDmode,
2035 gen_rtx_ASHIFT (DImode, temp,
2036 GEN_INT (lowest_bit_set - 10))));
2042 /* 1) sethi %hi(low_bits), %reg
2043 * or %reg, %lo(low_bits), %reg
2044 * 2) sethi %hi(~low_bits), %reg
2045 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2048 || high_bits == 0xffffffff)
2050 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2051 (high_bits == 0xffffffff));
2055 /* Now, try 3-insn sequences. */
2057 /* 1) sethi %hi(high_bits), %reg
2058 * or %reg, %lo(high_bits), %reg
2059 * sllx %reg, 32, %reg
2063 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2067 /* We may be able to do something quick
2068 when the constant is negated, so try that. */
2069 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2070 (~low_bits) & 0xfffffc00))
2072 /* NOTE: The trailing bits get XOR'd so we need the
2073 non-negated bits, not the negated ones. */
2074 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2076 if ((((~high_bits) & 0xffffffff) == 0
2077 && ((~low_bits) & 0x80000000) == 0)
2078 || (((~high_bits) & 0xffffffff) == 0xffffffff
2079 && ((~low_bits) & 0x80000000) != 0))
2081 int fast_int = (~low_bits & 0xffffffff);
2083 if ((SPARC_SETHI_P (fast_int)
2084 && (~high_bits & 0xffffffff) == 0)
2085 || SPARC_SIMM13_P (fast_int))
2086 emit_insn (gen_safe_SET64 (temp, fast_int));
2088 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2093 #if HOST_BITS_PER_WIDE_INT == 64
2094 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2095 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2097 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2098 (~high_bits) & 0xffffffff,
2101 sparc_emit_set_const64 (temp, negated_const);
2104 /* If we are XOR'ing with -1, then we should emit a one's complement
2105 instead. This way the combiner will notice logical operations
2106 such as ANDN later on and substitute. */
2107 if (trailing_bits == 0x3ff)
2109 emit_insn (gen_rtx_SET (VOIDmode, op0,
2110 gen_rtx_NOT (DImode, temp)));
2114 emit_insn (gen_rtx_SET (VOIDmode,
2116 gen_safe_XOR64 (temp,
2117 (-0x400 | trailing_bits))));
2122 /* 1) sethi %hi(xxx), %reg
2123 * or %reg, %lo(xxx), %reg
2124 * sllx %reg, yyy, %reg
2126 * ??? This is just a generalized version of the low_bits==0
2127 * thing above, FIXME...
2129 if ((highest_bit_set - lowest_bit_set) < 32)
2131 unsigned HOST_WIDE_INT focus_bits =
2132 create_simple_focus_bits (high_bits, low_bits,
2135 /* We can't get here in this state. */
2136 if (highest_bit_set < 32
2137 || lowest_bit_set >= 32)
2140 /* So what we know is that the set bits straddle the
2141 middle of the 64-bit word. */
2142 sparc_emit_set_const64_quick2 (op0, temp,
2148 /* 1) sethi %hi(high_bits), %reg
2149 * or %reg, %lo(high_bits), %reg
2150 * sllx %reg, 32, %reg
2151 * or %reg, low_bits, %reg
2153 if (SPARC_SIMM13_P(low_bits)
2154 && ((int)low_bits > 0))
2156 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2160 /* The easiest way when all else fails, is full decomposition. */
2162 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2163 high_bits, low_bits, ~high_bits, ~low_bits);
2165 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2168 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2169 return the mode to be used for the comparison. For floating-point,
2170 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2171 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2172 processing is needed. */
2175 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2177 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2203 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2204 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2206 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2207 return CCX_NOOVmode;
2213 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2220 /* X and Y are two things to compare using CODE. Emit the compare insn and
2221 return the rtx for the cc reg in the proper mode. */
2224 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2226 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2229 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2230 fcc regs (cse can't tell they're really call clobbered regs and will
2231 remove a duplicate comparison even if there is an intervening function
2232 call - it will then try to reload the cc reg via an int reg which is why
2233 we need the movcc patterns). It is possible to provide the movcc
2234 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2235 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2236 to tell cse that CCFPE mode registers (even pseudos) are call
2239 /* ??? This is an experiment. Rather than making changes to cse which may
2240 or may not be easy/clean, we do our own cse. This is possible because
2241 we will generate hard registers. Cse knows they're call clobbered (it
2242 doesn't know the same thing about pseudos). If we guess wrong, no big
2243 deal, but if we win, great! */
2245 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2246 #if 1 /* experiment */
2249 /* We cycle through the registers to ensure they're all exercised. */
2250 static int next_fcc_reg = 0;
2251 /* Previous x,y for each fcc reg. */
2252 static rtx prev_args[4][2];
2254 /* Scan prev_args for x,y. */
2255 for (reg = 0; reg < 4; reg++)
2256 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2261 prev_args[reg][0] = x;
2262 prev_args[reg][1] = y;
2263 next_fcc_reg = (next_fcc_reg + 1) & 3;
2265 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2268 cc_reg = gen_reg_rtx (mode);
2269 #endif /* ! experiment */
2270 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2271 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2273 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2275 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2276 gen_rtx_COMPARE (mode, x, y)));
2281 /* This function is used for v9 only.
2282 CODE is the code for an Scc's comparison.
2283 OPERANDS[0] is the target of the Scc insn.
2284 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2285 been generated yet).
2287 This function is needed to turn
2290 (gt (reg:CCX 100 %icc)
2294 (gt:DI (reg:CCX 100 %icc)
2297 IE: The instruction recognizer needs to see the mode of the comparison to
2298 find the right instruction. We could use "gt:DI" right in the
2299 define_expand, but leaving it out allows us to handle DI, SI, etc.
2301 We refer to the global sparc compare operands sparc_compare_op0 and
2302 sparc_compare_op1. */
2305 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2310 && (GET_MODE (sparc_compare_op0) == DImode
2311 || GET_MODE (operands[0]) == DImode))
2314 op0 = sparc_compare_op0;
2315 op1 = sparc_compare_op1;
2317 /* Try to use the movrCC insns. */
2319 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2320 && op1 == const0_rtx
2321 && v9_regcmp_p (compare_code))
2323 /* Special case for op0 != 0. This can be done with one instruction if
2324 operands[0] == sparc_compare_op0. */
2326 if (compare_code == NE
2327 && GET_MODE (operands[0]) == DImode
2328 && rtx_equal_p (op0, operands[0]))
2330 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2331 gen_rtx_IF_THEN_ELSE (DImode,
2332 gen_rtx_fmt_ee (compare_code, DImode,
2339 if (reg_overlap_mentioned_p (operands[0], op0))
2341 /* Handle the case where operands[0] == sparc_compare_op0.
2342 We "early clobber" the result. */
2343 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2344 emit_move_insn (op0, sparc_compare_op0);
2347 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2348 if (GET_MODE (op0) != DImode)
2350 temp = gen_reg_rtx (DImode);
2351 convert_move (temp, op0, 0);
2355 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2356 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2357 gen_rtx_fmt_ee (compare_code, DImode,
2365 operands[1] = gen_compare_reg (compare_code, op0, op1);
2367 switch (GET_MODE (operands[1]))
2377 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2378 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2379 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2380 gen_rtx_fmt_ee (compare_code,
2381 GET_MODE (operands[1]),
2382 operands[1], const0_rtx),
2383 const1_rtx, operands[0])));
2388 /* Emit a conditional jump insn for the v9 architecture using comparison code
2389 CODE and jump target LABEL.
2390 This function exists to take advantage of the v9 brxx insns. */
2393 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2395 emit_jump_insn (gen_rtx_SET (VOIDmode,
2397 gen_rtx_IF_THEN_ELSE (VOIDmode,
2398 gen_rtx_fmt_ee (code, GET_MODE (op0),
2400 gen_rtx_LABEL_REF (VOIDmode, label),
2404 /* Generate a DFmode part of a hard TFmode register.
2405 REG is the TFmode hard register, LOW is 1 for the
2406 low 64bit of the register and 0 otherwise.
2409 gen_df_reg (rtx reg, int low)
2411 int regno = REGNO (reg);
2413 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2414 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2415 return gen_rtx_REG (DFmode, regno);
2418 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2419 Unlike normal calls, TFmode operands are passed by reference. It is
2420 assumed that no more than 3 operands are required. */
2423 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2425 rtx ret_slot = NULL, arg[3], func_sym;
2428 /* We only expect to be called for conversions, unary, and binary ops. */
2429 if (nargs < 2 || nargs > 3)
2432 for (i = 0; i < nargs; ++i)
2434 rtx this_arg = operands[i];
2437 /* TFmode arguments and return values are passed by reference. */
2438 if (GET_MODE (this_arg) == TFmode)
2440 int force_stack_temp;
2442 force_stack_temp = 0;
2443 if (TARGET_BUGGY_QP_LIB && i == 0)
2444 force_stack_temp = 1;
2446 if (GET_CODE (this_arg) == MEM
2447 && ! force_stack_temp)
2448 this_arg = XEXP (this_arg, 0);
2449 else if (CONSTANT_P (this_arg)
2450 && ! force_stack_temp)
2452 this_slot = force_const_mem (TFmode, this_arg);
2453 this_arg = XEXP (this_slot, 0);
2457 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2459 /* Operand 0 is the return value. We'll copy it out later. */
2461 emit_move_insn (this_slot, this_arg);
2463 ret_slot = this_slot;
2465 this_arg = XEXP (this_slot, 0);
2472 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2474 if (GET_MODE (operands[0]) == TFmode)
2477 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2478 arg[0], GET_MODE (arg[0]),
2479 arg[1], GET_MODE (arg[1]));
2481 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2482 arg[0], GET_MODE (arg[0]),
2483 arg[1], GET_MODE (arg[1]),
2484 arg[2], GET_MODE (arg[2]));
2487 emit_move_insn (operands[0], ret_slot);
2496 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2497 GET_MODE (operands[0]), 1,
2498 arg[1], GET_MODE (arg[1]));
2500 if (ret != operands[0])
2501 emit_move_insn (operands[0], ret);
2505 /* Expand soft-float TFmode calls to sparc abi routines. */
2508 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2530 emit_soft_tfmode_libcall (func, 3, operands);
2534 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2547 emit_soft_tfmode_libcall (func, 2, operands);
2551 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2558 switch (GET_MODE (operands[1]))
2571 case FLOAT_TRUNCATE:
2572 switch (GET_MODE (operands[0]))
2586 switch (GET_MODE (operands[1]))
2599 case UNSIGNED_FLOAT:
2600 switch (GET_MODE (operands[1]))
2614 switch (GET_MODE (operands[0]))
2628 switch (GET_MODE (operands[0]))
2645 emit_soft_tfmode_libcall (func, 2, operands);
2648 /* Expand a hard-float tfmode operation. All arguments must be in
2652 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2656 if (GET_RTX_CLASS (code) == '1')
2658 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2659 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2663 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2664 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2665 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2666 operands[1], operands[2]);
2669 if (register_operand (operands[0], VOIDmode))
2672 dest = gen_reg_rtx (GET_MODE (operands[0]));
2674 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2676 if (dest != operands[0])
2677 emit_move_insn (operands[0], dest);
2681 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2683 if (TARGET_HARD_QUAD)
2684 emit_hard_tfmode_operation (code, operands);
2686 emit_soft_tfmode_binop (code, operands);
2690 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2692 if (TARGET_HARD_QUAD)
2693 emit_hard_tfmode_operation (code, operands);
2695 emit_soft_tfmode_unop (code, operands);
2699 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2701 if (TARGET_HARD_QUAD)
2702 emit_hard_tfmode_operation (code, operands);
2704 emit_soft_tfmode_cvt (code, operands);
2707 /* Return nonzero if a return peephole merging return with
2708 setting of output register is ok. */
2710 leaf_return_peephole_ok (void)
2712 return (actual_fsize == 0);
2715 /* Return nonzero if a branch/jump/call instruction will be emitting
2716 nop into its delay slot. */
2719 empty_delay_slot (rtx insn)
2723 /* If no previous instruction (should not happen), return true. */
2724 if (PREV_INSN (insn) == NULL)
2727 seq = NEXT_INSN (PREV_INSN (insn));
2728 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2734 /* Return nonzero if TRIAL can go into the function epilogue's
2735 delay slot. SLOT is the slot we are trying to fill. */
2738 eligible_for_epilogue_delay (rtx trial, int slot)
2745 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2748 if (get_attr_length (trial) != 1)
2751 /* If there are any call-saved registers, we should scan TRIAL if it
2752 does not reference them. For now just make it easy. */
2756 /* If the function uses __builtin_eh_return, the eh_return machinery
2757 occupies the delay slot. */
2758 if (current_function_calls_eh_return)
2761 /* In the case of a true leaf function, anything can go into the delay slot.
2762 A delay slot only exists however if the frame size is zero, otherwise
2763 we will put an insn to adjust the stack after the return. */
2764 if (current_function_uses_only_leaf_regs)
2766 if (leaf_return_peephole_ok ())
2767 return ((get_attr_in_uncond_branch_delay (trial)
2768 == IN_BRANCH_DELAY_TRUE));
2772 pat = PATTERN (trial);
2774 /* Otherwise, only operations which can be done in tandem with
2775 a `restore' or `return' insn can go into the delay slot. */
2776 if (GET_CODE (SET_DEST (pat)) != REG
2777 || REGNO (SET_DEST (pat)) < 24)
2780 /* If this instruction sets up floating point register and we have a return
2781 instruction, it can probably go in. But restore will not work
2783 if (REGNO (SET_DEST (pat)) >= 32)
2785 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2786 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2791 /* The set of insns matched here must agree precisely with the set of
2792 patterns paired with a RETURN in sparc.md. */
2794 src = SET_SRC (pat);
2796 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2797 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2798 && arith_operand (src, GET_MODE (src)))
2801 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2803 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2806 /* This matches "*return_di". */
2807 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2808 && arith_double_operand (src, GET_MODE (src)))
2809 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2811 /* This matches "*return_sf_no_fpu". */
2812 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2813 && register_operand (src, SFmode))
2816 /* If we have return instruction, anything that does not use
2817 local or output registers and can go into a delay slot wins. */
2818 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2819 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2822 /* This matches "*return_addsi". */
2823 else if (GET_CODE (src) == PLUS
2824 && arith_operand (XEXP (src, 0), SImode)
2825 && arith_operand (XEXP (src, 1), SImode)
2826 && (register_operand (XEXP (src, 0), SImode)
2827 || register_operand (XEXP (src, 1), SImode)))
2830 /* This matches "*return_adddi". */
2831 else if (GET_CODE (src) == PLUS
2832 && arith_double_operand (XEXP (src, 0), DImode)
2833 && arith_double_operand (XEXP (src, 1), DImode)
2834 && (register_operand (XEXP (src, 0), DImode)
2835 || register_operand (XEXP (src, 1), DImode)))
2838 /* This can match "*return_losum_[sd]i".
2839 Catch only some cases, so that return_losum* don't have
2841 else if (GET_CODE (src) == LO_SUM
2842 && ! TARGET_CM_MEDMID
2843 && ((register_operand (XEXP (src, 0), SImode)
2844 && immediate_operand (XEXP (src, 1), SImode))
2846 && register_operand (XEXP (src, 0), DImode)
2847 && immediate_operand (XEXP (src, 1), DImode))))
2850 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2851 else if (GET_CODE (src) == ASHIFT
2852 && (register_operand (XEXP (src, 0), SImode)
2853 || register_operand (XEXP (src, 0), DImode))
2854 && XEXP (src, 1) == const1_rtx)
2860 /* Return nonzero if TRIAL can go into the call delay slot. */
2862 tls_call_delay (rtx trial)
2867 call __tls_get_addr, %tgd_call (foo)
2868 add %l7, %o0, %o0, %tgd_add (foo)
2869 while Sun as/ld does not. */
2870 if (TARGET_GNU_TLS || !TARGET_TLS)
2873 pat = PATTERN (trial);
2874 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2877 unspec = XEXP (SET_DEST (pat), 1);
2878 if (GET_CODE (unspec) != UNSPEC
2879 || (XINT (unspec, 1) != UNSPEC_TLSGD
2880 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2886 /* Return nonzero if TRIAL can go into the sibling call
2890 eligible_for_sibcall_delay (rtx trial)
2894 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2897 if (get_attr_length (trial) != 1)
2900 pat = PATTERN (trial);
2902 if (current_function_uses_only_leaf_regs)
2904 /* If the tail call is done using the call instruction,
2905 we have to restore %o7 in the delay slot. */
2906 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2909 /* %g1 is used to build the function address */
2910 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2916 /* Otherwise, only operations which can be done in tandem with
2917 a `restore' insn can go into the delay slot. */
2918 if (GET_CODE (SET_DEST (pat)) != REG
2919 || REGNO (SET_DEST (pat)) < 24
2920 || REGNO (SET_DEST (pat)) >= 32)
2923 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2925 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2928 src = SET_SRC (pat);
2930 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2931 && arith_operand (src, GET_MODE (src)))
2934 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2936 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2939 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2940 && arith_double_operand (src, GET_MODE (src)))
2941 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2943 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2944 && register_operand (src, SFmode))
2947 else if (GET_CODE (src) == PLUS
2948 && arith_operand (XEXP (src, 0), SImode)
2949 && arith_operand (XEXP (src, 1), SImode)
2950 && (register_operand (XEXP (src, 0), SImode)
2951 || register_operand (XEXP (src, 1), SImode)))
2954 else if (GET_CODE (src) == PLUS
2955 && arith_double_operand (XEXP (src, 0), DImode)
2956 && arith_double_operand (XEXP (src, 1), DImode)
2957 && (register_operand (XEXP (src, 0), DImode)
2958 || register_operand (XEXP (src, 1), DImode)))
2961 else if (GET_CODE (src) == LO_SUM
2962 && ! TARGET_CM_MEDMID
2963 && ((register_operand (XEXP (src, 0), SImode)
2964 && immediate_operand (XEXP (src, 1), SImode))
2966 && register_operand (XEXP (src, 0), DImode)
2967 && immediate_operand (XEXP (src, 1), DImode))))
2970 else if (GET_CODE (src) == ASHIFT
2971 && (register_operand (XEXP (src, 0), SImode)
2972 || register_operand (XEXP (src, 0), DImode))
2973 && XEXP (src, 1) == const1_rtx)
2980 check_return_regs (rtx x)
2982 switch (GET_CODE (x))
2985 return IN_OR_GLOBAL_P (x);
3000 if (check_return_regs (XEXP (x, 1)) == 0)
3005 return check_return_regs (XEXP (x, 0));
3014 short_branch (int uid1, int uid2)
3016 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3018 /* Leave a few words of "slop". */
3019 if (delta >= -1023 && delta <= 1022)
3025 /* Return nonzero if REG is not used after INSN.
3026 We assume REG is a reload reg, and therefore does
3027 not live past labels or calls or jumps. */
3029 reg_unused_after (rtx reg, rtx insn)
3031 enum rtx_code code, prev_code = UNKNOWN;
3033 while ((insn = NEXT_INSN (insn)))
3035 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3038 code = GET_CODE (insn);
3039 if (GET_CODE (insn) == CODE_LABEL)
3042 if (GET_RTX_CLASS (code) == 'i')
3044 rtx set = single_set (insn);
3045 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3048 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3050 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3058 /* Determine if it's legal to put X into the constant pool. This
3059 is not possible if X contains the address of a symbol that is
3060 not constant (TLS) or not known at final link time (PIC). */
3063 sparc_cannot_force_const_mem (rtx x)
3065 switch (GET_CODE (x))
3069 /* Accept all non-symbolic constants. */
3073 /* Labels are OK iff we are non-PIC. */
3074 return flag_pic != 0;
3077 /* 'Naked' TLS symbol references are never OK,
3078 non-TLS symbols are OK iff we are non-PIC. */
3079 if (SYMBOL_REF_TLS_MODEL (x))
3082 return flag_pic != 0;
3085 return sparc_cannot_force_const_mem (XEXP (x, 0));
3088 return sparc_cannot_force_const_mem (XEXP (x, 0))
3089 || sparc_cannot_force_const_mem (XEXP (x, 1));
3097 /* The table we use to reference PIC data. */
3098 static GTY(()) rtx global_offset_table;
3100 /* The function we use to get at it. */
3101 static GTY(()) rtx get_pc_symbol;
3102 static char get_pc_symbol_name[256];
3104 /* Ensure that we are not using patterns that are not OK with PIC. */
3112 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3113 || (GET_CODE (recog_data.operand[i]) == CONST
3114 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3115 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3116 == global_offset_table)
3117 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3126 /* Return true if X is an address which needs a temporary register when
3127 reloaded while generating PIC code. */
3130 pic_address_needs_scratch (rtx x)
3132 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3133 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3134 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3135 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3136 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3142 /* Determine if a given RTX is a valid constant. We already know this
3143 satisfies CONSTANT_P. */
3146 legitimate_constant_p (rtx x)
3150 switch (GET_CODE (x))
3153 /* TLS symbols are not constant. */
3154 if (SYMBOL_REF_TLS_MODEL (x))
3159 inner = XEXP (x, 0);
3161 /* Offsets of TLS symbols are never valid.
3162 Discourage CSE from creating them. */
3163 if (GET_CODE (inner) == PLUS
3164 && tls_symbolic_operand (XEXP (inner, 0)))
3169 if (GET_MODE (x) == VOIDmode)
3172 /* Floating point constants are generally not ok.
3173 The only exception is 0.0 in VIS. */
3175 && (GET_MODE (x) == SFmode
3176 || GET_MODE (x) == DFmode
3177 || GET_MODE (x) == TFmode)
3178 && fp_zero_operand (x, GET_MODE (x)))
3190 /* Determine if a given RTX is a valid constant address. */
3193 constant_address_p (rtx x)
3195 switch (GET_CODE (x))
3203 if (flag_pic && pic_address_needs_scratch (x))
3205 return legitimate_constant_p (x);
3208 return !flag_pic && legitimate_constant_p (x);
3215 /* Nonzero if the constant value X is a legitimate general operand
3216 when generating PIC code. It is given that flag_pic is on and
3217 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3220 legitimate_pic_operand_p (rtx x)
3222 if (pic_address_needs_scratch (x))
3224 if (tls_symbolic_operand (x)
3225 || (GET_CODE (x) == CONST
3226 && GET_CODE (XEXP (x, 0)) == PLUS
3227 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3232 /* Return nonzero if ADDR is a valid memory address.
3233 STRICT specifies whether strict register checking applies. */
3236 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3238 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3240 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3242 else if (GET_CODE (addr) == PLUS)
3244 rs1 = XEXP (addr, 0);
3245 rs2 = XEXP (addr, 1);
3247 /* Canonicalize. REG comes first, if there are no regs,
3248 LO_SUM comes first. */
3250 && GET_CODE (rs1) != SUBREG
3252 || GET_CODE (rs2) == SUBREG
3253 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3255 rs1 = XEXP (addr, 1);
3256 rs2 = XEXP (addr, 0);
3260 && rs1 == pic_offset_table_rtx
3262 && GET_CODE (rs2) != SUBREG
3263 && GET_CODE (rs2) != LO_SUM
3264 && GET_CODE (rs2) != MEM
3265 && !tls_symbolic_operand (rs2)
3266 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3267 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3269 || GET_CODE (rs1) == SUBREG)
3270 && RTX_OK_FOR_OFFSET_P (rs2)))
3275 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3276 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3278 /* We prohibit REG + REG for TFmode when there are no instructions
3279 which accept REG+REG instructions. We do this because REG+REG
3280 is not an offsetable address. If we get the situation in reload
3281 where source and destination of a movtf pattern are both MEMs with
3282 REG+REG address, then only one of them gets converted to an
3283 offsetable address. */
3285 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3286 && TARGET_HARD_QUAD))
3289 /* We prohibit REG + REG on ARCH32 if not optimizing for
3290 DFmode/DImode because then mem_min_alignment is likely to be zero
3291 after reload and the forced split would lack a matching splitter
3293 if (TARGET_ARCH32 && !optimize
3294 && (mode == DFmode || mode == DImode))
3297 else if (USE_AS_OFFSETABLE_LO10
3298 && GET_CODE (rs1) == LO_SUM
3300 && ! TARGET_CM_MEDMID
3301 && RTX_OK_FOR_OLO10_P (rs2))
3305 imm1 = XEXP (rs1, 1);
3306 rs1 = XEXP (rs1, 0);
3307 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3311 else if (GET_CODE (addr) == LO_SUM)
3313 rs1 = XEXP (addr, 0);
3314 imm1 = XEXP (addr, 1);
3316 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3319 /* We can't allow TFmode, because an offset greater than or equal to the
3320 alignment (8) may cause the LO_SUM to overflow if !v9. */
3321 if (mode == TFmode && !TARGET_V9)
3324 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3329 if (GET_CODE (rs1) == SUBREG)
3330 rs1 = SUBREG_REG (rs1);
3336 if (GET_CODE (rs2) == SUBREG)
3337 rs2 = SUBREG_REG (rs2);
3344 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3345 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3350 if ((REGNO (rs1) >= 32
3351 && REGNO (rs1) != FRAME_POINTER_REGNUM
3352 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3354 && (REGNO (rs2) >= 32
3355 && REGNO (rs2) != FRAME_POINTER_REGNUM
3356 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3362 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3364 static GTY(()) rtx sparc_tls_symbol;
3366 sparc_tls_get_addr (void)
3368 if (!sparc_tls_symbol)
3369 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3371 return sparc_tls_symbol;
3375 sparc_tls_got (void)
3380 current_function_uses_pic_offset_table = 1;
3381 return pic_offset_table_rtx;
3384 if (!global_offset_table)
3385 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3386 temp = gen_reg_rtx (Pmode);
3387 emit_move_insn (temp, global_offset_table);
3392 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3393 this (thread-local) address. */
3396 legitimize_tls_address (rtx addr)
3398 rtx temp1, temp2, temp3, ret, o0, got, insn;
3403 if (GET_CODE (addr) == SYMBOL_REF)
3404 switch (SYMBOL_REF_TLS_MODEL (addr))
3406 case TLS_MODEL_GLOBAL_DYNAMIC:
3408 temp1 = gen_reg_rtx (SImode);
3409 temp2 = gen_reg_rtx (SImode);
3410 ret = gen_reg_rtx (Pmode);
3411 o0 = gen_rtx_REG (Pmode, 8);
3412 got = sparc_tls_got ();
3413 emit_insn (gen_tgd_hi22 (temp1, addr));
3414 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3417 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3418 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3423 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3424 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3427 CALL_INSN_FUNCTION_USAGE (insn)
3428 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3429 CALL_INSN_FUNCTION_USAGE (insn));
3430 insn = get_insns ();
3432 emit_libcall_block (insn, ret, o0, addr);
3435 case TLS_MODEL_LOCAL_DYNAMIC:
3437 temp1 = gen_reg_rtx (SImode);
3438 temp2 = gen_reg_rtx (SImode);
3439 temp3 = gen_reg_rtx (Pmode);
3440 ret = gen_reg_rtx (Pmode);
3441 o0 = gen_rtx_REG (Pmode, 8);
3442 got = sparc_tls_got ();
3443 emit_insn (gen_tldm_hi22 (temp1));
3444 emit_insn (gen_tldm_lo10 (temp2, temp1));
3447 emit_insn (gen_tldm_add32 (o0, got, temp2));
3448 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3453 emit_insn (gen_tldm_add64 (o0, got, temp2));
3454 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3457 CALL_INSN_FUNCTION_USAGE (insn)
3458 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3459 CALL_INSN_FUNCTION_USAGE (insn));
3460 insn = get_insns ();
3462 emit_libcall_block (insn, temp3, o0,
3463 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3464 UNSPEC_TLSLD_BASE));
3465 temp1 = gen_reg_rtx (SImode);
3466 temp2 = gen_reg_rtx (SImode);
3467 emit_insn (gen_tldo_hix22 (temp1, addr));
3468 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3470 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3472 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3475 case TLS_MODEL_INITIAL_EXEC:
3476 temp1 = gen_reg_rtx (SImode);
3477 temp2 = gen_reg_rtx (SImode);
3478 temp3 = gen_reg_rtx (Pmode);
3479 got = sparc_tls_got ();
3480 emit_insn (gen_tie_hi22 (temp1, addr));
3481 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3483 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3485 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3488 ret = gen_reg_rtx (Pmode);
3490 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3493 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3497 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3500 case TLS_MODEL_LOCAL_EXEC:
3501 temp1 = gen_reg_rtx (Pmode);
3502 temp2 = gen_reg_rtx (Pmode);
3505 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3506 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3510 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3511 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3513 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3521 abort (); /* for now ... */
3527 /* Legitimize PIC addresses. If the address is already position-independent,
3528 we return ORIG. Newly generated position-independent addresses go into a
3529 reg. This is REG if nonzero, otherwise we allocate register(s) as
3533 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3536 if (GET_CODE (orig) == SYMBOL_REF)
3538 rtx pic_ref, address;
3543 if (reload_in_progress || reload_completed)
3546 reg = gen_reg_rtx (Pmode);
3551 /* If not during reload, allocate another temp reg here for loading
3552 in the address, so that these instructions can be optimized
3554 rtx temp_reg = ((reload_in_progress || reload_completed)
3555 ? reg : gen_reg_rtx (Pmode));
3557 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3558 won't get confused into thinking that these two instructions
3559 are loading in the true address of the symbol. If in the
3560 future a PIC rtx exists, that should be used instead. */
3561 if (Pmode == SImode)
3563 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3564 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3568 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3569 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3576 pic_ref = gen_rtx_MEM (Pmode,
3577 gen_rtx_PLUS (Pmode,
3578 pic_offset_table_rtx, address));
3579 current_function_uses_pic_offset_table = 1;
3580 RTX_UNCHANGING_P (pic_ref) = 1;
3581 insn = emit_move_insn (reg, pic_ref);
3582 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3584 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3588 else if (GET_CODE (orig) == CONST)
3592 if (GET_CODE (XEXP (orig, 0)) == PLUS
3593 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3598 if (reload_in_progress || reload_completed)
3601 reg = gen_reg_rtx (Pmode);
3604 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3606 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3607 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3608 base == reg ? 0 : reg);
3613 if (GET_CODE (offset) == CONST_INT)
3615 if (SMALL_INT (offset))
3616 return plus_constant (base, INTVAL (offset));
3617 else if (! reload_in_progress && ! reload_completed)
3618 offset = force_reg (Pmode, offset);
3620 /* If we reach here, then something is seriously wrong. */
3623 return gen_rtx_PLUS (Pmode, base, offset);
3625 else if (GET_CODE (orig) == LABEL_REF)
3626 /* ??? Why do we do this? */
3627 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3628 the register is live instead, in case it is eliminated. */
3629 current_function_uses_pic_offset_table = 1;
3634 /* Try machine-dependent ways of modifying an illegitimate address X
3635 to be legitimate. If we find one, return the new, valid address.
3637 OLDX is the address as it was before break_out_memory_refs was called.
3638 In some cases it is useful to look at this to decide what needs to be done.
3640 MODE is the mode of the operand pointed to by X. */
3643 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3647 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3648 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3649 force_operand (XEXP (x, 0), NULL_RTX));
3650 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3651 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3652 force_operand (XEXP (x, 1), NULL_RTX));
3653 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3654 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3656 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3657 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3658 force_operand (XEXP (x, 1), NULL_RTX));
3660 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3663 if (tls_symbolic_operand (x))
3664 x = legitimize_tls_address (x);
3666 x = legitimize_pic_address (x, mode, 0);
3667 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3668 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3669 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3670 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3671 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3672 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3673 else if (GET_CODE (x) == SYMBOL_REF
3674 || GET_CODE (x) == CONST
3675 || GET_CODE (x) == LABEL_REF)
3676 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3680 /* Emit special PIC prologues. */
3683 load_pic_register (void)
3685 /* Labels to get the PC in the prologue of this function. */
3686 int orig_flag_pic = flag_pic;
3691 /* If we haven't emitted the special get_pc helper function, do so now. */
3692 if (get_pc_symbol_name[0] == 0)
3696 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3699 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3701 ASM_OUTPUT_ALIGN (asm_out_file, align);
3702 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3703 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3706 /* Initialize every time through, since we can't easily
3707 know this to be permanent. */
3708 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3709 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3712 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3715 flag_pic = orig_flag_pic;
3717 /* Need to emit this whether or not we obey regdecls,
3718 since setjmp/longjmp can cause life info to screw up.
3719 ??? In the case where we don't obey regdecls, this is not sufficient
3720 since we may not fall out the bottom. */
3721 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3724 /* Return 1 if RTX is a MEM which is known to be aligned to at
3725 least a DESIRED byte boundary. */
3728 mem_min_alignment (rtx mem, int desired)
3730 rtx addr, base, offset;
3732 /* If it's not a MEM we can't accept it. */
3733 if (GET_CODE (mem) != MEM)
3736 addr = XEXP (mem, 0);
3737 base = offset = NULL_RTX;
3738 if (GET_CODE (addr) == PLUS)
3740 if (GET_CODE (XEXP (addr, 0)) == REG)
3742 base = XEXP (addr, 0);
3744 /* What we are saying here is that if the base
3745 REG is aligned properly, the compiler will make
3746 sure any REG based index upon it will be so
3748 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3749 offset = XEXP (addr, 1);
3751 offset = const0_rtx;
3754 else if (GET_CODE (addr) == REG)
3757 offset = const0_rtx;
3760 if (base != NULL_RTX)
3762 int regno = REGNO (base);
3764 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3766 /* Check if the compiler has recorded some information
3767 about the alignment of the base REG. If reload has
3768 completed, we already matched with proper alignments.
3769 If not running global_alloc, reload might give us
3770 unaligned pointer to local stack though. */
3772 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3773 || (optimize && reload_completed))
3774 && (INTVAL (offset) & (desired - 1)) == 0)
3779 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3783 else if (! TARGET_UNALIGNED_DOUBLES
3784 || CONSTANT_P (addr)
3785 || GET_CODE (addr) == LO_SUM)
3787 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3788 is true, in which case we can only assume that an access is aligned if
3789 it is to a constant address, or the address involves a LO_SUM. */
3793 /* An obviously unaligned address. */
3798 /* Vectors to keep interesting information about registers where it can easily
3799 be got. We used to use the actual mode value as the bit number, but there
3800 are more than 32 modes now. Instead we use two tables: one indexed by
3801 hard register number, and one indexed by mode. */
3803 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3804 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3805 mapped into one sparc_mode_class mode. */
3807 enum sparc_mode_class {
3808 S_MODE, D_MODE, T_MODE, O_MODE,
3809 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3813 /* Modes for single-word and smaller quantities. */
3814 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3816 /* Modes for double-word and smaller quantities. */
3817 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3819 /* Modes for quad-word and smaller quantities. */
3820 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3822 /* Modes for 8-word and smaller quantities. */
3823 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3825 /* Modes for single-float quantities. We must allow any single word or
3826 smaller quantity. This is because the fix/float conversion instructions
3827 take integer inputs/outputs from the float registers. */
3828 #define SF_MODES (S_MODES)
3830 /* Modes for double-float and smaller quantities. */
3831 #define DF_MODES (S_MODES | D_MODES)
3833 /* Modes for double-float only quantities. */
3834 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3836 /* Modes for quad-float only quantities. */
3837 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3839 /* Modes for quad-float and smaller quantities. */
3840 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3842 /* Modes for quad-float and double-float quantities. */
3843 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3845 /* Modes for quad-float pair only quantities. */
3846 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3848 /* Modes for quad-float pairs and smaller quantities. */
3849 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3851 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3853 /* Modes for condition codes. */
3854 #define CC_MODES (1 << (int) CC_MODE)
3855 #define CCFP_MODES (1 << (int) CCFP_MODE)
3857 /* Value is 1 if register/mode pair is acceptable on sparc.
3858 The funny mixture of D and T modes is because integer operations
3859 do not specially operate on tetra quantities, so non-quad-aligned
3860 registers can hold quadword quantities (except %o4 and %i4 because
3861 they cross fixed registers). */
3863 /* This points to either the 32 bit or the 64 bit version. */
3864 const int *hard_regno_mode_classes;
3866 static const int hard_32bit_mode_classes[] = {
3867 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3868 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3869 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3870 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3872 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3873 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3874 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3875 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3877 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3878 and none can hold SFmode/SImode values. */
3879 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3880 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3881 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3882 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3885 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3891 static const int hard_64bit_mode_classes[] = {
3892 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3893 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3894 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3895 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3897 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3898 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3899 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3900 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3902 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3903 and none can hold SFmode/SImode values. */
3904 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3905 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3906 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3907 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3910 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3916 int sparc_mode_class [NUM_MACHINE_MODES];
3918 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3921 sparc_init_modes (void)
3925 for (i = 0; i < NUM_MACHINE_MODES; i++)
3927 switch (GET_MODE_CLASS (i))
3930 case MODE_PARTIAL_INT:
3931 case MODE_COMPLEX_INT:
3932 if (GET_MODE_SIZE (i) <= 4)
3933 sparc_mode_class[i] = 1 << (int) S_MODE;
3934 else if (GET_MODE_SIZE (i) == 8)
3935 sparc_mode_class[i] = 1 << (int) D_MODE;
3936 else if (GET_MODE_SIZE (i) == 16)
3937 sparc_mode_class[i] = 1 << (int) T_MODE;
3938 else if (GET_MODE_SIZE (i) == 32)
3939 sparc_mode_class[i] = 1 << (int) O_MODE;
3941 sparc_mode_class[i] = 0;
3944 case MODE_COMPLEX_FLOAT:
3945 if (GET_MODE_SIZE (i) <= 4)
3946 sparc_mode_class[i] = 1 << (int) SF_MODE;
3947 else if (GET_MODE_SIZE (i) == 8)
3948 sparc_mode_class[i] = 1 << (int) DF_MODE;
3949 else if (GET_MODE_SIZE (i) == 16)
3950 sparc_mode_class[i] = 1 << (int) TF_MODE;
3951 else if (GET_MODE_SIZE (i) == 32)
3952 sparc_mode_class[i] = 1 << (int) OF_MODE;
3954 sparc_mode_class[i] = 0;
3957 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3958 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3960 sparc_mode_class[i] = 1 << (int) CC_MODE;
3963 sparc_mode_class[i] = 0;
3969 hard_regno_mode_classes = hard_64bit_mode_classes;
3971 hard_regno_mode_classes = hard_32bit_mode_classes;
3973 /* Initialize the array used by REGNO_REG_CLASS. */
3974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3976 if (i < 16 && TARGET_V8PLUS)
3977 sparc_regno_reg_class[i] = I64_REGS;
3978 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3979 sparc_regno_reg_class[i] = GENERAL_REGS;
3981 sparc_regno_reg_class[i] = FP_REGS;
3983 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3985 sparc_regno_reg_class[i] = FPCC_REGS;
3987 sparc_regno_reg_class[i] = NO_REGS;
3991 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3992 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3993 v9 int regs as it simplifies the code. */
3996 save_regs (FILE *file, int low, int high, const char *base,
3997 int offset, int n_regs, int real_offset)
4001 if (TARGET_ARCH64 && high <= 32)
4003 for (i = low; i < high; i++)
4005 if (regs_ever_live[i] && ! call_used_regs[i])
4007 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4008 reg_names[i], base, offset + 4 * n_regs);
4009 if (dwarf2out_do_frame ())
4010 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4017 for (i = low; i < high; i += 2)
4019 if (regs_ever_live[i] && ! call_used_regs[i])
4021 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4023 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4024 reg_names[i], base, offset + 4 * n_regs);
4025 if (dwarf2out_do_frame ())
4027 char *l = dwarf2out_cfi_label ();
4028 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4029 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4035 fprintf (file, "\tst\t%s, [%s+%d]\n",
4036 reg_names[i], base, offset + 4 * n_regs);
4037 if (dwarf2out_do_frame ())
4038 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4044 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4046 fprintf (file, "\tst\t%s, [%s+%d]\n",
4047 reg_names[i+1], base, offset + 4 * n_regs + 4);
4048 if (dwarf2out_do_frame ())
4049 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4058 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4060 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4061 v9 int regs as it simplifies the code. */
4064 restore_regs (FILE *file, int low, int high, const char *base,
4065 int offset, int n_regs)
4069 if (TARGET_ARCH64 && high <= 32)
4071 for (i = low; i < high; i++)
4073 if (regs_ever_live[i] && ! call_used_regs[i])
4074 fprintf (file, "\tldx\t[%s+%d], %s\n",
4075 base, offset + 4 * n_regs, reg_names[i]),
4081 for (i = low; i < high; i += 2)
4083 if (regs_ever_live[i] && ! call_used_regs[i])
4084 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4085 fprintf (file, "\tldd\t[%s+%d], %s\n",
4086 base, offset + 4 * n_regs, reg_names[i]),
4089 fprintf (file, "\tld\t[%s+%d], %s\n",
4090 base, offset + 4 * n_regs, reg_names[i]),
4092 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4093 fprintf (file, "\tld\t[%s+%d], %s\n",
4094 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4101 /* Compute the frame size required by the function. This function is called
4102 during the reload pass and also by output_function_prologue(). */
4105 compute_frame_size (int size, int leaf_function)
4108 int outgoing_args_size = (current_function_outgoing_args_size
4109 + REG_PARM_STACK_SPACE (current_function_decl));
4111 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4112 even to v9 int regs to be consistent with save_regs/restore_regs. */
4116 for (i = 0; i < 8; i++)
4117 if (regs_ever_live[i] && ! call_used_regs[i])
4122 for (i = 0; i < 8; i += 2)
4123 if ((regs_ever_live[i] && ! call_used_regs[i])
4124 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4128 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4129 if ((regs_ever_live[i] && ! call_used_regs[i])
4130 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4133 /* Set up values for use in `function_epilogue'. */
4134 num_gfregs = n_regs;
4136 if (leaf_function && n_regs == 0
4137 && size == 0 && current_function_outgoing_args_size == 0)
4139 actual_fsize = apparent_fsize = 0;
4143 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4144 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4145 apparent_fsize += n_regs * 4;
4146 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4149 /* Make sure nothing can clobber our register windows.
4150 If a SAVE must be done, or there is a stack-local variable,
4151 the register window area must be allocated.
4152 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4153 if (leaf_function == 0 || size > 0)
4154 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4156 return SPARC_STACK_ALIGN (actual_fsize);
4159 /* Build a (32 bit) big number in a register. */
4160 /* ??? We may be able to use the set macro here too. */
4163 build_big_number (FILE *file, int num, const char *reg)
4165 if (num >= 0 || ! TARGET_ARCH64)
4167 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
4168 if ((num & 0x3ff) != 0)
4169 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
4171 else /* num < 0 && TARGET_ARCH64 */
4173 /* Sethi does not sign extend, so we must use a little trickery
4174 to use it for negative numbers. Invert the constant before
4175 loading it in, then use xor immediate to invert the loaded bits
4176 (along with the upper 32 bits) to the desired constant. This
4177 works because the sethi and immediate fields overlap. */
4180 int low = -0x400 + (asize & 0x3FF);
4182 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
4183 inv, reg, reg, low, reg);
4187 /* Output any necessary .register pseudo-ops. */
4189 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4191 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4197 /* Check if %g[2367] were used without
4198 .register being printed for them already. */
4199 for (i = 2; i < 8; i++)
4201 if (regs_ever_live [i]
4202 && ! sparc_hard_reg_printed [i])
4204 sparc_hard_reg_printed [i] = 1;
4205 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4212 /* This function generates the assembly code for function entry.
4213 FILE is a stdio stream to output the code to.
4214 SIZE is an int: how many units of temporary storage to allocate.
4215 Refer to the array `regs_ever_live' to determine which registers
4216 to save; `regs_ever_live[I]' is nonzero if register number I
4217 is ever used in the function. This macro is responsible for
4218 knowing which registers should not be saved even if used. */
4220 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4221 of memory. If any fpu reg is used in the function, we allocate
4222 such a block here, at the bottom of the frame, just in case it's needed.
4224 If this function is a leaf procedure, then we may choose not
4225 to do a "save" insn. The decision about whether or not
4226 to do this is made in regclass.c. */
4229 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4232 sparc_flat_function_prologue (file, size);
4234 sparc_nonflat_function_prologue (file, size,
4235 current_function_uses_only_leaf_regs);
4238 /* Output code for the function prologue. */
4241 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4244 sparc_output_scratch_registers (file);
4246 /* Need to use actual_fsize, since we are also allocating
4247 space for our callee (and our own register save area). */
4248 actual_fsize = compute_frame_size (size, leaf_function);
4252 frame_base_name = "%sp";
4253 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4257 frame_base_name = "%fp";
4258 frame_base_offset = SPARC_STACK_BIAS;
4261 /* This is only for the human reader. */
4262 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4264 if (actual_fsize == 0)
4266 else if (! leaf_function)
4268 if (actual_fsize <= 4096)
4269 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
4270 else if (actual_fsize <= 8192)
4272 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4273 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4277 build_big_number (file, -actual_fsize, "%g1");
4278 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4281 else /* leaf function */
4283 if (actual_fsize <= 4096)
4284 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
4285 else if (actual_fsize <= 8192)
4287 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4288 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4292 build_big_number (file, -actual_fsize, "%g1");
4293 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4297 if (dwarf2out_do_frame () && actual_fsize)
4299 char *label = dwarf2out_cfi_label ();
4301 /* The canonical frame address refers to the top of the frame. */
4302 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4303 : HARD_FRAME_POINTER_REGNUM),
4306 if (! leaf_function)
4308 /* Note the register window save. This tells the unwinder that
4309 it needs to restore the window registers from the previous
4310 frame's window save area at 0(cfa). */
4311 dwarf2out_window_save (label);
4313 /* The return address (-8) is now in %i7. */
4314 dwarf2out_return_reg (label, 31);
4318 /* If doing anything with PIC, do it now. */
4320 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4322 /* Call saved registers are saved just above the outgoing argument area. */
4325 int offset, real_offset, n_regs;
4328 real_offset = -apparent_fsize;
4329 offset = -apparent_fsize + frame_base_offset;
4330 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4332 /* ??? This might be optimized a little as %g1 might already have a
4333 value close enough that a single add insn will do. */
4334 /* ??? Although, all of this is probably only a temporary fix
4335 because if %g1 can hold a function result, then
4336 output_function_epilogue will lose (the result will get
4338 build_big_number (file, offset, "%g1");
4339 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4345 base = frame_base_name;
4348 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4349 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4354 /* Output code to restore any call saved registers. */
4357 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4362 offset = -apparent_fsize + frame_base_offset;
4363 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4365 build_big_number (file, offset, "%g1");
4366 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4372 base = frame_base_name;
4375 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4376 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4379 /* This function generates the assembly code for function exit,
4380 on machines that need it.
4382 The function epilogue should not depend on the current stack pointer!
4383 It should use the frame pointer only. This is mandatory because
4384 of alloca; we also take advantage of it to omit stack adjustments
4385 before returning. */
4388 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4391 sparc_flat_function_epilogue (file, size);
4393 sparc_nonflat_function_epilogue (file, size,
4394 current_function_uses_only_leaf_regs);
4397 /* Output code for the function epilogue. */
4400 sparc_nonflat_function_epilogue (FILE *file,
4401 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4406 if (current_function_epilogue_delay_list == 0)
4408 /* If code does not drop into the epilogue, we need
4409 do nothing except output pending case vectors.
4411 We have to still output a dummy nop for the sake of
4412 sane backtraces. Otherwise, if the last two instructions
4413 of a function were call foo; dslot; this can make the return
4414 PC of foo (ie. address of call instruction plus 8) point to
4415 the first instruction in the next function. */
4416 rtx insn, last_real_insn;
4418 insn = get_last_insn ();
4420 last_real_insn = prev_real_insn (insn);
4422 && GET_CODE (last_real_insn) == INSN
4423 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4424 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4426 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4427 fputs("\tnop\n", file);
4429 if (GET_CODE (insn) == NOTE)
4430 insn = prev_nonnote_insn (insn);
4431 if (insn && GET_CODE (insn) == BARRIER)
4432 goto output_vectors;
4436 output_restore_regs (file, leaf_function);
4438 /* Work out how to skip the caller's unimp instruction if required. */
4440 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4442 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4444 if (! leaf_function)
4446 if (current_function_calls_eh_return)
4448 if (current_function_epilogue_delay_list)
4450 if (SKIP_CALLERS_UNIMP_P)
4453 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4455 /* If we wound up with things in our delay slot, flush them here. */
4456 else if (current_function_epilogue_delay_list)
4458 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4460 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4462 epilogue_renumber (&delay, 0);
4463 fputs (SKIP_CALLERS_UNIMP_P
4464 ? "\treturn\t%i7+12\n"
4465 : "\treturn\t%i7+8\n", file);
4466 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4473 if (GET_CODE (delay) != SET)
4476 src = SET_SRC (delay);
4477 if (GET_CODE (src) == ASHIFT)
4479 if (XEXP (src, 1) != const1_rtx)
4482 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4486 insn = gen_rtx_PARALLEL (VOIDmode,
4487 gen_rtvec (2, delay,
4488 gen_rtx_RETURN (VOIDmode)));
4489 insn = emit_jump_insn (insn);
4491 sparc_emitting_epilogue = true;
4492 final_scan_insn (insn, file, 1, 0, 1);
4493 sparc_emitting_epilogue = false;
4496 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4497 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4499 fprintf (file, "\t%s\n\trestore\n", ret);
4501 /* All of the following cases are for leaf functions. */
4502 else if (current_function_calls_eh_return)
4504 else if (current_function_epilogue_delay_list)
4506 /* eligible_for_epilogue_delay_slot ensures that if this is a
4507 leaf function, then we will only have insn in the delay slot
4508 if the frame size is zero, thus no adjust for the stack is
4510 if (actual_fsize != 0)
4512 fprintf (file, "\t%s\n", ret);
4513 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4516 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4517 avoid generating confusing assembly language output. */
4518 else if (actual_fsize == 0)
4519 fprintf (file, "\t%s\n\tnop\n", ret);
4520 else if (actual_fsize <= 4096)
4521 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4522 else if (actual_fsize <= 8192)
4523 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4524 ret, actual_fsize - 4096);
4525 else if ((actual_fsize & 0x3ff) == 0)
4526 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4529 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4530 actual_fsize, actual_fsize, ret);
4533 sparc_output_deferred_case_vectors ();
4536 /* Output a sibling call. */
4539 output_sibcall (rtx insn, rtx call_operand)
4541 int leaf_regs = current_function_uses_only_leaf_regs;
4543 int delay_slot = dbr_sequence_length () > 0;
4547 /* Call to restore global regs might clobber
4548 the delay slot. Instead of checking for this
4549 output the delay slot now. */
4552 rtx delay = NEXT_INSN (insn);
4557 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4558 PATTERN (delay) = gen_blockage ();
4559 INSN_CODE (delay) = -1;
4562 output_restore_regs (asm_out_file, leaf_regs);
4565 operands[0] = call_operand;
4569 #ifdef HAVE_AS_RELAX_OPTION
4570 /* If as and ld are relaxing tail call insns into branch always,
4571 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4572 be optimized. With sethi/jmpl as nor ld has no easy way how to
4573 find out if somebody does not branch between the sethi and jmpl. */
4576 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4580 if ((actual_fsize || ! spare_slot) && delay_slot)
4582 rtx delay = NEXT_INSN (insn);
4587 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4588 PATTERN (delay) = gen_blockage ();
4589 INSN_CODE (delay) = -1;
4594 if (actual_fsize <= 4096)
4595 size = actual_fsize;
4596 else if (actual_fsize <= 8192)
4598 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4599 size = actual_fsize - 4096;
4601 else if ((actual_fsize & 0x3ff) == 0)
4602 fprintf (asm_out_file,
4603 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4607 fprintf (asm_out_file,
4608 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4609 actual_fsize, actual_fsize);
4610 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4615 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4616 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4618 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4619 else if (! delay_slot)
4620 fputs ("\t nop\n", asm_out_file);
4625 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4626 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4627 it into branch if possible. */
4628 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4629 output_asm_insn ("call\t%a0, 0", operands);
4630 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4635 output_asm_insn ("call\t%a0, 0", operands);
4638 rtx delay = NEXT_INSN (insn), pat;
4643 pat = PATTERN (delay);
4644 if (GET_CODE (pat) != SET)
4647 operands[0] = SET_DEST (pat);
4648 pat = SET_SRC (pat);
4649 switch (GET_CODE (pat))
4652 operands[1] = XEXP (pat, 0);
4653 operands[2] = XEXP (pat, 1);
4654 output_asm_insn (" restore %r1, %2, %Y0", operands);
4657 operands[1] = XEXP (pat, 0);
4658 operands[2] = XEXP (pat, 1);
4659 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4662 operands[1] = XEXP (pat, 0);
4663 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4667 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4670 PATTERN (delay) = gen_blockage ();
4671 INSN_CODE (delay) = -1;
4674 fputs ("\t restore\n", asm_out_file);
4678 /* Functions for handling argument passing.
4680 For v8 the first six args are normally in registers and the rest are
4681 pushed. Any arg that starts within the first 6 words is at least
4682 partially passed in a register unless its data type forbids.
4684 For v9, the argument registers are laid out as an array of 16 elements
4685 and arguments are added sequentially. The first 6 int args and up to the
4686 first 16 fp args (depending on size) are passed in regs.
4688 Slot Stack Integral Float Float in structure Double Long Double
4689 ---- ----- -------- ----- ------------------ ------ -----------
4690 15 [SP+248] %f31 %f30,%f31 %d30
4691 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4692 13 [SP+232] %f27 %f26,%f27 %d26
4693 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4694 11 [SP+216] %f23 %f22,%f23 %d22
4695 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4696 9 [SP+200] %f19 %f18,%f19 %d18
4697 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4698 7 [SP+184] %f15 %f14,%f15 %d14
4699 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4700 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4701 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4702 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4703 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4704 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4705 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4707 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4709 Integral arguments are always passed as 64 bit quantities appropriately
4712 Passing of floating point values is handled as follows.
4713 If a prototype is in scope:
4714 If the value is in a named argument (i.e. not a stdarg function or a
4715 value not part of the `...') then the value is passed in the appropriate
4717 If the value is part of the `...' and is passed in one of the first 6
4718 slots then the value is passed in the appropriate int reg.
4719 If the value is part of the `...' and is not passed in one of the first 6
4720 slots then the value is passed in memory.
4721 If a prototype is not in scope:
4722 If the value is one of the first 6 arguments the value is passed in the
4723 appropriate integer reg and the appropriate fp reg.
4724 If the value is not one of the first 6 arguments the value is passed in
4725 the appropriate fp reg and in memory.
4728 /* Maximum number of int regs for args. */
4729 #define SPARC_INT_ARG_MAX 6
4730 /* Maximum number of fp regs for args. */
4731 #define SPARC_FP_ARG_MAX 16
4733 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4735 /* Handle the INIT_CUMULATIVE_ARGS macro.
4736 Initialize a variable CUM of type CUMULATIVE_ARGS
4737 for a call to a function whose data type is FNTYPE.
4738 For a library call, FNTYPE is 0. */
4741 init_cumulative_args (struct sparc_args *cum, tree fntype,
4742 rtx libname ATTRIBUTE_UNUSED,
4743 tree fndecl ATTRIBUTE_UNUSED)
4746 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4747 cum->libcall_p = fntype == 0;
4750 /* Compute the slot number to pass an argument in.
4751 Returns the slot number or -1 if passing on the stack.
4753 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4754 the preceding args and about the function being called.
4755 MODE is the argument's machine mode.
4756 TYPE is the data type of the argument (as a tree).
4757 This is null for libcalls where that information may
4759 NAMED is nonzero if this argument is a named parameter
4760 (otherwise it is an extra parameter matching an ellipsis).
4761 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4762 *PREGNO records the register number to use if scalar type.
4763 *PPADDING records the amount of padding needed in words. */
4766 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4767 tree type, int named, int incoming_p,
4768 int *pregno, int *ppadding)
4770 int regbase = (incoming_p
4771 ? SPARC_INCOMING_INT_ARG_FIRST
4772 : SPARC_OUTGOING_INT_ARG_FIRST);
4773 int slotno = cum->words;
4778 if (type != 0 && TREE_ADDRESSABLE (type))
4781 && type != 0 && mode == BLKmode
4782 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4788 /* MODE is VOIDmode when generating the actual call.
4792 case QImode : case CQImode :
4793 case HImode : case CHImode :
4794 case SImode : case CSImode :
4795 case DImode : case CDImode :
4796 case TImode : case CTImode :
4797 if (slotno >= SPARC_INT_ARG_MAX)
4799 regno = regbase + slotno;
4802 case SFmode : case SCmode :
4803 case DFmode : case DCmode :
4804 case TFmode : case TCmode :
4807 if (slotno >= SPARC_INT_ARG_MAX)
4809 regno = regbase + slotno;
4813 if ((mode == TFmode || mode == TCmode)
4814 && (slotno & 1) != 0)
4815 slotno++, *ppadding = 1;
4816 if (TARGET_FPU && named)
4818 if (slotno >= SPARC_FP_ARG_MAX)
4820 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4826 if (slotno >= SPARC_INT_ARG_MAX)
4828 regno = regbase + slotno;
4834 /* For sparc64, objects requiring 16 byte alignment get it. */
4837 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4838 slotno++, *ppadding = 1;
4842 || (type && TREE_CODE (type) == UNION_TYPE))
4844 if (slotno >= SPARC_INT_ARG_MAX)
4846 regno = regbase + slotno;
4851 int intregs_p = 0, fpregs_p = 0;
4852 /* The ABI obviously doesn't specify how packed
4853 structures are passed. These are defined to be passed
4854 in int regs if possible, otherwise memory. */
4857 /* First see what kinds of registers we need. */
4858 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4860 if (TREE_CODE (field) == FIELD_DECL)
4862 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4867 if (DECL_PACKED (field))
4871 if (packed_p || !named)
4872 fpregs_p = 0, intregs_p = 1;
4874 /* If all arg slots are filled, then must pass on stack. */
4875 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4877 /* If there are only int args and all int arg slots are filled,
4878 then must pass on stack. */
4879 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4881 /* Note that even if all int arg slots are filled, fp members may
4882 still be passed in regs if such regs are available.
4883 *PREGNO isn't set because there may be more than one, it's up
4884 to the caller to compute them. */
4897 /* Handle recursive register counting for structure field layout. */
4899 struct function_arg_record_value_parms
4901 rtx ret; /* return expression being built. */
4902 int slotno; /* slot number of the argument. */
4903 int named; /* whether the argument is named. */
4904 int regbase; /* regno of the base register. */
4905 int stack; /* 1 if part of the argument is on the stack. */
4906 int intoffset; /* offset of the pending integer field. */
4907 unsigned int nregs; /* number of words passed in registers. */
4910 static void function_arg_record_value_3
4911 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4912 static void function_arg_record_value_2
4913 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4914 static void function_arg_record_value_1
4915 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4916 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4918 /* A subroutine of function_arg_record_value. Traverse the structure
4919 recursively and determine how many registers will be required. */
4922 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4923 struct function_arg_record_value_parms *parms,
4928 /* We need to compute how many registers are needed so we can
4929 allocate the PARALLEL but before we can do that we need to know
4930 whether there are any packed fields. The ABI obviously doesn't
4931 specify how structures are passed in this case, so they are
4932 defined to be passed in int regs if possible, otherwise memory,
4933 regardless of whether there are fp values present. */
4936 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4938 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4945 /* Compute how many registers we need. */
4946 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4948 if (TREE_CODE (field) == FIELD_DECL)
4950 HOST_WIDE_INT bitpos = startbitpos;
4952 if (DECL_SIZE (field) != 0
4953 && host_integerp (bit_position (field), 1))
4954 bitpos += int_bit_position (field);
4956 /* ??? FIXME: else assume zero offset. */
4958 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4959 function_arg_record_value_1 (TREE_TYPE (field),
4963 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4964 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4965 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4971 if (parms->intoffset != -1)
4973 int intslots, this_slotno;
4975 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4977 this_slotno = parms->slotno + parms->intoffset
4980 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4982 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4983 /* We need to pass this field on the stack. */
4987 parms->nregs += intslots;
4988 parms->intoffset = -1;
4991 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4992 If it wasn't true we wouldn't be here. */
4994 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4999 if (parms->intoffset == -1)
5000 parms->intoffset = bitpos;
5006 /* A subroutine of function_arg_record_value. Assign the bits of the
5007 structure between parms->intoffset and bitpos to integer registers. */
5010 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5011 struct function_arg_record_value_parms *parms)
5013 enum machine_mode mode;
5015 unsigned int startbit, endbit;
5016 int this_slotno, intslots, intoffset;
5019 if (parms->intoffset == -1)
5022 intoffset = parms->intoffset;
5023 parms->intoffset = -1;
5025 startbit = intoffset & -BITS_PER_WORD;
5026 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5027 intslots = (endbit - startbit) / BITS_PER_WORD;
5028 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5030 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5034 /* If this is the trailing part of a word, only load that much into
5035 the register. Otherwise load the whole register. Note that in
5036 the latter case we may pick up unwanted bits. It's not a problem
5037 at the moment but may wish to revisit. */
5039 if (intoffset % BITS_PER_WORD != 0)
5040 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5045 intoffset /= BITS_PER_UNIT;
5048 regno = parms->regbase + this_slotno;
5049 reg = gen_rtx_REG (mode, regno);
5050 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5051 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5054 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5058 while (intslots > 0);
5061 /* A subroutine of function_arg_record_value. Traverse the structure
5062 recursively and assign bits to floating point registers. Track which
5063 bits in between need integer registers; invoke function_arg_record_value_3
5064 to make that happen. */
5067 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5068 struct function_arg_record_value_parms *parms,
5074 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5076 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5083 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5085 if (TREE_CODE (field) == FIELD_DECL)
5087 HOST_WIDE_INT bitpos = startbitpos;
5089 if (DECL_SIZE (field) != 0
5090 && host_integerp (bit_position (field), 1))
5091 bitpos += int_bit_position (field);
5093 /* ??? FIXME: else assume zero offset. */
5095 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5096 function_arg_record_value_2 (TREE_TYPE (field),
5100 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5101 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5102 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5108 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5110 enum machine_mode mode = DECL_MODE (field);
5113 function_arg_record_value_3 (bitpos, parms);
5114 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5115 + ((mode == SFmode || mode == SCmode)
5116 && (bitpos & 32) != 0);
5119 case SCmode: mode = SFmode; break;
5120 case DCmode: mode = DFmode; break;
5121 case TCmode: mode = TFmode; break;
5124 reg = gen_rtx_REG (mode, regno);
5125 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5126 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5127 GEN_INT (bitpos / BITS_PER_UNIT));
5129 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5131 regno += GET_MODE_SIZE (mode) / 4;
5132 reg = gen_rtx_REG (mode, regno);
5133 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5134 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5135 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5142 if (parms->intoffset == -1)
5143 parms->intoffset = bitpos;
5149 /* Used by function_arg and function_value to implement the complex
5150 conventions of the 64-bit ABI for passing and returning structures.
5151 Return an expression valid as a return value for the two macros
5152 FUNCTION_ARG and FUNCTION_VALUE.
5154 TYPE is the data type of the argument (as a tree).
5155 This is null for libcalls where that information may
5157 MODE is the argument's machine mode.
5158 SLOTNO is the index number of the argument's slot in the parameter array.
5159 NAMED is nonzero if this argument is a named parameter
5160 (otherwise it is an extra parameter matching an ellipsis).
5161 REGBASE is the regno of the base register for the parameter array. */
5164 function_arg_record_value (tree type, enum machine_mode mode,
5165 int slotno, int named, int regbase)
5167 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5168 struct function_arg_record_value_parms parms;
5171 parms.ret = NULL_RTX;
5172 parms.slotno = slotno;
5173 parms.named = named;
5174 parms.regbase = regbase;
5177 /* Compute how many registers we need. */
5179 parms.intoffset = 0;
5180 function_arg_record_value_1 (type, 0, &parms, false);
5182 if (parms.intoffset != -1)
5184 unsigned int startbit, endbit;
5185 int intslots, this_slotno;
5187 startbit = parms.intoffset & -BITS_PER_WORD;
5188 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5189 intslots = (endbit - startbit) / BITS_PER_WORD;
5190 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5192 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5194 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5195 /* We need to pass this field on the stack. */
5199 parms.nregs += intslots;
5201 nregs = parms.nregs;
5203 /* Allocate the vector and handle some annoying special cases. */
5206 /* ??? Empty structure has no value? Duh? */
5209 /* Though there's nothing really to store, return a word register
5210 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5211 leads to breakage due to the fact that there are zero bytes to
5213 return gen_rtx_REG (mode, regbase);
5217 /* ??? C++ has structures with no fields, and yet a size. Give up
5218 for now and pass everything back in integer registers. */
5219 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5221 if (nregs + slotno > SPARC_INT_ARG_MAX)
5222 nregs = SPARC_INT_ARG_MAX - slotno;
5227 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5229 /* If at least one field must be passed on the stack, generate
5230 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5231 also be passed on the stack. We can't do much better because the
5232 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5233 of structures for which the fields passed exclusively in registers
5234 are not at the beginning of the structure. */
5236 XVECEXP (parms.ret, 0, 0)
5237 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5239 /* Fill in the entries. */
5241 parms.intoffset = 0;
5242 function_arg_record_value_2 (type, 0, &parms, false);
5243 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5245 if (parms.nregs != nregs)
5251 /* Handle the FUNCTION_ARG macro.
5252 Determine where to put an argument to a function.
5253 Value is zero to push the argument on the stack,
5254 or a hard register in which to store the argument.
5256 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5257 the preceding args and about the function being called.
5258 MODE is the argument's machine mode.
5259 TYPE is the data type of the argument (as a tree).
5260 This is null for libcalls where that information may
5262 NAMED is nonzero if this argument is a named parameter
5263 (otherwise it is an extra parameter matching an ellipsis).
5264 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5267 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5268 tree type, int named, int incoming_p)
5270 int regbase = (incoming_p
5271 ? SPARC_INCOMING_INT_ARG_FIRST
5272 : SPARC_OUTGOING_INT_ARG_FIRST);
5273 int slotno, regno, padding;
5276 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5284 reg = gen_rtx_REG (mode, regno);
5288 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5289 but also have the slot allocated for them.
5290 If no prototype is in scope fp values in register slots get passed
5291 in two places, either fp regs and int regs or fp regs and memory. */
5292 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5293 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5294 && SPARC_FP_REG_P (regno))
5296 reg = gen_rtx_REG (mode, regno);
5297 if (cum->prototype_p || cum->libcall_p)
5299 /* "* 2" because fp reg numbers are recorded in 4 byte
5302 /* ??? This will cause the value to be passed in the fp reg and
5303 in the stack. When a prototype exists we want to pass the
5304 value in the reg but reserve space on the stack. That's an
5305 optimization, and is deferred [for a bit]. */
5306 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5307 return gen_rtx_PARALLEL (mode,
5309 gen_rtx_EXPR_LIST (VOIDmode,
5310 NULL_RTX, const0_rtx),
5311 gen_rtx_EXPR_LIST (VOIDmode,
5315 /* ??? It seems that passing back a register even when past
5316 the area declared by REG_PARM_STACK_SPACE will allocate
5317 space appropriately, and will not copy the data onto the
5318 stack, exactly as we desire.
5320 This is due to locate_and_pad_parm being called in
5321 expand_call whenever reg_parm_stack_space > 0, which
5322 while beneficial to our example here, would seem to be
5323 in error from what had been intended. Ho hum... -- r~ */
5331 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5335 /* On incoming, we don't need to know that the value
5336 is passed in %f0 and %i0, and it confuses other parts
5337 causing needless spillage even on the simplest cases. */
5341 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5342 + (regno - SPARC_FP_ARG_FIRST) / 2);
5344 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5345 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5347 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5351 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5352 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5353 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5357 else if (type && TREE_CODE (type) == RECORD_TYPE)
5359 /* Structures up to 16 bytes in size are passed in arg slots on the
5360 stack and are promoted to registers where possible. */
5362 if (int_size_in_bytes (type) > 16)
5363 abort (); /* shouldn't get here */
5365 return function_arg_record_value (type, mode, slotno, named, regbase);
5367 else if (type && TREE_CODE (type) == UNION_TYPE)
5369 enum machine_mode mode;
5370 int bytes = int_size_in_bytes (type);
5375 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5376 reg = gen_rtx_REG (mode, regno);
5380 /* Scalar or complex int. */
5381 reg = gen_rtx_REG (mode, regno);
5387 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5388 For an arg passed partly in registers and partly in memory,
5389 this is the number of registers used.
5390 For args passed entirely in registers or entirely in memory, zero.
5392 Any arg that starts in the first 6 regs but won't entirely fit in them
5393 needs partial registers on v8. On v9, structures with integer
5394 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5395 values that begin in the last fp reg [where "last fp reg" varies with the
5396 mode] will be split between that reg and memory. */
5399 function_arg_partial_nregs (const struct sparc_args *cum,
5400 enum machine_mode mode, tree type, int named)
5402 int slotno, regno, padding;
5404 /* We pass 0 for incoming_p here, it doesn't matter. */
5405 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5412 if ((slotno + (mode == BLKmode
5413 ? ROUND_ADVANCE (int_size_in_bytes (type))
5414 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5415 > NPARM_REGS (SImode))
5416 return NPARM_REGS (SImode) - slotno;
5421 if (type && AGGREGATE_TYPE_P (type))
5423 int size = int_size_in_bytes (type);
5424 int align = TYPE_ALIGN (type);
5427 slotno += slotno & 1;
5428 if (size > 8 && size <= 16
5429 && slotno == SPARC_INT_ARG_MAX - 1)
5432 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5433 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5434 && ! (TARGET_FPU && named)))
5436 /* The complex types are passed as packed types. */
5437 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5440 if (GET_MODE_ALIGNMENT (mode) == 128)
5442 slotno += slotno & 1;
5444 /* ??? The mode needs 3 slots? */
5445 if (slotno == SPARC_INT_ARG_MAX - 2)
5450 if (slotno == SPARC_INT_ARG_MAX - 1)
5454 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5456 if (GET_MODE_ALIGNMENT (mode) == 128)
5457 slotno += slotno & 1;
5458 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5466 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5467 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5468 quad-precision floats by invisible reference.
5469 v9: Aggregates greater than 16 bytes are passed by reference.
5470 For Pascal, also pass arrays by reference. */
5473 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5474 enum machine_mode mode, tree type,
5475 int named ATTRIBUTE_UNUSED)
5479 return ((type && AGGREGATE_TYPE_P (type))
5480 || mode == TFmode || mode == TCmode);
5484 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5485 /* Consider complex values as aggregates, so care
5486 for CTImode and TCmode. */
5487 || GET_MODE_SIZE (mode) > 16
5489 && AGGREGATE_TYPE_P (type)
5490 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5494 /* Handle the FUNCTION_ARG_ADVANCE macro.
5495 Update the data in CUM to advance over an argument
5496 of mode MODE and data type TYPE.
5497 TYPE is null for libcalls where that information may not be available. */
5500 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5501 tree type, int named)
5503 int slotno, regno, padding;
5505 /* We pass 0 for incoming_p here, it doesn't matter. */
5506 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5508 /* If register required leading padding, add it. */
5510 cum->words += padding;
5514 cum->words += (mode != BLKmode
5515 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5516 : ROUND_ADVANCE (int_size_in_bytes (type)));
5520 if (type && AGGREGATE_TYPE_P (type))
5522 int size = int_size_in_bytes (type);
5526 else if (size <= 16)
5528 else /* passed by reference */
5533 cum->words += (mode != BLKmode
5534 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5535 : ROUND_ADVANCE (int_size_in_bytes (type)));
5540 /* Handle the FUNCTION_ARG_PADDING macro.
5541 For the 64 bit ABI structs are always stored left shifted in their
5545 function_arg_padding (enum machine_mode mode, tree type)
5547 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5550 /* Fall back to the default. */
5551 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5554 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5555 For v9, function return values are subject to the same rules as arguments,
5556 except that up to 32-bytes may be returned in registers. */
5559 function_value (tree type, enum machine_mode mode, int incoming_p)
5562 int regbase = (incoming_p
5563 ? SPARC_OUTGOING_INT_ARG_FIRST
5564 : SPARC_INCOMING_INT_ARG_FIRST);
5566 if (TARGET_ARCH64 && type)
5568 if (TREE_CODE (type) == RECORD_TYPE)
5570 /* Structures up to 32 bytes in size are passed in registers,
5571 promoted to fp registers where possible. */
5573 if (int_size_in_bytes (type) > 32)
5574 abort (); /* shouldn't get here */
5576 return function_arg_record_value (type, mode, 0, 1, regbase);
5578 else if (AGGREGATE_TYPE_P (type))
5580 /* All other aggregate types are passed in an integer register
5581 in a mode corresponding to the size of the type. */
5582 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5587 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5592 && GET_MODE_CLASS (mode) == MODE_INT
5593 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5594 && type && ! AGGREGATE_TYPE_P (type))
5598 regno = BASE_RETURN_VALUE_REG (mode);
5600 regno = BASE_OUTGOING_VALUE_REG (mode);
5602 return gen_rtx_REG (mode, regno);
5605 /* Do what is necessary for `va_start'. We look at the current function
5606 to determine if stdarg or varargs is used and return the address of
5607 the first unnamed parameter. */
5610 sparc_builtin_saveregs (void)
5612 int first_reg = current_function_args_info.words;
5616 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5617 emit_move_insn (gen_rtx_MEM (word_mode,
5618 gen_rtx_PLUS (Pmode,
5620 GEN_INT (FIRST_PARM_OFFSET (0)
5623 gen_rtx_REG (word_mode,
5624 BASE_INCOMING_ARG_REG (word_mode) + regno));
5626 address = gen_rtx_PLUS (Pmode,
5628 GEN_INT (FIRST_PARM_OFFSET (0)
5629 + UNITS_PER_WORD * first_reg));
5634 /* Implement `va_start' for varargs and stdarg. */
5637 sparc_va_start (tree valist, rtx nextarg)
5639 nextarg = expand_builtin_saveregs ();
5640 std_expand_builtin_va_start (valist, nextarg);
5643 /* Implement `va_arg'. */
5646 sparc_va_arg (tree valist, tree type)
5648 HOST_WIDE_INT size, rsize, align;
5653 /* Round up sizeof(type) to a word. */
5654 size = int_size_in_bytes (type);
5655 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5660 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5661 align = 2 * UNITS_PER_WORD;
5663 /* Consider complex values as aggregates, so care
5664 for CTImode and TCmode. */
5665 if ((unsigned HOST_WIDE_INT) size > 16)
5668 size = rsize = UNITS_PER_WORD;
5671 else if (AGGREGATE_TYPE_P (type))
5673 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5674 are given whole slots as needed. */
5676 size = rsize = UNITS_PER_WORD;
5683 if (AGGREGATE_TYPE_P (type)
5684 || TYPE_MODE (type) == TFmode
5685 || TYPE_MODE (type) == TCmode)
5688 size = rsize = UNITS_PER_WORD;
5695 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5696 build_int_2 (align - 1, 0)));
5697 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5698 build_int_2 (-align, -1)));
5701 addr = incr = save_expr (incr);
5702 if (BYTES_BIG_ENDIAN && size < rsize)
5704 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5705 build_int_2 (rsize - size, 0)));
5707 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5708 build_int_2 (rsize, 0)));
5710 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5711 TREE_SIDE_EFFECTS (incr) = 1;
5712 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5714 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5716 /* If the address isn't aligned properly for the type,
5717 we may need to copy to a temporary.
5718 FIXME: This is inefficient. Usually we can do this
5721 && TYPE_ALIGN (type) > BITS_PER_WORD
5724 /* FIXME: We really need to specify that the temporary is live
5725 for the whole function because expand_builtin_va_arg wants
5726 the alias set to be get_varargs_alias_set (), but in this
5727 case the alias set is that for TYPE and if the memory gets
5728 reused it will be reused with alias set TYPE. */
5729 rtx tmp = assign_temp (type, 0, 1, 0);
5732 addr_rtx = force_reg (Pmode, addr_rtx);
5733 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5734 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5735 set_mem_align (addr_rtx, BITS_PER_WORD);
5736 tmp = shallow_copy_rtx (tmp);
5737 PUT_MODE (tmp, BLKmode);
5738 set_mem_alias_set (tmp, 0);
5740 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5742 if (dest_addr != NULL_RTX)
5743 addr_rtx = dest_addr;
5745 addr_rtx = XCEXP (tmp, 0, MEM);
5750 addr_rtx = force_reg (Pmode, addr_rtx);
5751 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5752 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5758 /* Return the string to output a conditional branch to LABEL, which is
5759 the operand number of the label. OP is the conditional expression.
5760 XEXP (OP, 0) is assumed to be a condition code register (integer or
5761 floating point) and its mode specifies what kind of comparison we made.
5763 REVERSED is nonzero if we should reverse the sense of the comparison.
5765 ANNUL is nonzero if we should generate an annulling branch.
5767 NOOP is nonzero if we have to follow this branch by a noop.
5769 INSN, if set, is the insn. */
5772 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5775 static char string[50];
5776 enum rtx_code code = GET_CODE (op);
5777 rtx cc_reg = XEXP (op, 0);
5778 enum machine_mode mode = GET_MODE (cc_reg);
5779 const char *labelno, *branch;
5780 int spaces = 8, far;
5783 /* v9 branches are limited to +-1MB. If it is too far away,
5796 fbne,a,pn %fcc2, .LC29
5804 far = get_attr_length (insn) >= 3;
5807 /* Reversal of FP compares takes care -- an ordered compare
5808 becomes an unordered compare and vice versa. */
5809 if (mode == CCFPmode || mode == CCFPEmode)
5810 code = reverse_condition_maybe_unordered (code);
5812 code = reverse_condition (code);
5815 /* Start by writing the branch condition. */
5816 if (mode == CCFPmode || mode == CCFPEmode)
5867 /* ??? !v9: FP branches cannot be preceded by another floating point
5868 insn. Because there is currently no concept of pre-delay slots,
5869 we can fix this only by always emitting a nop before a floating
5874 strcpy (string, "nop\n\t");
5875 strcat (string, branch);
5888 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5900 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5921 strcpy (string, branch);
5923 spaces -= strlen (branch);
5924 p = strchr (string, '\0');
5926 /* Now add the annulling, the label, and a possible noop. */
5941 if (! far && insn && INSN_ADDRESSES_SET_P ())
5943 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5944 - INSN_ADDRESSES (INSN_UID (insn)));
5945 /* Leave some instructions for "slop". */
5946 if (delta < -260000 || delta >= 260000)
5950 if (mode == CCFPmode || mode == CCFPEmode)
5952 static char v9_fcc_labelno[] = "%%fccX, ";
5953 /* Set the char indicating the number of the fcc reg to use. */
5954 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5955 labelno = v9_fcc_labelno;
5958 if (REGNO (cc_reg) == SPARC_FCC_REG)
5964 else if (mode == CCXmode || mode == CCX_NOOVmode)
5966 labelno = "%%xcc, ";
5972 labelno = "%%icc, ";
5977 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5980 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5990 strcpy (p, labelno);
5991 p = strchr (p, '\0');
5994 strcpy (p, ".+12\n\tnop\n\tb\t");
6001 /* Set the char indicating the number of the operand containing the
6006 strcpy (p, "\n\tnop");
6011 /* Emit a library call comparison between floating point X and Y.
6012 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6013 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6014 values as arguments instead of the TFmode registers themselves,
6015 that's why we cannot call emit_float_lib_cmp. */
6017 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6020 rtx slot0, slot1, result, tem, tem2;
6021 enum machine_mode mode;
6026 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6030 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6034 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6038 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6042 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6046 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6057 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6067 if (GET_CODE (x) != MEM)
6069 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6070 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6075 if (GET_CODE (y) != MEM)
6077 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6078 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6083 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6085 XEXP (slot0, 0), Pmode,
6086 XEXP (slot1, 0), Pmode);
6092 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6094 x, TFmode, y, TFmode);
6100 /* Immediately move the result of the libcall into a pseudo
6101 register so reload doesn't clobber the value if it needs
6102 the return register for a spill reg. */
6103 result = gen_reg_rtx (mode);
6104 emit_move_insn (result, hard_libcall_value (mode));
6109 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6113 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6118 emit_cmp_insn (result, const1_rtx,
6119 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6122 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6125 tem = gen_reg_rtx (mode);
6127 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6129 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6130 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6134 tem = gen_reg_rtx (mode);
6136 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6138 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6139 tem2 = gen_reg_rtx (mode);
6141 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6143 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6144 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6150 /* Generate an unsigned DImode to FP conversion. This is the same code
6151 optabs would emit if we didn't have TFmode patterns. */
6154 sparc_emit_floatunsdi (rtx *operands)
6156 rtx neglab, donelab, i0, i1, f0, in, out;
6157 enum machine_mode mode;
6160 in = force_reg (DImode, operands[1]);
6161 mode = GET_MODE (out);
6162 neglab = gen_label_rtx ();
6163 donelab = gen_label_rtx ();
6164 i0 = gen_reg_rtx (DImode);
6165 i1 = gen_reg_rtx (DImode);
6166 f0 = gen_reg_rtx (mode);
6168 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6170 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6171 emit_jump_insn (gen_jump (donelab));
6174 emit_label (neglab);
6176 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6177 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6178 emit_insn (gen_iordi3 (i0, i0, i1));
6179 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6180 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6182 emit_label (donelab);
6185 /* Return the string to output a conditional branch to LABEL, testing
6186 register REG. LABEL is the operand number of the label; REG is the
6187 operand number of the reg. OP is the conditional expression. The mode
6188 of REG says what kind of comparison we made.
6190 REVERSED is nonzero if we should reverse the sense of the comparison.
6192 ANNUL is nonzero if we should generate an annulling branch.
6194 NOOP is nonzero if we have to follow this branch by a noop. */
6197 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6198 int annul, int noop, rtx insn)
6200 static char string[50];
6201 enum rtx_code code = GET_CODE (op);
6202 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6207 /* branch on register are limited to +-128KB. If it is too far away,
6220 brgez,a,pn %o1, .LC29
6226 ba,pt %xcc, .LC29 */
6228 far = get_attr_length (insn) >= 3;
6230 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6232 code = reverse_condition (code);
6234 /* Only 64 bit versions of these instructions exist. */
6238 /* Start by writing the branch condition. */
6243 strcpy (string, "brnz");
6247 strcpy (string, "brz");
6251 strcpy (string, "brgez");
6255 strcpy (string, "brlz");
6259 strcpy (string, "brlez");
6263 strcpy (string, "brgz");
6270 p = strchr (string, '\0');
6272 /* Now add the annulling, reg, label, and nop. */
6279 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6282 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6287 *p = p < string + 8 ? '\t' : ' ';
6295 int veryfar = 1, delta;
6297 if (INSN_ADDRESSES_SET_P ())
6299 delta = (INSN_ADDRESSES (INSN_UID (dest))
6300 - INSN_ADDRESSES (INSN_UID (insn)));
6301 /* Leave some instructions for "slop". */
6302 if (delta >= -260000 && delta < 260000)
6306 strcpy (p, ".+12\n\tnop\n\t");
6317 strcpy (p, "ba,pt\t%%xcc, ");
6327 strcpy (p, "\n\tnop");
6332 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6333 Such instructions cannot be used in the delay slot of return insn on v9.
6334 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6338 epilogue_renumber (register rtx *where, int test)
6340 register const char *fmt;
6342 register enum rtx_code code;
6347 code = GET_CODE (*where);
6352 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6354 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6355 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6363 /* Do not replace the frame pointer with the stack pointer because
6364 it can cause the delayed instruction to load below the stack.
6365 This occurs when instructions like:
6367 (set (reg/i:SI 24 %i0)
6368 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6369 (const_int -20 [0xffffffec])) 0))
6371 are in the return delayed slot. */
6373 if (GET_CODE (XEXP (*where, 0)) == REG
6374 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6375 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6376 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6381 if (SPARC_STACK_BIAS
6382 && GET_CODE (XEXP (*where, 0)) == REG
6383 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6391 fmt = GET_RTX_FORMAT (code);
6393 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6398 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6399 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6402 else if (fmt[i] == 'e'
6403 && epilogue_renumber (&(XEXP (*where, i)), test))
6409 /* Leaf functions and non-leaf functions have different needs. */
6412 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6415 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6417 static const int *const reg_alloc_orders[] = {
6418 reg_leaf_alloc_order,
6419 reg_nonleaf_alloc_order};
6422 order_regs_for_local_alloc (void)
6424 static int last_order_nonleaf = 1;
6426 if (regs_ever_live[15] != last_order_nonleaf)
6428 last_order_nonleaf = !last_order_nonleaf;
6429 memcpy ((char *) reg_alloc_order,
6430 (const char *) reg_alloc_orders[last_order_nonleaf],
6431 FIRST_PSEUDO_REGISTER * sizeof (int));
6435 /* Return 1 if REG and MEM are legitimate enough to allow the various
6436 mem<-->reg splits to be run. */
6439 sparc_splitdi_legitimate (rtx reg, rtx mem)
6441 /* Punt if we are here by mistake. */
6442 if (! reload_completed)
6445 /* We must have an offsettable memory reference. */
6446 if (! offsettable_memref_p (mem))
6449 /* If we have legitimate args for ldd/std, we do not want
6450 the split to happen. */
6451 if ((REGNO (reg) % 2) == 0
6452 && mem_min_alignment (mem, 8))
6459 /* Return 1 if x and y are some kind of REG and they refer to
6460 different hard registers. This test is guaranteed to be
6461 run after reload. */
6464 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6466 if (GET_CODE (x) != REG)
6468 if (GET_CODE (y) != REG)
6470 if (REGNO (x) == REGNO (y))
6475 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6476 This makes them candidates for using ldd and std insns.
6478 Note reg1 and reg2 *must* be hard registers. */
6481 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6483 /* We might have been passed a SUBREG. */
6484 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6487 if (REGNO (reg1) % 2 != 0)
6490 /* Integer ldd is deprecated in SPARC V9 */
6491 if (TARGET_V9 && REGNO (reg1) < 32)
6494 return (REGNO (reg1) == REGNO (reg2) - 1);
6497 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6500 This can only happen when addr1 and addr2, the addresses in mem1
6501 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6502 addr1 must also be aligned on a 64-bit boundary.
6504 Also iff dependent_reg_rtx is not null it should not be used to
6505 compute the address for mem1, i.e. we cannot optimize a sequence
6517 But, note that the transformation from:
6522 is perfectly fine. Thus, the peephole2 patterns always pass us
6523 the destination register of the first load, never the second one.
6525 For stores we don't have a similar problem, so dependent_reg_rtx is
6529 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6535 /* The mems cannot be volatile. */
6536 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6539 /* MEM1 should be aligned on a 64-bit boundary. */
6540 if (MEM_ALIGN (mem1) < 64)
6543 addr1 = XEXP (mem1, 0);
6544 addr2 = XEXP (mem2, 0);
6546 /* Extract a register number and offset (if used) from the first addr. */
6547 if (GET_CODE (addr1) == PLUS)
6549 /* If not a REG, return zero. */
6550 if (GET_CODE (XEXP (addr1, 0)) != REG)
6554 reg1 = REGNO (XEXP (addr1, 0));
6555 /* The offset must be constant! */
6556 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6558 offset1 = INTVAL (XEXP (addr1, 1));
6561 else if (GET_CODE (addr1) != REG)
6565 reg1 = REGNO (addr1);
6566 /* This was a simple (mem (reg)) expression. Offset is 0. */
6570 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6571 if (GET_CODE (addr2) != PLUS)
6574 if (GET_CODE (XEXP (addr2, 0)) != REG
6575 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6578 if (reg1 != REGNO (XEXP (addr2, 0)))
6581 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6584 /* The first offset must be evenly divisible by 8 to ensure the
6585 address is 64 bit aligned. */
6586 if (offset1 % 8 != 0)
6589 /* The offset for the second addr must be 4 more than the first addr. */
6590 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6593 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6598 /* Return 1 if reg is a pseudo, or is the first register in
6599 a hard register pair. This makes it a candidate for use in
6600 ldd and std insns. */
6603 register_ok_for_ldd (rtx reg)
6605 /* We might have been passed a SUBREG. */
6606 if (GET_CODE (reg) != REG)
6609 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6610 return (REGNO (reg) % 2 == 0);
6615 /* Print operand X (an rtx) in assembler syntax to file FILE.
6616 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6617 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6620 print_operand (FILE *file, rtx x, int code)
6625 /* Output a 'nop' if there's nothing for the delay slot. */
6626 if (dbr_sequence_length () == 0)
6627 fputs ("\n\t nop", file);
6630 /* Output an annul flag if there's nothing for the delay slot and we
6631 are optimizing. This is always used with '(' below. */
6632 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6633 this is a dbx bug. So, we only do this when optimizing. */
6634 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6635 Always emit a nop in case the next instruction is a branch. */
6636 if (dbr_sequence_length () == 0
6637 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6641 /* Output a 'nop' if there's nothing for the delay slot and we are
6642 not optimizing. This is always used with '*' above. */
6643 if (dbr_sequence_length () == 0
6644 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6645 fputs ("\n\t nop", file);
6648 /* Output the Embedded Medium/Anywhere code model base register. */
6649 fputs (EMBMEDANY_BASE_REG, file);
6652 /* Print out what we are using as the frame pointer. This might
6653 be %fp, or might be %sp+offset. */
6654 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6655 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6658 /* Print some local dynamic TLS name. */
6659 assemble_name (file, get_some_local_dynamic_name ());
6662 /* Adjust the operand to take into account a RESTORE operation. */
6663 if (GET_CODE (x) == CONST_INT)
6665 else if (GET_CODE (x) != REG)
6666 output_operand_lossage ("invalid %%Y operand");
6667 else if (REGNO (x) < 8)
6668 fputs (reg_names[REGNO (x)], file);
6669 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6670 fputs (reg_names[REGNO (x)-16], file);
6672 output_operand_lossage ("invalid %%Y operand");
6675 /* Print out the low order register name of a register pair. */
6676 if (WORDS_BIG_ENDIAN)
6677 fputs (reg_names[REGNO (x)+1], file);
6679 fputs (reg_names[REGNO (x)], file);
6682 /* Print out the high order register name of a register pair. */
6683 if (WORDS_BIG_ENDIAN)
6684 fputs (reg_names[REGNO (x)], file);
6686 fputs (reg_names[REGNO (x)+1], file);
6689 /* Print out the second register name of a register pair or quad.
6690 I.e., R (%o0) => %o1. */
6691 fputs (reg_names[REGNO (x)+1], file);
6694 /* Print out the third register name of a register quad.
6695 I.e., S (%o0) => %o2. */
6696 fputs (reg_names[REGNO (x)+2], file);
6699 /* Print out the fourth register name of a register quad.
6700 I.e., T (%o0) => %o3. */
6701 fputs (reg_names[REGNO (x)+3], file);
6704 /* Print a condition code register. */
6705 if (REGNO (x) == SPARC_ICC_REG)
6707 /* We don't handle CC[X]_NOOVmode because they're not supposed
6709 if (GET_MODE (x) == CCmode)
6710 fputs ("%icc", file);
6711 else if (GET_MODE (x) == CCXmode)
6712 fputs ("%xcc", file);
6717 /* %fccN register */
6718 fputs (reg_names[REGNO (x)], file);
6721 /* Print the operand's address only. */
6722 output_address (XEXP (x, 0));
6725 /* In this case we need a register. Use %g0 if the
6726 operand is const0_rtx. */
6728 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6730 fputs ("%g0", file);
6737 switch (GET_CODE (x))
6739 case IOR: fputs ("or", file); break;
6740 case AND: fputs ("and", file); break;
6741 case XOR: fputs ("xor", file); break;
6742 default: output_operand_lossage ("invalid %%A operand");
6747 switch (GET_CODE (x))
6749 case IOR: fputs ("orn", file); break;
6750 case AND: fputs ("andn", file); break;
6751 case XOR: fputs ("xnor", file); break;
6752 default: output_operand_lossage ("invalid %%B operand");
6756 /* These are used by the conditional move instructions. */
6760 enum rtx_code rc = GET_CODE (x);
6764 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6765 if (mode == CCFPmode || mode == CCFPEmode)
6766 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6768 rc = reverse_condition (GET_CODE (x));
6772 case NE: fputs ("ne", file); break;
6773 case EQ: fputs ("e", file); break;
6774 case GE: fputs ("ge", file); break;
6775 case GT: fputs ("g", file); break;
6776 case LE: fputs ("le", file); break;
6777 case LT: fputs ("l", file); break;
6778 case GEU: fputs ("geu", file); break;
6779 case GTU: fputs ("gu", file); break;
6780 case LEU: fputs ("leu", file); break;
6781 case LTU: fputs ("lu", file); break;
6782 case LTGT: fputs ("lg", file); break;
6783 case UNORDERED: fputs ("u", file); break;
6784 case ORDERED: fputs ("o", file); break;
6785 case UNLT: fputs ("ul", file); break;
6786 case UNLE: fputs ("ule", file); break;
6787 case UNGT: fputs ("ug", file); break;
6788 case UNGE: fputs ("uge", file); break;
6789 case UNEQ: fputs ("ue", file); break;
6790 default: output_operand_lossage (code == 'c'
6791 ? "invalid %%c operand"
6792 : "invalid %%C operand");
6797 /* These are used by the movr instruction pattern. */
6801 enum rtx_code rc = (code == 'd'
6802 ? reverse_condition (GET_CODE (x))
6806 case NE: fputs ("ne", file); break;
6807 case EQ: fputs ("e", file); break;
6808 case GE: fputs ("gez", file); break;
6809 case LT: fputs ("lz", file); break;
6810 case LE: fputs ("lez", file); break;
6811 case GT: fputs ("gz", file); break;
6812 default: output_operand_lossage (code == 'd'
6813 ? "invalid %%d operand"
6814 : "invalid %%D operand");
6821 /* Print a sign-extended character. */
6822 int i = trunc_int_for_mode (INTVAL (x), QImode);
6823 fprintf (file, "%d", i);
6828 /* Operand must be a MEM; write its address. */
6829 if (GET_CODE (x) != MEM)
6830 output_operand_lossage ("invalid %%f operand");
6831 output_address (XEXP (x, 0));
6836 /* Print a sign-extended 32-bit value. */
6838 if (GET_CODE(x) == CONST_INT)
6840 else if (GET_CODE(x) == CONST_DOUBLE)
6841 i = CONST_DOUBLE_LOW (x);
6844 output_operand_lossage ("invalid %%s operand");
6847 i = trunc_int_for_mode (i, SImode);
6848 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6853 /* Do nothing special. */
6857 /* Undocumented flag. */
6858 output_operand_lossage ("invalid operand output code");
6861 if (GET_CODE (x) == REG)
6862 fputs (reg_names[REGNO (x)], file);
6863 else if (GET_CODE (x) == MEM)
6866 /* Poor Sun assembler doesn't understand absolute addressing. */
6867 if (CONSTANT_P (XEXP (x, 0)))
6868 fputs ("%g0+", file);
6869 output_address (XEXP (x, 0));
6872 else if (GET_CODE (x) == HIGH)
6874 fputs ("%hi(", file);
6875 output_addr_const (file, XEXP (x, 0));
6878 else if (GET_CODE (x) == LO_SUM)
6880 print_operand (file, XEXP (x, 0), 0);
6881 if (TARGET_CM_MEDMID)
6882 fputs ("+%l44(", file);
6884 fputs ("+%lo(", file);
6885 output_addr_const (file, XEXP (x, 1));
6888 else if (GET_CODE (x) == CONST_DOUBLE
6889 && (GET_MODE (x) == VOIDmode
6890 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6892 if (CONST_DOUBLE_HIGH (x) == 0)
6893 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6894 else if (CONST_DOUBLE_HIGH (x) == -1
6895 && CONST_DOUBLE_LOW (x) < 0)
6896 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6898 output_operand_lossage ("long long constant not a valid immediate operand");
6900 else if (GET_CODE (x) == CONST_DOUBLE)
6901 output_operand_lossage ("floating point constant not a valid immediate operand");
6902 else { output_addr_const (file, x); }
6905 /* Target hook for assembling integer objects. The sparc version has
6906 special handling for aligned DI-mode objects. */
6909 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6911 /* ??? We only output .xword's for symbols and only then in environments
6912 where the assembler can handle them. */
6913 if (aligned_p && size == 8
6914 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6918 assemble_integer_with_op ("\t.xword\t", x);
6923 assemble_aligned_integer (4, const0_rtx);
6924 assemble_aligned_integer (4, x);
6928 return default_assemble_integer (x, size, aligned_p);
6931 /* Return the value of a code used in the .proc pseudo-op that says
6932 what kind of result this function returns. For non-C types, we pick
6933 the closest C type. */
6935 #ifndef SHORT_TYPE_SIZE
6936 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6939 #ifndef INT_TYPE_SIZE
6940 #define INT_TYPE_SIZE BITS_PER_WORD
6943 #ifndef LONG_TYPE_SIZE
6944 #define LONG_TYPE_SIZE BITS_PER_WORD
6947 #ifndef LONG_LONG_TYPE_SIZE
6948 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6951 #ifndef FLOAT_TYPE_SIZE
6952 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6955 #ifndef DOUBLE_TYPE_SIZE
6956 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6959 #ifndef LONG_DOUBLE_TYPE_SIZE
6960 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6964 sparc_type_code (register tree type)
6966 register unsigned long qualifiers = 0;
6967 register unsigned shift;
6969 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6970 setting more, since some assemblers will give an error for this. Also,
6971 we must be careful to avoid shifts of 32 bits or more to avoid getting
6972 unpredictable results. */
6974 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6976 switch (TREE_CODE (type))
6982 qualifiers |= (3 << shift);
6987 qualifiers |= (2 << shift);
6991 case REFERENCE_TYPE:
6993 qualifiers |= (1 << shift);
6997 return (qualifiers | 8);
7000 case QUAL_UNION_TYPE:
7001 return (qualifiers | 9);
7004 return (qualifiers | 10);
7007 return (qualifiers | 16);
7010 /* If this is a range type, consider it to be the underlying
7012 if (TREE_TYPE (type) != 0)
7015 /* Carefully distinguish all the standard types of C,
7016 without messing up if the language is not C. We do this by
7017 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7018 look at both the names and the above fields, but that's redundant.
7019 Any type whose size is between two C types will be considered
7020 to be the wider of the two types. Also, we do not have a
7021 special code to use for "long long", so anything wider than
7022 long is treated the same. Note that we can't distinguish
7023 between "int" and "long" in this code if they are the same
7024 size, but that's fine, since neither can the assembler. */
7026 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7027 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7029 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7030 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7032 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7033 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7036 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7039 /* If this is a range type, consider it to be the underlying
7041 if (TREE_TYPE (type) != 0)
7044 /* Carefully distinguish all the standard types of C,
7045 without messing up if the language is not C. */
7047 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7048 return (qualifiers | 6);
7051 return (qualifiers | 7);
7053 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7054 /* ??? We need to distinguish between double and float complex types,
7055 but I don't know how yet because I can't reach this code from
7056 existing front-ends. */
7057 return (qualifiers | 7); /* Who knows? */
7059 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7060 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7061 case FILE_TYPE: /* GNU Pascal FILE type. */
7062 case SET_TYPE: /* GNU Pascal SET type. */
7063 case LANG_TYPE: /* ? */
7067 abort (); /* Not a type! */
7074 /* Nested function support. */
7076 /* Emit RTL insns to initialize the variable parts of a trampoline.
7077 FNADDR is an RTX for the address of the function's pure code.
7078 CXT is an RTX for the static chain value for the function.
7080 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7081 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7082 (to store insns). This is a bit excessive. Perhaps a different
7083 mechanism would be better here.
7085 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7088 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7090 /* SPARC 32-bit trampoline:
7093 sethi %hi(static), %g2
7095 or %g2, %lo(static), %g2
7097 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7098 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7102 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7103 expand_binop (SImode, ior_optab,
7104 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7105 size_int (10), 0, 1),
7106 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7107 NULL_RTX, 1, OPTAB_DIRECT));
7110 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7111 expand_binop (SImode, ior_optab,
7112 expand_shift (RSHIFT_EXPR, SImode, cxt,
7113 size_int (10), 0, 1),
7114 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7115 NULL_RTX, 1, OPTAB_DIRECT));
7118 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7119 expand_binop (SImode, ior_optab,
7120 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7121 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7122 NULL_RTX, 1, OPTAB_DIRECT));
7125 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7126 expand_binop (SImode, ior_optab,
7127 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7128 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7129 NULL_RTX, 1, OPTAB_DIRECT));
7131 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7132 aligned on a 16 byte boundary so one flush clears it all. */
7133 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7134 if (sparc_cpu != PROCESSOR_ULTRASPARC
7135 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7136 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7137 plus_constant (tramp, 8)))));
7139 /* Call __enable_execute_stack after writing onto the stack to make sure
7140 the stack address is accessible. */
7141 #ifdef TRANSFER_FROM_TRAMPOLINE
7142 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7143 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7148 /* The 64-bit version is simpler because it makes more sense to load the
7149 values as "immediate" data out of the trampoline. It's also easier since
7150 we can read the PC without clobbering a register. */
7153 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7155 /* SPARC 64-bit trampoline:
7164 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7165 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7166 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7167 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7168 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7169 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7170 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7171 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7172 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7173 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7174 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7176 if (sparc_cpu != PROCESSOR_ULTRASPARC
7177 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7178 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7180 /* Call __enable_execute_stack after writing onto the stack to make sure
7181 the stack address is accessible. */
7182 #ifdef TRANSFER_FROM_TRAMPOLINE
7183 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7184 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7188 /* Subroutines to support a flat (single) register window calling
7191 /* Single-register window sparc stack frames look like:
7193 Before call After call
7194 +-----------------------+ +-----------------------+
7196 mem | caller's temps. | | caller's temps. |
7198 +-----------------------+ +-----------------------+
7200 | arguments on stack. | | arguments on stack. |
7202 +-----------------------+FP+92->+-----------------------+
7203 | 6 words to save | | 6 words to save |
7204 | arguments passed | | arguments passed |
7205 | in registers, even | | in registers, even |
7206 | if not passed. | | if not passed. |
7207 SP+68->+-----------------------+FP+68->+-----------------------+
7208 | 1 word struct addr | | 1 word struct addr |
7209 +-----------------------+FP+64->+-----------------------+
7211 | 16 word reg save area | | 16 word reg save area |
7213 SP->+-----------------------+ FP->+-----------------------+
7215 | fp/alu reg moves |
7216 FP-16->+-----------------------+
7220 +-----------------------+
7222 | fp register save |
7224 +-----------------------+
7226 | gp register save |
7228 +-----------------------+
7230 | alloca allocations |
7232 +-----------------------+
7234 | arguments on stack |
7236 SP+92->+-----------------------+
7238 | arguments passed |
7239 | in registers, even |
7240 low | if not passed. |
7241 memory SP+68->+-----------------------+
7242 | 1 word struct addr |
7243 SP+64->+-----------------------+
7245 I 16 word reg save area |
7247 SP->+-----------------------+ */
7249 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7250 save masks, and offsets for the current function. */
7252 struct sparc_frame_info
7254 unsigned long total_size; /* # bytes that the entire frame takes up. */
7255 unsigned long var_size; /* # bytes that variables take up. */
7256 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7257 unsigned long extra_size; /* # bytes of extra gunk. */
7258 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7259 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7260 unsigned long gmask; /* Mask of saved gp registers. */
7261 unsigned long fmask; /* Mask of saved fp registers. */
7262 unsigned long reg_offset; /* Offset from new sp to store regs. */
7263 int initialized; /* Nonzero if frame size already calculated. */
7266 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7267 struct sparc_frame_info current_frame_info;
7269 /* Zero structure to initialize current_frame_info. */
7270 struct sparc_frame_info zero_frame_info;
7272 #define RETURN_ADDR_REGNUM 15
7273 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7274 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7276 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7279 sparc_flat_must_save_register_p (int regno)
7281 /* General case: call-saved registers live at some point. */
7282 if (!call_used_regs[regno] && regs_ever_live[regno])
7285 /* Frame pointer register (%i7) if needed. */
7286 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7289 /* PIC register (%l7) if needed. */
7290 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7291 && flag_pic && current_function_uses_pic_offset_table)
7294 /* Return address register (%o7) if needed. */
7295 if (regno == RETURN_ADDR_REGNUM
7296 && (regs_ever_live[RETURN_ADDR_REGNUM]
7297 /* When the PIC offset table is used, the PIC register
7298 is set by using a bare call that clobbers %o7. */
7299 || (flag_pic && current_function_uses_pic_offset_table)))
7305 /* Return the bytes needed to compute the frame pointer from the current
7309 sparc_flat_compute_frame_size (int size)
7310 /* # of var. bytes allocated. */
7313 unsigned long total_size; /* # bytes that the entire frame takes up. */
7314 unsigned long var_size; /* # bytes that variables take up. */
7315 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7316 unsigned long extra_size; /* # extra bytes. */
7317 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7318 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7319 unsigned long gmask; /* Mask of saved gp registers. */
7320 unsigned long fmask; /* Mask of saved fp registers. */
7321 unsigned long reg_offset; /* Offset to register save area. */
7322 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7324 /* This is the size of the 16 word reg save area, 1 word struct addr
7325 area, and 4 word fp/alu register copy area. */
7326 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7336 if (!leaf_function_p ())
7338 /* Also include the size needed for the 6 parameter registers. */
7339 args_size = current_function_outgoing_args_size + 24;
7341 total_size = var_size + args_size;
7343 /* Calculate space needed for gp registers. */
7344 for (regno = 1; regno <= 31; regno++)
7346 if (sparc_flat_must_save_register_p (regno))
7348 /* If we need to save two regs in a row, ensure there's room to bump
7349 up the address to align it to a doubleword boundary. */
7350 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7352 if (gp_reg_size % 8 != 0)
7354 gp_reg_size += 2 * UNITS_PER_WORD;
7355 gmask |= 3 << regno;
7361 gp_reg_size += UNITS_PER_WORD;
7362 gmask |= 1 << regno;
7367 /* Calculate space needed for fp registers. */
7368 for (regno = 32; regno <= 63; regno++)
7370 if (regs_ever_live[regno] && !call_used_regs[regno])
7372 fp_reg_size += UNITS_PER_WORD;
7373 fmask |= 1 << (regno - 32);
7380 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7381 /* Ensure save area is 8 byte aligned if we need it. */
7383 if (need_aligned_p && n != 0)
7385 total_size += 8 - n;
7386 reg_offset += 8 - n;
7388 total_size += gp_reg_size + fp_reg_size;
7391 /* If we must allocate a stack frame at all, we must also allocate
7392 room for register window spillage, so as to be binary compatible
7393 with libraries and operating systems that do not use -mflat. */
7395 total_size += extra_size;
7399 total_size = SPARC_STACK_ALIGN (total_size);
7401 /* Save other computed information. */
7402 current_frame_info.total_size = total_size;
7403 current_frame_info.var_size = var_size;
7404 current_frame_info.args_size = args_size;
7405 current_frame_info.extra_size = extra_size;
7406 current_frame_info.gp_reg_size = gp_reg_size;
7407 current_frame_info.fp_reg_size = fp_reg_size;
7408 current_frame_info.gmask = gmask;
7409 current_frame_info.fmask = fmask;
7410 current_frame_info.reg_offset = reg_offset;
7411 current_frame_info.initialized = reload_completed;
7413 /* Ok, we're done. */
7417 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7420 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7421 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7422 [BASE_REG+OFFSET] will always be a valid address.
7424 WORD_OP is either "st" for save, "ld" for restore.
7425 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7428 sparc_flat_save_restore (FILE *file, const char *base_reg,
7429 unsigned int offset, long unsigned int gmask,
7430 long unsigned int fmask, const char *word_op,
7431 const char *doubleword_op,
7432 long unsigned int base_offset)
7436 if (gmask == 0 && fmask == 0)
7439 /* Save registers starting from high to low. We've already saved the
7440 previous frame pointer and previous return address for the debugger's
7441 sake. The debugger allows us to not need a nop in the epilog if at least
7442 one register is reloaded in addition to return address. */
7446 for (regno = 1; regno <= 31; regno++)
7448 if ((gmask & (1L << regno)) != 0)
7450 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7452 /* We can save two registers in a row. If we're not at a
7453 double word boundary, move to one.
7454 sparc_flat_compute_frame_size ensures there's room to do
7456 if (offset % 8 != 0)
7457 offset += UNITS_PER_WORD;
7459 if (word_op[0] == 's')
7461 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7462 doubleword_op, reg_names[regno],
7464 if (dwarf2out_do_frame ())
7466 char *l = dwarf2out_cfi_label ();
7467 dwarf2out_reg_save (l, regno, offset + base_offset);
7469 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7473 fprintf (file, "\t%s\t[%s+%d], %s\n",
7474 doubleword_op, base_reg, offset,
7477 offset += 2 * UNITS_PER_WORD;
7482 if (word_op[0] == 's')
7484 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7485 word_op, reg_names[regno],
7487 if (dwarf2out_do_frame ())
7488 dwarf2out_reg_save ("", regno, offset + base_offset);
7491 fprintf (file, "\t%s\t[%s+%d], %s\n",
7492 word_op, base_reg, offset, reg_names[regno]);
7494 offset += UNITS_PER_WORD;
7502 for (regno = 32; regno <= 63; regno++)
7504 if ((fmask & (1L << (regno - 32))) != 0)
7506 if (word_op[0] == 's')
7508 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7509 word_op, reg_names[regno],
7511 if (dwarf2out_do_frame ())
7512 dwarf2out_reg_save ("", regno, offset + base_offset);
7515 fprintf (file, "\t%s\t[%s+%d], %s\n",
7516 word_op, base_reg, offset, reg_names[regno]);
7518 offset += UNITS_PER_WORD;
7524 /* Set up the stack and frame (if desired) for the function. */
7527 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7529 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7530 unsigned long gmask = current_frame_info.gmask;
7532 sparc_output_scratch_registers (file);
7534 /* This is only for the human reader. */
7535 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7536 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7538 current_frame_info.var_size,
7539 current_frame_info.gp_reg_size / 4,
7540 current_frame_info.fp_reg_size / 4,
7541 current_function_outgoing_args_size,
7542 current_frame_info.extra_size);
7544 size = SPARC_STACK_ALIGN (size);
7545 size = (! current_frame_info.initialized
7546 ? sparc_flat_compute_frame_size (size)
7547 : current_frame_info.total_size);
7549 /* These cases shouldn't happen. Catch them now. */
7550 if (size == 0 && (gmask || current_frame_info.fmask))
7553 /* Allocate our stack frame by decrementing %sp.
7554 At present, the only algorithm gdb can use to determine if this is a
7555 flat frame is if we always set %i7 if we set %sp. This can be optimized
7556 in the future by putting in some sort of debugging information that says
7557 this is a `flat' function. However, there is still the case of debugging
7558 code without such debugging information (including cases where most fns
7559 have such info, but there is one that doesn't). So, always do this now
7560 so we don't get a lot of code out there that gdb can't handle.
7561 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7562 distinguish us from a non-flat function but there won't (and shouldn't)
7563 be any differences anyway. The return pc is saved (if necessary) right
7564 after %i7 so gdb won't have to look too far to find it. */
7567 unsigned int reg_offset = current_frame_info.reg_offset;
7568 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7569 static const char *const t1_str = "%g1";
7571 /* Things get a little tricky if local variables take up more than ~4096
7572 bytes and outgoing arguments take up more than ~4096 bytes. When that
7573 happens, the register save area can't be accessed from either end of
7574 the frame. Handle this by decrementing %sp to the start of the gp
7575 register save area, save the regs, update %i7, and then set %sp to its
7576 final value. Given that we only have one scratch register to play
7577 with it is the cheapest solution, and it helps gdb out as it won't
7578 slow down recognition of flat functions.
7579 Don't change the order of insns emitted here without checking with
7580 the gdb folk first. */
7582 /* Is the entire register save area offsettable from %sp? */
7583 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7587 fprintf (file, "\tadd\t%s, %d, %s\n",
7588 sp_str, (int) -size, sp_str);
7589 if (gmask & HARD_FRAME_POINTER_MASK)
7591 fprintf (file, "\tst\t%s, [%s+%d]\n",
7592 fp_str, sp_str, reg_offset);
7593 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7594 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7600 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7601 ", %s\n\tsub\t%s, %s, %s\n",
7602 size, t1_str, sp_str, t1_str, sp_str);
7603 if (gmask & HARD_FRAME_POINTER_MASK)
7605 fprintf (file, "\tst\t%s, [%s+%d]\n",
7606 fp_str, sp_str, reg_offset);
7607 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7608 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7612 if (dwarf2out_do_frame ())
7614 char *l = dwarf2out_cfi_label ();
7615 if (gmask & HARD_FRAME_POINTER_MASK)
7617 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7618 reg_offset - 4 - size);
7619 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7622 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7624 if (gmask & RETURN_ADDR_MASK)
7626 fprintf (file, "\tst\t%s, [%s+%d]\n",
7627 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7628 if (dwarf2out_do_frame ())
7629 dwarf2out_return_save ("", reg_offset - size);
7632 sparc_flat_save_restore (file, sp_str, reg_offset,
7633 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7634 current_frame_info.fmask,
7635 "st", "std", -size);
7639 /* Subtract %sp in two steps, but make sure there is always a
7640 64 byte register save area, and %sp is properly aligned. */
7641 /* Amount to decrement %sp by, the first time. */
7642 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7643 /* Offset to register save area from %sp. */
7644 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7648 fprintf (file, "\tadd\t%s, %d, %s\n",
7649 sp_str, (int) -size1, sp_str);
7650 if (gmask & HARD_FRAME_POINTER_MASK)
7652 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7653 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7654 fp_str, ASM_COMMENT_START);
7660 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7661 ", %s\n\tsub\t%s, %s, %s\n",
7662 size1, t1_str, sp_str, t1_str, sp_str);
7663 if (gmask & HARD_FRAME_POINTER_MASK)
7665 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7666 fp_str, sp_str, (int) offset, sp_str, t1_str,
7667 fp_str, ASM_COMMENT_START);
7671 if (dwarf2out_do_frame ())
7673 char *l = dwarf2out_cfi_label ();
7674 if (gmask & HARD_FRAME_POINTER_MASK)
7676 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7677 offset - 4 - size1);
7678 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7681 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7683 if (gmask & RETURN_ADDR_MASK)
7685 fprintf (file, "\tst\t%s, [%s+%d]\n",
7686 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7687 if (dwarf2out_do_frame ())
7688 /* offset - size1 == reg_offset - size
7689 if reg_offset were updated above like offset. */
7690 dwarf2out_return_save ("", offset - size1);
7693 sparc_flat_save_restore (file, sp_str, offset,
7694 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7695 current_frame_info.fmask,
7696 "st", "std", -size1);
7697 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7698 ", %s\n\tsub\t%s, %s, %s\n",
7699 size - size1, t1_str, sp_str, t1_str, sp_str);
7700 if (dwarf2out_do_frame ())
7701 if (! (gmask & HARD_FRAME_POINTER_MASK))
7702 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7706 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7709 /* Do any necessary cleanup after a function to restore stack, frame,
7713 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7715 rtx epilogue_delay = current_function_epilogue_delay_list;
7716 int noepilogue = FALSE;
7718 /* This is only for the human reader. */
7719 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7721 /* The epilogue does not depend on any registers, but the stack
7722 registers, so we assume that if we have 1 pending nop, it can be
7723 ignored, and 2 it must be filled (2 nops occur for integer
7724 multiply and divide). */
7726 size = SPARC_STACK_ALIGN (size);
7727 size = (!current_frame_info.initialized
7728 ? sparc_flat_compute_frame_size (size)
7729 : current_frame_info.total_size);
7731 if (size == 0 && epilogue_delay == 0)
7733 rtx insn = get_last_insn ();
7735 /* If the last insn was a BARRIER, we don't have to write any code
7736 because a jump (aka return) was put there. */
7737 if (GET_CODE (insn) == NOTE)
7738 insn = prev_nonnote_insn (insn);
7739 if (insn && GET_CODE (insn) == BARRIER)
7745 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7746 unsigned HOST_WIDE_INT size1;
7747 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7748 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7749 static const char *const t1_str = "%g1";
7751 /* In the reload sequence, we don't need to fill the load delay
7752 slots for most of the loads, also see if we can fill the final
7753 delay slot if not otherwise filled by the reload sequence. */
7756 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7759 if (frame_pointer_needed)
7762 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7763 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7765 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7766 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7769 /* Is the entire register save area offsettable from %sp? */
7770 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7776 /* Restore %sp in two steps, but make sure there is always a
7777 64 byte register save area, and %sp is properly aligned. */
7778 /* Amount to increment %sp by, the first time. */
7779 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7780 /* Offset to register save area from %sp. */
7781 reg_offset = size1 - reg_offset;
7783 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7784 ", %s\n\tadd\t%s, %s, %s\n",
7785 size1, t1_str, sp_str, t1_str, sp_str);
7788 /* We must restore the frame pointer and return address reg first
7789 because they are treated specially by the prologue output code. */
7790 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7792 fprintf (file, "\tld\t[%s+%d], %s\n",
7793 sp_str, (int) reg_offset, fp_str);
7796 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7798 fprintf (file, "\tld\t[%s+%d], %s\n",
7799 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7803 /* Restore any remaining saved registers. */
7804 sparc_flat_save_restore (file, sp_str, reg_offset,
7805 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7806 current_frame_info.fmask,
7809 /* If we had to increment %sp in two steps, record it so the second
7810 restoration in the epilogue finishes up. */
7815 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7819 if (current_function_returns_struct)
7820 fprintf (file, "\tjmp\t%%o7+12\n");
7822 fprintf (file, "\tretl\n");
7824 /* If the only register saved is the return address, we need a
7825 nop, unless we have an instruction to put into it. Otherwise
7826 we don't since reloading multiple registers doesn't reference
7827 the register being loaded. */
7833 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7836 else if (size > 4095)
7837 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7840 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7843 fprintf (file, "\tnop\n");
7846 /* Reset state info for each function. */
7847 current_frame_info = zero_frame_info;
7849 sparc_output_deferred_case_vectors ();
7852 /* Define the number of delay slots needed for the function epilogue.
7854 On the sparc, we need a slot if either no stack has been allocated,
7855 or the only register saved is the return register. */
7858 sparc_flat_epilogue_delay_slots (void)
7860 if (!current_frame_info.initialized)
7861 (void) sparc_flat_compute_frame_size (get_frame_size ());
7863 if (current_frame_info.total_size == 0)
7869 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7870 Any single length instruction which doesn't reference the stack or frame
7874 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
7876 rtx pat = PATTERN (trial);
7878 if (get_attr_length (trial) != 1)
7881 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7882 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7888 /* Adjust the cost of a scheduling dependency. Return the new cost of
7889 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7892 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7894 enum attr_type insn_type;
7896 if (! recog_memoized (insn))
7899 insn_type = get_attr_type (insn);
7901 if (REG_NOTE_KIND (link) == 0)
7903 /* Data dependency; DEP_INSN writes a register that INSN reads some
7906 /* if a load, then the dependence must be on the memory address;
7907 add an extra "cycle". Note that the cost could be two cycles
7908 if the reg was written late in an instruction group; we ca not tell
7910 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7913 /* Get the delay only if the address of the store is the dependence. */
7914 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7916 rtx pat = PATTERN(insn);
7917 rtx dep_pat = PATTERN (dep_insn);
7919 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7920 return cost; /* This should not happen! */
7922 /* The dependency between the two instructions was on the data that
7923 is being stored. Assume that this implies that the address of the
7924 store is not dependent. */
7925 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7928 return cost + 3; /* An approximation. */
7931 /* A shift instruction cannot receive its data from an instruction
7932 in the same cycle; add a one cycle penalty. */
7933 if (insn_type == TYPE_SHIFT)
7934 return cost + 3; /* Split before cascade into shift. */
7938 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7939 INSN writes some cycles later. */
7941 /* These are only significant for the fpu unit; writing a fp reg before
7942 the fpu has finished with it stalls the processor. */
7944 /* Reusing an integer register causes no problems. */
7945 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7953 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7955 enum attr_type insn_type, dep_type;
7956 rtx pat = PATTERN(insn);
7957 rtx dep_pat = PATTERN (dep_insn);
7959 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7962 insn_type = get_attr_type (insn);
7963 dep_type = get_attr_type (dep_insn);
7965 switch (REG_NOTE_KIND (link))
7968 /* Data dependency; DEP_INSN writes a register that INSN reads some
7975 /* Get the delay iff the address of the store is the dependence. */
7976 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7979 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7986 /* If a load, then the dependence must be on the memory address. If
7987 the addresses aren't equal, then it might be a false dependency */
7988 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7990 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7991 || GET_CODE (SET_DEST (dep_pat)) != MEM
7992 || GET_CODE (SET_SRC (pat)) != MEM
7993 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7994 XEXP (SET_SRC (pat), 0)))
8002 /* Compare to branch latency is 0. There is no benefit from
8003 separating compare and branch. */
8004 if (dep_type == TYPE_COMPARE)
8006 /* Floating point compare to branch latency is less than
8007 compare to conditional move. */
8008 if (dep_type == TYPE_FPCMP)
8017 /* Anti-dependencies only penalize the fpu unit. */
8018 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8030 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8034 case PROCESSOR_SUPERSPARC:
8035 cost = supersparc_adjust_cost (insn, link, dep, cost);
8037 case PROCESSOR_HYPERSPARC:
8038 case PROCESSOR_SPARCLITE86X:
8039 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8048 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8049 int sched_verbose ATTRIBUTE_UNUSED,
8050 int max_ready ATTRIBUTE_UNUSED)
8055 sparc_use_dfa_pipeline_interface (void)
8057 if ((1 << sparc_cpu) &
8058 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8059 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8060 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8061 (1 << PROCESSOR_ULTRASPARC3)))
8067 sparc_use_sched_lookahead (void)
8069 if (sparc_cpu == PROCESSOR_ULTRASPARC
8070 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8072 if ((1 << sparc_cpu) &
8073 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8074 (1 << PROCESSOR_SPARCLITE86X)))
8080 sparc_issue_rate (void)
8087 /* Assume V9 processors are capable of at least dual-issue. */
8089 case PROCESSOR_SUPERSPARC:
8091 case PROCESSOR_HYPERSPARC:
8092 case PROCESSOR_SPARCLITE86X:
8094 case PROCESSOR_ULTRASPARC:
8095 case PROCESSOR_ULTRASPARC3:
8101 set_extends (rtx insn)
8103 register rtx pat = PATTERN (insn);
8105 switch (GET_CODE (SET_SRC (pat)))
8107 /* Load and some shift instructions zero extend. */
8110 /* sethi clears the high bits */
8112 /* LO_SUM is used with sethi. sethi cleared the high
8113 bits and the values used with lo_sum are positive */
8115 /* Store flag stores 0 or 1 */
8125 rtx op0 = XEXP (SET_SRC (pat), 0);
8126 rtx op1 = XEXP (SET_SRC (pat), 1);
8127 if (GET_CODE (op1) == CONST_INT)
8128 return INTVAL (op1) >= 0;
8129 if (GET_CODE (op0) != REG)
8131 if (sparc_check_64 (op0, insn) == 1)
8133 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8138 rtx op0 = XEXP (SET_SRC (pat), 0);
8139 rtx op1 = XEXP (SET_SRC (pat), 1);
8140 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8142 if (GET_CODE (op1) == CONST_INT)
8143 return INTVAL (op1) >= 0;
8144 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8147 return GET_MODE (SET_SRC (pat)) == SImode;
8148 /* Positive integers leave the high bits zero. */
8150 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8152 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8155 return - (GET_MODE (SET_SRC (pat)) == SImode);
8157 return sparc_check_64 (SET_SRC (pat), insn);
8163 /* We _ought_ to have only one kind per function, but... */
8164 static GTY(()) rtx sparc_addr_diff_list;
8165 static GTY(()) rtx sparc_addr_list;
8168 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8170 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8172 sparc_addr_diff_list
8173 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8175 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8179 sparc_output_addr_vec (rtx vec)
8181 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8182 int idx, vlen = XVECLEN (body, 0);
8184 #ifdef ASM_OUTPUT_ADDR_VEC_START
8185 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8188 #ifdef ASM_OUTPUT_CASE_LABEL
8189 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8192 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8195 for (idx = 0; idx < vlen; idx++)
8197 ASM_OUTPUT_ADDR_VEC_ELT
8198 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8201 #ifdef ASM_OUTPUT_ADDR_VEC_END
8202 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8207 sparc_output_addr_diff_vec (rtx vec)
8209 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8210 rtx base = XEXP (XEXP (body, 0), 0);
8211 int idx, vlen = XVECLEN (body, 1);
8213 #ifdef ASM_OUTPUT_ADDR_VEC_START
8214 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8217 #ifdef ASM_OUTPUT_CASE_LABEL
8218 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8221 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8224 for (idx = 0; idx < vlen; idx++)
8226 ASM_OUTPUT_ADDR_DIFF_ELT
8229 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8230 CODE_LABEL_NUMBER (base));
8233 #ifdef ASM_OUTPUT_ADDR_VEC_END
8234 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8239 sparc_output_deferred_case_vectors (void)
8244 if (sparc_addr_list == NULL_RTX
8245 && sparc_addr_diff_list == NULL_RTX)
8248 /* Align to cache line in the function's code section. */
8249 function_section (current_function_decl);
8251 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8253 ASM_OUTPUT_ALIGN (asm_out_file, align);
8255 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8256 sparc_output_addr_vec (XEXP (t, 0));
8257 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8258 sparc_output_addr_diff_vec (XEXP (t, 0));
8260 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8263 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8264 unknown. Return 1 if the high bits are zero, -1 if the register is
8267 sparc_check_64 (rtx x, rtx insn)
8269 /* If a register is set only once it is safe to ignore insns this
8270 code does not know how to handle. The loop will either recognize
8271 the single set and return the correct value or fail to recognize
8276 if (GET_CODE (x) != REG)
8279 if (GET_MODE (x) == DImode)
8280 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8282 if (flag_expensive_optimizations
8283 && REG_N_SETS (REGNO (y)) == 1)
8289 insn = get_last_insn_anywhere ();
8294 while ((insn = PREV_INSN (insn)))
8296 switch (GET_CODE (insn))
8309 rtx pat = PATTERN (insn);
8310 if (GET_CODE (pat) != SET)
8312 if (rtx_equal_p (x, SET_DEST (pat)))
8313 return set_extends (insn);
8314 if (y && rtx_equal_p (y, SET_DEST (pat)))
8315 return set_extends (insn);
8316 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8324 /* Returns assembly code to perform a DImode shift using
8325 a 64-bit global or out register on SPARC-V8+. */
8327 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8329 static char asm_code[60];
8331 /* The scratch register is only required when the destination
8332 register is not a 64-bit global or out register. */
8333 if (which_alternative != 2)
8334 operands[3] = operands[0];
8336 /* We can only shift by constants <= 63. */
8337 if (GET_CODE (operands[2]) == CONST_INT)
8338 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8340 if (GET_CODE (operands[1]) == CONST_INT)
8342 output_asm_insn ("mov\t%1, %3", operands);
8346 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8347 if (sparc_check_64 (operands[1], insn) <= 0)
8348 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8349 output_asm_insn ("or\t%L1, %3, %3", operands);
8352 strcpy(asm_code, opcode);
8354 if (which_alternative != 2)
8355 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8357 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8360 /* Output rtl to increment the profiler label LABELNO
8361 for profiling a function entry. */
8364 sparc_profile_hook (int labelno)
8369 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8370 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8371 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8373 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8376 #ifdef OBJECT_FORMAT_ELF
8378 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8380 if (flags & SECTION_MERGE)
8382 /* entsize cannot be expressed in this section attributes
8384 default_elf_asm_named_section (name, flags);
8388 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8390 if (!(flags & SECTION_DEBUG))
8391 fputs (",#alloc", asm_out_file);
8392 if (flags & SECTION_WRITE)
8393 fputs (",#write", asm_out_file);
8394 if (flags & SECTION_CODE)
8395 fputs (",#execinstr", asm_out_file);
8397 /* ??? Handle SECTION_BSS. */
8399 fputc ('\n', asm_out_file);
8401 #endif /* OBJECT_FORMAT_ELF */
8403 /* We do not allow sibling calls if -mflat, nor
8404 we do not allow indirect calls to be optimized into sibling calls.
8406 Also, on sparc 32-bit we cannot emit a sibling call when the
8407 current function returns a structure. This is because the "unimp
8408 after call" convention would cause the callee to return to the
8409 wrong place. The generic code already disallows cases where the
8410 function being called returns a structure.
8412 It may seem strange how this last case could occur. Usually there
8413 is code after the call which jumps to epilogue code which dumps the
8414 return value into the struct return area. That ought to invalidate
8415 the sibling call right? Well, in the c++ case we can end up passing
8416 the pointer to the struct return area to a constructor (which returns
8417 void) and then nothing else happens. Such a sibling call would look
8418 valid without the added check here. */
8420 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8424 && (TARGET_ARCH64 || ! current_function_returns_struct));
8427 /* libfunc renaming. */
8428 #include "config/gofast.h"
8431 sparc_init_libfuncs (void)
8435 /* Use the subroutines that Sun's library provides for integer
8436 multiply and divide. The `*' prevents an underscore from
8437 being prepended by the compiler. .umul is a little faster
8439 set_optab_libfunc (smul_optab, SImode, "*.umul");
8440 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8441 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8442 set_optab_libfunc (smod_optab, SImode, "*.rem");
8443 set_optab_libfunc (umod_optab, SImode, "*.urem");
8445 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8446 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8447 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8448 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8449 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8450 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8452 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8453 is because with soft-float, the SFmode and DFmode sqrt
8454 instructions will be absent, and the compiler will notice and
8455 try to use the TFmode sqrt instruction for calls to the
8456 builtin function sqrt, but this fails. */
8458 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8460 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8461 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8462 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8463 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8464 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8465 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8467 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8468 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8469 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8470 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8472 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8473 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8474 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8476 if (SUN_CONVERSION_LIBFUNCS)
8478 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8479 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8480 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8481 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8486 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8487 do not exist in the library. Make sure the compiler does not
8488 emit calls to them by accident. (It should always use the
8489 hardware instructions.) */
8490 set_optab_libfunc (smul_optab, SImode, 0);
8491 set_optab_libfunc (sdiv_optab, SImode, 0);
8492 set_optab_libfunc (udiv_optab, SImode, 0);
8493 set_optab_libfunc (smod_optab, SImode, 0);
8494 set_optab_libfunc (umod_optab, SImode, 0);
8496 if (SUN_INTEGER_MULTIPLY_64)
8498 set_optab_libfunc (smul_optab, DImode, "__mul64");
8499 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8500 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8501 set_optab_libfunc (smod_optab, DImode, "__rem64");
8502 set_optab_libfunc (umod_optab, DImode, "__urem64");
8505 if (SUN_CONVERSION_LIBFUNCS)
8507 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8508 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8509 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8510 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8514 gofast_maybe_init_libfuncs ();
8517 /* ??? Similar to the standard section selection, but force reloc-y-ness
8518 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8519 pretending PIC always on), but that's what the old code did. */
8522 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8524 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8527 /* Use text section for a constant unless we need more alignment than
8531 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8532 unsigned HOST_WIDE_INT align)
8534 if (align <= MAX_TEXT_ALIGN
8535 && ! (flag_pic && (symbolic_operand (x, mode)
8536 || SUNOS4_SHARED_LIBRARIES)))
8537 readonly_data_section ();
8543 sparc_extra_constraint_check (rtx op, int c, int strict)
8548 && (c == 'T' || c == 'U'))
8554 return fp_sethi_p (op);
8557 return fp_mov_p (op);
8560 return fp_high_losum_p (op);
8564 || (GET_CODE (op) == REG
8565 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8566 || reg_renumber[REGNO (op)] >= 0)))
8567 return register_ok_for_ldd (op);
8579 /* Our memory extra constraints have to emulate the
8580 behavior of 'm' and 'o' in order for reload to work
8582 if (GET_CODE (op) == MEM)
8585 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8587 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8592 reload_ok_mem = (reload_in_progress
8593 && GET_CODE (op) == REG
8594 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8595 && reg_renumber [REGNO (op)] < 0);
8598 return reload_ok_mem;
8601 /* ??? This duplicates information provided to the compiler by the
8602 ??? scheduler description. Some day, teach genautomata to output
8603 ??? the latencies and then CSE will just use that. */
8606 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8610 case PLUS: case MINUS: case ABS: case NEG:
8611 case FLOAT: case UNSIGNED_FLOAT:
8612 case FIX: case UNSIGNED_FIX:
8613 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8614 if (FLOAT_MODE_P (GET_MODE (x)))
8618 case PROCESSOR_ULTRASPARC:
8619 case PROCESSOR_ULTRASPARC3:
8620 *total = COSTS_N_INSNS (4);
8623 case PROCESSOR_SUPERSPARC:
8624 *total = COSTS_N_INSNS (3);
8627 case PROCESSOR_CYPRESS:
8628 *total = COSTS_N_INSNS (5);
8631 case PROCESSOR_HYPERSPARC:
8632 case PROCESSOR_SPARCLITE86X:
8634 *total = COSTS_N_INSNS (1);
8639 *total = COSTS_N_INSNS (1);
8645 case PROCESSOR_ULTRASPARC:
8646 if (GET_MODE (x) == SFmode)
8647 *total = COSTS_N_INSNS (13);
8649 *total = COSTS_N_INSNS (23);
8652 case PROCESSOR_ULTRASPARC3:
8653 if (GET_MODE (x) == SFmode)
8654 *total = COSTS_N_INSNS (20);
8656 *total = COSTS_N_INSNS (29);
8659 case PROCESSOR_SUPERSPARC:
8660 *total = COSTS_N_INSNS (12);
8663 case PROCESSOR_CYPRESS:
8664 *total = COSTS_N_INSNS (63);
8667 case PROCESSOR_HYPERSPARC:
8668 case PROCESSOR_SPARCLITE86X:
8669 *total = COSTS_N_INSNS (17);
8673 *total = COSTS_N_INSNS (30);
8678 if (FLOAT_MODE_P (GET_MODE (x)))
8682 case PROCESSOR_ULTRASPARC:
8683 case PROCESSOR_ULTRASPARC3:
8684 *total = COSTS_N_INSNS (1);
8687 case PROCESSOR_SUPERSPARC:
8688 *total = COSTS_N_INSNS (3);
8691 case PROCESSOR_CYPRESS:
8692 *total = COSTS_N_INSNS (5);
8695 case PROCESSOR_HYPERSPARC:
8696 case PROCESSOR_SPARCLITE86X:
8698 *total = COSTS_N_INSNS (1);
8703 /* ??? Maybe mark integer compares as zero cost on
8704 ??? all UltraSPARC processors because the result
8705 ??? can be bypassed to a branch in the same group. */
8707 *total = COSTS_N_INSNS (1);
8711 if (FLOAT_MODE_P (GET_MODE (x)))
8715 case PROCESSOR_ULTRASPARC:
8716 case PROCESSOR_ULTRASPARC3:
8717 *total = COSTS_N_INSNS (4);
8720 case PROCESSOR_SUPERSPARC:
8721 *total = COSTS_N_INSNS (3);
8724 case PROCESSOR_CYPRESS:
8725 *total = COSTS_N_INSNS (7);
8728 case PROCESSOR_HYPERSPARC:
8729 case PROCESSOR_SPARCLITE86X:
8730 *total = COSTS_N_INSNS (1);
8734 *total = COSTS_N_INSNS (5);
8739 /* The latency is actually variable for Ultra-I/II
8740 And if one of the inputs have a known constant
8741 value, we could calculate this precisely.
8743 However, for that to be useful we would need to
8744 add some machine description changes which would
8745 make sure small constants ended up in rs1 of the
8746 multiply instruction. This is because the multiply
8747 latency is determined by the number of clear (or
8748 set if the value is negative) bits starting from
8749 the most significant bit of the first input.
8751 The algorithm for computing num_cycles of a multiply
8755 highest_bit = highest_clear_bit(rs1);
8757 highest_bit = highest_set_bit(rs1);
8760 num_cycles = 4 + ((highest_bit - 3) / 2);
8762 If we did that we would have to also consider register
8763 allocation issues that would result from forcing such
8764 a value into a register.
8766 There are other similar tricks we could play if we
8767 knew, for example, that one input was an array index.
8769 Since we do not play any such tricks currently the
8770 safest thing to do is report the worst case latency. */
8771 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8773 *total = (GET_MODE (x) == DImode
8774 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8778 /* Multiply latency on Ultra-III, fortunately, is constant. */
8779 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8781 *total = COSTS_N_INSNS (6);
8785 if (sparc_cpu == PROCESSOR_HYPERSPARC
8786 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8788 *total = COSTS_N_INSNS (17);
8792 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8799 if (FLOAT_MODE_P (GET_MODE (x)))
8803 case PROCESSOR_ULTRASPARC:
8804 if (GET_MODE (x) == SFmode)
8805 *total = COSTS_N_INSNS (13);
8807 *total = COSTS_N_INSNS (23);
8810 case PROCESSOR_ULTRASPARC3:
8811 if (GET_MODE (x) == SFmode)
8812 *total = COSTS_N_INSNS (17);
8814 *total = COSTS_N_INSNS (20);
8817 case PROCESSOR_SUPERSPARC:
8818 if (GET_MODE (x) == SFmode)
8819 *total = COSTS_N_INSNS (6);
8821 *total = COSTS_N_INSNS (9);
8824 case PROCESSOR_HYPERSPARC:
8825 case PROCESSOR_SPARCLITE86X:
8826 if (GET_MODE (x) == SFmode)
8827 *total = COSTS_N_INSNS (8);
8829 *total = COSTS_N_INSNS (12);
8833 *total = COSTS_N_INSNS (7);
8838 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8839 *total = (GET_MODE (x) == DImode
8840 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8841 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8842 *total = (GET_MODE (x) == DImode
8843 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8845 *total = COSTS_N_INSNS (25);
8849 /* Conditional moves. */
8852 case PROCESSOR_ULTRASPARC:
8853 *total = COSTS_N_INSNS (2);
8856 case PROCESSOR_ULTRASPARC3:
8857 if (FLOAT_MODE_P (GET_MODE (x)))
8858 *total = COSTS_N_INSNS (3);
8860 *total = COSTS_N_INSNS (2);
8864 *total = COSTS_N_INSNS (1);
8869 /* If outer-code is SIGN/ZERO extension we have to subtract
8870 out COSTS_N_INSNS (1) from whatever we return in determining
8874 case PROCESSOR_ULTRASPARC:
8875 if (outer_code == ZERO_EXTEND)
8876 *total = COSTS_N_INSNS (1);
8878 *total = COSTS_N_INSNS (2);
8881 case PROCESSOR_ULTRASPARC3:
8882 if (outer_code == ZERO_EXTEND)
8884 if (GET_MODE (x) == QImode
8885 || GET_MODE (x) == HImode
8886 || outer_code == SIGN_EXTEND)
8887 *total = COSTS_N_INSNS (2);
8889 *total = COSTS_N_INSNS (1);
8893 /* This handles sign extension (3 cycles)
8894 and everything else (2 cycles). */
8895 *total = COSTS_N_INSNS (2);
8899 case PROCESSOR_SUPERSPARC:
8900 if (FLOAT_MODE_P (GET_MODE (x))
8901 || outer_code == ZERO_EXTEND
8902 || outer_code == SIGN_EXTEND)
8903 *total = COSTS_N_INSNS (0);
8905 *total = COSTS_N_INSNS (1);
8908 case PROCESSOR_TSC701:
8909 if (outer_code == ZERO_EXTEND
8910 || outer_code == SIGN_EXTEND)
8911 *total = COSTS_N_INSNS (2);
8913 *total = COSTS_N_INSNS (3);
8916 case PROCESSOR_CYPRESS:
8917 if (outer_code == ZERO_EXTEND
8918 || outer_code == SIGN_EXTEND)
8919 *total = COSTS_N_INSNS (1);
8921 *total = COSTS_N_INSNS (2);
8924 case PROCESSOR_HYPERSPARC:
8925 case PROCESSOR_SPARCLITE86X:
8927 if (outer_code == ZERO_EXTEND
8928 || outer_code == SIGN_EXTEND)
8929 *total = COSTS_N_INSNS (0);
8931 *total = COSTS_N_INSNS (1);
8936 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8954 if (GET_MODE (x) == DImode
8955 && ((XINT (x, 3) == 0
8956 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8957 || (XINT (x, 3) == -1
8959 && XINT (x, 2) >= -0x1000)))
8970 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8971 Used for C++ multiple inheritance. */
8974 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8975 HOST_WIDE_INT delta,
8976 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8979 rtx this, insn, funexp, delta_rtx, tmp;
8981 reload_completed = 1;
8982 epilogue_completed = 1;
8984 current_function_uses_only_leaf_regs = 1;
8986 emit_note (NOTE_INSN_PROLOGUE_END);
8988 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8989 returns a structure, the structure return pointer is there instead. */
8990 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8991 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8993 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8995 /* Add DELTA. When possible use a plain add, otherwise load it into
8996 a register first. */
8997 delta_rtx = GEN_INT (delta);
8998 if (!SPARC_SIMM13_P (delta))
9000 rtx scratch = gen_rtx_REG (Pmode, 1);
9002 sparc_emit_set_const64 (scratch, delta_rtx);
9004 sparc_emit_set_const32 (scratch, delta_rtx);
9005 delta_rtx = scratch;
9008 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
9009 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
9011 /* Generate a tail call to the target function. */
9012 if (! TREE_USED (function))
9014 assemble_external (function);
9015 TREE_USED (function) = 1;
9017 funexp = XEXP (DECL_RTL (function), 0);
9018 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9019 insn = emit_call_insn (gen_sibcall (funexp));
9020 SIBLING_CALL_P (insn) = 1;
9023 /* Run just enough of rest_of_compilation to get the insns emitted.
9024 There's not really enough bulk here to make other passes such as
9025 instruction scheduling worth while. Note that use_thunk calls
9026 assemble_start_function and assemble_end_function. */
9027 insn = get_insns ();
9028 insn_locators_initialize ();
9029 shorten_branches (insn);
9030 final_start_function (insn, file, 1);
9031 final (insn, file, 1, 0);
9032 final_end_function ();
9034 reload_completed = 0;
9035 epilogue_completed = 0;
9039 /* How to allocate a 'struct machine_function'. */
9041 static struct machine_function *
9042 sparc_init_machine_status (void)
9044 return ggc_alloc_cleared (sizeof (struct machine_function));
9047 /* Locate some local-dynamic symbol still in use by this function
9048 so that we can print its name in local-dynamic base patterns. */
9051 get_some_local_dynamic_name (void)
9055 if (cfun->machine->some_ld_name)
9056 return cfun->machine->some_ld_name;
9058 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9060 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9061 return cfun->machine->some_ld_name;
9067 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9072 && GET_CODE (x) == SYMBOL_REF
9073 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9075 cfun->machine->some_ld_name = XSTR (x, 0);
9082 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9083 We need to emit DTP-relative relocations. */
9086 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9091 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9094 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9099 output_addr_const (file, x);
9103 #include "gt-sparc.h"