1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs = {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs = {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs = {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs = {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs = {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs = {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs = {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs = {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs = {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs = {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs *sparc_costs = &cypress_costs;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode = 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
402 const_tree, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
405 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
407 static void sparc_emit_set_const32 (rtx, rtx);
408 static void sparc_emit_set_const64 (rtx, rtx);
409 static void sparc_output_addr_vec (rtx);
410 static void sparc_output_addr_diff_vec (rtx);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
414 static rtx sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx *, int);
416 static bool sparc_assemble_integer (rtx, unsigned int, int);
417 static int set_extends (rtx);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree) ATTRIBUTE_UNUSED;
424 static int sparc_adjust_cost (rtx, rtx, rtx, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
430 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
431 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
432 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
433 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
435 static bool sparc_function_ok_for_sibcall (tree, tree);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
440 static tree sparc_fold_builtin (tree, int, tree *, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
443 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
444 HOST_WIDE_INT, tree);
445 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
446 HOST_WIDE_INT, const_tree);
447 static void sparc_reorg (void);
448 static struct machine_function * sparc_init_machine_status (void);
449 static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
450 static rtx sparc_tls_get_addr (void);
451 static rtx sparc_tls_got (void);
452 static const char *get_some_local_dynamic_name (void);
453 static int get_some_local_dynamic_name_1 (rtx *, void *);
454 static int sparc_register_move_cost (enum machine_mode,
455 reg_class_t, reg_class_t);
456 static bool sparc_rtx_costs (rtx, int, int, int, int *, bool);
457 static rtx sparc_function_value (const_tree, const_tree, bool);
458 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
459 static bool sparc_function_value_regno_p (const unsigned int);
460 static rtx sparc_struct_value_rtx (tree, int);
461 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
462 int *, const_tree, int);
463 static bool sparc_return_in_memory (const_tree, const_tree);
464 static bool sparc_strict_argument_naming (cumulative_args_t);
465 static void sparc_va_start (tree, rtx);
466 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
467 static bool sparc_vector_mode_supported_p (enum machine_mode);
468 static bool sparc_tls_referenced_p (rtx);
469 static rtx sparc_legitimize_tls_address (rtx);
470 static rtx sparc_legitimize_pic_address (rtx, rtx);
471 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
472 static rtx sparc_delegitimize_address (rtx);
473 static bool sparc_mode_dependent_address_p (const_rtx);
474 static bool sparc_pass_by_reference (cumulative_args_t,
475 enum machine_mode, const_tree, bool);
476 static void sparc_function_arg_advance (cumulative_args_t,
477 enum machine_mode, const_tree, bool);
478 static rtx sparc_function_arg_1 (cumulative_args_t,
479 enum machine_mode, const_tree, bool, bool);
480 static rtx sparc_function_arg (cumulative_args_t,
481 enum machine_mode, const_tree, bool);
482 static rtx sparc_function_incoming_arg (cumulative_args_t,
483 enum machine_mode, const_tree, bool);
484 static unsigned int sparc_function_arg_boundary (enum machine_mode,
486 static int sparc_arg_partial_bytes (cumulative_args_t,
487 enum machine_mode, tree, bool);
488 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
489 static void sparc_file_end (void);
490 static bool sparc_frame_pointer_required (void);
491 static bool sparc_can_eliminate (const int, const int);
492 static rtx sparc_builtin_setjmp_frame_value (void);
493 static void sparc_conditional_register_usage (void);
494 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
495 static const char *sparc_mangle_type (const_tree);
497 static void sparc_trampoline_init (rtx, tree, rtx);
498 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
499 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
500 static bool sparc_print_operand_punct_valid_p (unsigned char);
501 static void sparc_print_operand (FILE *, rtx, int);
502 static void sparc_print_operand_address (FILE *, rtx);
503 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
504 enum machine_mode, secondary_reload_info *);
506 #ifdef SUBTARGET_ATTRIBUTE_TABLE
507 /* Table of valid machine attributes. */
508 static const struct attribute_spec sparc_attribute_table[] =
510 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
512 SUBTARGET_ATTRIBUTE_TABLE,
513 { NULL, 0, 0, false, false, false, NULL, false }
517 /* Option handling. */
520 enum cmodel sparc_cmodel;
522 char sparc_hard_reg_printed[8];
524 /* Initialize the GCC target structure. */
526 /* The default is to use .half rather than .short for aligned HI objects. */
527 #undef TARGET_ASM_ALIGNED_HI_OP
528 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
530 #undef TARGET_ASM_UNALIGNED_HI_OP
531 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
532 #undef TARGET_ASM_UNALIGNED_SI_OP
533 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
534 #undef TARGET_ASM_UNALIGNED_DI_OP
535 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
537 /* The target hook has to handle DI-mode values. */
538 #undef TARGET_ASM_INTEGER
539 #define TARGET_ASM_INTEGER sparc_assemble_integer
541 #undef TARGET_ASM_FUNCTION_PROLOGUE
542 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
543 #undef TARGET_ASM_FUNCTION_EPILOGUE
544 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
546 #undef TARGET_SCHED_ADJUST_COST
547 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
548 #undef TARGET_SCHED_ISSUE_RATE
549 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
550 #undef TARGET_SCHED_INIT
551 #define TARGET_SCHED_INIT sparc_sched_init
552 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
553 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
555 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
556 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
558 #undef TARGET_INIT_LIBFUNCS
559 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
560 #undef TARGET_INIT_BUILTINS
561 #define TARGET_INIT_BUILTINS sparc_init_builtins
563 #undef TARGET_LEGITIMIZE_ADDRESS
564 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
565 #undef TARGET_DELEGITIMIZE_ADDRESS
566 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
567 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
568 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
570 #undef TARGET_EXPAND_BUILTIN
571 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
572 #undef TARGET_FOLD_BUILTIN
573 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
576 #undef TARGET_HAVE_TLS
577 #define TARGET_HAVE_TLS true
580 #undef TARGET_CANNOT_FORCE_CONST_MEM
581 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
583 #undef TARGET_ASM_OUTPUT_MI_THUNK
584 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
585 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
586 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
588 #undef TARGET_MACHINE_DEPENDENT_REORG
589 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
591 #undef TARGET_RTX_COSTS
592 #define TARGET_RTX_COSTS sparc_rtx_costs
593 #undef TARGET_ADDRESS_COST
594 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
595 #undef TARGET_REGISTER_MOVE_COST
596 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
598 #undef TARGET_PROMOTE_FUNCTION_MODE
599 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
601 #undef TARGET_FUNCTION_VALUE
602 #define TARGET_FUNCTION_VALUE sparc_function_value
603 #undef TARGET_LIBCALL_VALUE
604 #define TARGET_LIBCALL_VALUE sparc_libcall_value
605 #undef TARGET_FUNCTION_VALUE_REGNO_P
606 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
608 #undef TARGET_STRUCT_VALUE_RTX
609 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
610 #undef TARGET_RETURN_IN_MEMORY
611 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
612 #undef TARGET_MUST_PASS_IN_STACK
613 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
614 #undef TARGET_PASS_BY_REFERENCE
615 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
616 #undef TARGET_ARG_PARTIAL_BYTES
617 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
618 #undef TARGET_FUNCTION_ARG_ADVANCE
619 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
620 #undef TARGET_FUNCTION_ARG
621 #define TARGET_FUNCTION_ARG sparc_function_arg
622 #undef TARGET_FUNCTION_INCOMING_ARG
623 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
624 #undef TARGET_FUNCTION_ARG_BOUNDARY
625 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
627 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
628 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
629 #undef TARGET_STRICT_ARGUMENT_NAMING
630 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
632 #undef TARGET_EXPAND_BUILTIN_VA_START
633 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
634 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
635 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
637 #undef TARGET_VECTOR_MODE_SUPPORTED_P
638 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
640 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
641 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
643 #ifdef SUBTARGET_INSERT_ATTRIBUTES
644 #undef TARGET_INSERT_ATTRIBUTES
645 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
648 #ifdef SUBTARGET_ATTRIBUTE_TABLE
649 #undef TARGET_ATTRIBUTE_TABLE
650 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
653 #undef TARGET_RELAXED_ORDERING
654 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
656 #undef TARGET_OPTION_OVERRIDE
657 #define TARGET_OPTION_OVERRIDE sparc_option_override
659 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
660 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
661 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
664 #undef TARGET_ASM_FILE_END
665 #define TARGET_ASM_FILE_END sparc_file_end
667 #undef TARGET_FRAME_POINTER_REQUIRED
668 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
670 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
671 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
673 #undef TARGET_CAN_ELIMINATE
674 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
676 #undef TARGET_PREFERRED_RELOAD_CLASS
677 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
679 #undef TARGET_SECONDARY_RELOAD
680 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
682 #undef TARGET_CONDITIONAL_REGISTER_USAGE
683 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
685 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
686 #undef TARGET_MANGLE_TYPE
687 #define TARGET_MANGLE_TYPE sparc_mangle_type
690 #undef TARGET_LEGITIMATE_ADDRESS_P
691 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
693 #undef TARGET_LEGITIMATE_CONSTANT_P
694 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
696 #undef TARGET_TRAMPOLINE_INIT
697 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
699 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
700 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
701 #undef TARGET_PRINT_OPERAND
702 #define TARGET_PRINT_OPERAND sparc_print_operand
703 #undef TARGET_PRINT_OPERAND_ADDRESS
704 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
706 struct gcc_target targetm = TARGET_INITIALIZER;
709 dump_target_flag_bits (const int flags)
711 if (flags & MASK_64BIT)
712 fprintf (stderr, "64BIT ");
713 if (flags & MASK_APP_REGS)
714 fprintf (stderr, "APP_REGS ");
715 if (flags & MASK_FASTER_STRUCTS)
716 fprintf (stderr, "FASTER_STRUCTS ");
717 if (flags & MASK_FLAT)
718 fprintf (stderr, "FLAT ");
719 if (flags & MASK_FMAF)
720 fprintf (stderr, "FMAF ");
721 if (flags & MASK_FPU)
722 fprintf (stderr, "FPU ");
723 if (flags & MASK_HARD_QUAD)
724 fprintf (stderr, "HARD_QUAD ");
725 if (flags & MASK_POPC)
726 fprintf (stderr, "POPC ");
727 if (flags & MASK_PTR64)
728 fprintf (stderr, "PTR64 ");
729 if (flags & MASK_STACK_BIAS)
730 fprintf (stderr, "STACK_BIAS ");
731 if (flags & MASK_UNALIGNED_DOUBLES)
732 fprintf (stderr, "UNALIGNED_DOUBLES ");
733 if (flags & MASK_V8PLUS)
734 fprintf (stderr, "V8PLUS ");
735 if (flags & MASK_VIS)
736 fprintf (stderr, "VIS ");
737 if (flags & MASK_VIS2)
738 fprintf (stderr, "VIS2 ");
739 if (flags & MASK_VIS3)
740 fprintf (stderr, "VIS3 ");
741 if (flags & MASK_DEPRECATED_V8_INSNS)
742 fprintf (stderr, "DEPRECATED_V8_INSNS ");
743 if (flags & MASK_LITTLE_ENDIAN)
744 fprintf (stderr, "LITTLE_ENDIAN ");
745 if (flags & MASK_SPARCLET)
746 fprintf (stderr, "SPARCLET ");
747 if (flags & MASK_SPARCLITE)
748 fprintf (stderr, "SPARCLITE ");
750 fprintf (stderr, "V8 ");
752 fprintf (stderr, "V9 ");
756 dump_target_flags (const char *prefix, const int flags)
758 fprintf (stderr, "%s: (%08x) [ ", prefix, flags);
759 dump_target_flag_bits (flags);
760 fprintf(stderr, "]\n");
763 /* Validate and override various options, and do some machine dependent
767 sparc_option_override (void)
769 static struct code_model {
770 const char *const name;
771 const enum cmodel value;
772 } const cmodels[] = {
774 { "medlow", CM_MEDLOW },
775 { "medmid", CM_MEDMID },
776 { "medany", CM_MEDANY },
777 { "embmedany", CM_EMBMEDANY },
778 { NULL, (enum cmodel) 0 }
780 const struct code_model *cmodel;
781 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
782 static struct cpu_default {
784 const enum processor_type processor;
785 } const cpu_default[] = {
786 /* There must be one entry here for each TARGET_CPU value. */
787 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
788 { TARGET_CPU_v8, PROCESSOR_V8 },
789 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
790 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
791 { TARGET_CPU_leon, PROCESSOR_LEON },
792 { TARGET_CPU_sparclite, PROCESSOR_F930 },
793 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
794 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
795 { TARGET_CPU_v9, PROCESSOR_V9 },
796 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
797 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
798 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
799 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
800 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
801 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
804 const struct cpu_default *def;
805 /* Table of values for -m{cpu,tune}=. This must match the order of
806 the PROCESSOR_* enumeration. */
807 static struct cpu_table {
808 const char *const name;
811 } const cpu_table[] = {
812 { "v7", MASK_ISA, 0 },
813 { "cypress", MASK_ISA, 0 },
814 { "v8", MASK_ISA, MASK_V8 },
815 /* TI TMS390Z55 supersparc */
816 { "supersparc", MASK_ISA, MASK_V8 },
817 { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
819 { "leon", MASK_ISA, MASK_V8|MASK_FPU },
820 { "sparclite", MASK_ISA, MASK_SPARCLITE },
821 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
822 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
823 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
824 { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
825 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
826 { "sparclet", MASK_ISA, MASK_SPARCLET },
828 { "tsc701", MASK_ISA, MASK_SPARCLET },
829 { "v9", MASK_ISA, MASK_V9 },
830 /* UltraSPARC I, II, IIi */
831 { "ultrasparc", MASK_ISA,
832 /* Although insns using %y are deprecated, it is a clear win. */
833 MASK_V9|MASK_DEPRECATED_V8_INSNS },
835 /* ??? Check if %y issue still holds true. */
836 { "ultrasparc3", MASK_ISA,
837 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 },
839 { "niagara", MASK_ISA,
840 MASK_V9|MASK_DEPRECATED_V8_INSNS },
842 { "niagara2", MASK_ISA,
843 MASK_V9|MASK_POPC|MASK_VIS2 },
845 { "niagara3", MASK_ISA,
846 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
848 { "niagara4", MASK_ISA,
849 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
851 const struct cpu_table *cpu;
855 if (sparc_debug_string != NULL)
860 p = ASTRDUP (sparc_debug_string);
861 while ((q = strtok (p, ",")) != NULL)
875 if (! strcmp (q, "all"))
876 mask = MASK_DEBUG_ALL;
877 else if (! strcmp (q, "options"))
878 mask = MASK_DEBUG_OPTIONS;
880 error ("unknown -mdebug-%s switch", q);
883 sparc_debug &= ~mask;
889 if (TARGET_DEBUG_OPTIONS)
891 dump_target_flags("Initial target_flags", target_flags);
892 dump_target_flags("target_flags_explicit", target_flags_explicit);
895 #ifdef SUBTARGET_OVERRIDE_OPTIONS
896 SUBTARGET_OVERRIDE_OPTIONS;
899 #ifndef SPARC_BI_ARCH
900 /* Check for unsupported architecture size. */
901 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
902 error ("%s is not supported by this configuration",
903 DEFAULT_ARCH32_P ? "-m64" : "-m32");
906 /* We force all 64bit archs to use 128 bit long double */
907 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
909 error ("-mlong-double-64 not allowed with -m64");
910 target_flags |= MASK_LONG_DOUBLE_128;
913 /* Code model selection. */
914 sparc_cmodel = SPARC_DEFAULT_CMODEL;
918 sparc_cmodel = CM_32;
921 if (sparc_cmodel_string != NULL)
925 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
926 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
928 if (cmodel->name == NULL)
929 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
931 sparc_cmodel = cmodel->value;
934 error ("-mcmodel= is not supported on 32 bit systems");
937 /* Check that -fcall-saved-REG wasn't specified for out registers. */
938 for (i = 8; i < 16; i++)
939 if (!call_used_regs [i])
941 error ("-fcall-saved-REG is not supported for out registers");
942 call_used_regs [i] = 1;
945 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
947 /* Set the default CPU. */
948 if (!global_options_set.x_sparc_cpu_and_features)
950 for (def = &cpu_default[0]; def->cpu != -1; ++def)
951 if (def->cpu == TARGET_CPU_DEFAULT)
953 gcc_assert (def->cpu != -1);
954 sparc_cpu_and_features = def->processor;
957 if ((target_flags & MASK_V8PLUS)
958 && sparc_cpu_and_features < PROCESSOR_V9)
959 sparc_cpu_and_features = PROCESSOR_V9;
961 if (!global_options_set.x_sparc_cpu)
962 sparc_cpu = sparc_cpu_and_features;
964 cpu = &cpu_table[(int) sparc_cpu_and_features];
966 if (TARGET_DEBUG_OPTIONS)
968 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
969 fprintf (stderr, "sparc_cpu: %s\n",
970 cpu_table[(int) sparc_cpu].name);
971 dump_target_flags ("cpu->disable", cpu->disable);
972 dump_target_flags ("cpu->enable", cpu->enable);
975 target_flags &= ~cpu->disable;
976 target_flags |= (cpu->enable
977 #ifndef HAVE_AS_FMAF_HPC_VIS3
978 & ~(MASK_FMAF | MASK_VIS3)
982 /* If -mfpu or -mno-fpu was explicitly used, don't override with
983 the processor default. */
984 if (target_flags_explicit & MASK_FPU)
985 target_flags = (target_flags & ~MASK_FPU) | fpu;
987 /* -mvis2 implies -mvis */
989 target_flags |= MASK_VIS;
991 /* -mvis3 implies -mvis2 and -mvis */
993 target_flags |= MASK_VIS2 | MASK_VIS;
995 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
997 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF);
999 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1001 -m64 also implies v9. */
1002 if (TARGET_VIS || TARGET_ARCH64)
1004 target_flags |= MASK_V9;
1005 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
1008 /* -mvis also implies -mv8plus on 32-bit */
1009 if (TARGET_VIS && ! TARGET_ARCH64)
1010 target_flags |= MASK_V8PLUS;
1012 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1013 if (TARGET_V9 && TARGET_ARCH32)
1014 target_flags |= MASK_DEPRECATED_V8_INSNS;
1016 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1017 if (! TARGET_V9 || TARGET_ARCH64)
1018 target_flags &= ~MASK_V8PLUS;
1020 /* Don't use stack biasing in 32 bit mode. */
1022 target_flags &= ~MASK_STACK_BIAS;
1024 /* Supply a default value for align_functions. */
1025 if (align_functions == 0
1026 && (sparc_cpu == PROCESSOR_ULTRASPARC
1027 || sparc_cpu == PROCESSOR_ULTRASPARC3
1028 || sparc_cpu == PROCESSOR_NIAGARA
1029 || sparc_cpu == PROCESSOR_NIAGARA2
1030 || sparc_cpu == PROCESSOR_NIAGARA3
1031 || sparc_cpu == PROCESSOR_NIAGARA4))
1032 align_functions = 32;
1034 /* Validate PCC_STRUCT_RETURN. */
1035 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
1036 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
1038 /* Only use .uaxword when compiling for a 64-bit target. */
1040 targetm.asm_out.unaligned_op.di = NULL;
1042 /* Do various machine dependent initializations. */
1043 sparc_init_modes ();
1045 /* Set up function hooks. */
1046 init_machine_status = sparc_init_machine_status;
1051 case PROCESSOR_CYPRESS:
1052 sparc_costs = &cypress_costs;
1055 case PROCESSOR_SPARCLITE:
1056 case PROCESSOR_SUPERSPARC:
1057 sparc_costs = &supersparc_costs;
1059 case PROCESSOR_F930:
1060 case PROCESSOR_F934:
1061 case PROCESSOR_HYPERSPARC:
1062 case PROCESSOR_SPARCLITE86X:
1063 sparc_costs = &hypersparc_costs;
1065 case PROCESSOR_LEON:
1066 sparc_costs = &leon_costs;
1068 case PROCESSOR_SPARCLET:
1069 case PROCESSOR_TSC701:
1070 sparc_costs = &sparclet_costs;
1073 case PROCESSOR_ULTRASPARC:
1074 sparc_costs = &ultrasparc_costs;
1076 case PROCESSOR_ULTRASPARC3:
1077 sparc_costs = &ultrasparc3_costs;
1079 case PROCESSOR_NIAGARA:
1080 sparc_costs = &niagara_costs;
1082 case PROCESSOR_NIAGARA2:
1083 sparc_costs = &niagara2_costs;
1085 case PROCESSOR_NIAGARA3:
1086 case PROCESSOR_NIAGARA4:
1087 sparc_costs = &niagara3_costs;
1089 case PROCESSOR_NATIVE:
1093 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1094 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1095 target_flags |= MASK_LONG_DOUBLE_128;
1098 if (TARGET_DEBUG_OPTIONS)
1099 dump_target_flags ("Final target_flags", target_flags);
1101 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
1102 ((sparc_cpu == PROCESSOR_ULTRASPARC
1103 || sparc_cpu == PROCESSOR_NIAGARA
1104 || sparc_cpu == PROCESSOR_NIAGARA2
1105 || sparc_cpu == PROCESSOR_NIAGARA3
1106 || sparc_cpu == PROCESSOR_NIAGARA4)
1108 : (sparc_cpu == PROCESSOR_ULTRASPARC3
1110 global_options.x_param_values,
1111 global_options_set.x_param_values);
1112 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
1113 ((sparc_cpu == PROCESSOR_ULTRASPARC
1114 || sparc_cpu == PROCESSOR_ULTRASPARC3
1115 || sparc_cpu == PROCESSOR_NIAGARA
1116 || sparc_cpu == PROCESSOR_NIAGARA2
1117 || sparc_cpu == PROCESSOR_NIAGARA3
1118 || sparc_cpu == PROCESSOR_NIAGARA4)
1120 global_options.x_param_values,
1121 global_options_set.x_param_values);
1123 /* Disable save slot sharing for call-clobbered registers by default.
1124 The IRA sharing algorithm works on single registers only and this
1125 pessimizes for double floating-point registers. */
1126 if (!global_options_set.x_flag_ira_share_save_slots)
1127 flag_ira_share_save_slots = 0;
1130 /* Miscellaneous utilities. */
1132 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1133 or branch on register contents instructions. */
1136 v9_regcmp_p (enum rtx_code code)
1138 return (code == EQ || code == NE || code == GE || code == LT
1139 || code == LE || code == GT);
1142 /* Nonzero if OP is a floating point constant which can
1143 be loaded into an integer register using a single
1144 sethi instruction. */
1149 if (GET_CODE (op) == CONST_DOUBLE)
1154 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1155 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1156 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
1162 /* Nonzero if OP is a floating point constant which can
1163 be loaded into an integer register using a single
1169 if (GET_CODE (op) == CONST_DOUBLE)
1174 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1175 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1176 return SPARC_SIMM13_P (i);
1182 /* Nonzero if OP is a floating point constant which can
1183 be loaded into an integer register using a high/losum
1184 instruction sequence. */
1187 fp_high_losum_p (rtx op)
1189 /* The constraints calling this should only be in
1190 SFmode move insns, so any constant which cannot
1191 be moved using a single insn will do. */
1192 if (GET_CODE (op) == CONST_DOUBLE)
1197 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1198 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1199 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1205 /* Return true if the address of LABEL can be loaded by means of the
1206 mov{si,di}_pic_label_ref patterns in PIC mode. */
1209 can_use_mov_pic_label_ref (rtx label)
1211 /* VxWorks does not impose a fixed gap between segments; the run-time
1212 gap can be different from the object-file gap. We therefore can't
1213 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1214 are absolutely sure that X is in the same segment as the GOT.
1215 Unfortunately, the flexibility of linker scripts means that we
1216 can't be sure of that in general, so assume that GOT-relative
1217 accesses are never valid on VxWorks. */
1218 if (TARGET_VXWORKS_RTP)
1221 /* Similarly, if the label is non-local, it might end up being placed
1222 in a different section than the current one; now mov_pic_label_ref
1223 requires the label and the code to be in the same section. */
1224 if (LABEL_REF_NONLOCAL_P (label))
1227 /* Finally, if we are reordering basic blocks and partition into hot
1228 and cold sections, this might happen for any label. */
1229 if (flag_reorder_blocks_and_partition)
1235 /* Expand a move instruction. Return true if all work is done. */
1238 sparc_expand_move (enum machine_mode mode, rtx *operands)
1240 /* Handle sets of MEM first. */
1241 if (GET_CODE (operands[0]) == MEM)
1243 /* 0 is a register (or a pair of registers) on SPARC. */
1244 if (register_or_zero_operand (operands[1], mode))
1247 if (!reload_in_progress)
1249 operands[0] = validize_mem (operands[0]);
1250 operands[1] = force_reg (mode, operands[1]);
1254 /* Fixup TLS cases. */
1256 && CONSTANT_P (operands[1])
1257 && sparc_tls_referenced_p (operands [1]))
1259 operands[1] = sparc_legitimize_tls_address (operands[1]);
1263 /* Fixup PIC cases. */
1264 if (flag_pic && CONSTANT_P (operands[1]))
1266 if (pic_address_needs_scratch (operands[1]))
1267 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1269 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1270 if (GET_CODE (operands[1]) == LABEL_REF
1271 && can_use_mov_pic_label_ref (operands[1]))
1275 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1281 gcc_assert (TARGET_ARCH64);
1282 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1287 if (symbolic_operand (operands[1], mode))
1290 = sparc_legitimize_pic_address (operands[1],
1292 ? operands[0] : NULL_RTX);
1297 /* If we are trying to toss an integer constant into FP registers,
1298 or loading a FP or vector constant, force it into memory. */
1299 if (CONSTANT_P (operands[1])
1300 && REG_P (operands[0])
1301 && (SPARC_FP_REG_P (REGNO (operands[0]))
1302 || SCALAR_FLOAT_MODE_P (mode)
1303 || VECTOR_MODE_P (mode)))
1305 /* emit_group_store will send such bogosity to us when it is
1306 not storing directly into memory. So fix this up to avoid
1307 crashes in output_constant_pool. */
1308 if (operands [1] == const0_rtx)
1309 operands[1] = CONST0_RTX (mode);
1311 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1312 always other regs. */
1313 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1314 && (const_zero_operand (operands[1], mode)
1315 || const_all_ones_operand (operands[1], mode)))
1318 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1319 /* We are able to build any SF constant in integer registers
1320 with at most 2 instructions. */
1322 /* And any DF constant in integer registers. */
1324 && ! can_create_pseudo_p ())))
1327 operands[1] = force_const_mem (mode, operands[1]);
1328 if (!reload_in_progress)
1329 operands[1] = validize_mem (operands[1]);
1333 /* Accept non-constants and valid constants unmodified. */
1334 if (!CONSTANT_P (operands[1])
1335 || GET_CODE (operands[1]) == HIGH
1336 || input_operand (operands[1], mode))
1342 /* All QImode constants require only one insn, so proceed. */
1347 sparc_emit_set_const32 (operands[0], operands[1]);
1351 /* input_operand should have filtered out 32-bit mode. */
1352 sparc_emit_set_const64 (operands[0], operands[1]);
1362 /* Load OP1, a 32-bit constant, into OP0, a register.
1363 We know it can't be done in one insn when we get
1364 here, the move expander guarantees this. */
1367 sparc_emit_set_const32 (rtx op0, rtx op1)
1369 enum machine_mode mode = GET_MODE (op0);
1372 if (can_create_pseudo_p ())
1373 temp = gen_reg_rtx (mode);
1375 if (GET_CODE (op1) == CONST_INT)
1377 gcc_assert (!small_int_operand (op1, mode)
1378 && !const_high_operand (op1, mode));
1380 /* Emit them as real moves instead of a HIGH/LO_SUM,
1381 this way CSE can see everything and reuse intermediate
1382 values if it wants. */
1383 emit_insn (gen_rtx_SET (VOIDmode, temp,
1384 GEN_INT (INTVAL (op1)
1385 & ~(HOST_WIDE_INT)0x3ff)));
1387 emit_insn (gen_rtx_SET (VOIDmode,
1389 gen_rtx_IOR (mode, temp,
1390 GEN_INT (INTVAL (op1) & 0x3ff))));
1394 /* A symbol, emit in the traditional way. */
1395 emit_insn (gen_rtx_SET (VOIDmode, temp,
1396 gen_rtx_HIGH (mode, op1)));
1397 emit_insn (gen_rtx_SET (VOIDmode,
1398 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1402 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1403 If TEMP is nonzero, we are forbidden to use any other scratch
1404 registers. Otherwise, we are allowed to generate them as needed.
1406 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1407 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1410 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1412 rtx temp1, temp2, temp3, temp4, temp5;
1415 if (temp && GET_MODE (temp) == TImode)
1418 temp = gen_rtx_REG (DImode, REGNO (temp));
1421 /* SPARC-V9 code-model support. */
1422 switch (sparc_cmodel)
1425 /* The range spanned by all instructions in the object is less
1426 than 2^31 bytes (2GB) and the distance from any instruction
1427 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1428 than 2^31 bytes (2GB).
1430 The executable must be in the low 4TB of the virtual address
1433 sethi %hi(symbol), %temp1
1434 or %temp1, %lo(symbol), %reg */
1436 temp1 = temp; /* op0 is allowed. */
1438 temp1 = gen_reg_rtx (DImode);
1440 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1441 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1445 /* The range spanned by all instructions in the object is less
1446 than 2^31 bytes (2GB) and the distance from any instruction
1447 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1448 than 2^31 bytes (2GB).
1450 The executable must be in the low 16TB of the virtual address
1453 sethi %h44(symbol), %temp1
1454 or %temp1, %m44(symbol), %temp2
1455 sllx %temp2, 12, %temp3
1456 or %temp3, %l44(symbol), %reg */
1461 temp3 = temp; /* op0 is allowed. */
1465 temp1 = gen_reg_rtx (DImode);
1466 temp2 = gen_reg_rtx (DImode);
1467 temp3 = gen_reg_rtx (DImode);
1470 emit_insn (gen_seth44 (temp1, op1));
1471 emit_insn (gen_setm44 (temp2, temp1, op1));
1472 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1473 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1474 emit_insn (gen_setl44 (op0, temp3, op1));
1478 /* The range spanned by all instructions in the object is less
1479 than 2^31 bytes (2GB) and the distance from any instruction
1480 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1481 than 2^31 bytes (2GB).
1483 The executable can be placed anywhere in the virtual address
1486 sethi %hh(symbol), %temp1
1487 sethi %lm(symbol), %temp2
1488 or %temp1, %hm(symbol), %temp3
1489 sllx %temp3, 32, %temp4
1490 or %temp4, %temp2, %temp5
1491 or %temp5, %lo(symbol), %reg */
1494 /* It is possible that one of the registers we got for operands[2]
1495 might coincide with that of operands[0] (which is why we made
1496 it TImode). Pick the other one to use as our scratch. */
1497 if (rtx_equal_p (temp, op0))
1499 gcc_assert (ti_temp);
1500 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1503 temp2 = temp; /* op0 is _not_ allowed, see above. */
1510 temp1 = gen_reg_rtx (DImode);
1511 temp2 = gen_reg_rtx (DImode);
1512 temp3 = gen_reg_rtx (DImode);
1513 temp4 = gen_reg_rtx (DImode);
1514 temp5 = gen_reg_rtx (DImode);
1517 emit_insn (gen_sethh (temp1, op1));
1518 emit_insn (gen_setlm (temp2, op1));
1519 emit_insn (gen_sethm (temp3, temp1, op1));
1520 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1521 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1522 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1523 gen_rtx_PLUS (DImode, temp4, temp2)));
1524 emit_insn (gen_setlo (op0, temp5, op1));
1528 /* Old old old backwards compatibility kruft here.
1529 Essentially it is MEDLOW with a fixed 64-bit
1530 virtual base added to all data segment addresses.
1531 Text-segment stuff is computed like MEDANY, we can't
1532 reuse the code above because the relocation knobs
1535 Data segment: sethi %hi(symbol), %temp1
1536 add %temp1, EMBMEDANY_BASE_REG, %temp2
1537 or %temp2, %lo(symbol), %reg */
1538 if (data_segment_operand (op1, GET_MODE (op1)))
1542 temp1 = temp; /* op0 is allowed. */
1547 temp1 = gen_reg_rtx (DImode);
1548 temp2 = gen_reg_rtx (DImode);
1551 emit_insn (gen_embmedany_sethi (temp1, op1));
1552 emit_insn (gen_embmedany_brsum (temp2, temp1));
1553 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1556 /* Text segment: sethi %uhi(symbol), %temp1
1557 sethi %hi(symbol), %temp2
1558 or %temp1, %ulo(symbol), %temp3
1559 sllx %temp3, 32, %temp4
1560 or %temp4, %temp2, %temp5
1561 or %temp5, %lo(symbol), %reg */
1566 /* It is possible that one of the registers we got for operands[2]
1567 might coincide with that of operands[0] (which is why we made
1568 it TImode). Pick the other one to use as our scratch. */
1569 if (rtx_equal_p (temp, op0))
1571 gcc_assert (ti_temp);
1572 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1575 temp2 = temp; /* op0 is _not_ allowed, see above. */
1582 temp1 = gen_reg_rtx (DImode);
1583 temp2 = gen_reg_rtx (DImode);
1584 temp3 = gen_reg_rtx (DImode);
1585 temp4 = gen_reg_rtx (DImode);
1586 temp5 = gen_reg_rtx (DImode);
1589 emit_insn (gen_embmedany_textuhi (temp1, op1));
1590 emit_insn (gen_embmedany_texthi (temp2, op1));
1591 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1592 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1593 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1594 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1595 gen_rtx_PLUS (DImode, temp4, temp2)));
1596 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1605 #if HOST_BITS_PER_WIDE_INT == 32
1607 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1612 /* These avoid problems when cross compiling. If we do not
1613 go through all this hair then the optimizer will see
1614 invalid REG_EQUAL notes or in some cases none at all. */
1615 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
1616 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1617 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1618 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1620 /* The optimizer is not to assume anything about exactly
1621 which bits are set for a HIGH, they are unspecified.
1622 Unfortunately this leads to many missed optimizations
1623 during CSE. We mask out the non-HIGH bits, and matches
1624 a plain movdi, to alleviate this problem. */
1626 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1628 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
1632 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1634 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1638 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1640 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1644 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1646 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1649 /* Worker routines for 64-bit constant formation on arch64.
1650 One of the key things to be doing in these emissions is
1651 to create as many temp REGs as possible. This makes it
1652 possible for half-built constants to be used later when
1653 such values are similar to something required later on.
1654 Without doing this, the optimizer cannot see such
1657 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1658 unsigned HOST_WIDE_INT, int);
1661 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1662 unsigned HOST_WIDE_INT low_bits, int is_neg)
1664 unsigned HOST_WIDE_INT high_bits;
1667 high_bits = (~low_bits) & 0xffffffff;
1669 high_bits = low_bits;
1671 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1674 emit_insn (gen_rtx_SET (VOIDmode, op0,
1675 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1679 /* If we are XOR'ing with -1, then we should emit a one's complement
1680 instead. This way the combiner will notice logical operations
1681 such as ANDN later on and substitute. */
1682 if ((low_bits & 0x3ff) == 0x3ff)
1684 emit_insn (gen_rtx_SET (VOIDmode, op0,
1685 gen_rtx_NOT (DImode, temp)));
1689 emit_insn (gen_rtx_SET (VOIDmode, op0,
1690 gen_safe_XOR64 (temp,
1691 (-(HOST_WIDE_INT)0x400
1692 | (low_bits & 0x3ff)))));
1697 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1698 unsigned HOST_WIDE_INT, int);
1701 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1702 unsigned HOST_WIDE_INT high_bits,
1703 unsigned HOST_WIDE_INT low_immediate,
1708 if ((high_bits & 0xfffffc00) != 0)
1710 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1711 if ((high_bits & ~0xfffffc00) != 0)
1712 emit_insn (gen_rtx_SET (VOIDmode, op0,
1713 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1719 emit_insn (gen_safe_SET64 (temp, high_bits));
1723 /* Now shift it up into place. */
1724 emit_insn (gen_rtx_SET (VOIDmode, op0,
1725 gen_rtx_ASHIFT (DImode, temp2,
1726 GEN_INT (shift_count))));
1728 /* If there is a low immediate part piece, finish up by
1729 putting that in as well. */
1730 if (low_immediate != 0)
1731 emit_insn (gen_rtx_SET (VOIDmode, op0,
1732 gen_safe_OR64 (op0, low_immediate)));
1735 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1736 unsigned HOST_WIDE_INT);
1738 /* Full 64-bit constant decomposition. Even though this is the
1739 'worst' case, we still optimize a few things away. */
1741 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1742 unsigned HOST_WIDE_INT high_bits,
1743 unsigned HOST_WIDE_INT low_bits)
1747 if (can_create_pseudo_p ())
1748 sub_temp = gen_reg_rtx (DImode);
1750 if ((high_bits & 0xfffffc00) != 0)
1752 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1753 if ((high_bits & ~0xfffffc00) != 0)
1754 emit_insn (gen_rtx_SET (VOIDmode,
1756 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1762 emit_insn (gen_safe_SET64 (temp, high_bits));
1766 if (can_create_pseudo_p ())
1768 rtx temp2 = gen_reg_rtx (DImode);
1769 rtx temp3 = gen_reg_rtx (DImode);
1770 rtx temp4 = gen_reg_rtx (DImode);
1772 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1773 gen_rtx_ASHIFT (DImode, sub_temp,
1776 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1777 if ((low_bits & ~0xfffffc00) != 0)
1779 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1780 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1781 emit_insn (gen_rtx_SET (VOIDmode, op0,
1782 gen_rtx_PLUS (DImode, temp4, temp3)));
1786 emit_insn (gen_rtx_SET (VOIDmode, op0,
1787 gen_rtx_PLUS (DImode, temp4, temp2)));
1792 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1793 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1794 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1797 /* We are in the middle of reload, so this is really
1798 painful. However we do still make an attempt to
1799 avoid emitting truly stupid code. */
1800 if (low1 != const0_rtx)
1802 emit_insn (gen_rtx_SET (VOIDmode, op0,
1803 gen_rtx_ASHIFT (DImode, sub_temp,
1804 GEN_INT (to_shift))));
1805 emit_insn (gen_rtx_SET (VOIDmode, op0,
1806 gen_rtx_IOR (DImode, op0, low1)));
1814 if (low2 != const0_rtx)
1816 emit_insn (gen_rtx_SET (VOIDmode, op0,
1817 gen_rtx_ASHIFT (DImode, sub_temp,
1818 GEN_INT (to_shift))));
1819 emit_insn (gen_rtx_SET (VOIDmode, op0,
1820 gen_rtx_IOR (DImode, op0, low2)));
1828 emit_insn (gen_rtx_SET (VOIDmode, op0,
1829 gen_rtx_ASHIFT (DImode, sub_temp,
1830 GEN_INT (to_shift))));
1831 if (low3 != const0_rtx)
1832 emit_insn (gen_rtx_SET (VOIDmode, op0,
1833 gen_rtx_IOR (DImode, op0, low3)));
1838 /* Analyze a 64-bit constant for certain properties. */
1839 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1840 unsigned HOST_WIDE_INT,
1841 int *, int *, int *);
1844 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1845 unsigned HOST_WIDE_INT low_bits,
1846 int *hbsp, int *lbsp, int *abbasp)
1848 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1851 lowest_bit_set = highest_bit_set = -1;
1855 if ((lowest_bit_set == -1)
1856 && ((low_bits >> i) & 1))
1858 if ((highest_bit_set == -1)
1859 && ((high_bits >> (32 - i - 1)) & 1))
1860 highest_bit_set = (64 - i - 1);
1863 && ((highest_bit_set == -1)
1864 || (lowest_bit_set == -1)));
1870 if ((lowest_bit_set == -1)
1871 && ((high_bits >> i) & 1))
1872 lowest_bit_set = i + 32;
1873 if ((highest_bit_set == -1)
1874 && ((low_bits >> (32 - i - 1)) & 1))
1875 highest_bit_set = 32 - i - 1;
1878 && ((highest_bit_set == -1)
1879 || (lowest_bit_set == -1)));
1881 /* If there are no bits set this should have gone out
1882 as one instruction! */
1883 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1884 all_bits_between_are_set = 1;
1885 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1889 if ((low_bits & (1 << i)) != 0)
1894 if ((high_bits & (1 << (i - 32))) != 0)
1897 all_bits_between_are_set = 0;
1900 *hbsp = highest_bit_set;
1901 *lbsp = lowest_bit_set;
1902 *abbasp = all_bits_between_are_set;
1905 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1908 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1909 unsigned HOST_WIDE_INT low_bits)
1911 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1914 || high_bits == 0xffffffff)
1917 analyze_64bit_constant (high_bits, low_bits,
1918 &highest_bit_set, &lowest_bit_set,
1919 &all_bits_between_are_set);
1921 if ((highest_bit_set == 63
1922 || lowest_bit_set == 0)
1923 && all_bits_between_are_set != 0)
1926 if ((highest_bit_set - lowest_bit_set) < 21)
1932 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1933 unsigned HOST_WIDE_INT,
1936 static unsigned HOST_WIDE_INT
1937 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1938 unsigned HOST_WIDE_INT low_bits,
1939 int lowest_bit_set, int shift)
1941 HOST_WIDE_INT hi, lo;
1943 if (lowest_bit_set < 32)
1945 lo = (low_bits >> lowest_bit_set) << shift;
1946 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1951 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1953 gcc_assert (! (hi & lo));
1957 /* Here we are sure to be arch64 and this is an integer constant
1958 being loaded into a register. Emit the most efficient
1959 insn sequence possible. Detection of all the 1-insn cases
1960 has been done already. */
1962 sparc_emit_set_const64 (rtx op0, rtx op1)
1964 unsigned HOST_WIDE_INT high_bits, low_bits;
1965 int lowest_bit_set, highest_bit_set;
1966 int all_bits_between_are_set;
1969 /* Sanity check that we know what we are working with. */
1970 gcc_assert (TARGET_ARCH64
1971 && (GET_CODE (op0) == SUBREG
1972 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
1974 if (! can_create_pseudo_p ())
1977 if (GET_CODE (op1) != CONST_INT)
1979 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1984 temp = gen_reg_rtx (DImode);
1986 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1987 low_bits = (INTVAL (op1) & 0xffffffff);
1989 /* low_bits bits 0 --> 31
1990 high_bits bits 32 --> 63 */
1992 analyze_64bit_constant (high_bits, low_bits,
1993 &highest_bit_set, &lowest_bit_set,
1994 &all_bits_between_are_set);
1996 /* First try for a 2-insn sequence. */
1998 /* These situations are preferred because the optimizer can
1999 * do more things with them:
2001 * sllx %reg, shift, %reg
2003 * srlx %reg, shift, %reg
2004 * 3) mov some_small_const, %reg
2005 * sllx %reg, shift, %reg
2007 if (((highest_bit_set == 63
2008 || lowest_bit_set == 0)
2009 && all_bits_between_are_set != 0)
2010 || ((highest_bit_set - lowest_bit_set) < 12))
2012 HOST_WIDE_INT the_const = -1;
2013 int shift = lowest_bit_set;
2015 if ((highest_bit_set != 63
2016 && lowest_bit_set != 0)
2017 || all_bits_between_are_set == 0)
2020 create_simple_focus_bits (high_bits, low_bits,
2023 else if (lowest_bit_set == 0)
2024 shift = -(63 - highest_bit_set);
2026 gcc_assert (SPARC_SIMM13_P (the_const));
2027 gcc_assert (shift != 0);
2029 emit_insn (gen_safe_SET64 (temp, the_const));
2031 emit_insn (gen_rtx_SET (VOIDmode,
2033 gen_rtx_ASHIFT (DImode,
2037 emit_insn (gen_rtx_SET (VOIDmode,
2039 gen_rtx_LSHIFTRT (DImode,
2041 GEN_INT (-shift))));
2045 /* Now a range of 22 or less bits set somewhere.
2046 * 1) sethi %hi(focus_bits), %reg
2047 * sllx %reg, shift, %reg
2048 * 2) sethi %hi(focus_bits), %reg
2049 * srlx %reg, shift, %reg
2051 if ((highest_bit_set - lowest_bit_set) < 21)
2053 unsigned HOST_WIDE_INT focus_bits =
2054 create_simple_focus_bits (high_bits, low_bits,
2055 lowest_bit_set, 10);
2057 gcc_assert (SPARC_SETHI_P (focus_bits));
2058 gcc_assert (lowest_bit_set != 10);
2060 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
2062 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2063 if (lowest_bit_set < 10)
2064 emit_insn (gen_rtx_SET (VOIDmode,
2066 gen_rtx_LSHIFTRT (DImode, temp,
2067 GEN_INT (10 - lowest_bit_set))));
2068 else if (lowest_bit_set > 10)
2069 emit_insn (gen_rtx_SET (VOIDmode,
2071 gen_rtx_ASHIFT (DImode, temp,
2072 GEN_INT (lowest_bit_set - 10))));
2076 /* 1) sethi %hi(low_bits), %reg
2077 * or %reg, %lo(low_bits), %reg
2078 * 2) sethi %hi(~low_bits), %reg
2079 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2082 || high_bits == 0xffffffff)
2084 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2085 (high_bits == 0xffffffff));
2089 /* Now, try 3-insn sequences. */
2091 /* 1) sethi %hi(high_bits), %reg
2092 * or %reg, %lo(high_bits), %reg
2093 * sllx %reg, 32, %reg
2097 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2101 /* We may be able to do something quick
2102 when the constant is negated, so try that. */
2103 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2104 (~low_bits) & 0xfffffc00))
2106 /* NOTE: The trailing bits get XOR'd so we need the
2107 non-negated bits, not the negated ones. */
2108 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2110 if ((((~high_bits) & 0xffffffff) == 0
2111 && ((~low_bits) & 0x80000000) == 0)
2112 || (((~high_bits) & 0xffffffff) == 0xffffffff
2113 && ((~low_bits) & 0x80000000) != 0))
2115 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
2117 if ((SPARC_SETHI_P (fast_int)
2118 && (~high_bits & 0xffffffff) == 0)
2119 || SPARC_SIMM13_P (fast_int))
2120 emit_insn (gen_safe_SET64 (temp, fast_int));
2122 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
2127 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2128 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2129 sparc_emit_set_const64 (temp, negated_const);
2132 /* If we are XOR'ing with -1, then we should emit a one's complement
2133 instead. This way the combiner will notice logical operations
2134 such as ANDN later on and substitute. */
2135 if (trailing_bits == 0x3ff)
2137 emit_insn (gen_rtx_SET (VOIDmode, op0,
2138 gen_rtx_NOT (DImode, temp)));
2142 emit_insn (gen_rtx_SET (VOIDmode,
2144 gen_safe_XOR64 (temp,
2145 (-0x400 | trailing_bits))));
2150 /* 1) sethi %hi(xxx), %reg
2151 * or %reg, %lo(xxx), %reg
2152 * sllx %reg, yyy, %reg
2154 * ??? This is just a generalized version of the low_bits==0
2155 * thing above, FIXME...
2157 if ((highest_bit_set - lowest_bit_set) < 32)
2159 unsigned HOST_WIDE_INT focus_bits =
2160 create_simple_focus_bits (high_bits, low_bits,
2163 /* We can't get here in this state. */
2164 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
2166 /* So what we know is that the set bits straddle the
2167 middle of the 64-bit word. */
2168 sparc_emit_set_const64_quick2 (op0, temp,
2174 /* 1) sethi %hi(high_bits), %reg
2175 * or %reg, %lo(high_bits), %reg
2176 * sllx %reg, 32, %reg
2177 * or %reg, low_bits, %reg
2179 if (SPARC_SIMM13_P(low_bits)
2180 && ((int)low_bits > 0))
2182 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2186 /* The easiest way when all else fails, is full decomposition. */
2187 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2189 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2191 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2192 return the mode to be used for the comparison. For floating-point,
2193 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2194 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2195 processing is needed. */
2198 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2200 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2226 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2227 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2229 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2230 return CCX_NOOVmode;
2236 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2243 /* Emit the compare insn and return the CC reg for a CODE comparison
2244 with operands X and Y. */
2247 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2249 enum machine_mode mode;
2252 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2255 mode = SELECT_CC_MODE (code, x, y);
2257 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2258 fcc regs (cse can't tell they're really call clobbered regs and will
2259 remove a duplicate comparison even if there is an intervening function
2260 call - it will then try to reload the cc reg via an int reg which is why
2261 we need the movcc patterns). It is possible to provide the movcc
2262 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2263 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2264 to tell cse that CCFPE mode registers (even pseudos) are call
2267 /* ??? This is an experiment. Rather than making changes to cse which may
2268 or may not be easy/clean, we do our own cse. This is possible because
2269 we will generate hard registers. Cse knows they're call clobbered (it
2270 doesn't know the same thing about pseudos). If we guess wrong, no big
2271 deal, but if we win, great! */
2273 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2274 #if 1 /* experiment */
2277 /* We cycle through the registers to ensure they're all exercised. */
2278 static int next_fcc_reg = 0;
2279 /* Previous x,y for each fcc reg. */
2280 static rtx prev_args[4][2];
2282 /* Scan prev_args for x,y. */
2283 for (reg = 0; reg < 4; reg++)
2284 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2289 prev_args[reg][0] = x;
2290 prev_args[reg][1] = y;
2291 next_fcc_reg = (next_fcc_reg + 1) & 3;
2293 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2296 cc_reg = gen_reg_rtx (mode);
2297 #endif /* ! experiment */
2298 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2299 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2301 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2303 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2304 will only result in an unrecognizable insn so no point in asserting. */
2305 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2311 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2314 gen_compare_reg (rtx cmp)
2316 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2319 /* This function is used for v9 only.
2320 DEST is the target of the Scc insn.
2321 CODE is the code for an Scc's comparison.
2322 X and Y are the values we compare.
2324 This function is needed to turn
2327 (gt (reg:CCX 100 %icc)
2331 (gt:DI (reg:CCX 100 %icc)
2334 IE: The instruction recognizer needs to see the mode of the comparison to
2335 find the right instruction. We could use "gt:DI" right in the
2336 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2339 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2342 && (GET_MODE (x) == DImode
2343 || GET_MODE (dest) == DImode))
2346 /* Try to use the movrCC insns. */
2348 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2350 && v9_regcmp_p (compare_code))
2355 /* Special case for op0 != 0. This can be done with one instruction if
2358 if (compare_code == NE
2359 && GET_MODE (dest) == DImode
2360 && rtx_equal_p (op0, dest))
2362 emit_insn (gen_rtx_SET (VOIDmode, dest,
2363 gen_rtx_IF_THEN_ELSE (DImode,
2364 gen_rtx_fmt_ee (compare_code, DImode,
2371 if (reg_overlap_mentioned_p (dest, op0))
2373 /* Handle the case where dest == x.
2374 We "early clobber" the result. */
2375 op0 = gen_reg_rtx (GET_MODE (x));
2376 emit_move_insn (op0, x);
2379 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2380 if (GET_MODE (op0) != DImode)
2382 temp = gen_reg_rtx (DImode);
2383 convert_move (temp, op0, 0);
2387 emit_insn (gen_rtx_SET (VOIDmode, dest,
2388 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2389 gen_rtx_fmt_ee (compare_code, DImode,
2397 x = gen_compare_reg_1 (compare_code, x, y);
2400 gcc_assert (GET_MODE (x) != CC_NOOVmode
2401 && GET_MODE (x) != CCX_NOOVmode);
2403 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2404 emit_insn (gen_rtx_SET (VOIDmode, dest,
2405 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2406 gen_rtx_fmt_ee (compare_code,
2407 GET_MODE (x), x, y),
2408 const1_rtx, dest)));
2414 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2415 without jumps using the addx/subx instructions. */
2418 emit_scc_insn (rtx operands[])
2425 /* The quad-word fp compare library routines all return nonzero to indicate
2426 true, which is different from the equivalent libgcc routines, so we must
2427 handle them specially here. */
2428 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2430 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2431 GET_CODE (operands[1]));
2432 operands[2] = XEXP (operands[1], 0);
2433 operands[3] = XEXP (operands[1], 1);
2436 code = GET_CODE (operands[1]);
2440 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2441 more applications). The exception to this is "reg != 0" which can
2442 be done in one instruction on v9 (so we do it). */
2445 if (GET_MODE (x) == SImode)
2447 rtx pat = gen_seqsi_special (operands[0], x, y);
2451 else if (GET_MODE (x) == DImode)
2453 rtx pat = gen_seqdi_special (operands[0], x, y);
2461 if (GET_MODE (x) == SImode)
2463 rtx pat = gen_snesi_special (operands[0], x, y);
2467 else if (GET_MODE (x) == DImode)
2469 rtx pat = gen_snedi_special (operands[0], x, y);
2475 /* For the rest, on v9 we can use conditional moves. */
2479 if (gen_v9_scc (operands[0], code, x, y))
2483 /* We can do LTU and GEU using the addx/subx instructions too. And
2484 for GTU/LEU, if both operands are registers swap them and fall
2485 back to the easy case. */
2486 if (code == GTU || code == LEU)
2488 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2489 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2494 code = swap_condition (code);
2498 if (code == LTU || code == GEU)
2500 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2501 gen_rtx_fmt_ee (code, SImode,
2502 gen_compare_reg_1 (code, x, y),
2507 /* Nope, do branches. */
2511 /* Emit a conditional jump insn for the v9 architecture using comparison code
2512 CODE and jump target LABEL.
2513 This function exists to take advantage of the v9 brxx insns. */
2516 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2518 emit_jump_insn (gen_rtx_SET (VOIDmode,
2520 gen_rtx_IF_THEN_ELSE (VOIDmode,
2521 gen_rtx_fmt_ee (code, GET_MODE (op0),
2523 gen_rtx_LABEL_REF (VOIDmode, label),
2528 emit_conditional_branch_insn (rtx operands[])
2530 /* The quad-word fp compare library routines all return nonzero to indicate
2531 true, which is different from the equivalent libgcc routines, so we must
2532 handle them specially here. */
2533 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2535 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2536 GET_CODE (operands[0]));
2537 operands[1] = XEXP (operands[0], 0);
2538 operands[2] = XEXP (operands[0], 1);
2541 if (TARGET_ARCH64 && operands[2] == const0_rtx
2542 && GET_CODE (operands[1]) == REG
2543 && GET_MODE (operands[1]) == DImode)
2545 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2549 operands[1] = gen_compare_reg (operands[0]);
2550 operands[2] = const0_rtx;
2551 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2552 operands[1], operands[2]);
2553 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2558 /* Generate a DFmode part of a hard TFmode register.
2559 REG is the TFmode hard register, LOW is 1 for the
2560 low 64bit of the register and 0 otherwise.
2563 gen_df_reg (rtx reg, int low)
2565 int regno = REGNO (reg);
2567 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2568 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2569 return gen_rtx_REG (DFmode, regno);
2572 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2573 Unlike normal calls, TFmode operands are passed by reference. It is
2574 assumed that no more than 3 operands are required. */
2577 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2579 rtx ret_slot = NULL, arg[3], func_sym;
2582 /* We only expect to be called for conversions, unary, and binary ops. */
2583 gcc_assert (nargs == 2 || nargs == 3);
2585 for (i = 0; i < nargs; ++i)
2587 rtx this_arg = operands[i];
2590 /* TFmode arguments and return values are passed by reference. */
2591 if (GET_MODE (this_arg) == TFmode)
2593 int force_stack_temp;
2595 force_stack_temp = 0;
2596 if (TARGET_BUGGY_QP_LIB && i == 0)
2597 force_stack_temp = 1;
2599 if (GET_CODE (this_arg) == MEM
2600 && ! force_stack_temp)
2601 this_arg = XEXP (this_arg, 0);
2602 else if (CONSTANT_P (this_arg)
2603 && ! force_stack_temp)
2605 this_slot = force_const_mem (TFmode, this_arg);
2606 this_arg = XEXP (this_slot, 0);
2610 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2612 /* Operand 0 is the return value. We'll copy it out later. */
2614 emit_move_insn (this_slot, this_arg);
2616 ret_slot = this_slot;
2618 this_arg = XEXP (this_slot, 0);
2625 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2627 if (GET_MODE (operands[0]) == TFmode)
2630 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2631 arg[0], GET_MODE (arg[0]),
2632 arg[1], GET_MODE (arg[1]));
2634 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2635 arg[0], GET_MODE (arg[0]),
2636 arg[1], GET_MODE (arg[1]),
2637 arg[2], GET_MODE (arg[2]));
2640 emit_move_insn (operands[0], ret_slot);
2646 gcc_assert (nargs == 2);
2648 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2649 GET_MODE (operands[0]), 1,
2650 arg[1], GET_MODE (arg[1]));
2652 if (ret != operands[0])
2653 emit_move_insn (operands[0], ret);
2657 /* Expand soft-float TFmode calls to sparc abi routines. */
2660 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2682 emit_soft_tfmode_libcall (func, 3, operands);
2686 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2690 gcc_assert (code == SQRT);
2693 emit_soft_tfmode_libcall (func, 2, operands);
2697 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2704 switch (GET_MODE (operands[1]))
2717 case FLOAT_TRUNCATE:
2718 switch (GET_MODE (operands[0]))
2732 switch (GET_MODE (operands[1]))
2737 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
2747 case UNSIGNED_FLOAT:
2748 switch (GET_MODE (operands[1]))
2753 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2764 switch (GET_MODE (operands[0]))
2778 switch (GET_MODE (operands[0]))
2795 emit_soft_tfmode_libcall (func, 2, operands);
2798 /* Expand a hard-float tfmode operation. All arguments must be in
2802 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2806 if (GET_RTX_CLASS (code) == RTX_UNARY)
2808 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2809 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2813 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2814 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2815 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2816 operands[1], operands[2]);
2819 if (register_operand (operands[0], VOIDmode))
2822 dest = gen_reg_rtx (GET_MODE (operands[0]));
2824 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2826 if (dest != operands[0])
2827 emit_move_insn (operands[0], dest);
2831 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2833 if (TARGET_HARD_QUAD)
2834 emit_hard_tfmode_operation (code, operands);
2836 emit_soft_tfmode_binop (code, operands);
2840 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2842 if (TARGET_HARD_QUAD)
2843 emit_hard_tfmode_operation (code, operands);
2845 emit_soft_tfmode_unop (code, operands);
2849 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2851 if (TARGET_HARD_QUAD)
2852 emit_hard_tfmode_operation (code, operands);
2854 emit_soft_tfmode_cvt (code, operands);
2857 /* Return nonzero if a branch/jump/call instruction will be emitting
2858 nop into its delay slot. */
2861 empty_delay_slot (rtx insn)
2865 /* If no previous instruction (should not happen), return true. */
2866 if (PREV_INSN (insn) == NULL)
2869 seq = NEXT_INSN (PREV_INSN (insn));
2870 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2876 /* Return nonzero if TRIAL can go into the call delay slot. */
2879 tls_call_delay (rtx trial)
2884 call __tls_get_addr, %tgd_call (foo)
2885 add %l7, %o0, %o0, %tgd_add (foo)
2886 while Sun as/ld does not. */
2887 if (TARGET_GNU_TLS || !TARGET_TLS)
2890 pat = PATTERN (trial);
2892 /* We must reject tgd_add{32|64}, i.e.
2893 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2894 and tldm_add{32|64}, i.e.
2895 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2897 if (GET_CODE (pat) == SET
2898 && GET_CODE (SET_SRC (pat)) == PLUS)
2900 rtx unspec = XEXP (SET_SRC (pat), 1);
2902 if (GET_CODE (unspec) == UNSPEC
2903 && (XINT (unspec, 1) == UNSPEC_TLSGD
2904 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2911 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2912 instruction. RETURN_P is true if the v9 variant 'return' is to be
2913 considered in the test too.
2915 TRIAL must be a SET whose destination is a REG appropriate for the
2916 'restore' instruction or, if RETURN_P is true, for the 'return'
2920 eligible_for_restore_insn (rtx trial, bool return_p)
2922 rtx pat = PATTERN (trial);
2923 rtx src = SET_SRC (pat);
2925 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2926 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2927 && arith_operand (src, GET_MODE (src)))
2930 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2932 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2935 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2936 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2937 && arith_double_operand (src, GET_MODE (src)))
2938 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2940 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2941 else if (! TARGET_FPU && register_operand (src, SFmode))
2944 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2945 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
2948 /* If we have the 'return' instruction, anything that does not use
2949 local or output registers and can go into a delay slot wins. */
2952 && !epilogue_renumber (&pat, 1)
2953 && get_attr_in_uncond_branch_delay (trial)
2954 == IN_UNCOND_BRANCH_DELAY_TRUE)
2957 /* The 'restore src1,src2,dest' pattern for SImode. */
2958 else if (GET_CODE (src) == PLUS
2959 && register_operand (XEXP (src, 0), SImode)
2960 && arith_operand (XEXP (src, 1), SImode))
2963 /* The 'restore src1,src2,dest' pattern for DImode. */
2964 else if (GET_CODE (src) == PLUS
2965 && register_operand (XEXP (src, 0), DImode)
2966 && arith_double_operand (XEXP (src, 1), DImode))
2969 /* The 'restore src1,%lo(src2),dest' pattern. */
2970 else if (GET_CODE (src) == LO_SUM
2971 && ! TARGET_CM_MEDMID
2972 && ((register_operand (XEXP (src, 0), SImode)
2973 && immediate_operand (XEXP (src, 1), SImode))
2975 && register_operand (XEXP (src, 0), DImode)
2976 && immediate_operand (XEXP (src, 1), DImode))))
2979 /* The 'restore src,src,dest' pattern. */
2980 else if (GET_CODE (src) == ASHIFT
2981 && (register_operand (XEXP (src, 0), SImode)
2982 || register_operand (XEXP (src, 0), DImode))
2983 && XEXP (src, 1) == const1_rtx)
2989 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2992 eligible_for_return_delay (rtx trial)
2997 if (GET_CODE (trial) != INSN)
3000 if (get_attr_length (trial) != 1)
3003 /* If the function uses __builtin_eh_return, the eh_return machinery
3004 occupies the delay slot. */
3005 if (crtl->calls_eh_return)
3008 /* In the case of a leaf or flat function, anything can go into the slot. */
3009 if (sparc_leaf_function_p || TARGET_FLAT)
3011 get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
3013 pat = PATTERN (trial);
3014 if (GET_CODE (pat) == PARALLEL)
3020 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
3022 rtx expr = XVECEXP (pat, 0, i);
3023 if (GET_CODE (expr) != SET)
3025 if (GET_CODE (SET_DEST (expr)) != REG)
3027 regno = REGNO (SET_DEST (expr));
3028 if (regno >= 8 && regno < 24)
3031 return !epilogue_renumber (&pat, 1)
3032 && (get_attr_in_uncond_branch_delay (trial)
3033 == IN_UNCOND_BRANCH_DELAY_TRUE);
3036 if (GET_CODE (pat) != SET)
3039 if (GET_CODE (SET_DEST (pat)) != REG)
3042 regno = REGNO (SET_DEST (pat));
3044 /* Otherwise, only operations which can be done in tandem with
3045 a `restore' or `return' insn can go into the delay slot. */
3046 if (regno >= 8 && regno < 24)
3049 /* If this instruction sets up floating point register and we have a return
3050 instruction, it can probably go in. But restore will not work
3054 && !epilogue_renumber (&pat, 1)
3055 && get_attr_in_uncond_branch_delay (trial)
3056 == IN_UNCOND_BRANCH_DELAY_TRUE);
3058 return eligible_for_restore_insn (trial, true);
3061 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3064 eligible_for_sibcall_delay (rtx trial)
3068 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3071 if (get_attr_length (trial) != 1)
3074 pat = PATTERN (trial);
3076 if (sparc_leaf_function_p || TARGET_FLAT)
3078 /* If the tail call is done using the call instruction,
3079 we have to restore %o7 in the delay slot. */
3080 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3083 /* %g1 is used to build the function address */
3084 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3090 /* Otherwise, only operations which can be done in tandem with
3091 a `restore' insn can go into the delay slot. */
3092 if (GET_CODE (SET_DEST (pat)) != REG
3093 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3094 || REGNO (SET_DEST (pat)) >= 32)
3097 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3099 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3102 return eligible_for_restore_insn (trial, false);
3106 short_branch (int uid1, int uid2)
3108 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3110 /* Leave a few words of "slop". */
3111 if (delta >= -1023 && delta <= 1022)
3117 /* Return nonzero if REG is not used after INSN.
3118 We assume REG is a reload reg, and therefore does
3119 not live past labels or calls or jumps. */
3121 reg_unused_after (rtx reg, rtx insn)
3123 enum rtx_code code, prev_code = UNKNOWN;
3125 while ((insn = NEXT_INSN (insn)))
3127 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3130 code = GET_CODE (insn);
3131 if (GET_CODE (insn) == CODE_LABEL)
3136 rtx set = single_set (insn);
3137 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3140 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3142 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3150 /* Determine if it's legal to put X into the constant pool. This
3151 is not possible if X contains the address of a symbol that is
3152 not constant (TLS) or not known at final link time (PIC). */
3155 sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
3157 switch (GET_CODE (x))
3162 /* Accept all non-symbolic constants. */
3166 /* Labels are OK iff we are non-PIC. */
3167 return flag_pic != 0;
3170 /* 'Naked' TLS symbol references are never OK,
3171 non-TLS symbols are OK iff we are non-PIC. */
3172 if (SYMBOL_REF_TLS_MODEL (x))
3175 return flag_pic != 0;
3178 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
3181 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
3182 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
3190 /* Global Offset Table support. */
3191 static GTY(()) rtx got_helper_rtx = NULL_RTX;
3192 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
3194 /* Return the SYMBOL_REF for the Global Offset Table. */
3196 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
3201 if (!sparc_got_symbol)
3202 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3204 return sparc_got_symbol;
3207 /* Ensure that we are not using patterns that are not OK with PIC. */
3217 op = recog_data.operand[i];
3218 gcc_assert (GET_CODE (op) != SYMBOL_REF
3219 && (GET_CODE (op) != CONST
3220 || (GET_CODE (XEXP (op, 0)) == MINUS
3221 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3222 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3229 /* Return true if X is an address which needs a temporary register when
3230 reloaded while generating PIC code. */
3233 pic_address_needs_scratch (rtx x)
3235 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3236 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3237 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3238 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3239 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3245 /* Determine if a given RTX is a valid constant. We already know this
3246 satisfies CONSTANT_P. */
3249 sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
3251 switch (GET_CODE (x))
3255 if (sparc_tls_referenced_p (x))
3260 if (GET_MODE (x) == VOIDmode)
3263 /* Floating point constants are generally not ok.
3264 The only exception is 0.0 and all-ones in VIS. */
3266 && SCALAR_FLOAT_MODE_P (mode)
3267 && (const_zero_operand (x, mode)
3268 || const_all_ones_operand (x, mode)))
3274 /* Vector constants are generally not ok.
3275 The only exception is 0 or -1 in VIS. */
3277 && (const_zero_operand (x, mode)
3278 || const_all_ones_operand (x, mode)))
3290 /* Determine if a given RTX is a valid constant address. */
3293 constant_address_p (rtx x)
3295 switch (GET_CODE (x))
3303 if (flag_pic && pic_address_needs_scratch (x))
3305 return sparc_legitimate_constant_p (Pmode, x);
3308 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3315 /* Nonzero if the constant value X is a legitimate general operand
3316 when generating PIC code. It is given that flag_pic is on and
3317 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3320 legitimate_pic_operand_p (rtx x)
3322 if (pic_address_needs_scratch (x))
3324 if (sparc_tls_referenced_p (x))
3329 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3331 && INTVAL (X) >= -0x1000 \
3332 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3334 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3336 && INTVAL (X) >= -0x1000 \
3337 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3339 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3341 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3342 ordinarily. This changes a bit when generating PIC. */
3345 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3347 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3349 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3351 else if (GET_CODE (addr) == PLUS)
3353 rs1 = XEXP (addr, 0);
3354 rs2 = XEXP (addr, 1);
3356 /* Canonicalize. REG comes first, if there are no regs,
3357 LO_SUM comes first. */
3359 && GET_CODE (rs1) != SUBREG
3361 || GET_CODE (rs2) == SUBREG
3362 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3364 rs1 = XEXP (addr, 1);
3365 rs2 = XEXP (addr, 0);
3369 && rs1 == pic_offset_table_rtx
3371 && GET_CODE (rs2) != SUBREG
3372 && GET_CODE (rs2) != LO_SUM
3373 && GET_CODE (rs2) != MEM
3374 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3375 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3376 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3378 || GET_CODE (rs1) == SUBREG)
3379 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3384 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3385 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3387 /* We prohibit REG + REG for TFmode when there are no quad move insns
3388 and we consequently need to split. We do this because REG+REG
3389 is not an offsettable address. If we get the situation in reload
3390 where source and destination of a movtf pattern are both MEMs with
3391 REG+REG address, then only one of them gets converted to an
3392 offsettable address. */
3394 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3397 /* We prohibit REG + REG on ARCH32 if not optimizing for
3398 DFmode/DImode because then mem_min_alignment is likely to be zero
3399 after reload and the forced split would lack a matching splitter
3401 if (TARGET_ARCH32 && !optimize
3402 && (mode == DFmode || mode == DImode))
3405 else if (USE_AS_OFFSETABLE_LO10
3406 && GET_CODE (rs1) == LO_SUM
3408 && ! TARGET_CM_MEDMID
3409 && RTX_OK_FOR_OLO10_P (rs2, mode))
3412 imm1 = XEXP (rs1, 1);
3413 rs1 = XEXP (rs1, 0);
3414 if (!CONSTANT_P (imm1)
3415 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3419 else if (GET_CODE (addr) == LO_SUM)
3421 rs1 = XEXP (addr, 0);
3422 imm1 = XEXP (addr, 1);
3424 if (!CONSTANT_P (imm1)
3425 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3428 /* We can't allow TFmode in 32-bit mode, because an offset greater
3429 than the alignment (8) may cause the LO_SUM to overflow. */
3430 if (mode == TFmode && TARGET_ARCH32)
3433 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3438 if (GET_CODE (rs1) == SUBREG)
3439 rs1 = SUBREG_REG (rs1);
3445 if (GET_CODE (rs2) == SUBREG)
3446 rs2 = SUBREG_REG (rs2);
3453 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3454 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3459 if ((REGNO (rs1) >= 32
3460 && REGNO (rs1) != FRAME_POINTER_REGNUM
3461 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3463 && (REGNO (rs2) >= 32
3464 && REGNO (rs2) != FRAME_POINTER_REGNUM
3465 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3471 /* Return the SYMBOL_REF for the tls_get_addr function. */
3473 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3476 sparc_tls_get_addr (void)
3478 if (!sparc_tls_symbol)
3479 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3481 return sparc_tls_symbol;
3484 /* Return the Global Offset Table to be used in TLS mode. */
3487 sparc_tls_got (void)
3489 /* In PIC mode, this is just the PIC offset table. */
3492 crtl->uses_pic_offset_table = 1;
3493 return pic_offset_table_rtx;
3496 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3497 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3498 if (TARGET_SUN_TLS && TARGET_ARCH32)
3500 load_got_register ();
3501 return global_offset_table_rtx;
3504 /* In all other cases, we load a new pseudo with the GOT symbol. */
3505 return copy_to_reg (sparc_got ());
3508 /* Return true if X contains a thread-local symbol. */
3511 sparc_tls_referenced_p (rtx x)
3513 if (!TARGET_HAVE_TLS)
3516 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3517 x = XEXP (XEXP (x, 0), 0);
3519 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3522 /* That's all we handle in sparc_legitimize_tls_address for now. */
3526 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3527 this (thread-local) address. */
3530 sparc_legitimize_tls_address (rtx addr)
3532 rtx temp1, temp2, temp3, ret, o0, got, insn;
3534 gcc_assert (can_create_pseudo_p ());
3536 if (GET_CODE (addr) == SYMBOL_REF)
3537 switch (SYMBOL_REF_TLS_MODEL (addr))
3539 case TLS_MODEL_GLOBAL_DYNAMIC:
3541 temp1 = gen_reg_rtx (SImode);
3542 temp2 = gen_reg_rtx (SImode);
3543 ret = gen_reg_rtx (Pmode);
3544 o0 = gen_rtx_REG (Pmode, 8);
3545 got = sparc_tls_got ();
3546 emit_insn (gen_tgd_hi22 (temp1, addr));
3547 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3550 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3551 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3556 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3557 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3560 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3561 insn = get_insns ();
3563 emit_libcall_block (insn, ret, o0, addr);
3566 case TLS_MODEL_LOCAL_DYNAMIC:
3568 temp1 = gen_reg_rtx (SImode);
3569 temp2 = gen_reg_rtx (SImode);
3570 temp3 = gen_reg_rtx (Pmode);
3571 ret = gen_reg_rtx (Pmode);
3572 o0 = gen_rtx_REG (Pmode, 8);
3573 got = sparc_tls_got ();
3574 emit_insn (gen_tldm_hi22 (temp1));
3575 emit_insn (gen_tldm_lo10 (temp2, temp1));
3578 emit_insn (gen_tldm_add32 (o0, got, temp2));
3579 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3584 emit_insn (gen_tldm_add64 (o0, got, temp2));
3585 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3588 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3589 insn = get_insns ();
3591 emit_libcall_block (insn, temp3, o0,
3592 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3593 UNSPEC_TLSLD_BASE));
3594 temp1 = gen_reg_rtx (SImode);
3595 temp2 = gen_reg_rtx (SImode);
3596 emit_insn (gen_tldo_hix22 (temp1, addr));
3597 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3599 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3601 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3604 case TLS_MODEL_INITIAL_EXEC:
3605 temp1 = gen_reg_rtx (SImode);
3606 temp2 = gen_reg_rtx (SImode);
3607 temp3 = gen_reg_rtx (Pmode);
3608 got = sparc_tls_got ();
3609 emit_insn (gen_tie_hi22 (temp1, addr));
3610 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3612 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3614 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3617 ret = gen_reg_rtx (Pmode);
3619 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3622 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3626 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3629 case TLS_MODEL_LOCAL_EXEC:
3630 temp1 = gen_reg_rtx (Pmode);
3631 temp2 = gen_reg_rtx (Pmode);
3634 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3635 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3639 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3640 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3642 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3649 else if (GET_CODE (addr) == CONST)
3653 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3655 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3656 offset = XEXP (XEXP (addr, 0), 1);
3658 base = force_operand (base, NULL_RTX);
3659 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3660 offset = force_reg (Pmode, offset);
3661 ret = gen_rtx_PLUS (Pmode, base, offset);
3665 gcc_unreachable (); /* for now ... */
3670 /* Legitimize PIC addresses. If the address is already position-independent,
3671 we return ORIG. Newly generated position-independent addresses go into a
3672 reg. This is REG if nonzero, otherwise we allocate register(s) as
3676 sparc_legitimize_pic_address (rtx orig, rtx reg)
3678 bool gotdata_op = false;
3680 if (GET_CODE (orig) == SYMBOL_REF
3681 /* See the comment in sparc_expand_move. */
3682 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
3684 rtx pic_ref, address;
3689 gcc_assert (can_create_pseudo_p ());
3690 reg = gen_reg_rtx (Pmode);
3695 /* If not during reload, allocate another temp reg here for loading
3696 in the address, so that these instructions can be optimized
3698 rtx temp_reg = (! can_create_pseudo_p ()
3699 ? reg : gen_reg_rtx (Pmode));
3701 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3702 won't get confused into thinking that these two instructions
3703 are loading in the true address of the symbol. If in the
3704 future a PIC rtx exists, that should be used instead. */
3707 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3708 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3712 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3713 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3721 crtl->uses_pic_offset_table = 1;
3725 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3726 pic_offset_table_rtx,
3729 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3730 pic_offset_table_rtx,
3736 = gen_const_mem (Pmode,
3737 gen_rtx_PLUS (Pmode,
3738 pic_offset_table_rtx, address));
3739 insn = emit_move_insn (reg, pic_ref);
3742 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3744 set_unique_reg_note (insn, REG_EQUAL, orig);
3747 else if (GET_CODE (orig) == CONST)
3751 if (GET_CODE (XEXP (orig, 0)) == PLUS
3752 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3757 gcc_assert (can_create_pseudo_p ());
3758 reg = gen_reg_rtx (Pmode);
3761 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3762 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3763 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3764 base == reg ? NULL_RTX : reg);
3766 if (GET_CODE (offset) == CONST_INT)
3768 if (SMALL_INT (offset))
3769 return plus_constant (base, INTVAL (offset));
3770 else if (can_create_pseudo_p ())
3771 offset = force_reg (Pmode, offset);
3773 /* If we reach here, then something is seriously wrong. */
3776 return gen_rtx_PLUS (Pmode, base, offset);
3778 else if (GET_CODE (orig) == LABEL_REF)
3779 /* ??? We ought to be checking that the register is live instead, in case
3780 it is eliminated. */
3781 crtl->uses_pic_offset_table = 1;
3786 /* Try machine-dependent ways of modifying an illegitimate address X
3787 to be legitimate. If we find one, return the new, valid address.
3789 OLDX is the address as it was before break_out_memory_refs was called.
3790 In some cases it is useful to look at this to decide what needs to be done.
3792 MODE is the mode of the operand pointed to by X.
3794 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3797 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3798 enum machine_mode mode)
3802 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3803 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3804 force_operand (XEXP (x, 0), NULL_RTX));
3805 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3806 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3807 force_operand (XEXP (x, 1), NULL_RTX));
3808 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3809 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3811 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3812 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3813 force_operand (XEXP (x, 1), NULL_RTX));
3815 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
3818 if (sparc_tls_referenced_p (x))
3819 x = sparc_legitimize_tls_address (x);
3821 x = sparc_legitimize_pic_address (x, NULL_RTX);
3822 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3823 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3824 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3825 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3826 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3827 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3828 else if (GET_CODE (x) == SYMBOL_REF
3829 || GET_CODE (x) == CONST
3830 || GET_CODE (x) == LABEL_REF)
3831 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3836 /* Delegitimize an address that was legitimized by the above function. */
3839 sparc_delegitimize_address (rtx x)
3841 x = delegitimize_mem_from_attrs (x);
3843 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
3844 switch (XINT (XEXP (x, 1), 1))
3846 case UNSPEC_MOVE_PIC:
3848 x = XVECEXP (XEXP (x, 1), 0, 0);
3849 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3855 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3856 if (GET_CODE (x) == MINUS
3857 && REG_P (XEXP (x, 0))
3858 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3859 && GET_CODE (XEXP (x, 1)) == LO_SUM
3860 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3861 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3863 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3864 gcc_assert (GET_CODE (x) == LABEL_REF);
3870 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3871 replace the input X, or the original X if no replacement is called for.
3872 The output parameter *WIN is 1 if the calling macro should goto WIN,
3875 For SPARC, we wish to handle addresses by splitting them into
3876 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3877 This cuts the number of extra insns by one.
3879 Do nothing when generating PIC code and the address is a symbolic
3880 operand or requires a scratch register. */
3883 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3884 int opnum, int type,
3885 int ind_levels ATTRIBUTE_UNUSED, int *win)
3887 /* Decompose SImode constants into HIGH+LO_SUM. */
3889 && (mode != TFmode || TARGET_ARCH64)
3890 && GET_MODE (x) == SImode
3891 && GET_CODE (x) != LO_SUM
3892 && GET_CODE (x) != HIGH
3893 && sparc_cmodel <= CM_MEDLOW
3895 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3897 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3898 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3899 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3900 opnum, (enum reload_type)type);
3905 /* We have to recognize what we have already generated above. */
3906 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3908 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3909 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3910 opnum, (enum reload_type)type);
3919 /* Return true if ADDR (a legitimate address expression)
3920 has an effect that depends on the machine mode it is used for.
3926 is not equivalent to
3928 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3930 because [%l7+a+1] is interpreted as the address of (a+1). */
3934 sparc_mode_dependent_address_p (const_rtx addr)
3936 if (flag_pic && GET_CODE (addr) == PLUS)
3938 rtx op0 = XEXP (addr, 0);
3939 rtx op1 = XEXP (addr, 1);
3940 if (op0 == pic_offset_table_rtx
3941 && symbolic_operand (op1, VOIDmode))
3948 #ifdef HAVE_GAS_HIDDEN
3949 # define USE_HIDDEN_LINKONCE 1
3951 # define USE_HIDDEN_LINKONCE 0
3955 get_pc_thunk_name (char name[32], unsigned int regno)
3957 const char *reg_name = reg_names[regno];
3959 /* Skip the leading '%' as that cannot be used in a
3963 if (USE_HIDDEN_LINKONCE)
3964 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
3966 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
3969 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3972 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
3974 int orig_flag_pic = flag_pic;
3977 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3980 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
3982 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
3983 flag_pic = orig_flag_pic;
3988 /* Emit code to load the GOT register. */
3991 load_got_register (void)
3993 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3994 if (!global_offset_table_rtx)
3995 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
3997 if (TARGET_VXWORKS_RTP)
3998 emit_insn (gen_vxworks_load_got ());
4001 /* The GOT symbol is subject to a PC-relative relocation so we need a
4002 helper function to add the PC value and thus get the final value. */
4003 if (!got_helper_rtx)
4006 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
4007 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4010 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
4012 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
4015 /* Need to emit this whether or not we obey regdecls,
4016 since setjmp/longjmp can cause life info to screw up.
4017 ??? In the case where we don't obey regdecls, this is not sufficient
4018 since we may not fall out the bottom. */
4019 emit_use (global_offset_table_rtx);
4022 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4023 address of the call target. */
4026 sparc_emit_call_insn (rtx pat, rtx addr)
4030 insn = emit_call_insn (pat);
4032 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4033 if (TARGET_VXWORKS_RTP
4035 && GET_CODE (addr) == SYMBOL_REF
4036 && (SYMBOL_REF_DECL (addr)
4037 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
4038 : !SYMBOL_REF_LOCAL_P (addr)))
4040 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4041 crtl->uses_pic_offset_table = 1;
4045 /* Return 1 if RTX is a MEM which is known to be aligned to at
4046 least a DESIRED byte boundary. */
4049 mem_min_alignment (rtx mem, int desired)
4051 rtx addr, base, offset;
4053 /* If it's not a MEM we can't accept it. */
4054 if (GET_CODE (mem) != MEM)
4058 if (!TARGET_UNALIGNED_DOUBLES
4059 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4062 /* ??? The rest of the function predates MEM_ALIGN so
4063 there is probably a bit of redundancy. */
4064 addr = XEXP (mem, 0);
4065 base = offset = NULL_RTX;
4066 if (GET_CODE (addr) == PLUS)
4068 if (GET_CODE (XEXP (addr, 0)) == REG)
4070 base = XEXP (addr, 0);
4072 /* What we are saying here is that if the base
4073 REG is aligned properly, the compiler will make
4074 sure any REG based index upon it will be so
4076 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4077 offset = XEXP (addr, 1);
4079 offset = const0_rtx;
4082 else if (GET_CODE (addr) == REG)
4085 offset = const0_rtx;
4088 if (base != NULL_RTX)
4090 int regno = REGNO (base);
4092 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4094 /* Check if the compiler has recorded some information
4095 about the alignment of the base REG. If reload has
4096 completed, we already matched with proper alignments.
4097 If not running global_alloc, reload might give us
4098 unaligned pointer to local stack though. */
4100 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4101 || (optimize && reload_completed))
4102 && (INTVAL (offset) & (desired - 1)) == 0)
4107 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4111 else if (! TARGET_UNALIGNED_DOUBLES
4112 || CONSTANT_P (addr)
4113 || GET_CODE (addr) == LO_SUM)
4115 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4116 is true, in which case we can only assume that an access is aligned if
4117 it is to a constant address, or the address involves a LO_SUM. */
4121 /* An obviously unaligned address. */
4126 /* Vectors to keep interesting information about registers where it can easily
4127 be got. We used to use the actual mode value as the bit number, but there
4128 are more than 32 modes now. Instead we use two tables: one indexed by
4129 hard register number, and one indexed by mode. */
4131 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4132 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4133 mapped into one sparc_mode_class mode. */
4135 enum sparc_mode_class {
4136 S_MODE, D_MODE, T_MODE, O_MODE,
4137 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4141 /* Modes for single-word and smaller quantities. */
4142 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4144 /* Modes for double-word and smaller quantities. */
4145 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4147 /* Modes for quad-word and smaller quantities. */
4148 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4150 /* Modes for 8-word and smaller quantities. */
4151 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4153 /* Modes for single-float quantities. We must allow any single word or
4154 smaller quantity. This is because the fix/float conversion instructions
4155 take integer inputs/outputs from the float registers. */
4156 #define SF_MODES (S_MODES)
4158 /* Modes for double-float and smaller quantities. */
4159 #define DF_MODES (D_MODES)
4161 /* Modes for quad-float and smaller quantities. */
4162 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4164 /* Modes for quad-float pairs and smaller quantities. */
4165 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4167 /* Modes for double-float only quantities. */
4168 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4170 /* Modes for quad-float and double-float only quantities. */
4171 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4173 /* Modes for quad-float pairs and double-float only quantities. */
4174 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4176 /* Modes for condition codes. */
4177 #define CC_MODES (1 << (int) CC_MODE)
4178 #define CCFP_MODES (1 << (int) CCFP_MODE)
4180 /* Value is 1 if register/mode pair is acceptable on sparc.
4181 The funny mixture of D and T modes is because integer operations
4182 do not specially operate on tetra quantities, so non-quad-aligned
4183 registers can hold quadword quantities (except %o4 and %i4 because
4184 they cross fixed registers). */
4186 /* This points to either the 32 bit or the 64 bit version. */
4187 const int *hard_regno_mode_classes;
4189 static const int hard_32bit_mode_classes[] = {
4190 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4191 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4192 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4193 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4195 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4196 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4197 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4198 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4200 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4201 and none can hold SFmode/SImode values. */
4202 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4203 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4204 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4205 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4208 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4210 /* %icc, %sfp, %gsr */
4211 CC_MODES, 0, D_MODES
4214 static const int hard_64bit_mode_classes[] = {
4215 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4216 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4217 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4218 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4220 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4221 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4222 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4223 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4225 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4226 and none can hold SFmode/SImode values. */
4227 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4228 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4229 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4230 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4233 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4235 /* %icc, %sfp, %gsr */
4236 CC_MODES, 0, D_MODES
4239 int sparc_mode_class [NUM_MACHINE_MODES];
4241 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4244 sparc_init_modes (void)
4248 for (i = 0; i < NUM_MACHINE_MODES; i++)
4250 switch (GET_MODE_CLASS (i))
4253 case MODE_PARTIAL_INT:
4254 case MODE_COMPLEX_INT:
4255 if (GET_MODE_SIZE (i) <= 4)
4256 sparc_mode_class[i] = 1 << (int) S_MODE;
4257 else if (GET_MODE_SIZE (i) == 8)
4258 sparc_mode_class[i] = 1 << (int) D_MODE;
4259 else if (GET_MODE_SIZE (i) == 16)
4260 sparc_mode_class[i] = 1 << (int) T_MODE;
4261 else if (GET_MODE_SIZE (i) == 32)
4262 sparc_mode_class[i] = 1 << (int) O_MODE;
4264 sparc_mode_class[i] = 0;
4266 case MODE_VECTOR_INT:
4267 if (GET_MODE_SIZE (i) <= 4)
4268 sparc_mode_class[i] = 1 << (int)SF_MODE;
4269 else if (GET_MODE_SIZE (i) == 8)
4270 sparc_mode_class[i] = 1 << (int)DF_MODE;
4273 case MODE_COMPLEX_FLOAT:
4274 if (GET_MODE_SIZE (i) <= 4)
4275 sparc_mode_class[i] = 1 << (int) SF_MODE;
4276 else if (GET_MODE_SIZE (i) == 8)
4277 sparc_mode_class[i] = 1 << (int) DF_MODE;
4278 else if (GET_MODE_SIZE (i) == 16)
4279 sparc_mode_class[i] = 1 << (int) TF_MODE;
4280 else if (GET_MODE_SIZE (i) == 32)
4281 sparc_mode_class[i] = 1 << (int) OF_MODE;
4283 sparc_mode_class[i] = 0;
4286 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4287 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4289 sparc_mode_class[i] = 1 << (int) CC_MODE;
4292 sparc_mode_class[i] = 0;
4298 hard_regno_mode_classes = hard_64bit_mode_classes;
4300 hard_regno_mode_classes = hard_32bit_mode_classes;
4302 /* Initialize the array used by REGNO_REG_CLASS. */
4303 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4305 if (i < 16 && TARGET_V8PLUS)
4306 sparc_regno_reg_class[i] = I64_REGS;
4307 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4308 sparc_regno_reg_class[i] = GENERAL_REGS;
4310 sparc_regno_reg_class[i] = FP_REGS;
4312 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4314 sparc_regno_reg_class[i] = FPCC_REGS;
4316 sparc_regno_reg_class[i] = NO_REGS;
4320 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4323 save_global_or_fp_reg_p (unsigned int regno,
4324 int leaf_function ATTRIBUTE_UNUSED)
4326 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4329 /* Return whether the return address register (%i7) is needed. */
4332 return_addr_reg_needed_p (int leaf_function)
4334 /* If it is live, for example because of __builtin_return_address (0). */
4335 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4338 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4340 /* Loading the GOT register clobbers %o7. */
4341 || crtl->uses_pic_offset_table
4342 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4348 /* Return whether REGNO, a local or in register, must be saved/restored. */
4351 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4353 /* General case: call-saved registers live at some point. */
4354 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4357 /* Frame pointer register (%fp) if needed. */
4358 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4361 /* Return address register (%i7) if needed. */
4362 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4365 /* GOT register (%l7) if needed. */
4366 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4369 /* If the function accesses prior frames, the frame pointer and the return
4370 address of the previous frame must be saved on the stack. */
4371 if (crtl->accesses_prior_frames
4372 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4378 /* Compute the frame size required by the function. This function is called
4379 during the reload pass and also by sparc_expand_prologue. */
4382 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4384 HOST_WIDE_INT frame_size, apparent_frame_size;
4385 int args_size, n_global_fp_regs = 0;
4386 bool save_local_in_regs_p = false;
4389 /* If the function allocates dynamic stack space, the dynamic offset is
4390 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4391 if (leaf_function && !cfun->calls_alloca)
4394 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4396 /* Calculate space needed for global registers. */
4398 for (i = 0; i < 8; i++)
4399 if (save_global_or_fp_reg_p (i, 0))
4400 n_global_fp_regs += 2;
4402 for (i = 0; i < 8; i += 2)
4403 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4404 n_global_fp_regs += 2;
4406 /* In the flat window model, find out which local and in registers need to
4407 be saved. We don't reserve space in the current frame for them as they
4408 will be spilled into the register window save area of the caller's frame.
4409 However, as soon as we use this register window save area, we must create
4410 that of the current frame to make it the live one. */
4412 for (i = 16; i < 32; i++)
4413 if (save_local_or_in_reg_p (i, leaf_function))
4415 save_local_in_regs_p = true;
4419 /* Calculate space needed for FP registers. */
4420 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4421 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4422 n_global_fp_regs += 2;
4425 && n_global_fp_regs == 0
4427 && !save_local_in_regs_p)
4428 frame_size = apparent_frame_size = 0;
4431 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4432 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
4433 apparent_frame_size += n_global_fp_regs * 4;
4435 /* We need to add the size of the outgoing argument area. */
4436 frame_size = apparent_frame_size + ((args_size + 7) & -8);
4438 /* And that of the register window save area. */
4439 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4441 /* Finally, bump to the appropriate alignment. */
4442 frame_size = SPARC_STACK_ALIGN (frame_size);
4445 /* Set up values for use in prologue and epilogue. */
4446 sparc_frame_size = frame_size;
4447 sparc_apparent_frame_size = apparent_frame_size;
4448 sparc_n_global_fp_regs = n_global_fp_regs;
4449 sparc_save_local_in_regs_p = save_local_in_regs_p;
4454 /* Output any necessary .register pseudo-ops. */
4457 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4459 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4465 /* Check if %g[2367] were used without
4466 .register being printed for them already. */
4467 for (i = 2; i < 8; i++)
4469 if (df_regs_ever_live_p (i)
4470 && ! sparc_hard_reg_printed [i])
4472 sparc_hard_reg_printed [i] = 1;
4473 /* %g7 is used as TLS base register, use #ignore
4474 for it instead of #scratch. */
4475 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4476 i == 7 ? "ignore" : "scratch");
4483 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4485 #if PROBE_INTERVAL > 4096
4486 #error Cannot use indexed addressing mode for stack probing
4489 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4490 inclusive. These are offsets from the current stack pointer.
4492 Note that we don't use the REG+REG addressing mode for the probes because
4493 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4494 so the advantages of having a single code win here. */
4497 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4499 rtx g1 = gen_rtx_REG (Pmode, 1);
4501 /* See if we have a constant small number of probes to generate. If so,
4502 that's the easy case. */
4503 if (size <= PROBE_INTERVAL)
4505 emit_move_insn (g1, GEN_INT (first));
4506 emit_insn (gen_rtx_SET (VOIDmode, g1,
4507 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4508 emit_stack_probe (plus_constant (g1, -size));
4511 /* The run-time loop is made up of 10 insns in the generic case while the
4512 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4513 else if (size <= 5 * PROBE_INTERVAL)
4517 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4518 emit_insn (gen_rtx_SET (VOIDmode, g1,
4519 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4520 emit_stack_probe (g1);
4522 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4523 it exceeds SIZE. If only two probes are needed, this will not
4524 generate any code. Then probe at FIRST + SIZE. */
4525 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4527 emit_insn (gen_rtx_SET (VOIDmode, g1,
4528 plus_constant (g1, -PROBE_INTERVAL)));
4529 emit_stack_probe (g1);
4532 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4535 /* Otherwise, do the same as above, but in a loop. Note that we must be
4536 extra careful with variables wrapping around because we might be at
4537 the very top (or the very bottom) of the address space and we have
4538 to be able to handle this case properly; in particular, we use an
4539 equality test for the loop condition. */
4542 HOST_WIDE_INT rounded_size;
4543 rtx g4 = gen_rtx_REG (Pmode, 4);
4545 emit_move_insn (g1, GEN_INT (first));
4548 /* Step 1: round SIZE to the previous multiple of the interval. */
4550 rounded_size = size & -PROBE_INTERVAL;
4551 emit_move_insn (g4, GEN_INT (rounded_size));
4554 /* Step 2: compute initial and final value of the loop counter. */
4556 /* TEST_ADDR = SP + FIRST. */
4557 emit_insn (gen_rtx_SET (VOIDmode, g1,
4558 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4560 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4561 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4566 while (TEST_ADDR != LAST_ADDR)
4568 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4572 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4573 until it is equal to ROUNDED_SIZE. */
4576 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4578 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4581 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4582 that SIZE is equal to ROUNDED_SIZE. */
4584 if (size != rounded_size)
4585 emit_stack_probe (plus_constant (g4, rounded_size - size));
4588 /* Make sure nothing is scheduled before we are done. */
4589 emit_insn (gen_blockage ());
4592 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4593 absolute addresses. */
4596 output_probe_stack_range (rtx reg1, rtx reg2)
4598 static int labelno = 0;
4599 char loop_lab[32], end_lab[32];
4602 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4603 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4605 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4607 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4610 output_asm_insn ("cmp\t%0, %1", xops);
4612 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4614 fputs ("\tbe\t", asm_out_file);
4615 assemble_name_raw (asm_out_file, end_lab);
4616 fputc ('\n', asm_out_file);
4618 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4619 xops[1] = GEN_INT (-PROBE_INTERVAL);
4620 output_asm_insn (" add\t%0, %1, %0", xops);
4622 /* Probe at TEST_ADDR and branch. */
4624 fputs ("\tba,pt\t%xcc,", asm_out_file);
4626 fputs ("\tba\t", asm_out_file);
4627 assemble_name_raw (asm_out_file, loop_lab);
4628 fputc ('\n', asm_out_file);
4629 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4630 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4632 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4637 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4638 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4639 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4640 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4641 the action to be performed if it returns false. Return the new offset. */
4643 typedef bool (*sorr_pred_t) (unsigned int, int);
4644 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
4647 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
4648 int offset, int leaf_function, sorr_pred_t save_p,
4649 sorr_act_t action_true, sorr_act_t action_false)
4654 if (TARGET_ARCH64 && high <= 32)
4658 for (i = low; i < high; i++)
4660 if (save_p (i, leaf_function))
4662 mem = gen_frame_mem (DImode, plus_constant (base, offset));
4663 if (action_true == SORR_SAVE)
4665 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4666 RTX_FRAME_RELATED_P (insn) = 1;
4668 else /* action_true == SORR_RESTORE */
4670 /* The frame pointer must be restored last since its old
4671 value may be used as base address for the frame. This
4672 is problematic in 64-bit mode only because of the lack
4673 of double-word load instruction. */
4674 if (i == HARD_FRAME_POINTER_REGNUM)
4677 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4681 else if (action_false == SORR_ADVANCE)
4687 mem = gen_frame_mem (DImode, plus_constant (base, fp_offset));
4688 emit_move_insn (hard_frame_pointer_rtx, mem);
4693 for (i = low; i < high; i += 2)
4695 bool reg0 = save_p (i, leaf_function);
4696 bool reg1 = save_p (i + 1, leaf_function);
4697 enum machine_mode mode;
4702 mode = i < 32 ? DImode : DFmode;
4707 mode = i < 32 ? SImode : SFmode;
4712 mode = i < 32 ? SImode : SFmode;
4718 if (action_false == SORR_ADVANCE)
4723 mem = gen_frame_mem (mode, plus_constant (base, offset));
4724 if (action_true == SORR_SAVE)
4726 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4727 RTX_FRAME_RELATED_P (insn) = 1;
4731 mem = gen_frame_mem (SImode, plus_constant (base, offset));
4732 set1 = gen_rtx_SET (VOIDmode, mem,
4733 gen_rtx_REG (SImode, regno));
4734 RTX_FRAME_RELATED_P (set1) = 1;
4736 = gen_frame_mem (SImode, plus_constant (base, offset + 4));
4737 set2 = gen_rtx_SET (VOIDmode, mem,
4738 gen_rtx_REG (SImode, regno + 1));
4739 RTX_FRAME_RELATED_P (set2) = 1;
4740 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4741 gen_rtx_PARALLEL (VOIDmode,
4742 gen_rtvec (2, set1, set2)));
4745 else /* action_true == SORR_RESTORE */
4746 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4748 /* Always preserve double-word alignment. */
4749 offset = (offset + 8) & -8;
4756 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4759 emit_adjust_base_to_offset (rtx base, int offset)
4761 /* ??? This might be optimized a little as %g1 might already have a
4762 value close enough that a single add insn will do. */
4763 /* ??? Although, all of this is probably only a temporary fix because
4764 if %g1 can hold a function result, then sparc_expand_epilogue will
4765 lose (the result will be clobbered). */
4766 rtx new_base = gen_rtx_REG (Pmode, 1);
4767 emit_move_insn (new_base, GEN_INT (offset));
4768 emit_insn (gen_rtx_SET (VOIDmode,
4769 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
4773 /* Emit code to save/restore call-saved global and FP registers. */
4776 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
4778 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
4780 base = emit_adjust_base_to_offset (base, offset);
4785 = emit_save_or_restore_regs (0, 8, base, offset, 0,
4786 save_global_or_fp_reg_p, action, SORR_NONE);
4787 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
4788 save_global_or_fp_reg_p, action, SORR_NONE);
4791 /* Emit code to save/restore call-saved local and in registers. */
4794 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
4796 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
4798 base = emit_adjust_base_to_offset (base, offset);
4802 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
4803 save_local_or_in_reg_p, action, SORR_ADVANCE);
4806 /* Emit a window_save insn. */
4809 emit_window_save (rtx increment)
4811 rtx insn = emit_insn (gen_window_save (increment));
4812 RTX_FRAME_RELATED_P (insn) = 1;
4814 /* The incoming return address (%o7) is saved in %i7. */
4815 add_reg_note (insn, REG_CFA_REGISTER,
4816 gen_rtx_SET (VOIDmode,
4817 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
4819 INCOMING_RETURN_ADDR_REGNUM)));
4821 /* The window save event. */
4822 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
4824 /* The CFA is %fp, the hard frame pointer. */
4825 add_reg_note (insn, REG_CFA_DEF_CFA,
4826 plus_constant (hard_frame_pointer_rtx,
4827 INCOMING_FRAME_SP_OFFSET));
4832 /* Generate an increment for the stack pointer. */
4835 gen_stack_pointer_inc (rtx increment)
4837 return gen_rtx_SET (VOIDmode,
4839 gen_rtx_PLUS (Pmode,
4844 /* Generate a decrement for the stack pointer. */
4847 gen_stack_pointer_dec (rtx decrement)
4849 return gen_rtx_SET (VOIDmode,
4851 gen_rtx_MINUS (Pmode,
4856 /* Expand the function prologue. The prologue is responsible for reserving
4857 storage for the frame, saving the call-saved registers and loading the
4858 GOT register if needed. */
4861 sparc_expand_prologue (void)
4866 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4867 on the final value of the flag means deferring the prologue/epilogue
4868 expansion until just before the second scheduling pass, which is too
4869 late to emit multiple epilogues or return insns.
4871 Of course we are making the assumption that the value of the flag
4872 will not change between now and its final value. Of the three parts
4873 of the formula, only the last one can reasonably vary. Let's take a
4874 closer look, after assuming that the first two ones are set to true
4875 (otherwise the last value is effectively silenced).
4877 If only_leaf_regs_used returns false, the global predicate will also
4878 be false so the actual frame size calculated below will be positive.
4879 As a consequence, the save_register_window insn will be emitted in
4880 the instruction stream; now this insn explicitly references %fp
4881 which is not a leaf register so only_leaf_regs_used will always
4882 return false subsequently.
4884 If only_leaf_regs_used returns true, we hope that the subsequent
4885 optimization passes won't cause non-leaf registers to pop up. For
4886 example, the regrename pass has special provisions to not rename to
4887 non-leaf registers in a leaf function. */
4888 sparc_leaf_function_p
4889 = optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
4891 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4893 if (flag_stack_usage_info)
4894 current_function_static_stack_size = size;
4896 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4897 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4901 else if (sparc_leaf_function_p)
4903 rtx size_int_rtx = GEN_INT (-size);
4906 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
4907 else if (size <= 8192)
4909 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4910 /* %sp is still the CFA register. */
4911 RTX_FRAME_RELATED_P (insn) = 1;
4912 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4916 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4917 emit_move_insn (size_rtx, size_int_rtx);
4918 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
4919 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4920 gen_stack_pointer_inc (size_int_rtx));
4923 RTX_FRAME_RELATED_P (insn) = 1;
4927 rtx size_int_rtx = GEN_INT (-size);
4930 emit_window_save (size_int_rtx);
4931 else if (size <= 8192)
4933 emit_window_save (GEN_INT (-4096));
4934 /* %sp is not the CFA register anymore. */
4935 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4939 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4940 emit_move_insn (size_rtx, size_int_rtx);
4941 emit_window_save (size_rtx);
4945 if (sparc_leaf_function_p)
4947 sparc_frame_base_reg = stack_pointer_rtx;
4948 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
4952 sparc_frame_base_reg = hard_frame_pointer_rtx;
4953 sparc_frame_base_offset = SPARC_STACK_BIAS;
4956 if (sparc_n_global_fp_regs > 0)
4957 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
4958 sparc_frame_base_offset
4959 - sparc_apparent_frame_size,
4962 /* Load the GOT register if needed. */
4963 if (crtl->uses_pic_offset_table)
4964 load_got_register ();
4966 /* Advertise that the data calculated just above are now valid. */
4967 sparc_prologue_data_valid_p = true;
4970 /* Expand the function prologue. The prologue is responsible for reserving
4971 storage for the frame, saving the call-saved registers and loading the
4972 GOT register if needed. */
4975 sparc_flat_expand_prologue (void)
4980 sparc_leaf_function_p = optimize > 0 && current_function_is_leaf;
4982 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4984 if (flag_stack_usage_info)
4985 current_function_static_stack_size = size;
4987 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4988 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4990 if (sparc_save_local_in_regs_p)
4991 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
4998 rtx size_int_rtx, size_rtx;
5000 size_rtx = size_int_rtx = GEN_INT (-size);
5002 /* We establish the frame (i.e. decrement the stack pointer) first, even
5003 if we use a frame pointer, because we cannot clobber any call-saved
5004 registers, including the frame pointer, if we haven't created a new
5005 register save area, for the sake of compatibility with the ABI. */
5007 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5008 else if (size <= 8192 && !frame_pointer_needed)
5010 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5011 RTX_FRAME_RELATED_P (insn) = 1;
5012 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5016 size_rtx = gen_rtx_REG (Pmode, 1);
5017 emit_move_insn (size_rtx, size_int_rtx);
5018 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5019 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5020 gen_stack_pointer_inc (size_int_rtx));
5022 RTX_FRAME_RELATED_P (insn) = 1;
5024 /* Ensure nothing is scheduled until after the frame is established. */
5025 emit_insn (gen_blockage ());
5027 if (frame_pointer_needed)
5029 insn = emit_insn (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5030 gen_rtx_MINUS (Pmode,
5033 RTX_FRAME_RELATED_P (insn) = 1;
5035 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5036 gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5037 plus_constant (stack_pointer_rtx,
5041 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5043 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
5044 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
5046 insn = emit_move_insn (i7, o7);
5047 RTX_FRAME_RELATED_P (insn) = 1;
5049 add_reg_note (insn, REG_CFA_REGISTER,
5050 gen_rtx_SET (VOIDmode, i7, o7));
5052 /* Prevent this instruction from ever being considered dead,
5053 even if this function has no epilogue. */
5054 emit_insn (gen_rtx_USE (VOIDmode, i7));
5058 if (frame_pointer_needed)
5060 sparc_frame_base_reg = hard_frame_pointer_rtx;
5061 sparc_frame_base_offset = SPARC_STACK_BIAS;
5065 sparc_frame_base_reg = stack_pointer_rtx;
5066 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5069 if (sparc_n_global_fp_regs > 0)
5070 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5071 sparc_frame_base_offset
5072 - sparc_apparent_frame_size,
5075 /* Load the GOT register if needed. */
5076 if (crtl->uses_pic_offset_table)
5077 load_got_register ();
5079 /* Advertise that the data calculated just above are now valid. */
5080 sparc_prologue_data_valid_p = true;
5083 /* This function generates the assembly code for function entry, which boils
5084 down to emitting the necessary .register directives. */
5087 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5089 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5091 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
5093 sparc_output_scratch_registers (file);
5096 /* Expand the function epilogue, either normal or part of a sibcall.
5097 We emit all the instructions except the return or the call. */
5100 sparc_expand_epilogue (bool for_eh)
5102 HOST_WIDE_INT size = sparc_frame_size;
5104 if (sparc_n_global_fp_regs > 0)
5105 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5106 sparc_frame_base_offset
5107 - sparc_apparent_frame_size,
5110 if (size == 0 || for_eh)
5112 else if (sparc_leaf_function_p)
5115 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5116 else if (size <= 8192)
5118 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5119 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5123 rtx reg = gen_rtx_REG (Pmode, 1);
5124 emit_move_insn (reg, GEN_INT (-size));
5125 emit_insn (gen_stack_pointer_dec (reg));
5130 /* Expand the function epilogue, either normal or part of a sibcall.
5131 We emit all the instructions except the return or the call. */
5134 sparc_flat_expand_epilogue (bool for_eh)
5136 HOST_WIDE_INT size = sparc_frame_size;
5138 if (sparc_n_global_fp_regs > 0)
5139 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5140 sparc_frame_base_offset
5141 - sparc_apparent_frame_size,
5144 /* If we have a frame pointer, we'll need both to restore it before the
5145 frame is destroyed and use its current value in destroying the frame.
5146 Since we don't have an atomic way to do that in the flat window model,
5147 we save the current value into a temporary register (%g1). */
5148 if (frame_pointer_needed && !for_eh)
5149 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
5151 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5152 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5153 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5155 if (sparc_save_local_in_regs_p)
5156 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5157 sparc_frame_base_offset,
5160 if (size == 0 || for_eh)
5162 else if (frame_pointer_needed)
5164 /* Make sure the frame is destroyed after everything else is done. */
5165 emit_insn (gen_blockage ());
5167 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5172 emit_insn (gen_blockage ());
5175 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5176 else if (size <= 8192)
5178 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5179 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5183 rtx reg = gen_rtx_REG (Pmode, 1);
5184 emit_move_insn (reg, GEN_INT (-size));
5185 emit_insn (gen_stack_pointer_dec (reg));
5190 /* Return true if it is appropriate to emit `return' instructions in the
5191 body of a function. */
5194 sparc_can_use_return_insn_p (void)
5196 return sparc_prologue_data_valid_p
5197 && sparc_n_global_fp_regs == 0
5199 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5200 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5203 /* This function generates the assembly code for function exit. */
5206 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5208 /* If the last two instructions of a function are "call foo; dslot;"
5209 the return address might point to the first instruction in the next
5210 function and we have to output a dummy nop for the sake of sane
5211 backtraces in such cases. This is pointless for sibling calls since
5212 the return address is explicitly adjusted. */
5214 rtx insn, last_real_insn;
5216 insn = get_last_insn ();
5218 last_real_insn = prev_real_insn (insn);
5220 && GET_CODE (last_real_insn) == INSN
5221 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5222 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5225 && CALL_P (last_real_insn)
5226 && !SIBLING_CALL_P (last_real_insn))
5227 fputs("\tnop\n", file);
5229 sparc_output_deferred_case_vectors ();
5232 /* Output a 'restore' instruction. */
5235 output_restore (rtx pat)
5241 fputs ("\t restore\n", asm_out_file);
5245 gcc_assert (GET_CODE (pat) == SET);
5247 operands[0] = SET_DEST (pat);
5248 pat = SET_SRC (pat);
5250 switch (GET_CODE (pat))
5253 operands[1] = XEXP (pat, 0);
5254 operands[2] = XEXP (pat, 1);
5255 output_asm_insn (" restore %r1, %2, %Y0", operands);
5258 operands[1] = XEXP (pat, 0);
5259 operands[2] = XEXP (pat, 1);
5260 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5263 operands[1] = XEXP (pat, 0);
5264 gcc_assert (XEXP (pat, 1) == const1_rtx);
5265 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5269 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5274 /* Output a return. */
5277 output_return (rtx insn)
5279 if (crtl->calls_eh_return)
5281 /* If the function uses __builtin_eh_return, the eh_return
5282 machinery occupies the delay slot. */
5283 gcc_assert (!final_sequence);
5285 if (flag_delayed_branch)
5287 if (!TARGET_FLAT && TARGET_V9)
5288 fputs ("\treturn\t%i7+8\n", asm_out_file);
5292 fputs ("\trestore\n", asm_out_file);
5294 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5297 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5302 fputs ("\trestore\n", asm_out_file);
5304 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5305 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5308 else if (sparc_leaf_function_p || TARGET_FLAT)
5310 /* This is a leaf or flat function so we don't have to bother restoring
5311 the register window, which frees us from dealing with the convoluted
5312 semantics of restore/return. We simply output the jump to the
5313 return address and the insn in the delay slot (if any). */
5315 return "jmp\t%%o7+%)%#";
5319 /* This is a regular function so we have to restore the register window.
5320 We may have a pending insn for the delay slot, which will be either
5321 combined with the 'restore' instruction or put in the delay slot of
5322 the 'return' instruction. */
5328 delay = NEXT_INSN (insn);
5331 pat = PATTERN (delay);
5333 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5335 epilogue_renumber (&pat, 0);
5336 return "return\t%%i7+%)%#";
5340 output_asm_insn ("jmp\t%%i7+%)", NULL);
5341 output_restore (pat);
5342 PATTERN (delay) = gen_blockage ();
5343 INSN_CODE (delay) = -1;
5348 /* The delay slot is empty. */
5350 return "return\t%%i7+%)\n\t nop";
5351 else if (flag_delayed_branch)
5352 return "jmp\t%%i7+%)\n\t restore";
5354 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5361 /* Output a sibling call. */
5364 output_sibcall (rtx insn, rtx call_operand)
5368 gcc_assert (flag_delayed_branch);
5370 operands[0] = call_operand;
5372 if (sparc_leaf_function_p || TARGET_FLAT)
5374 /* This is a leaf or flat function so we don't have to bother restoring
5375 the register window. We simply output the jump to the function and
5376 the insn in the delay slot (if any). */
5378 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
5381 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5384 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5385 it into branch if possible. */
5386 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5391 /* This is a regular function so we have to restore the register window.
5392 We may have a pending insn for the delay slot, which will be combined
5393 with the 'restore' instruction. */
5395 output_asm_insn ("call\t%a0, 0", operands);
5399 rtx delay = NEXT_INSN (insn);
5402 output_restore (PATTERN (delay));
5404 PATTERN (delay) = gen_blockage ();
5405 INSN_CODE (delay) = -1;
5408 output_restore (NULL_RTX);
5414 /* Functions for handling argument passing.
5416 For 32-bit, the first 6 args are normally in registers and the rest are
5417 pushed. Any arg that starts within the first 6 words is at least
5418 partially passed in a register unless its data type forbids.
5420 For 64-bit, the argument registers are laid out as an array of 16 elements
5421 and arguments are added sequentially. The first 6 int args and up to the
5422 first 16 fp args (depending on size) are passed in regs.
5424 Slot Stack Integral Float Float in structure Double Long Double
5425 ---- ----- -------- ----- ------------------ ------ -----------
5426 15 [SP+248] %f31 %f30,%f31 %d30
5427 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5428 13 [SP+232] %f27 %f26,%f27 %d26
5429 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5430 11 [SP+216] %f23 %f22,%f23 %d22
5431 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5432 9 [SP+200] %f19 %f18,%f19 %d18
5433 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5434 7 [SP+184] %f15 %f14,%f15 %d14
5435 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5436 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5437 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5438 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5439 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5440 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5441 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5443 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5445 Integral arguments are always passed as 64-bit quantities appropriately
5448 Passing of floating point values is handled as follows.
5449 If a prototype is in scope:
5450 If the value is in a named argument (i.e. not a stdarg function or a
5451 value not part of the `...') then the value is passed in the appropriate
5453 If the value is part of the `...' and is passed in one of the first 6
5454 slots then the value is passed in the appropriate int reg.
5455 If the value is part of the `...' and is not passed in one of the first 6
5456 slots then the value is passed in memory.
5457 If a prototype is not in scope:
5458 If the value is one of the first 6 arguments the value is passed in the
5459 appropriate integer reg and the appropriate fp reg.
5460 If the value is not one of the first 6 arguments the value is passed in
5461 the appropriate fp reg and in memory.
5464 Summary of the calling conventions implemented by GCC on the SPARC:
5467 size argument return value
5469 small integer <4 int. reg. int. reg.
5470 word 4 int. reg. int. reg.
5471 double word 8 int. reg. int. reg.
5473 _Complex small integer <8 int. reg. int. reg.
5474 _Complex word 8 int. reg. int. reg.
5475 _Complex double word 16 memory int. reg.
5477 vector integer <=8 int. reg. FP reg.
5478 vector integer >8 memory memory
5480 float 4 int. reg. FP reg.
5481 double 8 int. reg. FP reg.
5482 long double 16 memory memory
5484 _Complex float 8 memory FP reg.
5485 _Complex double 16 memory FP reg.
5486 _Complex long double 32 memory FP reg.
5488 vector float any memory memory
5490 aggregate any memory memory
5495 size argument return value
5497 small integer <8 int. reg. int. reg.
5498 word 8 int. reg. int. reg.
5499 double word 16 int. reg. int. reg.
5501 _Complex small integer <16 int. reg. int. reg.
5502 _Complex word 16 int. reg. int. reg.
5503 _Complex double word 32 memory int. reg.
5505 vector integer <=16 FP reg. FP reg.
5506 vector integer 16<s<=32 memory FP reg.
5507 vector integer >32 memory memory
5509 float 4 FP reg. FP reg.
5510 double 8 FP reg. FP reg.
5511 long double 16 FP reg. FP reg.
5513 _Complex float 8 FP reg. FP reg.
5514 _Complex double 16 FP reg. FP reg.
5515 _Complex long double 32 memory FP reg.
5517 vector float <=16 FP reg. FP reg.
5518 vector float 16<s<=32 memory FP reg.
5519 vector float >32 memory memory
5521 aggregate <=16 reg. reg.
5522 aggregate 16<s<=32 memory reg.
5523 aggregate >32 memory memory
5527 Note #1: complex floating-point types follow the extended SPARC ABIs as
5528 implemented by the Sun compiler.
5530 Note #2: integral vector types follow the scalar floating-point types
5531 conventions to match what is implemented by the Sun VIS SDK.
5533 Note #3: floating-point vector types follow the aggregate types
5537 /* Maximum number of int regs for args. */
5538 #define SPARC_INT_ARG_MAX 6
5539 /* Maximum number of fp regs for args. */
5540 #define SPARC_FP_ARG_MAX 16
5542 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5544 /* Handle the INIT_CUMULATIVE_ARGS macro.
5545 Initialize a variable CUM of type CUMULATIVE_ARGS
5546 for a call to a function whose data type is FNTYPE.
5547 For a library call, FNTYPE is 0. */
5550 init_cumulative_args (struct sparc_args *cum, tree fntype,
5551 rtx libname ATTRIBUTE_UNUSED,
5552 tree fndecl ATTRIBUTE_UNUSED)
5555 cum->prototype_p = fntype && prototype_p (fntype);
5556 cum->libcall_p = fntype == 0;
5559 /* Handle promotion of pointer and integer arguments. */
5561 static enum machine_mode
5562 sparc_promote_function_mode (const_tree type,
5563 enum machine_mode mode,
5565 const_tree fntype ATTRIBUTE_UNUSED,
5566 int for_return ATTRIBUTE_UNUSED)
5568 if (type != NULL_TREE && POINTER_TYPE_P (type))
5570 *punsignedp = POINTERS_EXTEND_UNSIGNED;
5574 /* Integral arguments are passed as full words, as per the ABI. */
5575 if (GET_MODE_CLASS (mode) == MODE_INT
5576 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5582 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5585 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5587 return TARGET_ARCH64 ? true : false;
5590 /* Scan the record type TYPE and return the following predicates:
5591 - INTREGS_P: the record contains at least one field or sub-field
5592 that is eligible for promotion in integer registers.
5593 - FP_REGS_P: the record contains at least one field or sub-field
5594 that is eligible for promotion in floating-point registers.
5595 - PACKED_P: the record contains at least one field that is packed.
5597 Sub-fields are not taken into account for the PACKED_P predicate. */
5600 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5605 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5607 if (TREE_CODE (field) == FIELD_DECL)
5609 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5610 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5611 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5612 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5618 if (packed_p && DECL_PACKED (field))
5624 /* Compute the slot number to pass an argument in.
5625 Return the slot number or -1 if passing on the stack.
5627 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5628 the preceding args and about the function being called.
5629 MODE is the argument's machine mode.
5630 TYPE is the data type of the argument (as a tree).
5631 This is null for libcalls where that information may
5633 NAMED is nonzero if this argument is a named parameter
5634 (otherwise it is an extra parameter matching an ellipsis).
5635 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5636 *PREGNO records the register number to use if scalar type.
5637 *PPADDING records the amount of padding needed in words. */
5640 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5641 const_tree type, bool named, bool incoming_p,
5642 int *pregno, int *ppadding)
5644 int regbase = (incoming_p
5645 ? SPARC_INCOMING_INT_ARG_FIRST
5646 : SPARC_OUTGOING_INT_ARG_FIRST);
5647 int slotno = cum->words;
5648 enum mode_class mclass;
5653 if (type && TREE_ADDRESSABLE (type))
5659 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5662 /* For SPARC64, objects requiring 16-byte alignment get it. */
5664 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
5665 && (slotno & 1) != 0)
5666 slotno++, *ppadding = 1;
5668 mclass = GET_MODE_CLASS (mode);
5669 if (type && TREE_CODE (type) == VECTOR_TYPE)
5671 /* Vector types deserve special treatment because they are
5672 polymorphic wrt their mode, depending upon whether VIS
5673 instructions are enabled. */
5674 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5676 /* The SPARC port defines no floating-point vector modes. */
5677 gcc_assert (mode == BLKmode);
5681 /* Integral vector types should either have a vector
5682 mode or an integral mode, because we are guaranteed
5683 by pass_by_reference that their size is not greater
5684 than 16 bytes and TImode is 16-byte wide. */
5685 gcc_assert (mode != BLKmode);
5687 /* Vector integers are handled like floats according to
5689 mclass = MODE_FLOAT;
5696 case MODE_COMPLEX_FLOAT:
5697 case MODE_VECTOR_INT:
5698 if (TARGET_ARCH64 && TARGET_FPU && named)
5700 if (slotno >= SPARC_FP_ARG_MAX)
5702 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5703 /* Arguments filling only one single FP register are
5704 right-justified in the outer double FP register. */
5705 if (GET_MODE_SIZE (mode) <= 4)
5712 case MODE_COMPLEX_INT:
5713 if (slotno >= SPARC_INT_ARG_MAX)
5715 regno = regbase + slotno;
5719 if (mode == VOIDmode)
5720 /* MODE is VOIDmode when generating the actual call. */
5723 gcc_assert (mode == BLKmode);
5727 || (TREE_CODE (type) != VECTOR_TYPE
5728 && TREE_CODE (type) != RECORD_TYPE))
5730 if (slotno >= SPARC_INT_ARG_MAX)
5732 regno = regbase + slotno;
5734 else /* TARGET_ARCH64 && type */
5736 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5738 /* First see what kinds of registers we would need. */
5739 if (TREE_CODE (type) == VECTOR_TYPE)
5742 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5744 /* The ABI obviously doesn't specify how packed structures
5745 are passed. These are defined to be passed in int regs
5746 if possible, otherwise memory. */
5747 if (packed_p || !named)
5748 fpregs_p = 0, intregs_p = 1;
5750 /* If all arg slots are filled, then must pass on stack. */
5751 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5754 /* If there are only int args and all int arg slots are filled,
5755 then must pass on stack. */
5756 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5759 /* Note that even if all int arg slots are filled, fp members may
5760 still be passed in regs if such regs are available.
5761 *PREGNO isn't set because there may be more than one, it's up
5762 to the caller to compute them. */
5775 /* Handle recursive register counting for structure field layout. */
5777 struct function_arg_record_value_parms
5779 rtx ret; /* return expression being built. */
5780 int slotno; /* slot number of the argument. */
5781 int named; /* whether the argument is named. */
5782 int regbase; /* regno of the base register. */
5783 int stack; /* 1 if part of the argument is on the stack. */
5784 int intoffset; /* offset of the first pending integer field. */
5785 unsigned int nregs; /* number of words passed in registers. */
5788 static void function_arg_record_value_3
5789 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5790 static void function_arg_record_value_2
5791 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5792 static void function_arg_record_value_1
5793 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5794 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
5795 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5797 /* A subroutine of function_arg_record_value. Traverse the structure
5798 recursively and determine how many registers will be required. */
5801 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
5802 struct function_arg_record_value_parms *parms,
5807 /* We need to compute how many registers are needed so we can
5808 allocate the PARALLEL but before we can do that we need to know
5809 whether there are any packed fields. The ABI obviously doesn't
5810 specify how structures are passed in this case, so they are
5811 defined to be passed in int regs if possible, otherwise memory,
5812 regardless of whether there are fp values present. */
5815 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5817 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5824 /* Compute how many registers we need. */
5825 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5827 if (TREE_CODE (field) == FIELD_DECL)
5829 HOST_WIDE_INT bitpos = startbitpos;
5831 if (DECL_SIZE (field) != 0)
5833 if (integer_zerop (DECL_SIZE (field)))
5836 if (host_integerp (bit_position (field), 1))
5837 bitpos += int_bit_position (field);
5840 /* ??? FIXME: else assume zero offset. */
5842 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5843 function_arg_record_value_1 (TREE_TYPE (field),
5847 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5848 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5853 if (parms->intoffset != -1)
5855 unsigned int startbit, endbit;
5856 int intslots, this_slotno;
5858 startbit = parms->intoffset & -BITS_PER_WORD;
5859 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5861 intslots = (endbit - startbit) / BITS_PER_WORD;
5862 this_slotno = parms->slotno + parms->intoffset
5865 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5867 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5868 /* We need to pass this field on the stack. */
5872 parms->nregs += intslots;
5873 parms->intoffset = -1;
5876 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5877 If it wasn't true we wouldn't be here. */
5878 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5879 && DECL_MODE (field) == BLKmode)
5880 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5881 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5888 if (parms->intoffset == -1)
5889 parms->intoffset = bitpos;
5895 /* A subroutine of function_arg_record_value. Assign the bits of the
5896 structure between parms->intoffset and bitpos to integer registers. */
5899 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5900 struct function_arg_record_value_parms *parms)
5902 enum machine_mode mode;
5904 unsigned int startbit, endbit;
5905 int this_slotno, intslots, intoffset;
5908 if (parms->intoffset == -1)
5911 intoffset = parms->intoffset;
5912 parms->intoffset = -1;
5914 startbit = intoffset & -BITS_PER_WORD;
5915 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5916 intslots = (endbit - startbit) / BITS_PER_WORD;
5917 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5919 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5923 /* If this is the trailing part of a word, only load that much into
5924 the register. Otherwise load the whole register. Note that in
5925 the latter case we may pick up unwanted bits. It's not a problem
5926 at the moment but may wish to revisit. */
5928 if (intoffset % BITS_PER_WORD != 0)
5929 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5934 intoffset /= BITS_PER_UNIT;
5937 regno = parms->regbase + this_slotno;
5938 reg = gen_rtx_REG (mode, regno);
5939 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5940 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5943 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5948 while (intslots > 0);
5951 /* A subroutine of function_arg_record_value. Traverse the structure
5952 recursively and assign bits to floating point registers. Track which
5953 bits in between need integer registers; invoke function_arg_record_value_3
5954 to make that happen. */
5957 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
5958 struct function_arg_record_value_parms *parms,
5964 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5966 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5973 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5975 if (TREE_CODE (field) == FIELD_DECL)
5977 HOST_WIDE_INT bitpos = startbitpos;
5979 if (DECL_SIZE (field) != 0)
5981 if (integer_zerop (DECL_SIZE (field)))
5984 if (host_integerp (bit_position (field), 1))
5985 bitpos += int_bit_position (field);
5988 /* ??? FIXME: else assume zero offset. */
5990 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5991 function_arg_record_value_2 (TREE_TYPE (field),
5995 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5996 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6001 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
6002 int regno, nregs, pos;
6003 enum machine_mode mode = DECL_MODE (field);
6006 function_arg_record_value_3 (bitpos, parms);
6008 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
6011 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6012 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6014 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6016 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6022 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
6023 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
6025 reg = gen_rtx_REG (mode, regno);
6026 pos = bitpos / BITS_PER_UNIT;
6027 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6028 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6032 regno += GET_MODE_SIZE (mode) / 4;
6033 reg = gen_rtx_REG (mode, regno);
6034 pos += GET_MODE_SIZE (mode);
6035 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6036 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6042 if (parms->intoffset == -1)
6043 parms->intoffset = bitpos;
6049 /* Used by function_arg and sparc_function_value_1 to implement the complex
6050 conventions of the 64-bit ABI for passing and returning structures.
6051 Return an expression valid as a return value for the FUNCTION_ARG
6052 and TARGET_FUNCTION_VALUE.
6054 TYPE is the data type of the argument (as a tree).
6055 This is null for libcalls where that information may
6057 MODE is the argument's machine mode.
6058 SLOTNO is the index number of the argument's slot in the parameter array.
6059 NAMED is nonzero if this argument is a named parameter
6060 (otherwise it is an extra parameter matching an ellipsis).
6061 REGBASE is the regno of the base register for the parameter array. */
6064 function_arg_record_value (const_tree type, enum machine_mode mode,
6065 int slotno, int named, int regbase)
6067 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6068 struct function_arg_record_value_parms parms;
6071 parms.ret = NULL_RTX;
6072 parms.slotno = slotno;
6073 parms.named = named;
6074 parms.regbase = regbase;
6077 /* Compute how many registers we need. */
6079 parms.intoffset = 0;
6080 function_arg_record_value_1 (type, 0, &parms, false);
6082 /* Take into account pending integer fields. */
6083 if (parms.intoffset != -1)
6085 unsigned int startbit, endbit;
6086 int intslots, this_slotno;
6088 startbit = parms.intoffset & -BITS_PER_WORD;
6089 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6090 intslots = (endbit - startbit) / BITS_PER_WORD;
6091 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
6093 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
6095 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
6096 /* We need to pass this field on the stack. */
6100 parms.nregs += intslots;
6102 nregs = parms.nregs;
6104 /* Allocate the vector and handle some annoying special cases. */
6107 /* ??? Empty structure has no value? Duh? */
6110 /* Though there's nothing really to store, return a word register
6111 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6112 leads to breakage due to the fact that there are zero bytes to
6114 return gen_rtx_REG (mode, regbase);
6118 /* ??? C++ has structures with no fields, and yet a size. Give up
6119 for now and pass everything back in integer registers. */
6120 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6122 if (nregs + slotno > SPARC_INT_ARG_MAX)
6123 nregs = SPARC_INT_ARG_MAX - slotno;
6125 gcc_assert (nregs != 0);
6127 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
6129 /* If at least one field must be passed on the stack, generate
6130 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6131 also be passed on the stack. We can't do much better because the
6132 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6133 of structures for which the fields passed exclusively in registers
6134 are not at the beginning of the structure. */
6136 XVECEXP (parms.ret, 0, 0)
6137 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6139 /* Fill in the entries. */
6141 parms.intoffset = 0;
6142 function_arg_record_value_2 (type, 0, &parms, false);
6143 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
6145 gcc_assert (parms.nregs == nregs);
6150 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6151 of the 64-bit ABI for passing and returning unions.
6152 Return an expression valid as a return value for the FUNCTION_ARG
6153 and TARGET_FUNCTION_VALUE.
6155 SIZE is the size in bytes of the union.
6156 MODE is the argument's machine mode.
6157 REGNO is the hard register the union will be passed in. */
6160 function_arg_union_value (int size, enum machine_mode mode, int slotno,
6163 int nwords = ROUND_ADVANCE (size), i;
6166 /* See comment in previous function for empty structures. */
6168 return gen_rtx_REG (mode, regno);
6170 if (slotno == SPARC_INT_ARG_MAX - 1)
6173 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
6175 for (i = 0; i < nwords; i++)
6177 /* Unions are passed left-justified. */
6178 XVECEXP (regs, 0, i)
6179 = gen_rtx_EXPR_LIST (VOIDmode,
6180 gen_rtx_REG (word_mode, regno),
6181 GEN_INT (UNITS_PER_WORD * i));
6188 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6189 for passing and returning large (BLKmode) vectors.
6190 Return an expression valid as a return value for the FUNCTION_ARG
6191 and TARGET_FUNCTION_VALUE.
6193 SIZE is the size in bytes of the vector (at least 8 bytes).
6194 REGNO is the FP hard register the vector will be passed in. */
6197 function_arg_vector_value (int size, int regno)
6199 int i, nregs = size / 8;
6202 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6204 for (i = 0; i < nregs; i++)
6206 XVECEXP (regs, 0, i)
6207 = gen_rtx_EXPR_LIST (VOIDmode,
6208 gen_rtx_REG (DImode, regno + 2*i),
6215 /* Determine where to put an argument to a function.
6216 Value is zero to push the argument on the stack,
6217 or a hard register in which to store the argument.
6219 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6220 the preceding args and about the function being called.
6221 MODE is the argument's machine mode.
6222 TYPE is the data type of the argument (as a tree).
6223 This is null for libcalls where that information may
6225 NAMED is true if this argument is a named parameter
6226 (otherwise it is an extra parameter matching an ellipsis).
6227 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6228 TARGET_FUNCTION_INCOMING_ARG. */
6231 sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
6232 const_tree type, bool named, bool incoming_p)
6234 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6236 int regbase = (incoming_p
6237 ? SPARC_INCOMING_INT_ARG_FIRST
6238 : SPARC_OUTGOING_INT_ARG_FIRST);
6239 int slotno, regno, padding;
6240 enum mode_class mclass = GET_MODE_CLASS (mode);
6242 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6247 /* Vector types deserve special treatment because they are polymorphic wrt
6248 their mode, depending upon whether VIS instructions are enabled. */
6249 if (type && TREE_CODE (type) == VECTOR_TYPE)
6251 HOST_WIDE_INT size = int_size_in_bytes (type);
6252 gcc_assert ((TARGET_ARCH32 && size <= 8)
6253 || (TARGET_ARCH64 && size <= 16));
6255 if (mode == BLKmode)
6256 return function_arg_vector_value (size,
6257 SPARC_FP_ARG_FIRST + 2*slotno);
6259 mclass = MODE_FLOAT;
6263 return gen_rtx_REG (mode, regno);
6265 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6266 and are promoted to registers if possible. */
6267 if (type && TREE_CODE (type) == RECORD_TYPE)
6269 HOST_WIDE_INT size = int_size_in_bytes (type);
6270 gcc_assert (size <= 16);
6272 return function_arg_record_value (type, mode, slotno, named, regbase);
6275 /* Unions up to 16 bytes in size are passed in integer registers. */
6276 else if (type && TREE_CODE (type) == UNION_TYPE)
6278 HOST_WIDE_INT size = int_size_in_bytes (type);
6279 gcc_assert (size <= 16);
6281 return function_arg_union_value (size, mode, slotno, regno);
6284 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6285 but also have the slot allocated for them.
6286 If no prototype is in scope fp values in register slots get passed
6287 in two places, either fp regs and int regs or fp regs and memory. */
6288 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6289 && SPARC_FP_REG_P (regno))
6291 rtx reg = gen_rtx_REG (mode, regno);
6292 if (cum->prototype_p || cum->libcall_p)
6294 /* "* 2" because fp reg numbers are recorded in 4 byte
6297 /* ??? This will cause the value to be passed in the fp reg and
6298 in the stack. When a prototype exists we want to pass the
6299 value in the reg but reserve space on the stack. That's an
6300 optimization, and is deferred [for a bit]. */
6301 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
6302 return gen_rtx_PARALLEL (mode,
6304 gen_rtx_EXPR_LIST (VOIDmode,
6305 NULL_RTX, const0_rtx),
6306 gen_rtx_EXPR_LIST (VOIDmode,
6310 /* ??? It seems that passing back a register even when past
6311 the area declared by REG_PARM_STACK_SPACE will allocate
6312 space appropriately, and will not copy the data onto the
6313 stack, exactly as we desire.
6315 This is due to locate_and_pad_parm being called in
6316 expand_call whenever reg_parm_stack_space > 0, which
6317 while beneficial to our example here, would seem to be
6318 in error from what had been intended. Ho hum... -- r~ */
6326 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6330 /* On incoming, we don't need to know that the value
6331 is passed in %f0 and %i0, and it confuses other parts
6332 causing needless spillage even on the simplest cases. */
6336 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6337 + (regno - SPARC_FP_ARG_FIRST) / 2);
6339 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6340 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6342 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6346 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6347 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6348 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6353 /* All other aggregate types are passed in an integer register in a mode
6354 corresponding to the size of the type. */
6355 else if (type && AGGREGATE_TYPE_P (type))
6357 HOST_WIDE_INT size = int_size_in_bytes (type);
6358 gcc_assert (size <= 16);
6360 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6363 return gen_rtx_REG (mode, regno);
6366 /* Handle the TARGET_FUNCTION_ARG target hook. */
6369 sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
6370 const_tree type, bool named)
6372 return sparc_function_arg_1 (cum, mode, type, named, false);
6375 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6378 sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
6379 const_tree type, bool named)
6381 return sparc_function_arg_1 (cum, mode, type, named, true);
6384 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6387 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
6389 return ((TARGET_ARCH64
6390 && (GET_MODE_ALIGNMENT (mode) == 128
6391 || (type && TYPE_ALIGN (type) == 128)))
6396 /* For an arg passed partly in registers and partly in memory,
6397 this is the number of bytes of registers used.
6398 For args passed entirely in registers or entirely in memory, zero.
6400 Any arg that starts in the first 6 regs but won't entirely fit in them
6401 needs partial registers on v8. On v9, structures with integer
6402 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6403 values that begin in the last fp reg [where "last fp reg" varies with the
6404 mode] will be split between that reg and memory. */
6407 sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
6408 tree type, bool named)
6410 int slotno, regno, padding;
6412 /* We pass false for incoming_p here, it doesn't matter. */
6413 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6414 false, ®no, &padding);
6421 if ((slotno + (mode == BLKmode
6422 ? ROUND_ADVANCE (int_size_in_bytes (type))
6423 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
6424 > SPARC_INT_ARG_MAX)
6425 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
6429 /* We are guaranteed by pass_by_reference that the size of the
6430 argument is not greater than 16 bytes, so we only need to return
6431 one word if the argument is partially passed in registers. */
6433 if (type && AGGREGATE_TYPE_P (type))
6435 int size = int_size_in_bytes (type);
6437 if (size > UNITS_PER_WORD
6438 && slotno == SPARC_INT_ARG_MAX - 1)
6439 return UNITS_PER_WORD;
6441 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
6442 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6443 && ! (TARGET_FPU && named)))
6445 /* The complex types are passed as packed types. */
6446 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6447 && slotno == SPARC_INT_ARG_MAX - 1)
6448 return UNITS_PER_WORD;
6450 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6452 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6454 return UNITS_PER_WORD;
6461 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6462 Specify whether to pass the argument by reference. */
6465 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6466 enum machine_mode mode, const_tree type,
6467 bool named ATTRIBUTE_UNUSED)
6470 /* Original SPARC 32-bit ABI says that structures and unions,
6471 and quad-precision floats are passed by reference. For Pascal,
6472 also pass arrays by reference. All other base types are passed
6475 Extended ABI (as implemented by the Sun compiler) says that all
6476 complex floats are passed by reference. Pass complex integers
6477 in registers up to 8 bytes. More generally, enforce the 2-word
6478 cap for passing arguments in registers.
6480 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6481 integers are passed like floats of the same size, that is in
6482 registers up to 8 bytes. Pass all vector floats by reference
6483 like structure and unions. */
6484 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6486 /* Catch CDImode, TFmode, DCmode and TCmode. */
6487 || GET_MODE_SIZE (mode) > 8
6489 && TREE_CODE (type) == VECTOR_TYPE
6490 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6492 /* Original SPARC 64-bit ABI says that structures and unions
6493 smaller than 16 bytes are passed in registers, as well as
6494 all other base types.
6496 Extended ABI (as implemented by the Sun compiler) says that
6497 complex floats are passed in registers up to 16 bytes. Pass
6498 all complex integers in registers up to 16 bytes. More generally,
6499 enforce the 2-word cap for passing arguments in registers.
6501 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6502 integers are passed like floats of the same size, that is in
6503 registers (up to 16 bytes). Pass all vector floats like structure
6506 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6507 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6508 /* Catch CTImode and TCmode. */
6509 || GET_MODE_SIZE (mode) > 16);
6512 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6513 Update the data in CUM to advance over an argument
6514 of mode MODE and data type TYPE.
6515 TYPE is null for libcalls where that information may not be available. */
6518 sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
6519 const_tree type, bool named)
6521 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6524 /* We pass false for incoming_p here, it doesn't matter. */
6525 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
6527 /* If argument requires leading padding, add it. */
6528 cum->words += padding;
6532 cum->words += (mode != BLKmode
6533 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6534 : ROUND_ADVANCE (int_size_in_bytes (type)));
6538 if (type && AGGREGATE_TYPE_P (type))
6540 int size = int_size_in_bytes (type);
6544 else if (size <= 16)
6546 else /* passed by reference */
6551 cum->words += (mode != BLKmode
6552 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6553 : ROUND_ADVANCE (int_size_in_bytes (type)));
6558 /* Handle the FUNCTION_ARG_PADDING macro.
6559 For the 64 bit ABI structs are always stored left shifted in their
6563 function_arg_padding (enum machine_mode mode, const_tree type)
6565 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6568 /* Fall back to the default. */
6569 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6572 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6573 Specify whether to return the return value in memory. */
6576 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6579 /* Original SPARC 32-bit ABI says that structures and unions,
6580 and quad-precision floats are returned in memory. All other
6581 base types are returned in registers.
6583 Extended ABI (as implemented by the Sun compiler) says that
6584 all complex floats are returned in registers (8 FP registers
6585 at most for '_Complex long double'). Return all complex integers
6586 in registers (4 at most for '_Complex long long').
6588 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6589 integers are returned like floats of the same size, that is in
6590 registers up to 8 bytes and in memory otherwise. Return all
6591 vector floats in memory like structure and unions; note that
6592 they always have BLKmode like the latter. */
6593 return (TYPE_MODE (type) == BLKmode
6594 || TYPE_MODE (type) == TFmode
6595 || (TREE_CODE (type) == VECTOR_TYPE
6596 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6598 /* Original SPARC 64-bit ABI says that structures and unions
6599 smaller than 32 bytes are returned in registers, as well as
6600 all other base types.
6602 Extended ABI (as implemented by the Sun compiler) says that all
6603 complex floats are returned in registers (8 FP registers at most
6604 for '_Complex long double'). Return all complex integers in
6605 registers (4 at most for '_Complex TItype').
6607 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6608 integers are returned like floats of the same size, that is in
6609 registers. Return all vector floats like structure and unions;
6610 note that they always have BLKmode like the latter. */
6611 return (TYPE_MODE (type) == BLKmode
6612 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
6615 /* Handle the TARGET_STRUCT_VALUE target hook.
6616 Return where to find the structure return value address. */
6619 sparc_struct_value_rtx (tree fndecl, int incoming)
6628 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6629 STRUCT_VALUE_OFFSET));
6631 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6632 STRUCT_VALUE_OFFSET));
6634 /* Only follow the SPARC ABI for fixed-size structure returns.
6635 Variable size structure returns are handled per the normal
6636 procedures in GCC. This is enabled by -mstd-struct-return */
6638 && sparc_std_struct_return
6639 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6640 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6642 /* We must check and adjust the return address, as it is
6643 optional as to whether the return object is really
6645 rtx ret_reg = gen_rtx_REG (Pmode, 31);
6646 rtx scratch = gen_reg_rtx (SImode);
6647 rtx endlab = gen_label_rtx ();
6649 /* Calculate the return object size */
6650 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6651 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6652 /* Construct a temporary return value */
6654 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
6656 /* Implement SPARC 32-bit psABI callee return struct checking:
6658 Fetch the instruction where we will return to and see if
6659 it's an unimp instruction (the most significant 10 bits
6661 emit_move_insn (scratch, gen_rtx_MEM (SImode,
6662 plus_constant (ret_reg, 8)));
6663 /* Assume the size is valid and pre-adjust */
6664 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
6665 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6667 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
6668 /* Write the address of the memory pointed to by temp_val into
6669 the memory pointed to by mem */
6670 emit_move_insn (mem, XEXP (temp_val, 0));
6671 emit_label (endlab);
6678 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6679 For v9, function return values are subject to the same rules as arguments,
6680 except that up to 32 bytes may be returned in registers. */
6683 sparc_function_value_1 (const_tree type, enum machine_mode mode,
6686 /* Beware that the two values are swapped here wrt function_arg. */
6687 int regbase = (outgoing
6688 ? SPARC_INCOMING_INT_ARG_FIRST
6689 : SPARC_OUTGOING_INT_ARG_FIRST);
6690 enum mode_class mclass = GET_MODE_CLASS (mode);
6693 /* Vector types deserve special treatment because they are polymorphic wrt
6694 their mode, depending upon whether VIS instructions are enabled. */
6695 if (type && TREE_CODE (type) == VECTOR_TYPE)
6697 HOST_WIDE_INT size = int_size_in_bytes (type);
6698 gcc_assert ((TARGET_ARCH32 && size <= 8)
6699 || (TARGET_ARCH64 && size <= 32));
6701 if (mode == BLKmode)
6702 return function_arg_vector_value (size,
6703 SPARC_FP_ARG_FIRST);
6705 mclass = MODE_FLOAT;
6708 if (TARGET_ARCH64 && type)
6710 /* Structures up to 32 bytes in size are returned in registers. */
6711 if (TREE_CODE (type) == RECORD_TYPE)
6713 HOST_WIDE_INT size = int_size_in_bytes (type);
6714 gcc_assert (size <= 32);
6716 return function_arg_record_value (type, mode, 0, 1, regbase);
6719 /* Unions up to 32 bytes in size are returned in integer registers. */
6720 else if (TREE_CODE (type) == UNION_TYPE)
6722 HOST_WIDE_INT size = int_size_in_bytes (type);
6723 gcc_assert (size <= 32);
6725 return function_arg_union_value (size, mode, 0, regbase);
6728 /* Objects that require it are returned in FP registers. */
6729 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6732 /* All other aggregate types are returned in an integer register in a
6733 mode corresponding to the size of the type. */
6734 else if (AGGREGATE_TYPE_P (type))
6736 /* All other aggregate types are passed in an integer register
6737 in a mode corresponding to the size of the type. */
6738 HOST_WIDE_INT size = int_size_in_bytes (type);
6739 gcc_assert (size <= 32);
6741 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6743 /* ??? We probably should have made the same ABI change in
6744 3.4.0 as the one we made for unions. The latter was
6745 required by the SCD though, while the former is not
6746 specified, so we favored compatibility and efficiency.
6748 Now we're stuck for aggregates larger than 16 bytes,
6749 because OImode vanished in the meantime. Let's not
6750 try to be unduly clever, and simply follow the ABI
6751 for unions in that case. */
6752 if (mode == BLKmode)
6753 return function_arg_union_value (size, mode, 0, regbase);
6758 /* We should only have pointer and integer types at this point. This
6759 must match sparc_promote_function_mode. */
6760 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6764 /* We should only have pointer and integer types at this point. This must
6765 match sparc_promote_function_mode. */
6766 else if (TARGET_ARCH32
6767 && mclass == MODE_INT
6768 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6771 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
6772 regno = SPARC_FP_ARG_FIRST;
6776 return gen_rtx_REG (mode, regno);
6779 /* Handle TARGET_FUNCTION_VALUE.
6780 On the SPARC, the value is found in the first "output" register, but the
6781 called function leaves it in the first "input" register. */
6784 sparc_function_value (const_tree valtype,
6785 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6788 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6791 /* Handle TARGET_LIBCALL_VALUE. */
6794 sparc_libcall_value (enum machine_mode mode,
6795 const_rtx fun ATTRIBUTE_UNUSED)
6797 return sparc_function_value_1 (NULL_TREE, mode, false);
6800 /* Handle FUNCTION_VALUE_REGNO_P.
6801 On the SPARC, the first "output" reg is used for integer values, and the
6802 first floating point register is used for floating point values. */
6805 sparc_function_value_regno_p (const unsigned int regno)
6807 return (regno == 8 || regno == 32);
6810 /* Do what is necessary for `va_start'. We look at the current function
6811 to determine if stdarg or varargs is used and return the address of
6812 the first unnamed parameter. */
6815 sparc_builtin_saveregs (void)
6817 int first_reg = crtl->args.info.words;
6821 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6822 emit_move_insn (gen_rtx_MEM (word_mode,
6823 gen_rtx_PLUS (Pmode,
6825 GEN_INT (FIRST_PARM_OFFSET (0)
6828 gen_rtx_REG (word_mode,
6829 SPARC_INCOMING_INT_ARG_FIRST + regno));
6831 address = gen_rtx_PLUS (Pmode,
6833 GEN_INT (FIRST_PARM_OFFSET (0)
6834 + UNITS_PER_WORD * first_reg));
6839 /* Implement `va_start' for stdarg. */
6842 sparc_va_start (tree valist, rtx nextarg)
6844 nextarg = expand_builtin_saveregs ();
6845 std_expand_builtin_va_start (valist, nextarg);
6848 /* Implement `va_arg' for stdarg. */
6851 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6854 HOST_WIDE_INT size, rsize, align;
6857 tree ptrtype = build_pointer_type (type);
6859 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6862 size = rsize = UNITS_PER_WORD;
6868 size = int_size_in_bytes (type);
6869 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6874 /* For SPARC64, objects requiring 16-byte alignment get it. */
6875 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6876 align = 2 * UNITS_PER_WORD;
6878 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6879 are left-justified in their slots. */
6880 if (AGGREGATE_TYPE_P (type))
6883 size = rsize = UNITS_PER_WORD;
6893 incr = fold_build_pointer_plus_hwi (incr, align - 1);
6894 incr = fold_convert (sizetype, incr);
6895 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6897 incr = fold_convert (ptr_type_node, incr);
6900 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6903 if (BYTES_BIG_ENDIAN && size < rsize)
6904 addr = fold_build_pointer_plus_hwi (incr, rsize - size);
6908 addr = fold_convert (build_pointer_type (ptrtype), addr);
6909 addr = build_va_arg_indirect_ref (addr);
6912 /* If the address isn't aligned properly for the type, we need a temporary.
6913 FIXME: This is inefficient, usually we can do this in registers. */
6914 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
6916 tree tmp = create_tmp_var (type, "va_arg_tmp");
6917 tree dest_addr = build_fold_addr_expr (tmp);
6918 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
6919 3, dest_addr, addr, size_int (rsize));
6920 TREE_ADDRESSABLE (tmp) = 1;
6921 gimplify_and_add (copy, pre_p);
6926 addr = fold_convert (ptrtype, addr);
6928 incr = fold_build_pointer_plus_hwi (incr, rsize);
6929 gimplify_assign (valist, incr, post_p);
6931 return build_va_arg_indirect_ref (addr);
6934 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6935 Specify whether the vector mode is supported by the hardware. */
6938 sparc_vector_mode_supported_p (enum machine_mode mode)
6940 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6943 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6945 static enum machine_mode
6946 sparc_preferred_simd_mode (enum machine_mode mode)
6964 /* Return the string to output an unconditional branch to LABEL, which is
6965 the operand number of the label.
6967 DEST is the destination insn (i.e. the label), INSN is the source. */
6970 output_ubranch (rtx dest, int label, rtx insn)
6972 static char string[64];
6973 bool v9_form = false;
6976 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6978 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6979 - INSN_ADDRESSES (INSN_UID (insn)));
6980 /* Leave some instructions for "slop". */
6981 if (delta >= -260000 && delta < 260000)
6986 strcpy (string, "ba%*,pt\t%%xcc, ");
6988 strcpy (string, "b%*\t");
6990 p = strchr (string, '\0');
7001 /* Return the string to output a conditional branch to LABEL, which is
7002 the operand number of the label. OP is the conditional expression.
7003 XEXP (OP, 0) is assumed to be a condition code register (integer or
7004 floating point) and its mode specifies what kind of comparison we made.
7006 DEST is the destination insn (i.e. the label), INSN is the source.
7008 REVERSED is nonzero if we should reverse the sense of the comparison.
7010 ANNUL is nonzero if we should generate an annulling branch. */
7013 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
7016 static char string[64];
7017 enum rtx_code code = GET_CODE (op);
7018 rtx cc_reg = XEXP (op, 0);
7019 enum machine_mode mode = GET_MODE (cc_reg);
7020 const char *labelno, *branch;
7021 int spaces = 8, far;
7024 /* v9 branches are limited to +-1MB. If it is too far away,
7037 fbne,a,pn %fcc2, .LC29
7045 far = TARGET_V9 && (get_attr_length (insn) >= 3);
7048 /* Reversal of FP compares takes care -- an ordered compare
7049 becomes an unordered compare and vice versa. */
7050 if (mode == CCFPmode || mode == CCFPEmode)
7051 code = reverse_condition_maybe_unordered (code);
7053 code = reverse_condition (code);
7056 /* Start by writing the branch condition. */
7057 if (mode == CCFPmode || mode == CCFPEmode)
7108 /* ??? !v9: FP branches cannot be preceded by another floating point
7109 insn. Because there is currently no concept of pre-delay slots,
7110 we can fix this only by always emitting a nop before a floating
7115 strcpy (string, "nop\n\t");
7116 strcat (string, branch);
7129 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7141 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7162 strcpy (string, branch);
7164 spaces -= strlen (branch);
7165 p = strchr (string, '\0');
7167 /* Now add the annulling, the label, and a possible noop. */
7180 if (! far && insn && INSN_ADDRESSES_SET_P ())
7182 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7183 - INSN_ADDRESSES (INSN_UID (insn)));
7184 /* Leave some instructions for "slop". */
7185 if (delta < -260000 || delta >= 260000)
7189 if (mode == CCFPmode || mode == CCFPEmode)
7191 static char v9_fcc_labelno[] = "%%fccX, ";
7192 /* Set the char indicating the number of the fcc reg to use. */
7193 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7194 labelno = v9_fcc_labelno;
7197 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7201 else if (mode == CCXmode || mode == CCX_NOOVmode)
7203 labelno = "%%xcc, ";
7208 labelno = "%%icc, ";
7213 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7216 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7229 strcpy (p, labelno);
7230 p = strchr (p, '\0');
7233 strcpy (p, ".+12\n\t nop\n\tb\t");
7234 /* Skip the next insn if requested or
7235 if we know that it will be a nop. */
7236 if (annul || ! final_sequence)
7250 /* Emit a library call comparison between floating point X and Y.
7251 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7252 Return the new operator to be used in the comparison sequence.
7254 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7255 values as arguments instead of the TFmode registers themselves,
7256 that's why we cannot call emit_float_lib_cmp. */
7259 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7262 rtx slot0, slot1, result, tem, tem2, libfunc;
7263 enum machine_mode mode;
7264 enum rtx_code new_comparison;
7269 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7273 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7277 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7281 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7285 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7289 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7300 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7313 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7314 emit_move_insn (slot0, x);
7321 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7322 emit_move_insn (slot1, y);
7325 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7326 emit_library_call (libfunc, LCT_NORMAL,
7328 XEXP (slot0, 0), Pmode,
7329 XEXP (slot1, 0), Pmode);
7334 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7335 emit_library_call (libfunc, LCT_NORMAL,
7337 x, TFmode, y, TFmode);
7342 /* Immediately move the result of the libcall into a pseudo
7343 register so reload doesn't clobber the value if it needs
7344 the return register for a spill reg. */
7345 result = gen_reg_rtx (mode);
7346 emit_move_insn (result, hard_libcall_value (mode, libfunc));
7351 return gen_rtx_NE (VOIDmode, result, const0_rtx);
7354 new_comparison = (comparison == UNORDERED ? EQ : NE);
7355 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
7358 new_comparison = (comparison == UNGT ? GT : NE);
7359 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
7361 return gen_rtx_NE (VOIDmode, result, const2_rtx);
7363 tem = gen_reg_rtx (mode);
7365 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7367 emit_insn (gen_anddi3 (tem, result, const1_rtx));
7368 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
7371 tem = gen_reg_rtx (mode);
7373 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7375 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7376 tem2 = gen_reg_rtx (mode);
7378 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7380 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
7381 new_comparison = (comparison == UNEQ ? EQ : NE);
7382 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
7388 /* Generate an unsigned DImode to FP conversion. This is the same code
7389 optabs would emit if we didn't have TFmode patterns. */
7392 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
7394 rtx neglab, donelab, i0, i1, f0, in, out;
7397 in = force_reg (DImode, operands[1]);
7398 neglab = gen_label_rtx ();
7399 donelab = gen_label_rtx ();
7400 i0 = gen_reg_rtx (DImode);
7401 i1 = gen_reg_rtx (DImode);
7402 f0 = gen_reg_rtx (mode);
7404 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7406 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
7407 emit_jump_insn (gen_jump (donelab));
7410 emit_label (neglab);
7412 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7413 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7414 emit_insn (gen_iordi3 (i0, i0, i1));
7415 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
7416 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
7418 emit_label (donelab);
7421 /* Generate an FP to unsigned DImode conversion. This is the same code
7422 optabs would emit if we didn't have TFmode patterns. */
7425 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
7427 rtx neglab, donelab, i0, i1, f0, in, out, limit;
7430 in = force_reg (mode, operands[1]);
7431 neglab = gen_label_rtx ();
7432 donelab = gen_label_rtx ();
7433 i0 = gen_reg_rtx (DImode);
7434 i1 = gen_reg_rtx (DImode);
7435 limit = gen_reg_rtx (mode);
7436 f0 = gen_reg_rtx (mode);
7438 emit_move_insn (limit,
7439 CONST_DOUBLE_FROM_REAL_VALUE (
7440 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7441 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7443 emit_insn (gen_rtx_SET (VOIDmode,
7445 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7446 emit_jump_insn (gen_jump (donelab));
7449 emit_label (neglab);
7451 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
7452 emit_insn (gen_rtx_SET (VOIDmode,
7454 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7455 emit_insn (gen_movdi (i1, const1_rtx));
7456 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7457 emit_insn (gen_xordi3 (out, i0, i1));
7459 emit_label (donelab);
7462 /* Return the string to output a conditional branch to LABEL, testing
7463 register REG. LABEL is the operand number of the label; REG is the
7464 operand number of the reg. OP is the conditional expression. The mode
7465 of REG says what kind of comparison we made.
7467 DEST is the destination insn (i.e. the label), INSN is the source.
7469 REVERSED is nonzero if we should reverse the sense of the comparison.
7471 ANNUL is nonzero if we should generate an annulling branch. */
7474 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
7475 int annul, rtx insn)
7477 static char string[64];
7478 enum rtx_code code = GET_CODE (op);
7479 enum machine_mode mode = GET_MODE (XEXP (op, 0));
7484 /* branch on register are limited to +-128KB. If it is too far away,
7497 brgez,a,pn %o1, .LC29
7503 ba,pt %xcc, .LC29 */
7505 far = get_attr_length (insn) >= 3;
7507 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7509 code = reverse_condition (code);
7511 /* Only 64 bit versions of these instructions exist. */
7512 gcc_assert (mode == DImode);
7514 /* Start by writing the branch condition. */
7519 strcpy (string, "brnz");
7523 strcpy (string, "brz");
7527 strcpy (string, "brgez");
7531 strcpy (string, "brlz");
7535 strcpy (string, "brlez");
7539 strcpy (string, "brgz");
7546 p = strchr (string, '\0');
7548 /* Now add the annulling, reg, label, and nop. */
7555 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7558 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7563 *p = p < string + 8 ? '\t' : ' ';
7571 int veryfar = 1, delta;
7573 if (INSN_ADDRESSES_SET_P ())
7575 delta = (INSN_ADDRESSES (INSN_UID (dest))
7576 - INSN_ADDRESSES (INSN_UID (insn)));
7577 /* Leave some instructions for "slop". */
7578 if (delta >= -260000 && delta < 260000)
7582 strcpy (p, ".+12\n\t nop\n\t");
7583 /* Skip the next insn if requested or
7584 if we know that it will be a nop. */
7585 if (annul || ! final_sequence)
7595 strcpy (p, "ba,pt\t%%xcc, ");
7609 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7610 Such instructions cannot be used in the delay slot of return insn on v9.
7611 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7615 epilogue_renumber (register rtx *where, int test)
7617 register const char *fmt;
7619 register enum rtx_code code;
7624 code = GET_CODE (*where);
7629 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7631 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7632 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7640 /* Do not replace the frame pointer with the stack pointer because
7641 it can cause the delayed instruction to load below the stack.
7642 This occurs when instructions like:
7644 (set (reg/i:SI 24 %i0)
7645 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7646 (const_int -20 [0xffffffec])) 0))
7648 are in the return delayed slot. */
7650 if (GET_CODE (XEXP (*where, 0)) == REG
7651 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7652 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7653 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7658 if (SPARC_STACK_BIAS
7659 && GET_CODE (XEXP (*where, 0)) == REG
7660 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7668 fmt = GET_RTX_FORMAT (code);
7670 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7675 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7676 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7679 else if (fmt[i] == 'e'
7680 && epilogue_renumber (&(XEXP (*where, i)), test))
7686 /* Leaf functions and non-leaf functions have different needs. */
7689 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7692 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7694 static const int *const reg_alloc_orders[] = {
7695 reg_leaf_alloc_order,
7696 reg_nonleaf_alloc_order};
7699 order_regs_for_local_alloc (void)
7701 static int last_order_nonleaf = 1;
7703 if (df_regs_ever_live_p (15) != last_order_nonleaf)
7705 last_order_nonleaf = !last_order_nonleaf;
7706 memcpy ((char *) reg_alloc_order,
7707 (const char *) reg_alloc_orders[last_order_nonleaf],
7708 FIRST_PSEUDO_REGISTER * sizeof (int));
7712 /* Return 1 if REG and MEM are legitimate enough to allow the various
7713 mem<-->reg splits to be run. */
7716 sparc_splitdi_legitimate (rtx reg, rtx mem)
7718 /* Punt if we are here by mistake. */
7719 gcc_assert (reload_completed);
7721 /* We must have an offsettable memory reference. */
7722 if (! offsettable_memref_p (mem))
7725 /* If we have legitimate args for ldd/std, we do not want
7726 the split to happen. */
7727 if ((REGNO (reg) % 2) == 0
7728 && mem_min_alignment (mem, 8))
7735 /* Return 1 if x and y are some kind of REG and they refer to
7736 different hard registers. This test is guaranteed to be
7737 run after reload. */
7740 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7742 if (GET_CODE (x) != REG)
7744 if (GET_CODE (y) != REG)
7746 if (REGNO (x) == REGNO (y))
7751 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7752 This makes them candidates for using ldd and std insns.
7754 Note reg1 and reg2 *must* be hard registers. */
7757 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7759 /* We might have been passed a SUBREG. */
7760 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7763 if (REGNO (reg1) % 2 != 0)
7766 /* Integer ldd is deprecated in SPARC V9 */
7767 if (TARGET_V9 && REGNO (reg1) < 32)
7770 return (REGNO (reg1) == REGNO (reg2) - 1);
7773 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7776 This can only happen when addr1 and addr2, the addresses in mem1
7777 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7778 addr1 must also be aligned on a 64-bit boundary.
7780 Also iff dependent_reg_rtx is not null it should not be used to
7781 compute the address for mem1, i.e. we cannot optimize a sequence
7793 But, note that the transformation from:
7798 is perfectly fine. Thus, the peephole2 patterns always pass us
7799 the destination register of the first load, never the second one.
7801 For stores we don't have a similar problem, so dependent_reg_rtx is
7805 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7809 HOST_WIDE_INT offset1;
7811 /* The mems cannot be volatile. */
7812 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7815 /* MEM1 should be aligned on a 64-bit boundary. */
7816 if (MEM_ALIGN (mem1) < 64)
7819 addr1 = XEXP (mem1, 0);
7820 addr2 = XEXP (mem2, 0);
7822 /* Extract a register number and offset (if used) from the first addr. */
7823 if (GET_CODE (addr1) == PLUS)
7825 /* If not a REG, return zero. */
7826 if (GET_CODE (XEXP (addr1, 0)) != REG)
7830 reg1 = REGNO (XEXP (addr1, 0));
7831 /* The offset must be constant! */
7832 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7834 offset1 = INTVAL (XEXP (addr1, 1));
7837 else if (GET_CODE (addr1) != REG)
7841 reg1 = REGNO (addr1);
7842 /* This was a simple (mem (reg)) expression. Offset is 0. */
7846 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7847 if (GET_CODE (addr2) != PLUS)
7850 if (GET_CODE (XEXP (addr2, 0)) != REG
7851 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7854 if (reg1 != REGNO (XEXP (addr2, 0)))
7857 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7860 /* The first offset must be evenly divisible by 8 to ensure the
7861 address is 64 bit aligned. */
7862 if (offset1 % 8 != 0)
7865 /* The offset for the second addr must be 4 more than the first addr. */
7866 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7869 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7874 /* Return 1 if reg is a pseudo, or is the first register in
7875 a hard register pair. This makes it suitable for use in
7876 ldd and std insns. */
7879 register_ok_for_ldd (rtx reg)
7881 /* We might have been passed a SUBREG. */
7885 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7886 return (REGNO (reg) % 2 == 0);
7891 /* Return 1 if OP is a memory whose address is known to be
7892 aligned to 8-byte boundary, or a pseudo during reload.
7893 This makes it suitable for use in ldd and std insns. */
7896 memory_ok_for_ldd (rtx op)
7900 /* In 64-bit mode, we assume that the address is word-aligned. */
7901 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
7904 if (! can_create_pseudo_p ()
7905 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
7908 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
7910 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
7919 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7922 sparc_print_operand_punct_valid_p (unsigned char code)
7935 /* Implement TARGET_PRINT_OPERAND.
7936 Print operand X (an rtx) in assembler syntax to file FILE.
7937 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7938 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7941 sparc_print_operand (FILE *file, rtx x, int code)
7946 /* Output an insn in a delay slot. */
7948 sparc_indent_opcode = 1;
7950 fputs ("\n\t nop", file);
7953 /* Output an annul flag if there's nothing for the delay slot and we
7954 are optimizing. This is always used with '(' below.
7955 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7956 this is a dbx bug. So, we only do this when optimizing.
7957 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7958 Always emit a nop in case the next instruction is a branch. */
7959 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7963 /* Output a 'nop' if there's nothing for the delay slot and we are
7964 not optimizing. This is always used with '*' above. */
7965 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7966 fputs ("\n\t nop", file);
7967 else if (final_sequence)
7968 sparc_indent_opcode = 1;
7971 /* Output the right displacement from the saved PC on function return.
7972 The caller may have placed an "unimp" insn immediately after the call
7973 so we have to account for it. This insn is used in the 32-bit ABI
7974 when calling a function that returns a non zero-sized structure. The
7975 64-bit ABI doesn't have it. Be careful to have this test be the same
7976 as that for the call. The exception is when sparc_std_struct_return
7977 is enabled, the psABI is followed exactly and the adjustment is made
7978 by the code in sparc_struct_value_rtx. The call emitted is the same
7979 when sparc_std_struct_return is enabled. */
7981 && cfun->returns_struct
7982 && !sparc_std_struct_return
7983 && DECL_SIZE (DECL_RESULT (current_function_decl))
7984 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7986 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
7992 /* Output the Embedded Medium/Anywhere code model base register. */
7993 fputs (EMBMEDANY_BASE_REG, file);
7996 /* Print some local dynamic TLS name. */
7997 assemble_name (file, get_some_local_dynamic_name ());
8001 /* Adjust the operand to take into account a RESTORE operation. */
8002 if (GET_CODE (x) == CONST_INT)
8004 else if (GET_CODE (x) != REG)
8005 output_operand_lossage ("invalid %%Y operand");
8006 else if (REGNO (x) < 8)
8007 fputs (reg_names[REGNO (x)], file);
8008 else if (REGNO (x) >= 24 && REGNO (x) < 32)
8009 fputs (reg_names[REGNO (x)-16], file);
8011 output_operand_lossage ("invalid %%Y operand");
8014 /* Print out the low order register name of a register pair. */
8015 if (WORDS_BIG_ENDIAN)
8016 fputs (reg_names[REGNO (x)+1], file);
8018 fputs (reg_names[REGNO (x)], file);
8021 /* Print out the high order register name of a register pair. */
8022 if (WORDS_BIG_ENDIAN)
8023 fputs (reg_names[REGNO (x)], file);
8025 fputs (reg_names[REGNO (x)+1], file);
8028 /* Print out the second register name of a register pair or quad.
8029 I.e., R (%o0) => %o1. */
8030 fputs (reg_names[REGNO (x)+1], file);
8033 /* Print out the third register name of a register quad.
8034 I.e., S (%o0) => %o2. */
8035 fputs (reg_names[REGNO (x)+2], file);
8038 /* Print out the fourth register name of a register quad.
8039 I.e., T (%o0) => %o3. */
8040 fputs (reg_names[REGNO (x)+3], file);
8043 /* Print a condition code register. */
8044 if (REGNO (x) == SPARC_ICC_REG)
8046 /* We don't handle CC[X]_NOOVmode because they're not supposed
8048 if (GET_MODE (x) == CCmode)
8049 fputs ("%icc", file);
8050 else if (GET_MODE (x) == CCXmode)
8051 fputs ("%xcc", file);
8056 /* %fccN register */
8057 fputs (reg_names[REGNO (x)], file);
8060 /* Print the operand's address only. */
8061 output_address (XEXP (x, 0));
8064 /* In this case we need a register. Use %g0 if the
8065 operand is const0_rtx. */
8067 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
8069 fputs ("%g0", file);
8076 switch (GET_CODE (x))
8078 case IOR: fputs ("or", file); break;
8079 case AND: fputs ("and", file); break;
8080 case XOR: fputs ("xor", file); break;
8081 default: output_operand_lossage ("invalid %%A operand");
8086 switch (GET_CODE (x))
8088 case IOR: fputs ("orn", file); break;
8089 case AND: fputs ("andn", file); break;
8090 case XOR: fputs ("xnor", file); break;
8091 default: output_operand_lossage ("invalid %%B operand");
8095 /* These are used by the conditional move instructions. */
8099 enum rtx_code rc = GET_CODE (x);
8103 enum machine_mode mode = GET_MODE (XEXP (x, 0));
8104 if (mode == CCFPmode || mode == CCFPEmode)
8105 rc = reverse_condition_maybe_unordered (GET_CODE (x));
8107 rc = reverse_condition (GET_CODE (x));
8111 case NE: fputs ("ne", file); break;
8112 case EQ: fputs ("e", file); break;
8113 case GE: fputs ("ge", file); break;
8114 case GT: fputs ("g", file); break;
8115 case LE: fputs ("le", file); break;
8116 case LT: fputs ("l", file); break;
8117 case GEU: fputs ("geu", file); break;
8118 case GTU: fputs ("gu", file); break;
8119 case LEU: fputs ("leu", file); break;
8120 case LTU: fputs ("lu", file); break;
8121 case LTGT: fputs ("lg", file); break;
8122 case UNORDERED: fputs ("u", file); break;
8123 case ORDERED: fputs ("o", file); break;
8124 case UNLT: fputs ("ul", file); break;
8125 case UNLE: fputs ("ule", file); break;
8126 case UNGT: fputs ("ug", file); break;
8127 case UNGE: fputs ("uge", file); break;
8128 case UNEQ: fputs ("ue", file); break;
8129 default: output_operand_lossage (code == 'c'
8130 ? "invalid %%c operand"
8131 : "invalid %%C operand");
8136 /* These are used by the movr instruction pattern. */
8140 enum rtx_code rc = (code == 'd'
8141 ? reverse_condition (GET_CODE (x))
8145 case NE: fputs ("ne", file); break;
8146 case EQ: fputs ("e", file); break;
8147 case GE: fputs ("gez", file); break;
8148 case LT: fputs ("lz", file); break;
8149 case LE: fputs ("lez", file); break;
8150 case GT: fputs ("gz", file); break;
8151 default: output_operand_lossage (code == 'd'
8152 ? "invalid %%d operand"
8153 : "invalid %%D operand");
8160 /* Print a sign-extended character. */
8161 int i = trunc_int_for_mode (INTVAL (x), QImode);
8162 fprintf (file, "%d", i);
8167 /* Operand must be a MEM; write its address. */
8168 if (GET_CODE (x) != MEM)
8169 output_operand_lossage ("invalid %%f operand");
8170 output_address (XEXP (x, 0));
8175 /* Print a sign-extended 32-bit value. */
8177 if (GET_CODE(x) == CONST_INT)
8179 else if (GET_CODE(x) == CONST_DOUBLE)
8180 i = CONST_DOUBLE_LOW (x);
8183 output_operand_lossage ("invalid %%s operand");
8186 i = trunc_int_for_mode (i, SImode);
8187 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8192 /* Do nothing special. */
8196 /* Undocumented flag. */
8197 output_operand_lossage ("invalid operand output code");
8200 if (GET_CODE (x) == REG)
8201 fputs (reg_names[REGNO (x)], file);
8202 else if (GET_CODE (x) == MEM)
8205 /* Poor Sun assembler doesn't understand absolute addressing. */
8206 if (CONSTANT_P (XEXP (x, 0)))
8207 fputs ("%g0+", file);
8208 output_address (XEXP (x, 0));
8211 else if (GET_CODE (x) == HIGH)
8213 fputs ("%hi(", file);
8214 output_addr_const (file, XEXP (x, 0));
8217 else if (GET_CODE (x) == LO_SUM)
8219 sparc_print_operand (file, XEXP (x, 0), 0);
8220 if (TARGET_CM_MEDMID)
8221 fputs ("+%l44(", file);
8223 fputs ("+%lo(", file);
8224 output_addr_const (file, XEXP (x, 1));
8227 else if (GET_CODE (x) == CONST_DOUBLE
8228 && (GET_MODE (x) == VOIDmode
8229 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
8231 if (CONST_DOUBLE_HIGH (x) == 0)
8232 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
8233 else if (CONST_DOUBLE_HIGH (x) == -1
8234 && CONST_DOUBLE_LOW (x) < 0)
8235 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
8237 output_operand_lossage ("long long constant not a valid immediate operand");
8239 else if (GET_CODE (x) == CONST_DOUBLE)
8240 output_operand_lossage ("floating point constant not a valid immediate operand");
8241 else { output_addr_const (file, x); }
8244 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8247 sparc_print_operand_address (FILE *file, rtx x)
8249 register rtx base, index = 0;
8251 register rtx addr = x;
8254 fputs (reg_names[REGNO (addr)], file);
8255 else if (GET_CODE (addr) == PLUS)
8257 if (CONST_INT_P (XEXP (addr, 0)))
8258 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8259 else if (CONST_INT_P (XEXP (addr, 1)))
8260 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8262 base = XEXP (addr, 0), index = XEXP (addr, 1);
8263 if (GET_CODE (base) == LO_SUM)
8265 gcc_assert (USE_AS_OFFSETABLE_LO10
8267 && ! TARGET_CM_MEDMID);
8268 output_operand (XEXP (base, 0), 0);
8269 fputs ("+%lo(", file);
8270 output_address (XEXP (base, 1));
8271 fprintf (file, ")+%d", offset);
8275 fputs (reg_names[REGNO (base)], file);
8277 fprintf (file, "%+d", offset);
8278 else if (REG_P (index))
8279 fprintf (file, "+%s", reg_names[REGNO (index)]);
8280 else if (GET_CODE (index) == SYMBOL_REF
8281 || GET_CODE (index) == LABEL_REF
8282 || GET_CODE (index) == CONST)
8283 fputc ('+', file), output_addr_const (file, index);
8284 else gcc_unreachable ();
8287 else if (GET_CODE (addr) == MINUS
8288 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8290 output_addr_const (file, XEXP (addr, 0));
8292 output_addr_const (file, XEXP (addr, 1));
8293 fputs ("-.)", file);
8295 else if (GET_CODE (addr) == LO_SUM)
8297 output_operand (XEXP (addr, 0), 0);
8298 if (TARGET_CM_MEDMID)
8299 fputs ("+%l44(", file);
8301 fputs ("+%lo(", file);
8302 output_address (XEXP (addr, 1));
8306 && GET_CODE (addr) == CONST
8307 && GET_CODE (XEXP (addr, 0)) == MINUS
8308 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8309 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8310 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8312 addr = XEXP (addr, 0);
8313 output_addr_const (file, XEXP (addr, 0));
8314 /* Group the args of the second CONST in parenthesis. */
8316 /* Skip past the second CONST--it does nothing for us. */
8317 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8318 /* Close the parenthesis. */
8323 output_addr_const (file, addr);
8327 /* Target hook for assembling integer objects. The sparc version has
8328 special handling for aligned DI-mode objects. */
8331 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
8333 /* ??? We only output .xword's for symbols and only then in environments
8334 where the assembler can handle them. */
8335 if (aligned_p && size == 8
8336 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
8340 assemble_integer_with_op ("\t.xword\t", x);
8345 assemble_aligned_integer (4, const0_rtx);
8346 assemble_aligned_integer (4, x);
8350 return default_assemble_integer (x, size, aligned_p);
8353 /* Return the value of a code used in the .proc pseudo-op that says
8354 what kind of result this function returns. For non-C types, we pick
8355 the closest C type. */
8357 #ifndef SHORT_TYPE_SIZE
8358 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8361 #ifndef INT_TYPE_SIZE
8362 #define INT_TYPE_SIZE BITS_PER_WORD
8365 #ifndef LONG_TYPE_SIZE
8366 #define LONG_TYPE_SIZE BITS_PER_WORD
8369 #ifndef LONG_LONG_TYPE_SIZE
8370 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8373 #ifndef FLOAT_TYPE_SIZE
8374 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8377 #ifndef DOUBLE_TYPE_SIZE
8378 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8381 #ifndef LONG_DOUBLE_TYPE_SIZE
8382 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8386 sparc_type_code (register tree type)
8388 register unsigned long qualifiers = 0;
8389 register unsigned shift;
8391 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8392 setting more, since some assemblers will give an error for this. Also,
8393 we must be careful to avoid shifts of 32 bits or more to avoid getting
8394 unpredictable results. */
8396 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
8398 switch (TREE_CODE (type))
8404 qualifiers |= (3 << shift);
8409 qualifiers |= (2 << shift);
8413 case REFERENCE_TYPE:
8415 qualifiers |= (1 << shift);
8419 return (qualifiers | 8);
8422 case QUAL_UNION_TYPE:
8423 return (qualifiers | 9);
8426 return (qualifiers | 10);
8429 return (qualifiers | 16);
8432 /* If this is a range type, consider it to be the underlying
8434 if (TREE_TYPE (type) != 0)
8437 /* Carefully distinguish all the standard types of C,
8438 without messing up if the language is not C. We do this by
8439 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8440 look at both the names and the above fields, but that's redundant.
8441 Any type whose size is between two C types will be considered
8442 to be the wider of the two types. Also, we do not have a
8443 special code to use for "long long", so anything wider than
8444 long is treated the same. Note that we can't distinguish
8445 between "int" and "long" in this code if they are the same
8446 size, but that's fine, since neither can the assembler. */
8448 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8449 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
8451 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8452 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
8454 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8455 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
8458 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
8461 /* If this is a range type, consider it to be the underlying
8463 if (TREE_TYPE (type) != 0)
8466 /* Carefully distinguish all the standard types of C,
8467 without messing up if the language is not C. */
8469 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
8470 return (qualifiers | 6);
8473 return (qualifiers | 7);
8475 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
8476 /* ??? We need to distinguish between double and float complex types,
8477 but I don't know how yet because I can't reach this code from
8478 existing front-ends. */
8479 return (qualifiers | 7); /* Who knows? */
8482 case BOOLEAN_TYPE: /* Boolean truth value type. */
8488 gcc_unreachable (); /* Not a type! */
8495 /* Nested function support. */
8497 /* Emit RTL insns to initialize the variable parts of a trampoline.
8498 FNADDR is an RTX for the address of the function's pure code.
8499 CXT is an RTX for the static chain value for the function.
8501 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8502 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8503 (to store insns). This is a bit excessive. Perhaps a different
8504 mechanism would be better here.
8506 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8509 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8511 /* SPARC 32-bit trampoline:
8514 sethi %hi(static), %g2
8516 or %g2, %lo(static), %g2
8518 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8519 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8523 (adjust_address (m_tramp, SImode, 0),
8524 expand_binop (SImode, ior_optab,
8525 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
8526 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
8527 NULL_RTX, 1, OPTAB_DIRECT));
8530 (adjust_address (m_tramp, SImode, 4),
8531 expand_binop (SImode, ior_optab,
8532 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
8533 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
8534 NULL_RTX, 1, OPTAB_DIRECT));
8537 (adjust_address (m_tramp, SImode, 8),
8538 expand_binop (SImode, ior_optab,
8539 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
8540 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
8541 NULL_RTX, 1, OPTAB_DIRECT));
8544 (adjust_address (m_tramp, SImode, 12),
8545 expand_binop (SImode, ior_optab,
8546 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
8547 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
8548 NULL_RTX, 1, OPTAB_DIRECT));
8550 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8551 aligned on a 16 byte boundary so one flush clears it all. */
8552 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
8553 if (sparc_cpu != PROCESSOR_ULTRASPARC
8554 && sparc_cpu != PROCESSOR_ULTRASPARC3
8555 && sparc_cpu != PROCESSOR_NIAGARA
8556 && sparc_cpu != PROCESSOR_NIAGARA2
8557 && sparc_cpu != PROCESSOR_NIAGARA3
8558 && sparc_cpu != PROCESSOR_NIAGARA4)
8559 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
8561 /* Call __enable_execute_stack after writing onto the stack to make sure
8562 the stack address is accessible. */
8563 #ifdef HAVE_ENABLE_EXECUTE_STACK
8564 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8565 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8570 /* The 64-bit version is simpler because it makes more sense to load the
8571 values as "immediate" data out of the trampoline. It's also easier since
8572 we can read the PC without clobbering a register. */
8575 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8577 /* SPARC 64-bit trampoline:
8586 emit_move_insn (adjust_address (m_tramp, SImode, 0),
8587 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
8588 emit_move_insn (adjust_address (m_tramp, SImode, 4),
8589 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
8590 emit_move_insn (adjust_address (m_tramp, SImode, 8),
8591 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
8592 emit_move_insn (adjust_address (m_tramp, SImode, 12),
8593 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
8594 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
8595 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
8596 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
8598 if (sparc_cpu != PROCESSOR_ULTRASPARC
8599 && sparc_cpu != PROCESSOR_ULTRASPARC3
8600 && sparc_cpu != PROCESSOR_NIAGARA
8601 && sparc_cpu != PROCESSOR_NIAGARA2
8602 && sparc_cpu != PROCESSOR_NIAGARA3
8603 && sparc_cpu != PROCESSOR_NIAGARA4)
8604 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
8606 /* Call __enable_execute_stack after writing onto the stack to make sure
8607 the stack address is accessible. */
8608 #ifdef HAVE_ENABLE_EXECUTE_STACK
8609 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8610 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8614 /* Worker for TARGET_TRAMPOLINE_INIT. */
8617 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8619 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
8620 cxt = force_reg (Pmode, cxt);
8622 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
8624 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
8627 /* Adjust the cost of a scheduling dependency. Return the new cost of
8628 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8631 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8633 enum attr_type insn_type;
8635 if (! recog_memoized (insn))
8638 insn_type = get_attr_type (insn);
8640 if (REG_NOTE_KIND (link) == 0)
8642 /* Data dependency; DEP_INSN writes a register that INSN reads some
8645 /* if a load, then the dependence must be on the memory address;
8646 add an extra "cycle". Note that the cost could be two cycles
8647 if the reg was written late in an instruction group; we ca not tell
8649 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8652 /* Get the delay only if the address of the store is the dependence. */
8653 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8655 rtx pat = PATTERN(insn);
8656 rtx dep_pat = PATTERN (dep_insn);
8658 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8659 return cost; /* This should not happen! */
8661 /* The dependency between the two instructions was on the data that
8662 is being stored. Assume that this implies that the address of the
8663 store is not dependent. */
8664 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8667 return cost + 3; /* An approximation. */
8670 /* A shift instruction cannot receive its data from an instruction
8671 in the same cycle; add a one cycle penalty. */
8672 if (insn_type == TYPE_SHIFT)
8673 return cost + 3; /* Split before cascade into shift. */
8677 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8678 INSN writes some cycles later. */
8680 /* These are only significant for the fpu unit; writing a fp reg before
8681 the fpu has finished with it stalls the processor. */
8683 /* Reusing an integer register causes no problems. */
8684 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8692 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8694 enum attr_type insn_type, dep_type;
8695 rtx pat = PATTERN(insn);
8696 rtx dep_pat = PATTERN (dep_insn);
8698 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8701 insn_type = get_attr_type (insn);
8702 dep_type = get_attr_type (dep_insn);
8704 switch (REG_NOTE_KIND (link))
8707 /* Data dependency; DEP_INSN writes a register that INSN reads some
8714 /* Get the delay iff the address of the store is the dependence. */
8715 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8718 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8725 /* If a load, then the dependence must be on the memory address. If
8726 the addresses aren't equal, then it might be a false dependency */
8727 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8729 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8730 || GET_CODE (SET_DEST (dep_pat)) != MEM
8731 || GET_CODE (SET_SRC (pat)) != MEM
8732 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8733 XEXP (SET_SRC (pat), 0)))
8741 /* Compare to branch latency is 0. There is no benefit from
8742 separating compare and branch. */
8743 if (dep_type == TYPE_COMPARE)
8745 /* Floating point compare to branch latency is less than
8746 compare to conditional move. */
8747 if (dep_type == TYPE_FPCMP)
8756 /* Anti-dependencies only penalize the fpu unit. */
8757 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8769 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8773 case PROCESSOR_SUPERSPARC:
8774 cost = supersparc_adjust_cost (insn, link, dep, cost);
8776 case PROCESSOR_HYPERSPARC:
8777 case PROCESSOR_SPARCLITE86X:
8778 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8787 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8788 int sched_verbose ATTRIBUTE_UNUSED,
8789 int max_ready ATTRIBUTE_UNUSED)
8793 sparc_use_sched_lookahead (void)
8795 if (sparc_cpu == PROCESSOR_NIAGARA
8796 || sparc_cpu == PROCESSOR_NIAGARA2
8797 || sparc_cpu == PROCESSOR_NIAGARA3
8798 || sparc_cpu == PROCESSOR_NIAGARA4)
8800 if (sparc_cpu == PROCESSOR_ULTRASPARC
8801 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8803 if ((1 << sparc_cpu) &
8804 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8805 (1 << PROCESSOR_SPARCLITE86X)))
8811 sparc_issue_rate (void)
8815 case PROCESSOR_NIAGARA:
8816 case PROCESSOR_NIAGARA2:
8817 case PROCESSOR_NIAGARA3:
8818 case PROCESSOR_NIAGARA4:
8822 /* Assume V9 processors are capable of at least dual-issue. */
8824 case PROCESSOR_SUPERSPARC:
8826 case PROCESSOR_HYPERSPARC:
8827 case PROCESSOR_SPARCLITE86X:
8829 case PROCESSOR_ULTRASPARC:
8830 case PROCESSOR_ULTRASPARC3:
8836 set_extends (rtx insn)
8838 register rtx pat = PATTERN (insn);
8840 switch (GET_CODE (SET_SRC (pat)))
8842 /* Load and some shift instructions zero extend. */
8845 /* sethi clears the high bits */
8847 /* LO_SUM is used with sethi. sethi cleared the high
8848 bits and the values used with lo_sum are positive */
8850 /* Store flag stores 0 or 1 */
8860 rtx op0 = XEXP (SET_SRC (pat), 0);
8861 rtx op1 = XEXP (SET_SRC (pat), 1);
8862 if (GET_CODE (op1) == CONST_INT)
8863 return INTVAL (op1) >= 0;
8864 if (GET_CODE (op0) != REG)
8866 if (sparc_check_64 (op0, insn) == 1)
8868 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8873 rtx op0 = XEXP (SET_SRC (pat), 0);
8874 rtx op1 = XEXP (SET_SRC (pat), 1);
8875 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8877 if (GET_CODE (op1) == CONST_INT)
8878 return INTVAL (op1) >= 0;
8879 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8882 return GET_MODE (SET_SRC (pat)) == SImode;
8883 /* Positive integers leave the high bits zero. */
8885 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8887 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8890 return - (GET_MODE (SET_SRC (pat)) == SImode);
8892 return sparc_check_64 (SET_SRC (pat), insn);
8898 /* We _ought_ to have only one kind per function, but... */
8899 static GTY(()) rtx sparc_addr_diff_list;
8900 static GTY(()) rtx sparc_addr_list;
8903 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8905 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8907 sparc_addr_diff_list
8908 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8910 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8914 sparc_output_addr_vec (rtx vec)
8916 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8917 int idx, vlen = XVECLEN (body, 0);
8919 #ifdef ASM_OUTPUT_ADDR_VEC_START
8920 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8923 #ifdef ASM_OUTPUT_CASE_LABEL
8924 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8927 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8930 for (idx = 0; idx < vlen; idx++)
8932 ASM_OUTPUT_ADDR_VEC_ELT
8933 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8936 #ifdef ASM_OUTPUT_ADDR_VEC_END
8937 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8942 sparc_output_addr_diff_vec (rtx vec)
8944 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8945 rtx base = XEXP (XEXP (body, 0), 0);
8946 int idx, vlen = XVECLEN (body, 1);
8948 #ifdef ASM_OUTPUT_ADDR_VEC_START
8949 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8952 #ifdef ASM_OUTPUT_CASE_LABEL
8953 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8956 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8959 for (idx = 0; idx < vlen; idx++)
8961 ASM_OUTPUT_ADDR_DIFF_ELT
8964 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8965 CODE_LABEL_NUMBER (base));
8968 #ifdef ASM_OUTPUT_ADDR_VEC_END
8969 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8974 sparc_output_deferred_case_vectors (void)
8979 if (sparc_addr_list == NULL_RTX
8980 && sparc_addr_diff_list == NULL_RTX)
8983 /* Align to cache line in the function's code section. */
8984 switch_to_section (current_function_section ());
8986 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8988 ASM_OUTPUT_ALIGN (asm_out_file, align);
8990 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8991 sparc_output_addr_vec (XEXP (t, 0));
8992 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8993 sparc_output_addr_diff_vec (XEXP (t, 0));
8995 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8998 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8999 unknown. Return 1 if the high bits are zero, -1 if the register is
9002 sparc_check_64 (rtx x, rtx insn)
9004 /* If a register is set only once it is safe to ignore insns this
9005 code does not know how to handle. The loop will either recognize
9006 the single set and return the correct value or fail to recognize
9011 gcc_assert (GET_CODE (x) == REG);
9013 if (GET_MODE (x) == DImode)
9014 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
9016 if (flag_expensive_optimizations
9017 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
9023 insn = get_last_insn_anywhere ();
9028 while ((insn = PREV_INSN (insn)))
9030 switch (GET_CODE (insn))
9043 rtx pat = PATTERN (insn);
9044 if (GET_CODE (pat) != SET)
9046 if (rtx_equal_p (x, SET_DEST (pat)))
9047 return set_extends (insn);
9048 if (y && rtx_equal_p (y, SET_DEST (pat)))
9049 return set_extends (insn);
9050 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
9058 /* Returns assembly code to perform a DImode shift using
9059 a 64-bit global or out register on SPARC-V8+. */
9061 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
9063 static char asm_code[60];
9065 /* The scratch register is only required when the destination
9066 register is not a 64-bit global or out register. */
9067 if (which_alternative != 2)
9068 operands[3] = operands[0];
9070 /* We can only shift by constants <= 63. */
9071 if (GET_CODE (operands[2]) == CONST_INT)
9072 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
9074 if (GET_CODE (operands[1]) == CONST_INT)
9076 output_asm_insn ("mov\t%1, %3", operands);
9080 output_asm_insn ("sllx\t%H1, 32, %3", operands);
9081 if (sparc_check_64 (operands[1], insn) <= 0)
9082 output_asm_insn ("srl\t%L1, 0, %L1", operands);
9083 output_asm_insn ("or\t%L1, %3, %3", operands);
9086 strcpy(asm_code, opcode);
9088 if (which_alternative != 2)
9089 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9091 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9094 /* Output rtl to increment the profiler label LABELNO
9095 for profiling a function entry. */
9098 sparc_profile_hook (int labelno)
9103 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
9104 if (NO_PROFILE_COUNTERS)
9106 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
9110 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9111 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9112 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
9116 #ifdef TARGET_SOLARIS
9117 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9120 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
9121 tree decl ATTRIBUTE_UNUSED)
9123 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
9125 solaris_elf_asm_comdat_section (name, flags, decl);
9129 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
9131 if (!(flags & SECTION_DEBUG))
9132 fputs (",#alloc", asm_out_file);
9133 if (flags & SECTION_WRITE)
9134 fputs (",#write", asm_out_file);
9135 if (flags & SECTION_TLS)
9136 fputs (",#tls", asm_out_file);
9137 if (flags & SECTION_CODE)
9138 fputs (",#execinstr", asm_out_file);
9140 /* ??? Handle SECTION_BSS. */
9142 fputc ('\n', asm_out_file);
9144 #endif /* TARGET_SOLARIS */
9146 /* We do not allow indirect calls to be optimized into sibling calls.
9148 We cannot use sibling calls when delayed branches are disabled
9149 because they will likely require the call delay slot to be filled.
9151 Also, on SPARC 32-bit we cannot emit a sibling call when the
9152 current function returns a structure. This is because the "unimp
9153 after call" convention would cause the callee to return to the
9154 wrong place. The generic code already disallows cases where the
9155 function being called returns a structure.
9157 It may seem strange how this last case could occur. Usually there
9158 is code after the call which jumps to epilogue code which dumps the
9159 return value into the struct return area. That ought to invalidate
9160 the sibling call right? Well, in the C++ case we can end up passing
9161 the pointer to the struct return area to a constructor (which returns
9162 void) and then nothing else happens. Such a sibling call would look
9163 valid without the added check here.
9165 VxWorks PIC PLT entries require the global pointer to be initialized
9166 on entry. We therefore can't emit sibling calls to them. */
9168 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9171 && flag_delayed_branch
9172 && (TARGET_ARCH64 || ! cfun->returns_struct)
9173 && !(TARGET_VXWORKS_RTP
9175 && !targetm.binds_local_p (decl)));
9178 /* libfunc renaming. */
9181 sparc_init_libfuncs (void)
9185 /* Use the subroutines that Sun's library provides for integer
9186 multiply and divide. The `*' prevents an underscore from
9187 being prepended by the compiler. .umul is a little faster
9189 set_optab_libfunc (smul_optab, SImode, "*.umul");
9190 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9191 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9192 set_optab_libfunc (smod_optab, SImode, "*.rem");
9193 set_optab_libfunc (umod_optab, SImode, "*.urem");
9195 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9196 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9197 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9198 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9199 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9200 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9202 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9203 is because with soft-float, the SFmode and DFmode sqrt
9204 instructions will be absent, and the compiler will notice and
9205 try to use the TFmode sqrt instruction for calls to the
9206 builtin function sqrt, but this fails. */
9208 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9210 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9211 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
9212 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
9213 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
9214 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
9215 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
9217 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9218 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9219 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9220 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9222 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9223 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9224 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9225 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
9227 if (DITF_CONVERSION_LIBFUNCS)
9229 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9230 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9231 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9232 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
9235 if (SUN_CONVERSION_LIBFUNCS)
9237 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9238 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9239 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9240 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9245 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9246 do not exist in the library. Make sure the compiler does not
9247 emit calls to them by accident. (It should always use the
9248 hardware instructions.) */
9249 set_optab_libfunc (smul_optab, SImode, 0);
9250 set_optab_libfunc (sdiv_optab, SImode, 0);
9251 set_optab_libfunc (udiv_optab, SImode, 0);
9252 set_optab_libfunc (smod_optab, SImode, 0);
9253 set_optab_libfunc (umod_optab, SImode, 0);
9255 if (SUN_INTEGER_MULTIPLY_64)
9257 set_optab_libfunc (smul_optab, DImode, "__mul64");
9258 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9259 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9260 set_optab_libfunc (smod_optab, DImode, "__rem64");
9261 set_optab_libfunc (umod_optab, DImode, "__urem64");
9264 if (SUN_CONVERSION_LIBFUNCS)
9266 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9267 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9268 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9269 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
9274 static tree def_builtin(const char *name, int code, tree type)
9276 return add_builtin_function(name, type, code, BUILT_IN_MD, NULL,
9280 static tree def_builtin_const(const char *name, int code, tree type)
9282 tree t = def_builtin(name, code, type);
9285 TREE_READONLY (t) = 1;
9290 /* Implement the TARGET_INIT_BUILTINS target hook.
9291 Create builtin functions for special SPARC instructions. */
9294 sparc_init_builtins (void)
9297 sparc_vis_init_builtins ();
9300 /* Create builtin functions for VIS 1.0 instructions. */
9303 sparc_vis_init_builtins (void)
9305 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
9306 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
9307 tree v4hi = build_vector_type (intHI_type_node, 4);
9308 tree v2hi = build_vector_type (intHI_type_node, 2);
9309 tree v2si = build_vector_type (intSI_type_node, 2);
9310 tree v1si = build_vector_type (intSI_type_node, 1);
9312 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
9313 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
9314 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
9315 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
9316 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
9317 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
9318 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
9319 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
9320 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
9321 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
9322 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
9323 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
9324 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0);
9325 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0);
9326 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
9328 intDI_type_node, 0);
9329 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node,
9331 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
9333 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
9335 intDI_type_node, 0);
9336 tree si_ftype_si_si = build_function_type_list (intSI_type_node,
9338 intSI_type_node, 0);
9339 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
9341 intSI_type_node, 0);
9342 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
9344 intDI_type_node, 0);
9345 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
9348 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
9351 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
9353 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
9355 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
9357 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
9359 tree void_ftype_di = build_function_type_list (void_type_node,
9360 intDI_type_node, 0);
9361 tree di_ftype_void = build_function_type_list (intDI_type_node,
9363 tree void_ftype_si = build_function_type_list (void_type_node,
9364 intSI_type_node, 0);
9365 tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
9367 float_type_node, 0);
9368 tree df_ftype_df_df = build_function_type_list (double_type_node,
9370 double_type_node, 0);
9372 /* Packing and expanding vectors. */
9373 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
9375 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
9376 v8qi_ftype_v2si_v8qi);
9377 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
9379 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
9381 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
9382 v8qi_ftype_v4qi_v4qi);
9384 /* Multiplications. */
9385 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
9386 v4hi_ftype_v4qi_v4hi);
9387 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
9388 v4hi_ftype_v4qi_v2hi);
9389 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
9390 v4hi_ftype_v4qi_v2hi);
9391 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
9392 v4hi_ftype_v8qi_v4hi);
9393 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
9394 v4hi_ftype_v8qi_v4hi);
9395 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
9396 v2si_ftype_v4qi_v2hi);
9397 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
9398 v2si_ftype_v4qi_v2hi);
9400 /* Data aligning. */
9401 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
9402 v4hi_ftype_v4hi_v4hi);
9403 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
9404 v8qi_ftype_v8qi_v8qi);
9405 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
9406 v2si_ftype_v2si_v2si);
9407 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis,
9410 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
9412 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
9417 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
9419 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
9424 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
9426 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
9430 /* Pixel distance. */
9431 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
9432 di_ftype_v8qi_v8qi_di);
9434 /* Edge handling. */
9437 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
9439 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
9441 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
9443 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
9445 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
9447 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
9451 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis,
9453 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis,
9455 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis,
9457 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis,
9459 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis,
9461 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis,
9467 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
9469 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
9471 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
9473 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
9475 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
9477 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
9481 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis,
9483 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis,
9485 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis,
9487 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis,
9489 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis,
9491 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis,
9496 /* Pixel compare. */
9499 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
9500 di_ftype_v4hi_v4hi);
9501 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
9502 di_ftype_v2si_v2si);
9503 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
9504 di_ftype_v4hi_v4hi);
9505 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
9506 di_ftype_v2si_v2si);
9507 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
9508 di_ftype_v4hi_v4hi);
9509 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
9510 di_ftype_v2si_v2si);
9511 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
9512 di_ftype_v4hi_v4hi);
9513 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
9514 di_ftype_v2si_v2si);
9518 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
9519 si_ftype_v4hi_v4hi);
9520 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
9521 si_ftype_v2si_v2si);
9522 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
9523 si_ftype_v4hi_v4hi);
9524 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
9525 si_ftype_v2si_v2si);
9526 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
9527 si_ftype_v4hi_v4hi);
9528 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
9529 si_ftype_v2si_v2si);
9530 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
9531 si_ftype_v4hi_v4hi);
9532 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
9533 si_ftype_v2si_v2si);
9536 /* Addition and subtraction. */
9537 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3,
9538 v4hi_ftype_v4hi_v4hi);
9539 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3,
9540 v2hi_ftype_v2hi_v2hi);
9541 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3,
9542 v2si_ftype_v2si_v2si);
9543 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3,
9544 v1si_ftype_v1si_v1si);
9545 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3,
9546 v4hi_ftype_v4hi_v4hi);
9547 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3,
9548 v2hi_ftype_v2hi_v2hi);
9549 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3,
9550 v2si_ftype_v2si_v2si);
9551 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3,
9552 v1si_ftype_v1si_v1si);
9554 /* Three-dimensional array addressing. */
9557 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis,
9559 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis,
9561 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis,
9566 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis,
9568 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis,
9570 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis,
9576 /* Byte mask and shuffle */
9578 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis,
9581 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis,
9583 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis,
9584 v4hi_ftype_v4hi_v4hi);
9585 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis,
9586 v8qi_ftype_v8qi_v8qi);
9587 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis,
9588 v2si_ftype_v2si_v2si);
9589 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis,
9597 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis,
9599 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis,
9601 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis,
9606 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis,
9608 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis,
9610 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis,
9614 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis,
9615 v4hi_ftype_v4hi_v4hi);
9617 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3,
9618 v4hi_ftype_v4hi_v4hi);
9619 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3,
9620 v4hi_ftype_v4hi_v4hi);
9621 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3,
9622 v4hi_ftype_v4hi_v4hi);
9623 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3,
9624 v4hi_ftype_v4hi_v4hi);
9625 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3,
9626 v2si_ftype_v2si_v2si);
9627 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3,
9628 v2si_ftype_v2si_v2si);
9629 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3,
9630 v2si_ftype_v2si_v2si);
9631 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3,
9632 v2si_ftype_v2si_v2si);
9635 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis,
9636 di_ftype_v8qi_v8qi);
9638 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis,
9639 si_ftype_v8qi_v8qi);
9641 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
9642 v4hi_ftype_v4hi_v4hi);
9643 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
9645 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
9648 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
9649 v4hi_ftype_v4hi_v4hi);
9650 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3,
9651 v2hi_ftype_v2hi_v2hi);
9652 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3,
9653 v4hi_ftype_v4hi_v4hi);
9654 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3,
9655 v2hi_ftype_v2hi_v2hi);
9656 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3,
9657 v2si_ftype_v2si_v2si);
9658 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3,
9659 v1si_ftype_v1si_v1si);
9660 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3,
9661 v2si_ftype_v2si_v2si);
9662 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
9663 v1si_ftype_v1si_v1si);
9667 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis,
9668 di_ftype_v8qi_v8qi);
9669 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis,
9670 di_ftype_v8qi_v8qi);
9671 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis,
9672 di_ftype_v8qi_v8qi);
9673 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis,
9674 di_ftype_v8qi_v8qi);
9678 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis,
9679 si_ftype_v8qi_v8qi);
9680 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis,
9681 si_ftype_v8qi_v8qi);
9682 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis,
9683 si_ftype_v8qi_v8qi);
9684 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
9685 si_ftype_v8qi_v8qi);
9688 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
9690 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
9692 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
9694 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
9696 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
9698 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
9701 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
9703 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
9705 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
9710 /* Handle TARGET_EXPAND_BUILTIN target hook.
9711 Expand builtin functions for sparc intrinsics. */
9714 sparc_expand_builtin (tree exp, rtx target,
9715 rtx subtarget ATTRIBUTE_UNUSED,
9716 enum machine_mode tmode ATTRIBUTE_UNUSED,
9717 int ignore ATTRIBUTE_UNUSED)
9720 call_expr_arg_iterator iter;
9721 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9722 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
9727 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9731 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9733 || GET_MODE (target) != tmode
9734 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9735 op[0] = gen_reg_rtx (tmode);
9739 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9741 const struct insn_operand_data *insn_op;
9744 if (arg == error_mark_node)
9748 idx = arg_count - !nonvoid;
9749 insn_op = &insn_data[icode].operand[idx];
9750 op[arg_count] = expand_normal (arg);
9752 if (insn_op->mode == V1DImode
9753 && GET_MODE (op[arg_count]) == DImode)
9754 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]);
9755 else if (insn_op->mode == V1SImode
9756 && GET_MODE (op[arg_count]) == SImode)
9757 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]);
9759 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
9761 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
9767 pat = GEN_FCN (icode) (op[0]);
9771 pat = GEN_FCN (icode) (op[0], op[1]);
9773 pat = GEN_FCN (icode) (op[1]);
9776 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9779 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9797 sparc_vis_mul8x16 (int e8, int e16)
9799 return (e8 * e16 + 128) / 256;
9802 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9803 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9804 constants. A tree list with the results of the multiplications is returned,
9805 and each element in the list is of INNER_TYPE. */
9808 sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
9810 tree n_elts = NULL_TREE;
9815 case CODE_FOR_fmul8x16_vis:
9816 for (; elts0 && elts1;
9817 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9820 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9821 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
9822 n_elts = tree_cons (NULL_TREE,
9823 build_int_cst (inner_type, val),
9828 case CODE_FOR_fmul8x16au_vis:
9829 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9831 for (; elts0; elts0 = TREE_CHAIN (elts0))
9834 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9836 n_elts = tree_cons (NULL_TREE,
9837 build_int_cst (inner_type, val),
9842 case CODE_FOR_fmul8x16al_vis:
9843 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
9845 for (; elts0; elts0 = TREE_CHAIN (elts0))
9848 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9850 n_elts = tree_cons (NULL_TREE,
9851 build_int_cst (inner_type, val),
9860 return nreverse (n_elts);
9863 /* Handle TARGET_FOLD_BUILTIN target hook.
9864 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9865 result of the function call is ignored. NULL_TREE is returned if the
9866 function could not be folded. */
9869 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
9870 tree *args, bool ignore)
9872 tree arg0, arg1, arg2;
9873 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
9874 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
9878 /* Note that a switch statement instead of the sequence of tests would
9879 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9880 and that would yield multiple alternatives with identical values. */
9881 if (icode == CODE_FOR_alignaddrsi_vis
9882 || icode == CODE_FOR_alignaddrdi_vis
9883 || icode == CODE_FOR_wrgsr_vis
9884 || icode == CODE_FOR_bmasksi_vis
9885 || icode == CODE_FOR_bmaskdi_vis
9886 || icode == CODE_FOR_cmask8si_vis
9887 || icode == CODE_FOR_cmask8di_vis
9888 || icode == CODE_FOR_cmask16si_vis
9889 || icode == CODE_FOR_cmask16di_vis
9890 || icode == CODE_FOR_cmask32si_vis
9891 || icode == CODE_FOR_cmask32di_vis)
9894 return build_zero_cst (rtype);
9899 case CODE_FOR_fexpand_vis:
9903 if (TREE_CODE (arg0) == VECTOR_CST)
9905 tree inner_type = TREE_TYPE (rtype);
9906 tree elts = TREE_VECTOR_CST_ELTS (arg0);
9907 tree n_elts = NULL_TREE;
9909 for (; elts; elts = TREE_CHAIN (elts))
9911 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
9912 n_elts = tree_cons (NULL_TREE,
9913 build_int_cst (inner_type, val),
9916 return build_vector (rtype, nreverse (n_elts));
9920 case CODE_FOR_fmul8x16_vis:
9921 case CODE_FOR_fmul8x16au_vis:
9922 case CODE_FOR_fmul8x16al_vis:
9928 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9930 tree inner_type = TREE_TYPE (rtype);
9931 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9932 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9933 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
9936 return build_vector (rtype, n_elts);
9940 case CODE_FOR_fpmerge_vis:
9946 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
9948 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9949 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9950 tree n_elts = NULL_TREE;
9952 for (; elts0 && elts1;
9953 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9955 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
9956 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
9959 return build_vector (rtype, nreverse (n_elts));
9963 case CODE_FOR_pdist_vis:
9971 if (TREE_CODE (arg0) == VECTOR_CST
9972 && TREE_CODE (arg1) == VECTOR_CST
9973 && TREE_CODE (arg2) == INTEGER_CST)
9976 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
9977 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
9978 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
9979 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
9981 for (; elts0 && elts1;
9982 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9984 unsigned HOST_WIDE_INT
9985 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9986 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9987 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
9988 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
9990 unsigned HOST_WIDE_INT l;
9993 overflow |= neg_double (low1, high1, &l, &h);
9994 overflow |= add_double (low0, high0, l, h, &l, &h);
9996 overflow |= neg_double (l, h, &l, &h);
9998 overflow |= add_double (low, high, l, h, &low, &high);
10001 gcc_assert (overflow == 0);
10003 return build_int_cst_wide (rtype, low, high);
10013 /* ??? This duplicates information provided to the compiler by the
10014 ??? scheduler description. Some day, teach genautomata to output
10015 ??? the latencies and then CSE will just use that. */
10018 sparc_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
10019 int *total, bool speed ATTRIBUTE_UNUSED)
10021 enum machine_mode mode = GET_MODE (x);
10022 bool float_mode_p = FLOAT_MODE_P (mode);
10027 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
10045 if (GET_MODE (x) == VOIDmode
10046 && ((CONST_DOUBLE_HIGH (x) == 0
10047 && CONST_DOUBLE_LOW (x) < 0x1000)
10048 || (CONST_DOUBLE_HIGH (x) == -1
10049 && CONST_DOUBLE_LOW (x) < 0
10050 && CONST_DOUBLE_LOW (x) >= -0x1000)))
10057 /* If outer-code was a sign or zero extension, a cost
10058 of COSTS_N_INSNS (1) was already added in. This is
10059 why we are subtracting it back out. */
10060 if (outer_code == ZERO_EXTEND)
10062 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
10064 else if (outer_code == SIGN_EXTEND)
10066 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
10068 else if (float_mode_p)
10070 *total = sparc_costs->float_load;
10074 *total = sparc_costs->int_load;
10082 *total = sparc_costs->float_plusminus;
10084 *total = COSTS_N_INSNS (1);
10091 gcc_assert (float_mode_p);
10092 *total = sparc_costs->float_mul;
10095 if (GET_CODE (sub) == NEG)
10096 sub = XEXP (sub, 0);
10097 *total += rtx_cost (sub, FMA, 0, speed);
10100 if (GET_CODE (sub) == NEG)
10101 sub = XEXP (sub, 0);
10102 *total += rtx_cost (sub, FMA, 2, speed);
10108 *total = sparc_costs->float_mul;
10109 else if (! TARGET_HARD_MUL)
10110 *total = COSTS_N_INSNS (25);
10116 if (sparc_costs->int_mul_bit_factor)
10120 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
10122 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
10123 for (nbits = 0; value != 0; value &= value - 1)
10126 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
10127 && GET_MODE (XEXP (x, 1)) == VOIDmode)
10129 rtx x1 = XEXP (x, 1);
10130 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
10131 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
10133 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
10135 for (; value2 != 0; value2 &= value2 - 1)
10143 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
10144 bit_cost = COSTS_N_INSNS (bit_cost);
10147 if (mode == DImode)
10148 *total = sparc_costs->int_mulX + bit_cost;
10150 *total = sparc_costs->int_mul + bit_cost;
10157 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
10166 if (mode == DFmode)
10167 *total = sparc_costs->float_div_df;
10169 *total = sparc_costs->float_div_sf;
10173 if (mode == DImode)
10174 *total = sparc_costs->int_divX;
10176 *total = sparc_costs->int_div;
10181 if (! float_mode_p)
10183 *total = COSTS_N_INSNS (1);
10190 case UNSIGNED_FLOAT:
10194 case FLOAT_TRUNCATE:
10195 *total = sparc_costs->float_move;
10199 if (mode == DFmode)
10200 *total = sparc_costs->float_sqrt_df;
10202 *total = sparc_costs->float_sqrt_sf;
10207 *total = sparc_costs->float_cmp;
10209 *total = COSTS_N_INSNS (1);
10214 *total = sparc_costs->float_cmove;
10216 *total = sparc_costs->int_cmove;
10220 /* Handle the NAND vector patterns. */
10221 if (sparc_vector_mode_supported_p (GET_MODE (x))
10222 && GET_CODE (XEXP (x, 0)) == NOT
10223 && GET_CODE (XEXP (x, 1)) == NOT)
10225 *total = COSTS_N_INSNS (1);
10236 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10239 general_or_i64_p (reg_class_t rclass)
10241 return (rclass == GENERAL_REGS || rclass == I64_REGS);
10244 /* Implement TARGET_REGISTER_MOVE_COST. */
10247 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10248 reg_class_t from, reg_class_t to)
10250 if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
10251 || (general_or_i64_p (from) && FP_REG_CLASS_P (to))
10252 || from == FPCC_REGS
10253 || to == FPCC_REGS)
10255 if (sparc_cpu == PROCESSOR_ULTRASPARC
10256 || sparc_cpu == PROCESSOR_ULTRASPARC3
10257 || sparc_cpu == PROCESSOR_NIAGARA
10258 || sparc_cpu == PROCESSOR_NIAGARA2
10259 || sparc_cpu == PROCESSOR_NIAGARA3
10260 || sparc_cpu == PROCESSOR_NIAGARA4)
10269 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10270 This is achieved by means of a manual dynamic stack space allocation in
10271 the current frame. We make the assumption that SEQ doesn't contain any
10272 function calls, with the possible exception of calls to the GOT helper. */
10275 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
10277 /* We must preserve the lowest 16 words for the register save area. */
10278 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
10279 /* We really need only 2 words of fresh stack space. */
10280 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
10283 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
10284 SPARC_STACK_BIAS + offset));
10286 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
10287 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
10289 emit_insn (gen_rtx_SET (VOIDmode,
10290 adjust_address (slot, word_mode, UNITS_PER_WORD),
10294 emit_insn (gen_rtx_SET (VOIDmode,
10296 adjust_address (slot, word_mode, UNITS_PER_WORD)));
10297 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
10298 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
10301 /* Output the assembler code for a thunk function. THUNK_DECL is the
10302 declaration for the thunk function itself, FUNCTION is the decl for
10303 the target function. DELTA is an immediate constant offset to be
10304 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10305 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10308 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10309 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10312 rtx this_rtx, insn, funexp;
10313 unsigned int int_arg_first;
10315 reload_completed = 1;
10316 epilogue_completed = 1;
10318 emit_note (NOTE_INSN_PROLOGUE_END);
10322 sparc_leaf_function_p = 1;
10324 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10326 else if (flag_delayed_branch)
10328 /* We will emit a regular sibcall below, so we need to instruct
10329 output_sibcall that we are in a leaf function. */
10330 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
10332 /* This will cause final.c to invoke leaf_renumber_regs so we
10333 must behave as if we were in a not-yet-leafified function. */
10334 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
10338 /* We will emit the sibcall manually below, so we will need to
10339 manually spill non-leaf registers. */
10340 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
10342 /* We really are in a leaf function. */
10343 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10346 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10347 returns a structure, the structure return pointer is there instead. */
10349 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10350 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
10352 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
10354 /* Add DELTA. When possible use a plain add, otherwise load it into
10355 a register first. */
10358 rtx delta_rtx = GEN_INT (delta);
10360 if (! SPARC_SIMM13_P (delta))
10362 rtx scratch = gen_rtx_REG (Pmode, 1);
10363 emit_move_insn (scratch, delta_rtx);
10364 delta_rtx = scratch;
10367 /* THIS_RTX += DELTA. */
10368 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
10371 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10374 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10375 rtx scratch = gen_rtx_REG (Pmode, 1);
10377 gcc_assert (vcall_offset < 0);
10379 /* SCRATCH = *THIS_RTX. */
10380 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
10382 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10383 may not have any available scratch register at this point. */
10384 if (SPARC_SIMM13_P (vcall_offset))
10386 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10387 else if (! fixed_regs[5]
10388 /* The below sequence is made up of at least 2 insns,
10389 while the default method may need only one. */
10390 && vcall_offset < -8192)
10392 rtx scratch2 = gen_rtx_REG (Pmode, 5);
10393 emit_move_insn (scratch2, vcall_offset_rtx);
10394 vcall_offset_rtx = scratch2;
10398 rtx increment = GEN_INT (-4096);
10400 /* VCALL_OFFSET is a negative number whose typical range can be
10401 estimated as -32768..0 in 32-bit mode. In almost all cases
10402 it is therefore cheaper to emit multiple add insns than
10403 spilling and loading the constant into a register (at least
10405 while (! SPARC_SIMM13_P (vcall_offset))
10407 emit_insn (gen_add2_insn (scratch, increment));
10408 vcall_offset += 4096;
10410 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
10413 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10414 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
10415 gen_rtx_PLUS (Pmode,
10417 vcall_offset_rtx)));
10419 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10420 emit_insn (gen_add2_insn (this_rtx, scratch));
10423 /* Generate a tail call to the target function. */
10424 if (! TREE_USED (function))
10426 assemble_external (function);
10427 TREE_USED (function) = 1;
10429 funexp = XEXP (DECL_RTL (function), 0);
10431 if (flag_delayed_branch)
10433 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10434 insn = emit_call_insn (gen_sibcall (funexp));
10435 SIBLING_CALL_P (insn) = 1;
10439 /* The hoops we have to jump through in order to generate a sibcall
10440 without using delay slots... */
10441 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
10445 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
10447 load_got_register (); /* clobbers %o7 */
10448 scratch = sparc_legitimize_pic_address (funexp, scratch);
10449 seq = get_insns ();
10451 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
10453 else if (TARGET_ARCH32)
10455 emit_insn (gen_rtx_SET (VOIDmode,
10457 gen_rtx_HIGH (SImode, funexp)));
10458 emit_insn (gen_rtx_SET (VOIDmode,
10460 gen_rtx_LO_SUM (SImode, scratch, funexp)));
10462 else /* TARGET_ARCH64 */
10464 switch (sparc_cmodel)
10468 /* The destination can serve as a temporary. */
10469 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
10474 /* The destination cannot serve as a temporary. */
10475 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
10477 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
10478 seq = get_insns ();
10480 emit_and_preserve (seq, spill_reg, 0);
10484 gcc_unreachable ();
10488 emit_jump_insn (gen_indirect_jump (scratch));
10493 /* Run just enough of rest_of_compilation to get the insns emitted.
10494 There's not really enough bulk here to make other passes such as
10495 instruction scheduling worth while. Note that use_thunk calls
10496 assemble_start_function and assemble_end_function. */
10497 insn = get_insns ();
10498 insn_locators_alloc ();
10499 shorten_branches (insn);
10500 final_start_function (insn, file, 1);
10501 final (insn, file, 1);
10502 final_end_function ();
10504 reload_completed = 0;
10505 epilogue_completed = 0;
10508 /* Return true if sparc_output_mi_thunk would be able to output the
10509 assembler code for the thunk function specified by the arguments
10510 it is passed, and false otherwise. */
10512 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
10513 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
10514 HOST_WIDE_INT vcall_offset,
10515 const_tree function ATTRIBUTE_UNUSED)
10517 /* Bound the loop used in the default method above. */
10518 return (vcall_offset >= -32768 || ! fixed_regs[5]);
10521 /* We use the machine specific reorg pass to enable workarounds for errata. */
10528 /* The only erratum we handle for now is that of the AT697F processor. */
10529 if (!sparc_fix_at697f)
10532 /* We need to have the (essentially) final form of the insn stream in order
10533 to properly detect the various hazards. Run delay slot scheduling. */
10534 if (optimize > 0 && flag_delayed_branch)
10535 dbr_schedule (get_insns ());
10537 /* Now look for specific patterns in the insn stream. */
10538 for (insn = get_insns (); insn; insn = next)
10540 bool insert_nop = false;
10543 /* Look for a single-word load into an odd-numbered FP register. */
10544 if (NONJUMP_INSN_P (insn)
10545 && (set = single_set (insn)) != NULL_RTX
10546 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
10547 && MEM_P (SET_SRC (set))
10548 && REG_P (SET_DEST (set))
10549 && REGNO (SET_DEST (set)) > 31
10550 && REGNO (SET_DEST (set)) % 2 != 0)
10552 /* The wrong dependency is on the enclosing double register. */
10553 unsigned int x = REGNO (SET_DEST (set)) - 1;
10554 unsigned int src1, src2, dest;
10557 /* If the insn has a delay slot, then it cannot be problematic. */
10558 next = next_active_insn (insn);
10559 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
10563 extract_insn (next);
10564 code = INSN_CODE (next);
10569 case CODE_FOR_adddf3:
10570 case CODE_FOR_subdf3:
10571 case CODE_FOR_muldf3:
10572 case CODE_FOR_divdf3:
10573 dest = REGNO (recog_data.operand[0]);
10574 src1 = REGNO (recog_data.operand[1]);
10575 src2 = REGNO (recog_data.operand[2]);
10579 ld [address], %fx+1
10580 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10581 if ((src1 == x || src2 == x)
10582 && (dest == src1 || dest == src2))
10588 ld [address], %fx+1
10589 FPOPd %fx, %fx, %fx */
10592 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
10597 case CODE_FOR_sqrtdf2:
10598 dest = REGNO (recog_data.operand[0]);
10599 src1 = REGNO (recog_data.operand[1]);
10601 ld [address], %fx+1
10603 if (src1 == x && dest == src1)
10612 next = NEXT_INSN (insn);
10615 emit_insn_after (gen_nop (), insn);
10619 /* How to allocate a 'struct machine_function'. */
10621 static struct machine_function *
10622 sparc_init_machine_status (void)
10624 return ggc_alloc_cleared_machine_function ();
10627 /* Locate some local-dynamic symbol still in use by this function
10628 so that we can print its name in local-dynamic base patterns. */
10630 static const char *
10631 get_some_local_dynamic_name (void)
10635 if (cfun->machine->some_ld_name)
10636 return cfun->machine->some_ld_name;
10638 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10640 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10641 return cfun->machine->some_ld_name;
10643 gcc_unreachable ();
10647 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10652 && GET_CODE (x) == SYMBOL_REF
10653 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10655 cfun->machine->some_ld_name = XSTR (x, 0);
10662 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10663 We need to emit DTP-relative relocations. */
10666 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
10671 fputs ("\t.word\t%r_tls_dtpoff32(", file);
10674 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
10677 gcc_unreachable ();
10679 output_addr_const (file, x);
10683 /* Do whatever processing is required at the end of a file. */
10686 sparc_file_end (void)
10688 /* If we need to emit the special GOT helper function, do so now. */
10689 if (got_helper_rtx)
10691 const char *name = XSTR (got_helper_rtx, 0);
10692 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
10693 #ifdef DWARF2_UNWIND_INFO
10697 if (USE_HIDDEN_LINKONCE)
10699 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
10700 get_identifier (name),
10701 build_function_type_list (void_type_node,
10703 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
10704 NULL_TREE, void_type_node);
10705 TREE_STATIC (decl) = 1;
10706 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
10707 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
10708 DECL_VISIBILITY_SPECIFIED (decl) = 1;
10709 resolve_unique_section (decl, 0, flag_function_sections);
10710 allocate_struct_function (decl, true);
10711 cfun->is_thunk = 1;
10712 current_function_decl = decl;
10713 init_varasm_status ();
10714 assemble_start_function (decl, name);
10718 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10719 switch_to_section (text_section);
10721 ASM_OUTPUT_ALIGN (asm_out_file, align);
10722 ASM_OUTPUT_LABEL (asm_out_file, name);
10725 #ifdef DWARF2_UNWIND_INFO
10726 do_cfi = dwarf2out_do_cfi_asm ();
10728 fprintf (asm_out_file, "\t.cfi_startproc\n");
10730 if (flag_delayed_branch)
10731 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10732 reg_name, reg_name);
10734 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10735 reg_name, reg_name);
10736 #ifdef DWARF2_UNWIND_INFO
10738 fprintf (asm_out_file, "\t.cfi_endproc\n");
10742 if (NEED_INDICATE_EXEC_STACK)
10743 file_end_indicate_exec_stack ();
10745 #ifdef TARGET_SOLARIS
10746 solaris_file_end ();
10750 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10751 /* Implement TARGET_MANGLE_TYPE. */
10753 static const char *
10754 sparc_mangle_type (const_tree type)
10757 && TYPE_MAIN_VARIANT (type) == long_double_type_node
10758 && TARGET_LONG_DOUBLE_128)
10761 /* For all other types, use normal C++ mangling. */
10766 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10767 compare and swap on the word containing the byte or half-word. */
10770 sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
10772 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
10773 rtx addr = gen_reg_rtx (Pmode);
10774 rtx off = gen_reg_rtx (SImode);
10775 rtx oldv = gen_reg_rtx (SImode);
10776 rtx newv = gen_reg_rtx (SImode);
10777 rtx oldvalue = gen_reg_rtx (SImode);
10778 rtx newvalue = gen_reg_rtx (SImode);
10779 rtx res = gen_reg_rtx (SImode);
10780 rtx resv = gen_reg_rtx (SImode);
10781 rtx memsi, val, mask, end_label, loop_label, cc;
10783 emit_insn (gen_rtx_SET (VOIDmode, addr,
10784 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
10786 if (Pmode != SImode)
10787 addr1 = gen_lowpart (SImode, addr1);
10788 emit_insn (gen_rtx_SET (VOIDmode, off,
10789 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
10791 memsi = gen_rtx_MEM (SImode, addr);
10792 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
10793 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
10795 val = force_reg (SImode, memsi);
10797 emit_insn (gen_rtx_SET (VOIDmode, off,
10798 gen_rtx_XOR (SImode, off,
10799 GEN_INT (GET_MODE (mem) == QImode
10802 emit_insn (gen_rtx_SET (VOIDmode, off,
10803 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
10805 if (GET_MODE (mem) == QImode)
10806 mask = force_reg (SImode, GEN_INT (0xff));
10808 mask = force_reg (SImode, GEN_INT (0xffff));
10810 emit_insn (gen_rtx_SET (VOIDmode, mask,
10811 gen_rtx_ASHIFT (SImode, mask, off)));
10813 emit_insn (gen_rtx_SET (VOIDmode, val,
10814 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10817 oldval = gen_lowpart (SImode, oldval);
10818 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10819 gen_rtx_ASHIFT (SImode, oldval, off)));
10821 newval = gen_lowpart_common (SImode, newval);
10822 emit_insn (gen_rtx_SET (VOIDmode, newv,
10823 gen_rtx_ASHIFT (SImode, newval, off)));
10825 emit_insn (gen_rtx_SET (VOIDmode, oldv,
10826 gen_rtx_AND (SImode, oldv, mask)));
10828 emit_insn (gen_rtx_SET (VOIDmode, newv,
10829 gen_rtx_AND (SImode, newv, mask)));
10831 end_label = gen_label_rtx ();
10832 loop_label = gen_label_rtx ();
10833 emit_label (loop_label);
10835 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
10836 gen_rtx_IOR (SImode, oldv, val)));
10838 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
10839 gen_rtx_IOR (SImode, newv, val)));
10841 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue));
10843 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
10845 emit_insn (gen_rtx_SET (VOIDmode, resv,
10846 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
10849 cc = gen_compare_reg_1 (NE, resv, val);
10850 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
10852 /* Use cbranchcc4 to separate the compare and branch! */
10853 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
10854 cc, const0_rtx, loop_label));
10856 emit_label (end_label);
10858 emit_insn (gen_rtx_SET (VOIDmode, res,
10859 gen_rtx_AND (SImode, res, mask)));
10861 emit_insn (gen_rtx_SET (VOIDmode, res,
10862 gen_rtx_LSHIFTRT (SImode, res, off)));
10864 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
10868 sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
10872 sel = gen_lowpart (DImode, sel);
10876 /* inp = xxxxxxxAxxxxxxxB */
10877 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10878 NULL_RTX, 1, OPTAB_DIRECT);
10879 /* t_1 = ....xxxxxxxAxxx. */
10880 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
10881 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
10882 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
10883 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
10884 /* sel = .......B */
10885 /* t_1 = ...A.... */
10886 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
10887 /* sel = ...A...B */
10888 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
10889 /* sel = AAAABBBB * 4 */
10890 t_1 = force_reg (SImode, GEN_INT (0x01230123));
10891 /* sel = { A*4, A*4+1, A*4+2, ... } */
10895 /* inp = xxxAxxxBxxxCxxxD */
10896 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
10897 NULL_RTX, 1, OPTAB_DIRECT);
10898 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10899 NULL_RTX, 1, OPTAB_DIRECT);
10900 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
10901 NULL_RTX, 1, OPTAB_DIRECT);
10902 /* t_1 = ..xxxAxxxBxxxCxx */
10903 /* t_2 = ....xxxAxxxBxxxC */
10904 /* t_3 = ......xxxAxxxBxx */
10905 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
10907 NULL_RTX, 1, OPTAB_DIRECT);
10908 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
10910 NULL_RTX, 1, OPTAB_DIRECT);
10911 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
10912 GEN_INT (0x070000),
10913 NULL_RTX, 1, OPTAB_DIRECT);
10914 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
10915 GEN_INT (0x07000000),
10916 NULL_RTX, 1, OPTAB_DIRECT);
10917 /* sel = .......D */
10918 /* t_1 = .....C.. */
10919 /* t_2 = ...B.... */
10920 /* t_3 = .A...... */
10921 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
10922 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
10923 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
10924 /* sel = .A.B.C.D */
10925 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
10926 /* sel = AABBCCDD * 2 */
10927 t_1 = force_reg (SImode, GEN_INT (0x01010101));
10928 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
10932 /* input = xAxBxCxDxExFxGxH */
10933 sel = expand_simple_binop (DImode, AND, sel,
10934 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
10936 NULL_RTX, 1, OPTAB_DIRECT);
10937 /* sel = .A.B.C.D.E.F.G.H */
10938 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
10939 NULL_RTX, 1, OPTAB_DIRECT);
10940 /* t_1 = ..A.B.C.D.E.F.G. */
10941 sel = expand_simple_binop (DImode, IOR, sel, t_1,
10942 NULL_RTX, 1, OPTAB_DIRECT);
10943 /* sel = .AABBCCDDEEFFGGH */
10944 sel = expand_simple_binop (DImode, AND, sel,
10945 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
10947 NULL_RTX, 1, OPTAB_DIRECT);
10948 /* sel = ..AB..CD..EF..GH */
10949 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
10950 NULL_RTX, 1, OPTAB_DIRECT);
10951 /* t_1 = ....AB..CD..EF.. */
10952 sel = expand_simple_binop (DImode, IOR, sel, t_1,
10953 NULL_RTX, 1, OPTAB_DIRECT);
10954 /* sel = ..ABABCDCDEFEFGH */
10955 sel = expand_simple_binop (DImode, AND, sel,
10956 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
10957 NULL_RTX, 1, OPTAB_DIRECT);
10958 /* sel = ....ABCD....EFGH */
10959 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
10960 NULL_RTX, 1, OPTAB_DIRECT);
10961 /* t_1 = ........ABCD.... */
10962 sel = gen_lowpart (SImode, sel);
10963 t_1 = gen_lowpart (SImode, t_1);
10967 gcc_unreachable ();
10970 /* Always perform the final addition/merge within the bmask insn. */
10971 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
10974 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10977 sparc_frame_pointer_required (void)
10979 /* If the stack pointer is dynamically modified in the function, it cannot
10980 serve as the frame pointer. */
10981 if (cfun->calls_alloca)
10984 /* If the function receives nonlocal gotos, it needs to save the frame
10985 pointer in the nonlocal_goto_save_area object. */
10986 if (cfun->has_nonlocal_label)
10989 /* In flat mode, that's it. */
10993 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10994 return !(current_function_is_leaf && only_leaf_regs_used ());
10997 /* The way this is structured, we can't eliminate SFP in favor of SP
10998 if the frame pointer is required: we want to use the SFP->HFP elimination
10999 in that case. But the test in update_eliminables doesn't know we are
11000 assuming below that we only do the former elimination. */
11003 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11005 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
11008 /* Return the hard frame pointer directly to bypass the stack bias. */
11011 sparc_builtin_setjmp_frame_value (void)
11013 return hard_frame_pointer_rtx;
11016 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11017 they won't be allocated. */
11020 sparc_conditional_register_usage (void)
11022 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
11024 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11025 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11027 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11028 /* then honor it. */
11029 if (TARGET_ARCH32 && fixed_regs[5])
11031 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
11036 for (regno = SPARC_FIRST_V9_FP_REG;
11037 regno <= SPARC_LAST_V9_FP_REG;
11039 fixed_regs[regno] = 1;
11040 /* %fcc0 is used by v8 and v9. */
11041 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
11042 regno <= SPARC_LAST_V9_FCC_REG;
11044 fixed_regs[regno] = 1;
11049 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
11050 fixed_regs[regno] = 1;
11052 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
11053 /* then honor it. Likewise with g3 and g4. */
11054 if (fixed_regs[2] == 2)
11055 fixed_regs[2] = ! TARGET_APP_REGS;
11056 if (fixed_regs[3] == 2)
11057 fixed_regs[3] = ! TARGET_APP_REGS;
11058 if (TARGET_ARCH32 && fixed_regs[4] == 2)
11059 fixed_regs[4] = ! TARGET_APP_REGS;
11060 else if (TARGET_CM_EMBMEDANY)
11062 else if (fixed_regs[4] == 2)
11067 /* Disable leaf functions. */
11068 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
11069 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
11070 leaf_reg_remap [regno] = regno;
11073 global_regs[SPARC_GSR_REG] = 1;
11076 /* Implement TARGET_PREFERRED_RELOAD_CLASS
11078 - We can't load constants into FP registers.
11079 - We can't load FP constants into integer registers when soft-float,
11080 because there is no soft-float pattern with a r/F constraint.
11081 - We can't load FP constants into integer registers for TFmode unless
11082 it is 0.0L, because there is no movtf pattern with a r/F constraint.
11083 - Try and reload integer constants (symbolic or otherwise) back into
11084 registers directly, rather than having them dumped to memory. */
11087 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
11089 if (CONSTANT_P (x))
11091 if (FP_REG_CLASS_P (rclass)
11092 || rclass == GENERAL_OR_FP_REGS
11093 || rclass == GENERAL_OR_EXTRA_FP_REGS
11094 || (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT && ! TARGET_FPU)
11095 || (GET_MODE (x) == TFmode && ! const_zero_operand (x, TFmode)))
11098 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11099 return GENERAL_REGS;
11106 output_v8plus_mult (rtx insn, rtx *operands, const char *name)
11110 gcc_assert (! TARGET_ARCH64);
11112 if (sparc_check_64 (operands[1], insn) <= 0)
11113 output_asm_insn ("srl\t%L1, 0, %L1", operands);
11114 if (which_alternative == 1)
11115 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
11116 if (GET_CODE (operands[2]) == CONST_INT)
11118 if (which_alternative == 1)
11120 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11121 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", name);
11122 output_asm_insn (mulstr, operands);
11123 return "srlx\t%L0, 32, %H0";
11127 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11128 output_asm_insn ("or\t%L1, %3, %3", operands);
11129 sprintf (mulstr, "%s\t%%3, %%2, %%3", name);
11130 output_asm_insn (mulstr, operands);
11131 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11132 return "mov\t%3, %L0";
11135 else if (rtx_equal_p (operands[1], operands[2]))
11137 if (which_alternative == 1)
11139 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11140 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", name);
11141 output_asm_insn (mulstr, operands);
11142 return "srlx\t%L0, 32, %H0";
11146 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11147 output_asm_insn ("or\t%L1, %3, %3", operands);
11148 sprintf (mulstr, "%s\t%%3, %%3, %%3", name);
11149 output_asm_insn (mulstr, operands);
11150 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11151 return "mov\t%3, %L0";
11154 if (sparc_check_64 (operands[2], insn) <= 0)
11155 output_asm_insn ("srl\t%L2, 0, %L2", operands);
11156 if (which_alternative == 1)
11158 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11159 output_asm_insn ("sllx\t%H2, 32, %L1", operands);
11160 output_asm_insn ("or\t%L2, %L1, %L1", operands);
11161 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", name);
11162 output_asm_insn (mulstr, operands);
11163 return "srlx\t%L0, 32, %H0";
11167 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11168 output_asm_insn ("sllx\t%H2, 32, %4", operands);
11169 output_asm_insn ("or\t%L1, %3, %3", operands);
11170 output_asm_insn ("or\t%L2, %4, %4", operands);
11171 sprintf (mulstr, "%s\t%%3, %%4, %%3", name);
11172 output_asm_insn (mulstr, operands);
11173 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11174 return "mov\t%3, %L0";
11179 sparc_expand_vector_init (rtx target, rtx vals)
11181 enum machine_mode mode = GET_MODE (target);
11182 enum machine_mode inner_mode = GET_MODE_INNER (mode);
11183 int n_elts = GET_MODE_NUNITS (mode);
11187 for (i = 0; i < n_elts; i++)
11189 rtx x = XVECEXP (vals, 0, i);
11190 if (!CONSTANT_P (x))
11196 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
11200 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
11201 for (i = 0; i < n_elts; i++)
11202 emit_move_insn (adjust_address_nv (mem, inner_mode,
11203 i * GET_MODE_SIZE (inner_mode)),
11204 XVECEXP (vals, 0, i));
11205 emit_move_insn (target, mem);
11209 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
11210 enum machine_mode mode, secondary_reload_info *sri)
11212 enum reg_class rclass = (enum reg_class) rclass_i;
11214 /* We need a temporary when loading/storing a HImode/QImode value
11215 between memory and the FPU registers. This can happen when combine puts
11216 a paradoxical subreg in a float/fix conversion insn. */
11217 if (FP_REG_CLASS_P (rclass)
11218 && (mode == HImode || mode == QImode)
11219 && (GET_CODE (x) == MEM
11220 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
11221 && true_regnum (x) == -1)))
11222 return GENERAL_REGS;
11224 /* On 32-bit we need a temporary when loading/storing a DFmode value
11225 between unaligned memory and the upper FPU registers. */
11227 && rclass == EXTRA_FP_REGS
11229 && GET_CODE (x) == MEM
11230 && ! mem_min_alignment (x, 8))
11233 if (((TARGET_CM_MEDANY
11234 && symbolic_operand (x, mode))
11235 || (TARGET_CM_EMBMEDANY
11236 && text_segment_operand (x, mode)))
11240 sri->icode = direct_optab_handler (reload_in_optab, mode);
11242 sri->icode = direct_optab_handler (reload_out_optab, mode);
11249 #include "gt-sparc.h"