1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
141 tree, int, int, int *, int *);
143 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
144 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
146 static void sparc_output_addr_vec (rtx);
147 static void sparc_output_addr_diff_vec (rtx);
148 static void sparc_output_deferred_case_vectors (void);
149 static int check_return_regs (rtx);
150 static int epilogue_renumber (rtx *, int);
151 static bool sparc_assemble_integer (rtx, unsigned int, int);
152 static int set_extends (rtx);
153 static void output_restore_regs (FILE *, int);
154 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
155 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
156 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_save_restore (FILE *, const char *, int,
159 unsigned long, unsigned long,
160 const char *, const char *,
162 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
163 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
164 #ifdef OBJECT_FORMAT_ELF
165 static void sparc_elf_asm_named_section (const char *, unsigned int);
167 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
169 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
170 unsigned HOST_WIDE_INT)
173 static int sparc_adjust_cost (rtx, rtx, rtx, int);
174 static int sparc_issue_rate (void);
175 static void sparc_sched_init (FILE *, int, int);
176 static int sparc_use_dfa_pipeline_interface (void);
177 static int sparc_use_sched_lookahead (void);
179 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
180 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
181 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
182 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
183 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
185 static bool sparc_function_ok_for_sibcall (tree, tree);
186 static void sparc_init_libfuncs (void);
187 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
188 HOST_WIDE_INT, tree);
189 static struct machine_function * sparc_init_machine_status (void);
190 static bool sparc_cannot_force_const_mem (rtx);
191 static rtx sparc_tls_get_addr (void);
192 static rtx sparc_tls_got (void);
193 static const char *get_some_local_dynamic_name (void);
194 static int get_some_local_dynamic_name_1 (rtx *, void *);
195 static bool sparc_rtx_costs (rtx, int, int, int *);
197 /* Option handling. */
199 /* Code model option as passed by user. */
200 const char *sparc_cmodel_string;
202 enum cmodel sparc_cmodel;
204 char sparc_hard_reg_printed[8];
206 struct sparc_cpu_select sparc_select[] =
208 /* switch name, tune arch */
209 { (char *)0, "default", 1, 1 },
210 { (char *)0, "-mcpu=", 1, 1 },
211 { (char *)0, "-mtune=", 1, 0 },
215 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
216 enum processor_type sparc_cpu;
218 /* Initialize the GCC target structure. */
220 /* The sparc default is to use .half rather than .short for aligned
221 HI objects. Use .word instead of .long on non-ELF systems. */
222 #undef TARGET_ASM_ALIGNED_HI_OP
223 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
224 #ifndef OBJECT_FORMAT_ELF
225 #undef TARGET_ASM_ALIGNED_SI_OP
226 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
229 #undef TARGET_ASM_UNALIGNED_HI_OP
230 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
231 #undef TARGET_ASM_UNALIGNED_SI_OP
232 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
233 #undef TARGET_ASM_UNALIGNED_DI_OP
234 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
236 /* The target hook has to handle DI-mode values. */
237 #undef TARGET_ASM_INTEGER
238 #define TARGET_ASM_INTEGER sparc_assemble_integer
240 #undef TARGET_ASM_FUNCTION_PROLOGUE
241 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
242 #undef TARGET_ASM_FUNCTION_EPILOGUE
243 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
247 #undef TARGET_SCHED_ISSUE_RATE
248 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
249 #undef TARGET_SCHED_INIT
250 #define TARGET_SCHED_INIT sparc_sched_init
251 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
252 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
253 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
254 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
256 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
257 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
259 #undef TARGET_INIT_LIBFUNCS
260 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
263 #undef TARGET_HAVE_TLS
264 #define TARGET_HAVE_TLS true
266 #undef TARGET_CANNOT_FORCE_CONST_MEM
267 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
269 #undef TARGET_ASM_OUTPUT_MI_THUNK
270 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
271 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
272 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
274 #undef TARGET_RTX_COSTS
275 #define TARGET_RTX_COSTS sparc_rtx_costs
276 #undef TARGET_ADDRESS_COST
277 #define TARGET_ADDRESS_COST hook_int_rtx_0
279 struct gcc_target targetm = TARGET_INITIALIZER;
281 /* Validate and override various options, and do some machine dependent
285 sparc_override_options (void)
287 static struct code_model {
288 const char *const name;
290 } const cmodels[] = {
292 { "medlow", CM_MEDLOW },
293 { "medmid", CM_MEDMID },
294 { "medany", CM_MEDANY },
295 { "embmedany", CM_EMBMEDANY },
298 const struct code_model *cmodel;
299 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
300 static struct cpu_default {
302 const char *const name;
303 } const cpu_default[] = {
304 /* There must be one entry here for each TARGET_CPU value. */
305 { TARGET_CPU_sparc, "cypress" },
306 { TARGET_CPU_sparclet, "tsc701" },
307 { TARGET_CPU_sparclite, "f930" },
308 { TARGET_CPU_v8, "v8" },
309 { TARGET_CPU_hypersparc, "hypersparc" },
310 { TARGET_CPU_sparclite86x, "sparclite86x" },
311 { TARGET_CPU_supersparc, "supersparc" },
312 { TARGET_CPU_v9, "v9" },
313 { TARGET_CPU_ultrasparc, "ultrasparc" },
314 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
317 const struct cpu_default *def;
318 /* Table of values for -m{cpu,tune}=. */
319 static struct cpu_table {
320 const char *const name;
321 const enum processor_type processor;
324 } const cpu_table[] = {
325 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
326 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
327 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
328 /* TI TMS390Z55 supersparc */
329 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
330 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
331 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
332 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
333 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
334 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
335 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
336 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
338 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
340 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
341 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
342 /* TI ultrasparc I, II, IIi */
343 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
344 /* Although insns using %y are deprecated, it is a clear win on current
346 |MASK_DEPRECATED_V8_INSNS},
347 /* TI ultrasparc III */
348 /* ??? Check if %y issue still holds true in ultra3. */
349 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
352 const struct cpu_table *cpu;
353 const struct sparc_cpu_select *sel;
356 #ifndef SPARC_BI_ARCH
357 /* Check for unsupported architecture size. */
358 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
359 error ("%s is not supported by this configuration",
360 DEFAULT_ARCH32_P ? "-m64" : "-m32");
363 /* We force all 64bit archs to use 128 bit long double */
364 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
366 error ("-mlong-double-64 not allowed with -m64");
367 target_flags |= MASK_LONG_DOUBLE_128;
370 /* Code model selection. */
371 sparc_cmodel = SPARC_DEFAULT_CMODEL;
375 sparc_cmodel = CM_32;
378 if (sparc_cmodel_string != NULL)
382 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
383 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
385 if (cmodel->name == NULL)
386 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
388 sparc_cmodel = cmodel->value;
391 error ("-mcmodel= is not supported on 32 bit systems");
394 fpu = TARGET_FPU; /* save current -mfpu status */
396 /* Set the default CPU. */
397 for (def = &cpu_default[0]; def->name; ++def)
398 if (def->cpu == TARGET_CPU_DEFAULT)
402 sparc_select[0].string = def->name;
404 for (sel = &sparc_select[0]; sel->name; ++sel)
408 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
409 if (! strcmp (sel->string, cpu->name))
412 sparc_cpu = cpu->processor;
416 target_flags &= ~cpu->disable;
417 target_flags |= cpu->enable;
423 error ("bad value (%s) for %s switch", sel->string, sel->name);
427 /* If -mfpu or -mno-fpu was explicitly used, don't override with
428 the processor default. Clear MASK_FPU_SET to avoid confusing
429 the reverse mapping from switch values to names. */
432 target_flags = (target_flags & ~MASK_FPU) | fpu;
433 target_flags &= ~MASK_FPU_SET;
436 /* Don't allow -mvis if FPU is disabled. */
438 target_flags &= ~MASK_VIS;
440 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
442 -m64 also implies v9. */
443 if (TARGET_VIS || TARGET_ARCH64)
445 target_flags |= MASK_V9;
446 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
449 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
450 if (TARGET_V9 && TARGET_ARCH32)
451 target_flags |= MASK_DEPRECATED_V8_INSNS;
453 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
454 if (! TARGET_V9 || TARGET_ARCH64)
455 target_flags &= ~MASK_V8PLUS;
457 /* Don't use stack biasing in 32 bit mode. */
459 target_flags &= ~MASK_STACK_BIAS;
461 /* Supply a default value for align_functions. */
462 if (align_functions == 0
463 && (sparc_cpu == PROCESSOR_ULTRASPARC
464 || sparc_cpu == PROCESSOR_ULTRASPARC3))
465 align_functions = 32;
467 /* Validate PCC_STRUCT_RETURN. */
468 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
469 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
471 /* Only use .uaxword when compiling for a 64-bit target. */
473 targetm.asm_out.unaligned_op.di = NULL;
475 /* Do various machine dependent initializations. */
478 /* Set up function hooks. */
479 init_machine_status = sparc_init_machine_status;
482 /* Miscellaneous utilities. */
484 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
485 or branch on register contents instructions. */
488 v9_regcmp_p (enum rtx_code code)
490 return (code == EQ || code == NE || code == GE || code == LT
491 || code == LE || code == GT);
495 /* Operand constraints. */
497 /* Return nonzero only if OP is a register of mode MODE,
501 reg_or_0_operand (rtx op, enum machine_mode mode)
503 if (register_operand (op, mode))
505 if (op == const0_rtx)
507 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
508 && CONST_DOUBLE_HIGH (op) == 0
509 && CONST_DOUBLE_LOW (op) == 0)
511 if (fp_zero_operand (op, mode))
516 /* Return nonzero only if OP is const1_rtx. */
519 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
521 return op == const1_rtx;
524 /* Nonzero if OP is a floating point value with value 0.0. */
527 fp_zero_operand (rtx op, enum machine_mode mode)
529 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
531 return op == CONST0_RTX (mode);
534 /* Nonzero if OP is a register operand in floating point register. */
537 fp_register_operand (rtx op, enum machine_mode mode)
539 if (! register_operand (op, mode))
541 if (GET_CODE (op) == SUBREG)
542 op = SUBREG_REG (op);
543 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
546 /* Nonzero if OP is a floating point constant which can
547 be loaded into an integer register using a single
548 sethi instruction. */
553 if (GET_CODE (op) == CONST_DOUBLE)
558 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
559 if (REAL_VALUES_EQUAL (r, dconst0) &&
560 ! REAL_VALUE_MINUS_ZERO (r))
562 REAL_VALUE_TO_TARGET_SINGLE (r, i);
563 if (SPARC_SETHI_P (i))
570 /* Nonzero if OP is a floating point constant which can
571 be loaded into an integer register using a single
577 if (GET_CODE (op) == CONST_DOUBLE)
582 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
583 if (REAL_VALUES_EQUAL (r, dconst0) &&
584 ! REAL_VALUE_MINUS_ZERO (r))
586 REAL_VALUE_TO_TARGET_SINGLE (r, i);
587 if (SPARC_SIMM13_P (i))
594 /* Nonzero if OP is a floating point constant which can
595 be loaded into an integer register using a high/losum
596 instruction sequence. */
599 fp_high_losum_p (rtx op)
601 /* The constraints calling this should only be in
602 SFmode move insns, so any constant which cannot
603 be moved using a single insn will do. */
604 if (GET_CODE (op) == CONST_DOUBLE)
609 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
610 if (REAL_VALUES_EQUAL (r, dconst0) &&
611 ! REAL_VALUE_MINUS_ZERO (r))
613 REAL_VALUE_TO_TARGET_SINGLE (r, i);
614 if (! SPARC_SETHI_P (i)
615 && ! SPARC_SIMM13_P (i))
622 /* Nonzero if OP is an integer register. */
625 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
627 return (register_operand (op, SImode)
628 || (TARGET_ARCH64 && register_operand (op, DImode)));
631 /* Nonzero if OP is a floating point condition code register. */
634 fcc_reg_operand (rtx op, enum machine_mode mode)
636 /* This can happen when recog is called from combine. Op may be a MEM.
637 Fail instead of calling abort in this case. */
638 if (GET_CODE (op) != REG)
641 if (mode != VOIDmode && mode != GET_MODE (op))
644 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
647 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
648 if (reg_renumber == 0)
649 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
650 return REGNO_OK_FOR_CCFP_P (REGNO (op));
652 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
656 /* Nonzero if OP is a floating point condition code fcc0 register. */
659 fcc0_reg_operand (rtx op, enum machine_mode mode)
661 /* This can happen when recog is called from combine. Op may be a MEM.
662 Fail instead of calling abort in this case. */
663 if (GET_CODE (op) != REG)
666 if (mode != VOIDmode && mode != GET_MODE (op))
669 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
672 return REGNO (op) == SPARC_FCC_REG;
675 /* Nonzero if OP is an integer or floating point condition code register. */
678 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
680 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
682 if (mode != VOIDmode && mode != GET_MODE (op))
685 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
690 return fcc_reg_operand (op, mode);
693 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
695 restore_operand (rtx op, enum machine_mode mode)
697 return (GET_CODE (op) == REG && GET_MODE (op) == mode
698 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
701 /* Call insn on SPARC can take a PC-relative constant address, or any regular
705 call_operand (rtx op, enum machine_mode mode)
707 if (GET_CODE (op) != MEM)
710 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
714 call_operand_address (rtx op, enum machine_mode mode)
716 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
719 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
720 otherwise return 0. */
723 tls_symbolic_operand (rtx op)
725 if (GET_CODE (op) != SYMBOL_REF)
727 return SYMBOL_REF_TLS_MODEL (op);
731 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
733 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
737 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
739 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
743 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
745 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
749 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
751 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
754 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
755 reference and a constant. */
758 symbolic_operand (register rtx op, enum machine_mode mode)
760 enum machine_mode omode = GET_MODE (op);
762 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
765 switch (GET_CODE (op))
768 return !SYMBOL_REF_TLS_MODEL (op);
775 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
776 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
777 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
778 && GET_CODE (XEXP (op, 1)) == CONST_INT);
785 /* Return truth value of statement that OP is a symbolic memory
786 operand of mode MODE. */
789 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
791 if (GET_CODE (op) == SUBREG)
792 op = SUBREG_REG (op);
793 if (GET_CODE (op) != MEM)
796 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
797 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
798 || GET_CODE (op) == LABEL_REF);
801 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
804 label_ref_operand (rtx op, enum machine_mode mode)
806 if (GET_CODE (op) != LABEL_REF)
808 if (GET_MODE (op) != mode)
813 /* Return 1 if the operand is an argument used in generating pic references
814 in either the medium/low or medium/anywhere code models of sparc64. */
817 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
819 /* Check for (const (minus (symbol_ref:GOT)
820 (const (minus (label) (pc))))). */
821 if (GET_CODE (op) != CONST)
824 if (GET_CODE (op) != MINUS)
826 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
828 /* ??? Ensure symbol is GOT. */
829 if (GET_CODE (XEXP (op, 1)) != CONST)
831 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
836 /* Return 1 if the operand is a data segment reference. This includes
837 the readonly data segment, or in other words anything but the text segment.
838 This is needed in the medium/anywhere code model on v9. These values
839 are accessed with EMBMEDANY_BASE_REG. */
842 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
844 switch (GET_CODE (op))
847 return ! SYMBOL_REF_FUNCTION_P (op);
849 /* Assume canonical format of symbol + constant.
852 return data_segment_operand (XEXP (op, 0), VOIDmode);
858 /* Return 1 if the operand is a text segment reference.
859 This is needed in the medium/anywhere code model on v9. */
862 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
864 switch (GET_CODE (op))
869 return SYMBOL_REF_FUNCTION_P (op);
871 /* Assume canonical format of symbol + constant.
874 return text_segment_operand (XEXP (op, 0), VOIDmode);
880 /* Return 1 if the operand is either a register or a memory operand that is
884 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
886 if (register_operand (op, mode))
889 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
896 splittable_symbolic_memory_operand (rtx op,
897 enum machine_mode mode ATTRIBUTE_UNUSED)
899 if (GET_CODE (op) != MEM)
901 if (! symbolic_operand (XEXP (op, 0), Pmode))
907 splittable_immediate_memory_operand (rtx op,
908 enum machine_mode mode ATTRIBUTE_UNUSED)
910 if (GET_CODE (op) != MEM)
912 if (! immediate_operand (XEXP (op, 0), Pmode))
917 /* Return truth value of whether OP is EQ or NE. */
920 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
922 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
925 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
926 or LTU for non-floating-point. We handle those specially. */
929 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
931 enum rtx_code code = GET_CODE (op);
933 if (GET_RTX_CLASS (code) != '<')
936 if (GET_MODE (XEXP (op, 0)) == CCFPmode
937 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
940 return (code != NE && code != EQ && code != GEU && code != LTU);
943 /* Return 1 if this is a comparison operator. This allows the use of
944 MATCH_OPERATOR to recognize all the branch insns. */
947 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
949 enum rtx_code code = GET_CODE (op);
951 if (GET_RTX_CLASS (code) != '<')
954 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
955 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
956 /* These are the only branches which work with CC_NOOVmode. */
957 return (code == EQ || code == NE || code == GE || code == LT);
961 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
962 MATCH_OPERATOR to recognize all the branch insns. */
965 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
967 enum rtx_code code = GET_CODE (op);
972 if (GET_RTX_CLASS (code) != '<')
975 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
976 /* These are the only branches which work with CCX_NOOVmode. */
977 return (code == EQ || code == NE || code == GE || code == LT);
978 return (GET_MODE (XEXP (op, 0)) == CCXmode);
981 /* Nonzero if OP is a comparison operator suitable for use in v9
982 conditional move or branch on register contents instructions. */
985 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
987 enum rtx_code code = GET_CODE (op);
989 if (GET_RTX_CLASS (code) != '<')
992 return v9_regcmp_p (code);
995 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
998 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1000 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1003 /* Return nonzero if OP is an operator of mode MODE which can set
1004 the condition codes explicitly. We do not include PLUS and MINUS
1005 because these require CC_NOOVmode, which we handle explicitly. */
1008 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1010 if (GET_CODE (op) == AND
1011 || GET_CODE (op) == IOR
1012 || GET_CODE (op) == XOR)
1018 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1019 complement its second operand and set the condition codes explicitly. */
1022 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1024 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1025 and (xor ... (not ...)) to (not (xor ...)). */
1026 return (GET_CODE (op) == AND
1027 || GET_CODE (op) == IOR);
1030 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1031 signed 13 bit immediate field. This is an acceptable SImode operand for
1032 most 3 address instructions. */
1035 arith_operand (rtx op, enum machine_mode mode)
1037 if (register_operand (op, mode))
1039 if (GET_CODE (op) != CONST_INT)
1041 return SMALL_INT32 (op);
1044 /* Return true if OP is a constant 4096 */
1047 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1049 if (GET_CODE (op) != CONST_INT)
1052 return INTVAL (op) == 4096;
1055 /* Return true if OP is suitable as second operand for add/sub */
1058 arith_add_operand (rtx op, enum machine_mode mode)
1060 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1063 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1064 immediate field of OR and XOR instructions. Used for 64-bit
1065 constant formation patterns. */
1067 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1069 return ((GET_CODE (op) == CONST_INT
1070 && SPARC_SIMM13_P (INTVAL (op)))
1071 #if HOST_BITS_PER_WIDE_INT != 64
1072 || (GET_CODE (op) == CONST_DOUBLE
1073 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1074 && (CONST_DOUBLE_HIGH (op) ==
1075 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1076 (HOST_WIDE_INT)-1 : 0)))
1081 /* The same, but only for sethi instructions. */
1083 const64_high_operand (rtx op, enum machine_mode mode)
1085 return ((GET_CODE (op) == CONST_INT
1086 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1087 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1089 || (GET_CODE (op) == CONST_DOUBLE
1090 && CONST_DOUBLE_HIGH (op) == 0
1091 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1092 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1095 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1096 signed 11 bit immediate field. This is an acceptable SImode operand for
1097 the movcc instructions. */
1100 arith11_operand (rtx op, enum machine_mode mode)
1102 return (register_operand (op, mode)
1103 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1106 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1107 signed 10 bit immediate field. This is an acceptable SImode operand for
1108 the movrcc instructions. */
1111 arith10_operand (rtx op, enum machine_mode mode)
1113 return (register_operand (op, mode)
1114 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1117 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1118 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1120 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1121 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1122 for most 3 address instructions. */
1125 arith_double_operand (rtx op, enum machine_mode mode)
1127 return (register_operand (op, mode)
1128 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1130 && GET_CODE (op) == CONST_DOUBLE
1131 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1132 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1134 && GET_CODE (op) == CONST_DOUBLE
1135 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1136 && ((CONST_DOUBLE_HIGH (op) == -1
1137 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1138 || (CONST_DOUBLE_HIGH (op) == 0
1139 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1142 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1145 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1147 return (TARGET_ARCH64 &&
1148 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1149 (GET_CODE (op) == CONST_DOUBLE &&
1150 CONST_DOUBLE_LOW (op) == 4096 &&
1151 CONST_DOUBLE_HIGH (op) == 0)));
1154 /* Return true if OP is suitable as second operand for add/sub in DImode */
1157 arith_double_add_operand (rtx op, enum machine_mode mode)
1159 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1162 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1163 can fit in an 11 bit immediate field. This is an acceptable DImode
1164 operand for the movcc instructions. */
1165 /* ??? Replace with arith11_operand? */
1168 arith11_double_operand (rtx op, enum machine_mode mode)
1170 return (register_operand (op, mode)
1171 || (GET_CODE (op) == CONST_DOUBLE
1172 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1173 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1174 && ((CONST_DOUBLE_HIGH (op) == -1
1175 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1176 || (CONST_DOUBLE_HIGH (op) == 0
1177 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1178 || (GET_CODE (op) == CONST_INT
1179 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1180 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1183 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1184 can fit in an 10 bit immediate field. This is an acceptable DImode
1185 operand for the movrcc instructions. */
1186 /* ??? Replace with arith10_operand? */
1189 arith10_double_operand (rtx op, enum machine_mode mode)
1191 return (register_operand (op, mode)
1192 || (GET_CODE (op) == CONST_DOUBLE
1193 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1194 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1195 && ((CONST_DOUBLE_HIGH (op) == -1
1196 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1197 || (CONST_DOUBLE_HIGH (op) == 0
1198 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1199 || (GET_CODE (op) == CONST_INT
1200 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1201 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1204 /* Return truth value of whether OP is an integer which fits the
1205 range constraining immediate operands in most three-address insns,
1206 which have a 13 bit immediate field. */
1209 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1211 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1215 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1217 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1218 || (GET_CODE (op) == CONST_DOUBLE
1219 && CONST_DOUBLE_HIGH (op) == 0
1220 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1223 /* Recognize operand values for the umul instruction. That instruction sign
1224 extends immediate values just like all other sparc instructions, but
1225 interprets the extended result as an unsigned number. */
1228 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1230 #if HOST_BITS_PER_WIDE_INT > 32
1231 /* All allowed constants will fit a CONST_INT. */
1232 return (GET_CODE (op) == CONST_INT
1233 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1234 || (INTVAL (op) >= 0xFFFFF000
1235 && INTVAL (op) <= 0xFFFFFFFF)));
1237 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1238 || (GET_CODE (op) == CONST_DOUBLE
1239 && CONST_DOUBLE_HIGH (op) == 0
1240 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1245 uns_arith_operand (rtx op, enum machine_mode mode)
1247 return register_operand (op, mode) || uns_small_int (op, mode);
1250 /* Return truth value of statement that OP is a call-clobbered register. */
1252 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1254 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1257 /* Return 1 if OP is a valid operand for the source of a move insn. */
1260 input_operand (rtx op, enum machine_mode mode)
1262 /* If both modes are non-void they must be the same. */
1263 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1266 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1267 if (GET_CODE (op) == CONSTANT_P_RTX)
1270 /* Allow any one instruction integer constant, and all CONST_INT
1271 variants when we are working in DImode and !arch64. */
1272 if (GET_MODE_CLASS (mode) == MODE_INT
1273 && ((GET_CODE (op) == CONST_INT
1274 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1275 || SPARC_SIMM13_P (INTVAL (op))
1277 && ! TARGET_ARCH64)))
1279 && GET_CODE (op) == CONST_DOUBLE
1280 && ((CONST_DOUBLE_HIGH (op) == 0
1281 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1283 #if HOST_BITS_PER_WIDE_INT == 64
1284 (CONST_DOUBLE_HIGH (op) == 0
1285 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1287 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1288 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1289 && CONST_DOUBLE_HIGH (op) == 0)
1290 || (CONST_DOUBLE_HIGH (op) == -1
1291 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1296 /* If !arch64 and this is a DImode const, allow it so that
1297 the splits can be generated. */
1300 && GET_CODE (op) == CONST_DOUBLE)
1303 if (register_operand (op, mode))
1306 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1307 && GET_CODE (op) == CONST_DOUBLE)
1310 /* If this is a SUBREG, look inside so that we handle
1311 paradoxical ones. */
1312 if (GET_CODE (op) == SUBREG)
1313 op = SUBREG_REG (op);
1315 /* Check for valid MEM forms. */
1316 if (GET_CODE (op) == MEM)
1318 rtx inside = XEXP (op, 0);
1320 if (GET_CODE (inside) == LO_SUM)
1322 /* We can't allow these because all of the splits
1323 (eventually as they trickle down into DFmode
1324 splits) require offsettable memory references. */
1326 && GET_MODE (op) == TFmode)
1329 return (register_operand (XEXP (inside, 0), Pmode)
1330 && CONSTANT_P (XEXP (inside, 1)));
1332 return memory_address_p (mode, inside);
1339 /* We know it can't be done in one insn when we get here,
1340 the movsi expander guarantees this. */
1342 sparc_emit_set_const32 (rtx op0, rtx op1)
1344 enum machine_mode mode = GET_MODE (op0);
1347 if (GET_CODE (op1) == CONST_INT)
1349 HOST_WIDE_INT value = INTVAL (op1);
1351 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1352 || SPARC_SIMM13_P (value))
1356 /* Full 2-insn decomposition is needed. */
1357 if (reload_in_progress || reload_completed)
1360 temp = gen_reg_rtx (mode);
1362 if (GET_CODE (op1) == CONST_INT)
1364 /* Emit them as real moves instead of a HIGH/LO_SUM,
1365 this way CSE can see everything and reuse intermediate
1366 values if it wants. */
1368 && HOST_BITS_PER_WIDE_INT != 64
1369 && (INTVAL (op1) & 0x80000000) != 0)
1370 emit_insn (gen_rtx_SET
1372 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1375 emit_insn (gen_rtx_SET (VOIDmode, temp,
1376 GEN_INT (INTVAL (op1)
1377 & ~(HOST_WIDE_INT)0x3ff)));
1379 emit_insn (gen_rtx_SET (VOIDmode,
1381 gen_rtx_IOR (mode, temp,
1382 GEN_INT (INTVAL (op1) & 0x3ff))));
1386 /* A symbol, emit in the traditional way. */
1387 emit_insn (gen_rtx_SET (VOIDmode, temp,
1388 gen_rtx_HIGH (mode, op1)));
1389 emit_insn (gen_rtx_SET (VOIDmode,
1390 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1396 /* SPARC-v9 code-model support. */
1398 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1402 if (temp1 && GET_MODE (temp1) == TImode)
1405 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1408 switch (sparc_cmodel)
1411 /* The range spanned by all instructions in the object is less
1412 than 2^31 bytes (2GB) and the distance from any instruction
1413 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1414 than 2^31 bytes (2GB).
1416 The executable must be in the low 4TB of the virtual address
1419 sethi %hi(symbol), %temp
1420 or %temp, %lo(symbol), %reg */
1421 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1422 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1426 /* The range spanned by all instructions in the object is less
1427 than 2^31 bytes (2GB) and the distance from any instruction
1428 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1429 than 2^31 bytes (2GB).
1431 The executable must be in the low 16TB of the virtual address
1434 sethi %h44(symbol), %temp1
1435 or %temp1, %m44(symbol), %temp2
1436 sllx %temp2, 12, %temp3
1437 or %temp3, %l44(symbol), %reg */
1438 emit_insn (gen_seth44 (op0, op1));
1439 emit_insn (gen_setm44 (op0, op0, op1));
1440 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1441 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1442 emit_insn (gen_setl44 (op0, temp1, op1));
1446 /* The range spanned by all instructions in the object is less
1447 than 2^31 bytes (2GB) and the distance from any instruction
1448 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1449 than 2^31 bytes (2GB).
1451 The executable can be placed anywhere in the virtual address
1454 sethi %hh(symbol), %temp1
1455 sethi %lm(symbol), %temp2
1456 or %temp1, %hm(symbol), %temp3
1457 or %temp2, %lo(symbol), %temp4
1458 sllx %temp3, 32, %temp5
1459 or %temp4, %temp5, %reg */
1461 /* It is possible that one of the registers we got for operands[2]
1462 might coincide with that of operands[0] (which is why we made
1463 it TImode). Pick the other one to use as our scratch. */
1464 if (rtx_equal_p (temp1, op0))
1467 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1472 emit_insn (gen_sethh (op0, op1));
1473 emit_insn (gen_setlm (temp1, op1));
1474 emit_insn (gen_sethm (op0, op0, op1));
1475 emit_insn (gen_rtx_SET (VOIDmode, op0,
1476 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1477 emit_insn (gen_rtx_SET (VOIDmode, op0,
1478 gen_rtx_PLUS (DImode, op0, temp1)));
1479 emit_insn (gen_setlo (op0, op0, op1));
1483 /* Old old old backwards compatibility kruft here.
1484 Essentially it is MEDLOW with a fixed 64-bit
1485 virtual base added to all data segment addresses.
1486 Text-segment stuff is computed like MEDANY, we can't
1487 reuse the code above because the relocation knobs
1490 Data segment: sethi %hi(symbol), %temp1
1491 or %temp1, %lo(symbol), %temp2
1492 add %temp2, EMBMEDANY_BASE_REG, %reg
1494 Text segment: sethi %uhi(symbol), %temp1
1495 sethi %hi(symbol), %temp2
1496 or %temp1, %ulo(symbol), %temp3
1497 or %temp2, %lo(symbol), %temp4
1498 sllx %temp3, 32, %temp5
1499 or %temp4, %temp5, %reg */
1500 if (data_segment_operand (op1, GET_MODE (op1)))
1502 emit_insn (gen_embmedany_sethi (temp1, op1));
1503 emit_insn (gen_embmedany_brsum (op0, temp1));
1504 emit_insn (gen_embmedany_losum (op0, op0, op1));
1508 /* It is possible that one of the registers we got for operands[2]
1509 might coincide with that of operands[0] (which is why we made
1510 it TImode). Pick the other one to use as our scratch. */
1511 if (rtx_equal_p (temp1, op0))
1514 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1519 emit_insn (gen_embmedany_textuhi (op0, op1));
1520 emit_insn (gen_embmedany_texthi (temp1, op1));
1521 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1522 emit_insn (gen_rtx_SET (VOIDmode, op0,
1523 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1524 emit_insn (gen_rtx_SET (VOIDmode, op0,
1525 gen_rtx_PLUS (DImode, op0, temp1)));
1526 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1535 /* These avoid problems when cross compiling. If we do not
1536 go through all this hair then the optimizer will see
1537 invalid REG_EQUAL notes or in some cases none at all. */
1538 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1539 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1540 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1541 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1543 #if HOST_BITS_PER_WIDE_INT == 64
1544 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1545 #define GEN_INT64(__x) GEN_INT (__x)
1547 #define GEN_HIGHINT64(__x) \
1548 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1549 #define GEN_INT64(__x) \
1550 immed_double_const ((__x) & 0xffffffff, \
1551 ((__x) & 0x80000000 ? -1 : 0), DImode)
1554 /* The optimizer is not to assume anything about exactly
1555 which bits are set for a HIGH, they are unspecified.
1556 Unfortunately this leads to many missed optimizations
1557 during CSE. We mask out the non-HIGH bits, and matches
1558 a plain movdi, to alleviate this problem. */
1560 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1562 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1566 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1568 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1572 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1574 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1578 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1580 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1583 /* Worker routines for 64-bit constant formation on arch64.
1584 One of the key things to be doing in these emissions is
1585 to create as many temp REGs as possible. This makes it
1586 possible for half-built constants to be used later when
1587 such values are similar to something required later on.
1588 Without doing this, the optimizer cannot see such
1591 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1592 unsigned HOST_WIDE_INT, int);
1595 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1596 unsigned HOST_WIDE_INT low_bits, int is_neg)
1598 unsigned HOST_WIDE_INT high_bits;
1601 high_bits = (~low_bits) & 0xffffffff;
1603 high_bits = low_bits;
1605 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1608 emit_insn (gen_rtx_SET (VOIDmode, op0,
1609 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1613 /* If we are XOR'ing with -1, then we should emit a one's complement
1614 instead. This way the combiner will notice logical operations
1615 such as ANDN later on and substitute. */
1616 if ((low_bits & 0x3ff) == 0x3ff)
1618 emit_insn (gen_rtx_SET (VOIDmode, op0,
1619 gen_rtx_NOT (DImode, temp)));
1623 emit_insn (gen_rtx_SET (VOIDmode, op0,
1624 gen_safe_XOR64 (temp,
1625 (-(HOST_WIDE_INT)0x400
1626 | (low_bits & 0x3ff)))));
1631 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1632 unsigned HOST_WIDE_INT, int);
1635 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1636 unsigned HOST_WIDE_INT high_bits,
1637 unsigned HOST_WIDE_INT low_immediate,
1642 if ((high_bits & 0xfffffc00) != 0)
1644 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1645 if ((high_bits & ~0xfffffc00) != 0)
1646 emit_insn (gen_rtx_SET (VOIDmode, op0,
1647 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1653 emit_insn (gen_safe_SET64 (temp, high_bits));
1657 /* Now shift it up into place. */
1658 emit_insn (gen_rtx_SET (VOIDmode, op0,
1659 gen_rtx_ASHIFT (DImode, temp2,
1660 GEN_INT (shift_count))));
1662 /* If there is a low immediate part piece, finish up by
1663 putting that in as well. */
1664 if (low_immediate != 0)
1665 emit_insn (gen_rtx_SET (VOIDmode, op0,
1666 gen_safe_OR64 (op0, low_immediate)));
1669 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1670 unsigned HOST_WIDE_INT);
1672 /* Full 64-bit constant decomposition. Even though this is the
1673 'worst' case, we still optimize a few things away. */
1675 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1676 unsigned HOST_WIDE_INT high_bits,
1677 unsigned HOST_WIDE_INT low_bits)
1681 if (reload_in_progress || reload_completed)
1684 sub_temp = gen_reg_rtx (DImode);
1686 if ((high_bits & 0xfffffc00) != 0)
1688 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1689 if ((high_bits & ~0xfffffc00) != 0)
1690 emit_insn (gen_rtx_SET (VOIDmode,
1692 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1698 emit_insn (gen_safe_SET64 (temp, high_bits));
1702 if (!reload_in_progress && !reload_completed)
1704 rtx temp2 = gen_reg_rtx (DImode);
1705 rtx temp3 = gen_reg_rtx (DImode);
1706 rtx temp4 = gen_reg_rtx (DImode);
1708 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1709 gen_rtx_ASHIFT (DImode, sub_temp,
1712 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1713 if ((low_bits & ~0xfffffc00) != 0)
1715 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1716 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1717 emit_insn (gen_rtx_SET (VOIDmode, op0,
1718 gen_rtx_PLUS (DImode, temp4, temp3)));
1722 emit_insn (gen_rtx_SET (VOIDmode, op0,
1723 gen_rtx_PLUS (DImode, temp4, temp2)));
1728 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1729 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1730 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1733 /* We are in the middle of reload, so this is really
1734 painful. However we do still make an attempt to
1735 avoid emitting truly stupid code. */
1736 if (low1 != const0_rtx)
1738 emit_insn (gen_rtx_SET (VOIDmode, op0,
1739 gen_rtx_ASHIFT (DImode, sub_temp,
1740 GEN_INT (to_shift))));
1741 emit_insn (gen_rtx_SET (VOIDmode, op0,
1742 gen_rtx_IOR (DImode, op0, low1)));
1750 if (low2 != const0_rtx)
1752 emit_insn (gen_rtx_SET (VOIDmode, op0,
1753 gen_rtx_ASHIFT (DImode, sub_temp,
1754 GEN_INT (to_shift))));
1755 emit_insn (gen_rtx_SET (VOIDmode, op0,
1756 gen_rtx_IOR (DImode, op0, low2)));
1764 emit_insn (gen_rtx_SET (VOIDmode, op0,
1765 gen_rtx_ASHIFT (DImode, sub_temp,
1766 GEN_INT (to_shift))));
1767 if (low3 != const0_rtx)
1768 emit_insn (gen_rtx_SET (VOIDmode, op0,
1769 gen_rtx_IOR (DImode, op0, low3)));
1774 /* Analyze a 64-bit constant for certain properties. */
1775 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1776 unsigned HOST_WIDE_INT,
1777 int *, int *, int *);
1780 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1781 unsigned HOST_WIDE_INT low_bits,
1782 int *hbsp, int *lbsp, int *abbasp)
1784 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1787 lowest_bit_set = highest_bit_set = -1;
1791 if ((lowest_bit_set == -1)
1792 && ((low_bits >> i) & 1))
1794 if ((highest_bit_set == -1)
1795 && ((high_bits >> (32 - i - 1)) & 1))
1796 highest_bit_set = (64 - i - 1);
1799 && ((highest_bit_set == -1)
1800 || (lowest_bit_set == -1)));
1806 if ((lowest_bit_set == -1)
1807 && ((high_bits >> i) & 1))
1808 lowest_bit_set = i + 32;
1809 if ((highest_bit_set == -1)
1810 && ((low_bits >> (32 - i - 1)) & 1))
1811 highest_bit_set = 32 - i - 1;
1814 && ((highest_bit_set == -1)
1815 || (lowest_bit_set == -1)));
1817 /* If there are no bits set this should have gone out
1818 as one instruction! */
1819 if (lowest_bit_set == -1
1820 || highest_bit_set == -1)
1822 all_bits_between_are_set = 1;
1823 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1827 if ((low_bits & (1 << i)) != 0)
1832 if ((high_bits & (1 << (i - 32))) != 0)
1835 all_bits_between_are_set = 0;
1838 *hbsp = highest_bit_set;
1839 *lbsp = lowest_bit_set;
1840 *abbasp = all_bits_between_are_set;
1843 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1846 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1847 unsigned HOST_WIDE_INT low_bits)
1849 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1852 || high_bits == 0xffffffff)
1855 analyze_64bit_constant (high_bits, low_bits,
1856 &highest_bit_set, &lowest_bit_set,
1857 &all_bits_between_are_set);
1859 if ((highest_bit_set == 63
1860 || lowest_bit_set == 0)
1861 && all_bits_between_are_set != 0)
1864 if ((highest_bit_set - lowest_bit_set) < 21)
1870 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1871 unsigned HOST_WIDE_INT,
1874 static unsigned HOST_WIDE_INT
1875 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1876 unsigned HOST_WIDE_INT low_bits,
1877 int lowest_bit_set, int shift)
1879 HOST_WIDE_INT hi, lo;
1881 if (lowest_bit_set < 32)
1883 lo = (low_bits >> lowest_bit_set) << shift;
1884 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1889 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1896 /* Here we are sure to be arch64 and this is an integer constant
1897 being loaded into a register. Emit the most efficient
1898 insn sequence possible. Detection of all the 1-insn cases
1899 has been done already. */
1901 sparc_emit_set_const64 (rtx op0, rtx op1)
1903 unsigned HOST_WIDE_INT high_bits, low_bits;
1904 int lowest_bit_set, highest_bit_set;
1905 int all_bits_between_are_set;
1908 /* Sanity check that we know what we are working with. */
1909 if (! TARGET_ARCH64)
1912 if (GET_CODE (op0) != SUBREG)
1914 if (GET_CODE (op0) != REG
1915 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1916 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1920 if (reload_in_progress || reload_completed)
1923 temp = gen_reg_rtx (DImode);
1925 if (GET_CODE (op1) != CONST_DOUBLE
1926 && GET_CODE (op1) != CONST_INT)
1928 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1932 if (GET_CODE (op1) == CONST_DOUBLE)
1934 #if HOST_BITS_PER_WIDE_INT == 64
1935 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1936 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1938 high_bits = CONST_DOUBLE_HIGH (op1);
1939 low_bits = CONST_DOUBLE_LOW (op1);
1944 #if HOST_BITS_PER_WIDE_INT == 64
1945 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1946 low_bits = (INTVAL (op1) & 0xffffffff);
1948 high_bits = ((INTVAL (op1) < 0) ?
1951 low_bits = INTVAL (op1);
1955 /* low_bits bits 0 --> 31
1956 high_bits bits 32 --> 63 */
1958 analyze_64bit_constant (high_bits, low_bits,
1959 &highest_bit_set, &lowest_bit_set,
1960 &all_bits_between_are_set);
1962 /* First try for a 2-insn sequence. */
1964 /* These situations are preferred because the optimizer can
1965 * do more things with them:
1967 * sllx %reg, shift, %reg
1969 * srlx %reg, shift, %reg
1970 * 3) mov some_small_const, %reg
1971 * sllx %reg, shift, %reg
1973 if (((highest_bit_set == 63
1974 || lowest_bit_set == 0)
1975 && all_bits_between_are_set != 0)
1976 || ((highest_bit_set - lowest_bit_set) < 12))
1978 HOST_WIDE_INT the_const = -1;
1979 int shift = lowest_bit_set;
1981 if ((highest_bit_set != 63
1982 && lowest_bit_set != 0)
1983 || all_bits_between_are_set == 0)
1986 create_simple_focus_bits (high_bits, low_bits,
1989 else if (lowest_bit_set == 0)
1990 shift = -(63 - highest_bit_set);
1992 if (! SPARC_SIMM13_P (the_const))
1995 emit_insn (gen_safe_SET64 (temp, the_const));
1997 emit_insn (gen_rtx_SET (VOIDmode,
1999 gen_rtx_ASHIFT (DImode,
2003 emit_insn (gen_rtx_SET (VOIDmode,
2005 gen_rtx_LSHIFTRT (DImode,
2007 GEN_INT (-shift))));
2013 /* Now a range of 22 or less bits set somewhere.
2014 * 1) sethi %hi(focus_bits), %reg
2015 * sllx %reg, shift, %reg
2016 * 2) sethi %hi(focus_bits), %reg
2017 * srlx %reg, shift, %reg
2019 if ((highest_bit_set - lowest_bit_set) < 21)
2021 unsigned HOST_WIDE_INT focus_bits =
2022 create_simple_focus_bits (high_bits, low_bits,
2023 lowest_bit_set, 10);
2025 if (! SPARC_SETHI_P (focus_bits))
2028 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2030 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2031 if (lowest_bit_set < 10)
2032 emit_insn (gen_rtx_SET (VOIDmode,
2034 gen_rtx_LSHIFTRT (DImode, temp,
2035 GEN_INT (10 - lowest_bit_set))));
2036 else if (lowest_bit_set > 10)
2037 emit_insn (gen_rtx_SET (VOIDmode,
2039 gen_rtx_ASHIFT (DImode, temp,
2040 GEN_INT (lowest_bit_set - 10))));
2046 /* 1) sethi %hi(low_bits), %reg
2047 * or %reg, %lo(low_bits), %reg
2048 * 2) sethi %hi(~low_bits), %reg
2049 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2052 || high_bits == 0xffffffff)
2054 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2055 (high_bits == 0xffffffff));
2059 /* Now, try 3-insn sequences. */
2061 /* 1) sethi %hi(high_bits), %reg
2062 * or %reg, %lo(high_bits), %reg
2063 * sllx %reg, 32, %reg
2067 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2071 /* We may be able to do something quick
2072 when the constant is negated, so try that. */
2073 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2074 (~low_bits) & 0xfffffc00))
2076 /* NOTE: The trailing bits get XOR'd so we need the
2077 non-negated bits, not the negated ones. */
2078 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2080 if ((((~high_bits) & 0xffffffff) == 0
2081 && ((~low_bits) & 0x80000000) == 0)
2082 || (((~high_bits) & 0xffffffff) == 0xffffffff
2083 && ((~low_bits) & 0x80000000) != 0))
2085 int fast_int = (~low_bits & 0xffffffff);
2087 if ((SPARC_SETHI_P (fast_int)
2088 && (~high_bits & 0xffffffff) == 0)
2089 || SPARC_SIMM13_P (fast_int))
2090 emit_insn (gen_safe_SET64 (temp, fast_int));
2092 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2097 #if HOST_BITS_PER_WIDE_INT == 64
2098 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2099 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2101 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2102 (~high_bits) & 0xffffffff,
2105 sparc_emit_set_const64 (temp, negated_const);
2108 /* If we are XOR'ing with -1, then we should emit a one's complement
2109 instead. This way the combiner will notice logical operations
2110 such as ANDN later on and substitute. */
2111 if (trailing_bits == 0x3ff)
2113 emit_insn (gen_rtx_SET (VOIDmode, op0,
2114 gen_rtx_NOT (DImode, temp)));
2118 emit_insn (gen_rtx_SET (VOIDmode,
2120 gen_safe_XOR64 (temp,
2121 (-0x400 | trailing_bits))));
2126 /* 1) sethi %hi(xxx), %reg
2127 * or %reg, %lo(xxx), %reg
2128 * sllx %reg, yyy, %reg
2130 * ??? This is just a generalized version of the low_bits==0
2131 * thing above, FIXME...
2133 if ((highest_bit_set - lowest_bit_set) < 32)
2135 unsigned HOST_WIDE_INT focus_bits =
2136 create_simple_focus_bits (high_bits, low_bits,
2139 /* We can't get here in this state. */
2140 if (highest_bit_set < 32
2141 || lowest_bit_set >= 32)
2144 /* So what we know is that the set bits straddle the
2145 middle of the 64-bit word. */
2146 sparc_emit_set_const64_quick2 (op0, temp,
2152 /* 1) sethi %hi(high_bits), %reg
2153 * or %reg, %lo(high_bits), %reg
2154 * sllx %reg, 32, %reg
2155 * or %reg, low_bits, %reg
2157 if (SPARC_SIMM13_P(low_bits)
2158 && ((int)low_bits > 0))
2160 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2164 /* The easiest way when all else fails, is full decomposition. */
2166 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2167 high_bits, low_bits, ~high_bits, ~low_bits);
2169 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2172 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2173 return the mode to be used for the comparison. For floating-point,
2174 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2175 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2176 processing is needed. */
2179 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2181 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2207 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2208 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2210 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2211 return CCX_NOOVmode;
2217 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2224 /* X and Y are two things to compare using CODE. Emit the compare insn and
2225 return the rtx for the cc reg in the proper mode. */
2228 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2230 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2233 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2234 fcc regs (cse can't tell they're really call clobbered regs and will
2235 remove a duplicate comparison even if there is an intervening function
2236 call - it will then try to reload the cc reg via an int reg which is why
2237 we need the movcc patterns). It is possible to provide the movcc
2238 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2239 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2240 to tell cse that CCFPE mode registers (even pseudos) are call
2243 /* ??? This is an experiment. Rather than making changes to cse which may
2244 or may not be easy/clean, we do our own cse. This is possible because
2245 we will generate hard registers. Cse knows they're call clobbered (it
2246 doesn't know the same thing about pseudos). If we guess wrong, no big
2247 deal, but if we win, great! */
2249 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2250 #if 1 /* experiment */
2253 /* We cycle through the registers to ensure they're all exercised. */
2254 static int next_fcc_reg = 0;
2255 /* Previous x,y for each fcc reg. */
2256 static rtx prev_args[4][2];
2258 /* Scan prev_args for x,y. */
2259 for (reg = 0; reg < 4; reg++)
2260 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2265 prev_args[reg][0] = x;
2266 prev_args[reg][1] = y;
2267 next_fcc_reg = (next_fcc_reg + 1) & 3;
2269 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2272 cc_reg = gen_reg_rtx (mode);
2273 #endif /* ! experiment */
2274 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2275 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2277 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2279 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2280 gen_rtx_COMPARE (mode, x, y)));
2285 /* This function is used for v9 only.
2286 CODE is the code for an Scc's comparison.
2287 OPERANDS[0] is the target of the Scc insn.
2288 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2289 been generated yet).
2291 This function is needed to turn
2294 (gt (reg:CCX 100 %icc)
2298 (gt:DI (reg:CCX 100 %icc)
2301 IE: The instruction recognizer needs to see the mode of the comparison to
2302 find the right instruction. We could use "gt:DI" right in the
2303 define_expand, but leaving it out allows us to handle DI, SI, etc.
2305 We refer to the global sparc compare operands sparc_compare_op0 and
2306 sparc_compare_op1. */
2309 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2314 && (GET_MODE (sparc_compare_op0) == DImode
2315 || GET_MODE (operands[0]) == DImode))
2318 op0 = sparc_compare_op0;
2319 op1 = sparc_compare_op1;
2321 /* Try to use the movrCC insns. */
2323 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2324 && op1 == const0_rtx
2325 && v9_regcmp_p (compare_code))
2327 /* Special case for op0 != 0. This can be done with one instruction if
2328 operands[0] == sparc_compare_op0. */
2330 if (compare_code == NE
2331 && GET_MODE (operands[0]) == DImode
2332 && rtx_equal_p (op0, operands[0]))
2334 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2335 gen_rtx_IF_THEN_ELSE (DImode,
2336 gen_rtx_fmt_ee (compare_code, DImode,
2343 if (reg_overlap_mentioned_p (operands[0], op0))
2345 /* Handle the case where operands[0] == sparc_compare_op0.
2346 We "early clobber" the result. */
2347 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2348 emit_move_insn (op0, sparc_compare_op0);
2351 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2352 if (GET_MODE (op0) != DImode)
2354 temp = gen_reg_rtx (DImode);
2355 convert_move (temp, op0, 0);
2359 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2360 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2361 gen_rtx_fmt_ee (compare_code, DImode,
2369 operands[1] = gen_compare_reg (compare_code, op0, op1);
2371 switch (GET_MODE (operands[1]))
2381 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2382 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2383 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2384 gen_rtx_fmt_ee (compare_code,
2385 GET_MODE (operands[1]),
2386 operands[1], const0_rtx),
2387 const1_rtx, operands[0])));
2392 /* Emit a conditional jump insn for the v9 architecture using comparison code
2393 CODE and jump target LABEL.
2394 This function exists to take advantage of the v9 brxx insns. */
2397 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2399 emit_jump_insn (gen_rtx_SET (VOIDmode,
2401 gen_rtx_IF_THEN_ELSE (VOIDmode,
2402 gen_rtx_fmt_ee (code, GET_MODE (op0),
2404 gen_rtx_LABEL_REF (VOIDmode, label),
2408 /* Generate a DFmode part of a hard TFmode register.
2409 REG is the TFmode hard register, LOW is 1 for the
2410 low 64bit of the register and 0 otherwise.
2413 gen_df_reg (rtx reg, int low)
2415 int regno = REGNO (reg);
2417 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2418 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2419 return gen_rtx_REG (DFmode, regno);
2422 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2423 Unlike normal calls, TFmode operands are passed by reference. It is
2424 assumed that no more than 3 operands are required. */
2427 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2429 rtx ret_slot = NULL, arg[3], func_sym;
2432 /* We only expect to be called for conversions, unary, and binary ops. */
2433 if (nargs < 2 || nargs > 3)
2436 for (i = 0; i < nargs; ++i)
2438 rtx this_arg = operands[i];
2441 /* TFmode arguments and return values are passed by reference. */
2442 if (GET_MODE (this_arg) == TFmode)
2444 int force_stack_temp;
2446 force_stack_temp = 0;
2447 if (TARGET_BUGGY_QP_LIB && i == 0)
2448 force_stack_temp = 1;
2450 if (GET_CODE (this_arg) == MEM
2451 && ! force_stack_temp)
2452 this_arg = XEXP (this_arg, 0);
2453 else if (CONSTANT_P (this_arg)
2454 && ! force_stack_temp)
2456 this_slot = force_const_mem (TFmode, this_arg);
2457 this_arg = XEXP (this_slot, 0);
2461 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2463 /* Operand 0 is the return value. We'll copy it out later. */
2465 emit_move_insn (this_slot, this_arg);
2467 ret_slot = this_slot;
2469 this_arg = XEXP (this_slot, 0);
2476 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2478 if (GET_MODE (operands[0]) == TFmode)
2481 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2482 arg[0], GET_MODE (arg[0]),
2483 arg[1], GET_MODE (arg[1]));
2485 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2486 arg[0], GET_MODE (arg[0]),
2487 arg[1], GET_MODE (arg[1]),
2488 arg[2], GET_MODE (arg[2]));
2491 emit_move_insn (operands[0], ret_slot);
2500 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2501 GET_MODE (operands[0]), 1,
2502 arg[1], GET_MODE (arg[1]));
2504 if (ret != operands[0])
2505 emit_move_insn (operands[0], ret);
2509 /* Expand soft-float TFmode calls to sparc abi routines. */
2512 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2534 emit_soft_tfmode_libcall (func, 3, operands);
2538 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2551 emit_soft_tfmode_libcall (func, 2, operands);
2555 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2562 switch (GET_MODE (operands[1]))
2575 case FLOAT_TRUNCATE:
2576 switch (GET_MODE (operands[0]))
2590 switch (GET_MODE (operands[1]))
2603 case UNSIGNED_FLOAT:
2604 switch (GET_MODE (operands[1]))
2618 switch (GET_MODE (operands[0]))
2632 switch (GET_MODE (operands[0]))
2649 emit_soft_tfmode_libcall (func, 2, operands);
2652 /* Expand a hard-float tfmode operation. All arguments must be in
2656 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2660 if (GET_RTX_CLASS (code) == '1')
2662 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2663 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2667 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2668 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2669 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2670 operands[1], operands[2]);
2673 if (register_operand (operands[0], VOIDmode))
2676 dest = gen_reg_rtx (GET_MODE (operands[0]));
2678 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2680 if (dest != operands[0])
2681 emit_move_insn (operands[0], dest);
2685 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2687 if (TARGET_HARD_QUAD)
2688 emit_hard_tfmode_operation (code, operands);
2690 emit_soft_tfmode_binop (code, operands);
2694 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2696 if (TARGET_HARD_QUAD)
2697 emit_hard_tfmode_operation (code, operands);
2699 emit_soft_tfmode_unop (code, operands);
2703 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2705 if (TARGET_HARD_QUAD)
2706 emit_hard_tfmode_operation (code, operands);
2708 emit_soft_tfmode_cvt (code, operands);
2711 /* Return nonzero if a return peephole merging return with
2712 setting of output register is ok. */
2714 leaf_return_peephole_ok (void)
2716 return (actual_fsize == 0);
2719 /* Return nonzero if a branch/jump/call instruction will be emitting
2720 nop into its delay slot. */
2723 empty_delay_slot (rtx insn)
2727 /* If no previous instruction (should not happen), return true. */
2728 if (PREV_INSN (insn) == NULL)
2731 seq = NEXT_INSN (PREV_INSN (insn));
2732 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2738 /* Return nonzero if TRIAL can go into the function epilogue's
2739 delay slot. SLOT is the slot we are trying to fill. */
2742 eligible_for_epilogue_delay (rtx trial, int slot)
2749 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2752 if (get_attr_length (trial) != 1)
2755 /* If there are any call-saved registers, we should scan TRIAL if it
2756 does not reference them. For now just make it easy. */
2760 /* If the function uses __builtin_eh_return, the eh_return machinery
2761 occupies the delay slot. */
2762 if (current_function_calls_eh_return)
2765 /* In the case of a true leaf function, anything can go into the delay slot.
2766 A delay slot only exists however if the frame size is zero, otherwise
2767 we will put an insn to adjust the stack after the return. */
2768 if (current_function_uses_only_leaf_regs)
2770 if (leaf_return_peephole_ok ())
2771 return ((get_attr_in_uncond_branch_delay (trial)
2772 == IN_BRANCH_DELAY_TRUE));
2776 pat = PATTERN (trial);
2778 /* Otherwise, only operations which can be done in tandem with
2779 a `restore' or `return' insn can go into the delay slot. */
2780 if (GET_CODE (SET_DEST (pat)) != REG
2781 || REGNO (SET_DEST (pat)) < 24)
2784 /* If this instruction sets up floating point register and we have a return
2785 instruction, it can probably go in. But restore will not work
2787 if (REGNO (SET_DEST (pat)) >= 32)
2789 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2790 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2795 /* The set of insns matched here must agree precisely with the set of
2796 patterns paired with a RETURN in sparc.md. */
2798 src = SET_SRC (pat);
2800 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2801 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2802 && arith_operand (src, GET_MODE (src)))
2805 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2807 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2810 /* This matches "*return_di". */
2811 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2812 && arith_double_operand (src, GET_MODE (src)))
2813 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2815 /* This matches "*return_sf_no_fpu". */
2816 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2817 && register_operand (src, SFmode))
2820 /* If we have return instruction, anything that does not use
2821 local or output registers and can go into a delay slot wins. */
2822 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2823 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2826 /* This matches "*return_addsi". */
2827 else if (GET_CODE (src) == PLUS
2828 && arith_operand (XEXP (src, 0), SImode)
2829 && arith_operand (XEXP (src, 1), SImode)
2830 && (register_operand (XEXP (src, 0), SImode)
2831 || register_operand (XEXP (src, 1), SImode)))
2834 /* This matches "*return_adddi". */
2835 else if (GET_CODE (src) == PLUS
2836 && arith_double_operand (XEXP (src, 0), DImode)
2837 && arith_double_operand (XEXP (src, 1), DImode)
2838 && (register_operand (XEXP (src, 0), DImode)
2839 || register_operand (XEXP (src, 1), DImode)))
2842 /* This can match "*return_losum_[sd]i".
2843 Catch only some cases, so that return_losum* don't have
2845 else if (GET_CODE (src) == LO_SUM
2846 && ! TARGET_CM_MEDMID
2847 && ((register_operand (XEXP (src, 0), SImode)
2848 && immediate_operand (XEXP (src, 1), SImode))
2850 && register_operand (XEXP (src, 0), DImode)
2851 && immediate_operand (XEXP (src, 1), DImode))))
2854 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2855 else if (GET_CODE (src) == ASHIFT
2856 && (register_operand (XEXP (src, 0), SImode)
2857 || register_operand (XEXP (src, 0), DImode))
2858 && XEXP (src, 1) == const1_rtx)
2864 /* Return nonzero if TRIAL can go into the call delay slot. */
2866 tls_call_delay (rtx trial)
2871 call __tls_get_addr, %tgd_call (foo)
2872 add %l7, %o0, %o0, %tgd_add (foo)
2873 while Sun as/ld does not. */
2874 if (TARGET_GNU_TLS || !TARGET_TLS)
2877 pat = PATTERN (trial);
2878 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2881 unspec = XEXP (SET_DEST (pat), 1);
2882 if (GET_CODE (unspec) != UNSPEC
2883 || (XINT (unspec, 1) != UNSPEC_TLSGD
2884 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2890 /* Return nonzero if TRIAL can go into the sibling call
2894 eligible_for_sibcall_delay (rtx trial)
2898 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2901 if (get_attr_length (trial) != 1)
2904 pat = PATTERN (trial);
2906 if (current_function_uses_only_leaf_regs)
2908 /* If the tail call is done using the call instruction,
2909 we have to restore %o7 in the delay slot. */
2910 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2913 /* %g1 is used to build the function address */
2914 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2920 /* Otherwise, only operations which can be done in tandem with
2921 a `restore' insn can go into the delay slot. */
2922 if (GET_CODE (SET_DEST (pat)) != REG
2923 || REGNO (SET_DEST (pat)) < 24
2924 || REGNO (SET_DEST (pat)) >= 32)
2927 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2929 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2932 src = SET_SRC (pat);
2934 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2935 && arith_operand (src, GET_MODE (src)))
2938 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2940 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2943 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2944 && arith_double_operand (src, GET_MODE (src)))
2945 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2947 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2948 && register_operand (src, SFmode))
2951 else if (GET_CODE (src) == PLUS
2952 && arith_operand (XEXP (src, 0), SImode)
2953 && arith_operand (XEXP (src, 1), SImode)
2954 && (register_operand (XEXP (src, 0), SImode)
2955 || register_operand (XEXP (src, 1), SImode)))
2958 else if (GET_CODE (src) == PLUS
2959 && arith_double_operand (XEXP (src, 0), DImode)
2960 && arith_double_operand (XEXP (src, 1), DImode)
2961 && (register_operand (XEXP (src, 0), DImode)
2962 || register_operand (XEXP (src, 1), DImode)))
2965 else if (GET_CODE (src) == LO_SUM
2966 && ! TARGET_CM_MEDMID
2967 && ((register_operand (XEXP (src, 0), SImode)
2968 && immediate_operand (XEXP (src, 1), SImode))
2970 && register_operand (XEXP (src, 0), DImode)
2971 && immediate_operand (XEXP (src, 1), DImode))))
2974 else if (GET_CODE (src) == ASHIFT
2975 && (register_operand (XEXP (src, 0), SImode)
2976 || register_operand (XEXP (src, 0), DImode))
2977 && XEXP (src, 1) == const1_rtx)
2984 check_return_regs (rtx x)
2986 switch (GET_CODE (x))
2989 return IN_OR_GLOBAL_P (x);
3004 if (check_return_regs (XEXP (x, 1)) == 0)
3009 return check_return_regs (XEXP (x, 0));
3018 short_branch (int uid1, int uid2)
3020 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3022 /* Leave a few words of "slop". */
3023 if (delta >= -1023 && delta <= 1022)
3029 /* Return nonzero if REG is not used after INSN.
3030 We assume REG is a reload reg, and therefore does
3031 not live past labels or calls or jumps. */
3033 reg_unused_after (rtx reg, rtx insn)
3035 enum rtx_code code, prev_code = UNKNOWN;
3037 while ((insn = NEXT_INSN (insn)))
3039 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3042 code = GET_CODE (insn);
3043 if (GET_CODE (insn) == CODE_LABEL)
3046 if (GET_RTX_CLASS (code) == 'i')
3048 rtx set = single_set (insn);
3049 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3052 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3054 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3062 /* Determine if it's legal to put X into the constant pool. This
3063 is not possible if X contains the address of a symbol that is
3064 not constant (TLS) or not known at final link time (PIC). */
3067 sparc_cannot_force_const_mem (rtx x)
3069 switch (GET_CODE (x))
3073 /* Accept all non-symbolic constants. */
3077 /* Labels are OK iff we are non-PIC. */
3078 return flag_pic != 0;
3081 /* 'Naked' TLS symbol references are never OK,
3082 non-TLS symbols are OK iff we are non-PIC. */
3083 if (SYMBOL_REF_TLS_MODEL (x))
3086 return flag_pic != 0;
3089 return sparc_cannot_force_const_mem (XEXP (x, 0));
3092 return sparc_cannot_force_const_mem (XEXP (x, 0))
3093 || sparc_cannot_force_const_mem (XEXP (x, 1));
3101 /* The table we use to reference PIC data. */
3102 static GTY(()) rtx global_offset_table;
3104 /* The function we use to get at it. */
3105 static GTY(()) rtx get_pc_symbol;
3106 static char get_pc_symbol_name[256];
3108 /* Ensure that we are not using patterns that are not OK with PIC. */
3116 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3117 || (GET_CODE (recog_data.operand[i]) == CONST
3118 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3119 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3120 == global_offset_table)
3121 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3130 /* Return true if X is an address which needs a temporary register when
3131 reloaded while generating PIC code. */
3134 pic_address_needs_scratch (rtx x)
3136 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3137 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3138 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3139 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3140 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3146 /* Determine if a given RTX is a valid constant. We already know this
3147 satisfies CONSTANT_P. */
3150 legitimate_constant_p (rtx x)
3154 switch (GET_CODE (x))
3157 /* TLS symbols are not constant. */
3158 if (SYMBOL_REF_TLS_MODEL (x))
3163 inner = XEXP (x, 0);
3165 /* Offsets of TLS symbols are never valid.
3166 Discourage CSE from creating them. */
3167 if (GET_CODE (inner) == PLUS
3168 && tls_symbolic_operand (XEXP (inner, 0)))
3173 if (GET_MODE (x) == VOIDmode)
3176 /* Floating point constants are generally not ok.
3177 The only exception is 0.0 in VIS. */
3179 && (GET_MODE (x) == SFmode
3180 || GET_MODE (x) == DFmode
3181 || GET_MODE (x) == TFmode)
3182 && fp_zero_operand (x, GET_MODE (x)))
3194 /* Determine if a given RTX is a valid constant address. */
3197 constant_address_p (rtx x)
3199 switch (GET_CODE (x))
3207 if (flag_pic && pic_address_needs_scratch (x))
3209 return legitimate_constant_p (x);
3212 return !flag_pic && legitimate_constant_p (x);
3219 /* Nonzero if the constant value X is a legitimate general operand
3220 when generating PIC code. It is given that flag_pic is on and
3221 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3224 legitimate_pic_operand_p (rtx x)
3226 if (pic_address_needs_scratch (x))
3228 if (tls_symbolic_operand (x)
3229 || (GET_CODE (x) == CONST
3230 && GET_CODE (XEXP (x, 0)) == PLUS
3231 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3236 /* Return nonzero if ADDR is a valid memory address.
3237 STRICT specifies whether strict register checking applies. */
3240 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3242 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3244 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3246 else if (GET_CODE (addr) == PLUS)
3248 rs1 = XEXP (addr, 0);
3249 rs2 = XEXP (addr, 1);
3251 /* Canonicalize. REG comes first, if there are no regs,
3252 LO_SUM comes first. */
3254 && GET_CODE (rs1) != SUBREG
3256 || GET_CODE (rs2) == SUBREG
3257 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3259 rs1 = XEXP (addr, 1);
3260 rs2 = XEXP (addr, 0);
3264 && rs1 == pic_offset_table_rtx
3266 && GET_CODE (rs2) != SUBREG
3267 && GET_CODE (rs2) != LO_SUM
3268 && GET_CODE (rs2) != MEM
3269 && !tls_symbolic_operand (rs2)
3270 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3271 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3273 || GET_CODE (rs1) == SUBREG)
3274 && RTX_OK_FOR_OFFSET_P (rs2)))
3279 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3280 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3282 /* We prohibit REG + REG for TFmode when there are no instructions
3283 which accept REG+REG instructions. We do this because REG+REG
3284 is not an offsetable address. If we get the situation in reload
3285 where source and destination of a movtf pattern are both MEMs with
3286 REG+REG address, then only one of them gets converted to an
3287 offsetable address. */
3289 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3290 && TARGET_HARD_QUAD))
3293 /* We prohibit REG + REG on ARCH32 if not optimizing for
3294 DFmode/DImode because then mem_min_alignment is likely to be zero
3295 after reload and the forced split would lack a matching splitter
3297 if (TARGET_ARCH32 && !optimize
3298 && (mode == DFmode || mode == DImode))
3301 else if (USE_AS_OFFSETABLE_LO10
3302 && GET_CODE (rs1) == LO_SUM
3304 && ! TARGET_CM_MEDMID
3305 && RTX_OK_FOR_OLO10_P (rs2))
3309 imm1 = XEXP (rs1, 1);
3310 rs1 = XEXP (rs1, 0);
3311 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3315 else if (GET_CODE (addr) == LO_SUM)
3317 rs1 = XEXP (addr, 0);
3318 imm1 = XEXP (addr, 1);
3320 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3323 /* We can't allow TFmode, because an offset greater than or equal to the
3324 alignment (8) may cause the LO_SUM to overflow if !v9. */
3325 if (mode == TFmode && !TARGET_V9)
3328 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3333 if (GET_CODE (rs1) == SUBREG)
3334 rs1 = SUBREG_REG (rs1);
3340 if (GET_CODE (rs2) == SUBREG)
3341 rs2 = SUBREG_REG (rs2);
3348 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3349 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3354 if ((REGNO (rs1) >= 32
3355 && REGNO (rs1) != FRAME_POINTER_REGNUM
3356 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3358 && (REGNO (rs2) >= 32
3359 && REGNO (rs2) != FRAME_POINTER_REGNUM
3360 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3366 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3368 static GTY(()) rtx sparc_tls_symbol;
3370 sparc_tls_get_addr (void)
3372 if (!sparc_tls_symbol)
3373 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3375 return sparc_tls_symbol;
3379 sparc_tls_got (void)
3384 current_function_uses_pic_offset_table = 1;
3385 return pic_offset_table_rtx;
3388 if (!global_offset_table)
3389 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3390 temp = gen_reg_rtx (Pmode);
3391 emit_move_insn (temp, global_offset_table);
3396 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3397 this (thread-local) address. */
3400 legitimize_tls_address (rtx addr)
3402 rtx temp1, temp2, temp3, ret, o0, got, insn;
3407 if (GET_CODE (addr) == SYMBOL_REF)
3408 switch (SYMBOL_REF_TLS_MODEL (addr))
3410 case TLS_MODEL_GLOBAL_DYNAMIC:
3412 temp1 = gen_reg_rtx (SImode);
3413 temp2 = gen_reg_rtx (SImode);
3414 ret = gen_reg_rtx (Pmode);
3415 o0 = gen_rtx_REG (Pmode, 8);
3416 got = sparc_tls_got ();
3417 emit_insn (gen_tgd_hi22 (temp1, addr));
3418 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3421 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3422 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3427 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3428 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3431 CALL_INSN_FUNCTION_USAGE (insn)
3432 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3433 CALL_INSN_FUNCTION_USAGE (insn));
3434 insn = get_insns ();
3436 emit_libcall_block (insn, ret, o0, addr);
3439 case TLS_MODEL_LOCAL_DYNAMIC:
3441 temp1 = gen_reg_rtx (SImode);
3442 temp2 = gen_reg_rtx (SImode);
3443 temp3 = gen_reg_rtx (Pmode);
3444 ret = gen_reg_rtx (Pmode);
3445 o0 = gen_rtx_REG (Pmode, 8);
3446 got = sparc_tls_got ();
3447 emit_insn (gen_tldm_hi22 (temp1));
3448 emit_insn (gen_tldm_lo10 (temp2, temp1));
3451 emit_insn (gen_tldm_add32 (o0, got, temp2));
3452 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3457 emit_insn (gen_tldm_add64 (o0, got, temp2));
3458 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3461 CALL_INSN_FUNCTION_USAGE (insn)
3462 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3463 CALL_INSN_FUNCTION_USAGE (insn));
3464 insn = get_insns ();
3466 emit_libcall_block (insn, temp3, o0,
3467 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3468 UNSPEC_TLSLD_BASE));
3469 temp1 = gen_reg_rtx (SImode);
3470 temp2 = gen_reg_rtx (SImode);
3471 emit_insn (gen_tldo_hix22 (temp1, addr));
3472 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3474 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3476 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3479 case TLS_MODEL_INITIAL_EXEC:
3480 temp1 = gen_reg_rtx (SImode);
3481 temp2 = gen_reg_rtx (SImode);
3482 temp3 = gen_reg_rtx (Pmode);
3483 got = sparc_tls_got ();
3484 emit_insn (gen_tie_hi22 (temp1, addr));
3485 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3487 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3489 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3492 ret = gen_reg_rtx (Pmode);
3494 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3497 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3501 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3504 case TLS_MODEL_LOCAL_EXEC:
3505 temp1 = gen_reg_rtx (Pmode);
3506 temp2 = gen_reg_rtx (Pmode);
3509 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3510 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3514 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3515 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3517 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3525 abort (); /* for now ... */
3531 /* Legitimize PIC addresses. If the address is already position-independent,
3532 we return ORIG. Newly generated position-independent addresses go into a
3533 reg. This is REG if nonzero, otherwise we allocate register(s) as
3537 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3540 if (GET_CODE (orig) == SYMBOL_REF)
3542 rtx pic_ref, address;
3547 if (reload_in_progress || reload_completed)
3550 reg = gen_reg_rtx (Pmode);
3555 /* If not during reload, allocate another temp reg here for loading
3556 in the address, so that these instructions can be optimized
3558 rtx temp_reg = ((reload_in_progress || reload_completed)
3559 ? reg : gen_reg_rtx (Pmode));
3561 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3562 won't get confused into thinking that these two instructions
3563 are loading in the true address of the symbol. If in the
3564 future a PIC rtx exists, that should be used instead. */
3565 if (Pmode == SImode)
3567 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3568 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3572 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3573 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3580 pic_ref = gen_rtx_MEM (Pmode,
3581 gen_rtx_PLUS (Pmode,
3582 pic_offset_table_rtx, address));
3583 current_function_uses_pic_offset_table = 1;
3584 RTX_UNCHANGING_P (pic_ref) = 1;
3585 insn = emit_move_insn (reg, pic_ref);
3586 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3588 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3592 else if (GET_CODE (orig) == CONST)
3596 if (GET_CODE (XEXP (orig, 0)) == PLUS
3597 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3602 if (reload_in_progress || reload_completed)
3605 reg = gen_reg_rtx (Pmode);
3608 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3610 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3611 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3612 base == reg ? 0 : reg);
3617 if (GET_CODE (offset) == CONST_INT)
3619 if (SMALL_INT (offset))
3620 return plus_constant (base, INTVAL (offset));
3621 else if (! reload_in_progress && ! reload_completed)
3622 offset = force_reg (Pmode, offset);
3624 /* If we reach here, then something is seriously wrong. */
3627 return gen_rtx_PLUS (Pmode, base, offset);
3629 else if (GET_CODE (orig) == LABEL_REF)
3630 /* ??? Why do we do this? */
3631 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3632 the register is live instead, in case it is eliminated. */
3633 current_function_uses_pic_offset_table = 1;
3638 /* Try machine-dependent ways of modifying an illegitimate address X
3639 to be legitimate. If we find one, return the new, valid address.
3641 OLDX is the address as it was before break_out_memory_refs was called.
3642 In some cases it is useful to look at this to decide what needs to be done.
3644 MODE is the mode of the operand pointed to by X. */
3647 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3651 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3652 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3653 force_operand (XEXP (x, 0), NULL_RTX));
3654 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3655 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3656 force_operand (XEXP (x, 1), NULL_RTX));
3657 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3658 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3660 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3661 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3662 force_operand (XEXP (x, 1), NULL_RTX));
3664 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3667 if (tls_symbolic_operand (x))
3668 x = legitimize_tls_address (x);
3670 x = legitimize_pic_address (x, mode, 0);
3671 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3672 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3673 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3674 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3675 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3676 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3677 else if (GET_CODE (x) == SYMBOL_REF
3678 || GET_CODE (x) == CONST
3679 || GET_CODE (x) == LABEL_REF)
3680 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3684 /* Emit special PIC prologues. */
3687 load_pic_register (void)
3689 /* Labels to get the PC in the prologue of this function. */
3690 int orig_flag_pic = flag_pic;
3695 /* If we haven't emitted the special get_pc helper function, do so now. */
3696 if (get_pc_symbol_name[0] == 0)
3700 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3703 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3705 ASM_OUTPUT_ALIGN (asm_out_file, align);
3706 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3707 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3710 /* Initialize every time through, since we can't easily
3711 know this to be permanent. */
3712 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3713 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3716 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3719 flag_pic = orig_flag_pic;
3721 /* Need to emit this whether or not we obey regdecls,
3722 since setjmp/longjmp can cause life info to screw up.
3723 ??? In the case where we don't obey regdecls, this is not sufficient
3724 since we may not fall out the bottom. */
3725 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3728 /* Return 1 if RTX is a MEM which is known to be aligned to at
3729 least a DESIRED byte boundary. */
3732 mem_min_alignment (rtx mem, int desired)
3734 rtx addr, base, offset;
3736 /* If it's not a MEM we can't accept it. */
3737 if (GET_CODE (mem) != MEM)
3740 addr = XEXP (mem, 0);
3741 base = offset = NULL_RTX;
3742 if (GET_CODE (addr) == PLUS)
3744 if (GET_CODE (XEXP (addr, 0)) == REG)
3746 base = XEXP (addr, 0);
3748 /* What we are saying here is that if the base
3749 REG is aligned properly, the compiler will make
3750 sure any REG based index upon it will be so
3752 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3753 offset = XEXP (addr, 1);
3755 offset = const0_rtx;
3758 else if (GET_CODE (addr) == REG)
3761 offset = const0_rtx;
3764 if (base != NULL_RTX)
3766 int regno = REGNO (base);
3768 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3770 /* Check if the compiler has recorded some information
3771 about the alignment of the base REG. If reload has
3772 completed, we already matched with proper alignments.
3773 If not running global_alloc, reload might give us
3774 unaligned pointer to local stack though. */
3776 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3777 || (optimize && reload_completed))
3778 && (INTVAL (offset) & (desired - 1)) == 0)
3783 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3787 else if (! TARGET_UNALIGNED_DOUBLES
3788 || CONSTANT_P (addr)
3789 || GET_CODE (addr) == LO_SUM)
3791 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3792 is true, in which case we can only assume that an access is aligned if
3793 it is to a constant address, or the address involves a LO_SUM. */
3797 /* An obviously unaligned address. */
3802 /* Vectors to keep interesting information about registers where it can easily
3803 be got. We used to use the actual mode value as the bit number, but there
3804 are more than 32 modes now. Instead we use two tables: one indexed by
3805 hard register number, and one indexed by mode. */
3807 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3808 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3809 mapped into one sparc_mode_class mode. */
3811 enum sparc_mode_class {
3812 S_MODE, D_MODE, T_MODE, O_MODE,
3813 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3817 /* Modes for single-word and smaller quantities. */
3818 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3820 /* Modes for double-word and smaller quantities. */
3821 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3823 /* Modes for quad-word and smaller quantities. */
3824 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3826 /* Modes for 8-word and smaller quantities. */
3827 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3829 /* Modes for single-float quantities. We must allow any single word or
3830 smaller quantity. This is because the fix/float conversion instructions
3831 take integer inputs/outputs from the float registers. */
3832 #define SF_MODES (S_MODES)
3834 /* Modes for double-float and smaller quantities. */
3835 #define DF_MODES (S_MODES | D_MODES)
3837 /* Modes for double-float only quantities. */
3838 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3840 /* Modes for quad-float only quantities. */
3841 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3843 /* Modes for quad-float and smaller quantities. */
3844 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3846 /* Modes for quad-float and double-float quantities. */
3847 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3849 /* Modes for quad-float pair only quantities. */
3850 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3852 /* Modes for quad-float pairs and smaller quantities. */
3853 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3855 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3857 /* Modes for condition codes. */
3858 #define CC_MODES (1 << (int) CC_MODE)
3859 #define CCFP_MODES (1 << (int) CCFP_MODE)
3861 /* Value is 1 if register/mode pair is acceptable on sparc.
3862 The funny mixture of D and T modes is because integer operations
3863 do not specially operate on tetra quantities, so non-quad-aligned
3864 registers can hold quadword quantities (except %o4 and %i4 because
3865 they cross fixed registers). */
3867 /* This points to either the 32 bit or the 64 bit version. */
3868 const int *hard_regno_mode_classes;
3870 static const int hard_32bit_mode_classes[] = {
3871 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3872 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3873 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3874 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3876 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3877 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3878 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3879 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3881 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3882 and none can hold SFmode/SImode values. */
3883 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3884 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3885 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3886 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3889 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3895 static const int hard_64bit_mode_classes[] = {
3896 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3897 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3898 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3899 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3901 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3902 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3903 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3904 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3906 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3907 and none can hold SFmode/SImode values. */
3908 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3909 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3910 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3911 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3914 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3920 int sparc_mode_class [NUM_MACHINE_MODES];
3922 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3925 sparc_init_modes (void)
3929 for (i = 0; i < NUM_MACHINE_MODES; i++)
3931 switch (GET_MODE_CLASS (i))
3934 case MODE_PARTIAL_INT:
3935 case MODE_COMPLEX_INT:
3936 if (GET_MODE_SIZE (i) <= 4)
3937 sparc_mode_class[i] = 1 << (int) S_MODE;
3938 else if (GET_MODE_SIZE (i) == 8)
3939 sparc_mode_class[i] = 1 << (int) D_MODE;
3940 else if (GET_MODE_SIZE (i) == 16)
3941 sparc_mode_class[i] = 1 << (int) T_MODE;
3942 else if (GET_MODE_SIZE (i) == 32)
3943 sparc_mode_class[i] = 1 << (int) O_MODE;
3945 sparc_mode_class[i] = 0;
3948 case MODE_COMPLEX_FLOAT:
3949 if (GET_MODE_SIZE (i) <= 4)
3950 sparc_mode_class[i] = 1 << (int) SF_MODE;
3951 else if (GET_MODE_SIZE (i) == 8)
3952 sparc_mode_class[i] = 1 << (int) DF_MODE;
3953 else if (GET_MODE_SIZE (i) == 16)
3954 sparc_mode_class[i] = 1 << (int) TF_MODE;
3955 else if (GET_MODE_SIZE (i) == 32)
3956 sparc_mode_class[i] = 1 << (int) OF_MODE;
3958 sparc_mode_class[i] = 0;
3961 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3962 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3964 sparc_mode_class[i] = 1 << (int) CC_MODE;
3967 sparc_mode_class[i] = 0;
3973 hard_regno_mode_classes = hard_64bit_mode_classes;
3975 hard_regno_mode_classes = hard_32bit_mode_classes;
3977 /* Initialize the array used by REGNO_REG_CLASS. */
3978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3980 if (i < 16 && TARGET_V8PLUS)
3981 sparc_regno_reg_class[i] = I64_REGS;
3982 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3983 sparc_regno_reg_class[i] = GENERAL_REGS;
3985 sparc_regno_reg_class[i] = FP_REGS;
3987 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3989 sparc_regno_reg_class[i] = FPCC_REGS;
3991 sparc_regno_reg_class[i] = NO_REGS;
3995 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3996 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3997 v9 int regs as it simplifies the code. */
4000 save_regs (FILE *file, int low, int high, const char *base,
4001 int offset, int n_regs, HOST_WIDE_INT real_offset)
4005 if (TARGET_ARCH64 && high <= 32)
4007 for (i = low; i < high; i++)
4009 if (regs_ever_live[i] && ! call_used_regs[i])
4011 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4012 reg_names[i], base, offset + 4 * n_regs);
4013 if (dwarf2out_do_frame ())
4014 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4021 for (i = low; i < high; i += 2)
4023 if (regs_ever_live[i] && ! call_used_regs[i])
4025 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4027 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4028 reg_names[i], base, offset + 4 * n_regs);
4029 if (dwarf2out_do_frame ())
4031 char *l = dwarf2out_cfi_label ();
4032 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4033 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4039 fprintf (file, "\tst\t%s, [%s+%d]\n",
4040 reg_names[i], base, offset + 4 * n_regs);
4041 if (dwarf2out_do_frame ())
4042 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4048 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4050 fprintf (file, "\tst\t%s, [%s+%d]\n",
4051 reg_names[i+1], base, offset + 4 * n_regs + 4);
4052 if (dwarf2out_do_frame ())
4053 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4062 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4064 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4065 v9 int regs as it simplifies the code. */
4068 restore_regs (FILE *file, int low, int high, const char *base,
4069 int offset, int n_regs)
4073 if (TARGET_ARCH64 && high <= 32)
4075 for (i = low; i < high; i++)
4077 if (regs_ever_live[i] && ! call_used_regs[i])
4078 fprintf (file, "\tldx\t[%s+%d], %s\n",
4079 base, offset + 4 * n_regs, reg_names[i]),
4085 for (i = low; i < high; i += 2)
4087 if (regs_ever_live[i] && ! call_used_regs[i])
4088 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4089 fprintf (file, "\tldd\t[%s+%d], %s\n",
4090 base, offset + 4 * n_regs, reg_names[i]),
4093 fprintf (file, "\tld\t[%s+%d], %s\n",
4094 base, offset + 4 * n_regs, reg_names[i]),
4096 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4097 fprintf (file, "\tld\t[%s+%d], %s\n",
4098 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4105 /* Compute the frame size required by the function. This function is called
4106 during the reload pass and also by output_function_prologue(). */
4109 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4112 int outgoing_args_size = (current_function_outgoing_args_size
4113 + REG_PARM_STACK_SPACE (current_function_decl));
4115 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4116 even to v9 int regs to be consistent with save_regs/restore_regs. */
4120 for (i = 0; i < 8; i++)
4121 if (regs_ever_live[i] && ! call_used_regs[i])
4126 for (i = 0; i < 8; i += 2)
4127 if ((regs_ever_live[i] && ! call_used_regs[i])
4128 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4132 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4133 if ((regs_ever_live[i] && ! call_used_regs[i])
4134 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4137 /* Set up values for use in `function_epilogue'. */
4138 num_gfregs = n_regs;
4140 if (leaf_function && n_regs == 0
4141 && size == 0 && current_function_outgoing_args_size == 0)
4143 actual_fsize = apparent_fsize = 0;
4147 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4148 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4149 apparent_fsize += n_regs * 4;
4150 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4153 /* Make sure nothing can clobber our register windows.
4154 If a SAVE must be done, or there is a stack-local variable,
4155 the register window area must be allocated.
4156 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4157 if (leaf_function == 0 || size > 0)
4158 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4160 return SPARC_STACK_ALIGN (actual_fsize);
4163 /* Build big number NUM in register REG and output the result to FILE.
4164 REG is guaranteed to be the only clobbered register. The function
4165 will very likely emit several instructions, so it must not be called
4166 from within a delay slot. */
4169 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4171 #if HOST_BITS_PER_WIDE_INT == 64
4172 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4180 /* We don't use the 'set' macro because it appears to be broken
4181 in the Solaris 7 assembler. */
4182 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4184 if ((num & 0x3ff) != 0)
4185 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4188 #if HOST_BITS_PER_WIDE_INT == 64
4189 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4191 else /* num < 0 && TARGET_ARCH64 */
4194 /* Sethi does not sign extend, so we must use a little trickery
4195 to use it for negative numbers. Invert the constant before
4196 loading it in, then use xor immediate to invert the loaded bits
4197 (along with the upper 32 bits) to the desired constant. This
4198 works because the sethi and immediate fields overlap. */
4199 HOST_WIDE_INT inv = ~num;
4200 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4202 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4204 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4207 #if HOST_BITS_PER_WIDE_INT == 64
4208 else /* TARGET_ARCH64 */
4210 /* We don't use the 'setx' macro because if requires a scratch register.
4211 This is the translation of sparc_emit_set_const64_longway into asm.
4212 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4213 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4214 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4215 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4218 /* We don't use the 'set' macro because it appears to be broken
4219 in the Solaris 7 assembler. */
4220 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4222 if ((high_bits & 0x3ff) != 0)
4223 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4224 reg, high_bits, reg);
4228 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4229 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4239 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4240 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4248 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4250 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4256 /* Output any necessary .register pseudo-ops. */
4258 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4260 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4266 /* Check if %g[2367] were used without
4267 .register being printed for them already. */
4268 for (i = 2; i < 8; i++)
4270 if (regs_ever_live [i]
4271 && ! sparc_hard_reg_printed [i])
4273 sparc_hard_reg_printed [i] = 1;
4274 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4281 /* This function generates the assembly code for function entry.
4282 FILE is a stdio stream to output the code to.
4283 SIZE is an int: how many units of temporary storage to allocate.
4284 Refer to the array `regs_ever_live' to determine which registers
4285 to save; `regs_ever_live[I]' is nonzero if register number I
4286 is ever used in the function. This macro is responsible for
4287 knowing which registers should not be saved even if used. */
4289 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4290 of memory. If any fpu reg is used in the function, we allocate
4291 such a block here, at the bottom of the frame, just in case it's needed.
4293 If this function is a leaf procedure, then we may choose not
4294 to do a "save" insn. The decision about whether or not
4295 to do this is made in regclass.c. */
4298 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4301 sparc_flat_function_prologue (file, size);
4303 sparc_nonflat_function_prologue (file, size,
4304 current_function_uses_only_leaf_regs);
4307 /* Output code for the function prologue. */
4310 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4313 sparc_output_scratch_registers (file);
4315 /* Need to use actual_fsize, since we are also allocating
4316 space for our callee (and our own register save area). */
4317 actual_fsize = compute_frame_size (size, leaf_function);
4321 frame_base_name = "%sp";
4322 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4326 frame_base_name = "%fp";
4327 frame_base_offset = SPARC_STACK_BIAS;
4330 /* This is only for the human reader. */
4331 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4333 if (actual_fsize == 0)
4335 else if (! leaf_function)
4337 if (actual_fsize <= 4096)
4338 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4340 else if (actual_fsize <= 8192)
4342 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4343 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4344 actual_fsize - 4096);
4348 build_big_number (file, -actual_fsize, "%g1");
4349 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4352 else /* leaf function */
4354 if (actual_fsize <= 4096)
4355 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4357 else if (actual_fsize <= 8192)
4359 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4360 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4361 actual_fsize - 4096);
4365 build_big_number (file, -actual_fsize, "%g1");
4366 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4370 if (dwarf2out_do_frame () && actual_fsize)
4372 char *label = dwarf2out_cfi_label ();
4374 /* The canonical frame address refers to the top of the frame. */
4375 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4376 : HARD_FRAME_POINTER_REGNUM),
4379 if (! leaf_function)
4381 /* Note the register window save. This tells the unwinder that
4382 it needs to restore the window registers from the previous
4383 frame's window save area at 0(cfa). */
4384 dwarf2out_window_save (label);
4386 /* The return address (-8) is now in %i7. */
4387 dwarf2out_return_reg (label, 31);
4391 /* If doing anything with PIC, do it now. */
4393 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4395 /* Call saved registers are saved just above the outgoing argument area. */
4398 HOST_WIDE_INT offset, real_offset;
4402 real_offset = -apparent_fsize;
4403 offset = -apparent_fsize + frame_base_offset;
4404 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4406 /* ??? This might be optimized a little as %g1 might already have a
4407 value close enough that a single add insn will do. */
4408 /* ??? Although, all of this is probably only a temporary fix
4409 because if %g1 can hold a function result, then
4410 output_function_epilogue will lose (the result will get
4412 build_big_number (file, offset, "%g1");
4413 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4419 base = frame_base_name;
4422 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4423 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4428 /* Output code to restore any call saved registers. */
4431 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4433 HOST_WIDE_INT offset;
4437 offset = -apparent_fsize + frame_base_offset;
4438 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4440 build_big_number (file, offset, "%g1");
4441 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4447 base = frame_base_name;
4450 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4451 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4454 /* This function generates the assembly code for function exit,
4455 on machines that need it.
4457 The function epilogue should not depend on the current stack pointer!
4458 It should use the frame pointer only. This is mandatory because
4459 of alloca; we also take advantage of it to omit stack adjustments
4460 before returning. */
4463 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4466 sparc_flat_function_epilogue (file, size);
4468 sparc_nonflat_function_epilogue (file, size,
4469 current_function_uses_only_leaf_regs);
4472 /* Output code for the function epilogue. */
4475 sparc_nonflat_function_epilogue (FILE *file,
4476 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4481 if (current_function_epilogue_delay_list == 0)
4483 /* If code does not drop into the epilogue, we need
4484 do nothing except output pending case vectors.
4486 We have to still output a dummy nop for the sake of
4487 sane backtraces. Otherwise, if the last two instructions
4488 of a function were call foo; dslot; this can make the return
4489 PC of foo (ie. address of call instruction plus 8) point to
4490 the first instruction in the next function. */
4491 rtx insn, last_real_insn;
4493 insn = get_last_insn ();
4495 last_real_insn = prev_real_insn (insn);
4497 && GET_CODE (last_real_insn) == INSN
4498 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4499 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4501 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4502 fputs("\tnop\n", file);
4504 if (GET_CODE (insn) == NOTE)
4505 insn = prev_nonnote_insn (insn);
4506 if (insn && GET_CODE (insn) == BARRIER)
4507 goto output_vectors;
4511 output_restore_regs (file, leaf_function);
4513 /* Work out how to skip the caller's unimp instruction if required. */
4515 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4517 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4519 if (! leaf_function)
4521 if (current_function_calls_eh_return)
4523 if (current_function_epilogue_delay_list)
4525 if (SKIP_CALLERS_UNIMP_P)
4528 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4530 /* If we wound up with things in our delay slot, flush them here. */
4531 else if (current_function_epilogue_delay_list)
4533 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4535 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4537 epilogue_renumber (&delay, 0);
4538 fputs (SKIP_CALLERS_UNIMP_P
4539 ? "\treturn\t%i7+12\n"
4540 : "\treturn\t%i7+8\n", file);
4541 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4548 if (GET_CODE (delay) != SET)
4551 src = SET_SRC (delay);
4552 if (GET_CODE (src) == ASHIFT)
4554 if (XEXP (src, 1) != const1_rtx)
4557 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4561 insn = gen_rtx_PARALLEL (VOIDmode,
4562 gen_rtvec (2, delay,
4563 gen_rtx_RETURN (VOIDmode)));
4564 insn = emit_jump_insn (insn);
4566 sparc_emitting_epilogue = true;
4567 final_scan_insn (insn, file, 1, 0, 1);
4568 sparc_emitting_epilogue = false;
4571 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4572 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4574 fprintf (file, "\t%s\n\trestore\n", ret);
4576 /* All of the following cases are for leaf functions. */
4577 else if (current_function_calls_eh_return)
4579 else if (current_function_epilogue_delay_list)
4581 /* eligible_for_epilogue_delay_slot ensures that if this is a
4582 leaf function, then we will only have insn in the delay slot
4583 if the frame size is zero, thus no adjust for the stack is
4585 if (actual_fsize != 0)
4587 fprintf (file, "\t%s\n", ret);
4588 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4591 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4592 avoid generating confusing assembly language output. */
4593 else if (actual_fsize == 0)
4594 fprintf (file, "\t%s\n\tnop\n", ret);
4595 else if (actual_fsize <= 4096)
4596 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4598 else if (actual_fsize <= 8192)
4599 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4600 ret, actual_fsize - 4096);
4603 build_big_number (file, actual_fsize, "%g1");
4604 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4608 sparc_output_deferred_case_vectors ();
4611 /* Output a sibling call. */
4614 output_sibcall (rtx insn, rtx call_operand)
4616 int leaf_regs = current_function_uses_only_leaf_regs;
4618 int delay_slot = dbr_sequence_length () > 0;
4622 /* Call to restore global regs might clobber
4623 the delay slot. Instead of checking for this
4624 output the delay slot now. */
4627 rtx delay = NEXT_INSN (insn);
4632 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4633 PATTERN (delay) = gen_blockage ();
4634 INSN_CODE (delay) = -1;
4637 output_restore_regs (asm_out_file, leaf_regs);
4640 operands[0] = call_operand;
4644 #ifdef HAVE_AS_RELAX_OPTION
4645 /* If as and ld are relaxing tail call insns into branch always,
4646 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4647 be optimized. With sethi/jmpl as nor ld has no easy way how to
4648 find out if somebody does not branch between the sethi and jmpl. */
4651 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4653 HOST_WIDE_INT size = 0;
4655 if ((actual_fsize || ! spare_slot) && delay_slot)
4657 rtx delay = NEXT_INSN (insn);
4662 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4663 PATTERN (delay) = gen_blockage ();
4664 INSN_CODE (delay) = -1;
4669 if (actual_fsize <= 4096)
4670 size = actual_fsize;
4671 else if (actual_fsize <= 8192)
4673 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4674 size = actual_fsize - 4096;
4678 build_big_number (asm_out_file, actual_fsize, "%g1");
4679 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4684 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4685 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4687 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4688 else if (! delay_slot)
4689 fputs ("\t nop\n", asm_out_file);
4694 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4695 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4696 it into branch if possible. */
4697 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4698 output_asm_insn ("call\t%a0, 0", operands);
4699 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4704 output_asm_insn ("call\t%a0, 0", operands);
4707 rtx delay = NEXT_INSN (insn), pat;
4712 pat = PATTERN (delay);
4713 if (GET_CODE (pat) != SET)
4716 operands[0] = SET_DEST (pat);
4717 pat = SET_SRC (pat);
4718 switch (GET_CODE (pat))
4721 operands[1] = XEXP (pat, 0);
4722 operands[2] = XEXP (pat, 1);
4723 output_asm_insn (" restore %r1, %2, %Y0", operands);
4726 operands[1] = XEXP (pat, 0);
4727 operands[2] = XEXP (pat, 1);
4728 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4731 operands[1] = XEXP (pat, 0);
4732 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4736 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4739 PATTERN (delay) = gen_blockage ();
4740 INSN_CODE (delay) = -1;
4743 fputs ("\t restore\n", asm_out_file);
4747 /* Functions for handling argument passing.
4749 For v8 the first six args are normally in registers and the rest are
4750 pushed. Any arg that starts within the first 6 words is at least
4751 partially passed in a register unless its data type forbids.
4753 For v9, the argument registers are laid out as an array of 16 elements
4754 and arguments are added sequentially. The first 6 int args and up to the
4755 first 16 fp args (depending on size) are passed in regs.
4757 Slot Stack Integral Float Float in structure Double Long Double
4758 ---- ----- -------- ----- ------------------ ------ -----------
4759 15 [SP+248] %f31 %f30,%f31 %d30
4760 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4761 13 [SP+232] %f27 %f26,%f27 %d26
4762 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4763 11 [SP+216] %f23 %f22,%f23 %d22
4764 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4765 9 [SP+200] %f19 %f18,%f19 %d18
4766 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4767 7 [SP+184] %f15 %f14,%f15 %d14
4768 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4769 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4770 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4771 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4772 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4773 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4774 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4776 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4778 Integral arguments are always passed as 64 bit quantities appropriately
4781 Passing of floating point values is handled as follows.
4782 If a prototype is in scope:
4783 If the value is in a named argument (i.e. not a stdarg function or a
4784 value not part of the `...') then the value is passed in the appropriate
4786 If the value is part of the `...' and is passed in one of the first 6
4787 slots then the value is passed in the appropriate int reg.
4788 If the value is part of the `...' and is not passed in one of the first 6
4789 slots then the value is passed in memory.
4790 If a prototype is not in scope:
4791 If the value is one of the first 6 arguments the value is passed in the
4792 appropriate integer reg and the appropriate fp reg.
4793 If the value is not one of the first 6 arguments the value is passed in
4794 the appropriate fp reg and in memory.
4797 /* Maximum number of int regs for args. */
4798 #define SPARC_INT_ARG_MAX 6
4799 /* Maximum number of fp regs for args. */
4800 #define SPARC_FP_ARG_MAX 16
4802 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4804 /* Handle the INIT_CUMULATIVE_ARGS macro.
4805 Initialize a variable CUM of type CUMULATIVE_ARGS
4806 for a call to a function whose data type is FNTYPE.
4807 For a library call, FNTYPE is 0. */
4810 init_cumulative_args (struct sparc_args *cum, tree fntype,
4811 rtx libname ATTRIBUTE_UNUSED,
4812 tree fndecl ATTRIBUTE_UNUSED)
4815 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4816 cum->libcall_p = fntype == 0;
4819 /* Compute the slot number to pass an argument in.
4820 Returns the slot number or -1 if passing on the stack.
4822 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4823 the preceding args and about the function being called.
4824 MODE is the argument's machine mode.
4825 TYPE is the data type of the argument (as a tree).
4826 This is null for libcalls where that information may
4828 NAMED is nonzero if this argument is a named parameter
4829 (otherwise it is an extra parameter matching an ellipsis).
4830 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4831 *PREGNO records the register number to use if scalar type.
4832 *PPADDING records the amount of padding needed in words. */
4835 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4836 tree type, int named, int incoming_p,
4837 int *pregno, int *ppadding)
4839 int regbase = (incoming_p
4840 ? SPARC_INCOMING_INT_ARG_FIRST
4841 : SPARC_OUTGOING_INT_ARG_FIRST);
4842 int slotno = cum->words;
4847 if (type != 0 && TREE_ADDRESSABLE (type))
4850 && type != 0 && mode == BLKmode
4851 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4857 /* MODE is VOIDmode when generating the actual call.
4861 case QImode : case CQImode :
4862 case HImode : case CHImode :
4863 case SImode : case CSImode :
4864 case DImode : case CDImode :
4865 case TImode : case CTImode :
4866 if (slotno >= SPARC_INT_ARG_MAX)
4868 regno = regbase + slotno;
4871 case SFmode : case SCmode :
4872 case DFmode : case DCmode :
4873 case TFmode : case TCmode :
4876 if (slotno >= SPARC_INT_ARG_MAX)
4878 regno = regbase + slotno;
4882 if ((mode == TFmode || mode == TCmode)
4883 && (slotno & 1) != 0)
4884 slotno++, *ppadding = 1;
4885 if (TARGET_FPU && named)
4887 if (slotno >= SPARC_FP_ARG_MAX)
4889 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4895 if (slotno >= SPARC_INT_ARG_MAX)
4897 regno = regbase + slotno;
4903 /* For sparc64, objects requiring 16 byte alignment get it. */
4906 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4907 slotno++, *ppadding = 1;
4911 || (type && TREE_CODE (type) == UNION_TYPE))
4913 if (slotno >= SPARC_INT_ARG_MAX)
4915 regno = regbase + slotno;
4920 int intregs_p = 0, fpregs_p = 0;
4921 /* The ABI obviously doesn't specify how packed
4922 structures are passed. These are defined to be passed
4923 in int regs if possible, otherwise memory. */
4926 /* First see what kinds of registers we need. */
4927 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4929 if (TREE_CODE (field) == FIELD_DECL)
4931 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4936 if (DECL_PACKED (field))
4940 if (packed_p || !named)
4941 fpregs_p = 0, intregs_p = 1;
4943 /* If all arg slots are filled, then must pass on stack. */
4944 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4946 /* If there are only int args and all int arg slots are filled,
4947 then must pass on stack. */
4948 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4950 /* Note that even if all int arg slots are filled, fp members may
4951 still be passed in regs if such regs are available.
4952 *PREGNO isn't set because there may be more than one, it's up
4953 to the caller to compute them. */
4966 /* Handle recursive register counting for structure field layout. */
4968 struct function_arg_record_value_parms
4970 rtx ret; /* return expression being built. */
4971 int slotno; /* slot number of the argument. */
4972 int named; /* whether the argument is named. */
4973 int regbase; /* regno of the base register. */
4974 int stack; /* 1 if part of the argument is on the stack. */
4975 int intoffset; /* offset of the pending integer field. */
4976 unsigned int nregs; /* number of words passed in registers. */
4979 static void function_arg_record_value_3
4980 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4981 static void function_arg_record_value_2
4982 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4983 static void function_arg_record_value_1
4984 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4985 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4987 /* A subroutine of function_arg_record_value. Traverse the structure
4988 recursively and determine how many registers will be required. */
4991 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4992 struct function_arg_record_value_parms *parms,
4997 /* We need to compute how many registers are needed so we can
4998 allocate the PARALLEL but before we can do that we need to know
4999 whether there are any packed fields. The ABI obviously doesn't
5000 specify how structures are passed in this case, so they are
5001 defined to be passed in int regs if possible, otherwise memory,
5002 regardless of whether there are fp values present. */
5005 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5007 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5014 /* Compute how many registers we need. */
5015 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5017 if (TREE_CODE (field) == FIELD_DECL)
5019 HOST_WIDE_INT bitpos = startbitpos;
5021 if (DECL_SIZE (field) != 0
5022 && host_integerp (bit_position (field), 1))
5023 bitpos += int_bit_position (field);
5025 /* ??? FIXME: else assume zero offset. */
5027 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5028 function_arg_record_value_1 (TREE_TYPE (field),
5032 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5033 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5034 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5040 if (parms->intoffset != -1)
5042 int intslots, this_slotno;
5044 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
5046 this_slotno = parms->slotno + parms->intoffset
5049 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5051 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5052 /* We need to pass this field on the stack. */
5056 parms->nregs += intslots;
5057 parms->intoffset = -1;
5060 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5061 If it wasn't true we wouldn't be here. */
5063 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5068 if (parms->intoffset == -1)
5069 parms->intoffset = bitpos;
5075 /* A subroutine of function_arg_record_value. Assign the bits of the
5076 structure between parms->intoffset and bitpos to integer registers. */
5079 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5080 struct function_arg_record_value_parms *parms)
5082 enum machine_mode mode;
5084 unsigned int startbit, endbit;
5085 int this_slotno, intslots, intoffset;
5088 if (parms->intoffset == -1)
5091 intoffset = parms->intoffset;
5092 parms->intoffset = -1;
5094 startbit = intoffset & -BITS_PER_WORD;
5095 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5096 intslots = (endbit - startbit) / BITS_PER_WORD;
5097 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5099 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5103 /* If this is the trailing part of a word, only load that much into
5104 the register. Otherwise load the whole register. Note that in
5105 the latter case we may pick up unwanted bits. It's not a problem
5106 at the moment but may wish to revisit. */
5108 if (intoffset % BITS_PER_WORD != 0)
5109 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5114 intoffset /= BITS_PER_UNIT;
5117 regno = parms->regbase + this_slotno;
5118 reg = gen_rtx_REG (mode, regno);
5119 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5120 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5123 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5127 while (intslots > 0);
5130 /* A subroutine of function_arg_record_value. Traverse the structure
5131 recursively and assign bits to floating point registers. Track which
5132 bits in between need integer registers; invoke function_arg_record_value_3
5133 to make that happen. */
5136 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5137 struct function_arg_record_value_parms *parms,
5143 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5145 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5152 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5154 if (TREE_CODE (field) == FIELD_DECL)
5156 HOST_WIDE_INT bitpos = startbitpos;
5158 if (DECL_SIZE (field) != 0
5159 && host_integerp (bit_position (field), 1))
5160 bitpos += int_bit_position (field);
5162 /* ??? FIXME: else assume zero offset. */
5164 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5165 function_arg_record_value_2 (TREE_TYPE (field),
5169 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5170 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5171 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5177 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5179 enum machine_mode mode = DECL_MODE (field);
5182 function_arg_record_value_3 (bitpos, parms);
5183 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5184 + ((mode == SFmode || mode == SCmode)
5185 && (bitpos & 32) != 0);
5188 case SCmode: mode = SFmode; break;
5189 case DCmode: mode = DFmode; break;
5190 case TCmode: mode = TFmode; break;
5193 reg = gen_rtx_REG (mode, regno);
5194 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5195 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5196 GEN_INT (bitpos / BITS_PER_UNIT));
5198 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5200 regno += GET_MODE_SIZE (mode) / 4;
5201 reg = gen_rtx_REG (mode, regno);
5202 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5203 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5204 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5211 if (parms->intoffset == -1)
5212 parms->intoffset = bitpos;
5218 /* Used by function_arg and function_value to implement the complex
5219 conventions of the 64-bit ABI for passing and returning structures.
5220 Return an expression valid as a return value for the two macros
5221 FUNCTION_ARG and FUNCTION_VALUE.
5223 TYPE is the data type of the argument (as a tree).
5224 This is null for libcalls where that information may
5226 MODE is the argument's machine mode.
5227 SLOTNO is the index number of the argument's slot in the parameter array.
5228 NAMED is nonzero if this argument is a named parameter
5229 (otherwise it is an extra parameter matching an ellipsis).
5230 REGBASE is the regno of the base register for the parameter array. */
5233 function_arg_record_value (tree type, enum machine_mode mode,
5234 int slotno, int named, int regbase)
5236 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5237 struct function_arg_record_value_parms parms;
5240 parms.ret = NULL_RTX;
5241 parms.slotno = slotno;
5242 parms.named = named;
5243 parms.regbase = regbase;
5246 /* Compute how many registers we need. */
5248 parms.intoffset = 0;
5249 function_arg_record_value_1 (type, 0, &parms, false);
5251 if (parms.intoffset != -1)
5253 unsigned int startbit, endbit;
5254 int intslots, this_slotno;
5256 startbit = parms.intoffset & -BITS_PER_WORD;
5257 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5258 intslots = (endbit - startbit) / BITS_PER_WORD;
5259 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5261 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5263 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5264 /* We need to pass this field on the stack. */
5268 parms.nregs += intslots;
5270 nregs = parms.nregs;
5272 /* Allocate the vector and handle some annoying special cases. */
5275 /* ??? Empty structure has no value? Duh? */
5278 /* Though there's nothing really to store, return a word register
5279 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5280 leads to breakage due to the fact that there are zero bytes to
5282 return gen_rtx_REG (mode, regbase);
5286 /* ??? C++ has structures with no fields, and yet a size. Give up
5287 for now and pass everything back in integer registers. */
5288 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5290 if (nregs + slotno > SPARC_INT_ARG_MAX)
5291 nregs = SPARC_INT_ARG_MAX - slotno;
5296 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5298 /* If at least one field must be passed on the stack, generate
5299 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5300 also be passed on the stack. We can't do much better because the
5301 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5302 of structures for which the fields passed exclusively in registers
5303 are not at the beginning of the structure. */
5305 XVECEXP (parms.ret, 0, 0)
5306 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5308 /* Fill in the entries. */
5310 parms.intoffset = 0;
5311 function_arg_record_value_2 (type, 0, &parms, false);
5312 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5314 if (parms.nregs != nregs)
5320 /* Handle the FUNCTION_ARG macro.
5321 Determine where to put an argument to a function.
5322 Value is zero to push the argument on the stack,
5323 or a hard register in which to store the argument.
5325 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5326 the preceding args and about the function being called.
5327 MODE is the argument's machine mode.
5328 TYPE is the data type of the argument (as a tree).
5329 This is null for libcalls where that information may
5331 NAMED is nonzero if this argument is a named parameter
5332 (otherwise it is an extra parameter matching an ellipsis).
5333 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5336 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5337 tree type, int named, int incoming_p)
5339 int regbase = (incoming_p
5340 ? SPARC_INCOMING_INT_ARG_FIRST
5341 : SPARC_OUTGOING_INT_ARG_FIRST);
5342 int slotno, regno, padding;
5345 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5353 reg = gen_rtx_REG (mode, regno);
5357 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5358 but also have the slot allocated for them.
5359 If no prototype is in scope fp values in register slots get passed
5360 in two places, either fp regs and int regs or fp regs and memory. */
5361 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5362 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5363 && SPARC_FP_REG_P (regno))
5365 reg = gen_rtx_REG (mode, regno);
5366 if (cum->prototype_p || cum->libcall_p)
5368 /* "* 2" because fp reg numbers are recorded in 4 byte
5371 /* ??? This will cause the value to be passed in the fp reg and
5372 in the stack. When a prototype exists we want to pass the
5373 value in the reg but reserve space on the stack. That's an
5374 optimization, and is deferred [for a bit]. */
5375 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5376 return gen_rtx_PARALLEL (mode,
5378 gen_rtx_EXPR_LIST (VOIDmode,
5379 NULL_RTX, const0_rtx),
5380 gen_rtx_EXPR_LIST (VOIDmode,
5384 /* ??? It seems that passing back a register even when past
5385 the area declared by REG_PARM_STACK_SPACE will allocate
5386 space appropriately, and will not copy the data onto the
5387 stack, exactly as we desire.
5389 This is due to locate_and_pad_parm being called in
5390 expand_call whenever reg_parm_stack_space > 0, which
5391 while beneficial to our example here, would seem to be
5392 in error from what had been intended. Ho hum... -- r~ */
5400 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5404 /* On incoming, we don't need to know that the value
5405 is passed in %f0 and %i0, and it confuses other parts
5406 causing needless spillage even on the simplest cases. */
5410 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5411 + (regno - SPARC_FP_ARG_FIRST) / 2);
5413 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5414 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5416 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5420 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5421 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5422 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5426 else if (type && TREE_CODE (type) == RECORD_TYPE)
5428 /* Structures up to 16 bytes in size are passed in arg slots on the
5429 stack and are promoted to registers where possible. */
5431 if (int_size_in_bytes (type) > 16)
5432 abort (); /* shouldn't get here */
5434 return function_arg_record_value (type, mode, slotno, named, regbase);
5436 else if (type && TREE_CODE (type) == UNION_TYPE)
5438 enum machine_mode mode;
5439 int bytes = int_size_in_bytes (type);
5444 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5445 reg = gen_rtx_REG (mode, regno);
5449 /* Scalar or complex int. */
5450 reg = gen_rtx_REG (mode, regno);
5456 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5457 For an arg passed partly in registers and partly in memory,
5458 this is the number of registers used.
5459 For args passed entirely in registers or entirely in memory, zero.
5461 Any arg that starts in the first 6 regs but won't entirely fit in them
5462 needs partial registers on v8. On v9, structures with integer
5463 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5464 values that begin in the last fp reg [where "last fp reg" varies with the
5465 mode] will be split between that reg and memory. */
5468 function_arg_partial_nregs (const struct sparc_args *cum,
5469 enum machine_mode mode, tree type, int named)
5471 int slotno, regno, padding;
5473 /* We pass 0 for incoming_p here, it doesn't matter. */
5474 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5481 if ((slotno + (mode == BLKmode
5482 ? ROUND_ADVANCE (int_size_in_bytes (type))
5483 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5484 > NPARM_REGS (SImode))
5485 return NPARM_REGS (SImode) - slotno;
5490 if (type && AGGREGATE_TYPE_P (type))
5492 int size = int_size_in_bytes (type);
5493 int align = TYPE_ALIGN (type);
5496 slotno += slotno & 1;
5497 if (size > 8 && size <= 16
5498 && slotno == SPARC_INT_ARG_MAX - 1)
5501 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5502 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5503 && ! (TARGET_FPU && named)))
5505 /* The complex types are passed as packed types. */
5506 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5509 if (GET_MODE_ALIGNMENT (mode) == 128)
5511 slotno += slotno & 1;
5513 /* ??? The mode needs 3 slots? */
5514 if (slotno == SPARC_INT_ARG_MAX - 2)
5519 if (slotno == SPARC_INT_ARG_MAX - 1)
5523 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5525 if (GET_MODE_ALIGNMENT (mode) == 128)
5526 slotno += slotno & 1;
5527 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5535 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5536 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5537 quad-precision floats by invisible reference.
5538 v9: Aggregates greater than 16 bytes are passed by reference.
5539 For Pascal, also pass arrays by reference. */
5542 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5543 enum machine_mode mode, tree type,
5544 int named ATTRIBUTE_UNUSED)
5548 return ((type && AGGREGATE_TYPE_P (type))
5549 || mode == TFmode || mode == TCmode);
5553 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5554 /* Consider complex values as aggregates, so care
5555 for CTImode and TCmode. */
5556 || GET_MODE_SIZE (mode) > 16
5558 && AGGREGATE_TYPE_P (type)
5559 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5563 /* Handle the FUNCTION_ARG_ADVANCE macro.
5564 Update the data in CUM to advance over an argument
5565 of mode MODE and data type TYPE.
5566 TYPE is null for libcalls where that information may not be available. */
5569 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5570 tree type, int named)
5572 int slotno, regno, padding;
5574 /* We pass 0 for incoming_p here, it doesn't matter. */
5575 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5577 /* If register required leading padding, add it. */
5579 cum->words += padding;
5583 cum->words += (mode != BLKmode
5584 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5585 : ROUND_ADVANCE (int_size_in_bytes (type)));
5589 if (type && AGGREGATE_TYPE_P (type))
5591 int size = int_size_in_bytes (type);
5595 else if (size <= 16)
5597 else /* passed by reference */
5602 cum->words += (mode != BLKmode
5603 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5604 : ROUND_ADVANCE (int_size_in_bytes (type)));
5609 /* Handle the FUNCTION_ARG_PADDING macro.
5610 For the 64 bit ABI structs are always stored left shifted in their
5614 function_arg_padding (enum machine_mode mode, tree type)
5616 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5619 /* Fall back to the default. */
5620 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5623 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5624 For v9, function return values are subject to the same rules as arguments,
5625 except that up to 32-bytes may be returned in registers. */
5628 function_value (tree type, enum machine_mode mode, int incoming_p)
5631 int regbase = (incoming_p
5632 ? SPARC_OUTGOING_INT_ARG_FIRST
5633 : SPARC_INCOMING_INT_ARG_FIRST);
5635 if (TARGET_ARCH64 && type)
5637 if (TREE_CODE (type) == RECORD_TYPE)
5639 /* Structures up to 32 bytes in size are passed in registers,
5640 promoted to fp registers where possible. */
5642 if (int_size_in_bytes (type) > 32)
5643 abort (); /* shouldn't get here */
5645 return function_arg_record_value (type, mode, 0, 1, regbase);
5647 else if (AGGREGATE_TYPE_P (type))
5649 /* All other aggregate types are passed in an integer register
5650 in a mode corresponding to the size of the type. */
5651 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5656 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5661 && GET_MODE_CLASS (mode) == MODE_INT
5662 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5663 && type && ! AGGREGATE_TYPE_P (type))
5667 regno = BASE_RETURN_VALUE_REG (mode);
5669 regno = BASE_OUTGOING_VALUE_REG (mode);
5671 return gen_rtx_REG (mode, regno);
5674 /* Do what is necessary for `va_start'. We look at the current function
5675 to determine if stdarg or varargs is used and return the address of
5676 the first unnamed parameter. */
5679 sparc_builtin_saveregs (void)
5681 int first_reg = current_function_args_info.words;
5685 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5686 emit_move_insn (gen_rtx_MEM (word_mode,
5687 gen_rtx_PLUS (Pmode,
5689 GEN_INT (FIRST_PARM_OFFSET (0)
5692 gen_rtx_REG (word_mode,
5693 BASE_INCOMING_ARG_REG (word_mode) + regno));
5695 address = gen_rtx_PLUS (Pmode,
5697 GEN_INT (FIRST_PARM_OFFSET (0)
5698 + UNITS_PER_WORD * first_reg));
5703 /* Implement `va_start' for varargs and stdarg. */
5706 sparc_va_start (tree valist, rtx nextarg)
5708 nextarg = expand_builtin_saveregs ();
5709 std_expand_builtin_va_start (valist, nextarg);
5712 /* Implement `va_arg'. */
5715 sparc_va_arg (tree valist, tree type)
5717 HOST_WIDE_INT size, rsize, align;
5722 /* Round up sizeof(type) to a word. */
5723 size = int_size_in_bytes (type);
5724 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5729 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5730 align = 2 * UNITS_PER_WORD;
5732 /* Consider complex values as aggregates, so care
5733 for CTImode and TCmode. */
5734 if ((unsigned HOST_WIDE_INT) size > 16)
5737 size = rsize = UNITS_PER_WORD;
5740 else if (AGGREGATE_TYPE_P (type))
5742 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5743 are given whole slots as needed. */
5745 size = rsize = UNITS_PER_WORD;
5752 if (AGGREGATE_TYPE_P (type)
5753 || TYPE_MODE (type) == TFmode
5754 || TYPE_MODE (type) == TCmode)
5757 size = rsize = UNITS_PER_WORD;
5764 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5765 build_int_2 (align - 1, 0)));
5766 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5767 build_int_2 (-align, -1)));
5770 addr = incr = save_expr (incr);
5771 if (BYTES_BIG_ENDIAN && size < rsize)
5773 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5774 build_int_2 (rsize - size, 0)));
5776 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5777 build_int_2 (rsize, 0)));
5779 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5780 TREE_SIDE_EFFECTS (incr) = 1;
5781 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5783 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5785 /* If the address isn't aligned properly for the type,
5786 we may need to copy to a temporary.
5787 FIXME: This is inefficient. Usually we can do this
5790 && TYPE_ALIGN (type) > BITS_PER_WORD
5793 /* FIXME: We really need to specify that the temporary is live
5794 for the whole function because expand_builtin_va_arg wants
5795 the alias set to be get_varargs_alias_set (), but in this
5796 case the alias set is that for TYPE and if the memory gets
5797 reused it will be reused with alias set TYPE. */
5798 rtx tmp = assign_temp (type, 0, 1, 0);
5801 addr_rtx = force_reg (Pmode, addr_rtx);
5802 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5803 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5804 set_mem_align (addr_rtx, BITS_PER_WORD);
5805 tmp = shallow_copy_rtx (tmp);
5806 PUT_MODE (tmp, BLKmode);
5807 set_mem_alias_set (tmp, 0);
5809 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5811 if (dest_addr != NULL_RTX)
5812 addr_rtx = dest_addr;
5814 addr_rtx = XCEXP (tmp, 0, MEM);
5819 addr_rtx = force_reg (Pmode, addr_rtx);
5820 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5821 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5827 /* Return the string to output a conditional branch to LABEL, which is
5828 the operand number of the label. OP is the conditional expression.
5829 XEXP (OP, 0) is assumed to be a condition code register (integer or
5830 floating point) and its mode specifies what kind of comparison we made.
5832 REVERSED is nonzero if we should reverse the sense of the comparison.
5834 ANNUL is nonzero if we should generate an annulling branch.
5836 NOOP is nonzero if we have to follow this branch by a noop.
5838 INSN, if set, is the insn. */
5841 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5844 static char string[50];
5845 enum rtx_code code = GET_CODE (op);
5846 rtx cc_reg = XEXP (op, 0);
5847 enum machine_mode mode = GET_MODE (cc_reg);
5848 const char *labelno, *branch;
5849 int spaces = 8, far;
5852 /* v9 branches are limited to +-1MB. If it is too far away,
5865 fbne,a,pn %fcc2, .LC29
5873 far = get_attr_length (insn) >= 3;
5876 /* Reversal of FP compares takes care -- an ordered compare
5877 becomes an unordered compare and vice versa. */
5878 if (mode == CCFPmode || mode == CCFPEmode)
5879 code = reverse_condition_maybe_unordered (code);
5881 code = reverse_condition (code);
5884 /* Start by writing the branch condition. */
5885 if (mode == CCFPmode || mode == CCFPEmode)
5936 /* ??? !v9: FP branches cannot be preceded by another floating point
5937 insn. Because there is currently no concept of pre-delay slots,
5938 we can fix this only by always emitting a nop before a floating
5943 strcpy (string, "nop\n\t");
5944 strcat (string, branch);
5957 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5969 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5990 strcpy (string, branch);
5992 spaces -= strlen (branch);
5993 p = strchr (string, '\0');
5995 /* Now add the annulling, the label, and a possible noop. */
6010 if (! far && insn && INSN_ADDRESSES_SET_P ())
6012 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6013 - INSN_ADDRESSES (INSN_UID (insn)));
6014 /* Leave some instructions for "slop". */
6015 if (delta < -260000 || delta >= 260000)
6019 if (mode == CCFPmode || mode == CCFPEmode)
6021 static char v9_fcc_labelno[] = "%%fccX, ";
6022 /* Set the char indicating the number of the fcc reg to use. */
6023 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6024 labelno = v9_fcc_labelno;
6027 if (REGNO (cc_reg) == SPARC_FCC_REG)
6033 else if (mode == CCXmode || mode == CCX_NOOVmode)
6035 labelno = "%%xcc, ";
6041 labelno = "%%icc, ";
6046 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6049 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6059 strcpy (p, labelno);
6060 p = strchr (p, '\0');
6063 strcpy (p, ".+12\n\tnop\n\tb\t");
6070 /* Set the char indicating the number of the operand containing the
6075 strcpy (p, "\n\tnop");
6080 /* Emit a library call comparison between floating point X and Y.
6081 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6082 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6083 values as arguments instead of the TFmode registers themselves,
6084 that's why we cannot call emit_float_lib_cmp. */
6086 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6089 rtx slot0, slot1, result, tem, tem2;
6090 enum machine_mode mode;
6095 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6099 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6103 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6107 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6111 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6115 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6126 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6136 if (GET_CODE (x) != MEM)
6138 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6139 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6144 if (GET_CODE (y) != MEM)
6146 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6147 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6152 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6154 XEXP (slot0, 0), Pmode,
6155 XEXP (slot1, 0), Pmode);
6161 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6163 x, TFmode, y, TFmode);
6169 /* Immediately move the result of the libcall into a pseudo
6170 register so reload doesn't clobber the value if it needs
6171 the return register for a spill reg. */
6172 result = gen_reg_rtx (mode);
6173 emit_move_insn (result, hard_libcall_value (mode));
6178 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6182 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6187 emit_cmp_insn (result, const1_rtx,
6188 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6191 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6194 tem = gen_reg_rtx (mode);
6196 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6198 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6199 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6203 tem = gen_reg_rtx (mode);
6205 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6207 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6208 tem2 = gen_reg_rtx (mode);
6210 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6212 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6213 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6219 /* Generate an unsigned DImode to FP conversion. This is the same code
6220 optabs would emit if we didn't have TFmode patterns. */
6223 sparc_emit_floatunsdi (rtx *operands)
6225 rtx neglab, donelab, i0, i1, f0, in, out;
6226 enum machine_mode mode;
6229 in = force_reg (DImode, operands[1]);
6230 mode = GET_MODE (out);
6231 neglab = gen_label_rtx ();
6232 donelab = gen_label_rtx ();
6233 i0 = gen_reg_rtx (DImode);
6234 i1 = gen_reg_rtx (DImode);
6235 f0 = gen_reg_rtx (mode);
6237 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6239 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6240 emit_jump_insn (gen_jump (donelab));
6243 emit_label (neglab);
6245 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6246 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6247 emit_insn (gen_iordi3 (i0, i0, i1));
6248 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6249 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6251 emit_label (donelab);
6254 /* Return the string to output a conditional branch to LABEL, testing
6255 register REG. LABEL is the operand number of the label; REG is the
6256 operand number of the reg. OP is the conditional expression. The mode
6257 of REG says what kind of comparison we made.
6259 REVERSED is nonzero if we should reverse the sense of the comparison.
6261 ANNUL is nonzero if we should generate an annulling branch.
6263 NOOP is nonzero if we have to follow this branch by a noop. */
6266 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6267 int annul, int noop, rtx insn)
6269 static char string[50];
6270 enum rtx_code code = GET_CODE (op);
6271 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6276 /* branch on register are limited to +-128KB. If it is too far away,
6289 brgez,a,pn %o1, .LC29
6295 ba,pt %xcc, .LC29 */
6297 far = get_attr_length (insn) >= 3;
6299 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6301 code = reverse_condition (code);
6303 /* Only 64 bit versions of these instructions exist. */
6307 /* Start by writing the branch condition. */
6312 strcpy (string, "brnz");
6316 strcpy (string, "brz");
6320 strcpy (string, "brgez");
6324 strcpy (string, "brlz");
6328 strcpy (string, "brlez");
6332 strcpy (string, "brgz");
6339 p = strchr (string, '\0');
6341 /* Now add the annulling, reg, label, and nop. */
6348 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6351 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6356 *p = p < string + 8 ? '\t' : ' ';
6364 int veryfar = 1, delta;
6366 if (INSN_ADDRESSES_SET_P ())
6368 delta = (INSN_ADDRESSES (INSN_UID (dest))
6369 - INSN_ADDRESSES (INSN_UID (insn)));
6370 /* Leave some instructions for "slop". */
6371 if (delta >= -260000 && delta < 260000)
6375 strcpy (p, ".+12\n\tnop\n\t");
6386 strcpy (p, "ba,pt\t%%xcc, ");
6396 strcpy (p, "\n\tnop");
6401 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6402 Such instructions cannot be used in the delay slot of return insn on v9.
6403 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6407 epilogue_renumber (register rtx *where, int test)
6409 register const char *fmt;
6411 register enum rtx_code code;
6416 code = GET_CODE (*where);
6421 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6423 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6424 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6432 /* Do not replace the frame pointer with the stack pointer because
6433 it can cause the delayed instruction to load below the stack.
6434 This occurs when instructions like:
6436 (set (reg/i:SI 24 %i0)
6437 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6438 (const_int -20 [0xffffffec])) 0))
6440 are in the return delayed slot. */
6442 if (GET_CODE (XEXP (*where, 0)) == REG
6443 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6444 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6445 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6450 if (SPARC_STACK_BIAS
6451 && GET_CODE (XEXP (*where, 0)) == REG
6452 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6460 fmt = GET_RTX_FORMAT (code);
6462 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6467 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6468 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6471 else if (fmt[i] == 'e'
6472 && epilogue_renumber (&(XEXP (*where, i)), test))
6478 /* Leaf functions and non-leaf functions have different needs. */
6481 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6484 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6486 static const int *const reg_alloc_orders[] = {
6487 reg_leaf_alloc_order,
6488 reg_nonleaf_alloc_order};
6491 order_regs_for_local_alloc (void)
6493 static int last_order_nonleaf = 1;
6495 if (regs_ever_live[15] != last_order_nonleaf)
6497 last_order_nonleaf = !last_order_nonleaf;
6498 memcpy ((char *) reg_alloc_order,
6499 (const char *) reg_alloc_orders[last_order_nonleaf],
6500 FIRST_PSEUDO_REGISTER * sizeof (int));
6504 /* Return 1 if REG and MEM are legitimate enough to allow the various
6505 mem<-->reg splits to be run. */
6508 sparc_splitdi_legitimate (rtx reg, rtx mem)
6510 /* Punt if we are here by mistake. */
6511 if (! reload_completed)
6514 /* We must have an offsettable memory reference. */
6515 if (! offsettable_memref_p (mem))
6518 /* If we have legitimate args for ldd/std, we do not want
6519 the split to happen. */
6520 if ((REGNO (reg) % 2) == 0
6521 && mem_min_alignment (mem, 8))
6528 /* Return 1 if x and y are some kind of REG and they refer to
6529 different hard registers. This test is guaranteed to be
6530 run after reload. */
6533 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6535 if (GET_CODE (x) != REG)
6537 if (GET_CODE (y) != REG)
6539 if (REGNO (x) == REGNO (y))
6544 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6545 This makes them candidates for using ldd and std insns.
6547 Note reg1 and reg2 *must* be hard registers. */
6550 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6552 /* We might have been passed a SUBREG. */
6553 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6556 if (REGNO (reg1) % 2 != 0)
6559 /* Integer ldd is deprecated in SPARC V9 */
6560 if (TARGET_V9 && REGNO (reg1) < 32)
6563 return (REGNO (reg1) == REGNO (reg2) - 1);
6566 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6569 This can only happen when addr1 and addr2, the addresses in mem1
6570 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6571 addr1 must also be aligned on a 64-bit boundary.
6573 Also iff dependent_reg_rtx is not null it should not be used to
6574 compute the address for mem1, i.e. we cannot optimize a sequence
6586 But, note that the transformation from:
6591 is perfectly fine. Thus, the peephole2 patterns always pass us
6592 the destination register of the first load, never the second one.
6594 For stores we don't have a similar problem, so dependent_reg_rtx is
6598 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6602 HOST_WIDE_INT offset1;
6604 /* The mems cannot be volatile. */
6605 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6608 /* MEM1 should be aligned on a 64-bit boundary. */
6609 if (MEM_ALIGN (mem1) < 64)
6612 addr1 = XEXP (mem1, 0);
6613 addr2 = XEXP (mem2, 0);
6615 /* Extract a register number and offset (if used) from the first addr. */
6616 if (GET_CODE (addr1) == PLUS)
6618 /* If not a REG, return zero. */
6619 if (GET_CODE (XEXP (addr1, 0)) != REG)
6623 reg1 = REGNO (XEXP (addr1, 0));
6624 /* The offset must be constant! */
6625 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6627 offset1 = INTVAL (XEXP (addr1, 1));
6630 else if (GET_CODE (addr1) != REG)
6634 reg1 = REGNO (addr1);
6635 /* This was a simple (mem (reg)) expression. Offset is 0. */
6639 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6640 if (GET_CODE (addr2) != PLUS)
6643 if (GET_CODE (XEXP (addr2, 0)) != REG
6644 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6647 if (reg1 != REGNO (XEXP (addr2, 0)))
6650 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6653 /* The first offset must be evenly divisible by 8 to ensure the
6654 address is 64 bit aligned. */
6655 if (offset1 % 8 != 0)
6658 /* The offset for the second addr must be 4 more than the first addr. */
6659 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6662 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6667 /* Return 1 if reg is a pseudo, or is the first register in
6668 a hard register pair. This makes it a candidate for use in
6669 ldd and std insns. */
6672 register_ok_for_ldd (rtx reg)
6674 /* We might have been passed a SUBREG. */
6675 if (GET_CODE (reg) != REG)
6678 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6679 return (REGNO (reg) % 2 == 0);
6684 /* Print operand X (an rtx) in assembler syntax to file FILE.
6685 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6686 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6689 print_operand (FILE *file, rtx x, int code)
6694 /* Output a 'nop' if there's nothing for the delay slot. */
6695 if (dbr_sequence_length () == 0)
6696 fputs ("\n\t nop", file);
6699 /* Output an annul flag if there's nothing for the delay slot and we
6700 are optimizing. This is always used with '(' below. */
6701 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6702 this is a dbx bug. So, we only do this when optimizing. */
6703 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6704 Always emit a nop in case the next instruction is a branch. */
6705 if (dbr_sequence_length () == 0
6706 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6710 /* Output a 'nop' if there's nothing for the delay slot and we are
6711 not optimizing. This is always used with '*' above. */
6712 if (dbr_sequence_length () == 0
6713 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6714 fputs ("\n\t nop", file);
6717 /* Output the Embedded Medium/Anywhere code model base register. */
6718 fputs (EMBMEDANY_BASE_REG, file);
6721 /* Print out what we are using as the frame pointer. This might
6722 be %fp, or might be %sp+offset. */
6723 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6724 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6727 /* Print some local dynamic TLS name. */
6728 assemble_name (file, get_some_local_dynamic_name ());
6731 /* Adjust the operand to take into account a RESTORE operation. */
6732 if (GET_CODE (x) == CONST_INT)
6734 else if (GET_CODE (x) != REG)
6735 output_operand_lossage ("invalid %%Y operand");
6736 else if (REGNO (x) < 8)
6737 fputs (reg_names[REGNO (x)], file);
6738 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6739 fputs (reg_names[REGNO (x)-16], file);
6741 output_operand_lossage ("invalid %%Y operand");
6744 /* Print out the low order register name of a register pair. */
6745 if (WORDS_BIG_ENDIAN)
6746 fputs (reg_names[REGNO (x)+1], file);
6748 fputs (reg_names[REGNO (x)], file);
6751 /* Print out the high order register name of a register pair. */
6752 if (WORDS_BIG_ENDIAN)
6753 fputs (reg_names[REGNO (x)], file);
6755 fputs (reg_names[REGNO (x)+1], file);
6758 /* Print out the second register name of a register pair or quad.
6759 I.e., R (%o0) => %o1. */
6760 fputs (reg_names[REGNO (x)+1], file);
6763 /* Print out the third register name of a register quad.
6764 I.e., S (%o0) => %o2. */
6765 fputs (reg_names[REGNO (x)+2], file);
6768 /* Print out the fourth register name of a register quad.
6769 I.e., T (%o0) => %o3. */
6770 fputs (reg_names[REGNO (x)+3], file);
6773 /* Print a condition code register. */
6774 if (REGNO (x) == SPARC_ICC_REG)
6776 /* We don't handle CC[X]_NOOVmode because they're not supposed
6778 if (GET_MODE (x) == CCmode)
6779 fputs ("%icc", file);
6780 else if (GET_MODE (x) == CCXmode)
6781 fputs ("%xcc", file);
6786 /* %fccN register */
6787 fputs (reg_names[REGNO (x)], file);
6790 /* Print the operand's address only. */
6791 output_address (XEXP (x, 0));
6794 /* In this case we need a register. Use %g0 if the
6795 operand is const0_rtx. */
6797 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6799 fputs ("%g0", file);
6806 switch (GET_CODE (x))
6808 case IOR: fputs ("or", file); break;
6809 case AND: fputs ("and", file); break;
6810 case XOR: fputs ("xor", file); break;
6811 default: output_operand_lossage ("invalid %%A operand");
6816 switch (GET_CODE (x))
6818 case IOR: fputs ("orn", file); break;
6819 case AND: fputs ("andn", file); break;
6820 case XOR: fputs ("xnor", file); break;
6821 default: output_operand_lossage ("invalid %%B operand");
6825 /* These are used by the conditional move instructions. */
6829 enum rtx_code rc = GET_CODE (x);
6833 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6834 if (mode == CCFPmode || mode == CCFPEmode)
6835 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6837 rc = reverse_condition (GET_CODE (x));
6841 case NE: fputs ("ne", file); break;
6842 case EQ: fputs ("e", file); break;
6843 case GE: fputs ("ge", file); break;
6844 case GT: fputs ("g", file); break;
6845 case LE: fputs ("le", file); break;
6846 case LT: fputs ("l", file); break;
6847 case GEU: fputs ("geu", file); break;
6848 case GTU: fputs ("gu", file); break;
6849 case LEU: fputs ("leu", file); break;
6850 case LTU: fputs ("lu", file); break;
6851 case LTGT: fputs ("lg", file); break;
6852 case UNORDERED: fputs ("u", file); break;
6853 case ORDERED: fputs ("o", file); break;
6854 case UNLT: fputs ("ul", file); break;
6855 case UNLE: fputs ("ule", file); break;
6856 case UNGT: fputs ("ug", file); break;
6857 case UNGE: fputs ("uge", file); break;
6858 case UNEQ: fputs ("ue", file); break;
6859 default: output_operand_lossage (code == 'c'
6860 ? "invalid %%c operand"
6861 : "invalid %%C operand");
6866 /* These are used by the movr instruction pattern. */
6870 enum rtx_code rc = (code == 'd'
6871 ? reverse_condition (GET_CODE (x))
6875 case NE: fputs ("ne", file); break;
6876 case EQ: fputs ("e", file); break;
6877 case GE: fputs ("gez", file); break;
6878 case LT: fputs ("lz", file); break;
6879 case LE: fputs ("lez", file); break;
6880 case GT: fputs ("gz", file); break;
6881 default: output_operand_lossage (code == 'd'
6882 ? "invalid %%d operand"
6883 : "invalid %%D operand");
6890 /* Print a sign-extended character. */
6891 int i = trunc_int_for_mode (INTVAL (x), QImode);
6892 fprintf (file, "%d", i);
6897 /* Operand must be a MEM; write its address. */
6898 if (GET_CODE (x) != MEM)
6899 output_operand_lossage ("invalid %%f operand");
6900 output_address (XEXP (x, 0));
6905 /* Print a sign-extended 32-bit value. */
6907 if (GET_CODE(x) == CONST_INT)
6909 else if (GET_CODE(x) == CONST_DOUBLE)
6910 i = CONST_DOUBLE_LOW (x);
6913 output_operand_lossage ("invalid %%s operand");
6916 i = trunc_int_for_mode (i, SImode);
6917 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6922 /* Do nothing special. */
6926 /* Undocumented flag. */
6927 output_operand_lossage ("invalid operand output code");
6930 if (GET_CODE (x) == REG)
6931 fputs (reg_names[REGNO (x)], file);
6932 else if (GET_CODE (x) == MEM)
6935 /* Poor Sun assembler doesn't understand absolute addressing. */
6936 if (CONSTANT_P (XEXP (x, 0)))
6937 fputs ("%g0+", file);
6938 output_address (XEXP (x, 0));
6941 else if (GET_CODE (x) == HIGH)
6943 fputs ("%hi(", file);
6944 output_addr_const (file, XEXP (x, 0));
6947 else if (GET_CODE (x) == LO_SUM)
6949 print_operand (file, XEXP (x, 0), 0);
6950 if (TARGET_CM_MEDMID)
6951 fputs ("+%l44(", file);
6953 fputs ("+%lo(", file);
6954 output_addr_const (file, XEXP (x, 1));
6957 else if (GET_CODE (x) == CONST_DOUBLE
6958 && (GET_MODE (x) == VOIDmode
6959 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6961 if (CONST_DOUBLE_HIGH (x) == 0)
6962 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6963 else if (CONST_DOUBLE_HIGH (x) == -1
6964 && CONST_DOUBLE_LOW (x) < 0)
6965 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6967 output_operand_lossage ("long long constant not a valid immediate operand");
6969 else if (GET_CODE (x) == CONST_DOUBLE)
6970 output_operand_lossage ("floating point constant not a valid immediate operand");
6971 else { output_addr_const (file, x); }
6974 /* Target hook for assembling integer objects. The sparc version has
6975 special handling for aligned DI-mode objects. */
6978 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6980 /* ??? We only output .xword's for symbols and only then in environments
6981 where the assembler can handle them. */
6982 if (aligned_p && size == 8
6983 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6987 assemble_integer_with_op ("\t.xword\t", x);
6992 assemble_aligned_integer (4, const0_rtx);
6993 assemble_aligned_integer (4, x);
6997 return default_assemble_integer (x, size, aligned_p);
7000 /* Return the value of a code used in the .proc pseudo-op that says
7001 what kind of result this function returns. For non-C types, we pick
7002 the closest C type. */
7004 #ifndef SHORT_TYPE_SIZE
7005 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7008 #ifndef INT_TYPE_SIZE
7009 #define INT_TYPE_SIZE BITS_PER_WORD
7012 #ifndef LONG_TYPE_SIZE
7013 #define LONG_TYPE_SIZE BITS_PER_WORD
7016 #ifndef LONG_LONG_TYPE_SIZE
7017 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7020 #ifndef FLOAT_TYPE_SIZE
7021 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7024 #ifndef DOUBLE_TYPE_SIZE
7025 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7028 #ifndef LONG_DOUBLE_TYPE_SIZE
7029 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7033 sparc_type_code (register tree type)
7035 register unsigned long qualifiers = 0;
7036 register unsigned shift;
7038 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7039 setting more, since some assemblers will give an error for this. Also,
7040 we must be careful to avoid shifts of 32 bits or more to avoid getting
7041 unpredictable results. */
7043 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7045 switch (TREE_CODE (type))
7051 qualifiers |= (3 << shift);
7056 qualifiers |= (2 << shift);
7060 case REFERENCE_TYPE:
7062 qualifiers |= (1 << shift);
7066 return (qualifiers | 8);
7069 case QUAL_UNION_TYPE:
7070 return (qualifiers | 9);
7073 return (qualifiers | 10);
7076 return (qualifiers | 16);
7079 /* If this is a range type, consider it to be the underlying
7081 if (TREE_TYPE (type) != 0)
7084 /* Carefully distinguish all the standard types of C,
7085 without messing up if the language is not C. We do this by
7086 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7087 look at both the names and the above fields, but that's redundant.
7088 Any type whose size is between two C types will be considered
7089 to be the wider of the two types. Also, we do not have a
7090 special code to use for "long long", so anything wider than
7091 long is treated the same. Note that we can't distinguish
7092 between "int" and "long" in this code if they are the same
7093 size, but that's fine, since neither can the assembler. */
7095 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7096 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7098 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7099 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7101 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7102 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7105 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7108 /* If this is a range type, consider it to be the underlying
7110 if (TREE_TYPE (type) != 0)
7113 /* Carefully distinguish all the standard types of C,
7114 without messing up if the language is not C. */
7116 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7117 return (qualifiers | 6);
7120 return (qualifiers | 7);
7122 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7123 /* ??? We need to distinguish between double and float complex types,
7124 but I don't know how yet because I can't reach this code from
7125 existing front-ends. */
7126 return (qualifiers | 7); /* Who knows? */
7128 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7129 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7130 case FILE_TYPE: /* GNU Pascal FILE type. */
7131 case SET_TYPE: /* GNU Pascal SET type. */
7132 case LANG_TYPE: /* ? */
7136 abort (); /* Not a type! */
7143 /* Nested function support. */
7145 /* Emit RTL insns to initialize the variable parts of a trampoline.
7146 FNADDR is an RTX for the address of the function's pure code.
7147 CXT is an RTX for the static chain value for the function.
7149 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7150 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7151 (to store insns). This is a bit excessive. Perhaps a different
7152 mechanism would be better here.
7154 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7157 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7159 /* SPARC 32-bit trampoline:
7162 sethi %hi(static), %g2
7164 or %g2, %lo(static), %g2
7166 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7167 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7171 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7172 expand_binop (SImode, ior_optab,
7173 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7174 size_int (10), 0, 1),
7175 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7176 NULL_RTX, 1, OPTAB_DIRECT));
7179 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7180 expand_binop (SImode, ior_optab,
7181 expand_shift (RSHIFT_EXPR, SImode, cxt,
7182 size_int (10), 0, 1),
7183 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7184 NULL_RTX, 1, OPTAB_DIRECT));
7187 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7188 expand_binop (SImode, ior_optab,
7189 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7190 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7191 NULL_RTX, 1, OPTAB_DIRECT));
7194 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7195 expand_binop (SImode, ior_optab,
7196 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7197 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7198 NULL_RTX, 1, OPTAB_DIRECT));
7200 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7201 aligned on a 16 byte boundary so one flush clears it all. */
7202 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7203 if (sparc_cpu != PROCESSOR_ULTRASPARC
7204 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7205 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7206 plus_constant (tramp, 8)))));
7208 /* Call __enable_execute_stack after writing onto the stack to make sure
7209 the stack address is accessible. */
7210 #ifdef TRANSFER_FROM_TRAMPOLINE
7211 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7212 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7217 /* The 64-bit version is simpler because it makes more sense to load the
7218 values as "immediate" data out of the trampoline. It's also easier since
7219 we can read the PC without clobbering a register. */
7222 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7224 /* SPARC 64-bit trampoline:
7233 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7234 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7235 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7236 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7237 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7238 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7239 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7240 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7241 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7242 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7243 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7245 if (sparc_cpu != PROCESSOR_ULTRASPARC
7246 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7247 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7249 /* Call __enable_execute_stack after writing onto the stack to make sure
7250 the stack address is accessible. */
7251 #ifdef TRANSFER_FROM_TRAMPOLINE
7252 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7253 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7257 /* Subroutines to support a flat (single) register window calling
7260 /* Single-register window sparc stack frames look like:
7262 Before call After call
7263 +-----------------------+ +-----------------------+
7265 mem | caller's temps. | | caller's temps. |
7267 +-----------------------+ +-----------------------+
7269 | arguments on stack. | | arguments on stack. |
7271 +-----------------------+FP+92->+-----------------------+
7272 | 6 words to save | | 6 words to save |
7273 | arguments passed | | arguments passed |
7274 | in registers, even | | in registers, even |
7275 | if not passed. | | if not passed. |
7276 SP+68->+-----------------------+FP+68->+-----------------------+
7277 | 1 word struct addr | | 1 word struct addr |
7278 +-----------------------+FP+64->+-----------------------+
7280 | 16 word reg save area | | 16 word reg save area |
7282 SP->+-----------------------+ FP->+-----------------------+
7284 | fp/alu reg moves |
7285 FP-16->+-----------------------+
7289 +-----------------------+
7291 | fp register save |
7293 +-----------------------+
7295 | gp register save |
7297 +-----------------------+
7299 | alloca allocations |
7301 +-----------------------+
7303 | arguments on stack |
7305 SP+92->+-----------------------+
7307 | arguments passed |
7308 | in registers, even |
7309 low | if not passed. |
7310 memory SP+68->+-----------------------+
7311 | 1 word struct addr |
7312 SP+64->+-----------------------+
7314 I 16 word reg save area |
7316 SP->+-----------------------+ */
7318 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7319 save masks, and offsets for the current function. */
7321 struct sparc_frame_info
7323 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7324 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7325 int args_size; /* # bytes that outgoing arguments take up. */
7326 int extra_size; /* # bytes of extra gunk. */
7327 int gp_reg_size; /* # bytes needed to store gp regs. */
7328 int fp_reg_size; /* # bytes needed to store fp regs. */
7329 unsigned long gmask; /* Mask of saved gp registers. */
7330 unsigned long fmask; /* Mask of saved fp registers. */
7331 int reg_offset; /* Offset from new sp to store regs. */
7332 int initialized; /* Nonzero if frame size already calculated. */
7335 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7336 struct sparc_frame_info current_frame_info;
7338 /* Zero structure to initialize current_frame_info. */
7339 struct sparc_frame_info zero_frame_info;
7341 #define RETURN_ADDR_REGNUM 15
7342 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7343 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7345 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7348 sparc_flat_must_save_register_p (int regno)
7350 /* General case: call-saved registers live at some point. */
7351 if (!call_used_regs[regno] && regs_ever_live[regno])
7354 /* Frame pointer register (%i7) if needed. */
7355 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7358 /* PIC register (%l7) if needed. */
7359 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7360 && flag_pic && current_function_uses_pic_offset_table)
7363 /* Return address register (%o7) if needed. */
7364 if (regno == RETURN_ADDR_REGNUM
7365 && (regs_ever_live[RETURN_ADDR_REGNUM]
7366 /* When the PIC offset table is used, the PIC register
7367 is set by using a bare call that clobbers %o7. */
7368 || (flag_pic && current_function_uses_pic_offset_table)))
7374 /* Return the bytes needed to compute the frame pointer from the current
7378 sparc_flat_compute_frame_size (HOST_WIDE_INT size)
7379 /* # of var. bytes allocated. */
7382 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7383 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7384 int args_size; /* # bytes that outgoing arguments take up. */
7385 int extra_size; /* # extra bytes. */
7386 int gp_reg_size; /* # bytes needed to store gp regs. */
7387 int fp_reg_size; /* # bytes needed to store fp regs. */
7388 unsigned long gmask; /* Mask of saved gp registers. */
7389 unsigned long fmask; /* Mask of saved fp registers. */
7390 int reg_offset; /* Offset to register save area. */
7391 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7393 /* This is the size of the 16 word reg save area, 1 word struct addr
7394 area, and 4 word fp/alu register copy area. */
7395 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7405 if (!leaf_function_p ())
7407 /* Also include the size needed for the 6 parameter registers. */
7408 args_size = current_function_outgoing_args_size + 24;
7410 total_size = var_size + args_size;
7412 /* Calculate space needed for gp registers. */
7413 for (regno = 1; regno <= 31; regno++)
7415 if (sparc_flat_must_save_register_p (regno))
7417 /* If we need to save two regs in a row, ensure there's room to bump
7418 up the address to align it to a doubleword boundary. */
7419 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7421 if (gp_reg_size % 8 != 0)
7423 gp_reg_size += 2 * UNITS_PER_WORD;
7424 gmask |= 3 << regno;
7430 gp_reg_size += UNITS_PER_WORD;
7431 gmask |= 1 << regno;
7436 /* Calculate space needed for fp registers. */
7437 for (regno = 32; regno <= 63; regno++)
7439 if (regs_ever_live[regno] && !call_used_regs[regno])
7441 fp_reg_size += UNITS_PER_WORD;
7442 fmask |= 1 << (regno - 32);
7449 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7450 /* Ensure save area is 8 byte aligned if we need it. */
7452 if (need_aligned_p && n != 0)
7454 total_size += 8 - n;
7455 reg_offset += 8 - n;
7457 total_size += gp_reg_size + fp_reg_size;
7460 /* If we must allocate a stack frame at all, we must also allocate
7461 room for register window spillage, so as to be binary compatible
7462 with libraries and operating systems that do not use -mflat. */
7464 total_size += extra_size;
7468 total_size = SPARC_STACK_ALIGN (total_size);
7470 /* Save other computed information. */
7471 current_frame_info.total_size = total_size;
7472 current_frame_info.var_size = var_size;
7473 current_frame_info.args_size = args_size;
7474 current_frame_info.extra_size = extra_size;
7475 current_frame_info.gp_reg_size = gp_reg_size;
7476 current_frame_info.fp_reg_size = fp_reg_size;
7477 current_frame_info.gmask = gmask;
7478 current_frame_info.fmask = fmask;
7479 current_frame_info.reg_offset = reg_offset;
7480 current_frame_info.initialized = reload_completed;
7482 /* Ok, we're done. */
7486 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7489 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7490 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7491 [BASE_REG+OFFSET] will always be a valid address.
7493 WORD_OP is either "st" for save, "ld" for restore.
7494 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7497 sparc_flat_save_restore (FILE *file, const char *base_reg, int offset,
7498 unsigned long gmask, unsigned long fmask,
7499 const char *word_op, const char *doubleword_op,
7500 HOST_WIDE_INT base_offset)
7504 if (gmask == 0 && fmask == 0)
7507 /* Save registers starting from high to low. We've already saved the
7508 previous frame pointer and previous return address for the debugger's
7509 sake. The debugger allows us to not need a nop in the epilog if at least
7510 one register is reloaded in addition to return address. */
7514 for (regno = 1; regno <= 31; regno++)
7516 if ((gmask & (1L << regno)) != 0)
7518 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7520 /* We can save two registers in a row. If we're not at a
7521 double word boundary, move to one.
7522 sparc_flat_compute_frame_size ensures there's room to do
7524 if (offset % 8 != 0)
7525 offset += UNITS_PER_WORD;
7527 if (word_op[0] == 's')
7529 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7530 doubleword_op, reg_names[regno],
7532 if (dwarf2out_do_frame ())
7534 char *l = dwarf2out_cfi_label ();
7535 dwarf2out_reg_save (l, regno, offset + base_offset);
7537 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7541 fprintf (file, "\t%s\t[%s+%d], %s\n",
7542 doubleword_op, base_reg, offset,
7545 offset += 2 * UNITS_PER_WORD;
7550 if (word_op[0] == 's')
7552 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7553 word_op, reg_names[regno],
7555 if (dwarf2out_do_frame ())
7556 dwarf2out_reg_save ("", regno, offset + base_offset);
7559 fprintf (file, "\t%s\t[%s+%d], %s\n",
7560 word_op, base_reg, offset, reg_names[regno]);
7562 offset += UNITS_PER_WORD;
7570 for (regno = 32; regno <= 63; regno++)
7572 if ((fmask & (1L << (regno - 32))) != 0)
7574 if (word_op[0] == 's')
7576 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7577 word_op, reg_names[regno],
7579 if (dwarf2out_do_frame ())
7580 dwarf2out_reg_save ("", regno, offset + base_offset);
7583 fprintf (file, "\t%s\t[%s+%d], %s\n",
7584 word_op, base_reg, offset, reg_names[regno]);
7586 offset += UNITS_PER_WORD;
7592 /* Set up the stack and frame (if desired) for the function. */
7595 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7597 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7598 unsigned long gmask = current_frame_info.gmask;
7600 sparc_output_scratch_registers (file);
7602 /* This is only for the human reader. */
7603 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7604 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", "
7605 "regs= %d/%d, args= %d, extra= %d\n",
7607 current_frame_info.var_size,
7608 current_frame_info.gp_reg_size / 4,
7609 current_frame_info.fp_reg_size / 4,
7610 current_function_outgoing_args_size,
7611 current_frame_info.extra_size);
7613 size = SPARC_STACK_ALIGN (size);
7614 size = (! current_frame_info.initialized
7615 ? sparc_flat_compute_frame_size (size)
7616 : current_frame_info.total_size);
7618 /* These cases shouldn't happen. Catch them now. */
7619 if (size == 0 && (gmask || current_frame_info.fmask))
7622 /* Allocate our stack frame by decrementing %sp.
7623 At present, the only algorithm gdb can use to determine if this is a
7624 flat frame is if we always set %i7 if we set %sp. This can be optimized
7625 in the future by putting in some sort of debugging information that says
7626 this is a `flat' function. However, there is still the case of debugging
7627 code without such debugging information (including cases where most fns
7628 have such info, but there is one that doesn't). So, always do this now
7629 so we don't get a lot of code out there that gdb can't handle.
7630 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7631 distinguish us from a non-flat function but there won't (and shouldn't)
7632 be any differences anyway. The return pc is saved (if necessary) right
7633 after %i7 so gdb won't have to look too far to find it. */
7636 int reg_offset = current_frame_info.reg_offset;
7637 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7638 static const char *const t1_str = "%g1";
7640 /* Things get a little tricky if local variables take up more than ~4096
7641 bytes and outgoing arguments take up more than ~4096 bytes. When that
7642 happens, the register save area can't be accessed from either end of
7643 the frame. Handle this by decrementing %sp to the start of the gp
7644 register save area, save the regs, update %i7, and then set %sp to its
7645 final value. Given that we only have one scratch register to play
7646 with it is the cheapest solution, and it helps gdb out as it won't
7647 slow down recognition of flat functions.
7648 Don't change the order of insns emitted here without checking with
7649 the gdb folk first. */
7651 /* Is the entire register save area offsettable from %sp? */
7652 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7656 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7657 sp_str, size, sp_str);
7658 if (gmask & HARD_FRAME_POINTER_MASK)
7660 fprintf (file, "\tst\t%s, [%s+%d]\n",
7661 fp_str, sp_str, reg_offset);
7662 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7663 "\t%s# set up frame pointer\n",
7664 sp_str, size, fp_str, ASM_COMMENT_START);
7670 build_big_number (file, size, t1_str);
7671 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7672 if (gmask & HARD_FRAME_POINTER_MASK)
7674 fprintf (file, "\tst\t%s, [%s+%d]\n",
7675 fp_str, sp_str, reg_offset);
7676 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7677 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7681 if (dwarf2out_do_frame ())
7683 char *l = dwarf2out_cfi_label ();
7684 if (gmask & HARD_FRAME_POINTER_MASK)
7686 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7687 reg_offset - 4 - size);
7688 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7691 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7693 if (gmask & RETURN_ADDR_MASK)
7695 fprintf (file, "\tst\t%s, [%s+%d]\n",
7696 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7697 if (dwarf2out_do_frame ())
7698 dwarf2out_return_save ("", reg_offset - size);
7701 sparc_flat_save_restore (file, sp_str, reg_offset,
7702 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7703 current_frame_info.fmask,
7704 "st", "std", -size);
7708 /* Subtract %sp in two steps, but make sure there is always a
7709 64-byte register save area, and %sp is properly aligned. */
7711 /* Amount to decrement %sp by, the first time. */
7712 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7714 /* Amount to decrement %sp by, the second time. */
7715 HOST_WIDE_INT size2 = size - size1;
7717 /* Offset to register save area from %sp after first decrement. */
7718 int offset = (int)(size1 - (size - reg_offset));
7722 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7723 sp_str, size1, sp_str);
7724 if (gmask & HARD_FRAME_POINTER_MASK)
7726 fprintf (file, "\tst\t%s, [%s+%d]\n"
7727 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7728 "\t%s# set up frame pointer\n",
7729 fp_str, sp_str, offset, sp_str, size1,
7730 fp_str, ASM_COMMENT_START);
7736 build_big_number (file, size1, t1_str);
7737 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7738 if (gmask & HARD_FRAME_POINTER_MASK)
7740 fprintf (file, "\tst\t%s, [%s+%d]\n"
7741 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7742 fp_str, sp_str, offset, sp_str, t1_str,
7743 fp_str, ASM_COMMENT_START);
7747 if (dwarf2out_do_frame ())
7749 char *l = dwarf2out_cfi_label ();
7750 if (gmask & HARD_FRAME_POINTER_MASK)
7752 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7753 offset - 4 - size1);
7754 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7757 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7759 if (gmask & RETURN_ADDR_MASK)
7761 fprintf (file, "\tst\t%s, [%s+%d]\n",
7762 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
7763 if (dwarf2out_do_frame ())
7764 /* offset - size1 == reg_offset - size
7765 if reg_offset were updated above like offset. */
7766 dwarf2out_return_save ("", offset - size1);
7769 sparc_flat_save_restore (file, sp_str, offset,
7770 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7771 current_frame_info.fmask,
7772 "st", "std", -size1);
7774 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7775 sp_str, size2, sp_str);
7778 build_big_number (file, size2, t1_str);
7779 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7781 if (dwarf2out_do_frame ())
7782 if (! (gmask & HARD_FRAME_POINTER_MASK))
7783 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7787 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7790 /* Do any necessary cleanup after a function to restore stack, frame,
7794 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7796 rtx epilogue_delay = current_function_epilogue_delay_list;
7797 int noepilogue = FALSE;
7799 /* This is only for the human reader. */
7800 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7802 /* The epilogue does not depend on any registers, but the stack
7803 registers, so we assume that if we have 1 pending nop, it can be
7804 ignored, and 2 it must be filled (2 nops occur for integer
7805 multiply and divide). */
7807 size = SPARC_STACK_ALIGN (size);
7808 size = (!current_frame_info.initialized
7809 ? sparc_flat_compute_frame_size (size)
7810 : current_frame_info.total_size);
7812 if (size == 0 && epilogue_delay == 0)
7814 rtx insn = get_last_insn ();
7816 /* If the last insn was a BARRIER, we don't have to write any code
7817 because a jump (aka return) was put there. */
7818 if (GET_CODE (insn) == NOTE)
7819 insn = prev_nonnote_insn (insn);
7820 if (insn && GET_CODE (insn) == BARRIER)
7826 int reg_offset = current_frame_info.reg_offset;
7828 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7829 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7830 static const char *const t1_str = "%g1";
7832 /* In the reload sequence, we don't need to fill the load delay
7833 slots for most of the loads, also see if we can fill the final
7834 delay slot if not otherwise filled by the reload sequence. */
7837 build_big_number (file, size, t1_str);
7839 if (frame_pointer_needed)
7842 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7843 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7845 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7846 "\t\t%s# sp not trusted here\n",
7847 fp_str, size, sp_str, ASM_COMMENT_START);
7850 /* Is the entire register save area offsettable from %sp? */
7851 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7857 /* Restore %sp in two steps, but make sure there is always a
7858 64-byte register save area, and %sp is properly aligned. */
7860 /* Amount to increment %sp by, the first time. */
7861 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16;
7863 /* Offset to register save area from %sp. */
7864 reg_offset = reg_offset1 - reg_offset;
7866 if (reg_offset1 > 4096)
7868 build_big_number (file, reg_offset1, t1_str);
7869 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7872 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str);
7875 /* We must restore the frame pointer and return address reg first
7876 because they are treated specially by the prologue output code. */
7877 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7879 fprintf (file, "\tld\t[%s+%d], %s\n",
7880 sp_str, reg_offset, fp_str);
7883 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7885 fprintf (file, "\tld\t[%s+%d], %s\n",
7886 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7890 /* Restore any remaining saved registers. */
7891 sparc_flat_save_restore (file, sp_str, reg_offset,
7892 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7893 current_frame_info.fmask,
7896 /* If we had to increment %sp in two steps, record it so the second
7897 restoration in the epilogue finishes up. */
7898 if (reg_offset1 > 0)
7900 size -= reg_offset1;
7902 build_big_number (file, size, t1_str);
7905 if (current_function_returns_struct)
7906 fprintf (file, "\tjmp\t%%o7+12\n");
7908 fprintf (file, "\tretl\n");
7910 /* If the only register saved is the return address, we need a
7911 nop, unless we have an instruction to put into it. Otherwise
7912 we don't since reloading multiple registers doesn't reference
7913 the register being loaded. */
7919 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7922 else if (size > 4096)
7923 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7926 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7927 sp_str, size, sp_str);
7930 fprintf (file, "\tnop\n");
7933 /* Reset state info for each function. */
7934 current_frame_info = zero_frame_info;
7936 sparc_output_deferred_case_vectors ();
7939 /* Define the number of delay slots needed for the function epilogue.
7941 On the sparc, we need a slot if either no stack has been allocated,
7942 or the only register saved is the return register. */
7945 sparc_flat_epilogue_delay_slots (void)
7947 if (!current_frame_info.initialized)
7948 (void) sparc_flat_compute_frame_size (get_frame_size ());
7950 if (current_frame_info.total_size == 0)
7956 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7957 Any single length instruction which doesn't reference the stack or frame
7961 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
7963 rtx pat = PATTERN (trial);
7965 if (get_attr_length (trial) != 1)
7968 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7969 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7975 /* Adjust the cost of a scheduling dependency. Return the new cost of
7976 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7979 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7981 enum attr_type insn_type;
7983 if (! recog_memoized (insn))
7986 insn_type = get_attr_type (insn);
7988 if (REG_NOTE_KIND (link) == 0)
7990 /* Data dependency; DEP_INSN writes a register that INSN reads some
7993 /* if a load, then the dependence must be on the memory address;
7994 add an extra "cycle". Note that the cost could be two cycles
7995 if the reg was written late in an instruction group; we ca not tell
7997 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8000 /* Get the delay only if the address of the store is the dependence. */
8001 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8003 rtx pat = PATTERN(insn);
8004 rtx dep_pat = PATTERN (dep_insn);
8006 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8007 return cost; /* This should not happen! */
8009 /* The dependency between the two instructions was on the data that
8010 is being stored. Assume that this implies that the address of the
8011 store is not dependent. */
8012 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8015 return cost + 3; /* An approximation. */
8018 /* A shift instruction cannot receive its data from an instruction
8019 in the same cycle; add a one cycle penalty. */
8020 if (insn_type == TYPE_SHIFT)
8021 return cost + 3; /* Split before cascade into shift. */
8025 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8026 INSN writes some cycles later. */
8028 /* These are only significant for the fpu unit; writing a fp reg before
8029 the fpu has finished with it stalls the processor. */
8031 /* Reusing an integer register causes no problems. */
8032 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8040 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8042 enum attr_type insn_type, dep_type;
8043 rtx pat = PATTERN(insn);
8044 rtx dep_pat = PATTERN (dep_insn);
8046 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8049 insn_type = get_attr_type (insn);
8050 dep_type = get_attr_type (dep_insn);
8052 switch (REG_NOTE_KIND (link))
8055 /* Data dependency; DEP_INSN writes a register that INSN reads some
8062 /* Get the delay iff the address of the store is the dependence. */
8063 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8066 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8073 /* If a load, then the dependence must be on the memory address. If
8074 the addresses aren't equal, then it might be a false dependency */
8075 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8077 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8078 || GET_CODE (SET_DEST (dep_pat)) != MEM
8079 || GET_CODE (SET_SRC (pat)) != MEM
8080 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8081 XEXP (SET_SRC (pat), 0)))
8089 /* Compare to branch latency is 0. There is no benefit from
8090 separating compare and branch. */
8091 if (dep_type == TYPE_COMPARE)
8093 /* Floating point compare to branch latency is less than
8094 compare to conditional move. */
8095 if (dep_type == TYPE_FPCMP)
8104 /* Anti-dependencies only penalize the fpu unit. */
8105 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8117 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8121 case PROCESSOR_SUPERSPARC:
8122 cost = supersparc_adjust_cost (insn, link, dep, cost);
8124 case PROCESSOR_HYPERSPARC:
8125 case PROCESSOR_SPARCLITE86X:
8126 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8135 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8136 int sched_verbose ATTRIBUTE_UNUSED,
8137 int max_ready ATTRIBUTE_UNUSED)
8142 sparc_use_dfa_pipeline_interface (void)
8144 if ((1 << sparc_cpu) &
8145 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8146 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8147 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8148 (1 << PROCESSOR_ULTRASPARC3)))
8154 sparc_use_sched_lookahead (void)
8156 if (sparc_cpu == PROCESSOR_ULTRASPARC
8157 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8159 if ((1 << sparc_cpu) &
8160 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8161 (1 << PROCESSOR_SPARCLITE86X)))
8167 sparc_issue_rate (void)
8174 /* Assume V9 processors are capable of at least dual-issue. */
8176 case PROCESSOR_SUPERSPARC:
8178 case PROCESSOR_HYPERSPARC:
8179 case PROCESSOR_SPARCLITE86X:
8181 case PROCESSOR_ULTRASPARC:
8182 case PROCESSOR_ULTRASPARC3:
8188 set_extends (rtx insn)
8190 register rtx pat = PATTERN (insn);
8192 switch (GET_CODE (SET_SRC (pat)))
8194 /* Load and some shift instructions zero extend. */
8197 /* sethi clears the high bits */
8199 /* LO_SUM is used with sethi. sethi cleared the high
8200 bits and the values used with lo_sum are positive */
8202 /* Store flag stores 0 or 1 */
8212 rtx op0 = XEXP (SET_SRC (pat), 0);
8213 rtx op1 = XEXP (SET_SRC (pat), 1);
8214 if (GET_CODE (op1) == CONST_INT)
8215 return INTVAL (op1) >= 0;
8216 if (GET_CODE (op0) != REG)
8218 if (sparc_check_64 (op0, insn) == 1)
8220 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8225 rtx op0 = XEXP (SET_SRC (pat), 0);
8226 rtx op1 = XEXP (SET_SRC (pat), 1);
8227 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8229 if (GET_CODE (op1) == CONST_INT)
8230 return INTVAL (op1) >= 0;
8231 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8234 return GET_MODE (SET_SRC (pat)) == SImode;
8235 /* Positive integers leave the high bits zero. */
8237 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8239 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8242 return - (GET_MODE (SET_SRC (pat)) == SImode);
8244 return sparc_check_64 (SET_SRC (pat), insn);
8250 /* We _ought_ to have only one kind per function, but... */
8251 static GTY(()) rtx sparc_addr_diff_list;
8252 static GTY(()) rtx sparc_addr_list;
8255 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8257 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8259 sparc_addr_diff_list
8260 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8262 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8266 sparc_output_addr_vec (rtx vec)
8268 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8269 int idx, vlen = XVECLEN (body, 0);
8271 #ifdef ASM_OUTPUT_ADDR_VEC_START
8272 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8275 #ifdef ASM_OUTPUT_CASE_LABEL
8276 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8279 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8282 for (idx = 0; idx < vlen; idx++)
8284 ASM_OUTPUT_ADDR_VEC_ELT
8285 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8288 #ifdef ASM_OUTPUT_ADDR_VEC_END
8289 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8294 sparc_output_addr_diff_vec (rtx vec)
8296 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8297 rtx base = XEXP (XEXP (body, 0), 0);
8298 int idx, vlen = XVECLEN (body, 1);
8300 #ifdef ASM_OUTPUT_ADDR_VEC_START
8301 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8304 #ifdef ASM_OUTPUT_CASE_LABEL
8305 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8308 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8311 for (idx = 0; idx < vlen; idx++)
8313 ASM_OUTPUT_ADDR_DIFF_ELT
8316 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8317 CODE_LABEL_NUMBER (base));
8320 #ifdef ASM_OUTPUT_ADDR_VEC_END
8321 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8326 sparc_output_deferred_case_vectors (void)
8331 if (sparc_addr_list == NULL_RTX
8332 && sparc_addr_diff_list == NULL_RTX)
8335 /* Align to cache line in the function's code section. */
8336 function_section (current_function_decl);
8338 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8340 ASM_OUTPUT_ALIGN (asm_out_file, align);
8342 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8343 sparc_output_addr_vec (XEXP (t, 0));
8344 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8345 sparc_output_addr_diff_vec (XEXP (t, 0));
8347 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8350 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8351 unknown. Return 1 if the high bits are zero, -1 if the register is
8354 sparc_check_64 (rtx x, rtx insn)
8356 /* If a register is set only once it is safe to ignore insns this
8357 code does not know how to handle. The loop will either recognize
8358 the single set and return the correct value or fail to recognize
8363 if (GET_CODE (x) != REG)
8366 if (GET_MODE (x) == DImode)
8367 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8369 if (flag_expensive_optimizations
8370 && REG_N_SETS (REGNO (y)) == 1)
8376 insn = get_last_insn_anywhere ();
8381 while ((insn = PREV_INSN (insn)))
8383 switch (GET_CODE (insn))
8396 rtx pat = PATTERN (insn);
8397 if (GET_CODE (pat) != SET)
8399 if (rtx_equal_p (x, SET_DEST (pat)))
8400 return set_extends (insn);
8401 if (y && rtx_equal_p (y, SET_DEST (pat)))
8402 return set_extends (insn);
8403 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8411 /* Returns assembly code to perform a DImode shift using
8412 a 64-bit global or out register on SPARC-V8+. */
8414 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8416 static char asm_code[60];
8418 /* The scratch register is only required when the destination
8419 register is not a 64-bit global or out register. */
8420 if (which_alternative != 2)
8421 operands[3] = operands[0];
8423 /* We can only shift by constants <= 63. */
8424 if (GET_CODE (operands[2]) == CONST_INT)
8425 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8427 if (GET_CODE (operands[1]) == CONST_INT)
8429 output_asm_insn ("mov\t%1, %3", operands);
8433 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8434 if (sparc_check_64 (operands[1], insn) <= 0)
8435 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8436 output_asm_insn ("or\t%L1, %3, %3", operands);
8439 strcpy(asm_code, opcode);
8441 if (which_alternative != 2)
8442 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8444 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8447 /* Output rtl to increment the profiler label LABELNO
8448 for profiling a function entry. */
8451 sparc_profile_hook (int labelno)
8456 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8457 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8458 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8460 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8463 #ifdef OBJECT_FORMAT_ELF
8465 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8467 if (flags & SECTION_MERGE)
8469 /* entsize cannot be expressed in this section attributes
8471 default_elf_asm_named_section (name, flags);
8475 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8477 if (!(flags & SECTION_DEBUG))
8478 fputs (",#alloc", asm_out_file);
8479 if (flags & SECTION_WRITE)
8480 fputs (",#write", asm_out_file);
8481 if (flags & SECTION_CODE)
8482 fputs (",#execinstr", asm_out_file);
8484 /* ??? Handle SECTION_BSS. */
8486 fputc ('\n', asm_out_file);
8488 #endif /* OBJECT_FORMAT_ELF */
8490 /* We do not allow sibling calls if -mflat, nor
8491 we do not allow indirect calls to be optimized into sibling calls.
8493 Also, on sparc 32-bit we cannot emit a sibling call when the
8494 current function returns a structure. This is because the "unimp
8495 after call" convention would cause the callee to return to the
8496 wrong place. The generic code already disallows cases where the
8497 function being called returns a structure.
8499 It may seem strange how this last case could occur. Usually there
8500 is code after the call which jumps to epilogue code which dumps the
8501 return value into the struct return area. That ought to invalidate
8502 the sibling call right? Well, in the c++ case we can end up passing
8503 the pointer to the struct return area to a constructor (which returns
8504 void) and then nothing else happens. Such a sibling call would look
8505 valid without the added check here. */
8507 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8511 && (TARGET_ARCH64 || ! current_function_returns_struct));
8514 /* libfunc renaming. */
8515 #include "config/gofast.h"
8518 sparc_init_libfuncs (void)
8522 /* Use the subroutines that Sun's library provides for integer
8523 multiply and divide. The `*' prevents an underscore from
8524 being prepended by the compiler. .umul is a little faster
8526 set_optab_libfunc (smul_optab, SImode, "*.umul");
8527 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8528 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8529 set_optab_libfunc (smod_optab, SImode, "*.rem");
8530 set_optab_libfunc (umod_optab, SImode, "*.urem");
8532 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8533 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8534 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8535 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8536 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8537 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8539 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8540 is because with soft-float, the SFmode and DFmode sqrt
8541 instructions will be absent, and the compiler will notice and
8542 try to use the TFmode sqrt instruction for calls to the
8543 builtin function sqrt, but this fails. */
8545 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8547 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8548 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8549 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8550 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8551 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8552 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8554 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8555 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8556 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8557 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8559 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8560 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8561 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8563 if (SUN_CONVERSION_LIBFUNCS)
8565 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8566 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8567 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8568 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8573 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8574 do not exist in the library. Make sure the compiler does not
8575 emit calls to them by accident. (It should always use the
8576 hardware instructions.) */
8577 set_optab_libfunc (smul_optab, SImode, 0);
8578 set_optab_libfunc (sdiv_optab, SImode, 0);
8579 set_optab_libfunc (udiv_optab, SImode, 0);
8580 set_optab_libfunc (smod_optab, SImode, 0);
8581 set_optab_libfunc (umod_optab, SImode, 0);
8583 if (SUN_INTEGER_MULTIPLY_64)
8585 set_optab_libfunc (smul_optab, DImode, "__mul64");
8586 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8587 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8588 set_optab_libfunc (smod_optab, DImode, "__rem64");
8589 set_optab_libfunc (umod_optab, DImode, "__urem64");
8592 if (SUN_CONVERSION_LIBFUNCS)
8594 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8595 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8596 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8597 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8601 gofast_maybe_init_libfuncs ();
8604 /* ??? Similar to the standard section selection, but force reloc-y-ness
8605 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8606 pretending PIC always on), but that's what the old code did. */
8609 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8611 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8614 /* Use text section for a constant unless we need more alignment than
8618 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8619 unsigned HOST_WIDE_INT align)
8621 if (align <= MAX_TEXT_ALIGN
8622 && ! (flag_pic && (symbolic_operand (x, mode)
8623 || SUNOS4_SHARED_LIBRARIES)))
8624 readonly_data_section ();
8630 sparc_extra_constraint_check (rtx op, int c, int strict)
8635 && (c == 'T' || c == 'U'))
8641 return fp_sethi_p (op);
8644 return fp_mov_p (op);
8647 return fp_high_losum_p (op);
8651 || (GET_CODE (op) == REG
8652 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8653 || reg_renumber[REGNO (op)] >= 0)))
8654 return register_ok_for_ldd (op);
8666 /* Our memory extra constraints have to emulate the
8667 behavior of 'm' and 'o' in order for reload to work
8669 if (GET_CODE (op) == MEM)
8672 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8674 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8679 reload_ok_mem = (reload_in_progress
8680 && GET_CODE (op) == REG
8681 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8682 && reg_renumber [REGNO (op)] < 0);
8685 return reload_ok_mem;
8688 /* ??? This duplicates information provided to the compiler by the
8689 ??? scheduler description. Some day, teach genautomata to output
8690 ??? the latencies and then CSE will just use that. */
8693 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8697 case PLUS: case MINUS: case ABS: case NEG:
8698 case FLOAT: case UNSIGNED_FLOAT:
8699 case FIX: case UNSIGNED_FIX:
8700 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8701 if (FLOAT_MODE_P (GET_MODE (x)))
8705 case PROCESSOR_ULTRASPARC:
8706 case PROCESSOR_ULTRASPARC3:
8707 *total = COSTS_N_INSNS (4);
8710 case PROCESSOR_SUPERSPARC:
8711 *total = COSTS_N_INSNS (3);
8714 case PROCESSOR_CYPRESS:
8715 *total = COSTS_N_INSNS (5);
8718 case PROCESSOR_HYPERSPARC:
8719 case PROCESSOR_SPARCLITE86X:
8721 *total = COSTS_N_INSNS (1);
8726 *total = COSTS_N_INSNS (1);
8732 case PROCESSOR_ULTRASPARC:
8733 if (GET_MODE (x) == SFmode)
8734 *total = COSTS_N_INSNS (13);
8736 *total = COSTS_N_INSNS (23);
8739 case PROCESSOR_ULTRASPARC3:
8740 if (GET_MODE (x) == SFmode)
8741 *total = COSTS_N_INSNS (20);
8743 *total = COSTS_N_INSNS (29);
8746 case PROCESSOR_SUPERSPARC:
8747 *total = COSTS_N_INSNS (12);
8750 case PROCESSOR_CYPRESS:
8751 *total = COSTS_N_INSNS (63);
8754 case PROCESSOR_HYPERSPARC:
8755 case PROCESSOR_SPARCLITE86X:
8756 *total = COSTS_N_INSNS (17);
8760 *total = COSTS_N_INSNS (30);
8765 if (FLOAT_MODE_P (GET_MODE (x)))
8769 case PROCESSOR_ULTRASPARC:
8770 case PROCESSOR_ULTRASPARC3:
8771 *total = COSTS_N_INSNS (1);
8774 case PROCESSOR_SUPERSPARC:
8775 *total = COSTS_N_INSNS (3);
8778 case PROCESSOR_CYPRESS:
8779 *total = COSTS_N_INSNS (5);
8782 case PROCESSOR_HYPERSPARC:
8783 case PROCESSOR_SPARCLITE86X:
8785 *total = COSTS_N_INSNS (1);
8790 /* ??? Maybe mark integer compares as zero cost on
8791 ??? all UltraSPARC processors because the result
8792 ??? can be bypassed to a branch in the same group. */
8794 *total = COSTS_N_INSNS (1);
8798 if (FLOAT_MODE_P (GET_MODE (x)))
8802 case PROCESSOR_ULTRASPARC:
8803 case PROCESSOR_ULTRASPARC3:
8804 *total = COSTS_N_INSNS (4);
8807 case PROCESSOR_SUPERSPARC:
8808 *total = COSTS_N_INSNS (3);
8811 case PROCESSOR_CYPRESS:
8812 *total = COSTS_N_INSNS (7);
8815 case PROCESSOR_HYPERSPARC:
8816 case PROCESSOR_SPARCLITE86X:
8817 *total = COSTS_N_INSNS (1);
8821 *total = COSTS_N_INSNS (5);
8826 /* The latency is actually variable for Ultra-I/II
8827 And if one of the inputs have a known constant
8828 value, we could calculate this precisely.
8830 However, for that to be useful we would need to
8831 add some machine description changes which would
8832 make sure small constants ended up in rs1 of the
8833 multiply instruction. This is because the multiply
8834 latency is determined by the number of clear (or
8835 set if the value is negative) bits starting from
8836 the most significant bit of the first input.
8838 The algorithm for computing num_cycles of a multiply
8842 highest_bit = highest_clear_bit(rs1);
8844 highest_bit = highest_set_bit(rs1);
8847 num_cycles = 4 + ((highest_bit - 3) / 2);
8849 If we did that we would have to also consider register
8850 allocation issues that would result from forcing such
8851 a value into a register.
8853 There are other similar tricks we could play if we
8854 knew, for example, that one input was an array index.
8856 Since we do not play any such tricks currently the
8857 safest thing to do is report the worst case latency. */
8858 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8860 *total = (GET_MODE (x) == DImode
8861 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8865 /* Multiply latency on Ultra-III, fortunately, is constant. */
8866 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8868 *total = COSTS_N_INSNS (6);
8872 if (sparc_cpu == PROCESSOR_HYPERSPARC
8873 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8875 *total = COSTS_N_INSNS (17);
8879 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8886 if (FLOAT_MODE_P (GET_MODE (x)))
8890 case PROCESSOR_ULTRASPARC:
8891 if (GET_MODE (x) == SFmode)
8892 *total = COSTS_N_INSNS (13);
8894 *total = COSTS_N_INSNS (23);
8897 case PROCESSOR_ULTRASPARC3:
8898 if (GET_MODE (x) == SFmode)
8899 *total = COSTS_N_INSNS (17);
8901 *total = COSTS_N_INSNS (20);
8904 case PROCESSOR_SUPERSPARC:
8905 if (GET_MODE (x) == SFmode)
8906 *total = COSTS_N_INSNS (6);
8908 *total = COSTS_N_INSNS (9);
8911 case PROCESSOR_HYPERSPARC:
8912 case PROCESSOR_SPARCLITE86X:
8913 if (GET_MODE (x) == SFmode)
8914 *total = COSTS_N_INSNS (8);
8916 *total = COSTS_N_INSNS (12);
8920 *total = COSTS_N_INSNS (7);
8925 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8926 *total = (GET_MODE (x) == DImode
8927 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8928 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8929 *total = (GET_MODE (x) == DImode
8930 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8932 *total = COSTS_N_INSNS (25);
8936 /* Conditional moves. */
8939 case PROCESSOR_ULTRASPARC:
8940 *total = COSTS_N_INSNS (2);
8943 case PROCESSOR_ULTRASPARC3:
8944 if (FLOAT_MODE_P (GET_MODE (x)))
8945 *total = COSTS_N_INSNS (3);
8947 *total = COSTS_N_INSNS (2);
8951 *total = COSTS_N_INSNS (1);
8956 /* If outer-code is SIGN/ZERO extension we have to subtract
8957 out COSTS_N_INSNS (1) from whatever we return in determining
8961 case PROCESSOR_ULTRASPARC:
8962 if (outer_code == ZERO_EXTEND)
8963 *total = COSTS_N_INSNS (1);
8965 *total = COSTS_N_INSNS (2);
8968 case PROCESSOR_ULTRASPARC3:
8969 if (outer_code == ZERO_EXTEND)
8971 if (GET_MODE (x) == QImode
8972 || GET_MODE (x) == HImode
8973 || outer_code == SIGN_EXTEND)
8974 *total = COSTS_N_INSNS (2);
8976 *total = COSTS_N_INSNS (1);
8980 /* This handles sign extension (3 cycles)
8981 and everything else (2 cycles). */
8982 *total = COSTS_N_INSNS (2);
8986 case PROCESSOR_SUPERSPARC:
8987 if (FLOAT_MODE_P (GET_MODE (x))
8988 || outer_code == ZERO_EXTEND
8989 || outer_code == SIGN_EXTEND)
8990 *total = COSTS_N_INSNS (0);
8992 *total = COSTS_N_INSNS (1);
8995 case PROCESSOR_TSC701:
8996 if (outer_code == ZERO_EXTEND
8997 || outer_code == SIGN_EXTEND)
8998 *total = COSTS_N_INSNS (2);
9000 *total = COSTS_N_INSNS (3);
9003 case PROCESSOR_CYPRESS:
9004 if (outer_code == ZERO_EXTEND
9005 || outer_code == SIGN_EXTEND)
9006 *total = COSTS_N_INSNS (1);
9008 *total = COSTS_N_INSNS (2);
9011 case PROCESSOR_HYPERSPARC:
9012 case PROCESSOR_SPARCLITE86X:
9014 if (outer_code == ZERO_EXTEND
9015 || outer_code == SIGN_EXTEND)
9016 *total = COSTS_N_INSNS (0);
9018 *total = COSTS_N_INSNS (1);
9023 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9041 if (GET_MODE (x) == DImode
9042 && ((XINT (x, 3) == 0
9043 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
9044 || (XINT (x, 3) == -1
9046 && XINT (x, 2) >= -0x1000)))
9057 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
9058 Used for C++ multiple inheritance. */
9061 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9062 HOST_WIDE_INT delta,
9063 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
9066 rtx this, insn, funexp, delta_rtx, tmp;
9068 reload_completed = 1;
9069 epilogue_completed = 1;
9071 current_function_uses_only_leaf_regs = 1;
9073 emit_note (NOTE_INSN_PROLOGUE_END);
9075 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9076 returns a structure, the structure return pointer is there instead. */
9077 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9078 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
9080 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
9082 /* Add DELTA. When possible use a plain add, otherwise load it into
9083 a register first. */
9084 delta_rtx = GEN_INT (delta);
9085 if (!SPARC_SIMM13_P (delta))
9087 rtx scratch = gen_rtx_REG (Pmode, 1);
9089 if (input_operand (delta_rtx, GET_MODE (scratch)))
9090 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
9094 sparc_emit_set_const64 (scratch, delta_rtx);
9096 sparc_emit_set_const32 (scratch, delta_rtx);
9099 delta_rtx = scratch;
9102 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
9103 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
9105 /* Generate a tail call to the target function. */
9106 if (! TREE_USED (function))
9108 assemble_external (function);
9109 TREE_USED (function) = 1;
9111 funexp = XEXP (DECL_RTL (function), 0);
9112 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9113 insn = emit_call_insn (gen_sibcall (funexp));
9114 SIBLING_CALL_P (insn) = 1;
9117 /* Run just enough of rest_of_compilation to get the insns emitted.
9118 There's not really enough bulk here to make other passes such as
9119 instruction scheduling worth while. Note that use_thunk calls
9120 assemble_start_function and assemble_end_function. */
9121 insn = get_insns ();
9122 insn_locators_initialize ();
9123 shorten_branches (insn);
9124 final_start_function (insn, file, 1);
9125 final (insn, file, 1, 0);
9126 final_end_function ();
9128 reload_completed = 0;
9129 epilogue_completed = 0;
9133 /* How to allocate a 'struct machine_function'. */
9135 static struct machine_function *
9136 sparc_init_machine_status (void)
9138 return ggc_alloc_cleared (sizeof (struct machine_function));
9141 /* Locate some local-dynamic symbol still in use by this function
9142 so that we can print its name in local-dynamic base patterns. */
9145 get_some_local_dynamic_name (void)
9149 if (cfun->machine->some_ld_name)
9150 return cfun->machine->some_ld_name;
9152 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9154 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9155 return cfun->machine->some_ld_name;
9161 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9166 && GET_CODE (x) == SYMBOL_REF
9167 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9169 cfun->machine->some_ld_name = XSTR (x, 0);
9176 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9177 We need to emit DTP-relative relocations. */
9180 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9185 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9188 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9193 output_addr_const (file, x);
9197 #include "gt-sparc.h"