1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static int apparent_fsize;
71 static int actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static int frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, int);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, int, const char *);
140 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
141 tree, int, int, int *, int *);
143 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
144 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
146 static void sparc_output_addr_vec (rtx);
147 static void sparc_output_addr_diff_vec (rtx);
148 static void sparc_output_deferred_case_vectors (void);
149 static int check_return_regs (rtx);
150 static int epilogue_renumber (rtx *, int);
151 static bool sparc_assemble_integer (rtx, unsigned int, int);
152 static int set_extends (rtx);
153 static void output_restore_regs (FILE *, int);
154 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
155 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
156 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
158 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
159 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
160 #ifdef OBJECT_FORMAT_ELF
161 static void sparc_elf_asm_named_section (const char *, unsigned int);
163 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
165 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
166 unsigned HOST_WIDE_INT)
169 static int sparc_adjust_cost (rtx, rtx, rtx, int);
170 static int sparc_issue_rate (void);
171 static void sparc_sched_init (FILE *, int, int);
172 static int sparc_use_dfa_pipeline_interface (void);
173 static int sparc_use_sched_lookahead (void);
175 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
176 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
177 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
178 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
179 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
181 static bool sparc_function_ok_for_sibcall (tree, tree);
182 static void sparc_init_libfuncs (void);
183 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
184 HOST_WIDE_INT, tree);
185 static struct machine_function * sparc_init_machine_status (void);
186 static bool sparc_cannot_force_const_mem (rtx);
187 static rtx sparc_tls_get_addr (void);
188 static rtx sparc_tls_got (void);
189 static const char *get_some_local_dynamic_name (void);
190 static int get_some_local_dynamic_name_1 (rtx *, void *);
191 static bool sparc_rtx_costs (rtx, int, int, int *);
193 /* Option handling. */
195 /* Code model option as passed by user. */
196 const char *sparc_cmodel_string;
198 enum cmodel sparc_cmodel;
200 char sparc_hard_reg_printed[8];
202 struct sparc_cpu_select sparc_select[] =
204 /* switch name, tune arch */
205 { (char *)0, "default", 1, 1 },
206 { (char *)0, "-mcpu=", 1, 1 },
207 { (char *)0, "-mtune=", 1, 0 },
211 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
212 enum processor_type sparc_cpu;
214 /* Initialize the GCC target structure. */
216 /* The sparc default is to use .half rather than .short for aligned
217 HI objects. Use .word instead of .long on non-ELF systems. */
218 #undef TARGET_ASM_ALIGNED_HI_OP
219 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
220 #ifndef OBJECT_FORMAT_ELF
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
225 #undef TARGET_ASM_UNALIGNED_HI_OP
226 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
227 #undef TARGET_ASM_UNALIGNED_SI_OP
228 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
229 #undef TARGET_ASM_UNALIGNED_DI_OP
230 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
232 /* The target hook has to handle DI-mode values. */
233 #undef TARGET_ASM_INTEGER
234 #define TARGET_ASM_INTEGER sparc_assemble_integer
236 #undef TARGET_ASM_FUNCTION_PROLOGUE
237 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
238 #undef TARGET_ASM_FUNCTION_EPILOGUE
239 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
243 #undef TARGET_SCHED_ISSUE_RATE
244 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
245 #undef TARGET_SCHED_INIT
246 #define TARGET_SCHED_INIT sparc_sched_init
247 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
248 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
249 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
250 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
252 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
253 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
255 #undef TARGET_INIT_LIBFUNCS
256 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
259 #undef TARGET_HAVE_TLS
260 #define TARGET_HAVE_TLS true
262 #undef TARGET_CANNOT_FORCE_CONST_MEM
263 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
265 #undef TARGET_ASM_OUTPUT_MI_THUNK
266 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
267 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
268 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS sparc_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST hook_int_rtx_0
275 struct gcc_target targetm = TARGET_INITIALIZER;
277 /* Validate and override various options, and do some machine dependent
281 sparc_override_options (void)
283 static struct code_model {
284 const char *const name;
286 } const cmodels[] = {
288 { "medlow", CM_MEDLOW },
289 { "medmid", CM_MEDMID },
290 { "medany", CM_MEDANY },
291 { "embmedany", CM_EMBMEDANY },
294 const struct code_model *cmodel;
295 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
296 static struct cpu_default {
298 const char *const name;
299 } const cpu_default[] = {
300 /* There must be one entry here for each TARGET_CPU value. */
301 { TARGET_CPU_sparc, "cypress" },
302 { TARGET_CPU_sparclet, "tsc701" },
303 { TARGET_CPU_sparclite, "f930" },
304 { TARGET_CPU_v8, "v8" },
305 { TARGET_CPU_hypersparc, "hypersparc" },
306 { TARGET_CPU_sparclite86x, "sparclite86x" },
307 { TARGET_CPU_supersparc, "supersparc" },
308 { TARGET_CPU_v9, "v9" },
309 { TARGET_CPU_ultrasparc, "ultrasparc" },
310 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
313 const struct cpu_default *def;
314 /* Table of values for -m{cpu,tune}=. */
315 static struct cpu_table {
316 const char *const name;
317 const enum processor_type processor;
320 } const cpu_table[] = {
321 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
322 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
323 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
324 /* TI TMS390Z55 supersparc */
325 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
326 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
327 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
328 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
329 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
330 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
331 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
332 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
334 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
336 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
337 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
338 /* TI ultrasparc I, II, IIi */
339 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
340 /* Although insns using %y are deprecated, it is a clear win on current
342 |MASK_DEPRECATED_V8_INSNS},
343 /* TI ultrasparc III */
344 /* ??? Check if %y issue still holds true in ultra3. */
345 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
348 const struct cpu_table *cpu;
349 const struct sparc_cpu_select *sel;
352 #ifndef SPARC_BI_ARCH
353 /* Check for unsupported architecture size. */
354 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
355 error ("%s is not supported by this configuration",
356 DEFAULT_ARCH32_P ? "-m64" : "-m32");
359 /* We force all 64bit archs to use 128 bit long double */
360 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
362 error ("-mlong-double-64 not allowed with -m64");
363 target_flags |= MASK_LONG_DOUBLE_128;
366 /* Code model selection. */
367 sparc_cmodel = SPARC_DEFAULT_CMODEL;
371 sparc_cmodel = CM_32;
374 if (sparc_cmodel_string != NULL)
378 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
379 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
381 if (cmodel->name == NULL)
382 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
384 sparc_cmodel = cmodel->value;
387 error ("-mcmodel= is not supported on 32 bit systems");
390 fpu = TARGET_FPU; /* save current -mfpu status */
392 /* Set the default CPU. */
393 for (def = &cpu_default[0]; def->name; ++def)
394 if (def->cpu == TARGET_CPU_DEFAULT)
398 sparc_select[0].string = def->name;
400 for (sel = &sparc_select[0]; sel->name; ++sel)
404 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
405 if (! strcmp (sel->string, cpu->name))
408 sparc_cpu = cpu->processor;
412 target_flags &= ~cpu->disable;
413 target_flags |= cpu->enable;
419 error ("bad value (%s) for %s switch", sel->string, sel->name);
423 /* If -mfpu or -mno-fpu was explicitly used, don't override with
424 the processor default. Clear MASK_FPU_SET to avoid confusing
425 the reverse mapping from switch values to names. */
428 target_flags = (target_flags & ~MASK_FPU) | fpu;
429 target_flags &= ~MASK_FPU_SET;
432 /* Don't allow -mvis if FPU is disabled. */
434 target_flags &= ~MASK_VIS;
436 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
438 -m64 also implies v9. */
439 if (TARGET_VIS || TARGET_ARCH64)
441 target_flags |= MASK_V9;
442 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
445 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
446 if (TARGET_V9 && TARGET_ARCH32)
447 target_flags |= MASK_DEPRECATED_V8_INSNS;
449 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
450 if (! TARGET_V9 || TARGET_ARCH64)
451 target_flags &= ~MASK_V8PLUS;
453 /* Don't use stack biasing in 32 bit mode. */
455 target_flags &= ~MASK_STACK_BIAS;
457 /* Supply a default value for align_functions. */
458 if (align_functions == 0
459 && (sparc_cpu == PROCESSOR_ULTRASPARC
460 || sparc_cpu == PROCESSOR_ULTRASPARC3))
461 align_functions = 32;
463 /* Validate PCC_STRUCT_RETURN. */
464 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
465 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
467 /* Only use .uaxword when compiling for a 64-bit target. */
469 targetm.asm_out.unaligned_op.di = NULL;
471 /* Do various machine dependent initializations. */
474 /* Set up function hooks. */
475 init_machine_status = sparc_init_machine_status;
478 /* Miscellaneous utilities. */
480 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
481 or branch on register contents instructions. */
484 v9_regcmp_p (enum rtx_code code)
486 return (code == EQ || code == NE || code == GE || code == LT
487 || code == LE || code == GT);
491 /* Operand constraints. */
493 /* Return nonzero only if OP is a register of mode MODE,
497 reg_or_0_operand (rtx op, enum machine_mode mode)
499 if (register_operand (op, mode))
501 if (op == const0_rtx)
503 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
504 && CONST_DOUBLE_HIGH (op) == 0
505 && CONST_DOUBLE_LOW (op) == 0)
507 if (fp_zero_operand (op, mode))
512 /* Return nonzero only if OP is const1_rtx. */
515 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
517 return op == const1_rtx;
520 /* Nonzero if OP is a floating point value with value 0.0. */
523 fp_zero_operand (rtx op, enum machine_mode mode)
525 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
527 return op == CONST0_RTX (mode);
530 /* Nonzero if OP is a register operand in floating point register. */
533 fp_register_operand (rtx op, enum machine_mode mode)
535 if (! register_operand (op, mode))
537 if (GET_CODE (op) == SUBREG)
538 op = SUBREG_REG (op);
539 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
542 /* Nonzero if OP is a floating point constant which can
543 be loaded into an integer register using a single
544 sethi instruction. */
549 if (GET_CODE (op) == CONST_DOUBLE)
554 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
555 if (REAL_VALUES_EQUAL (r, dconst0) &&
556 ! REAL_VALUE_MINUS_ZERO (r))
558 REAL_VALUE_TO_TARGET_SINGLE (r, i);
559 if (SPARC_SETHI_P (i))
566 /* Nonzero if OP is a floating point constant which can
567 be loaded into an integer register using a single
573 if (GET_CODE (op) == CONST_DOUBLE)
578 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
579 if (REAL_VALUES_EQUAL (r, dconst0) &&
580 ! REAL_VALUE_MINUS_ZERO (r))
582 REAL_VALUE_TO_TARGET_SINGLE (r, i);
583 if (SPARC_SIMM13_P (i))
590 /* Nonzero if OP is a floating point constant which can
591 be loaded into an integer register using a high/losum
592 instruction sequence. */
595 fp_high_losum_p (rtx op)
597 /* The constraints calling this should only be in
598 SFmode move insns, so any constant which cannot
599 be moved using a single insn will do. */
600 if (GET_CODE (op) == CONST_DOUBLE)
605 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
606 if (REAL_VALUES_EQUAL (r, dconst0) &&
607 ! REAL_VALUE_MINUS_ZERO (r))
609 REAL_VALUE_TO_TARGET_SINGLE (r, i);
610 if (! SPARC_SETHI_P (i)
611 && ! SPARC_SIMM13_P (i))
618 /* Nonzero if OP is an integer register. */
621 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
623 return (register_operand (op, SImode)
624 || (TARGET_ARCH64 && register_operand (op, DImode)));
627 /* Nonzero if OP is a floating point condition code register. */
630 fcc_reg_operand (rtx op, enum machine_mode mode)
632 /* This can happen when recog is called from combine. Op may be a MEM.
633 Fail instead of calling abort in this case. */
634 if (GET_CODE (op) != REG)
637 if (mode != VOIDmode && mode != GET_MODE (op))
640 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
643 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
644 if (reg_renumber == 0)
645 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
646 return REGNO_OK_FOR_CCFP_P (REGNO (op));
648 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
652 /* Nonzero if OP is a floating point condition code fcc0 register. */
655 fcc0_reg_operand (rtx op, enum machine_mode mode)
657 /* This can happen when recog is called from combine. Op may be a MEM.
658 Fail instead of calling abort in this case. */
659 if (GET_CODE (op) != REG)
662 if (mode != VOIDmode && mode != GET_MODE (op))
665 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
668 return REGNO (op) == SPARC_FCC_REG;
671 /* Nonzero if OP is an integer or floating point condition code register. */
674 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
676 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
678 if (mode != VOIDmode && mode != GET_MODE (op))
681 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
686 return fcc_reg_operand (op, mode);
689 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
691 restore_operand (rtx op, enum machine_mode mode)
693 return (GET_CODE (op) == REG && GET_MODE (op) == mode
694 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
697 /* Call insn on SPARC can take a PC-relative constant address, or any regular
701 call_operand (rtx op, enum machine_mode mode)
703 if (GET_CODE (op) != MEM)
706 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
710 call_operand_address (rtx op, enum machine_mode mode)
712 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
715 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
716 otherwise return 0. */
719 tls_symbolic_operand (rtx op)
721 if (GET_CODE (op) != SYMBOL_REF)
723 return SYMBOL_REF_TLS_MODEL (op);
727 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
729 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
733 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
735 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
739 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
741 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
745 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
747 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
750 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
751 reference and a constant. */
754 symbolic_operand (register rtx op, enum machine_mode mode)
756 enum machine_mode omode = GET_MODE (op);
758 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
761 switch (GET_CODE (op))
764 return !SYMBOL_REF_TLS_MODEL (op);
771 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
772 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
773 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
774 && GET_CODE (XEXP (op, 1)) == CONST_INT);
781 /* Return truth value of statement that OP is a symbolic memory
782 operand of mode MODE. */
785 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
787 if (GET_CODE (op) == SUBREG)
788 op = SUBREG_REG (op);
789 if (GET_CODE (op) != MEM)
792 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
793 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
794 || GET_CODE (op) == LABEL_REF);
797 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
800 label_ref_operand (rtx op, enum machine_mode mode)
802 if (GET_CODE (op) != LABEL_REF)
804 if (GET_MODE (op) != mode)
809 /* Return 1 if the operand is an argument used in generating pic references
810 in either the medium/low or medium/anywhere code models of sparc64. */
813 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
815 /* Check for (const (minus (symbol_ref:GOT)
816 (const (minus (label) (pc))))). */
817 if (GET_CODE (op) != CONST)
820 if (GET_CODE (op) != MINUS)
822 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
824 /* ??? Ensure symbol is GOT. */
825 if (GET_CODE (XEXP (op, 1)) != CONST)
827 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
832 /* Return 1 if the operand is a data segment reference. This includes
833 the readonly data segment, or in other words anything but the text segment.
834 This is needed in the medium/anywhere code model on v9. These values
835 are accessed with EMBMEDANY_BASE_REG. */
838 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
840 switch (GET_CODE (op))
843 return ! SYMBOL_REF_FUNCTION_P (op);
845 /* Assume canonical format of symbol + constant.
848 return data_segment_operand (XEXP (op, 0), VOIDmode);
854 /* Return 1 if the operand is a text segment reference.
855 This is needed in the medium/anywhere code model on v9. */
858 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
860 switch (GET_CODE (op))
865 return SYMBOL_REF_FUNCTION_P (op);
867 /* Assume canonical format of symbol + constant.
870 return text_segment_operand (XEXP (op, 0), VOIDmode);
876 /* Return 1 if the operand is either a register or a memory operand that is
880 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
882 if (register_operand (op, mode))
885 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
892 splittable_symbolic_memory_operand (rtx op,
893 enum machine_mode mode ATTRIBUTE_UNUSED)
895 if (GET_CODE (op) != MEM)
897 if (! symbolic_operand (XEXP (op, 0), Pmode))
903 splittable_immediate_memory_operand (rtx op,
904 enum machine_mode mode ATTRIBUTE_UNUSED)
906 if (GET_CODE (op) != MEM)
908 if (! immediate_operand (XEXP (op, 0), Pmode))
913 /* Return truth value of whether OP is EQ or NE. */
916 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
918 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
921 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
922 or LTU for non-floating-point. We handle those specially. */
925 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
927 enum rtx_code code = GET_CODE (op);
929 if (GET_RTX_CLASS (code) != '<')
932 if (GET_MODE (XEXP (op, 0)) == CCFPmode
933 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
936 return (code != NE && code != EQ && code != GEU && code != LTU);
939 /* Return 1 if this is a comparison operator. This allows the use of
940 MATCH_OPERATOR to recognize all the branch insns. */
943 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
945 enum rtx_code code = GET_CODE (op);
947 if (GET_RTX_CLASS (code) != '<')
950 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
951 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
952 /* These are the only branches which work with CC_NOOVmode. */
953 return (code == EQ || code == NE || code == GE || code == LT);
957 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
958 MATCH_OPERATOR to recognize all the branch insns. */
961 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
963 enum rtx_code code = GET_CODE (op);
968 if (GET_RTX_CLASS (code) != '<')
971 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
972 /* These are the only branches which work with CCX_NOOVmode. */
973 return (code == EQ || code == NE || code == GE || code == LT);
974 return (GET_MODE (XEXP (op, 0)) == CCXmode);
977 /* Nonzero if OP is a comparison operator suitable for use in v9
978 conditional move or branch on register contents instructions. */
981 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
983 enum rtx_code code = GET_CODE (op);
985 if (GET_RTX_CLASS (code) != '<')
988 return v9_regcmp_p (code);
991 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
994 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
996 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
999 /* Return nonzero if OP is an operator of mode MODE which can set
1000 the condition codes explicitly. We do not include PLUS and MINUS
1001 because these require CC_NOOVmode, which we handle explicitly. */
1004 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1006 if (GET_CODE (op) == AND
1007 || GET_CODE (op) == IOR
1008 || GET_CODE (op) == XOR)
1014 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1015 complement its second operand and set the condition codes explicitly. */
1018 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1020 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1021 and (xor ... (not ...)) to (not (xor ...)). */
1022 return (GET_CODE (op) == AND
1023 || GET_CODE (op) == IOR);
1026 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1027 signed 13 bit immediate field. This is an acceptable SImode operand for
1028 most 3 address instructions. */
1031 arith_operand (rtx op, enum machine_mode mode)
1033 if (register_operand (op, mode))
1035 if (GET_CODE (op) != CONST_INT)
1037 return SMALL_INT32 (op);
1040 /* Return true if OP is a constant 4096 */
1043 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1045 if (GET_CODE (op) != CONST_INT)
1048 return INTVAL (op) == 4096;
1051 /* Return true if OP is suitable as second operand for add/sub */
1054 arith_add_operand (rtx op, enum machine_mode mode)
1056 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1059 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1060 immediate field of OR and XOR instructions. Used for 64-bit
1061 constant formation patterns. */
1063 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1065 return ((GET_CODE (op) == CONST_INT
1066 && SPARC_SIMM13_P (INTVAL (op)))
1067 #if HOST_BITS_PER_WIDE_INT != 64
1068 || (GET_CODE (op) == CONST_DOUBLE
1069 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1070 && (CONST_DOUBLE_HIGH (op) ==
1071 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1072 (HOST_WIDE_INT)-1 : 0)))
1077 /* The same, but only for sethi instructions. */
1079 const64_high_operand (rtx op, enum machine_mode mode)
1081 return ((GET_CODE (op) == CONST_INT
1082 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1083 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1085 || (GET_CODE (op) == CONST_DOUBLE
1086 && CONST_DOUBLE_HIGH (op) == 0
1087 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1088 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1091 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1092 signed 11 bit immediate field. This is an acceptable SImode operand for
1093 the movcc instructions. */
1096 arith11_operand (rtx op, enum machine_mode mode)
1098 return (register_operand (op, mode)
1099 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1102 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1103 signed 10 bit immediate field. This is an acceptable SImode operand for
1104 the movrcc instructions. */
1107 arith10_operand (rtx op, enum machine_mode mode)
1109 return (register_operand (op, mode)
1110 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1113 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1114 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1116 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1117 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1118 for most 3 address instructions. */
1121 arith_double_operand (rtx op, enum machine_mode mode)
1123 return (register_operand (op, mode)
1124 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1126 && GET_CODE (op) == CONST_DOUBLE
1127 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1128 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1130 && GET_CODE (op) == CONST_DOUBLE
1131 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1132 && ((CONST_DOUBLE_HIGH (op) == -1
1133 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1134 || (CONST_DOUBLE_HIGH (op) == 0
1135 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1138 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1141 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1143 return (TARGET_ARCH64 &&
1144 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1145 (GET_CODE (op) == CONST_DOUBLE &&
1146 CONST_DOUBLE_LOW (op) == 4096 &&
1147 CONST_DOUBLE_HIGH (op) == 0)));
1150 /* Return true if OP is suitable as second operand for add/sub in DImode */
1153 arith_double_add_operand (rtx op, enum machine_mode mode)
1155 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1158 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1159 can fit in an 11 bit immediate field. This is an acceptable DImode
1160 operand for the movcc instructions. */
1161 /* ??? Replace with arith11_operand? */
1164 arith11_double_operand (rtx op, enum machine_mode mode)
1166 return (register_operand (op, mode)
1167 || (GET_CODE (op) == CONST_DOUBLE
1168 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1169 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1170 && ((CONST_DOUBLE_HIGH (op) == -1
1171 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1172 || (CONST_DOUBLE_HIGH (op) == 0
1173 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1174 || (GET_CODE (op) == CONST_INT
1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1176 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1179 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1180 can fit in an 10 bit immediate field. This is an acceptable DImode
1181 operand for the movrcc instructions. */
1182 /* ??? Replace with arith10_operand? */
1185 arith10_double_operand (rtx op, enum machine_mode mode)
1187 return (register_operand (op, mode)
1188 || (GET_CODE (op) == CONST_DOUBLE
1189 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1190 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1191 && ((CONST_DOUBLE_HIGH (op) == -1
1192 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1193 || (CONST_DOUBLE_HIGH (op) == 0
1194 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1195 || (GET_CODE (op) == CONST_INT
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1200 /* Return truth value of whether OP is an integer which fits the
1201 range constraining immediate operands in most three-address insns,
1202 which have a 13 bit immediate field. */
1205 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1207 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1211 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1213 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1214 || (GET_CODE (op) == CONST_DOUBLE
1215 && CONST_DOUBLE_HIGH (op) == 0
1216 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1219 /* Recognize operand values for the umul instruction. That instruction sign
1220 extends immediate values just like all other sparc instructions, but
1221 interprets the extended result as an unsigned number. */
1224 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 #if HOST_BITS_PER_WIDE_INT > 32
1227 /* All allowed constants will fit a CONST_INT. */
1228 return (GET_CODE (op) == CONST_INT
1229 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1230 || (INTVAL (op) >= 0xFFFFF000
1231 && INTVAL (op) <= 0xFFFFFFFF)));
1233 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1234 || (GET_CODE (op) == CONST_DOUBLE
1235 && CONST_DOUBLE_HIGH (op) == 0
1236 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1241 uns_arith_operand (rtx op, enum machine_mode mode)
1243 return register_operand (op, mode) || uns_small_int (op, mode);
1246 /* Return truth value of statement that OP is a call-clobbered register. */
1248 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1250 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1253 /* Return 1 if OP is a valid operand for the source of a move insn. */
1256 input_operand (rtx op, enum machine_mode mode)
1258 /* If both modes are non-void they must be the same. */
1259 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1262 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1263 if (GET_CODE (op) == CONSTANT_P_RTX)
1266 /* Allow any one instruction integer constant, and all CONST_INT
1267 variants when we are working in DImode and !arch64. */
1268 if (GET_MODE_CLASS (mode) == MODE_INT
1269 && ((GET_CODE (op) == CONST_INT
1270 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1271 || SPARC_SIMM13_P (INTVAL (op))
1273 && ! TARGET_ARCH64)))
1275 && GET_CODE (op) == CONST_DOUBLE
1276 && ((CONST_DOUBLE_HIGH (op) == 0
1277 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1279 #if HOST_BITS_PER_WIDE_INT == 64
1280 (CONST_DOUBLE_HIGH (op) == 0
1281 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1283 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1284 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1285 && CONST_DOUBLE_HIGH (op) == 0)
1286 || (CONST_DOUBLE_HIGH (op) == -1
1287 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1292 /* If !arch64 and this is a DImode const, allow it so that
1293 the splits can be generated. */
1296 && GET_CODE (op) == CONST_DOUBLE)
1299 if (register_operand (op, mode))
1302 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1303 && GET_CODE (op) == CONST_DOUBLE)
1306 /* If this is a SUBREG, look inside so that we handle
1307 paradoxical ones. */
1308 if (GET_CODE (op) == SUBREG)
1309 op = SUBREG_REG (op);
1311 /* Check for valid MEM forms. */
1312 if (GET_CODE (op) == MEM)
1314 rtx inside = XEXP (op, 0);
1316 if (GET_CODE (inside) == LO_SUM)
1318 /* We can't allow these because all of the splits
1319 (eventually as they trickle down into DFmode
1320 splits) require offsettable memory references. */
1322 && GET_MODE (op) == TFmode)
1325 return (register_operand (XEXP (inside, 0), Pmode)
1326 && CONSTANT_P (XEXP (inside, 1)));
1328 return memory_address_p (mode, inside);
1335 /* We know it can't be done in one insn when we get here,
1336 the movsi expander guarantees this. */
1338 sparc_emit_set_const32 (rtx op0, rtx op1)
1340 enum machine_mode mode = GET_MODE (op0);
1343 if (GET_CODE (op1) == CONST_INT)
1345 HOST_WIDE_INT value = INTVAL (op1);
1347 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1348 || SPARC_SIMM13_P (value))
1352 /* Full 2-insn decomposition is needed. */
1353 if (reload_in_progress || reload_completed)
1356 temp = gen_reg_rtx (mode);
1358 if (GET_CODE (op1) == CONST_INT)
1360 /* Emit them as real moves instead of a HIGH/LO_SUM,
1361 this way CSE can see everything and reuse intermediate
1362 values if it wants. */
1364 && HOST_BITS_PER_WIDE_INT != 64
1365 && (INTVAL (op1) & 0x80000000) != 0)
1366 emit_insn (gen_rtx_SET
1368 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1371 emit_insn (gen_rtx_SET (VOIDmode, temp,
1372 GEN_INT (INTVAL (op1)
1373 & ~(HOST_WIDE_INT)0x3ff)));
1375 emit_insn (gen_rtx_SET (VOIDmode,
1377 gen_rtx_IOR (mode, temp,
1378 GEN_INT (INTVAL (op1) & 0x3ff))));
1382 /* A symbol, emit in the traditional way. */
1383 emit_insn (gen_rtx_SET (VOIDmode, temp,
1384 gen_rtx_HIGH (mode, op1)));
1385 emit_insn (gen_rtx_SET (VOIDmode,
1386 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1392 /* SPARC-v9 code-model support. */
1394 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1398 if (temp1 && GET_MODE (temp1) == TImode)
1401 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1404 switch (sparc_cmodel)
1407 /* The range spanned by all instructions in the object is less
1408 than 2^31 bytes (2GB) and the distance from any instruction
1409 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1410 than 2^31 bytes (2GB).
1412 The executable must be in the low 4TB of the virtual address
1415 sethi %hi(symbol), %temp
1416 or %temp, %lo(symbol), %reg */
1417 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1418 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1422 /* The range spanned by all instructions in the object is less
1423 than 2^31 bytes (2GB) and the distance from any instruction
1424 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1425 than 2^31 bytes (2GB).
1427 The executable must be in the low 16TB of the virtual address
1430 sethi %h44(symbol), %temp1
1431 or %temp1, %m44(symbol), %temp2
1432 sllx %temp2, 12, %temp3
1433 or %temp3, %l44(symbol), %reg */
1434 emit_insn (gen_seth44 (op0, op1));
1435 emit_insn (gen_setm44 (op0, op0, op1));
1436 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1437 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1438 emit_insn (gen_setl44 (op0, temp1, op1));
1442 /* The range spanned by all instructions in the object is less
1443 than 2^31 bytes (2GB) and the distance from any instruction
1444 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1445 than 2^31 bytes (2GB).
1447 The executable can be placed anywhere in the virtual address
1450 sethi %hh(symbol), %temp1
1451 sethi %lm(symbol), %temp2
1452 or %temp1, %hm(symbol), %temp3
1453 or %temp2, %lo(symbol), %temp4
1454 sllx %temp3, 32, %temp5
1455 or %temp4, %temp5, %reg */
1457 /* It is possible that one of the registers we got for operands[2]
1458 might coincide with that of operands[0] (which is why we made
1459 it TImode). Pick the other one to use as our scratch. */
1460 if (rtx_equal_p (temp1, op0))
1463 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1468 emit_insn (gen_sethh (op0, op1));
1469 emit_insn (gen_setlm (temp1, op1));
1470 emit_insn (gen_sethm (op0, op0, op1));
1471 emit_insn (gen_rtx_SET (VOIDmode, op0,
1472 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1473 emit_insn (gen_rtx_SET (VOIDmode, op0,
1474 gen_rtx_PLUS (DImode, op0, temp1)));
1475 emit_insn (gen_setlo (op0, op0, op1));
1479 /* Old old old backwards compatibility kruft here.
1480 Essentially it is MEDLOW with a fixed 64-bit
1481 virtual base added to all data segment addresses.
1482 Text-segment stuff is computed like MEDANY, we can't
1483 reuse the code above because the relocation knobs
1486 Data segment: sethi %hi(symbol), %temp1
1487 or %temp1, %lo(symbol), %temp2
1488 add %temp2, EMBMEDANY_BASE_REG, %reg
1490 Text segment: sethi %uhi(symbol), %temp1
1491 sethi %hi(symbol), %temp2
1492 or %temp1, %ulo(symbol), %temp3
1493 or %temp2, %lo(symbol), %temp4
1494 sllx %temp3, 32, %temp5
1495 or %temp4, %temp5, %reg */
1496 if (data_segment_operand (op1, GET_MODE (op1)))
1498 emit_insn (gen_embmedany_sethi (temp1, op1));
1499 emit_insn (gen_embmedany_brsum (op0, temp1));
1500 emit_insn (gen_embmedany_losum (op0, op0, op1));
1504 /* It is possible that one of the registers we got for operands[2]
1505 might coincide with that of operands[0] (which is why we made
1506 it TImode). Pick the other one to use as our scratch. */
1507 if (rtx_equal_p (temp1, op0))
1510 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1515 emit_insn (gen_embmedany_textuhi (op0, op1));
1516 emit_insn (gen_embmedany_texthi (temp1, op1));
1517 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1518 emit_insn (gen_rtx_SET (VOIDmode, op0,
1519 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1520 emit_insn (gen_rtx_SET (VOIDmode, op0,
1521 gen_rtx_PLUS (DImode, op0, temp1)));
1522 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1531 /* These avoid problems when cross compiling. If we do not
1532 go through all this hair then the optimizer will see
1533 invalid REG_EQUAL notes or in some cases none at all. */
1534 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1535 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1536 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1537 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1539 #if HOST_BITS_PER_WIDE_INT == 64
1540 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1541 #define GEN_INT64(__x) GEN_INT (__x)
1543 #define GEN_HIGHINT64(__x) \
1544 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1545 #define GEN_INT64(__x) \
1546 immed_double_const ((__x) & 0xffffffff, \
1547 ((__x) & 0x80000000 ? -1 : 0), DImode)
1550 /* The optimizer is not to assume anything about exactly
1551 which bits are set for a HIGH, they are unspecified.
1552 Unfortunately this leads to many missed optimizations
1553 during CSE. We mask out the non-HIGH bits, and matches
1554 a plain movdi, to alleviate this problem. */
1556 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1558 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1562 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1564 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1568 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1570 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1574 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1576 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1579 /* Worker routines for 64-bit constant formation on arch64.
1580 One of the key things to be doing in these emissions is
1581 to create as many temp REGs as possible. This makes it
1582 possible for half-built constants to be used later when
1583 such values are similar to something required later on.
1584 Without doing this, the optimizer cannot see such
1587 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1588 unsigned HOST_WIDE_INT, int);
1591 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1592 unsigned HOST_WIDE_INT low_bits, int is_neg)
1594 unsigned HOST_WIDE_INT high_bits;
1597 high_bits = (~low_bits) & 0xffffffff;
1599 high_bits = low_bits;
1601 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1604 emit_insn (gen_rtx_SET (VOIDmode, op0,
1605 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1609 /* If we are XOR'ing with -1, then we should emit a one's complement
1610 instead. This way the combiner will notice logical operations
1611 such as ANDN later on and substitute. */
1612 if ((low_bits & 0x3ff) == 0x3ff)
1614 emit_insn (gen_rtx_SET (VOIDmode, op0,
1615 gen_rtx_NOT (DImode, temp)));
1619 emit_insn (gen_rtx_SET (VOIDmode, op0,
1620 gen_safe_XOR64 (temp,
1621 (-(HOST_WIDE_INT)0x400
1622 | (low_bits & 0x3ff)))));
1627 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1628 unsigned HOST_WIDE_INT, int);
1631 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1632 unsigned HOST_WIDE_INT high_bits,
1633 unsigned HOST_WIDE_INT low_immediate,
1638 if ((high_bits & 0xfffffc00) != 0)
1640 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1641 if ((high_bits & ~0xfffffc00) != 0)
1642 emit_insn (gen_rtx_SET (VOIDmode, op0,
1643 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1649 emit_insn (gen_safe_SET64 (temp, high_bits));
1653 /* Now shift it up into place. */
1654 emit_insn (gen_rtx_SET (VOIDmode, op0,
1655 gen_rtx_ASHIFT (DImode, temp2,
1656 GEN_INT (shift_count))));
1658 /* If there is a low immediate part piece, finish up by
1659 putting that in as well. */
1660 if (low_immediate != 0)
1661 emit_insn (gen_rtx_SET (VOIDmode, op0,
1662 gen_safe_OR64 (op0, low_immediate)));
1665 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1666 unsigned HOST_WIDE_INT);
1668 /* Full 64-bit constant decomposition. Even though this is the
1669 'worst' case, we still optimize a few things away. */
1671 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1672 unsigned HOST_WIDE_INT high_bits,
1673 unsigned HOST_WIDE_INT low_bits)
1677 if (reload_in_progress || reload_completed)
1680 sub_temp = gen_reg_rtx (DImode);
1682 if ((high_bits & 0xfffffc00) != 0)
1684 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1685 if ((high_bits & ~0xfffffc00) != 0)
1686 emit_insn (gen_rtx_SET (VOIDmode,
1688 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1694 emit_insn (gen_safe_SET64 (temp, high_bits));
1698 if (!reload_in_progress && !reload_completed)
1700 rtx temp2 = gen_reg_rtx (DImode);
1701 rtx temp3 = gen_reg_rtx (DImode);
1702 rtx temp4 = gen_reg_rtx (DImode);
1704 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1705 gen_rtx_ASHIFT (DImode, sub_temp,
1708 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1709 if ((low_bits & ~0xfffffc00) != 0)
1711 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1712 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1713 emit_insn (gen_rtx_SET (VOIDmode, op0,
1714 gen_rtx_PLUS (DImode, temp4, temp3)));
1718 emit_insn (gen_rtx_SET (VOIDmode, op0,
1719 gen_rtx_PLUS (DImode, temp4, temp2)));
1724 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1725 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1726 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1729 /* We are in the middle of reload, so this is really
1730 painful. However we do still make an attempt to
1731 avoid emitting truly stupid code. */
1732 if (low1 != const0_rtx)
1734 emit_insn (gen_rtx_SET (VOIDmode, op0,
1735 gen_rtx_ASHIFT (DImode, sub_temp,
1736 GEN_INT (to_shift))));
1737 emit_insn (gen_rtx_SET (VOIDmode, op0,
1738 gen_rtx_IOR (DImode, op0, low1)));
1746 if (low2 != const0_rtx)
1748 emit_insn (gen_rtx_SET (VOIDmode, op0,
1749 gen_rtx_ASHIFT (DImode, sub_temp,
1750 GEN_INT (to_shift))));
1751 emit_insn (gen_rtx_SET (VOIDmode, op0,
1752 gen_rtx_IOR (DImode, op0, low2)));
1760 emit_insn (gen_rtx_SET (VOIDmode, op0,
1761 gen_rtx_ASHIFT (DImode, sub_temp,
1762 GEN_INT (to_shift))));
1763 if (low3 != const0_rtx)
1764 emit_insn (gen_rtx_SET (VOIDmode, op0,
1765 gen_rtx_IOR (DImode, op0, low3)));
1770 /* Analyze a 64-bit constant for certain properties. */
1771 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1772 unsigned HOST_WIDE_INT,
1773 int *, int *, int *);
1776 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1777 unsigned HOST_WIDE_INT low_bits,
1778 int *hbsp, int *lbsp, int *abbasp)
1780 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1783 lowest_bit_set = highest_bit_set = -1;
1787 if ((lowest_bit_set == -1)
1788 && ((low_bits >> i) & 1))
1790 if ((highest_bit_set == -1)
1791 && ((high_bits >> (32 - i - 1)) & 1))
1792 highest_bit_set = (64 - i - 1);
1795 && ((highest_bit_set == -1)
1796 || (lowest_bit_set == -1)));
1802 if ((lowest_bit_set == -1)
1803 && ((high_bits >> i) & 1))
1804 lowest_bit_set = i + 32;
1805 if ((highest_bit_set == -1)
1806 && ((low_bits >> (32 - i - 1)) & 1))
1807 highest_bit_set = 32 - i - 1;
1810 && ((highest_bit_set == -1)
1811 || (lowest_bit_set == -1)));
1813 /* If there are no bits set this should have gone out
1814 as one instruction! */
1815 if (lowest_bit_set == -1
1816 || highest_bit_set == -1)
1818 all_bits_between_are_set = 1;
1819 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1823 if ((low_bits & (1 << i)) != 0)
1828 if ((high_bits & (1 << (i - 32))) != 0)
1831 all_bits_between_are_set = 0;
1834 *hbsp = highest_bit_set;
1835 *lbsp = lowest_bit_set;
1836 *abbasp = all_bits_between_are_set;
1839 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1842 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1843 unsigned HOST_WIDE_INT low_bits)
1845 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1848 || high_bits == 0xffffffff)
1851 analyze_64bit_constant (high_bits, low_bits,
1852 &highest_bit_set, &lowest_bit_set,
1853 &all_bits_between_are_set);
1855 if ((highest_bit_set == 63
1856 || lowest_bit_set == 0)
1857 && all_bits_between_are_set != 0)
1860 if ((highest_bit_set - lowest_bit_set) < 21)
1866 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1867 unsigned HOST_WIDE_INT,
1870 static unsigned HOST_WIDE_INT
1871 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1872 unsigned HOST_WIDE_INT low_bits,
1873 int lowest_bit_set, int shift)
1875 HOST_WIDE_INT hi, lo;
1877 if (lowest_bit_set < 32)
1879 lo = (low_bits >> lowest_bit_set) << shift;
1880 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1885 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1892 /* Here we are sure to be arch64 and this is an integer constant
1893 being loaded into a register. Emit the most efficient
1894 insn sequence possible. Detection of all the 1-insn cases
1895 has been done already. */
1897 sparc_emit_set_const64 (rtx op0, rtx op1)
1899 unsigned HOST_WIDE_INT high_bits, low_bits;
1900 int lowest_bit_set, highest_bit_set;
1901 int all_bits_between_are_set;
1904 /* Sanity check that we know what we are working with. */
1905 if (! TARGET_ARCH64)
1908 if (GET_CODE (op0) != SUBREG)
1910 if (GET_CODE (op0) != REG
1911 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1912 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1916 if (reload_in_progress || reload_completed)
1919 temp = gen_reg_rtx (DImode);
1921 if (GET_CODE (op1) != CONST_DOUBLE
1922 && GET_CODE (op1) != CONST_INT)
1924 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1928 if (GET_CODE (op1) == CONST_DOUBLE)
1930 #if HOST_BITS_PER_WIDE_INT == 64
1931 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1932 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1934 high_bits = CONST_DOUBLE_HIGH (op1);
1935 low_bits = CONST_DOUBLE_LOW (op1);
1940 #if HOST_BITS_PER_WIDE_INT == 64
1941 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1942 low_bits = (INTVAL (op1) & 0xffffffff);
1944 high_bits = ((INTVAL (op1) < 0) ?
1947 low_bits = INTVAL (op1);
1951 /* low_bits bits 0 --> 31
1952 high_bits bits 32 --> 63 */
1954 analyze_64bit_constant (high_bits, low_bits,
1955 &highest_bit_set, &lowest_bit_set,
1956 &all_bits_between_are_set);
1958 /* First try for a 2-insn sequence. */
1960 /* These situations are preferred because the optimizer can
1961 * do more things with them:
1963 * sllx %reg, shift, %reg
1965 * srlx %reg, shift, %reg
1966 * 3) mov some_small_const, %reg
1967 * sllx %reg, shift, %reg
1969 if (((highest_bit_set == 63
1970 || lowest_bit_set == 0)
1971 && all_bits_between_are_set != 0)
1972 || ((highest_bit_set - lowest_bit_set) < 12))
1974 HOST_WIDE_INT the_const = -1;
1975 int shift = lowest_bit_set;
1977 if ((highest_bit_set != 63
1978 && lowest_bit_set != 0)
1979 || all_bits_between_are_set == 0)
1982 create_simple_focus_bits (high_bits, low_bits,
1985 else if (lowest_bit_set == 0)
1986 shift = -(63 - highest_bit_set);
1988 if (! SPARC_SIMM13_P (the_const))
1991 emit_insn (gen_safe_SET64 (temp, the_const));
1993 emit_insn (gen_rtx_SET (VOIDmode,
1995 gen_rtx_ASHIFT (DImode,
1999 emit_insn (gen_rtx_SET (VOIDmode,
2001 gen_rtx_LSHIFTRT (DImode,
2003 GEN_INT (-shift))));
2009 /* Now a range of 22 or less bits set somewhere.
2010 * 1) sethi %hi(focus_bits), %reg
2011 * sllx %reg, shift, %reg
2012 * 2) sethi %hi(focus_bits), %reg
2013 * srlx %reg, shift, %reg
2015 if ((highest_bit_set - lowest_bit_set) < 21)
2017 unsigned HOST_WIDE_INT focus_bits =
2018 create_simple_focus_bits (high_bits, low_bits,
2019 lowest_bit_set, 10);
2021 if (! SPARC_SETHI_P (focus_bits))
2024 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2026 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2027 if (lowest_bit_set < 10)
2028 emit_insn (gen_rtx_SET (VOIDmode,
2030 gen_rtx_LSHIFTRT (DImode, temp,
2031 GEN_INT (10 - lowest_bit_set))));
2032 else if (lowest_bit_set > 10)
2033 emit_insn (gen_rtx_SET (VOIDmode,
2035 gen_rtx_ASHIFT (DImode, temp,
2036 GEN_INT (lowest_bit_set - 10))));
2042 /* 1) sethi %hi(low_bits), %reg
2043 * or %reg, %lo(low_bits), %reg
2044 * 2) sethi %hi(~low_bits), %reg
2045 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2048 || high_bits == 0xffffffff)
2050 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2051 (high_bits == 0xffffffff));
2055 /* Now, try 3-insn sequences. */
2057 /* 1) sethi %hi(high_bits), %reg
2058 * or %reg, %lo(high_bits), %reg
2059 * sllx %reg, 32, %reg
2063 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2067 /* We may be able to do something quick
2068 when the constant is negated, so try that. */
2069 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2070 (~low_bits) & 0xfffffc00))
2072 /* NOTE: The trailing bits get XOR'd so we need the
2073 non-negated bits, not the negated ones. */
2074 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2076 if ((((~high_bits) & 0xffffffff) == 0
2077 && ((~low_bits) & 0x80000000) == 0)
2078 || (((~high_bits) & 0xffffffff) == 0xffffffff
2079 && ((~low_bits) & 0x80000000) != 0))
2081 int fast_int = (~low_bits & 0xffffffff);
2083 if ((SPARC_SETHI_P (fast_int)
2084 && (~high_bits & 0xffffffff) == 0)
2085 || SPARC_SIMM13_P (fast_int))
2086 emit_insn (gen_safe_SET64 (temp, fast_int));
2088 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2093 #if HOST_BITS_PER_WIDE_INT == 64
2094 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2095 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2097 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2098 (~high_bits) & 0xffffffff,
2101 sparc_emit_set_const64 (temp, negated_const);
2104 /* If we are XOR'ing with -1, then we should emit a one's complement
2105 instead. This way the combiner will notice logical operations
2106 such as ANDN later on and substitute. */
2107 if (trailing_bits == 0x3ff)
2109 emit_insn (gen_rtx_SET (VOIDmode, op0,
2110 gen_rtx_NOT (DImode, temp)));
2114 emit_insn (gen_rtx_SET (VOIDmode,
2116 gen_safe_XOR64 (temp,
2117 (-0x400 | trailing_bits))));
2122 /* 1) sethi %hi(xxx), %reg
2123 * or %reg, %lo(xxx), %reg
2124 * sllx %reg, yyy, %reg
2126 * ??? This is just a generalized version of the low_bits==0
2127 * thing above, FIXME...
2129 if ((highest_bit_set - lowest_bit_set) < 32)
2131 unsigned HOST_WIDE_INT focus_bits =
2132 create_simple_focus_bits (high_bits, low_bits,
2135 /* We can't get here in this state. */
2136 if (highest_bit_set < 32
2137 || lowest_bit_set >= 32)
2140 /* So what we know is that the set bits straddle the
2141 middle of the 64-bit word. */
2142 sparc_emit_set_const64_quick2 (op0, temp,
2148 /* 1) sethi %hi(high_bits), %reg
2149 * or %reg, %lo(high_bits), %reg
2150 * sllx %reg, 32, %reg
2151 * or %reg, low_bits, %reg
2153 if (SPARC_SIMM13_P(low_bits)
2154 && ((int)low_bits > 0))
2156 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2160 /* The easiest way when all else fails, is full decomposition. */
2162 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2163 high_bits, low_bits, ~high_bits, ~low_bits);
2165 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2168 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2169 return the mode to be used for the comparison. For floating-point,
2170 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2171 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2172 processing is needed. */
2175 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2177 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2203 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2204 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2206 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2207 return CCX_NOOVmode;
2213 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2220 /* X and Y are two things to compare using CODE. Emit the compare insn and
2221 return the rtx for the cc reg in the proper mode. */
2224 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2226 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2229 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2230 fcc regs (cse can't tell they're really call clobbered regs and will
2231 remove a duplicate comparison even if there is an intervening function
2232 call - it will then try to reload the cc reg via an int reg which is why
2233 we need the movcc patterns). It is possible to provide the movcc
2234 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2235 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2236 to tell cse that CCFPE mode registers (even pseudos) are call
2239 /* ??? This is an experiment. Rather than making changes to cse which may
2240 or may not be easy/clean, we do our own cse. This is possible because
2241 we will generate hard registers. Cse knows they're call clobbered (it
2242 doesn't know the same thing about pseudos). If we guess wrong, no big
2243 deal, but if we win, great! */
2245 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2246 #if 1 /* experiment */
2249 /* We cycle through the registers to ensure they're all exercised. */
2250 static int next_fcc_reg = 0;
2251 /* Previous x,y for each fcc reg. */
2252 static rtx prev_args[4][2];
2254 /* Scan prev_args for x,y. */
2255 for (reg = 0; reg < 4; reg++)
2256 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2261 prev_args[reg][0] = x;
2262 prev_args[reg][1] = y;
2263 next_fcc_reg = (next_fcc_reg + 1) & 3;
2265 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2268 cc_reg = gen_reg_rtx (mode);
2269 #endif /* ! experiment */
2270 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2271 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2273 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2275 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2276 gen_rtx_COMPARE (mode, x, y)));
2281 /* This function is used for v9 only.
2282 CODE is the code for an Scc's comparison.
2283 OPERANDS[0] is the target of the Scc insn.
2284 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2285 been generated yet).
2287 This function is needed to turn
2290 (gt (reg:CCX 100 %icc)
2294 (gt:DI (reg:CCX 100 %icc)
2297 IE: The instruction recognizer needs to see the mode of the comparison to
2298 find the right instruction. We could use "gt:DI" right in the
2299 define_expand, but leaving it out allows us to handle DI, SI, etc.
2301 We refer to the global sparc compare operands sparc_compare_op0 and
2302 sparc_compare_op1. */
2305 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2310 && (GET_MODE (sparc_compare_op0) == DImode
2311 || GET_MODE (operands[0]) == DImode))
2314 op0 = sparc_compare_op0;
2315 op1 = sparc_compare_op1;
2317 /* Try to use the movrCC insns. */
2319 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2320 && op1 == const0_rtx
2321 && v9_regcmp_p (compare_code))
2323 /* Special case for op0 != 0. This can be done with one instruction if
2324 operands[0] == sparc_compare_op0. */
2326 if (compare_code == NE
2327 && GET_MODE (operands[0]) == DImode
2328 && rtx_equal_p (op0, operands[0]))
2330 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2331 gen_rtx_IF_THEN_ELSE (DImode,
2332 gen_rtx_fmt_ee (compare_code, DImode,
2339 if (reg_overlap_mentioned_p (operands[0], op0))
2341 /* Handle the case where operands[0] == sparc_compare_op0.
2342 We "early clobber" the result. */
2343 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2344 emit_move_insn (op0, sparc_compare_op0);
2347 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2348 if (GET_MODE (op0) != DImode)
2350 temp = gen_reg_rtx (DImode);
2351 convert_move (temp, op0, 0);
2355 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2356 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2357 gen_rtx_fmt_ee (compare_code, DImode,
2365 operands[1] = gen_compare_reg (compare_code, op0, op1);
2367 switch (GET_MODE (operands[1]))
2377 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2378 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2379 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2380 gen_rtx_fmt_ee (compare_code,
2381 GET_MODE (operands[1]),
2382 operands[1], const0_rtx),
2383 const1_rtx, operands[0])));
2388 /* Emit a conditional jump insn for the v9 architecture using comparison code
2389 CODE and jump target LABEL.
2390 This function exists to take advantage of the v9 brxx insns. */
2393 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2395 emit_jump_insn (gen_rtx_SET (VOIDmode,
2397 gen_rtx_IF_THEN_ELSE (VOIDmode,
2398 gen_rtx_fmt_ee (code, GET_MODE (op0),
2400 gen_rtx_LABEL_REF (VOIDmode, label),
2404 /* Generate a DFmode part of a hard TFmode register.
2405 REG is the TFmode hard register, LOW is 1 for the
2406 low 64bit of the register and 0 otherwise.
2409 gen_df_reg (rtx reg, int low)
2411 int regno = REGNO (reg);
2413 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2414 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2415 return gen_rtx_REG (DFmode, regno);
2418 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2419 Unlike normal calls, TFmode operands are passed by reference. It is
2420 assumed that no more than 3 operands are required. */
2423 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2425 rtx ret_slot = NULL, arg[3], func_sym;
2428 /* We only expect to be called for conversions, unary, and binary ops. */
2429 if (nargs < 2 || nargs > 3)
2432 for (i = 0; i < nargs; ++i)
2434 rtx this_arg = operands[i];
2437 /* TFmode arguments and return values are passed by reference. */
2438 if (GET_MODE (this_arg) == TFmode)
2440 int force_stack_temp;
2442 force_stack_temp = 0;
2443 if (TARGET_BUGGY_QP_LIB && i == 0)
2444 force_stack_temp = 1;
2446 if (GET_CODE (this_arg) == MEM
2447 && ! force_stack_temp)
2448 this_arg = XEXP (this_arg, 0);
2449 else if (CONSTANT_P (this_arg)
2450 && ! force_stack_temp)
2452 this_slot = force_const_mem (TFmode, this_arg);
2453 this_arg = XEXP (this_slot, 0);
2457 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2459 /* Operand 0 is the return value. We'll copy it out later. */
2461 emit_move_insn (this_slot, this_arg);
2463 ret_slot = this_slot;
2465 this_arg = XEXP (this_slot, 0);
2472 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2474 if (GET_MODE (operands[0]) == TFmode)
2477 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2478 arg[0], GET_MODE (arg[0]),
2479 arg[1], GET_MODE (arg[1]));
2481 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2482 arg[0], GET_MODE (arg[0]),
2483 arg[1], GET_MODE (arg[1]),
2484 arg[2], GET_MODE (arg[2]));
2487 emit_move_insn (operands[0], ret_slot);
2496 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2497 GET_MODE (operands[0]), 1,
2498 arg[1], GET_MODE (arg[1]));
2500 if (ret != operands[0])
2501 emit_move_insn (operands[0], ret);
2505 /* Expand soft-float TFmode calls to sparc abi routines. */
2508 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2530 emit_soft_tfmode_libcall (func, 3, operands);
2534 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2547 emit_soft_tfmode_libcall (func, 2, operands);
2551 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2558 switch (GET_MODE (operands[1]))
2571 case FLOAT_TRUNCATE:
2572 switch (GET_MODE (operands[0]))
2586 switch (GET_MODE (operands[1]))
2599 case UNSIGNED_FLOAT:
2600 switch (GET_MODE (operands[1]))
2614 switch (GET_MODE (operands[0]))
2628 switch (GET_MODE (operands[0]))
2645 emit_soft_tfmode_libcall (func, 2, operands);
2648 /* Expand a hard-float tfmode operation. All arguments must be in
2652 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2656 if (GET_RTX_CLASS (code) == '1')
2658 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2659 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2663 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2664 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2665 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2666 operands[1], operands[2]);
2669 if (register_operand (operands[0], VOIDmode))
2672 dest = gen_reg_rtx (GET_MODE (operands[0]));
2674 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2676 if (dest != operands[0])
2677 emit_move_insn (operands[0], dest);
2681 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2683 if (TARGET_HARD_QUAD)
2684 emit_hard_tfmode_operation (code, operands);
2686 emit_soft_tfmode_binop (code, operands);
2690 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2692 if (TARGET_HARD_QUAD)
2693 emit_hard_tfmode_operation (code, operands);
2695 emit_soft_tfmode_unop (code, operands);
2699 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2701 if (TARGET_HARD_QUAD)
2702 emit_hard_tfmode_operation (code, operands);
2704 emit_soft_tfmode_cvt (code, operands);
2707 /* Return nonzero if a return peephole merging return with
2708 setting of output register is ok. */
2710 leaf_return_peephole_ok (void)
2712 return (actual_fsize == 0);
2715 /* Return nonzero if a branch/jump/call instruction will be emitting
2716 nop into its delay slot. */
2719 empty_delay_slot (rtx insn)
2723 /* If no previous instruction (should not happen), return true. */
2724 if (PREV_INSN (insn) == NULL)
2727 seq = NEXT_INSN (PREV_INSN (insn));
2728 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2734 /* Return nonzero if TRIAL can go into the function epilogue's
2735 delay slot. SLOT is the slot we are trying to fill. */
2738 eligible_for_epilogue_delay (rtx trial, int slot)
2745 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2748 if (get_attr_length (trial) != 1)
2751 /* If there are any call-saved registers, we should scan TRIAL if it
2752 does not reference them. For now just make it easy. */
2756 /* If the function uses __builtin_eh_return, the eh_return machinery
2757 occupies the delay slot. */
2758 if (current_function_calls_eh_return)
2761 /* In the case of a true leaf function, anything can go into the delay slot.
2762 A delay slot only exists however if the frame size is zero, otherwise
2763 we will put an insn to adjust the stack after the return. */
2764 if (current_function_uses_only_leaf_regs)
2766 if (leaf_return_peephole_ok ())
2767 return ((get_attr_in_uncond_branch_delay (trial)
2768 == IN_BRANCH_DELAY_TRUE));
2772 pat = PATTERN (trial);
2774 /* Otherwise, only operations which can be done in tandem with
2775 a `restore' or `return' insn can go into the delay slot. */
2776 if (GET_CODE (SET_DEST (pat)) != REG
2777 || REGNO (SET_DEST (pat)) < 24)
2780 /* If this instruction sets up floating point register and we have a return
2781 instruction, it can probably go in. But restore will not work
2783 if (REGNO (SET_DEST (pat)) >= 32)
2785 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2786 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2791 /* The set of insns matched here must agree precisely with the set of
2792 patterns paired with a RETURN in sparc.md. */
2794 src = SET_SRC (pat);
2796 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2797 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2798 && arith_operand (src, GET_MODE (src)))
2801 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2803 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2806 /* This matches "*return_di". */
2807 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2808 && arith_double_operand (src, GET_MODE (src)))
2809 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2811 /* This matches "*return_sf_no_fpu". */
2812 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2813 && register_operand (src, SFmode))
2816 /* If we have return instruction, anything that does not use
2817 local or output registers and can go into a delay slot wins. */
2818 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2819 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2822 /* This matches "*return_addsi". */
2823 else if (GET_CODE (src) == PLUS
2824 && arith_operand (XEXP (src, 0), SImode)
2825 && arith_operand (XEXP (src, 1), SImode)
2826 && (register_operand (XEXP (src, 0), SImode)
2827 || register_operand (XEXP (src, 1), SImode)))
2830 /* This matches "*return_adddi". */
2831 else if (GET_CODE (src) == PLUS
2832 && arith_double_operand (XEXP (src, 0), DImode)
2833 && arith_double_operand (XEXP (src, 1), DImode)
2834 && (register_operand (XEXP (src, 0), DImode)
2835 || register_operand (XEXP (src, 1), DImode)))
2838 /* This can match "*return_losum_[sd]i".
2839 Catch only some cases, so that return_losum* don't have
2841 else if (GET_CODE (src) == LO_SUM
2842 && ! TARGET_CM_MEDMID
2843 && ((register_operand (XEXP (src, 0), SImode)
2844 && immediate_operand (XEXP (src, 1), SImode))
2846 && register_operand (XEXP (src, 0), DImode)
2847 && immediate_operand (XEXP (src, 1), DImode))))
2850 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2851 else if (GET_CODE (src) == ASHIFT
2852 && (register_operand (XEXP (src, 0), SImode)
2853 || register_operand (XEXP (src, 0), DImode))
2854 && XEXP (src, 1) == const1_rtx)
2860 /* Return nonzero if TRIAL can go into the call delay slot. */
2862 tls_call_delay (rtx trial)
2867 call __tls_get_addr, %tgd_call (foo)
2868 add %l7, %o0, %o0, %tgd_add (foo)
2869 while Sun as/ld does not. */
2870 if (TARGET_GNU_TLS || !TARGET_TLS)
2873 pat = PATTERN (trial);
2874 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2877 unspec = XEXP (SET_DEST (pat), 1);
2878 if (GET_CODE (unspec) != UNSPEC
2879 || (XINT (unspec, 1) != UNSPEC_TLSGD
2880 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2886 /* Return nonzero if TRIAL can go into the sibling call
2890 eligible_for_sibcall_delay (rtx trial)
2894 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2897 if (get_attr_length (trial) != 1)
2900 pat = PATTERN (trial);
2902 if (current_function_uses_only_leaf_regs)
2904 /* If the tail call is done using the call instruction,
2905 we have to restore %o7 in the delay slot. */
2906 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2909 /* %g1 is used to build the function address */
2910 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2916 /* Otherwise, only operations which can be done in tandem with
2917 a `restore' insn can go into the delay slot. */
2918 if (GET_CODE (SET_DEST (pat)) != REG
2919 || REGNO (SET_DEST (pat)) < 24
2920 || REGNO (SET_DEST (pat)) >= 32)
2923 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2925 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2928 src = SET_SRC (pat);
2930 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2931 && arith_operand (src, GET_MODE (src)))
2934 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2936 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2939 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2940 && arith_double_operand (src, GET_MODE (src)))
2941 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2943 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2944 && register_operand (src, SFmode))
2947 else if (GET_CODE (src) == PLUS
2948 && arith_operand (XEXP (src, 0), SImode)
2949 && arith_operand (XEXP (src, 1), SImode)
2950 && (register_operand (XEXP (src, 0), SImode)
2951 || register_operand (XEXP (src, 1), SImode)))
2954 else if (GET_CODE (src) == PLUS
2955 && arith_double_operand (XEXP (src, 0), DImode)
2956 && arith_double_operand (XEXP (src, 1), DImode)
2957 && (register_operand (XEXP (src, 0), DImode)
2958 || register_operand (XEXP (src, 1), DImode)))
2961 else if (GET_CODE (src) == LO_SUM
2962 && ! TARGET_CM_MEDMID
2963 && ((register_operand (XEXP (src, 0), SImode)
2964 && immediate_operand (XEXP (src, 1), SImode))
2966 && register_operand (XEXP (src, 0), DImode)
2967 && immediate_operand (XEXP (src, 1), DImode))))
2970 else if (GET_CODE (src) == ASHIFT
2971 && (register_operand (XEXP (src, 0), SImode)
2972 || register_operand (XEXP (src, 0), DImode))
2973 && XEXP (src, 1) == const1_rtx)
2980 check_return_regs (rtx x)
2982 switch (GET_CODE (x))
2985 return IN_OR_GLOBAL_P (x);
3000 if (check_return_regs (XEXP (x, 1)) == 0)
3005 return check_return_regs (XEXP (x, 0));
3014 short_branch (int uid1, int uid2)
3016 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3018 /* Leave a few words of "slop". */
3019 if (delta >= -1023 && delta <= 1022)
3025 /* Return nonzero if REG is not used after INSN.
3026 We assume REG is a reload reg, and therefore does
3027 not live past labels or calls or jumps. */
3029 reg_unused_after (rtx reg, rtx insn)
3031 enum rtx_code code, prev_code = UNKNOWN;
3033 while ((insn = NEXT_INSN (insn)))
3035 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3038 code = GET_CODE (insn);
3039 if (GET_CODE (insn) == CODE_LABEL)
3042 if (GET_RTX_CLASS (code) == 'i')
3044 rtx set = single_set (insn);
3045 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3048 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3050 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3058 /* Determine if it's legal to put X into the constant pool. This
3059 is not possible if X contains the address of a symbol that is
3060 not constant (TLS) or not known at final link time (PIC). */
3063 sparc_cannot_force_const_mem (rtx x)
3065 switch (GET_CODE (x))
3069 /* Accept all non-symbolic constants. */
3073 /* Labels are OK iff we are non-PIC. */
3074 return flag_pic != 0;
3077 /* 'Naked' TLS symbol references are never OK,
3078 non-TLS symbols are OK iff we are non-PIC. */
3079 if (SYMBOL_REF_TLS_MODEL (x))
3082 return flag_pic != 0;
3085 return sparc_cannot_force_const_mem (XEXP (x, 0));
3088 return sparc_cannot_force_const_mem (XEXP (x, 0))
3089 || sparc_cannot_force_const_mem (XEXP (x, 1));
3097 /* The table we use to reference PIC data. */
3098 static GTY(()) rtx global_offset_table;
3100 /* The function we use to get at it. */
3101 static GTY(()) rtx get_pc_symbol;
3102 static char get_pc_symbol_name[256];
3104 /* Ensure that we are not using patterns that are not OK with PIC. */
3112 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3113 || (GET_CODE (recog_data.operand[i]) == CONST
3114 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3115 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3116 == global_offset_table)
3117 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3126 /* Return true if X is an address which needs a temporary register when
3127 reloaded while generating PIC code. */
3130 pic_address_needs_scratch (rtx x)
3132 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3133 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3134 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3135 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3136 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3142 /* Determine if a given RTX is a valid constant. We already know this
3143 satisfies CONSTANT_P. */
3146 legitimate_constant_p (rtx x)
3150 switch (GET_CODE (x))
3153 /* TLS symbols are not constant. */
3154 if (SYMBOL_REF_TLS_MODEL (x))
3159 inner = XEXP (x, 0);
3161 /* Offsets of TLS symbols are never valid.
3162 Discourage CSE from creating them. */
3163 if (GET_CODE (inner) == PLUS
3164 && tls_symbolic_operand (XEXP (inner, 0)))
3169 if (GET_MODE (x) == VOIDmode)
3172 /* Floating point constants are generally not ok.
3173 The only exception is 0.0 in VIS. */
3175 && (GET_MODE (x) == SFmode
3176 || GET_MODE (x) == DFmode
3177 || GET_MODE (x) == TFmode)
3178 && fp_zero_operand (x, GET_MODE (x)))
3190 /* Determine if a given RTX is a valid constant address. */
3193 constant_address_p (rtx x)
3195 switch (GET_CODE (x))
3203 if (flag_pic && pic_address_needs_scratch (x))
3205 return legitimate_constant_p (x);
3208 return !flag_pic && legitimate_constant_p (x);
3215 /* Nonzero if the constant value X is a legitimate general operand
3216 when generating PIC code. It is given that flag_pic is on and
3217 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3220 legitimate_pic_operand_p (rtx x)
3222 if (pic_address_needs_scratch (x))
3224 if (tls_symbolic_operand (x)
3225 || (GET_CODE (x) == CONST
3226 && GET_CODE (XEXP (x, 0)) == PLUS
3227 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3232 /* Return nonzero if ADDR is a valid memory address.
3233 STRICT specifies whether strict register checking applies. */
3236 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3238 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3240 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3242 else if (GET_CODE (addr) == PLUS)
3244 rs1 = XEXP (addr, 0);
3245 rs2 = XEXP (addr, 1);
3247 /* Canonicalize. REG comes first, if there are no regs,
3248 LO_SUM comes first. */
3250 && GET_CODE (rs1) != SUBREG
3252 || GET_CODE (rs2) == SUBREG
3253 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3255 rs1 = XEXP (addr, 1);
3256 rs2 = XEXP (addr, 0);
3260 && rs1 == pic_offset_table_rtx
3262 && GET_CODE (rs2) != SUBREG
3263 && GET_CODE (rs2) != LO_SUM
3264 && GET_CODE (rs2) != MEM
3265 && !tls_symbolic_operand (rs2)
3266 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3267 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3269 || GET_CODE (rs1) == SUBREG)
3270 && RTX_OK_FOR_OFFSET_P (rs2)))
3275 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3276 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3278 /* We prohibit REG + REG for TFmode when there are no instructions
3279 which accept REG+REG instructions. We do this because REG+REG
3280 is not an offsetable address. If we get the situation in reload
3281 where source and destination of a movtf pattern are both MEMs with
3282 REG+REG address, then only one of them gets converted to an
3283 offsetable address. */
3285 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3286 && TARGET_HARD_QUAD))
3289 /* We prohibit REG + REG on ARCH32 if not optimizing for
3290 DFmode/DImode because then mem_min_alignment is likely to be zero
3291 after reload and the forced split would lack a matching splitter
3293 if (TARGET_ARCH32 && !optimize
3294 && (mode == DFmode || mode == DImode))
3297 else if (USE_AS_OFFSETABLE_LO10
3298 && GET_CODE (rs1) == LO_SUM
3300 && ! TARGET_CM_MEDMID
3301 && RTX_OK_FOR_OLO10_P (rs2))
3305 imm1 = XEXP (rs1, 1);
3306 rs1 = XEXP (rs1, 0);
3307 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3311 else if (GET_CODE (addr) == LO_SUM)
3313 rs1 = XEXP (addr, 0);
3314 imm1 = XEXP (addr, 1);
3316 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3319 /* We can't allow TFmode, because an offset greater than or equal to the
3320 alignment (8) may cause the LO_SUM to overflow if !v9. */
3321 if (mode == TFmode && !TARGET_V9)
3324 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3329 if (GET_CODE (rs1) == SUBREG)
3330 rs1 = SUBREG_REG (rs1);
3336 if (GET_CODE (rs2) == SUBREG)
3337 rs2 = SUBREG_REG (rs2);
3344 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3345 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3350 if ((REGNO (rs1) >= 32
3351 && REGNO (rs1) != FRAME_POINTER_REGNUM
3352 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3354 && (REGNO (rs2) >= 32
3355 && REGNO (rs2) != FRAME_POINTER_REGNUM
3356 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3362 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3364 static GTY(()) rtx sparc_tls_symbol;
3366 sparc_tls_get_addr (void)
3368 if (!sparc_tls_symbol)
3369 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3371 return sparc_tls_symbol;
3375 sparc_tls_got (void)
3380 current_function_uses_pic_offset_table = 1;
3381 return pic_offset_table_rtx;
3384 if (!global_offset_table)
3385 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3386 temp = gen_reg_rtx (Pmode);
3387 emit_move_insn (temp, global_offset_table);
3392 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3393 this (thread-local) address. */
3396 legitimize_tls_address (rtx addr)
3398 rtx temp1, temp2, temp3, ret, o0, got, insn;
3403 if (GET_CODE (addr) == SYMBOL_REF)
3404 switch (SYMBOL_REF_TLS_MODEL (addr))
3406 case TLS_MODEL_GLOBAL_DYNAMIC:
3408 temp1 = gen_reg_rtx (SImode);
3409 temp2 = gen_reg_rtx (SImode);
3410 ret = gen_reg_rtx (Pmode);
3411 o0 = gen_rtx_REG (Pmode, 8);
3412 got = sparc_tls_got ();
3413 emit_insn (gen_tgd_hi22 (temp1, addr));
3414 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3417 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3418 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3423 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3424 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3427 CALL_INSN_FUNCTION_USAGE (insn)
3428 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3429 CALL_INSN_FUNCTION_USAGE (insn));
3430 insn = get_insns ();
3432 emit_libcall_block (insn, ret, o0, addr);
3435 case TLS_MODEL_LOCAL_DYNAMIC:
3437 temp1 = gen_reg_rtx (SImode);
3438 temp2 = gen_reg_rtx (SImode);
3439 temp3 = gen_reg_rtx (Pmode);
3440 ret = gen_reg_rtx (Pmode);
3441 o0 = gen_rtx_REG (Pmode, 8);
3442 got = sparc_tls_got ();
3443 emit_insn (gen_tldm_hi22 (temp1));
3444 emit_insn (gen_tldm_lo10 (temp2, temp1));
3447 emit_insn (gen_tldm_add32 (o0, got, temp2));
3448 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3453 emit_insn (gen_tldm_add64 (o0, got, temp2));
3454 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3457 CALL_INSN_FUNCTION_USAGE (insn)
3458 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3459 CALL_INSN_FUNCTION_USAGE (insn));
3460 insn = get_insns ();
3462 emit_libcall_block (insn, temp3, o0,
3463 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3464 UNSPEC_TLSLD_BASE));
3465 temp1 = gen_reg_rtx (SImode);
3466 temp2 = gen_reg_rtx (SImode);
3467 emit_insn (gen_tldo_hix22 (temp1, addr));
3468 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3470 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3472 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3475 case TLS_MODEL_INITIAL_EXEC:
3476 temp1 = gen_reg_rtx (SImode);
3477 temp2 = gen_reg_rtx (SImode);
3478 temp3 = gen_reg_rtx (Pmode);
3479 got = sparc_tls_got ();
3480 emit_insn (gen_tie_hi22 (temp1, addr));
3481 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3483 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3485 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3488 ret = gen_reg_rtx (Pmode);
3490 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3493 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3497 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3500 case TLS_MODEL_LOCAL_EXEC:
3501 temp1 = gen_reg_rtx (Pmode);
3502 temp2 = gen_reg_rtx (Pmode);
3505 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3506 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3510 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3511 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3513 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3521 abort (); /* for now ... */
3527 /* Legitimize PIC addresses. If the address is already position-independent,
3528 we return ORIG. Newly generated position-independent addresses go into a
3529 reg. This is REG if nonzero, otherwise we allocate register(s) as
3533 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3536 if (GET_CODE (orig) == SYMBOL_REF)
3538 rtx pic_ref, address;
3543 if (reload_in_progress || reload_completed)
3546 reg = gen_reg_rtx (Pmode);
3551 /* If not during reload, allocate another temp reg here for loading
3552 in the address, so that these instructions can be optimized
3554 rtx temp_reg = ((reload_in_progress || reload_completed)
3555 ? reg : gen_reg_rtx (Pmode));
3557 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3558 won't get confused into thinking that these two instructions
3559 are loading in the true address of the symbol. If in the
3560 future a PIC rtx exists, that should be used instead. */
3561 if (Pmode == SImode)
3563 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3564 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3568 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3569 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3576 pic_ref = gen_rtx_MEM (Pmode,
3577 gen_rtx_PLUS (Pmode,
3578 pic_offset_table_rtx, address));
3579 current_function_uses_pic_offset_table = 1;
3580 RTX_UNCHANGING_P (pic_ref) = 1;
3581 insn = emit_move_insn (reg, pic_ref);
3582 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3584 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3588 else if (GET_CODE (orig) == CONST)
3592 if (GET_CODE (XEXP (orig, 0)) == PLUS
3593 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3598 if (reload_in_progress || reload_completed)
3601 reg = gen_reg_rtx (Pmode);
3604 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3606 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3607 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3608 base == reg ? 0 : reg);
3613 if (GET_CODE (offset) == CONST_INT)
3615 if (SMALL_INT (offset))
3616 return plus_constant (base, INTVAL (offset));
3617 else if (! reload_in_progress && ! reload_completed)
3618 offset = force_reg (Pmode, offset);
3620 /* If we reach here, then something is seriously wrong. */
3623 return gen_rtx_PLUS (Pmode, base, offset);
3625 else if (GET_CODE (orig) == LABEL_REF)
3626 /* ??? Why do we do this? */
3627 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3628 the register is live instead, in case it is eliminated. */
3629 current_function_uses_pic_offset_table = 1;
3634 /* Try machine-dependent ways of modifying an illegitimate address X
3635 to be legitimate. If we find one, return the new, valid address.
3637 OLDX is the address as it was before break_out_memory_refs was called.
3638 In some cases it is useful to look at this to decide what needs to be done.
3640 MODE is the mode of the operand pointed to by X. */
3643 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3647 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3648 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3649 force_operand (XEXP (x, 0), NULL_RTX));
3650 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3651 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3652 force_operand (XEXP (x, 1), NULL_RTX));
3653 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3654 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3656 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3657 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3658 force_operand (XEXP (x, 1), NULL_RTX));
3660 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3663 if (tls_symbolic_operand (x))
3664 x = legitimize_tls_address (x);
3666 x = legitimize_pic_address (x, mode, 0);
3667 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3668 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3669 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3670 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3671 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3672 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3673 else if (GET_CODE (x) == SYMBOL_REF
3674 || GET_CODE (x) == CONST
3675 || GET_CODE (x) == LABEL_REF)
3676 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3680 /* Emit special PIC prologues. */
3683 load_pic_register (void)
3685 /* Labels to get the PC in the prologue of this function. */
3686 int orig_flag_pic = flag_pic;
3691 /* If we haven't emitted the special get_pc helper function, do so now. */
3692 if (get_pc_symbol_name[0] == 0)
3696 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3699 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3701 ASM_OUTPUT_ALIGN (asm_out_file, align);
3702 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3703 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3706 /* Initialize every time through, since we can't easily
3707 know this to be permanent. */
3708 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3709 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3712 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3715 flag_pic = orig_flag_pic;
3717 /* Need to emit this whether or not we obey regdecls,
3718 since setjmp/longjmp can cause life info to screw up.
3719 ??? In the case where we don't obey regdecls, this is not sufficient
3720 since we may not fall out the bottom. */
3721 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3724 /* Return 1 if RTX is a MEM which is known to be aligned to at
3725 least a DESIRED byte boundary. */
3728 mem_min_alignment (rtx mem, int desired)
3730 rtx addr, base, offset;
3732 /* If it's not a MEM we can't accept it. */
3733 if (GET_CODE (mem) != MEM)
3736 addr = XEXP (mem, 0);
3737 base = offset = NULL_RTX;
3738 if (GET_CODE (addr) == PLUS)
3740 if (GET_CODE (XEXP (addr, 0)) == REG)
3742 base = XEXP (addr, 0);
3744 /* What we are saying here is that if the base
3745 REG is aligned properly, the compiler will make
3746 sure any REG based index upon it will be so
3748 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3749 offset = XEXP (addr, 1);
3751 offset = const0_rtx;
3754 else if (GET_CODE (addr) == REG)
3757 offset = const0_rtx;
3760 if (base != NULL_RTX)
3762 int regno = REGNO (base);
3764 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3766 /* Check if the compiler has recorded some information
3767 about the alignment of the base REG. If reload has
3768 completed, we already matched with proper alignments.
3769 If not running global_alloc, reload might give us
3770 unaligned pointer to local stack though. */
3772 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3773 || (optimize && reload_completed))
3774 && (INTVAL (offset) & (desired - 1)) == 0)
3779 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3783 else if (! TARGET_UNALIGNED_DOUBLES
3784 || CONSTANT_P (addr)
3785 || GET_CODE (addr) == LO_SUM)
3787 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3788 is true, in which case we can only assume that an access is aligned if
3789 it is to a constant address, or the address involves a LO_SUM. */
3793 /* An obviously unaligned address. */
3798 /* Vectors to keep interesting information about registers where it can easily
3799 be got. We used to use the actual mode value as the bit number, but there
3800 are more than 32 modes now. Instead we use two tables: one indexed by
3801 hard register number, and one indexed by mode. */
3803 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3804 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3805 mapped into one sparc_mode_class mode. */
3807 enum sparc_mode_class {
3808 S_MODE, D_MODE, T_MODE, O_MODE,
3809 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3813 /* Modes for single-word and smaller quantities. */
3814 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3816 /* Modes for double-word and smaller quantities. */
3817 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3819 /* Modes for quad-word and smaller quantities. */
3820 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3822 /* Modes for 8-word and smaller quantities. */
3823 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3825 /* Modes for single-float quantities. We must allow any single word or
3826 smaller quantity. This is because the fix/float conversion instructions
3827 take integer inputs/outputs from the float registers. */
3828 #define SF_MODES (S_MODES)
3830 /* Modes for double-float and smaller quantities. */
3831 #define DF_MODES (S_MODES | D_MODES)
3833 /* Modes for double-float only quantities. */
3834 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3836 /* Modes for quad-float only quantities. */
3837 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3839 /* Modes for quad-float and smaller quantities. */
3840 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3842 /* Modes for quad-float and double-float quantities. */
3843 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3845 /* Modes for quad-float pair only quantities. */
3846 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3848 /* Modes for quad-float pairs and smaller quantities. */
3849 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3851 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3853 /* Modes for condition codes. */
3854 #define CC_MODES (1 << (int) CC_MODE)
3855 #define CCFP_MODES (1 << (int) CCFP_MODE)
3857 /* Value is 1 if register/mode pair is acceptable on sparc.
3858 The funny mixture of D and T modes is because integer operations
3859 do not specially operate on tetra quantities, so non-quad-aligned
3860 registers can hold quadword quantities (except %o4 and %i4 because
3861 they cross fixed registers). */
3863 /* This points to either the 32 bit or the 64 bit version. */
3864 const int *hard_regno_mode_classes;
3866 static const int hard_32bit_mode_classes[] = {
3867 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3868 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3869 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3870 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3872 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3873 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3874 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3875 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3877 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3878 and none can hold SFmode/SImode values. */
3879 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3880 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3881 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3882 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3885 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3891 static const int hard_64bit_mode_classes[] = {
3892 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3893 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3894 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3895 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3897 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3898 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3899 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3900 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3902 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3903 and none can hold SFmode/SImode values. */
3904 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3905 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3906 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3907 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3910 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3916 int sparc_mode_class [NUM_MACHINE_MODES];
3918 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3921 sparc_init_modes (void)
3925 for (i = 0; i < NUM_MACHINE_MODES; i++)
3927 switch (GET_MODE_CLASS (i))
3930 case MODE_PARTIAL_INT:
3931 case MODE_COMPLEX_INT:
3932 if (GET_MODE_SIZE (i) <= 4)
3933 sparc_mode_class[i] = 1 << (int) S_MODE;
3934 else if (GET_MODE_SIZE (i) == 8)
3935 sparc_mode_class[i] = 1 << (int) D_MODE;
3936 else if (GET_MODE_SIZE (i) == 16)
3937 sparc_mode_class[i] = 1 << (int) T_MODE;
3938 else if (GET_MODE_SIZE (i) == 32)
3939 sparc_mode_class[i] = 1 << (int) O_MODE;
3941 sparc_mode_class[i] = 0;
3944 case MODE_COMPLEX_FLOAT:
3945 if (GET_MODE_SIZE (i) <= 4)
3946 sparc_mode_class[i] = 1 << (int) SF_MODE;
3947 else if (GET_MODE_SIZE (i) == 8)
3948 sparc_mode_class[i] = 1 << (int) DF_MODE;
3949 else if (GET_MODE_SIZE (i) == 16)
3950 sparc_mode_class[i] = 1 << (int) TF_MODE;
3951 else if (GET_MODE_SIZE (i) == 32)
3952 sparc_mode_class[i] = 1 << (int) OF_MODE;
3954 sparc_mode_class[i] = 0;
3958 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3959 we must explicitly check for them here. */
3960 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3961 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3962 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3963 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3964 sparc_mode_class[i] = 1 << (int) CC_MODE;
3966 sparc_mode_class[i] = 0;
3972 hard_regno_mode_classes = hard_64bit_mode_classes;
3974 hard_regno_mode_classes = hard_32bit_mode_classes;
3976 /* Initialize the array used by REGNO_REG_CLASS. */
3977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3979 if (i < 16 && TARGET_V8PLUS)
3980 sparc_regno_reg_class[i] = I64_REGS;
3981 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3982 sparc_regno_reg_class[i] = GENERAL_REGS;
3984 sparc_regno_reg_class[i] = FP_REGS;
3986 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3988 sparc_regno_reg_class[i] = FPCC_REGS;
3990 sparc_regno_reg_class[i] = NO_REGS;
3994 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3995 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3996 v9 int regs as it simplifies the code. */
3999 save_regs (FILE *file, int low, int high, const char *base,
4000 int offset, int n_regs, int real_offset)
4004 if (TARGET_ARCH64 && high <= 32)
4006 for (i = low; i < high; i++)
4008 if (regs_ever_live[i] && ! call_used_regs[i])
4010 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4011 reg_names[i], base, offset + 4 * n_regs);
4012 if (dwarf2out_do_frame ())
4013 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4020 for (i = low; i < high; i += 2)
4022 if (regs_ever_live[i] && ! call_used_regs[i])
4024 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4026 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4027 reg_names[i], base, offset + 4 * n_regs);
4028 if (dwarf2out_do_frame ())
4030 char *l = dwarf2out_cfi_label ();
4031 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4032 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4038 fprintf (file, "\tst\t%s, [%s+%d]\n",
4039 reg_names[i], base, offset + 4 * n_regs);
4040 if (dwarf2out_do_frame ())
4041 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4047 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4049 fprintf (file, "\tst\t%s, [%s+%d]\n",
4050 reg_names[i+1], base, offset + 4 * n_regs + 4);
4051 if (dwarf2out_do_frame ())
4052 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4061 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4063 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4064 v9 int regs as it simplifies the code. */
4067 restore_regs (FILE *file, int low, int high, const char *base,
4068 int offset, int n_regs)
4072 if (TARGET_ARCH64 && high <= 32)
4074 for (i = low; i < high; i++)
4076 if (regs_ever_live[i] && ! call_used_regs[i])
4077 fprintf (file, "\tldx\t[%s+%d], %s\n",
4078 base, offset + 4 * n_regs, reg_names[i]),
4084 for (i = low; i < high; i += 2)
4086 if (regs_ever_live[i] && ! call_used_regs[i])
4087 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4088 fprintf (file, "\tldd\t[%s+%d], %s\n",
4089 base, offset + 4 * n_regs, reg_names[i]),
4092 fprintf (file, "\tld\t[%s+%d], %s\n",
4093 base, offset + 4 * n_regs, reg_names[i]),
4095 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4096 fprintf (file, "\tld\t[%s+%d], %s\n",
4097 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4104 /* Compute the frame size required by the function. This function is called
4105 during the reload pass and also by output_function_prologue(). */
4108 compute_frame_size (int size, int leaf_function)
4111 int outgoing_args_size = (current_function_outgoing_args_size
4112 + REG_PARM_STACK_SPACE (current_function_decl));
4114 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4115 even to v9 int regs to be consistent with save_regs/restore_regs. */
4119 for (i = 0; i < 8; i++)
4120 if (regs_ever_live[i] && ! call_used_regs[i])
4125 for (i = 0; i < 8; i += 2)
4126 if ((regs_ever_live[i] && ! call_used_regs[i])
4127 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4131 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4132 if ((regs_ever_live[i] && ! call_used_regs[i])
4133 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4136 /* Set up values for use in `function_epilogue'. */
4137 num_gfregs = n_regs;
4139 if (leaf_function && n_regs == 0
4140 && size == 0 && current_function_outgoing_args_size == 0)
4142 actual_fsize = apparent_fsize = 0;
4146 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4147 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4148 apparent_fsize += n_regs * 4;
4149 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4152 /* Make sure nothing can clobber our register windows.
4153 If a SAVE must be done, or there is a stack-local variable,
4154 the register window area must be allocated.
4155 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4156 if (leaf_function == 0 || size > 0)
4157 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4159 return SPARC_STACK_ALIGN (actual_fsize);
4162 /* Build a (32 bit) big number in a register. */
4163 /* ??? We may be able to use the set macro here too. */
4166 build_big_number (FILE *file, int num, const char *reg)
4168 if (num >= 0 || ! TARGET_ARCH64)
4170 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
4171 if ((num & 0x3ff) != 0)
4172 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
4174 else /* num < 0 && TARGET_ARCH64 */
4176 /* Sethi does not sign extend, so we must use a little trickery
4177 to use it for negative numbers. Invert the constant before
4178 loading it in, then use xor immediate to invert the loaded bits
4179 (along with the upper 32 bits) to the desired constant. This
4180 works because the sethi and immediate fields overlap. */
4183 int low = -0x400 + (asize & 0x3FF);
4185 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
4186 inv, reg, reg, low, reg);
4190 /* Output any necessary .register pseudo-ops. */
4192 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4194 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4200 /* Check if %g[2367] were used without
4201 .register being printed for them already. */
4202 for (i = 2; i < 8; i++)
4204 if (regs_ever_live [i]
4205 && ! sparc_hard_reg_printed [i])
4207 sparc_hard_reg_printed [i] = 1;
4208 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4215 /* This function generates the assembly code for function entry.
4216 FILE is a stdio stream to output the code to.
4217 SIZE is an int: how many units of temporary storage to allocate.
4218 Refer to the array `regs_ever_live' to determine which registers
4219 to save; `regs_ever_live[I]' is nonzero if register number I
4220 is ever used in the function. This macro is responsible for
4221 knowing which registers should not be saved even if used. */
4223 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4224 of memory. If any fpu reg is used in the function, we allocate
4225 such a block here, at the bottom of the frame, just in case it's needed.
4227 If this function is a leaf procedure, then we may choose not
4228 to do a "save" insn. The decision about whether or not
4229 to do this is made in regclass.c. */
4232 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4235 sparc_flat_function_prologue (file, size);
4237 sparc_nonflat_function_prologue (file, size,
4238 current_function_uses_only_leaf_regs);
4241 /* Output code for the function prologue. */
4244 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4247 sparc_output_scratch_registers (file);
4249 /* Need to use actual_fsize, since we are also allocating
4250 space for our callee (and our own register save area). */
4251 actual_fsize = compute_frame_size (size, leaf_function);
4255 frame_base_name = "%sp";
4256 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4260 frame_base_name = "%fp";
4261 frame_base_offset = SPARC_STACK_BIAS;
4264 /* This is only for the human reader. */
4265 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4267 if (actual_fsize == 0)
4269 else if (! leaf_function)
4271 if (actual_fsize <= 4096)
4272 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
4273 else if (actual_fsize <= 8192)
4275 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4276 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4280 build_big_number (file, -actual_fsize, "%g1");
4281 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4284 else /* leaf function */
4286 if (actual_fsize <= 4096)
4287 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
4288 else if (actual_fsize <= 8192)
4290 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4291 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
4295 build_big_number (file, -actual_fsize, "%g1");
4296 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4300 if (dwarf2out_do_frame () && actual_fsize)
4302 char *label = dwarf2out_cfi_label ();
4304 /* The canonical frame address refers to the top of the frame. */
4305 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4306 : HARD_FRAME_POINTER_REGNUM),
4309 if (! leaf_function)
4311 /* Note the register window save. This tells the unwinder that
4312 it needs to restore the window registers from the previous
4313 frame's window save area at 0(cfa). */
4314 dwarf2out_window_save (label);
4316 /* The return address (-8) is now in %i7. */
4317 dwarf2out_return_reg (label, 31);
4321 /* If doing anything with PIC, do it now. */
4323 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4325 /* Call saved registers are saved just above the outgoing argument area. */
4328 int offset, real_offset, n_regs;
4331 real_offset = -apparent_fsize;
4332 offset = -apparent_fsize + frame_base_offset;
4333 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4335 /* ??? This might be optimized a little as %g1 might already have a
4336 value close enough that a single add insn will do. */
4337 /* ??? Although, all of this is probably only a temporary fix
4338 because if %g1 can hold a function result, then
4339 output_function_epilogue will lose (the result will get
4341 build_big_number (file, offset, "%g1");
4342 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4348 base = frame_base_name;
4351 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4352 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4357 /* Output code to restore any call saved registers. */
4360 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4365 offset = -apparent_fsize + frame_base_offset;
4366 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4368 build_big_number (file, offset, "%g1");
4369 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4375 base = frame_base_name;
4378 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4379 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4382 /* This function generates the assembly code for function exit,
4383 on machines that need it.
4385 The function epilogue should not depend on the current stack pointer!
4386 It should use the frame pointer only. This is mandatory because
4387 of alloca; we also take advantage of it to omit stack adjustments
4388 before returning. */
4391 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4394 sparc_flat_function_epilogue (file, size);
4396 sparc_nonflat_function_epilogue (file, size,
4397 current_function_uses_only_leaf_regs);
4400 /* Output code for the function epilogue. */
4403 sparc_nonflat_function_epilogue (FILE *file,
4404 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4409 if (current_function_epilogue_delay_list == 0)
4411 /* If code does not drop into the epilogue, we need
4412 do nothing except output pending case vectors.
4414 We have to still output a dummy nop for the sake of
4415 sane backtraces. Otherwise, if the last two instructions
4416 of a function were call foo; dslot; this can make the return
4417 PC of foo (ie. address of call instruction plus 8) point to
4418 the first instruction in the next function. */
4419 rtx insn, last_real_insn;
4421 insn = get_last_insn ();
4423 last_real_insn = prev_real_insn (insn);
4425 && GET_CODE (last_real_insn) == INSN
4426 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4427 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4429 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4430 fputs("\tnop\n", file);
4432 if (GET_CODE (insn) == NOTE)
4433 insn = prev_nonnote_insn (insn);
4434 if (insn && GET_CODE (insn) == BARRIER)
4435 goto output_vectors;
4439 output_restore_regs (file, leaf_function);
4441 /* Work out how to skip the caller's unimp instruction if required. */
4443 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4445 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4447 if (! leaf_function)
4449 if (current_function_calls_eh_return)
4451 if (current_function_epilogue_delay_list)
4453 if (SKIP_CALLERS_UNIMP_P)
4456 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4458 /* If we wound up with things in our delay slot, flush them here. */
4459 else if (current_function_epilogue_delay_list)
4461 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4463 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4465 epilogue_renumber (&delay, 0);
4466 fputs (SKIP_CALLERS_UNIMP_P
4467 ? "\treturn\t%i7+12\n"
4468 : "\treturn\t%i7+8\n", file);
4469 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4476 if (GET_CODE (delay) != SET)
4479 src = SET_SRC (delay);
4480 if (GET_CODE (src) == ASHIFT)
4482 if (XEXP (src, 1) != const1_rtx)
4485 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4489 insn = gen_rtx_PARALLEL (VOIDmode,
4490 gen_rtvec (2, delay,
4491 gen_rtx_RETURN (VOIDmode)));
4492 insn = emit_jump_insn (insn);
4494 sparc_emitting_epilogue = true;
4495 final_scan_insn (insn, file, 1, 0, 1);
4496 sparc_emitting_epilogue = false;
4499 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4500 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4502 fprintf (file, "\t%s\n\trestore\n", ret);
4504 /* All of the following cases are for leaf functions. */
4505 else if (current_function_calls_eh_return)
4507 else if (current_function_epilogue_delay_list)
4509 /* eligible_for_epilogue_delay_slot ensures that if this is a
4510 leaf function, then we will only have insn in the delay slot
4511 if the frame size is zero, thus no adjust for the stack is
4513 if (actual_fsize != 0)
4515 fprintf (file, "\t%s\n", ret);
4516 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4519 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4520 avoid generating confusing assembly language output. */
4521 else if (actual_fsize == 0)
4522 fprintf (file, "\t%s\n\tnop\n", ret);
4523 else if (actual_fsize <= 4096)
4524 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4525 else if (actual_fsize <= 8192)
4526 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4527 ret, actual_fsize - 4096);
4528 else if ((actual_fsize & 0x3ff) == 0)
4529 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4532 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4533 actual_fsize, actual_fsize, ret);
4536 sparc_output_deferred_case_vectors ();
4539 /* Output a sibling call. */
4542 output_sibcall (rtx insn, rtx call_operand)
4544 int leaf_regs = current_function_uses_only_leaf_regs;
4546 int delay_slot = dbr_sequence_length () > 0;
4550 /* Call to restore global regs might clobber
4551 the delay slot. Instead of checking for this
4552 output the delay slot now. */
4555 rtx delay = NEXT_INSN (insn);
4560 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4561 PATTERN (delay) = gen_blockage ();
4562 INSN_CODE (delay) = -1;
4565 output_restore_regs (asm_out_file, leaf_regs);
4568 operands[0] = call_operand;
4572 #ifdef HAVE_AS_RELAX_OPTION
4573 /* If as and ld are relaxing tail call insns into branch always,
4574 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4575 be optimized. With sethi/jmpl as nor ld has no easy way how to
4576 find out if somebody does not branch between the sethi and jmpl. */
4579 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4583 if ((actual_fsize || ! spare_slot) && delay_slot)
4585 rtx delay = NEXT_INSN (insn);
4590 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4591 PATTERN (delay) = gen_blockage ();
4592 INSN_CODE (delay) = -1;
4597 if (actual_fsize <= 4096)
4598 size = actual_fsize;
4599 else if (actual_fsize <= 8192)
4601 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4602 size = actual_fsize - 4096;
4604 else if ((actual_fsize & 0x3ff) == 0)
4605 fprintf (asm_out_file,
4606 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4610 fprintf (asm_out_file,
4611 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4612 actual_fsize, actual_fsize);
4613 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4618 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4619 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4621 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4622 else if (! delay_slot)
4623 fputs ("\t nop\n", asm_out_file);
4628 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4629 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4630 it into branch if possible. */
4631 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4632 output_asm_insn ("call\t%a0, 0", operands);
4633 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4638 output_asm_insn ("call\t%a0, 0", operands);
4641 rtx delay = NEXT_INSN (insn), pat;
4646 pat = PATTERN (delay);
4647 if (GET_CODE (pat) != SET)
4650 operands[0] = SET_DEST (pat);
4651 pat = SET_SRC (pat);
4652 switch (GET_CODE (pat))
4655 operands[1] = XEXP (pat, 0);
4656 operands[2] = XEXP (pat, 1);
4657 output_asm_insn (" restore %r1, %2, %Y0", operands);
4660 operands[1] = XEXP (pat, 0);
4661 operands[2] = XEXP (pat, 1);
4662 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4665 operands[1] = XEXP (pat, 0);
4666 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4670 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4673 PATTERN (delay) = gen_blockage ();
4674 INSN_CODE (delay) = -1;
4677 fputs ("\t restore\n", asm_out_file);
4681 /* Functions for handling argument passing.
4683 For v8 the first six args are normally in registers and the rest are
4684 pushed. Any arg that starts within the first 6 words is at least
4685 partially passed in a register unless its data type forbids.
4687 For v9, the argument registers are laid out as an array of 16 elements
4688 and arguments are added sequentially. The first 6 int args and up to the
4689 first 16 fp args (depending on size) are passed in regs.
4691 Slot Stack Integral Float Float in structure Double Long Double
4692 ---- ----- -------- ----- ------------------ ------ -----------
4693 15 [SP+248] %f31 %f30,%f31 %d30
4694 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4695 13 [SP+232] %f27 %f26,%f27 %d26
4696 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4697 11 [SP+216] %f23 %f22,%f23 %d22
4698 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4699 9 [SP+200] %f19 %f18,%f19 %d18
4700 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4701 7 [SP+184] %f15 %f14,%f15 %d14
4702 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4703 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4704 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4705 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4706 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4707 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4708 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4710 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4712 Integral arguments are always passed as 64 bit quantities appropriately
4715 Passing of floating point values is handled as follows.
4716 If a prototype is in scope:
4717 If the value is in a named argument (i.e. not a stdarg function or a
4718 value not part of the `...') then the value is passed in the appropriate
4720 If the value is part of the `...' and is passed in one of the first 6
4721 slots then the value is passed in the appropriate int reg.
4722 If the value is part of the `...' and is not passed in one of the first 6
4723 slots then the value is passed in memory.
4724 If a prototype is not in scope:
4725 If the value is one of the first 6 arguments the value is passed in the
4726 appropriate integer reg and the appropriate fp reg.
4727 If the value is not one of the first 6 arguments the value is passed in
4728 the appropriate fp reg and in memory.
4731 /* Maximum number of int regs for args. */
4732 #define SPARC_INT_ARG_MAX 6
4733 /* Maximum number of fp regs for args. */
4734 #define SPARC_FP_ARG_MAX 16
4736 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4738 /* Handle the INIT_CUMULATIVE_ARGS macro.
4739 Initialize a variable CUM of type CUMULATIVE_ARGS
4740 for a call to a function whose data type is FNTYPE.
4741 For a library call, FNTYPE is 0. */
4744 init_cumulative_args (struct sparc_args *cum, tree fntype,
4745 rtx libname ATTRIBUTE_UNUSED,
4746 tree fndecl ATTRIBUTE_UNUSED)
4749 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4750 cum->libcall_p = fntype == 0;
4753 /* Compute the slot number to pass an argument in.
4754 Returns the slot number or -1 if passing on the stack.
4756 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4757 the preceding args and about the function being called.
4758 MODE is the argument's machine mode.
4759 TYPE is the data type of the argument (as a tree).
4760 This is null for libcalls where that information may
4762 NAMED is nonzero if this argument is a named parameter
4763 (otherwise it is an extra parameter matching an ellipsis).
4764 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4765 *PREGNO records the register number to use if scalar type.
4766 *PPADDING records the amount of padding needed in words. */
4769 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4770 tree type, int named, int incoming_p,
4771 int *pregno, int *ppadding)
4773 int regbase = (incoming_p
4774 ? SPARC_INCOMING_INT_ARG_FIRST
4775 : SPARC_OUTGOING_INT_ARG_FIRST);
4776 int slotno = cum->words;
4781 if (type != 0 && TREE_ADDRESSABLE (type))
4784 && type != 0 && mode == BLKmode
4785 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4791 /* MODE is VOIDmode when generating the actual call.
4795 case QImode : case CQImode :
4796 case HImode : case CHImode :
4797 case SImode : case CSImode :
4798 case DImode : case CDImode :
4799 case TImode : case CTImode :
4800 if (slotno >= SPARC_INT_ARG_MAX)
4802 regno = regbase + slotno;
4805 case SFmode : case SCmode :
4806 case DFmode : case DCmode :
4807 case TFmode : case TCmode :
4810 if (slotno >= SPARC_INT_ARG_MAX)
4812 regno = regbase + slotno;
4816 if ((mode == TFmode || mode == TCmode)
4817 && (slotno & 1) != 0)
4818 slotno++, *ppadding = 1;
4819 if (TARGET_FPU && named)
4821 if (slotno >= SPARC_FP_ARG_MAX)
4823 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4829 if (slotno >= SPARC_INT_ARG_MAX)
4831 regno = regbase + slotno;
4837 /* For sparc64, objects requiring 16 byte alignment get it. */
4840 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4841 slotno++, *ppadding = 1;
4845 || (type && TREE_CODE (type) == UNION_TYPE))
4847 if (slotno >= SPARC_INT_ARG_MAX)
4849 regno = regbase + slotno;
4854 int intregs_p = 0, fpregs_p = 0;
4855 /* The ABI obviously doesn't specify how packed
4856 structures are passed. These are defined to be passed
4857 in int regs if possible, otherwise memory. */
4860 /* First see what kinds of registers we need. */
4861 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4863 if (TREE_CODE (field) == FIELD_DECL)
4865 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4870 if (DECL_PACKED (field))
4874 if (packed_p || !named)
4875 fpregs_p = 0, intregs_p = 1;
4877 /* If all arg slots are filled, then must pass on stack. */
4878 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4880 /* If there are only int args and all int arg slots are filled,
4881 then must pass on stack. */
4882 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4884 /* Note that even if all int arg slots are filled, fp members may
4885 still be passed in regs if such regs are available.
4886 *PREGNO isn't set because there may be more than one, it's up
4887 to the caller to compute them. */
4900 /* Handle recursive register counting for structure field layout. */
4902 struct function_arg_record_value_parms
4904 rtx ret; /* return expression being built. */
4905 int slotno; /* slot number of the argument. */
4906 int named; /* whether the argument is named. */
4907 int regbase; /* regno of the base register. */
4908 int stack; /* 1 if part of the argument is on the stack. */
4909 int intoffset; /* offset of the pending integer field. */
4910 unsigned int nregs; /* number of words passed in registers. */
4913 static void function_arg_record_value_3
4914 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4915 static void function_arg_record_value_2
4916 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4917 static void function_arg_record_value_1
4918 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
4919 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4921 /* A subroutine of function_arg_record_value. Traverse the structure
4922 recursively and determine how many registers will be required. */
4925 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4926 struct function_arg_record_value_parms *parms)
4930 /* The ABI obviously doesn't specify how packed structures are
4931 passed. These are defined to be passed in int regs if possible,
4932 otherwise memory. */
4935 /* We need to compute how many registers are needed so we can
4936 allocate the PARALLEL but before we can do that we need to know
4937 whether there are any packed fields. If there are, int regs are
4938 used regardless of whether there are fp values present. */
4939 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4941 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4948 /* Compute how many registers we need. */
4949 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4951 if (TREE_CODE (field) == FIELD_DECL)
4953 HOST_WIDE_INT bitpos = startbitpos;
4955 if (DECL_SIZE (field) != 0
4956 && host_integerp (bit_position (field), 1))
4957 bitpos += int_bit_position (field);
4959 /* ??? FIXME: else assume zero offset. */
4961 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4962 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4963 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4964 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4965 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4971 if (parms->intoffset != -1)
4973 int intslots, this_slotno;
4975 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4977 this_slotno = parms->slotno + parms->intoffset
4980 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4982 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4983 /* We need to pass this field on the stack. */
4987 parms->nregs += intslots;
4988 parms->intoffset = -1;
4991 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4992 If it wasn't true we wouldn't be here. */
4994 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4999 if (parms->intoffset == -1)
5000 parms->intoffset = bitpos;
5006 /* A subroutine of function_arg_record_value. Assign the bits of the
5007 structure between parms->intoffset and bitpos to integer registers. */
5010 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5011 struct function_arg_record_value_parms *parms)
5013 enum machine_mode mode;
5015 unsigned int startbit, endbit;
5016 int this_slotno, intslots, intoffset;
5019 if (parms->intoffset == -1)
5022 intoffset = parms->intoffset;
5023 parms->intoffset = -1;
5025 startbit = intoffset & -BITS_PER_WORD;
5026 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5027 intslots = (endbit - startbit) / BITS_PER_WORD;
5028 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5030 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5034 /* If this is the trailing part of a word, only load that much into
5035 the register. Otherwise load the whole register. Note that in
5036 the latter case we may pick up unwanted bits. It's not a problem
5037 at the moment but may wish to revisit. */
5039 if (intoffset % BITS_PER_WORD != 0)
5040 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5045 intoffset /= BITS_PER_UNIT;
5048 regno = parms->regbase + this_slotno;
5049 reg = gen_rtx_REG (mode, regno);
5050 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5051 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5054 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5058 while (intslots > 0);
5061 /* A subroutine of function_arg_record_value. Traverse the structure
5062 recursively and assign bits to floating point registers. Track which
5063 bits in between need integer registers; invoke function_arg_record_value_3
5064 to make that happen. */
5067 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5068 struct function_arg_record_value_parms *parms)
5073 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5075 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5082 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5084 if (TREE_CODE (field) == FIELD_DECL)
5086 HOST_WIDE_INT bitpos = startbitpos;
5088 if (DECL_SIZE (field) != 0
5089 && host_integerp (bit_position (field), 1))
5090 bitpos += int_bit_position (field);
5092 /* ??? FIXME: else assume zero offset. */
5094 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5095 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
5096 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5097 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
5098 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
5104 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5106 enum machine_mode mode = DECL_MODE (field);
5109 function_arg_record_value_3 (bitpos, parms);
5110 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5111 + ((mode == SFmode || mode == SCmode)
5112 && (bitpos & 32) != 0);
5115 case SCmode: mode = SFmode; break;
5116 case DCmode: mode = DFmode; break;
5117 case TCmode: mode = TFmode; break;
5120 reg = gen_rtx_REG (mode, regno);
5121 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5122 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5123 GEN_INT (bitpos / BITS_PER_UNIT));
5125 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5127 regno += GET_MODE_SIZE (mode) / 4;
5128 reg = gen_rtx_REG (mode, regno);
5129 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5130 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5131 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5138 if (parms->intoffset == -1)
5139 parms->intoffset = bitpos;
5145 /* Used by function_arg and function_value to implement the complex
5146 conventions of the 64-bit ABI for passing and returning structures.
5147 Return an expression valid as a return value for the two macros
5148 FUNCTION_ARG and FUNCTION_VALUE.
5150 TYPE is the data type of the argument (as a tree).
5151 This is null for libcalls where that information may
5153 MODE is the argument's machine mode.
5154 SLOTNO is the index number of the argument's slot in the parameter array.
5155 NAMED is nonzero if this argument is a named parameter
5156 (otherwise it is an extra parameter matching an ellipsis).
5157 REGBASE is the regno of the base register for the parameter array. */
5160 function_arg_record_value (tree type, enum machine_mode mode,
5161 int slotno, int named, int regbase)
5163 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5164 struct function_arg_record_value_parms parms;
5167 parms.ret = NULL_RTX;
5168 parms.slotno = slotno;
5169 parms.named = named;
5170 parms.regbase = regbase;
5173 /* Compute how many registers we need. */
5175 parms.intoffset = 0;
5176 function_arg_record_value_1 (type, 0, &parms);
5178 if (parms.intoffset != -1)
5180 unsigned int startbit, endbit;
5181 int intslots, this_slotno;
5183 startbit = parms.intoffset & -BITS_PER_WORD;
5184 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5185 intslots = (endbit - startbit) / BITS_PER_WORD;
5186 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5188 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5190 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5191 /* We need to pass this field on the stack. */
5195 parms.nregs += intslots;
5197 nregs = parms.nregs;
5199 /* Allocate the vector and handle some annoying special cases. */
5202 /* ??? Empty structure has no value? Duh? */
5205 /* Though there's nothing really to store, return a word register
5206 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5207 leads to breakage due to the fact that there are zero bytes to
5209 return gen_rtx_REG (mode, regbase);
5213 /* ??? C++ has structures with no fields, and yet a size. Give up
5214 for now and pass everything back in integer registers. */
5215 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5217 if (nregs + slotno > SPARC_INT_ARG_MAX)
5218 nregs = SPARC_INT_ARG_MAX - slotno;
5223 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5225 /* If at least one field must be passed on the stack, generate
5226 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5227 also be passed on the stack. We can't do much better because the
5228 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5229 of structures for which the fields passed exclusively in registers
5230 are not at the beginning of the structure. */
5232 XVECEXP (parms.ret, 0, 0)
5233 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5235 /* Fill in the entries. */
5237 parms.intoffset = 0;
5238 function_arg_record_value_2 (type, 0, &parms);
5239 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5241 if (parms.nregs != nregs)
5247 /* Handle the FUNCTION_ARG macro.
5248 Determine where to put an argument to a function.
5249 Value is zero to push the argument on the stack,
5250 or a hard register in which to store the argument.
5252 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5253 the preceding args and about the function being called.
5254 MODE is the argument's machine mode.
5255 TYPE is the data type of the argument (as a tree).
5256 This is null for libcalls where that information may
5258 NAMED is nonzero if this argument is a named parameter
5259 (otherwise it is an extra parameter matching an ellipsis).
5260 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5263 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5264 tree type, int named, int incoming_p)
5266 int regbase = (incoming_p
5267 ? SPARC_INCOMING_INT_ARG_FIRST
5268 : SPARC_OUTGOING_INT_ARG_FIRST);
5269 int slotno, regno, padding;
5272 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5280 reg = gen_rtx_REG (mode, regno);
5284 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5285 but also have the slot allocated for them.
5286 If no prototype is in scope fp values in register slots get passed
5287 in two places, either fp regs and int regs or fp regs and memory. */
5288 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5289 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5290 && SPARC_FP_REG_P (regno))
5292 reg = gen_rtx_REG (mode, regno);
5293 if (cum->prototype_p || cum->libcall_p)
5295 /* "* 2" because fp reg numbers are recorded in 4 byte
5298 /* ??? This will cause the value to be passed in the fp reg and
5299 in the stack. When a prototype exists we want to pass the
5300 value in the reg but reserve space on the stack. That's an
5301 optimization, and is deferred [for a bit]. */
5302 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5303 return gen_rtx_PARALLEL (mode,
5305 gen_rtx_EXPR_LIST (VOIDmode,
5306 NULL_RTX, const0_rtx),
5307 gen_rtx_EXPR_LIST (VOIDmode,
5311 /* ??? It seems that passing back a register even when past
5312 the area declared by REG_PARM_STACK_SPACE will allocate
5313 space appropriately, and will not copy the data onto the
5314 stack, exactly as we desire.
5316 This is due to locate_and_pad_parm being called in
5317 expand_call whenever reg_parm_stack_space > 0, which
5318 while beneficial to our example here, would seem to be
5319 in error from what had been intended. Ho hum... -- r~ */
5327 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5331 /* On incoming, we don't need to know that the value
5332 is passed in %f0 and %i0, and it confuses other parts
5333 causing needless spillage even on the simplest cases. */
5337 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5338 + (regno - SPARC_FP_ARG_FIRST) / 2);
5340 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5341 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5343 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5347 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5348 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5349 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5353 else if (type && TREE_CODE (type) == RECORD_TYPE)
5355 /* Structures up to 16 bytes in size are passed in arg slots on the
5356 stack and are promoted to registers where possible. */
5358 if (int_size_in_bytes (type) > 16)
5359 abort (); /* shouldn't get here */
5361 return function_arg_record_value (type, mode, slotno, named, regbase);
5363 else if (type && TREE_CODE (type) == UNION_TYPE)
5365 enum machine_mode mode;
5366 int bytes = int_size_in_bytes (type);
5371 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5372 reg = gen_rtx_REG (mode, regno);
5376 /* Scalar or complex int. */
5377 reg = gen_rtx_REG (mode, regno);
5383 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5384 For an arg passed partly in registers and partly in memory,
5385 this is the number of registers used.
5386 For args passed entirely in registers or entirely in memory, zero.
5388 Any arg that starts in the first 6 regs but won't entirely fit in them
5389 needs partial registers on v8. On v9, structures with integer
5390 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5391 values that begin in the last fp reg [where "last fp reg" varies with the
5392 mode] will be split between that reg and memory. */
5395 function_arg_partial_nregs (const struct sparc_args *cum,
5396 enum machine_mode mode, tree type, int named)
5398 int slotno, regno, padding;
5400 /* We pass 0 for incoming_p here, it doesn't matter. */
5401 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5408 if ((slotno + (mode == BLKmode
5409 ? ROUND_ADVANCE (int_size_in_bytes (type))
5410 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5411 > NPARM_REGS (SImode))
5412 return NPARM_REGS (SImode) - slotno;
5417 if (type && AGGREGATE_TYPE_P (type))
5419 int size = int_size_in_bytes (type);
5420 int align = TYPE_ALIGN (type);
5423 slotno += slotno & 1;
5424 if (size > 8 && size <= 16
5425 && slotno == SPARC_INT_ARG_MAX - 1)
5428 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5429 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5430 && ! (TARGET_FPU && named)))
5432 if (GET_MODE_ALIGNMENT (mode) == 128)
5434 slotno += slotno & 1;
5435 if (slotno == SPARC_INT_ARG_MAX - 2)
5440 if (slotno == SPARC_INT_ARG_MAX - 1)
5444 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5446 if (GET_MODE_ALIGNMENT (mode) == 128)
5447 slotno += slotno & 1;
5448 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5456 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5457 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5458 quad-precision floats by invisible reference.
5459 v9: Aggregates greater than 16 bytes are passed by reference.
5460 For Pascal, also pass arrays by reference. */
5463 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5464 enum machine_mode mode, tree type,
5465 int named ATTRIBUTE_UNUSED)
5469 return ((type && AGGREGATE_TYPE_P (type))
5470 || mode == TFmode || mode == TCmode);
5474 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5475 /* Consider complex values as aggregates, so care for TCmode. */
5476 || GET_MODE_SIZE (mode) > 16
5478 && AGGREGATE_TYPE_P (type)
5479 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5483 /* Handle the FUNCTION_ARG_ADVANCE macro.
5484 Update the data in CUM to advance over an argument
5485 of mode MODE and data type TYPE.
5486 TYPE is null for libcalls where that information may not be available. */
5489 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5490 tree type, int named)
5492 int slotno, regno, padding;
5494 /* We pass 0 for incoming_p here, it doesn't matter. */
5495 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5497 /* If register required leading padding, add it. */
5499 cum->words += padding;
5503 cum->words += (mode != BLKmode
5504 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5505 : ROUND_ADVANCE (int_size_in_bytes (type)));
5509 if (type && AGGREGATE_TYPE_P (type))
5511 int size = int_size_in_bytes (type);
5515 else if (size <= 16)
5517 else /* passed by reference */
5520 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5524 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5526 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5530 cum->words += (mode != BLKmode
5531 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5532 : ROUND_ADVANCE (int_size_in_bytes (type)));
5537 /* Handle the FUNCTION_ARG_PADDING macro.
5538 For the 64 bit ABI structs are always stored left shifted in their
5542 function_arg_padding (enum machine_mode mode, tree type)
5544 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5547 /* Fall back to the default. */
5548 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5551 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5552 For v9, function return values are subject to the same rules as arguments,
5553 except that up to 32-bytes may be returned in registers. */
5556 function_value (tree type, enum machine_mode mode, int incoming_p)
5559 int regbase = (incoming_p
5560 ? SPARC_OUTGOING_INT_ARG_FIRST
5561 : SPARC_INCOMING_INT_ARG_FIRST);
5563 if (TARGET_ARCH64 && type)
5565 if (TREE_CODE (type) == RECORD_TYPE)
5567 /* Structures up to 32 bytes in size are passed in registers,
5568 promoted to fp registers where possible. */
5570 if (int_size_in_bytes (type) > 32)
5571 abort (); /* shouldn't get here */
5573 return function_arg_record_value (type, mode, 0, 1, regbase);
5575 else if (AGGREGATE_TYPE_P (type))
5577 /* All other aggregate types are passed in an integer register
5578 in a mode corresponding to the size of the type. */
5579 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5584 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5589 && GET_MODE_CLASS (mode) == MODE_INT
5590 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5591 && type && ! AGGREGATE_TYPE_P (type))
5595 regno = BASE_RETURN_VALUE_REG (mode);
5597 regno = BASE_OUTGOING_VALUE_REG (mode);
5599 return gen_rtx_REG (mode, regno);
5602 /* Do what is necessary for `va_start'. We look at the current function
5603 to determine if stdarg or varargs is used and return the address of
5604 the first unnamed parameter. */
5607 sparc_builtin_saveregs (void)
5609 int first_reg = current_function_args_info.words;
5613 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5614 emit_move_insn (gen_rtx_MEM (word_mode,
5615 gen_rtx_PLUS (Pmode,
5617 GEN_INT (FIRST_PARM_OFFSET (0)
5620 gen_rtx_REG (word_mode,
5621 BASE_INCOMING_ARG_REG (word_mode) + regno));
5623 address = gen_rtx_PLUS (Pmode,
5625 GEN_INT (FIRST_PARM_OFFSET (0)
5626 + UNITS_PER_WORD * first_reg));
5631 /* Implement `va_start' for varargs and stdarg. */
5634 sparc_va_start (tree valist, rtx nextarg)
5636 nextarg = expand_builtin_saveregs ();
5637 std_expand_builtin_va_start (valist, nextarg);
5640 /* Implement `va_arg'. */
5643 sparc_va_arg (tree valist, tree type)
5645 HOST_WIDE_INT size, rsize, align;
5650 /* Round up sizeof(type) to a word. */
5651 size = int_size_in_bytes (type);
5652 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5657 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5658 align = 2 * UNITS_PER_WORD;
5660 if (AGGREGATE_TYPE_P (type))
5662 if ((unsigned HOST_WIDE_INT) size > 16)
5665 size = rsize = UNITS_PER_WORD;
5668 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5669 given one 8 byte slot. */
5671 size = rsize = UNITS_PER_WORD;
5678 if (AGGREGATE_TYPE_P (type)
5679 || TYPE_MODE (type) == TFmode
5680 || TYPE_MODE (type) == TCmode)
5683 size = rsize = UNITS_PER_WORD;
5690 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5691 build_int_2 (align - 1, 0)));
5692 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5693 build_int_2 (-align, -1)));
5696 addr = incr = save_expr (incr);
5697 if (BYTES_BIG_ENDIAN && size < rsize)
5699 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5700 build_int_2 (rsize - size, 0)));
5702 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5703 build_int_2 (rsize, 0)));
5705 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5706 TREE_SIDE_EFFECTS (incr) = 1;
5707 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5709 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5711 /* If the address isn't aligned properly for the type,
5712 we may need to copy to a temporary.
5713 FIXME: This is inefficient. Usually we can do this
5716 && TYPE_ALIGN (type) > BITS_PER_WORD
5719 /* FIXME: We really need to specify that the temporary is live
5720 for the whole function because expand_builtin_va_arg wants
5721 the alias set to be get_varargs_alias_set (), but in this
5722 case the alias set is that for TYPE and if the memory gets
5723 reused it will be reused with alias set TYPE. */
5724 rtx tmp = assign_temp (type, 0, 1, 0);
5727 addr_rtx = force_reg (Pmode, addr_rtx);
5728 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5729 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5730 set_mem_align (addr_rtx, BITS_PER_WORD);
5731 tmp = shallow_copy_rtx (tmp);
5732 PUT_MODE (tmp, BLKmode);
5733 set_mem_alias_set (tmp, 0);
5735 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5737 if (dest_addr != NULL_RTX)
5738 addr_rtx = dest_addr;
5740 addr_rtx = XCEXP (tmp, 0, MEM);
5745 addr_rtx = force_reg (Pmode, addr_rtx);
5746 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5747 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5753 /* Return the string to output a conditional branch to LABEL, which is
5754 the operand number of the label. OP is the conditional expression.
5755 XEXP (OP, 0) is assumed to be a condition code register (integer or
5756 floating point) and its mode specifies what kind of comparison we made.
5758 REVERSED is nonzero if we should reverse the sense of the comparison.
5760 ANNUL is nonzero if we should generate an annulling branch.
5762 NOOP is nonzero if we have to follow this branch by a noop.
5764 INSN, if set, is the insn. */
5767 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5770 static char string[50];
5771 enum rtx_code code = GET_CODE (op);
5772 rtx cc_reg = XEXP (op, 0);
5773 enum machine_mode mode = GET_MODE (cc_reg);
5774 const char *labelno, *branch;
5775 int spaces = 8, far;
5778 /* v9 branches are limited to +-1MB. If it is too far away,
5791 fbne,a,pn %fcc2, .LC29
5799 far = get_attr_length (insn) >= 3;
5802 /* Reversal of FP compares takes care -- an ordered compare
5803 becomes an unordered compare and vice versa. */
5804 if (mode == CCFPmode || mode == CCFPEmode)
5805 code = reverse_condition_maybe_unordered (code);
5807 code = reverse_condition (code);
5810 /* Start by writing the branch condition. */
5811 if (mode == CCFPmode || mode == CCFPEmode)
5862 /* ??? !v9: FP branches cannot be preceded by another floating point
5863 insn. Because there is currently no concept of pre-delay slots,
5864 we can fix this only by always emitting a nop before a floating
5869 strcpy (string, "nop\n\t");
5870 strcat (string, branch);
5883 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5895 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5916 strcpy (string, branch);
5918 spaces -= strlen (branch);
5919 p = strchr (string, '\0');
5921 /* Now add the annulling, the label, and a possible noop. */
5936 if (! far && insn && INSN_ADDRESSES_SET_P ())
5938 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5939 - INSN_ADDRESSES (INSN_UID (insn)));
5940 /* Leave some instructions for "slop". */
5941 if (delta < -260000 || delta >= 260000)
5945 if (mode == CCFPmode || mode == CCFPEmode)
5947 static char v9_fcc_labelno[] = "%%fccX, ";
5948 /* Set the char indicating the number of the fcc reg to use. */
5949 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5950 labelno = v9_fcc_labelno;
5953 if (REGNO (cc_reg) == SPARC_FCC_REG)
5959 else if (mode == CCXmode || mode == CCX_NOOVmode)
5961 labelno = "%%xcc, ";
5967 labelno = "%%icc, ";
5972 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5975 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5985 strcpy (p, labelno);
5986 p = strchr (p, '\0');
5989 strcpy (p, ".+12\n\tnop\n\tb\t");
5996 /* Set the char indicating the number of the operand containing the
6001 strcpy (p, "\n\tnop");
6006 /* Emit a library call comparison between floating point X and Y.
6007 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6008 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6009 values as arguments instead of the TFmode registers themselves,
6010 that's why we cannot call emit_float_lib_cmp. */
6012 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6015 rtx slot0, slot1, result, tem, tem2;
6016 enum machine_mode mode;
6021 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6025 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6029 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6033 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6037 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6041 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6052 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6062 if (GET_CODE (x) != MEM)
6064 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6065 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6070 if (GET_CODE (y) != MEM)
6072 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6073 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6078 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6080 XEXP (slot0, 0), Pmode,
6081 XEXP (slot1, 0), Pmode);
6087 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6089 x, TFmode, y, TFmode);
6095 /* Immediately move the result of the libcall into a pseudo
6096 register so reload doesn't clobber the value if it needs
6097 the return register for a spill reg. */
6098 result = gen_reg_rtx (mode);
6099 emit_move_insn (result, hard_libcall_value (mode));
6104 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6108 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6113 emit_cmp_insn (result, const1_rtx,
6114 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6117 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6120 tem = gen_reg_rtx (mode);
6122 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6124 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6125 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6129 tem = gen_reg_rtx (mode);
6131 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6133 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6134 tem2 = gen_reg_rtx (mode);
6136 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6138 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6139 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6145 /* Generate an unsigned DImode to FP conversion. This is the same code
6146 optabs would emit if we didn't have TFmode patterns. */
6149 sparc_emit_floatunsdi (rtx *operands)
6151 rtx neglab, donelab, i0, i1, f0, in, out;
6152 enum machine_mode mode;
6155 in = force_reg (DImode, operands[1]);
6156 mode = GET_MODE (out);
6157 neglab = gen_label_rtx ();
6158 donelab = gen_label_rtx ();
6159 i0 = gen_reg_rtx (DImode);
6160 i1 = gen_reg_rtx (DImode);
6161 f0 = gen_reg_rtx (mode);
6163 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6165 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6166 emit_jump_insn (gen_jump (donelab));
6169 emit_label (neglab);
6171 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6172 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6173 emit_insn (gen_iordi3 (i0, i0, i1));
6174 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6175 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6177 emit_label (donelab);
6180 /* Return the string to output a conditional branch to LABEL, testing
6181 register REG. LABEL is the operand number of the label; REG is the
6182 operand number of the reg. OP is the conditional expression. The mode
6183 of REG says what kind of comparison we made.
6185 REVERSED is nonzero if we should reverse the sense of the comparison.
6187 ANNUL is nonzero if we should generate an annulling branch.
6189 NOOP is nonzero if we have to follow this branch by a noop. */
6192 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6193 int annul, int noop, rtx insn)
6195 static char string[50];
6196 enum rtx_code code = GET_CODE (op);
6197 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6202 /* branch on register are limited to +-128KB. If it is too far away,
6215 brgez,a,pn %o1, .LC29
6221 ba,pt %xcc, .LC29 */
6223 far = get_attr_length (insn) >= 3;
6225 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6227 code = reverse_condition (code);
6229 /* Only 64 bit versions of these instructions exist. */
6233 /* Start by writing the branch condition. */
6238 strcpy (string, "brnz");
6242 strcpy (string, "brz");
6246 strcpy (string, "brgez");
6250 strcpy (string, "brlz");
6254 strcpy (string, "brlez");
6258 strcpy (string, "brgz");
6265 p = strchr (string, '\0');
6267 /* Now add the annulling, reg, label, and nop. */
6274 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6277 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6282 *p = p < string + 8 ? '\t' : ' ';
6290 int veryfar = 1, delta;
6292 if (INSN_ADDRESSES_SET_P ())
6294 delta = (INSN_ADDRESSES (INSN_UID (dest))
6295 - INSN_ADDRESSES (INSN_UID (insn)));
6296 /* Leave some instructions for "slop". */
6297 if (delta >= -260000 && delta < 260000)
6301 strcpy (p, ".+12\n\tnop\n\t");
6312 strcpy (p, "ba,pt\t%%xcc, ");
6322 strcpy (p, "\n\tnop");
6327 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6328 Such instructions cannot be used in the delay slot of return insn on v9.
6329 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6333 epilogue_renumber (register rtx *where, int test)
6335 register const char *fmt;
6337 register enum rtx_code code;
6342 code = GET_CODE (*where);
6347 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6349 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6350 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6358 /* Do not replace the frame pointer with the stack pointer because
6359 it can cause the delayed instruction to load below the stack.
6360 This occurs when instructions like:
6362 (set (reg/i:SI 24 %i0)
6363 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6364 (const_int -20 [0xffffffec])) 0))
6366 are in the return delayed slot. */
6368 if (GET_CODE (XEXP (*where, 0)) == REG
6369 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6370 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6371 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6376 if (SPARC_STACK_BIAS
6377 && GET_CODE (XEXP (*where, 0)) == REG
6378 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6386 fmt = GET_RTX_FORMAT (code);
6388 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6393 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6394 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6397 else if (fmt[i] == 'e'
6398 && epilogue_renumber (&(XEXP (*where, i)), test))
6404 /* Leaf functions and non-leaf functions have different needs. */
6407 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6410 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6412 static const int *const reg_alloc_orders[] = {
6413 reg_leaf_alloc_order,
6414 reg_nonleaf_alloc_order};
6417 order_regs_for_local_alloc (void)
6419 static int last_order_nonleaf = 1;
6421 if (regs_ever_live[15] != last_order_nonleaf)
6423 last_order_nonleaf = !last_order_nonleaf;
6424 memcpy ((char *) reg_alloc_order,
6425 (const char *) reg_alloc_orders[last_order_nonleaf],
6426 FIRST_PSEUDO_REGISTER * sizeof (int));
6430 /* Return 1 if REG and MEM are legitimate enough to allow the various
6431 mem<-->reg splits to be run. */
6434 sparc_splitdi_legitimate (rtx reg, rtx mem)
6436 /* Punt if we are here by mistake. */
6437 if (! reload_completed)
6440 /* We must have an offsettable memory reference. */
6441 if (! offsettable_memref_p (mem))
6444 /* If we have legitimate args for ldd/std, we do not want
6445 the split to happen. */
6446 if ((REGNO (reg) % 2) == 0
6447 && mem_min_alignment (mem, 8))
6454 /* Return 1 if x and y are some kind of REG and they refer to
6455 different hard registers. This test is guaranteed to be
6456 run after reload. */
6459 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6461 if (GET_CODE (x) != REG)
6463 if (GET_CODE (y) != REG)
6465 if (REGNO (x) == REGNO (y))
6470 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6471 This makes them candidates for using ldd and std insns.
6473 Note reg1 and reg2 *must* be hard registers. */
6476 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6478 /* We might have been passed a SUBREG. */
6479 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6482 if (REGNO (reg1) % 2 != 0)
6485 /* Integer ldd is deprecated in SPARC V9 */
6486 if (TARGET_V9 && REGNO (reg1) < 32)
6489 return (REGNO (reg1) == REGNO (reg2) - 1);
6492 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6495 This can only happen when addr1 and addr2, the addresses in mem1
6496 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6497 addr1 must also be aligned on a 64-bit boundary.
6499 Also iff dependent_reg_rtx is not null it should not be used to
6500 compute the address for mem1, i.e. we cannot optimize a sequence
6512 But, note that the transformation from:
6517 is perfectly fine. Thus, the peephole2 patterns always pass us
6518 the destination register of the first load, never the second one.
6520 For stores we don't have a similar problem, so dependent_reg_rtx is
6524 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6530 /* The mems cannot be volatile. */
6531 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6534 /* MEM1 should be aligned on a 64-bit boundary. */
6535 if (MEM_ALIGN (mem1) < 64)
6538 addr1 = XEXP (mem1, 0);
6539 addr2 = XEXP (mem2, 0);
6541 /* Extract a register number and offset (if used) from the first addr. */
6542 if (GET_CODE (addr1) == PLUS)
6544 /* If not a REG, return zero. */
6545 if (GET_CODE (XEXP (addr1, 0)) != REG)
6549 reg1 = REGNO (XEXP (addr1, 0));
6550 /* The offset must be constant! */
6551 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6553 offset1 = INTVAL (XEXP (addr1, 1));
6556 else if (GET_CODE (addr1) != REG)
6560 reg1 = REGNO (addr1);
6561 /* This was a simple (mem (reg)) expression. Offset is 0. */
6565 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6566 if (GET_CODE (addr2) != PLUS)
6569 if (GET_CODE (XEXP (addr2, 0)) != REG
6570 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6573 if (reg1 != REGNO (XEXP (addr2, 0)))
6576 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6579 /* The first offset must be evenly divisible by 8 to ensure the
6580 address is 64 bit aligned. */
6581 if (offset1 % 8 != 0)
6584 /* The offset for the second addr must be 4 more than the first addr. */
6585 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6588 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6593 /* Return 1 if reg is a pseudo, or is the first register in
6594 a hard register pair. This makes it a candidate for use in
6595 ldd and std insns. */
6598 register_ok_for_ldd (rtx reg)
6600 /* We might have been passed a SUBREG. */
6601 if (GET_CODE (reg) != REG)
6604 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6605 return (REGNO (reg) % 2 == 0);
6610 /* Print operand X (an rtx) in assembler syntax to file FILE.
6611 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6612 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6615 print_operand (FILE *file, rtx x, int code)
6620 /* Output a 'nop' if there's nothing for the delay slot. */
6621 if (dbr_sequence_length () == 0)
6622 fputs ("\n\t nop", file);
6625 /* Output an annul flag if there's nothing for the delay slot and we
6626 are optimizing. This is always used with '(' below. */
6627 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6628 this is a dbx bug. So, we only do this when optimizing. */
6629 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6630 Always emit a nop in case the next instruction is a branch. */
6631 if (dbr_sequence_length () == 0
6632 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6636 /* Output a 'nop' if there's nothing for the delay slot and we are
6637 not optimizing. This is always used with '*' above. */
6638 if (dbr_sequence_length () == 0
6639 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6640 fputs ("\n\t nop", file);
6643 /* Output the Embedded Medium/Anywhere code model base register. */
6644 fputs (EMBMEDANY_BASE_REG, file);
6647 /* Print out what we are using as the frame pointer. This might
6648 be %fp, or might be %sp+offset. */
6649 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6650 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6653 /* Print some local dynamic TLS name. */
6654 assemble_name (file, get_some_local_dynamic_name ());
6657 /* Adjust the operand to take into account a RESTORE operation. */
6658 if (GET_CODE (x) == CONST_INT)
6660 else if (GET_CODE (x) != REG)
6661 output_operand_lossage ("invalid %%Y operand");
6662 else if (REGNO (x) < 8)
6663 fputs (reg_names[REGNO (x)], file);
6664 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6665 fputs (reg_names[REGNO (x)-16], file);
6667 output_operand_lossage ("invalid %%Y operand");
6670 /* Print out the low order register name of a register pair. */
6671 if (WORDS_BIG_ENDIAN)
6672 fputs (reg_names[REGNO (x)+1], file);
6674 fputs (reg_names[REGNO (x)], file);
6677 /* Print out the high order register name of a register pair. */
6678 if (WORDS_BIG_ENDIAN)
6679 fputs (reg_names[REGNO (x)], file);
6681 fputs (reg_names[REGNO (x)+1], file);
6684 /* Print out the second register name of a register pair or quad.
6685 I.e., R (%o0) => %o1. */
6686 fputs (reg_names[REGNO (x)+1], file);
6689 /* Print out the third register name of a register quad.
6690 I.e., S (%o0) => %o2. */
6691 fputs (reg_names[REGNO (x)+2], file);
6694 /* Print out the fourth register name of a register quad.
6695 I.e., T (%o0) => %o3. */
6696 fputs (reg_names[REGNO (x)+3], file);
6699 /* Print a condition code register. */
6700 if (REGNO (x) == SPARC_ICC_REG)
6702 /* We don't handle CC[X]_NOOVmode because they're not supposed
6704 if (GET_MODE (x) == CCmode)
6705 fputs ("%icc", file);
6706 else if (GET_MODE (x) == CCXmode)
6707 fputs ("%xcc", file);
6712 /* %fccN register */
6713 fputs (reg_names[REGNO (x)], file);
6716 /* Print the operand's address only. */
6717 output_address (XEXP (x, 0));
6720 /* In this case we need a register. Use %g0 if the
6721 operand is const0_rtx. */
6723 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6725 fputs ("%g0", file);
6732 switch (GET_CODE (x))
6734 case IOR: fputs ("or", file); break;
6735 case AND: fputs ("and", file); break;
6736 case XOR: fputs ("xor", file); break;
6737 default: output_operand_lossage ("invalid %%A operand");
6742 switch (GET_CODE (x))
6744 case IOR: fputs ("orn", file); break;
6745 case AND: fputs ("andn", file); break;
6746 case XOR: fputs ("xnor", file); break;
6747 default: output_operand_lossage ("invalid %%B operand");
6751 /* These are used by the conditional move instructions. */
6755 enum rtx_code rc = GET_CODE (x);
6759 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6760 if (mode == CCFPmode || mode == CCFPEmode)
6761 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6763 rc = reverse_condition (GET_CODE (x));
6767 case NE: fputs ("ne", file); break;
6768 case EQ: fputs ("e", file); break;
6769 case GE: fputs ("ge", file); break;
6770 case GT: fputs ("g", file); break;
6771 case LE: fputs ("le", file); break;
6772 case LT: fputs ("l", file); break;
6773 case GEU: fputs ("geu", file); break;
6774 case GTU: fputs ("gu", file); break;
6775 case LEU: fputs ("leu", file); break;
6776 case LTU: fputs ("lu", file); break;
6777 case LTGT: fputs ("lg", file); break;
6778 case UNORDERED: fputs ("u", file); break;
6779 case ORDERED: fputs ("o", file); break;
6780 case UNLT: fputs ("ul", file); break;
6781 case UNLE: fputs ("ule", file); break;
6782 case UNGT: fputs ("ug", file); break;
6783 case UNGE: fputs ("uge", file); break;
6784 case UNEQ: fputs ("ue", file); break;
6785 default: output_operand_lossage (code == 'c'
6786 ? "invalid %%c operand"
6787 : "invalid %%C operand");
6792 /* These are used by the movr instruction pattern. */
6796 enum rtx_code rc = (code == 'd'
6797 ? reverse_condition (GET_CODE (x))
6801 case NE: fputs ("ne", file); break;
6802 case EQ: fputs ("e", file); break;
6803 case GE: fputs ("gez", file); break;
6804 case LT: fputs ("lz", file); break;
6805 case LE: fputs ("lez", file); break;
6806 case GT: fputs ("gz", file); break;
6807 default: output_operand_lossage (code == 'd'
6808 ? "invalid %%d operand"
6809 : "invalid %%D operand");
6816 /* Print a sign-extended character. */
6817 int i = trunc_int_for_mode (INTVAL (x), QImode);
6818 fprintf (file, "%d", i);
6823 /* Operand must be a MEM; write its address. */
6824 if (GET_CODE (x) != MEM)
6825 output_operand_lossage ("invalid %%f operand");
6826 output_address (XEXP (x, 0));
6831 /* Print a sign-extended 32-bit value. */
6833 if (GET_CODE(x) == CONST_INT)
6835 else if (GET_CODE(x) == CONST_DOUBLE)
6836 i = CONST_DOUBLE_LOW (x);
6839 output_operand_lossage ("invalid %%s operand");
6842 i = trunc_int_for_mode (i, SImode);
6843 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6848 /* Do nothing special. */
6852 /* Undocumented flag. */
6853 output_operand_lossage ("invalid operand output code");
6856 if (GET_CODE (x) == REG)
6857 fputs (reg_names[REGNO (x)], file);
6858 else if (GET_CODE (x) == MEM)
6861 /* Poor Sun assembler doesn't understand absolute addressing. */
6862 if (CONSTANT_P (XEXP (x, 0)))
6863 fputs ("%g0+", file);
6864 output_address (XEXP (x, 0));
6867 else if (GET_CODE (x) == HIGH)
6869 fputs ("%hi(", file);
6870 output_addr_const (file, XEXP (x, 0));
6873 else if (GET_CODE (x) == LO_SUM)
6875 print_operand (file, XEXP (x, 0), 0);
6876 if (TARGET_CM_MEDMID)
6877 fputs ("+%l44(", file);
6879 fputs ("+%lo(", file);
6880 output_addr_const (file, XEXP (x, 1));
6883 else if (GET_CODE (x) == CONST_DOUBLE
6884 && (GET_MODE (x) == VOIDmode
6885 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6887 if (CONST_DOUBLE_HIGH (x) == 0)
6888 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6889 else if (CONST_DOUBLE_HIGH (x) == -1
6890 && CONST_DOUBLE_LOW (x) < 0)
6891 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6893 output_operand_lossage ("long long constant not a valid immediate operand");
6895 else if (GET_CODE (x) == CONST_DOUBLE)
6896 output_operand_lossage ("floating point constant not a valid immediate operand");
6897 else { output_addr_const (file, x); }
6900 /* Target hook for assembling integer objects. The sparc version has
6901 special handling for aligned DI-mode objects. */
6904 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
6906 /* ??? We only output .xword's for symbols and only then in environments
6907 where the assembler can handle them. */
6908 if (aligned_p && size == 8
6909 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6913 assemble_integer_with_op ("\t.xword\t", x);
6918 assemble_aligned_integer (4, const0_rtx);
6919 assemble_aligned_integer (4, x);
6923 return default_assemble_integer (x, size, aligned_p);
6926 /* Return the value of a code used in the .proc pseudo-op that says
6927 what kind of result this function returns. For non-C types, we pick
6928 the closest C type. */
6930 #ifndef SHORT_TYPE_SIZE
6931 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6934 #ifndef INT_TYPE_SIZE
6935 #define INT_TYPE_SIZE BITS_PER_WORD
6938 #ifndef LONG_TYPE_SIZE
6939 #define LONG_TYPE_SIZE BITS_PER_WORD
6942 #ifndef LONG_LONG_TYPE_SIZE
6943 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6946 #ifndef FLOAT_TYPE_SIZE
6947 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6950 #ifndef DOUBLE_TYPE_SIZE
6951 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6954 #ifndef LONG_DOUBLE_TYPE_SIZE
6955 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6959 sparc_type_code (register tree type)
6961 register unsigned long qualifiers = 0;
6962 register unsigned shift;
6964 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6965 setting more, since some assemblers will give an error for this. Also,
6966 we must be careful to avoid shifts of 32 bits or more to avoid getting
6967 unpredictable results. */
6969 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6971 switch (TREE_CODE (type))
6977 qualifiers |= (3 << shift);
6982 qualifiers |= (2 << shift);
6986 case REFERENCE_TYPE:
6988 qualifiers |= (1 << shift);
6992 return (qualifiers | 8);
6995 case QUAL_UNION_TYPE:
6996 return (qualifiers | 9);
6999 return (qualifiers | 10);
7002 return (qualifiers | 16);
7005 /* If this is a range type, consider it to be the underlying
7007 if (TREE_TYPE (type) != 0)
7010 /* Carefully distinguish all the standard types of C,
7011 without messing up if the language is not C. We do this by
7012 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7013 look at both the names and the above fields, but that's redundant.
7014 Any type whose size is between two C types will be considered
7015 to be the wider of the two types. Also, we do not have a
7016 special code to use for "long long", so anything wider than
7017 long is treated the same. Note that we can't distinguish
7018 between "int" and "long" in this code if they are the same
7019 size, but that's fine, since neither can the assembler. */
7021 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7022 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7024 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7025 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7027 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7028 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7031 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7034 /* If this is a range type, consider it to be the underlying
7036 if (TREE_TYPE (type) != 0)
7039 /* Carefully distinguish all the standard types of C,
7040 without messing up if the language is not C. */
7042 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7043 return (qualifiers | 6);
7046 return (qualifiers | 7);
7048 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7049 /* ??? We need to distinguish between double and float complex types,
7050 but I don't know how yet because I can't reach this code from
7051 existing front-ends. */
7052 return (qualifiers | 7); /* Who knows? */
7054 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7055 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7056 case FILE_TYPE: /* GNU Pascal FILE type. */
7057 case SET_TYPE: /* GNU Pascal SET type. */
7058 case LANG_TYPE: /* ? */
7062 abort (); /* Not a type! */
7069 /* Nested function support. */
7071 /* Emit RTL insns to initialize the variable parts of a trampoline.
7072 FNADDR is an RTX for the address of the function's pure code.
7073 CXT is an RTX for the static chain value for the function.
7075 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7076 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7077 (to store insns). This is a bit excessive. Perhaps a different
7078 mechanism would be better here.
7080 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7083 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7085 /* SPARC 32 bit trampoline:
7088 sethi %hi(static), %g2
7090 or %g2, %lo(static), %g2
7092 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7093 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7095 #ifdef TRANSFER_FROM_TRAMPOLINE
7096 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7097 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7101 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7102 expand_binop (SImode, ior_optab,
7103 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7104 size_int (10), 0, 1),
7105 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7106 NULL_RTX, 1, OPTAB_DIRECT));
7109 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7110 expand_binop (SImode, ior_optab,
7111 expand_shift (RSHIFT_EXPR, SImode, cxt,
7112 size_int (10), 0, 1),
7113 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7114 NULL_RTX, 1, OPTAB_DIRECT));
7117 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7118 expand_binop (SImode, ior_optab,
7119 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7120 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7121 NULL_RTX, 1, OPTAB_DIRECT));
7124 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7125 expand_binop (SImode, ior_optab,
7126 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7127 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7128 NULL_RTX, 1, OPTAB_DIRECT));
7130 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7131 aligned on a 16 byte boundary so one flush clears it all. */
7132 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7133 if (sparc_cpu != PROCESSOR_ULTRASPARC
7134 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7135 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7136 plus_constant (tramp, 8)))));
7139 /* The 64 bit version is simpler because it makes more sense to load the
7140 values as "immediate" data out of the trampoline. It's also easier since
7141 we can read the PC without clobbering a register. */
7144 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7146 #ifdef TRANSFER_FROM_TRAMPOLINE
7147 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7148 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7159 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7160 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7161 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7162 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7163 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7164 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7165 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7166 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7167 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7168 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7169 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7171 if (sparc_cpu != PROCESSOR_ULTRASPARC
7172 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7173 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7176 /* Subroutines to support a flat (single) register window calling
7179 /* Single-register window sparc stack frames look like:
7181 Before call After call
7182 +-----------------------+ +-----------------------+
7184 mem | caller's temps. | | caller's temps. |
7186 +-----------------------+ +-----------------------+
7188 | arguments on stack. | | arguments on stack. |
7190 +-----------------------+FP+92->+-----------------------+
7191 | 6 words to save | | 6 words to save |
7192 | arguments passed | | arguments passed |
7193 | in registers, even | | in registers, even |
7194 | if not passed. | | if not passed. |
7195 SP+68->+-----------------------+FP+68->+-----------------------+
7196 | 1 word struct addr | | 1 word struct addr |
7197 +-----------------------+FP+64->+-----------------------+
7199 | 16 word reg save area | | 16 word reg save area |
7201 SP->+-----------------------+ FP->+-----------------------+
7203 | fp/alu reg moves |
7204 FP-16->+-----------------------+
7208 +-----------------------+
7210 | fp register save |
7212 +-----------------------+
7214 | gp register save |
7216 +-----------------------+
7218 | alloca allocations |
7220 +-----------------------+
7222 | arguments on stack |
7224 SP+92->+-----------------------+
7226 | arguments passed |
7227 | in registers, even |
7228 low | if not passed. |
7229 memory SP+68->+-----------------------+
7230 | 1 word struct addr |
7231 SP+64->+-----------------------+
7233 I 16 word reg save area |
7235 SP->+-----------------------+ */
7237 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7238 save masks, and offsets for the current function. */
7240 struct sparc_frame_info
7242 unsigned long total_size; /* # bytes that the entire frame takes up. */
7243 unsigned long var_size; /* # bytes that variables take up. */
7244 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7245 unsigned long extra_size; /* # bytes of extra gunk. */
7246 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7247 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7248 unsigned long gmask; /* Mask of saved gp registers. */
7249 unsigned long fmask; /* Mask of saved fp registers. */
7250 unsigned long reg_offset; /* Offset from new sp to store regs. */
7251 int initialized; /* Nonzero if frame size already calculated. */
7254 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7255 struct sparc_frame_info current_frame_info;
7257 /* Zero structure to initialize current_frame_info. */
7258 struct sparc_frame_info zero_frame_info;
7260 #define RETURN_ADDR_REGNUM 15
7261 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7262 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7264 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7267 sparc_flat_must_save_register_p (int regno)
7269 /* General case: call-saved registers live at some point. */
7270 if (!call_used_regs[regno] && regs_ever_live[regno])
7273 /* Frame pointer register (%i7) if needed. */
7274 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7277 /* PIC register (%l7) if needed. */
7278 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7279 && flag_pic && current_function_uses_pic_offset_table)
7282 /* Return address register (%o7) if needed. */
7283 if (regno == RETURN_ADDR_REGNUM
7284 && (regs_ever_live[RETURN_ADDR_REGNUM]
7285 /* When the PIC offset table is used, the PIC register
7286 is set by using a bare call that clobbers %o7. */
7287 || (flag_pic && current_function_uses_pic_offset_table)))
7293 /* Return the bytes needed to compute the frame pointer from the current
7297 sparc_flat_compute_frame_size (int size)
7298 /* # of var. bytes allocated. */
7301 unsigned long total_size; /* # bytes that the entire frame takes up. */
7302 unsigned long var_size; /* # bytes that variables take up. */
7303 unsigned long args_size; /* # bytes that outgoing arguments take up. */
7304 unsigned long extra_size; /* # extra bytes. */
7305 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
7306 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
7307 unsigned long gmask; /* Mask of saved gp registers. */
7308 unsigned long fmask; /* Mask of saved fp registers. */
7309 unsigned long reg_offset; /* Offset to register save area. */
7310 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7312 /* This is the size of the 16 word reg save area, 1 word struct addr
7313 area, and 4 word fp/alu register copy area. */
7314 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7324 if (!leaf_function_p ())
7326 /* Also include the size needed for the 6 parameter registers. */
7327 args_size = current_function_outgoing_args_size + 24;
7329 total_size = var_size + args_size;
7331 /* Calculate space needed for gp registers. */
7332 for (regno = 1; regno <= 31; regno++)
7334 if (sparc_flat_must_save_register_p (regno))
7336 /* If we need to save two regs in a row, ensure there's room to bump
7337 up the address to align it to a doubleword boundary. */
7338 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7340 if (gp_reg_size % 8 != 0)
7342 gp_reg_size += 2 * UNITS_PER_WORD;
7343 gmask |= 3 << regno;
7349 gp_reg_size += UNITS_PER_WORD;
7350 gmask |= 1 << regno;
7355 /* Calculate space needed for fp registers. */
7356 for (regno = 32; regno <= 63; regno++)
7358 if (regs_ever_live[regno] && !call_used_regs[regno])
7360 fp_reg_size += UNITS_PER_WORD;
7361 fmask |= 1 << (regno - 32);
7368 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7369 /* Ensure save area is 8 byte aligned if we need it. */
7371 if (need_aligned_p && n != 0)
7373 total_size += 8 - n;
7374 reg_offset += 8 - n;
7376 total_size += gp_reg_size + fp_reg_size;
7379 /* If we must allocate a stack frame at all, we must also allocate
7380 room for register window spillage, so as to be binary compatible
7381 with libraries and operating systems that do not use -mflat. */
7383 total_size += extra_size;
7387 total_size = SPARC_STACK_ALIGN (total_size);
7389 /* Save other computed information. */
7390 current_frame_info.total_size = total_size;
7391 current_frame_info.var_size = var_size;
7392 current_frame_info.args_size = args_size;
7393 current_frame_info.extra_size = extra_size;
7394 current_frame_info.gp_reg_size = gp_reg_size;
7395 current_frame_info.fp_reg_size = fp_reg_size;
7396 current_frame_info.gmask = gmask;
7397 current_frame_info.fmask = fmask;
7398 current_frame_info.reg_offset = reg_offset;
7399 current_frame_info.initialized = reload_completed;
7401 /* Ok, we're done. */
7405 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7408 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7409 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7410 [BASE_REG+OFFSET] will always be a valid address.
7412 WORD_OP is either "st" for save, "ld" for restore.
7413 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7416 sparc_flat_save_restore (FILE *file, const char *base_reg,
7417 unsigned int offset, long unsigned int gmask,
7418 long unsigned int fmask, const char *word_op,
7419 const char *doubleword_op,
7420 long unsigned int base_offset)
7424 if (gmask == 0 && fmask == 0)
7427 /* Save registers starting from high to low. We've already saved the
7428 previous frame pointer and previous return address for the debugger's
7429 sake. The debugger allows us to not need a nop in the epilog if at least
7430 one register is reloaded in addition to return address. */
7434 for (regno = 1; regno <= 31; regno++)
7436 if ((gmask & (1L << regno)) != 0)
7438 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7440 /* We can save two registers in a row. If we're not at a
7441 double word boundary, move to one.
7442 sparc_flat_compute_frame_size ensures there's room to do
7444 if (offset % 8 != 0)
7445 offset += UNITS_PER_WORD;
7447 if (word_op[0] == 's')
7449 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7450 doubleword_op, reg_names[regno],
7452 if (dwarf2out_do_frame ())
7454 char *l = dwarf2out_cfi_label ();
7455 dwarf2out_reg_save (l, regno, offset + base_offset);
7457 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7461 fprintf (file, "\t%s\t[%s+%d], %s\n",
7462 doubleword_op, base_reg, offset,
7465 offset += 2 * UNITS_PER_WORD;
7470 if (word_op[0] == 's')
7472 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7473 word_op, reg_names[regno],
7475 if (dwarf2out_do_frame ())
7476 dwarf2out_reg_save ("", regno, offset + base_offset);
7479 fprintf (file, "\t%s\t[%s+%d], %s\n",
7480 word_op, base_reg, offset, reg_names[regno]);
7482 offset += UNITS_PER_WORD;
7490 for (regno = 32; regno <= 63; regno++)
7492 if ((fmask & (1L << (regno - 32))) != 0)
7494 if (word_op[0] == 's')
7496 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7497 word_op, reg_names[regno],
7499 if (dwarf2out_do_frame ())
7500 dwarf2out_reg_save ("", regno, offset + base_offset);
7503 fprintf (file, "\t%s\t[%s+%d], %s\n",
7504 word_op, base_reg, offset, reg_names[regno]);
7506 offset += UNITS_PER_WORD;
7512 /* Set up the stack and frame (if desired) for the function. */
7515 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7517 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7518 unsigned long gmask = current_frame_info.gmask;
7520 sparc_output_scratch_registers (file);
7522 /* This is only for the human reader. */
7523 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7524 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7526 current_frame_info.var_size,
7527 current_frame_info.gp_reg_size / 4,
7528 current_frame_info.fp_reg_size / 4,
7529 current_function_outgoing_args_size,
7530 current_frame_info.extra_size);
7532 size = SPARC_STACK_ALIGN (size);
7533 size = (! current_frame_info.initialized
7534 ? sparc_flat_compute_frame_size (size)
7535 : current_frame_info.total_size);
7537 /* These cases shouldn't happen. Catch them now. */
7538 if (size == 0 && (gmask || current_frame_info.fmask))
7541 /* Allocate our stack frame by decrementing %sp.
7542 At present, the only algorithm gdb can use to determine if this is a
7543 flat frame is if we always set %i7 if we set %sp. This can be optimized
7544 in the future by putting in some sort of debugging information that says
7545 this is a `flat' function. However, there is still the case of debugging
7546 code without such debugging information (including cases where most fns
7547 have such info, but there is one that doesn't). So, always do this now
7548 so we don't get a lot of code out there that gdb can't handle.
7549 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7550 distinguish us from a non-flat function but there won't (and shouldn't)
7551 be any differences anyway. The return pc is saved (if necessary) right
7552 after %i7 so gdb won't have to look too far to find it. */
7555 unsigned int reg_offset = current_frame_info.reg_offset;
7556 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7557 static const char *const t1_str = "%g1";
7559 /* Things get a little tricky if local variables take up more than ~4096
7560 bytes and outgoing arguments take up more than ~4096 bytes. When that
7561 happens, the register save area can't be accessed from either end of
7562 the frame. Handle this by decrementing %sp to the start of the gp
7563 register save area, save the regs, update %i7, and then set %sp to its
7564 final value. Given that we only have one scratch register to play
7565 with it is the cheapest solution, and it helps gdb out as it won't
7566 slow down recognition of flat functions.
7567 Don't change the order of insns emitted here without checking with
7568 the gdb folk first. */
7570 /* Is the entire register save area offsettable from %sp? */
7571 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7575 fprintf (file, "\tadd\t%s, %d, %s\n",
7576 sp_str, (int) -size, sp_str);
7577 if (gmask & HARD_FRAME_POINTER_MASK)
7579 fprintf (file, "\tst\t%s, [%s+%d]\n",
7580 fp_str, sp_str, reg_offset);
7581 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7582 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7588 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7589 ", %s\n\tsub\t%s, %s, %s\n",
7590 size, t1_str, sp_str, t1_str, sp_str);
7591 if (gmask & HARD_FRAME_POINTER_MASK)
7593 fprintf (file, "\tst\t%s, [%s+%d]\n",
7594 fp_str, sp_str, reg_offset);
7595 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7596 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7600 if (dwarf2out_do_frame ())
7602 char *l = dwarf2out_cfi_label ();
7603 if (gmask & HARD_FRAME_POINTER_MASK)
7605 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7606 reg_offset - 4 - size);
7607 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7610 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7612 if (gmask & RETURN_ADDR_MASK)
7614 fprintf (file, "\tst\t%s, [%s+%d]\n",
7615 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7616 if (dwarf2out_do_frame ())
7617 dwarf2out_return_save ("", reg_offset - size);
7620 sparc_flat_save_restore (file, sp_str, reg_offset,
7621 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7622 current_frame_info.fmask,
7623 "st", "std", -size);
7627 /* Subtract %sp in two steps, but make sure there is always a
7628 64 byte register save area, and %sp is properly aligned. */
7629 /* Amount to decrement %sp by, the first time. */
7630 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7631 /* Offset to register save area from %sp. */
7632 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7636 fprintf (file, "\tadd\t%s, %d, %s\n",
7637 sp_str, (int) -size1, sp_str);
7638 if (gmask & HARD_FRAME_POINTER_MASK)
7640 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7641 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7642 fp_str, ASM_COMMENT_START);
7648 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7649 ", %s\n\tsub\t%s, %s, %s\n",
7650 size1, t1_str, sp_str, t1_str, sp_str);
7651 if (gmask & HARD_FRAME_POINTER_MASK)
7653 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7654 fp_str, sp_str, (int) offset, sp_str, t1_str,
7655 fp_str, ASM_COMMENT_START);
7659 if (dwarf2out_do_frame ())
7661 char *l = dwarf2out_cfi_label ();
7662 if (gmask & HARD_FRAME_POINTER_MASK)
7664 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7665 offset - 4 - size1);
7666 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7669 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7671 if (gmask & RETURN_ADDR_MASK)
7673 fprintf (file, "\tst\t%s, [%s+%d]\n",
7674 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7675 if (dwarf2out_do_frame ())
7676 /* offset - size1 == reg_offset - size
7677 if reg_offset were updated above like offset. */
7678 dwarf2out_return_save ("", offset - size1);
7681 sparc_flat_save_restore (file, sp_str, offset,
7682 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7683 current_frame_info.fmask,
7684 "st", "std", -size1);
7685 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7686 ", %s\n\tsub\t%s, %s, %s\n",
7687 size - size1, t1_str, sp_str, t1_str, sp_str);
7688 if (dwarf2out_do_frame ())
7689 if (! (gmask & HARD_FRAME_POINTER_MASK))
7690 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7694 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7697 /* Do any necessary cleanup after a function to restore stack, frame,
7701 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
7703 rtx epilogue_delay = current_function_epilogue_delay_list;
7704 int noepilogue = FALSE;
7706 /* This is only for the human reader. */
7707 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7709 /* The epilogue does not depend on any registers, but the stack
7710 registers, so we assume that if we have 1 pending nop, it can be
7711 ignored, and 2 it must be filled (2 nops occur for integer
7712 multiply and divide). */
7714 size = SPARC_STACK_ALIGN (size);
7715 size = (!current_frame_info.initialized
7716 ? sparc_flat_compute_frame_size (size)
7717 : current_frame_info.total_size);
7719 if (size == 0 && epilogue_delay == 0)
7721 rtx insn = get_last_insn ();
7723 /* If the last insn was a BARRIER, we don't have to write any code
7724 because a jump (aka return) was put there. */
7725 if (GET_CODE (insn) == NOTE)
7726 insn = prev_nonnote_insn (insn);
7727 if (insn && GET_CODE (insn) == BARRIER)
7733 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7734 unsigned HOST_WIDE_INT size1;
7735 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7736 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7737 static const char *const t1_str = "%g1";
7739 /* In the reload sequence, we don't need to fill the load delay
7740 slots for most of the loads, also see if we can fill the final
7741 delay slot if not otherwise filled by the reload sequence. */
7744 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7747 if (frame_pointer_needed)
7750 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7751 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7753 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7754 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7757 /* Is the entire register save area offsettable from %sp? */
7758 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7764 /* Restore %sp in two steps, but make sure there is always a
7765 64 byte register save area, and %sp is properly aligned. */
7766 /* Amount to increment %sp by, the first time. */
7767 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7768 /* Offset to register save area from %sp. */
7769 reg_offset = size1 - reg_offset;
7771 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC
7772 ", %s\n\tadd\t%s, %s, %s\n",
7773 size1, t1_str, sp_str, t1_str, sp_str);
7776 /* We must restore the frame pointer and return address reg first
7777 because they are treated specially by the prologue output code. */
7778 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7780 fprintf (file, "\tld\t[%s+%d], %s\n",
7781 sp_str, (int) reg_offset, fp_str);
7784 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7786 fprintf (file, "\tld\t[%s+%d], %s\n",
7787 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7791 /* Restore any remaining saved registers. */
7792 sparc_flat_save_restore (file, sp_str, reg_offset,
7793 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7794 current_frame_info.fmask,
7797 /* If we had to increment %sp in two steps, record it so the second
7798 restoration in the epilogue finishes up. */
7803 fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n",
7807 if (current_function_returns_struct)
7808 fprintf (file, "\tjmp\t%%o7+12\n");
7810 fprintf (file, "\tretl\n");
7812 /* If the only register saved is the return address, we need a
7813 nop, unless we have an instruction to put into it. Otherwise
7814 we don't since reloading multiple registers doesn't reference
7815 the register being loaded. */
7821 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7824 else if (size > 4095)
7825 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7828 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7831 fprintf (file, "\tnop\n");
7834 /* Reset state info for each function. */
7835 current_frame_info = zero_frame_info;
7837 sparc_output_deferred_case_vectors ();
7840 /* Define the number of delay slots needed for the function epilogue.
7842 On the sparc, we need a slot if either no stack has been allocated,
7843 or the only register saved is the return register. */
7846 sparc_flat_epilogue_delay_slots (void)
7848 if (!current_frame_info.initialized)
7849 (void) sparc_flat_compute_frame_size (get_frame_size ());
7851 if (current_frame_info.total_size == 0)
7857 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7858 Any single length instruction which doesn't reference the stack or frame
7862 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
7864 rtx pat = PATTERN (trial);
7866 if (get_attr_length (trial) != 1)
7869 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7870 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7876 /* Adjust the cost of a scheduling dependency. Return the new cost of
7877 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7880 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7882 enum attr_type insn_type;
7884 if (! recog_memoized (insn))
7887 insn_type = get_attr_type (insn);
7889 if (REG_NOTE_KIND (link) == 0)
7891 /* Data dependency; DEP_INSN writes a register that INSN reads some
7894 /* if a load, then the dependence must be on the memory address;
7895 add an extra "cycle". Note that the cost could be two cycles
7896 if the reg was written late in an instruction group; we ca not tell
7898 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7901 /* Get the delay only if the address of the store is the dependence. */
7902 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7904 rtx pat = PATTERN(insn);
7905 rtx dep_pat = PATTERN (dep_insn);
7907 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7908 return cost; /* This should not happen! */
7910 /* The dependency between the two instructions was on the data that
7911 is being stored. Assume that this implies that the address of the
7912 store is not dependent. */
7913 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7916 return cost + 3; /* An approximation. */
7919 /* A shift instruction cannot receive its data from an instruction
7920 in the same cycle; add a one cycle penalty. */
7921 if (insn_type == TYPE_SHIFT)
7922 return cost + 3; /* Split before cascade into shift. */
7926 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7927 INSN writes some cycles later. */
7929 /* These are only significant for the fpu unit; writing a fp reg before
7930 the fpu has finished with it stalls the processor. */
7932 /* Reusing an integer register causes no problems. */
7933 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7941 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7943 enum attr_type insn_type, dep_type;
7944 rtx pat = PATTERN(insn);
7945 rtx dep_pat = PATTERN (dep_insn);
7947 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7950 insn_type = get_attr_type (insn);
7951 dep_type = get_attr_type (dep_insn);
7953 switch (REG_NOTE_KIND (link))
7956 /* Data dependency; DEP_INSN writes a register that INSN reads some
7963 /* Get the delay iff the address of the store is the dependence. */
7964 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7967 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7974 /* If a load, then the dependence must be on the memory address. If
7975 the addresses aren't equal, then it might be a false dependency */
7976 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7978 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7979 || GET_CODE (SET_DEST (dep_pat)) != MEM
7980 || GET_CODE (SET_SRC (pat)) != MEM
7981 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7982 XEXP (SET_SRC (pat), 0)))
7990 /* Compare to branch latency is 0. There is no benefit from
7991 separating compare and branch. */
7992 if (dep_type == TYPE_COMPARE)
7994 /* Floating point compare to branch latency is less than
7995 compare to conditional move. */
7996 if (dep_type == TYPE_FPCMP)
8005 /* Anti-dependencies only penalize the fpu unit. */
8006 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8018 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8022 case PROCESSOR_SUPERSPARC:
8023 cost = supersparc_adjust_cost (insn, link, dep, cost);
8025 case PROCESSOR_HYPERSPARC:
8026 case PROCESSOR_SPARCLITE86X:
8027 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8036 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8037 int sched_verbose ATTRIBUTE_UNUSED,
8038 int max_ready ATTRIBUTE_UNUSED)
8043 sparc_use_dfa_pipeline_interface (void)
8045 if ((1 << sparc_cpu) &
8046 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8047 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8048 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8049 (1 << PROCESSOR_ULTRASPARC3)))
8055 sparc_use_sched_lookahead (void)
8057 if (sparc_cpu == PROCESSOR_ULTRASPARC
8058 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8060 if ((1 << sparc_cpu) &
8061 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8062 (1 << PROCESSOR_SPARCLITE86X)))
8068 sparc_issue_rate (void)
8075 /* Assume V9 processors are capable of at least dual-issue. */
8077 case PROCESSOR_SUPERSPARC:
8079 case PROCESSOR_HYPERSPARC:
8080 case PROCESSOR_SPARCLITE86X:
8082 case PROCESSOR_ULTRASPARC:
8083 case PROCESSOR_ULTRASPARC3:
8089 set_extends (rtx insn)
8091 register rtx pat = PATTERN (insn);
8093 switch (GET_CODE (SET_SRC (pat)))
8095 /* Load and some shift instructions zero extend. */
8098 /* sethi clears the high bits */
8100 /* LO_SUM is used with sethi. sethi cleared the high
8101 bits and the values used with lo_sum are positive */
8103 /* Store flag stores 0 or 1 */
8113 rtx op0 = XEXP (SET_SRC (pat), 0);
8114 rtx op1 = XEXP (SET_SRC (pat), 1);
8115 if (GET_CODE (op1) == CONST_INT)
8116 return INTVAL (op1) >= 0;
8117 if (GET_CODE (op0) != REG)
8119 if (sparc_check_64 (op0, insn) == 1)
8121 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8126 rtx op0 = XEXP (SET_SRC (pat), 0);
8127 rtx op1 = XEXP (SET_SRC (pat), 1);
8128 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8130 if (GET_CODE (op1) == CONST_INT)
8131 return INTVAL (op1) >= 0;
8132 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8135 return GET_MODE (SET_SRC (pat)) == SImode;
8136 /* Positive integers leave the high bits zero. */
8138 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8140 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8143 return - (GET_MODE (SET_SRC (pat)) == SImode);
8145 return sparc_check_64 (SET_SRC (pat), insn);
8151 /* We _ought_ to have only one kind per function, but... */
8152 static GTY(()) rtx sparc_addr_diff_list;
8153 static GTY(()) rtx sparc_addr_list;
8156 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8158 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8160 sparc_addr_diff_list
8161 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8163 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8167 sparc_output_addr_vec (rtx vec)
8169 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8170 int idx, vlen = XVECLEN (body, 0);
8172 #ifdef ASM_OUTPUT_ADDR_VEC_START
8173 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8176 #ifdef ASM_OUTPUT_CASE_LABEL
8177 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8180 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8183 for (idx = 0; idx < vlen; idx++)
8185 ASM_OUTPUT_ADDR_VEC_ELT
8186 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8189 #ifdef ASM_OUTPUT_ADDR_VEC_END
8190 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8195 sparc_output_addr_diff_vec (rtx vec)
8197 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8198 rtx base = XEXP (XEXP (body, 0), 0);
8199 int idx, vlen = XVECLEN (body, 1);
8201 #ifdef ASM_OUTPUT_ADDR_VEC_START
8202 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8205 #ifdef ASM_OUTPUT_CASE_LABEL
8206 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8209 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8212 for (idx = 0; idx < vlen; idx++)
8214 ASM_OUTPUT_ADDR_DIFF_ELT
8217 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8218 CODE_LABEL_NUMBER (base));
8221 #ifdef ASM_OUTPUT_ADDR_VEC_END
8222 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8227 sparc_output_deferred_case_vectors (void)
8232 if (sparc_addr_list == NULL_RTX
8233 && sparc_addr_diff_list == NULL_RTX)
8236 /* Align to cache line in the function's code section. */
8237 function_section (current_function_decl);
8239 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8241 ASM_OUTPUT_ALIGN (asm_out_file, align);
8243 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8244 sparc_output_addr_vec (XEXP (t, 0));
8245 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8246 sparc_output_addr_diff_vec (XEXP (t, 0));
8248 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8251 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8252 unknown. Return 1 if the high bits are zero, -1 if the register is
8255 sparc_check_64 (rtx x, rtx insn)
8257 /* If a register is set only once it is safe to ignore insns this
8258 code does not know how to handle. The loop will either recognize
8259 the single set and return the correct value or fail to recognize
8264 if (GET_CODE (x) != REG)
8267 if (GET_MODE (x) == DImode)
8268 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8270 if (flag_expensive_optimizations
8271 && REG_N_SETS (REGNO (y)) == 1)
8277 insn = get_last_insn_anywhere ();
8282 while ((insn = PREV_INSN (insn)))
8284 switch (GET_CODE (insn))
8297 rtx pat = PATTERN (insn);
8298 if (GET_CODE (pat) != SET)
8300 if (rtx_equal_p (x, SET_DEST (pat)))
8301 return set_extends (insn);
8302 if (y && rtx_equal_p (y, SET_DEST (pat)))
8303 return set_extends (insn);
8304 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8312 /* Returns assembly code to perform a DImode shift using
8313 a 64-bit global or out register on SPARC-V8+. */
8315 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8317 static char asm_code[60];
8319 /* The scratch register is only required when the destination
8320 register is not a 64-bit global or out register. */
8321 if (which_alternative != 2)
8322 operands[3] = operands[0];
8324 /* We can only shift by constants <= 63. */
8325 if (GET_CODE (operands[2]) == CONST_INT)
8326 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8328 if (GET_CODE (operands[1]) == CONST_INT)
8330 output_asm_insn ("mov\t%1, %3", operands);
8334 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8335 if (sparc_check_64 (operands[1], insn) <= 0)
8336 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8337 output_asm_insn ("or\t%L1, %3, %3", operands);
8340 strcpy(asm_code, opcode);
8342 if (which_alternative != 2)
8343 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8345 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8348 /* Output rtl to increment the profiler label LABELNO
8349 for profiling a function entry. */
8352 sparc_profile_hook (int labelno)
8357 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8358 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8359 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8361 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8364 #ifdef OBJECT_FORMAT_ELF
8366 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8368 if (flags & SECTION_MERGE)
8370 /* entsize cannot be expressed in this section attributes
8372 default_elf_asm_named_section (name, flags);
8376 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8378 if (!(flags & SECTION_DEBUG))
8379 fputs (",#alloc", asm_out_file);
8380 if (flags & SECTION_WRITE)
8381 fputs (",#write", asm_out_file);
8382 if (flags & SECTION_CODE)
8383 fputs (",#execinstr", asm_out_file);
8385 /* ??? Handle SECTION_BSS. */
8387 fputc ('\n', asm_out_file);
8389 #endif /* OBJECT_FORMAT_ELF */
8391 /* We do not allow sibling calls if -mflat, nor
8392 we do not allow indirect calls to be optimized into sibling calls.
8394 Also, on sparc 32-bit we cannot emit a sibling call when the
8395 current function returns a structure. This is because the "unimp
8396 after call" convention would cause the callee to return to the
8397 wrong place. The generic code already disallows cases where the
8398 function being called returns a structure.
8400 It may seem strange how this last case could occur. Usually there
8401 is code after the call which jumps to epilogue code which dumps the
8402 return value into the struct return area. That ought to invalidate
8403 the sibling call right? Well, in the c++ case we can end up passing
8404 the pointer to the struct return area to a constructor (which returns
8405 void) and then nothing else happens. Such a sibling call would look
8406 valid without the added check here. */
8408 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8412 && (TARGET_ARCH64 || ! current_function_returns_struct));
8415 /* libfunc renaming. */
8416 #include "config/gofast.h"
8419 sparc_init_libfuncs (void)
8423 /* Use the subroutines that Sun's library provides for integer
8424 multiply and divide. The `*' prevents an underscore from
8425 being prepended by the compiler. .umul is a little faster
8427 set_optab_libfunc (smul_optab, SImode, "*.umul");
8428 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8429 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8430 set_optab_libfunc (smod_optab, SImode, "*.rem");
8431 set_optab_libfunc (umod_optab, SImode, "*.urem");
8433 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8434 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8435 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8436 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8437 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8438 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8440 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8441 is because with soft-float, the SFmode and DFmode sqrt
8442 instructions will be absent, and the compiler will notice and
8443 try to use the TFmode sqrt instruction for calls to the
8444 builtin function sqrt, but this fails. */
8446 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8448 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8449 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8450 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8451 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8452 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8453 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8455 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8456 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8457 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8458 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8460 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8461 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8462 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8464 if (SUN_CONVERSION_LIBFUNCS)
8466 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8467 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8468 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8469 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8474 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8475 do not exist in the library. Make sure the compiler does not
8476 emit calls to them by accident. (It should always use the
8477 hardware instructions.) */
8478 set_optab_libfunc (smul_optab, SImode, 0);
8479 set_optab_libfunc (sdiv_optab, SImode, 0);
8480 set_optab_libfunc (udiv_optab, SImode, 0);
8481 set_optab_libfunc (smod_optab, SImode, 0);
8482 set_optab_libfunc (umod_optab, SImode, 0);
8484 if (SUN_INTEGER_MULTIPLY_64)
8486 set_optab_libfunc (smul_optab, DImode, "__mul64");
8487 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8488 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8489 set_optab_libfunc (smod_optab, DImode, "__rem64");
8490 set_optab_libfunc (umod_optab, DImode, "__urem64");
8493 if (SUN_CONVERSION_LIBFUNCS)
8495 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8496 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8497 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8498 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8502 gofast_maybe_init_libfuncs ();
8505 /* ??? Similar to the standard section selection, but force reloc-y-ness
8506 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8507 pretending PIC always on), but that's what the old code did. */
8510 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8512 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8515 /* Use text section for a constant unless we need more alignment than
8519 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8520 unsigned HOST_WIDE_INT align)
8522 if (align <= MAX_TEXT_ALIGN
8523 && ! (flag_pic && (symbolic_operand (x, mode)
8524 || SUNOS4_SHARED_LIBRARIES)))
8525 readonly_data_section ();
8531 sparc_extra_constraint_check (rtx op, int c, int strict)
8536 && (c == 'T' || c == 'U'))
8542 return fp_sethi_p (op);
8545 return fp_mov_p (op);
8548 return fp_high_losum_p (op);
8552 || (GET_CODE (op) == REG
8553 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8554 || reg_renumber[REGNO (op)] >= 0)))
8555 return register_ok_for_ldd (op);
8567 /* Our memory extra constraints have to emulate the
8568 behavior of 'm' and 'o' in order for reload to work
8570 if (GET_CODE (op) == MEM)
8573 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8575 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8580 reload_ok_mem = (reload_in_progress
8581 && GET_CODE (op) == REG
8582 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8583 && reg_renumber [REGNO (op)] < 0);
8586 return reload_ok_mem;
8589 /* ??? This duplicates information provided to the compiler by the
8590 ??? scheduler description. Some day, teach genautomata to output
8591 ??? the latencies and then CSE will just use that. */
8594 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8598 case PLUS: case MINUS: case ABS: case NEG:
8599 case FLOAT: case UNSIGNED_FLOAT:
8600 case FIX: case UNSIGNED_FIX:
8601 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8602 if (FLOAT_MODE_P (GET_MODE (x)))
8606 case PROCESSOR_ULTRASPARC:
8607 case PROCESSOR_ULTRASPARC3:
8608 *total = COSTS_N_INSNS (4);
8611 case PROCESSOR_SUPERSPARC:
8612 *total = COSTS_N_INSNS (3);
8615 case PROCESSOR_CYPRESS:
8616 *total = COSTS_N_INSNS (5);
8619 case PROCESSOR_HYPERSPARC:
8620 case PROCESSOR_SPARCLITE86X:
8622 *total = COSTS_N_INSNS (1);
8627 *total = COSTS_N_INSNS (1);
8633 case PROCESSOR_ULTRASPARC:
8634 if (GET_MODE (x) == SFmode)
8635 *total = COSTS_N_INSNS (13);
8637 *total = COSTS_N_INSNS (23);
8640 case PROCESSOR_ULTRASPARC3:
8641 if (GET_MODE (x) == SFmode)
8642 *total = COSTS_N_INSNS (20);
8644 *total = COSTS_N_INSNS (29);
8647 case PROCESSOR_SUPERSPARC:
8648 *total = COSTS_N_INSNS (12);
8651 case PROCESSOR_CYPRESS:
8652 *total = COSTS_N_INSNS (63);
8655 case PROCESSOR_HYPERSPARC:
8656 case PROCESSOR_SPARCLITE86X:
8657 *total = COSTS_N_INSNS (17);
8661 *total = COSTS_N_INSNS (30);
8666 if (FLOAT_MODE_P (GET_MODE (x)))
8670 case PROCESSOR_ULTRASPARC:
8671 case PROCESSOR_ULTRASPARC3:
8672 *total = COSTS_N_INSNS (1);
8675 case PROCESSOR_SUPERSPARC:
8676 *total = COSTS_N_INSNS (3);
8679 case PROCESSOR_CYPRESS:
8680 *total = COSTS_N_INSNS (5);
8683 case PROCESSOR_HYPERSPARC:
8684 case PROCESSOR_SPARCLITE86X:
8686 *total = COSTS_N_INSNS (1);
8691 /* ??? Maybe mark integer compares as zero cost on
8692 ??? all UltraSPARC processors because the result
8693 ??? can be bypassed to a branch in the same group. */
8695 *total = COSTS_N_INSNS (1);
8699 if (FLOAT_MODE_P (GET_MODE (x)))
8703 case PROCESSOR_ULTRASPARC:
8704 case PROCESSOR_ULTRASPARC3:
8705 *total = COSTS_N_INSNS (4);
8708 case PROCESSOR_SUPERSPARC:
8709 *total = COSTS_N_INSNS (3);
8712 case PROCESSOR_CYPRESS:
8713 *total = COSTS_N_INSNS (7);
8716 case PROCESSOR_HYPERSPARC:
8717 case PROCESSOR_SPARCLITE86X:
8718 *total = COSTS_N_INSNS (1);
8722 *total = COSTS_N_INSNS (5);
8727 /* The latency is actually variable for Ultra-I/II
8728 And if one of the inputs have a known constant
8729 value, we could calculate this precisely.
8731 However, for that to be useful we would need to
8732 add some machine description changes which would
8733 make sure small constants ended up in rs1 of the
8734 multiply instruction. This is because the multiply
8735 latency is determined by the number of clear (or
8736 set if the value is negative) bits starting from
8737 the most significant bit of the first input.
8739 The algorithm for computing num_cycles of a multiply
8743 highest_bit = highest_clear_bit(rs1);
8745 highest_bit = highest_set_bit(rs1);
8748 num_cycles = 4 + ((highest_bit - 3) / 2);
8750 If we did that we would have to also consider register
8751 allocation issues that would result from forcing such
8752 a value into a register.
8754 There are other similar tricks we could play if we
8755 knew, for example, that one input was an array index.
8757 Since we do not play any such tricks currently the
8758 safest thing to do is report the worst case latency. */
8759 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8761 *total = (GET_MODE (x) == DImode
8762 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8766 /* Multiply latency on Ultra-III, fortunately, is constant. */
8767 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8769 *total = COSTS_N_INSNS (6);
8773 if (sparc_cpu == PROCESSOR_HYPERSPARC
8774 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8776 *total = COSTS_N_INSNS (17);
8780 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8787 if (FLOAT_MODE_P (GET_MODE (x)))
8791 case PROCESSOR_ULTRASPARC:
8792 if (GET_MODE (x) == SFmode)
8793 *total = COSTS_N_INSNS (13);
8795 *total = COSTS_N_INSNS (23);
8798 case PROCESSOR_ULTRASPARC3:
8799 if (GET_MODE (x) == SFmode)
8800 *total = COSTS_N_INSNS (17);
8802 *total = COSTS_N_INSNS (20);
8805 case PROCESSOR_SUPERSPARC:
8806 if (GET_MODE (x) == SFmode)
8807 *total = COSTS_N_INSNS (6);
8809 *total = COSTS_N_INSNS (9);
8812 case PROCESSOR_HYPERSPARC:
8813 case PROCESSOR_SPARCLITE86X:
8814 if (GET_MODE (x) == SFmode)
8815 *total = COSTS_N_INSNS (8);
8817 *total = COSTS_N_INSNS (12);
8821 *total = COSTS_N_INSNS (7);
8826 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8827 *total = (GET_MODE (x) == DImode
8828 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8829 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8830 *total = (GET_MODE (x) == DImode
8831 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8833 *total = COSTS_N_INSNS (25);
8837 /* Conditional moves. */
8840 case PROCESSOR_ULTRASPARC:
8841 *total = COSTS_N_INSNS (2);
8844 case PROCESSOR_ULTRASPARC3:
8845 if (FLOAT_MODE_P (GET_MODE (x)))
8846 *total = COSTS_N_INSNS (3);
8848 *total = COSTS_N_INSNS (2);
8852 *total = COSTS_N_INSNS (1);
8857 /* If outer-code is SIGN/ZERO extension we have to subtract
8858 out COSTS_N_INSNS (1) from whatever we return in determining
8862 case PROCESSOR_ULTRASPARC:
8863 if (outer_code == ZERO_EXTEND)
8864 *total = COSTS_N_INSNS (1);
8866 *total = COSTS_N_INSNS (2);
8869 case PROCESSOR_ULTRASPARC3:
8870 if (outer_code == ZERO_EXTEND)
8872 if (GET_MODE (x) == QImode
8873 || GET_MODE (x) == HImode
8874 || outer_code == SIGN_EXTEND)
8875 *total = COSTS_N_INSNS (2);
8877 *total = COSTS_N_INSNS (1);
8881 /* This handles sign extension (3 cycles)
8882 and everything else (2 cycles). */
8883 *total = COSTS_N_INSNS (2);
8887 case PROCESSOR_SUPERSPARC:
8888 if (FLOAT_MODE_P (GET_MODE (x))
8889 || outer_code == ZERO_EXTEND
8890 || outer_code == SIGN_EXTEND)
8891 *total = COSTS_N_INSNS (0);
8893 *total = COSTS_N_INSNS (1);
8896 case PROCESSOR_TSC701:
8897 if (outer_code == ZERO_EXTEND
8898 || outer_code == SIGN_EXTEND)
8899 *total = COSTS_N_INSNS (2);
8901 *total = COSTS_N_INSNS (3);
8904 case PROCESSOR_CYPRESS:
8905 if (outer_code == ZERO_EXTEND
8906 || outer_code == SIGN_EXTEND)
8907 *total = COSTS_N_INSNS (1);
8909 *total = COSTS_N_INSNS (2);
8912 case PROCESSOR_HYPERSPARC:
8913 case PROCESSOR_SPARCLITE86X:
8915 if (outer_code == ZERO_EXTEND
8916 || outer_code == SIGN_EXTEND)
8917 *total = COSTS_N_INSNS (0);
8919 *total = COSTS_N_INSNS (1);
8924 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8942 if (GET_MODE (x) == DImode
8943 && ((XINT (x, 3) == 0
8944 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8945 || (XINT (x, 3) == -1
8947 && XINT (x, 2) >= -0x1000)))
8958 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8959 Used for C++ multiple inheritance. */
8962 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8963 HOST_WIDE_INT delta,
8964 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8967 rtx this, insn, funexp, delta_rtx, tmp;
8969 reload_completed = 1;
8970 epilogue_completed = 1;
8972 current_function_uses_only_leaf_regs = 1;
8974 emit_note (NOTE_INSN_PROLOGUE_END);
8976 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8977 returns a structure, the structure return pointer is there instead. */
8978 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8979 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8981 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8983 /* Add DELTA. When possible use a plain add, otherwise load it into
8984 a register first. */
8985 delta_rtx = GEN_INT (delta);
8986 if (!SPARC_SIMM13_P (delta))
8988 rtx scratch = gen_rtx_REG (Pmode, 1);
8990 sparc_emit_set_const64 (scratch, delta_rtx);
8992 sparc_emit_set_const32 (scratch, delta_rtx);
8993 delta_rtx = scratch;
8996 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8997 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8999 /* Generate a tail call to the target function. */
9000 if (! TREE_USED (function))
9002 assemble_external (function);
9003 TREE_USED (function) = 1;
9005 funexp = XEXP (DECL_RTL (function), 0);
9006 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9007 insn = emit_call_insn (gen_sibcall (funexp));
9008 SIBLING_CALL_P (insn) = 1;
9011 /* Run just enough of rest_of_compilation to get the insns emitted.
9012 There's not really enough bulk here to make other passes such as
9013 instruction scheduling worth while. Note that use_thunk calls
9014 assemble_start_function and assemble_end_function. */
9015 insn = get_insns ();
9016 insn_locators_initialize ();
9017 shorten_branches (insn);
9018 final_start_function (insn, file, 1);
9019 final (insn, file, 1, 0);
9020 final_end_function ();
9022 reload_completed = 0;
9023 epilogue_completed = 0;
9027 /* How to allocate a 'struct machine_function'. */
9029 static struct machine_function *
9030 sparc_init_machine_status (void)
9032 return ggc_alloc_cleared (sizeof (struct machine_function));
9035 /* Locate some local-dynamic symbol still in use by this function
9036 so that we can print its name in local-dynamic base patterns. */
9039 get_some_local_dynamic_name (void)
9043 if (cfun->machine->some_ld_name)
9044 return cfun->machine->some_ld_name;
9046 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9048 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9049 return cfun->machine->some_ld_name;
9055 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9060 && GET_CODE (x) == SYMBOL_REF
9061 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9063 cfun->machine->some_ld_name = XSTR (x, 0);
9070 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9071 We need to emit DTP-relative relocations. */
9074 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9079 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9082 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9087 output_addr_const (file, x);
9091 #include "gt-sparc.h"