1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
52 #ifdef HAVE_AS_RELAX_OPTION
53 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
54 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
55 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
56 somebody does not branch between the sethi and jmp. */
57 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
59 #define LEAF_SIBCALL_SLOT_RESERVED_P \
60 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
63 /* Global variables for machine-dependent things. */
65 /* Size of frame. Need to know this to emit return insns from leaf procedures.
66 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
67 reload pass. This is important as the value is later used for scheduling
68 (to see what can go in a delay slot).
69 APPARENT_FSIZE is the size of the stack less the register save area and less
70 the outgoing argument area. It is used when saving call preserved regs. */
71 static HOST_WIDE_INT apparent_fsize;
72 static HOST_WIDE_INT actual_fsize;
74 /* Number of live general or floating point registers needed to be
75 saved (as 4-byte quantities). */
76 static int num_gfregs;
78 /* The alias set for prologue/epilogue register save/restore. */
79 static GTY(()) int sparc_sr_alias_set;
81 /* Save the operands last given to a compare for use when we
82 generate a scc or bcc insn. */
83 rtx sparc_compare_op0, sparc_compare_op1;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Register we pretend to think the frame pointer is allocated to.
129 Normally, this is %fp, but if we are in a leaf procedure, this
130 is %sp+"something". We record "something" separately as it may
131 be too big for reg+constant addressing. */
133 static rtx frame_base_reg;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static void scan_record_type (tree, int *, int *, int *);
138 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
139 tree, int, int, int *, int *);
141 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
142 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
144 static void sparc_output_addr_vec (rtx);
145 static void sparc_output_addr_diff_vec (rtx);
146 static void sparc_output_deferred_case_vectors (void);
147 static rtx sparc_builtin_saveregs (void);
148 static int epilogue_renumber (rtx *, int);
149 static bool sparc_assemble_integer (rtx, unsigned int, int);
150 static int set_extends (rtx);
151 static void load_pic_register (void);
152 static int save_or_restore_regs (int, int, rtx, int, int);
153 static void emit_save_regs (void);
154 static void emit_restore_regs (void);
155 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
157 #ifdef OBJECT_FORMAT_ELF
158 static void sparc_elf_asm_named_section (const char *, unsigned int);
161 static int sparc_adjust_cost (rtx, rtx, rtx, int);
162 static int sparc_issue_rate (void);
163 static void sparc_sched_init (FILE *, int, int);
164 static int sparc_use_dfa_pipeline_interface (void);
165 static int sparc_use_sched_lookahead (void);
167 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
168 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
169 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
170 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
171 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
173 static bool sparc_function_ok_for_sibcall (tree, tree);
174 static void sparc_init_libfuncs (void);
175 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
176 HOST_WIDE_INT, tree);
177 static struct machine_function * sparc_init_machine_status (void);
178 static bool sparc_cannot_force_const_mem (rtx);
179 static rtx sparc_tls_get_addr (void);
180 static rtx sparc_tls_got (void);
181 static const char *get_some_local_dynamic_name (void);
182 static int get_some_local_dynamic_name_1 (rtx *, void *);
183 static bool sparc_rtx_costs (rtx, int, int, int *);
184 static bool sparc_promote_prototypes (tree);
185 static rtx sparc_struct_value_rtx (tree, int);
186 static bool sparc_return_in_memory (tree, tree);
187 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
188 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
190 /* Option handling. */
192 /* Code model option as passed by user. */
193 const char *sparc_cmodel_string;
195 enum cmodel sparc_cmodel;
197 char sparc_hard_reg_printed[8];
199 struct sparc_cpu_select sparc_select[] =
201 /* switch name, tune arch */
202 { (char *)0, "default", 1, 1 },
203 { (char *)0, "-mcpu=", 1, 1 },
204 { (char *)0, "-mtune=", 1, 0 },
208 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
209 enum processor_type sparc_cpu;
211 /* Initialize the GCC target structure. */
213 /* The sparc default is to use .half rather than .short for aligned
214 HI objects. Use .word instead of .long on non-ELF systems. */
215 #undef TARGET_ASM_ALIGNED_HI_OP
216 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
217 #ifndef OBJECT_FORMAT_ELF
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
222 #undef TARGET_ASM_UNALIGNED_HI_OP
223 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
224 #undef TARGET_ASM_UNALIGNED_SI_OP
225 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
226 #undef TARGET_ASM_UNALIGNED_DI_OP
227 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
229 /* The target hook has to handle DI-mode values. */
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER sparc_assemble_integer
233 #undef TARGET_ASM_FUNCTION_PROLOGUE
234 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
235 #undef TARGET_ASM_FUNCTION_EPILOGUE
236 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
238 #undef TARGET_SCHED_ADJUST_COST
239 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
240 #undef TARGET_SCHED_ISSUE_RATE
241 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
242 #undef TARGET_SCHED_INIT
243 #define TARGET_SCHED_INIT sparc_sched_init
244 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
245 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
246 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
247 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
249 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
250 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
252 #undef TARGET_INIT_LIBFUNCS
253 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
256 #undef TARGET_HAVE_TLS
257 #define TARGET_HAVE_TLS true
259 #undef TARGET_CANNOT_FORCE_CONST_MEM
260 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
262 #undef TARGET_ASM_OUTPUT_MI_THUNK
263 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
264 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
265 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
267 #undef TARGET_RTX_COSTS
268 #define TARGET_RTX_COSTS sparc_rtx_costs
269 #undef TARGET_ADDRESS_COST
270 #define TARGET_ADDRESS_COST hook_int_rtx_0
272 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
273 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
274 test for this value. */
275 #undef TARGET_PROMOTE_FUNCTION_ARGS
276 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
278 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
279 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
280 test for this value. */
281 #undef TARGET_PROMOTE_FUNCTION_RETURN
282 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
284 #undef TARGET_PROMOTE_PROTOTYPES
285 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
287 #undef TARGET_STRUCT_VALUE_RTX
288 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
289 #undef TARGET_RETURN_IN_MEMORY
290 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
292 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
293 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
294 #undef TARGET_STRICT_ARGUMENT_NAMING
295 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
297 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
298 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
300 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
301 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
303 struct gcc_target targetm = TARGET_INITIALIZER;
305 /* Validate and override various options, and do some machine dependent
309 sparc_override_options (void)
311 static struct code_model {
312 const char *const name;
314 } const cmodels[] = {
316 { "medlow", CM_MEDLOW },
317 { "medmid", CM_MEDMID },
318 { "medany", CM_MEDANY },
319 { "embmedany", CM_EMBMEDANY },
322 const struct code_model *cmodel;
323 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
324 static struct cpu_default {
326 const char *const name;
327 } const cpu_default[] = {
328 /* There must be one entry here for each TARGET_CPU value. */
329 { TARGET_CPU_sparc, "cypress" },
330 { TARGET_CPU_sparclet, "tsc701" },
331 { TARGET_CPU_sparclite, "f930" },
332 { TARGET_CPU_v8, "v8" },
333 { TARGET_CPU_hypersparc, "hypersparc" },
334 { TARGET_CPU_sparclite86x, "sparclite86x" },
335 { TARGET_CPU_supersparc, "supersparc" },
336 { TARGET_CPU_v9, "v9" },
337 { TARGET_CPU_ultrasparc, "ultrasparc" },
338 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
341 const struct cpu_default *def;
342 /* Table of values for -m{cpu,tune}=. */
343 static struct cpu_table {
344 const char *const name;
345 const enum processor_type processor;
348 } const cpu_table[] = {
349 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
350 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
351 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
352 /* TI TMS390Z55 supersparc */
353 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
354 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
355 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
356 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
357 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
358 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
359 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
360 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
362 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
364 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
365 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
366 /* TI ultrasparc I, II, IIi */
367 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
368 /* Although insns using %y are deprecated, it is a clear win on current
370 |MASK_DEPRECATED_V8_INSNS},
371 /* TI ultrasparc III */
372 /* ??? Check if %y issue still holds true in ultra3. */
373 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
376 const struct cpu_table *cpu;
377 const struct sparc_cpu_select *sel;
380 #ifndef SPARC_BI_ARCH
381 /* Check for unsupported architecture size. */
382 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
383 error ("%s is not supported by this configuration",
384 DEFAULT_ARCH32_P ? "-m64" : "-m32");
387 /* We force all 64bit archs to use 128 bit long double */
388 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
390 error ("-mlong-double-64 not allowed with -m64");
391 target_flags |= MASK_LONG_DOUBLE_128;
394 /* Code model selection. */
395 sparc_cmodel = SPARC_DEFAULT_CMODEL;
399 sparc_cmodel = CM_32;
402 if (sparc_cmodel_string != NULL)
406 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
407 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
409 if (cmodel->name == NULL)
410 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
412 sparc_cmodel = cmodel->value;
415 error ("-mcmodel= is not supported on 32 bit systems");
418 fpu = TARGET_FPU; /* save current -mfpu status */
420 /* Set the default CPU. */
421 for (def = &cpu_default[0]; def->name; ++def)
422 if (def->cpu == TARGET_CPU_DEFAULT)
426 sparc_select[0].string = def->name;
428 for (sel = &sparc_select[0]; sel->name; ++sel)
432 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
433 if (! strcmp (sel->string, cpu->name))
436 sparc_cpu = cpu->processor;
440 target_flags &= ~cpu->disable;
441 target_flags |= cpu->enable;
447 error ("bad value (%s) for %s switch", sel->string, sel->name);
451 /* If -mfpu or -mno-fpu was explicitly used, don't override with
452 the processor default. Clear MASK_FPU_SET to avoid confusing
453 the reverse mapping from switch values to names. */
456 target_flags = (target_flags & ~MASK_FPU) | fpu;
457 target_flags &= ~MASK_FPU_SET;
460 /* Don't allow -mvis if FPU is disabled. */
462 target_flags &= ~MASK_VIS;
464 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
466 -m64 also implies v9. */
467 if (TARGET_VIS || TARGET_ARCH64)
469 target_flags |= MASK_V9;
470 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
473 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
474 if (TARGET_V9 && TARGET_ARCH32)
475 target_flags |= MASK_DEPRECATED_V8_INSNS;
477 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
478 if (! TARGET_V9 || TARGET_ARCH64)
479 target_flags &= ~MASK_V8PLUS;
481 /* Don't use stack biasing in 32 bit mode. */
483 target_flags &= ~MASK_STACK_BIAS;
485 /* Supply a default value for align_functions. */
486 if (align_functions == 0
487 && (sparc_cpu == PROCESSOR_ULTRASPARC
488 || sparc_cpu == PROCESSOR_ULTRASPARC3))
489 align_functions = 32;
491 /* Validate PCC_STRUCT_RETURN. */
492 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
493 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
495 /* Only use .uaxword when compiling for a 64-bit target. */
497 targetm.asm_out.unaligned_op.di = NULL;
499 /* Do various machine dependent initializations. */
502 /* Acquire a unique set number for our register saves and restores. */
503 sparc_sr_alias_set = new_alias_set ();
505 /* Set up function hooks. */
506 init_machine_status = sparc_init_machine_status;
509 /* Miscellaneous utilities. */
511 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
512 or branch on register contents instructions. */
515 v9_regcmp_p (enum rtx_code code)
517 return (code == EQ || code == NE || code == GE || code == LT
518 || code == LE || code == GT);
522 /* Operand constraints. */
524 /* Return nonzero only if OP is a register of mode MODE,
528 reg_or_0_operand (rtx op, enum machine_mode mode)
530 if (register_operand (op, mode))
532 if (op == const0_rtx)
534 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
535 && CONST_DOUBLE_HIGH (op) == 0
536 && CONST_DOUBLE_LOW (op) == 0)
538 if (fp_zero_operand (op, mode))
543 /* Return nonzero only if OP is const1_rtx. */
546 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
548 return op == const1_rtx;
551 /* Nonzero if OP is a floating point value with value 0.0. */
554 fp_zero_operand (rtx op, enum machine_mode mode)
556 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
558 return op == CONST0_RTX (mode);
561 /* Nonzero if OP is a register operand in floating point register. */
564 fp_register_operand (rtx op, enum machine_mode mode)
566 if (! register_operand (op, mode))
568 if (GET_CODE (op) == SUBREG)
569 op = SUBREG_REG (op);
570 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
573 /* Nonzero if OP is a floating point constant which can
574 be loaded into an integer register using a single
575 sethi instruction. */
580 if (GET_CODE (op) == CONST_DOUBLE)
585 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
586 if (REAL_VALUES_EQUAL (r, dconst0) &&
587 ! REAL_VALUE_MINUS_ZERO (r))
589 REAL_VALUE_TO_TARGET_SINGLE (r, i);
590 if (SPARC_SETHI_P (i))
597 /* Nonzero if OP is a floating point constant which can
598 be loaded into an integer register using a single
604 if (GET_CODE (op) == CONST_DOUBLE)
609 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
610 if (REAL_VALUES_EQUAL (r, dconst0) &&
611 ! REAL_VALUE_MINUS_ZERO (r))
613 REAL_VALUE_TO_TARGET_SINGLE (r, i);
614 if (SPARC_SIMM13_P (i))
621 /* Nonzero if OP is a floating point constant which can
622 be loaded into an integer register using a high/losum
623 instruction sequence. */
626 fp_high_losum_p (rtx op)
628 /* The constraints calling this should only be in
629 SFmode move insns, so any constant which cannot
630 be moved using a single insn will do. */
631 if (GET_CODE (op) == CONST_DOUBLE)
636 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
637 if (REAL_VALUES_EQUAL (r, dconst0) &&
638 ! REAL_VALUE_MINUS_ZERO (r))
640 REAL_VALUE_TO_TARGET_SINGLE (r, i);
641 if (! SPARC_SETHI_P (i)
642 && ! SPARC_SIMM13_P (i))
649 /* Nonzero if OP is an integer register. */
652 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
654 return (register_operand (op, SImode)
655 || (TARGET_ARCH64 && register_operand (op, DImode)));
658 /* Nonzero if OP is a floating point condition code register. */
661 fcc_reg_operand (rtx op, enum machine_mode mode)
663 /* This can happen when recog is called from combine. Op may be a MEM.
664 Fail instead of calling abort in this case. */
665 if (GET_CODE (op) != REG)
668 if (mode != VOIDmode && mode != GET_MODE (op))
671 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
674 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
675 if (reg_renumber == 0)
676 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
677 return REGNO_OK_FOR_CCFP_P (REGNO (op));
679 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
683 /* Nonzero if OP is a floating point condition code fcc0 register. */
686 fcc0_reg_operand (rtx op, enum machine_mode mode)
688 /* This can happen when recog is called from combine. Op may be a MEM.
689 Fail instead of calling abort in this case. */
690 if (GET_CODE (op) != REG)
693 if (mode != VOIDmode && mode != GET_MODE (op))
696 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
699 return REGNO (op) == SPARC_FCC_REG;
702 /* Nonzero if OP is an integer or floating point condition code register. */
705 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
707 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
709 if (mode != VOIDmode && mode != GET_MODE (op))
712 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
717 return fcc_reg_operand (op, mode);
720 /* Call insn on SPARC can take a PC-relative constant address, or any regular
724 call_operand (rtx op, enum machine_mode mode)
726 if (GET_CODE (op) != MEM)
729 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
733 call_operand_address (rtx op, enum machine_mode mode)
735 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
738 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
739 otherwise return 0. */
742 tls_symbolic_operand (rtx op)
744 if (GET_CODE (op) != SYMBOL_REF)
746 return SYMBOL_REF_TLS_MODEL (op);
750 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
752 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
756 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
758 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
762 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
764 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
768 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
770 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
773 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
774 reference and a constant. */
777 symbolic_operand (register rtx op, enum machine_mode mode)
779 enum machine_mode omode = GET_MODE (op);
781 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
784 switch (GET_CODE (op))
787 return !SYMBOL_REF_TLS_MODEL (op);
794 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
795 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
796 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
797 && GET_CODE (XEXP (op, 1)) == CONST_INT);
804 /* Return truth value of statement that OP is a symbolic memory
805 operand of mode MODE. */
808 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
810 if (GET_CODE (op) == SUBREG)
811 op = SUBREG_REG (op);
812 if (GET_CODE (op) != MEM)
815 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
816 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
817 || GET_CODE (op) == LABEL_REF);
820 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
823 label_ref_operand (rtx op, enum machine_mode mode)
825 if (GET_CODE (op) != LABEL_REF)
827 if (GET_MODE (op) != mode)
832 /* Return 1 if the operand is an argument used in generating pic references
833 in either the medium/low or medium/anywhere code models of sparc64. */
836 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
838 /* Check for (const (minus (symbol_ref:GOT)
839 (const (minus (label) (pc))))). */
840 if (GET_CODE (op) != CONST)
843 if (GET_CODE (op) != MINUS)
845 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
847 /* ??? Ensure symbol is GOT. */
848 if (GET_CODE (XEXP (op, 1)) != CONST)
850 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
855 /* Return 1 if the operand is a data segment reference. This includes
856 the readonly data segment, or in other words anything but the text segment.
857 This is needed in the medium/anywhere code model on v9. These values
858 are accessed with EMBMEDANY_BASE_REG. */
861 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
863 switch (GET_CODE (op))
866 return ! SYMBOL_REF_FUNCTION_P (op);
868 /* Assume canonical format of symbol + constant.
871 return data_segment_operand (XEXP (op, 0), VOIDmode);
877 /* Return 1 if the operand is a text segment reference.
878 This is needed in the medium/anywhere code model on v9. */
881 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
883 switch (GET_CODE (op))
888 return SYMBOL_REF_FUNCTION_P (op);
890 /* Assume canonical format of symbol + constant.
893 return text_segment_operand (XEXP (op, 0), VOIDmode);
899 /* Return 1 if the operand is either a register or a memory operand that is
903 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
905 if (register_operand (op, mode))
908 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
915 splittable_symbolic_memory_operand (rtx op,
916 enum machine_mode mode ATTRIBUTE_UNUSED)
918 if (GET_CODE (op) != MEM)
920 if (! symbolic_operand (XEXP (op, 0), Pmode))
926 splittable_immediate_memory_operand (rtx op,
927 enum machine_mode mode ATTRIBUTE_UNUSED)
929 if (GET_CODE (op) != MEM)
931 if (! immediate_operand (XEXP (op, 0), Pmode))
936 /* Return truth value of whether OP is EQ or NE. */
939 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
941 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
944 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
945 or LTU for non-floating-point. We handle those specially. */
948 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
952 if (!COMPARISON_P (op))
955 if (GET_MODE (XEXP (op, 0)) == CCFPmode
956 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
959 code = GET_CODE (op);
960 return (code != NE && code != EQ && code != GEU && code != LTU);
963 /* Return 1 if this is a comparison operator. This allows the use of
964 MATCH_OPERATOR to recognize all the branch insns. */
967 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
971 if (!COMPARISON_P (op))
974 code = GET_CODE (op);
975 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
976 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
977 /* These are the only branches which work with CC_NOOVmode. */
978 return (code == EQ || code == NE || code == GE || code == LT);
982 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
983 MATCH_OPERATOR to recognize all the branch insns. */
986 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
993 if (!COMPARISON_P (op))
996 code = GET_CODE (op);
997 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
998 /* These are the only branches which work with CCX_NOOVmode. */
999 return (code == EQ || code == NE || code == GE || code == LT);
1000 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1003 /* Nonzero if OP is a comparison operator suitable for use in v9
1004 conditional move or branch on register contents instructions. */
1007 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1011 if (!COMPARISON_P (op))
1014 code = GET_CODE (op);
1015 return v9_regcmp_p (code);
1018 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1021 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1023 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1026 /* Return nonzero if OP is an operator of mode MODE which can set
1027 the condition codes explicitly. We do not include PLUS and MINUS
1028 because these require CC_NOOVmode, which we handle explicitly. */
1031 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1033 if (GET_CODE (op) == AND
1034 || GET_CODE (op) == IOR
1035 || GET_CODE (op) == XOR)
1041 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1042 complement its second operand and set the condition codes explicitly. */
1045 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1047 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1048 and (xor ... (not ...)) to (not (xor ...)). */
1049 return (GET_CODE (op) == AND
1050 || GET_CODE (op) == IOR);
1053 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1054 signed 13 bit immediate field. This is an acceptable SImode operand for
1055 most 3 address instructions. */
1058 arith_operand (rtx op, enum machine_mode mode)
1060 if (register_operand (op, mode))
1062 if (GET_CODE (op) != CONST_INT)
1064 return SMALL_INT32 (op);
1067 /* Return true if OP is a constant 4096 */
1070 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1072 if (GET_CODE (op) != CONST_INT)
1075 return INTVAL (op) == 4096;
1078 /* Return true if OP is suitable as second operand for add/sub */
1081 arith_add_operand (rtx op, enum machine_mode mode)
1083 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1086 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1087 immediate field of OR and XOR instructions. Used for 64-bit
1088 constant formation patterns. */
1090 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1092 return ((GET_CODE (op) == CONST_INT
1093 && SPARC_SIMM13_P (INTVAL (op)))
1094 #if HOST_BITS_PER_WIDE_INT != 64
1095 || (GET_CODE (op) == CONST_DOUBLE
1096 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1097 && (CONST_DOUBLE_HIGH (op) ==
1098 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1099 (HOST_WIDE_INT)-1 : 0)))
1104 /* The same, but only for sethi instructions. */
1106 const64_high_operand (rtx op, enum machine_mode mode)
1108 return ((GET_CODE (op) == CONST_INT
1109 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1110 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1112 || (GET_CODE (op) == CONST_DOUBLE
1113 && CONST_DOUBLE_HIGH (op) == 0
1114 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1115 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1118 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1119 signed 11 bit immediate field. This is an acceptable SImode operand for
1120 the movcc instructions. */
1123 arith11_operand (rtx op, enum machine_mode mode)
1125 return (register_operand (op, mode)
1126 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1129 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1130 signed 10 bit immediate field. This is an acceptable SImode operand for
1131 the movrcc instructions. */
1134 arith10_operand (rtx op, enum machine_mode mode)
1136 return (register_operand (op, mode)
1137 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1140 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1141 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1143 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1144 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1145 for most 3 address instructions. */
1148 arith_double_operand (rtx op, enum machine_mode mode)
1150 return (register_operand (op, mode)
1151 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1153 && GET_CODE (op) == CONST_DOUBLE
1154 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1155 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1157 && GET_CODE (op) == CONST_DOUBLE
1158 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1159 && ((CONST_DOUBLE_HIGH (op) == -1
1160 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1161 || (CONST_DOUBLE_HIGH (op) == 0
1162 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1165 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1168 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1170 return (TARGET_ARCH64 &&
1171 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1172 (GET_CODE (op) == CONST_DOUBLE &&
1173 CONST_DOUBLE_LOW (op) == 4096 &&
1174 CONST_DOUBLE_HIGH (op) == 0)));
1177 /* Return true if OP is suitable as second operand for add/sub in DImode */
1180 arith_double_add_operand (rtx op, enum machine_mode mode)
1182 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1185 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1186 can fit in an 11 bit immediate field. This is an acceptable DImode
1187 operand for the movcc instructions. */
1188 /* ??? Replace with arith11_operand? */
1191 arith11_double_operand (rtx op, enum machine_mode mode)
1193 return (register_operand (op, mode)
1194 || (GET_CODE (op) == CONST_DOUBLE
1195 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1196 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1197 && ((CONST_DOUBLE_HIGH (op) == -1
1198 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1199 || (CONST_DOUBLE_HIGH (op) == 0
1200 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1201 || (GET_CODE (op) == CONST_INT
1202 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1203 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1206 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1207 can fit in an 10 bit immediate field. This is an acceptable DImode
1208 operand for the movrcc instructions. */
1209 /* ??? Replace with arith10_operand? */
1212 arith10_double_operand (rtx op, enum machine_mode mode)
1214 return (register_operand (op, mode)
1215 || (GET_CODE (op) == CONST_DOUBLE
1216 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1217 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1218 && ((CONST_DOUBLE_HIGH (op) == -1
1219 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1220 || (CONST_DOUBLE_HIGH (op) == 0
1221 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1222 || (GET_CODE (op) == CONST_INT
1223 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1224 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1227 /* Return truth value of whether OP is an integer which fits the
1228 range constraining immediate operands in most three-address insns,
1229 which have a 13 bit immediate field. */
1232 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1234 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1238 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1240 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1241 || (GET_CODE (op) == CONST_DOUBLE
1242 && CONST_DOUBLE_HIGH (op) == 0
1243 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1246 /* Recognize operand values for the umul instruction. That instruction sign
1247 extends immediate values just like all other sparc instructions, but
1248 interprets the extended result as an unsigned number. */
1251 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1253 #if HOST_BITS_PER_WIDE_INT > 32
1254 /* All allowed constants will fit a CONST_INT. */
1255 return (GET_CODE (op) == CONST_INT
1256 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1257 || (INTVAL (op) >= 0xFFFFF000
1258 && INTVAL (op) <= 0xFFFFFFFF)));
1260 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1261 || (GET_CODE (op) == CONST_DOUBLE
1262 && CONST_DOUBLE_HIGH (op) == 0
1263 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1268 uns_arith_operand (rtx op, enum machine_mode mode)
1270 return register_operand (op, mode) || uns_small_int (op, mode);
1273 /* Return truth value of statement that OP is a call-clobbered register. */
1275 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1277 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1280 /* Return 1 if OP is a valid operand for the source of a move insn. */
1283 input_operand (rtx op, enum machine_mode mode)
1285 /* If both modes are non-void they must be the same. */
1286 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1289 /* Allow any one instruction integer constant, and all CONST_INT
1290 variants when we are working in DImode and !arch64. */
1291 if (GET_MODE_CLASS (mode) == MODE_INT
1292 && ((GET_CODE (op) == CONST_INT
1293 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1294 || SPARC_SIMM13_P (INTVAL (op))
1296 && ! TARGET_ARCH64)))
1298 && GET_CODE (op) == CONST_DOUBLE
1299 && ((CONST_DOUBLE_HIGH (op) == 0
1300 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1302 #if HOST_BITS_PER_WIDE_INT == 64
1303 (CONST_DOUBLE_HIGH (op) == 0
1304 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1306 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1307 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1308 && CONST_DOUBLE_HIGH (op) == 0)
1309 || (CONST_DOUBLE_HIGH (op) == -1
1310 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1315 /* If !arch64 and this is a DImode const, allow it so that
1316 the splits can be generated. */
1319 && GET_CODE (op) == CONST_DOUBLE)
1322 if (register_operand (op, mode))
1325 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1326 && GET_CODE (op) == CONST_DOUBLE)
1329 /* If this is a SUBREG, look inside so that we handle
1330 paradoxical ones. */
1331 if (GET_CODE (op) == SUBREG)
1332 op = SUBREG_REG (op);
1334 /* Check for valid MEM forms. */
1335 if (GET_CODE (op) == MEM)
1337 rtx inside = XEXP (op, 0);
1339 if (GET_CODE (inside) == LO_SUM)
1341 /* We can't allow these because all of the splits
1342 (eventually as they trickle down into DFmode
1343 splits) require offsettable memory references. */
1345 && GET_MODE (op) == TFmode)
1348 return (register_operand (XEXP (inside, 0), Pmode)
1349 && CONSTANT_P (XEXP (inside, 1)));
1351 return memory_address_p (mode, inside);
1357 /* Return 1 if OP is valid for the lhs of a compare insn. */
1360 compare_operand (rtx op, enum machine_mode mode)
1362 if (GET_CODE (op) == ZERO_EXTRACT)
1363 return (register_operand (XEXP (op, 0), mode)
1364 && small_int_or_double (XEXP (op, 1), mode)
1365 && small_int_or_double (XEXP (op, 2), mode)
1366 /* This matches cmp_zero_extract. */
1368 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1369 && INTVAL (XEXP (op, 2)) > 19)
1370 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1371 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1372 /* This matches cmp_zero_extract_sp64. */
1375 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1376 && INTVAL (XEXP (op, 2)) > 51)
1377 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1378 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1380 return register_operand (op, mode);
1384 /* We know it can't be done in one insn when we get here,
1385 the movsi expander guarantees this. */
1387 sparc_emit_set_const32 (rtx op0, rtx op1)
1389 enum machine_mode mode = GET_MODE (op0);
1392 if (GET_CODE (op1) == CONST_INT)
1394 HOST_WIDE_INT value = INTVAL (op1);
1396 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1397 || SPARC_SIMM13_P (value))
1401 /* Full 2-insn decomposition is needed. */
1402 if (reload_in_progress || reload_completed)
1405 temp = gen_reg_rtx (mode);
1407 if (GET_CODE (op1) == CONST_INT)
1409 /* Emit them as real moves instead of a HIGH/LO_SUM,
1410 this way CSE can see everything and reuse intermediate
1411 values if it wants. */
1413 && HOST_BITS_PER_WIDE_INT != 64
1414 && (INTVAL (op1) & 0x80000000) != 0)
1415 emit_insn (gen_rtx_SET
1417 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1420 emit_insn (gen_rtx_SET (VOIDmode, temp,
1421 GEN_INT (INTVAL (op1)
1422 & ~(HOST_WIDE_INT)0x3ff)));
1424 emit_insn (gen_rtx_SET (VOIDmode,
1426 gen_rtx_IOR (mode, temp,
1427 GEN_INT (INTVAL (op1) & 0x3ff))));
1431 /* A symbol, emit in the traditional way. */
1432 emit_insn (gen_rtx_SET (VOIDmode, temp,
1433 gen_rtx_HIGH (mode, op1)));
1434 emit_insn (gen_rtx_SET (VOIDmode,
1435 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1441 /* SPARC-v9 code-model support. */
1443 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1447 if (temp1 && GET_MODE (temp1) == TImode)
1450 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1453 switch (sparc_cmodel)
1456 /* The range spanned by all instructions in the object is less
1457 than 2^31 bytes (2GB) and the distance from any instruction
1458 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1459 than 2^31 bytes (2GB).
1461 The executable must be in the low 4TB of the virtual address
1464 sethi %hi(symbol), %temp
1465 or %temp, %lo(symbol), %reg */
1466 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1467 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1471 /* The range spanned by all instructions in the object is less
1472 than 2^31 bytes (2GB) and the distance from any instruction
1473 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1474 than 2^31 bytes (2GB).
1476 The executable must be in the low 16TB of the virtual address
1479 sethi %h44(symbol), %temp1
1480 or %temp1, %m44(symbol), %temp2
1481 sllx %temp2, 12, %temp3
1482 or %temp3, %l44(symbol), %reg */
1483 emit_insn (gen_seth44 (op0, op1));
1484 emit_insn (gen_setm44 (op0, op0, op1));
1485 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1486 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1487 emit_insn (gen_setl44 (op0, temp1, op1));
1491 /* The range spanned by all instructions in the object is less
1492 than 2^31 bytes (2GB) and the distance from any instruction
1493 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1494 than 2^31 bytes (2GB).
1496 The executable can be placed anywhere in the virtual address
1499 sethi %hh(symbol), %temp1
1500 sethi %lm(symbol), %temp2
1501 or %temp1, %hm(symbol), %temp3
1502 or %temp2, %lo(symbol), %temp4
1503 sllx %temp3, 32, %temp5
1504 or %temp4, %temp5, %reg */
1506 /* It is possible that one of the registers we got for operands[2]
1507 might coincide with that of operands[0] (which is why we made
1508 it TImode). Pick the other one to use as our scratch. */
1509 if (rtx_equal_p (temp1, op0))
1512 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1517 emit_insn (gen_sethh (op0, op1));
1518 emit_insn (gen_setlm (temp1, op1));
1519 emit_insn (gen_sethm (op0, op0, op1));
1520 emit_insn (gen_rtx_SET (VOIDmode, op0,
1521 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1522 emit_insn (gen_rtx_SET (VOIDmode, op0,
1523 gen_rtx_PLUS (DImode, op0, temp1)));
1524 emit_insn (gen_setlo (op0, op0, op1));
1528 /* Old old old backwards compatibility kruft here.
1529 Essentially it is MEDLOW with a fixed 64-bit
1530 virtual base added to all data segment addresses.
1531 Text-segment stuff is computed like MEDANY, we can't
1532 reuse the code above because the relocation knobs
1535 Data segment: sethi %hi(symbol), %temp1
1536 or %temp1, %lo(symbol), %temp2
1537 add %temp2, EMBMEDANY_BASE_REG, %reg
1539 Text segment: sethi %uhi(symbol), %temp1
1540 sethi %hi(symbol), %temp2
1541 or %temp1, %ulo(symbol), %temp3
1542 or %temp2, %lo(symbol), %temp4
1543 sllx %temp3, 32, %temp5
1544 or %temp4, %temp5, %reg */
1545 if (data_segment_operand (op1, GET_MODE (op1)))
1547 emit_insn (gen_embmedany_sethi (temp1, op1));
1548 emit_insn (gen_embmedany_brsum (op0, temp1));
1549 emit_insn (gen_embmedany_losum (op0, op0, op1));
1553 /* It is possible that one of the registers we got for operands[2]
1554 might coincide with that of operands[0] (which is why we made
1555 it TImode). Pick the other one to use as our scratch. */
1556 if (rtx_equal_p (temp1, op0))
1559 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1564 emit_insn (gen_embmedany_textuhi (op0, op1));
1565 emit_insn (gen_embmedany_texthi (temp1, op1));
1566 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1567 emit_insn (gen_rtx_SET (VOIDmode, op0,
1568 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1569 emit_insn (gen_rtx_SET (VOIDmode, op0,
1570 gen_rtx_PLUS (DImode, op0, temp1)));
1571 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1580 /* These avoid problems when cross compiling. If we do not
1581 go through all this hair then the optimizer will see
1582 invalid REG_EQUAL notes or in some cases none at all. */
1583 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1584 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1585 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1586 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1588 #if HOST_BITS_PER_WIDE_INT == 64
1589 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1590 #define GEN_INT64(__x) GEN_INT (__x)
1592 #define GEN_HIGHINT64(__x) \
1593 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1594 #define GEN_INT64(__x) \
1595 immed_double_const ((__x) & 0xffffffff, \
1596 ((__x) & 0x80000000 ? -1 : 0), DImode)
1599 /* The optimizer is not to assume anything about exactly
1600 which bits are set for a HIGH, they are unspecified.
1601 Unfortunately this leads to many missed optimizations
1602 during CSE. We mask out the non-HIGH bits, and matches
1603 a plain movdi, to alleviate this problem. */
1605 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1607 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1611 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1613 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1617 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1619 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1623 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1625 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1628 /* Worker routines for 64-bit constant formation on arch64.
1629 One of the key things to be doing in these emissions is
1630 to create as many temp REGs as possible. This makes it
1631 possible for half-built constants to be used later when
1632 such values are similar to something required later on.
1633 Without doing this, the optimizer cannot see such
1636 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1637 unsigned HOST_WIDE_INT, int);
1640 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1641 unsigned HOST_WIDE_INT low_bits, int is_neg)
1643 unsigned HOST_WIDE_INT high_bits;
1646 high_bits = (~low_bits) & 0xffffffff;
1648 high_bits = low_bits;
1650 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1653 emit_insn (gen_rtx_SET (VOIDmode, op0,
1654 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1658 /* If we are XOR'ing with -1, then we should emit a one's complement
1659 instead. This way the combiner will notice logical operations
1660 such as ANDN later on and substitute. */
1661 if ((low_bits & 0x3ff) == 0x3ff)
1663 emit_insn (gen_rtx_SET (VOIDmode, op0,
1664 gen_rtx_NOT (DImode, temp)));
1668 emit_insn (gen_rtx_SET (VOIDmode, op0,
1669 gen_safe_XOR64 (temp,
1670 (-(HOST_WIDE_INT)0x400
1671 | (low_bits & 0x3ff)))));
1676 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1677 unsigned HOST_WIDE_INT, int);
1680 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1681 unsigned HOST_WIDE_INT high_bits,
1682 unsigned HOST_WIDE_INT low_immediate,
1687 if ((high_bits & 0xfffffc00) != 0)
1689 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1690 if ((high_bits & ~0xfffffc00) != 0)
1691 emit_insn (gen_rtx_SET (VOIDmode, op0,
1692 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1698 emit_insn (gen_safe_SET64 (temp, high_bits));
1702 /* Now shift it up into place. */
1703 emit_insn (gen_rtx_SET (VOIDmode, op0,
1704 gen_rtx_ASHIFT (DImode, temp2,
1705 GEN_INT (shift_count))));
1707 /* If there is a low immediate part piece, finish up by
1708 putting that in as well. */
1709 if (low_immediate != 0)
1710 emit_insn (gen_rtx_SET (VOIDmode, op0,
1711 gen_safe_OR64 (op0, low_immediate)));
1714 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1715 unsigned HOST_WIDE_INT);
1717 /* Full 64-bit constant decomposition. Even though this is the
1718 'worst' case, we still optimize a few things away. */
1720 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1721 unsigned HOST_WIDE_INT high_bits,
1722 unsigned HOST_WIDE_INT low_bits)
1726 if (reload_in_progress || reload_completed)
1729 sub_temp = gen_reg_rtx (DImode);
1731 if ((high_bits & 0xfffffc00) != 0)
1733 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1734 if ((high_bits & ~0xfffffc00) != 0)
1735 emit_insn (gen_rtx_SET (VOIDmode,
1737 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1743 emit_insn (gen_safe_SET64 (temp, high_bits));
1747 if (!reload_in_progress && !reload_completed)
1749 rtx temp2 = gen_reg_rtx (DImode);
1750 rtx temp3 = gen_reg_rtx (DImode);
1751 rtx temp4 = gen_reg_rtx (DImode);
1753 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1754 gen_rtx_ASHIFT (DImode, sub_temp,
1757 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1758 if ((low_bits & ~0xfffffc00) != 0)
1760 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1761 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1762 emit_insn (gen_rtx_SET (VOIDmode, op0,
1763 gen_rtx_PLUS (DImode, temp4, temp3)));
1767 emit_insn (gen_rtx_SET (VOIDmode, op0,
1768 gen_rtx_PLUS (DImode, temp4, temp2)));
1773 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1774 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1775 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1778 /* We are in the middle of reload, so this is really
1779 painful. However we do still make an attempt to
1780 avoid emitting truly stupid code. */
1781 if (low1 != const0_rtx)
1783 emit_insn (gen_rtx_SET (VOIDmode, op0,
1784 gen_rtx_ASHIFT (DImode, sub_temp,
1785 GEN_INT (to_shift))));
1786 emit_insn (gen_rtx_SET (VOIDmode, op0,
1787 gen_rtx_IOR (DImode, op0, low1)));
1795 if (low2 != const0_rtx)
1797 emit_insn (gen_rtx_SET (VOIDmode, op0,
1798 gen_rtx_ASHIFT (DImode, sub_temp,
1799 GEN_INT (to_shift))));
1800 emit_insn (gen_rtx_SET (VOIDmode, op0,
1801 gen_rtx_IOR (DImode, op0, low2)));
1809 emit_insn (gen_rtx_SET (VOIDmode, op0,
1810 gen_rtx_ASHIFT (DImode, sub_temp,
1811 GEN_INT (to_shift))));
1812 if (low3 != const0_rtx)
1813 emit_insn (gen_rtx_SET (VOIDmode, op0,
1814 gen_rtx_IOR (DImode, op0, low3)));
1819 /* Analyze a 64-bit constant for certain properties. */
1820 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1821 unsigned HOST_WIDE_INT,
1822 int *, int *, int *);
1825 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1826 unsigned HOST_WIDE_INT low_bits,
1827 int *hbsp, int *lbsp, int *abbasp)
1829 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1832 lowest_bit_set = highest_bit_set = -1;
1836 if ((lowest_bit_set == -1)
1837 && ((low_bits >> i) & 1))
1839 if ((highest_bit_set == -1)
1840 && ((high_bits >> (32 - i - 1)) & 1))
1841 highest_bit_set = (64 - i - 1);
1844 && ((highest_bit_set == -1)
1845 || (lowest_bit_set == -1)));
1851 if ((lowest_bit_set == -1)
1852 && ((high_bits >> i) & 1))
1853 lowest_bit_set = i + 32;
1854 if ((highest_bit_set == -1)
1855 && ((low_bits >> (32 - i - 1)) & 1))
1856 highest_bit_set = 32 - i - 1;
1859 && ((highest_bit_set == -1)
1860 || (lowest_bit_set == -1)));
1862 /* If there are no bits set this should have gone out
1863 as one instruction! */
1864 if (lowest_bit_set == -1
1865 || highest_bit_set == -1)
1867 all_bits_between_are_set = 1;
1868 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1872 if ((low_bits & (1 << i)) != 0)
1877 if ((high_bits & (1 << (i - 32))) != 0)
1880 all_bits_between_are_set = 0;
1883 *hbsp = highest_bit_set;
1884 *lbsp = lowest_bit_set;
1885 *abbasp = all_bits_between_are_set;
1888 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1891 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1892 unsigned HOST_WIDE_INT low_bits)
1894 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1897 || high_bits == 0xffffffff)
1900 analyze_64bit_constant (high_bits, low_bits,
1901 &highest_bit_set, &lowest_bit_set,
1902 &all_bits_between_are_set);
1904 if ((highest_bit_set == 63
1905 || lowest_bit_set == 0)
1906 && all_bits_between_are_set != 0)
1909 if ((highest_bit_set - lowest_bit_set) < 21)
1915 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1916 unsigned HOST_WIDE_INT,
1919 static unsigned HOST_WIDE_INT
1920 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1921 unsigned HOST_WIDE_INT low_bits,
1922 int lowest_bit_set, int shift)
1924 HOST_WIDE_INT hi, lo;
1926 if (lowest_bit_set < 32)
1928 lo = (low_bits >> lowest_bit_set) << shift;
1929 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1934 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1941 /* Here we are sure to be arch64 and this is an integer constant
1942 being loaded into a register. Emit the most efficient
1943 insn sequence possible. Detection of all the 1-insn cases
1944 has been done already. */
1946 sparc_emit_set_const64 (rtx op0, rtx op1)
1948 unsigned HOST_WIDE_INT high_bits, low_bits;
1949 int lowest_bit_set, highest_bit_set;
1950 int all_bits_between_are_set;
1953 /* Sanity check that we know what we are working with. */
1954 if (! TARGET_ARCH64)
1957 if (GET_CODE (op0) != SUBREG)
1959 if (GET_CODE (op0) != REG
1960 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1961 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1965 if (reload_in_progress || reload_completed)
1968 temp = gen_reg_rtx (DImode);
1970 if (GET_CODE (op1) != CONST_DOUBLE
1971 && GET_CODE (op1) != CONST_INT)
1973 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1977 if (GET_CODE (op1) == CONST_DOUBLE)
1979 #if HOST_BITS_PER_WIDE_INT == 64
1980 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1981 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1983 high_bits = CONST_DOUBLE_HIGH (op1);
1984 low_bits = CONST_DOUBLE_LOW (op1);
1989 #if HOST_BITS_PER_WIDE_INT == 64
1990 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1991 low_bits = (INTVAL (op1) & 0xffffffff);
1993 high_bits = ((INTVAL (op1) < 0) ?
1996 low_bits = INTVAL (op1);
2000 /* low_bits bits 0 --> 31
2001 high_bits bits 32 --> 63 */
2003 analyze_64bit_constant (high_bits, low_bits,
2004 &highest_bit_set, &lowest_bit_set,
2005 &all_bits_between_are_set);
2007 /* First try for a 2-insn sequence. */
2009 /* These situations are preferred because the optimizer can
2010 * do more things with them:
2012 * sllx %reg, shift, %reg
2014 * srlx %reg, shift, %reg
2015 * 3) mov some_small_const, %reg
2016 * sllx %reg, shift, %reg
2018 if (((highest_bit_set == 63
2019 || lowest_bit_set == 0)
2020 && all_bits_between_are_set != 0)
2021 || ((highest_bit_set - lowest_bit_set) < 12))
2023 HOST_WIDE_INT the_const = -1;
2024 int shift = lowest_bit_set;
2026 if ((highest_bit_set != 63
2027 && lowest_bit_set != 0)
2028 || all_bits_between_are_set == 0)
2031 create_simple_focus_bits (high_bits, low_bits,
2034 else if (lowest_bit_set == 0)
2035 shift = -(63 - highest_bit_set);
2037 if (! SPARC_SIMM13_P (the_const))
2040 emit_insn (gen_safe_SET64 (temp, the_const));
2042 emit_insn (gen_rtx_SET (VOIDmode,
2044 gen_rtx_ASHIFT (DImode,
2048 emit_insn (gen_rtx_SET (VOIDmode,
2050 gen_rtx_LSHIFTRT (DImode,
2052 GEN_INT (-shift))));
2058 /* Now a range of 22 or less bits set somewhere.
2059 * 1) sethi %hi(focus_bits), %reg
2060 * sllx %reg, shift, %reg
2061 * 2) sethi %hi(focus_bits), %reg
2062 * srlx %reg, shift, %reg
2064 if ((highest_bit_set - lowest_bit_set) < 21)
2066 unsigned HOST_WIDE_INT focus_bits =
2067 create_simple_focus_bits (high_bits, low_bits,
2068 lowest_bit_set, 10);
2070 if (! SPARC_SETHI_P (focus_bits))
2073 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2075 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2076 if (lowest_bit_set < 10)
2077 emit_insn (gen_rtx_SET (VOIDmode,
2079 gen_rtx_LSHIFTRT (DImode, temp,
2080 GEN_INT (10 - lowest_bit_set))));
2081 else if (lowest_bit_set > 10)
2082 emit_insn (gen_rtx_SET (VOIDmode,
2084 gen_rtx_ASHIFT (DImode, temp,
2085 GEN_INT (lowest_bit_set - 10))));
2091 /* 1) sethi %hi(low_bits), %reg
2092 * or %reg, %lo(low_bits), %reg
2093 * 2) sethi %hi(~low_bits), %reg
2094 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2097 || high_bits == 0xffffffff)
2099 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2100 (high_bits == 0xffffffff));
2104 /* Now, try 3-insn sequences. */
2106 /* 1) sethi %hi(high_bits), %reg
2107 * or %reg, %lo(high_bits), %reg
2108 * sllx %reg, 32, %reg
2112 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2116 /* We may be able to do something quick
2117 when the constant is negated, so try that. */
2118 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2119 (~low_bits) & 0xfffffc00))
2121 /* NOTE: The trailing bits get XOR'd so we need the
2122 non-negated bits, not the negated ones. */
2123 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2125 if ((((~high_bits) & 0xffffffff) == 0
2126 && ((~low_bits) & 0x80000000) == 0)
2127 || (((~high_bits) & 0xffffffff) == 0xffffffff
2128 && ((~low_bits) & 0x80000000) != 0))
2130 int fast_int = (~low_bits & 0xffffffff);
2132 if ((SPARC_SETHI_P (fast_int)
2133 && (~high_bits & 0xffffffff) == 0)
2134 || SPARC_SIMM13_P (fast_int))
2135 emit_insn (gen_safe_SET64 (temp, fast_int));
2137 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2142 #if HOST_BITS_PER_WIDE_INT == 64
2143 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2144 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2146 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2147 (~high_bits) & 0xffffffff,
2150 sparc_emit_set_const64 (temp, negated_const);
2153 /* If we are XOR'ing with -1, then we should emit a one's complement
2154 instead. This way the combiner will notice logical operations
2155 such as ANDN later on and substitute. */
2156 if (trailing_bits == 0x3ff)
2158 emit_insn (gen_rtx_SET (VOIDmode, op0,
2159 gen_rtx_NOT (DImode, temp)));
2163 emit_insn (gen_rtx_SET (VOIDmode,
2165 gen_safe_XOR64 (temp,
2166 (-0x400 | trailing_bits))));
2171 /* 1) sethi %hi(xxx), %reg
2172 * or %reg, %lo(xxx), %reg
2173 * sllx %reg, yyy, %reg
2175 * ??? This is just a generalized version of the low_bits==0
2176 * thing above, FIXME...
2178 if ((highest_bit_set - lowest_bit_set) < 32)
2180 unsigned HOST_WIDE_INT focus_bits =
2181 create_simple_focus_bits (high_bits, low_bits,
2184 /* We can't get here in this state. */
2185 if (highest_bit_set < 32
2186 || lowest_bit_set >= 32)
2189 /* So what we know is that the set bits straddle the
2190 middle of the 64-bit word. */
2191 sparc_emit_set_const64_quick2 (op0, temp,
2197 /* 1) sethi %hi(high_bits), %reg
2198 * or %reg, %lo(high_bits), %reg
2199 * sllx %reg, 32, %reg
2200 * or %reg, low_bits, %reg
2202 if (SPARC_SIMM13_P(low_bits)
2203 && ((int)low_bits > 0))
2205 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2209 /* The easiest way when all else fails, is full decomposition. */
2211 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2212 high_bits, low_bits, ~high_bits, ~low_bits);
2214 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2217 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2218 return the mode to be used for the comparison. For floating-point,
2219 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2220 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2221 processing is needed. */
2224 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2226 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2252 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2253 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2255 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2256 return CCX_NOOVmode;
2262 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2269 /* X and Y are two things to compare using CODE. Emit the compare insn and
2270 return the rtx for the cc reg in the proper mode. */
2273 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2275 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2278 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2279 fcc regs (cse can't tell they're really call clobbered regs and will
2280 remove a duplicate comparison even if there is an intervening function
2281 call - it will then try to reload the cc reg via an int reg which is why
2282 we need the movcc patterns). It is possible to provide the movcc
2283 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2284 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2285 to tell cse that CCFPE mode registers (even pseudos) are call
2288 /* ??? This is an experiment. Rather than making changes to cse which may
2289 or may not be easy/clean, we do our own cse. This is possible because
2290 we will generate hard registers. Cse knows they're call clobbered (it
2291 doesn't know the same thing about pseudos). If we guess wrong, no big
2292 deal, but if we win, great! */
2294 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2295 #if 1 /* experiment */
2298 /* We cycle through the registers to ensure they're all exercised. */
2299 static int next_fcc_reg = 0;
2300 /* Previous x,y for each fcc reg. */
2301 static rtx prev_args[4][2];
2303 /* Scan prev_args for x,y. */
2304 for (reg = 0; reg < 4; reg++)
2305 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2310 prev_args[reg][0] = x;
2311 prev_args[reg][1] = y;
2312 next_fcc_reg = (next_fcc_reg + 1) & 3;
2314 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2317 cc_reg = gen_reg_rtx (mode);
2318 #endif /* ! experiment */
2319 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2320 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2322 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2324 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2325 gen_rtx_COMPARE (mode, x, y)));
2330 /* This function is used for v9 only.
2331 CODE is the code for an Scc's comparison.
2332 OPERANDS[0] is the target of the Scc insn.
2333 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2334 been generated yet).
2336 This function is needed to turn
2339 (gt (reg:CCX 100 %icc)
2343 (gt:DI (reg:CCX 100 %icc)
2346 IE: The instruction recognizer needs to see the mode of the comparison to
2347 find the right instruction. We could use "gt:DI" right in the
2348 define_expand, but leaving it out allows us to handle DI, SI, etc.
2350 We refer to the global sparc compare operands sparc_compare_op0 and
2351 sparc_compare_op1. */
2354 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2359 && (GET_MODE (sparc_compare_op0) == DImode
2360 || GET_MODE (operands[0]) == DImode))
2363 op0 = sparc_compare_op0;
2364 op1 = sparc_compare_op1;
2366 /* Try to use the movrCC insns. */
2368 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2369 && op1 == const0_rtx
2370 && v9_regcmp_p (compare_code))
2372 /* Special case for op0 != 0. This can be done with one instruction if
2373 operands[0] == sparc_compare_op0. */
2375 if (compare_code == NE
2376 && GET_MODE (operands[0]) == DImode
2377 && rtx_equal_p (op0, operands[0]))
2379 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2380 gen_rtx_IF_THEN_ELSE (DImode,
2381 gen_rtx_fmt_ee (compare_code, DImode,
2388 if (reg_overlap_mentioned_p (operands[0], op0))
2390 /* Handle the case where operands[0] == sparc_compare_op0.
2391 We "early clobber" the result. */
2392 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2393 emit_move_insn (op0, sparc_compare_op0);
2396 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2397 if (GET_MODE (op0) != DImode)
2399 temp = gen_reg_rtx (DImode);
2400 convert_move (temp, op0, 0);
2404 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2405 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2406 gen_rtx_fmt_ee (compare_code, DImode,
2414 operands[1] = gen_compare_reg (compare_code, op0, op1);
2416 switch (GET_MODE (operands[1]))
2426 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2427 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2428 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2429 gen_rtx_fmt_ee (compare_code,
2430 GET_MODE (operands[1]),
2431 operands[1], const0_rtx),
2432 const1_rtx, operands[0])));
2437 /* Emit a conditional jump insn for the v9 architecture using comparison code
2438 CODE and jump target LABEL.
2439 This function exists to take advantage of the v9 brxx insns. */
2442 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2444 emit_jump_insn (gen_rtx_SET (VOIDmode,
2446 gen_rtx_IF_THEN_ELSE (VOIDmode,
2447 gen_rtx_fmt_ee (code, GET_MODE (op0),
2449 gen_rtx_LABEL_REF (VOIDmode, label),
2453 /* Generate a DFmode part of a hard TFmode register.
2454 REG is the TFmode hard register, LOW is 1 for the
2455 low 64bit of the register and 0 otherwise.
2458 gen_df_reg (rtx reg, int low)
2460 int regno = REGNO (reg);
2462 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2463 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2464 return gen_rtx_REG (DFmode, regno);
2467 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2468 Unlike normal calls, TFmode operands are passed by reference. It is
2469 assumed that no more than 3 operands are required. */
2472 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2474 rtx ret_slot = NULL, arg[3], func_sym;
2477 /* We only expect to be called for conversions, unary, and binary ops. */
2478 if (nargs < 2 || nargs > 3)
2481 for (i = 0; i < nargs; ++i)
2483 rtx this_arg = operands[i];
2486 /* TFmode arguments and return values are passed by reference. */
2487 if (GET_MODE (this_arg) == TFmode)
2489 int force_stack_temp;
2491 force_stack_temp = 0;
2492 if (TARGET_BUGGY_QP_LIB && i == 0)
2493 force_stack_temp = 1;
2495 if (GET_CODE (this_arg) == MEM
2496 && ! force_stack_temp)
2497 this_arg = XEXP (this_arg, 0);
2498 else if (CONSTANT_P (this_arg)
2499 && ! force_stack_temp)
2501 this_slot = force_const_mem (TFmode, this_arg);
2502 this_arg = XEXP (this_slot, 0);
2506 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2508 /* Operand 0 is the return value. We'll copy it out later. */
2510 emit_move_insn (this_slot, this_arg);
2512 ret_slot = this_slot;
2514 this_arg = XEXP (this_slot, 0);
2521 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2523 if (GET_MODE (operands[0]) == TFmode)
2526 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2527 arg[0], GET_MODE (arg[0]),
2528 arg[1], GET_MODE (arg[1]));
2530 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2531 arg[0], GET_MODE (arg[0]),
2532 arg[1], GET_MODE (arg[1]),
2533 arg[2], GET_MODE (arg[2]));
2536 emit_move_insn (operands[0], ret_slot);
2545 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2546 GET_MODE (operands[0]), 1,
2547 arg[1], GET_MODE (arg[1]));
2549 if (ret != operands[0])
2550 emit_move_insn (operands[0], ret);
2554 /* Expand soft-float TFmode calls to sparc abi routines. */
2557 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2579 emit_soft_tfmode_libcall (func, 3, operands);
2583 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2596 emit_soft_tfmode_libcall (func, 2, operands);
2600 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2607 switch (GET_MODE (operands[1]))
2620 case FLOAT_TRUNCATE:
2621 switch (GET_MODE (operands[0]))
2635 switch (GET_MODE (operands[1]))
2648 case UNSIGNED_FLOAT:
2649 switch (GET_MODE (operands[1]))
2663 switch (GET_MODE (operands[0]))
2677 switch (GET_MODE (operands[0]))
2694 emit_soft_tfmode_libcall (func, 2, operands);
2697 /* Expand a hard-float tfmode operation. All arguments must be in
2701 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2705 if (GET_RTX_CLASS (code) == RTX_UNARY)
2707 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2708 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2712 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2713 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2714 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2715 operands[1], operands[2]);
2718 if (register_operand (operands[0], VOIDmode))
2721 dest = gen_reg_rtx (GET_MODE (operands[0]));
2723 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2725 if (dest != operands[0])
2726 emit_move_insn (operands[0], dest);
2730 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2732 if (TARGET_HARD_QUAD)
2733 emit_hard_tfmode_operation (code, operands);
2735 emit_soft_tfmode_binop (code, operands);
2739 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2741 if (TARGET_HARD_QUAD)
2742 emit_hard_tfmode_operation (code, operands);
2744 emit_soft_tfmode_unop (code, operands);
2748 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2750 if (TARGET_HARD_QUAD)
2751 emit_hard_tfmode_operation (code, operands);
2753 emit_soft_tfmode_cvt (code, operands);
2756 /* Return nonzero if a branch/jump/call instruction will be emitting
2757 nop into its delay slot. */
2760 empty_delay_slot (rtx insn)
2764 /* If no previous instruction (should not happen), return true. */
2765 if (PREV_INSN (insn) == NULL)
2768 seq = NEXT_INSN (PREV_INSN (insn));
2769 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2775 /* Return nonzero if TRIAL can go into the call delay slot. */
2778 tls_call_delay (rtx trial)
2783 call __tls_get_addr, %tgd_call (foo)
2784 add %l7, %o0, %o0, %tgd_add (foo)
2785 while Sun as/ld does not. */
2786 if (TARGET_GNU_TLS || !TARGET_TLS)
2789 pat = PATTERN (trial);
2790 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2793 unspec = XEXP (SET_DEST (pat), 1);
2794 if (GET_CODE (unspec) != UNSPEC
2795 || (XINT (unspec, 1) != UNSPEC_TLSGD
2796 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2802 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2803 instruction. RETURN_P is true if the v9 variant 'return' is to be
2804 considered in the test too.
2806 TRIAL must be a SET whose destination is a REG appropriate for the
2807 'restore' instruction or, if RETURN_P is true, for the 'return'
2811 eligible_for_restore_insn (rtx trial, bool return_p)
2813 rtx pat = PATTERN (trial);
2814 rtx src = SET_SRC (pat);
2816 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2817 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2818 && arith_operand (src, GET_MODE (src)))
2821 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2823 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2826 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2827 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2828 && arith_double_operand (src, GET_MODE (src)))
2829 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2831 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2832 else if (! TARGET_FPU && register_operand (src, SFmode))
2835 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2836 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
2839 /* If we have the 'return' instruction, anything that does not use
2840 local or output registers and can go into a delay slot wins. */
2841 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
2842 && (get_attr_in_uncond_branch_delay (trial)
2843 == IN_UNCOND_BRANCH_DELAY_TRUE))
2846 /* The 'restore src1,src2,dest' pattern for SImode. */
2847 else if (GET_CODE (src) == PLUS
2848 && register_operand (XEXP (src, 0), SImode)
2849 && arith_operand (XEXP (src, 1), SImode))
2852 /* The 'restore src1,src2,dest' pattern for DImode. */
2853 else if (GET_CODE (src) == PLUS
2854 && register_operand (XEXP (src, 0), DImode)
2855 && arith_double_operand (XEXP (src, 1), DImode))
2858 /* The 'restore src1,%lo(src2),dest' pattern. */
2859 else if (GET_CODE (src) == LO_SUM
2860 && ! TARGET_CM_MEDMID
2861 && ((register_operand (XEXP (src, 0), SImode)
2862 && immediate_operand (XEXP (src, 1), SImode))
2864 && register_operand (XEXP (src, 0), DImode)
2865 && immediate_operand (XEXP (src, 1), DImode))))
2868 /* The 'restore src,src,dest' pattern. */
2869 else if (GET_CODE (src) == ASHIFT
2870 && (register_operand (XEXP (src, 0), SImode)
2871 || register_operand (XEXP (src, 0), DImode))
2872 && XEXP (src, 1) == const1_rtx)
2878 /* Return nonzero if TRIAL can go into the function return's
2882 eligible_for_return_delay (rtx trial)
2884 int leaf_function_p = current_function_uses_only_leaf_regs;
2887 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2890 if (get_attr_length (trial) != 1)
2893 /* If there are any call-saved registers, we should scan TRIAL if it
2894 does not reference them. For now just make it easy. */
2898 /* If the function uses __builtin_eh_return, the eh_return machinery
2899 occupies the delay slot. */
2900 if (current_function_calls_eh_return)
2903 /* In the case of a true leaf function, anything can go into the slot. */
2904 if (leaf_function_p)
2905 return get_attr_in_uncond_branch_delay (trial)
2906 == IN_UNCOND_BRANCH_DELAY_TRUE;
2908 pat = PATTERN (trial);
2910 /* Otherwise, only operations which can be done in tandem with
2911 a `restore' or `return' insn can go into the delay slot. */
2912 if (GET_CODE (SET_DEST (pat)) != REG
2913 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2916 /* If this instruction sets up floating point register and we have a return
2917 instruction, it can probably go in. But restore will not work
2919 if (REGNO (SET_DEST (pat)) >= 32)
2921 && ! epilogue_renumber (&pat, 1)
2922 && (get_attr_in_uncond_branch_delay (trial)
2923 == IN_UNCOND_BRANCH_DELAY_TRUE));
2925 return eligible_for_restore_insn (trial, true);
2928 /* Return nonzero if TRIAL can go into the sibling call's
2932 eligible_for_sibcall_delay (rtx trial)
2934 int leaf_function_p = current_function_uses_only_leaf_regs;
2937 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2940 if (get_attr_length (trial) != 1)
2943 pat = PATTERN (trial);
2945 if (leaf_function_p)
2947 /* If the tail call is done using the call instruction,
2948 we have to restore %o7 in the delay slot. */
2949 if (LEAF_SIBCALL_SLOT_RESERVED_P)
2952 /* %g1 is used to build the function address */
2953 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2959 /* Otherwise, only operations which can be done in tandem with
2960 a `restore' insn can go into the delay slot. */
2961 if (GET_CODE (SET_DEST (pat)) != REG
2962 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
2963 || REGNO (SET_DEST (pat)) >= 32)
2966 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2968 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2971 return eligible_for_restore_insn (trial, false);
2975 short_branch (int uid1, int uid2)
2977 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
2979 /* Leave a few words of "slop". */
2980 if (delta >= -1023 && delta <= 1022)
2986 /* Return nonzero if REG is not used after INSN.
2987 We assume REG is a reload reg, and therefore does
2988 not live past labels or calls or jumps. */
2990 reg_unused_after (rtx reg, rtx insn)
2992 enum rtx_code code, prev_code = UNKNOWN;
2994 while ((insn = NEXT_INSN (insn)))
2996 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2999 code = GET_CODE (insn);
3000 if (GET_CODE (insn) == CODE_LABEL)
3005 rtx set = single_set (insn);
3006 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3009 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3011 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3019 /* Determine if it's legal to put X into the constant pool. This
3020 is not possible if X contains the address of a symbol that is
3021 not constant (TLS) or not known at final link time (PIC). */
3024 sparc_cannot_force_const_mem (rtx x)
3026 switch (GET_CODE (x))
3030 /* Accept all non-symbolic constants. */
3034 /* Labels are OK iff we are non-PIC. */
3035 return flag_pic != 0;
3038 /* 'Naked' TLS symbol references are never OK,
3039 non-TLS symbols are OK iff we are non-PIC. */
3040 if (SYMBOL_REF_TLS_MODEL (x))
3043 return flag_pic != 0;
3046 return sparc_cannot_force_const_mem (XEXP (x, 0));
3049 return sparc_cannot_force_const_mem (XEXP (x, 0))
3050 || sparc_cannot_force_const_mem (XEXP (x, 1));
3058 /* The table we use to reference PIC data. */
3059 static GTY(()) rtx global_offset_table;
3061 /* The function we use to get at it. */
3062 static GTY(()) rtx add_pc_to_pic_symbol;
3063 static GTY(()) char add_pc_to_pic_symbol_name[256];
3065 /* Ensure that we are not using patterns that are not OK with PIC. */
3073 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3074 || (GET_CODE (recog_data.operand[i]) == CONST
3075 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3076 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3077 == global_offset_table)
3078 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3087 /* Return true if X is an address which needs a temporary register when
3088 reloaded while generating PIC code. */
3091 pic_address_needs_scratch (rtx x)
3093 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3094 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3095 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3096 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3097 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3103 /* Determine if a given RTX is a valid constant. We already know this
3104 satisfies CONSTANT_P. */
3107 legitimate_constant_p (rtx x)
3111 switch (GET_CODE (x))
3114 /* TLS symbols are not constant. */
3115 if (SYMBOL_REF_TLS_MODEL (x))
3120 inner = XEXP (x, 0);
3122 /* Offsets of TLS symbols are never valid.
3123 Discourage CSE from creating them. */
3124 if (GET_CODE (inner) == PLUS
3125 && tls_symbolic_operand (XEXP (inner, 0)))
3130 if (GET_MODE (x) == VOIDmode)
3133 /* Floating point constants are generally not ok.
3134 The only exception is 0.0 in VIS. */
3136 && (GET_MODE (x) == SFmode
3137 || GET_MODE (x) == DFmode
3138 || GET_MODE (x) == TFmode)
3139 && fp_zero_operand (x, GET_MODE (x)))
3151 /* Determine if a given RTX is a valid constant address. */
3154 constant_address_p (rtx x)
3156 switch (GET_CODE (x))
3164 if (flag_pic && pic_address_needs_scratch (x))
3166 return legitimate_constant_p (x);
3169 return !flag_pic && legitimate_constant_p (x);
3176 /* Nonzero if the constant value X is a legitimate general operand
3177 when generating PIC code. It is given that flag_pic is on and
3178 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3181 legitimate_pic_operand_p (rtx x)
3183 if (pic_address_needs_scratch (x))
3185 if (tls_symbolic_operand (x)
3186 || (GET_CODE (x) == CONST
3187 && GET_CODE (XEXP (x, 0)) == PLUS
3188 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3193 /* Return nonzero if ADDR is a valid memory address.
3194 STRICT specifies whether strict register checking applies. */
3197 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3199 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3201 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3203 else if (GET_CODE (addr) == PLUS)
3205 rs1 = XEXP (addr, 0);
3206 rs2 = XEXP (addr, 1);
3208 /* Canonicalize. REG comes first, if there are no regs,
3209 LO_SUM comes first. */
3211 && GET_CODE (rs1) != SUBREG
3213 || GET_CODE (rs2) == SUBREG
3214 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3216 rs1 = XEXP (addr, 1);
3217 rs2 = XEXP (addr, 0);
3221 && rs1 == pic_offset_table_rtx
3223 && GET_CODE (rs2) != SUBREG
3224 && GET_CODE (rs2) != LO_SUM
3225 && GET_CODE (rs2) != MEM
3226 && !tls_symbolic_operand (rs2)
3227 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3228 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3230 || GET_CODE (rs1) == SUBREG)
3231 && RTX_OK_FOR_OFFSET_P (rs2)))
3236 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3237 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3239 /* We prohibit REG + REG for TFmode when there are no instructions
3240 which accept REG+REG instructions. We do this because REG+REG
3241 is not an offsetable address. If we get the situation in reload
3242 where source and destination of a movtf pattern are both MEMs with
3243 REG+REG address, then only one of them gets converted to an
3244 offsetable address. */
3246 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3247 && TARGET_HARD_QUAD))
3250 /* We prohibit REG + REG on ARCH32 if not optimizing for
3251 DFmode/DImode because then mem_min_alignment is likely to be zero
3252 after reload and the forced split would lack a matching splitter
3254 if (TARGET_ARCH32 && !optimize
3255 && (mode == DFmode || mode == DImode))
3258 else if (USE_AS_OFFSETABLE_LO10
3259 && GET_CODE (rs1) == LO_SUM
3261 && ! TARGET_CM_MEDMID
3262 && RTX_OK_FOR_OLO10_P (rs2))
3266 imm1 = XEXP (rs1, 1);
3267 rs1 = XEXP (rs1, 0);
3268 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3272 else if (GET_CODE (addr) == LO_SUM)
3274 rs1 = XEXP (addr, 0);
3275 imm1 = XEXP (addr, 1);
3277 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3280 /* We can't allow TFmode, because an offset greater than or equal to the
3281 alignment (8) may cause the LO_SUM to overflow if !v9. */
3282 if (mode == TFmode && !TARGET_V9)
3285 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3290 if (GET_CODE (rs1) == SUBREG)
3291 rs1 = SUBREG_REG (rs1);
3297 if (GET_CODE (rs2) == SUBREG)
3298 rs2 = SUBREG_REG (rs2);
3305 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3306 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3311 if ((REGNO (rs1) >= 32
3312 && REGNO (rs1) != FRAME_POINTER_REGNUM
3313 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3315 && (REGNO (rs2) >= 32
3316 && REGNO (rs2) != FRAME_POINTER_REGNUM
3317 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3323 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3325 static GTY(()) rtx sparc_tls_symbol;
3327 sparc_tls_get_addr (void)
3329 if (!sparc_tls_symbol)
3330 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3332 return sparc_tls_symbol;
3336 sparc_tls_got (void)
3341 current_function_uses_pic_offset_table = 1;
3342 return pic_offset_table_rtx;
3345 if (!global_offset_table)
3346 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3347 temp = gen_reg_rtx (Pmode);
3348 emit_move_insn (temp, global_offset_table);
3353 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3354 this (thread-local) address. */
3357 legitimize_tls_address (rtx addr)
3359 rtx temp1, temp2, temp3, ret, o0, got, insn;
3364 if (GET_CODE (addr) == SYMBOL_REF)
3365 switch (SYMBOL_REF_TLS_MODEL (addr))
3367 case TLS_MODEL_GLOBAL_DYNAMIC:
3369 temp1 = gen_reg_rtx (SImode);
3370 temp2 = gen_reg_rtx (SImode);
3371 ret = gen_reg_rtx (Pmode);
3372 o0 = gen_rtx_REG (Pmode, 8);
3373 got = sparc_tls_got ();
3374 emit_insn (gen_tgd_hi22 (temp1, addr));
3375 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3378 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3379 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3384 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3385 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3388 CALL_INSN_FUNCTION_USAGE (insn)
3389 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3390 CALL_INSN_FUNCTION_USAGE (insn));
3391 insn = get_insns ();
3393 emit_libcall_block (insn, ret, o0, addr);
3396 case TLS_MODEL_LOCAL_DYNAMIC:
3398 temp1 = gen_reg_rtx (SImode);
3399 temp2 = gen_reg_rtx (SImode);
3400 temp3 = gen_reg_rtx (Pmode);
3401 ret = gen_reg_rtx (Pmode);
3402 o0 = gen_rtx_REG (Pmode, 8);
3403 got = sparc_tls_got ();
3404 emit_insn (gen_tldm_hi22 (temp1));
3405 emit_insn (gen_tldm_lo10 (temp2, temp1));
3408 emit_insn (gen_tldm_add32 (o0, got, temp2));
3409 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3414 emit_insn (gen_tldm_add64 (o0, got, temp2));
3415 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3418 CALL_INSN_FUNCTION_USAGE (insn)
3419 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3420 CALL_INSN_FUNCTION_USAGE (insn));
3421 insn = get_insns ();
3423 emit_libcall_block (insn, temp3, o0,
3424 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3425 UNSPEC_TLSLD_BASE));
3426 temp1 = gen_reg_rtx (SImode);
3427 temp2 = gen_reg_rtx (SImode);
3428 emit_insn (gen_tldo_hix22 (temp1, addr));
3429 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3431 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3433 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3436 case TLS_MODEL_INITIAL_EXEC:
3437 temp1 = gen_reg_rtx (SImode);
3438 temp2 = gen_reg_rtx (SImode);
3439 temp3 = gen_reg_rtx (Pmode);
3440 got = sparc_tls_got ();
3441 emit_insn (gen_tie_hi22 (temp1, addr));
3442 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3444 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3446 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3449 ret = gen_reg_rtx (Pmode);
3451 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3454 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3458 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3461 case TLS_MODEL_LOCAL_EXEC:
3462 temp1 = gen_reg_rtx (Pmode);
3463 temp2 = gen_reg_rtx (Pmode);
3466 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3467 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3471 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3472 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3474 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3482 abort (); /* for now ... */
3488 /* Legitimize PIC addresses. If the address is already position-independent,
3489 we return ORIG. Newly generated position-independent addresses go into a
3490 reg. This is REG if nonzero, otherwise we allocate register(s) as
3494 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3497 if (GET_CODE (orig) == SYMBOL_REF)
3499 rtx pic_ref, address;
3504 if (reload_in_progress || reload_completed)
3507 reg = gen_reg_rtx (Pmode);
3512 /* If not during reload, allocate another temp reg here for loading
3513 in the address, so that these instructions can be optimized
3515 rtx temp_reg = ((reload_in_progress || reload_completed)
3516 ? reg : gen_reg_rtx (Pmode));
3518 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3519 won't get confused into thinking that these two instructions
3520 are loading in the true address of the symbol. If in the
3521 future a PIC rtx exists, that should be used instead. */
3522 if (Pmode == SImode)
3524 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3525 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3529 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3530 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3537 pic_ref = gen_rtx_MEM (Pmode,
3538 gen_rtx_PLUS (Pmode,
3539 pic_offset_table_rtx, address));
3540 current_function_uses_pic_offset_table = 1;
3541 RTX_UNCHANGING_P (pic_ref) = 1;
3542 insn = emit_move_insn (reg, pic_ref);
3543 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3545 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3549 else if (GET_CODE (orig) == CONST)
3553 if (GET_CODE (XEXP (orig, 0)) == PLUS
3554 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3559 if (reload_in_progress || reload_completed)
3562 reg = gen_reg_rtx (Pmode);
3565 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3567 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3568 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3569 base == reg ? 0 : reg);
3574 if (GET_CODE (offset) == CONST_INT)
3576 if (SMALL_INT (offset))
3577 return plus_constant (base, INTVAL (offset));
3578 else if (! reload_in_progress && ! reload_completed)
3579 offset = force_reg (Pmode, offset);
3581 /* If we reach here, then something is seriously wrong. */
3584 return gen_rtx_PLUS (Pmode, base, offset);
3586 else if (GET_CODE (orig) == LABEL_REF)
3587 /* ??? Why do we do this? */
3588 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3589 the register is live instead, in case it is eliminated. */
3590 current_function_uses_pic_offset_table = 1;
3595 /* Try machine-dependent ways of modifying an illegitimate address X
3596 to be legitimate. If we find one, return the new, valid address.
3598 OLDX is the address as it was before break_out_memory_refs was called.
3599 In some cases it is useful to look at this to decide what needs to be done.
3601 MODE is the mode of the operand pointed to by X. */
3604 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3608 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3609 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3610 force_operand (XEXP (x, 0), NULL_RTX));
3611 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3612 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3613 force_operand (XEXP (x, 1), NULL_RTX));
3614 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3615 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3617 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3618 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3619 force_operand (XEXP (x, 1), NULL_RTX));
3621 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3624 if (tls_symbolic_operand (x))
3625 x = legitimize_tls_address (x);
3627 x = legitimize_pic_address (x, mode, 0);
3628 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3629 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3630 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3631 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3632 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3633 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3634 else if (GET_CODE (x) == SYMBOL_REF
3635 || GET_CODE (x) == CONST
3636 || GET_CODE (x) == LABEL_REF)
3637 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3641 /* Emit the special PIC prologue. */
3644 load_pic_register (void)
3646 int orig_flag_pic = flag_pic;
3648 /* If we haven't emitted the special helper function, do so now. */
3649 if (add_pc_to_pic_symbol_name[0] == 0)
3651 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3654 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3657 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3659 ASM_OUTPUT_ALIGN (asm_out_file, align);
3660 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3661 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3662 pic_name, pic_name);
3665 /* Initialize every time through, since we can't easily
3666 know this to be permanent. */
3667 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3668 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3671 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3672 add_pc_to_pic_symbol));
3673 flag_pic = orig_flag_pic;
3675 /* Need to emit this whether or not we obey regdecls,
3676 since setjmp/longjmp can cause life info to screw up.
3677 ??? In the case where we don't obey regdecls, this is not sufficient
3678 since we may not fall out the bottom. */
3679 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3682 /* Return 1 if RTX is a MEM which is known to be aligned to at
3683 least a DESIRED byte boundary. */
3686 mem_min_alignment (rtx mem, int desired)
3688 rtx addr, base, offset;
3690 /* If it's not a MEM we can't accept it. */
3691 if (GET_CODE (mem) != MEM)
3694 addr = XEXP (mem, 0);
3695 base = offset = NULL_RTX;
3696 if (GET_CODE (addr) == PLUS)
3698 if (GET_CODE (XEXP (addr, 0)) == REG)
3700 base = XEXP (addr, 0);
3702 /* What we are saying here is that if the base
3703 REG is aligned properly, the compiler will make
3704 sure any REG based index upon it will be so
3706 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3707 offset = XEXP (addr, 1);
3709 offset = const0_rtx;
3712 else if (GET_CODE (addr) == REG)
3715 offset = const0_rtx;
3718 if (base != NULL_RTX)
3720 int regno = REGNO (base);
3722 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3724 /* Check if the compiler has recorded some information
3725 about the alignment of the base REG. If reload has
3726 completed, we already matched with proper alignments.
3727 If not running global_alloc, reload might give us
3728 unaligned pointer to local stack though. */
3730 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3731 || (optimize && reload_completed))
3732 && (INTVAL (offset) & (desired - 1)) == 0)
3737 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3741 else if (! TARGET_UNALIGNED_DOUBLES
3742 || CONSTANT_P (addr)
3743 || GET_CODE (addr) == LO_SUM)
3745 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3746 is true, in which case we can only assume that an access is aligned if
3747 it is to a constant address, or the address involves a LO_SUM. */
3751 /* An obviously unaligned address. */
3756 /* Vectors to keep interesting information about registers where it can easily
3757 be got. We used to use the actual mode value as the bit number, but there
3758 are more than 32 modes now. Instead we use two tables: one indexed by
3759 hard register number, and one indexed by mode. */
3761 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3762 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3763 mapped into one sparc_mode_class mode. */
3765 enum sparc_mode_class {
3766 S_MODE, D_MODE, T_MODE, O_MODE,
3767 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3771 /* Modes for single-word and smaller quantities. */
3772 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3774 /* Modes for double-word and smaller quantities. */
3775 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3777 /* Modes for quad-word and smaller quantities. */
3778 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3780 /* Modes for 8-word and smaller quantities. */
3781 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3783 /* Modes for single-float quantities. We must allow any single word or
3784 smaller quantity. This is because the fix/float conversion instructions
3785 take integer inputs/outputs from the float registers. */
3786 #define SF_MODES (S_MODES)
3788 /* Modes for double-float and smaller quantities. */
3789 #define DF_MODES (S_MODES | D_MODES)
3791 /* Modes for double-float only quantities. */
3792 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3794 /* Modes for quad-float only quantities. */
3795 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3797 /* Modes for quad-float and smaller quantities. */
3798 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3800 /* Modes for quad-float and double-float quantities. */
3801 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3803 /* Modes for quad-float pair only quantities. */
3804 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3806 /* Modes for quad-float pairs and smaller quantities. */
3807 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3809 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3811 /* Modes for condition codes. */
3812 #define CC_MODES (1 << (int) CC_MODE)
3813 #define CCFP_MODES (1 << (int) CCFP_MODE)
3815 /* Value is 1 if register/mode pair is acceptable on sparc.
3816 The funny mixture of D and T modes is because integer operations
3817 do not specially operate on tetra quantities, so non-quad-aligned
3818 registers can hold quadword quantities (except %o4 and %i4 because
3819 they cross fixed registers). */
3821 /* This points to either the 32 bit or the 64 bit version. */
3822 const int *hard_regno_mode_classes;
3824 static const int hard_32bit_mode_classes[] = {
3825 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3826 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3827 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3828 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3830 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3831 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3832 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3833 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3835 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3836 and none can hold SFmode/SImode values. */
3837 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3838 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3839 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3840 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3843 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3849 static const int hard_64bit_mode_classes[] = {
3850 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3851 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3852 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3853 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3855 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3856 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3857 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3858 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3860 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3861 and none can hold SFmode/SImode values. */
3862 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3863 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3864 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3865 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3868 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3874 int sparc_mode_class [NUM_MACHINE_MODES];
3876 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3879 sparc_init_modes (void)
3883 for (i = 0; i < NUM_MACHINE_MODES; i++)
3885 switch (GET_MODE_CLASS (i))
3888 case MODE_PARTIAL_INT:
3889 case MODE_COMPLEX_INT:
3890 if (GET_MODE_SIZE (i) <= 4)
3891 sparc_mode_class[i] = 1 << (int) S_MODE;
3892 else if (GET_MODE_SIZE (i) == 8)
3893 sparc_mode_class[i] = 1 << (int) D_MODE;
3894 else if (GET_MODE_SIZE (i) == 16)
3895 sparc_mode_class[i] = 1 << (int) T_MODE;
3896 else if (GET_MODE_SIZE (i) == 32)
3897 sparc_mode_class[i] = 1 << (int) O_MODE;
3899 sparc_mode_class[i] = 0;
3902 case MODE_COMPLEX_FLOAT:
3903 if (GET_MODE_SIZE (i) <= 4)
3904 sparc_mode_class[i] = 1 << (int) SF_MODE;
3905 else if (GET_MODE_SIZE (i) == 8)
3906 sparc_mode_class[i] = 1 << (int) DF_MODE;
3907 else if (GET_MODE_SIZE (i) == 16)
3908 sparc_mode_class[i] = 1 << (int) TF_MODE;
3909 else if (GET_MODE_SIZE (i) == 32)
3910 sparc_mode_class[i] = 1 << (int) OF_MODE;
3912 sparc_mode_class[i] = 0;
3915 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3916 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3918 sparc_mode_class[i] = 1 << (int) CC_MODE;
3921 sparc_mode_class[i] = 0;
3927 hard_regno_mode_classes = hard_64bit_mode_classes;
3929 hard_regno_mode_classes = hard_32bit_mode_classes;
3931 /* Initialize the array used by REGNO_REG_CLASS. */
3932 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3934 if (i < 16 && TARGET_V8PLUS)
3935 sparc_regno_reg_class[i] = I64_REGS;
3936 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3937 sparc_regno_reg_class[i] = GENERAL_REGS;
3939 sparc_regno_reg_class[i] = FP_REGS;
3941 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3943 sparc_regno_reg_class[i] = FPCC_REGS;
3945 sparc_regno_reg_class[i] = NO_REGS;
3949 /* Compute the frame size required by the function. This function is called
3950 during the reload pass and also by sparc_expand_prologue. */
3953 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
3955 int outgoing_args_size = (current_function_outgoing_args_size
3956 + REG_PARM_STACK_SPACE (current_function_decl));
3957 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3962 for (i = 0; i < 8; i++)
3963 if (regs_ever_live[i] && ! call_used_regs[i])
3968 for (i = 0; i < 8; i += 2)
3969 if ((regs_ever_live[i] && ! call_used_regs[i])
3970 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3974 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3975 if ((regs_ever_live[i] && ! call_used_regs[i])
3976 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3979 /* Set up values for use in prologue and epilogue. */
3980 num_gfregs = n_regs;
3985 && current_function_outgoing_args_size == 0)
3986 actual_fsize = apparent_fsize = 0;
3989 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3990 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3991 apparent_fsize += n_regs * 4;
3992 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3995 /* Make sure nothing can clobber our register windows.
3996 If a SAVE must be done, or there is a stack-local variable,
3997 the register window area must be allocated.
3998 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3999 if (! leaf_function_p || size > 0)
4000 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4002 return SPARC_STACK_ALIGN (actual_fsize);
4005 /* Output any necessary .register pseudo-ops. */
4008 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4010 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4016 /* Check if %g[2367] were used without
4017 .register being printed for them already. */
4018 for (i = 2; i < 8; i++)
4020 if (regs_ever_live [i]
4021 && ! sparc_hard_reg_printed [i])
4023 sparc_hard_reg_printed [i] = 1;
4024 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4031 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4032 as needed. LOW should be double-word aligned for 32-bit registers.
4033 Return the new OFFSET. */
4036 #define SORR_RESTORE 1
4039 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4044 if (TARGET_ARCH64 && high <= 32)
4046 for (i = low; i < high; i++)
4048 if (regs_ever_live[i] && ! call_used_regs[i])
4050 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4051 set_mem_alias_set (mem, sparc_sr_alias_set);
4052 if (action == SORR_SAVE)
4054 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4055 RTX_FRAME_RELATED_P (insn) = 1;
4057 else /* action == SORR_RESTORE */
4058 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4065 for (i = low; i < high; i += 2)
4067 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4068 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4069 enum machine_mode mode;
4074 mode = i < 32 ? DImode : DFmode;
4079 mode = i < 32 ? SImode : SFmode;
4084 mode = i < 32 ? SImode : SFmode;
4091 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4092 set_mem_alias_set (mem, sparc_sr_alias_set);
4093 if (action == SORR_SAVE)
4095 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4096 RTX_FRAME_RELATED_P (insn) = 1;
4098 else /* action == SORR_RESTORE */
4099 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4101 /* Always preserve double-word alignment. */
4102 offset = (offset + 7) & -8;
4109 /* Emit code to save call-saved registers. */
4112 emit_save_regs (void)
4114 HOST_WIDE_INT offset;
4117 offset = frame_base_offset - apparent_fsize;
4119 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4121 /* ??? This might be optimized a little as %g1 might already have a
4122 value close enough that a single add insn will do. */
4123 /* ??? Although, all of this is probably only a temporary fix
4124 because if %g1 can hold a function result, then
4125 sparc_expand_epilogue will lose (the result will be
4127 base = gen_rtx_REG (Pmode, 1);
4128 emit_move_insn (base, GEN_INT (offset));
4129 emit_insn (gen_rtx_SET (VOIDmode,
4131 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4135 base = frame_base_reg;
4137 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4138 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4141 /* Emit code to restore call-saved registers. */
4144 emit_restore_regs (void)
4146 HOST_WIDE_INT offset;
4149 offset = frame_base_offset - apparent_fsize;
4151 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4153 base = gen_rtx_REG (Pmode, 1);
4154 emit_move_insn (base, GEN_INT (offset));
4155 emit_insn (gen_rtx_SET (VOIDmode,
4157 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4161 base = frame_base_reg;
4163 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4164 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4167 /* Emit an increment for the stack pointer. */
4170 emit_stack_pointer_increment (rtx increment)
4173 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4175 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4178 /* Emit a decrement for the stack pointer. */
4181 emit_stack_pointer_decrement (rtx decrement)
4184 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4186 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4189 /* Expand the function prologue. The prologue is responsible for reserving
4190 storage for the frame, saving the call-saved registers and loading the
4191 PIC register if needed. */
4194 sparc_expand_prologue (void)
4196 int leaf_function_p = current_function_uses_only_leaf_regs;
4198 /* Need to use actual_fsize, since we are also allocating
4199 space for our callee (and our own register save area). */
4200 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4202 if (leaf_function_p)
4204 frame_base_reg = stack_pointer_rtx;
4205 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4209 frame_base_reg = hard_frame_pointer_rtx;
4210 frame_base_offset = SPARC_STACK_BIAS;
4213 if (actual_fsize == 0)
4215 else if (leaf_function_p)
4217 if (actual_fsize <= 4096)
4218 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4219 else if (actual_fsize <= 8192)
4221 emit_stack_pointer_increment (GEN_INT (-4096));
4222 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4226 rtx reg = gen_rtx_REG (Pmode, 1);
4227 emit_move_insn (reg, GEN_INT (-actual_fsize));
4228 emit_stack_pointer_increment (reg);
4233 if (actual_fsize <= 4096)
4234 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4235 else if (actual_fsize <= 8192)
4237 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4238 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4242 rtx reg = gen_rtx_REG (Pmode, 1);
4243 emit_move_insn (reg, GEN_INT (-actual_fsize));
4244 emit_insn (gen_save_register_window (reg));
4248 /* Call-saved registers are saved just above the outgoing argument area. */
4252 /* Load the PIC register if needed. */
4253 if (flag_pic && current_function_uses_pic_offset_table)
4254 load_pic_register ();
4257 /* This function generates the assembly code for function entry, which boils
4258 down to emitting the necessary .register directives. It also informs the
4259 DWARF-2 back-end on the layout of the frame.
4261 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4262 an 8-byte block of memory. If any fpu reg is used in the function, we
4263 allocate such a block here, at the bottom of the frame, just in case it's
4264 needed." Could this explain the -8 in emit_restore_regs? */
4267 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4269 int leaf_function_p = current_function_uses_only_leaf_regs;
4271 sparc_output_scratch_registers (file);
4273 if (dwarf2out_do_frame () && actual_fsize)
4275 char *label = dwarf2out_cfi_label ();
4277 /* The canonical frame address refers to the top of the frame. */
4278 dwarf2out_def_cfa (label,
4280 ? STACK_POINTER_REGNUM
4281 : HARD_FRAME_POINTER_REGNUM,
4284 if (! leaf_function_p)
4286 /* Note the register window save. This tells the unwinder that
4287 it needs to restore the window registers from the previous
4288 frame's window save area at 0(cfa). */
4289 dwarf2out_window_save (label);
4291 /* The return address (-8) is now in %i7. */
4292 dwarf2out_return_reg (label, 31);
4297 /* Expand the function epilogue, either normal or part of a sibcall.
4298 We emit all the instructions except the return or the call. */
4301 sparc_expand_epilogue (void)
4303 int leaf_function_p = current_function_uses_only_leaf_regs;
4306 emit_restore_regs ();
4308 if (actual_fsize == 0)
4310 else if (leaf_function_p)
4312 if (actual_fsize <= 4096)
4313 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4314 else if (actual_fsize <= 8192)
4316 emit_stack_pointer_decrement (GEN_INT (-4096));
4317 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4321 rtx reg = gen_rtx_REG (Pmode, 1);
4322 emit_move_insn (reg, GEN_INT (-actual_fsize));
4323 emit_stack_pointer_decrement (reg);
4328 /* This function generates the assembly code for function exit. */
4331 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4333 /* If code does not drop into the epilogue, we have to still output
4334 a dummy nop for the sake of sane backtraces. Otherwise, if the
4335 last two instructions of a function were "call foo; dslot;" this
4336 can make the return PC of foo (ie. address of call instruction
4337 plus 8) point to the first instruction in the next function. */
4339 rtx insn, last_real_insn;
4341 insn = get_last_insn ();
4343 last_real_insn = prev_real_insn (insn);
4345 && GET_CODE (last_real_insn) == INSN
4346 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4347 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4349 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4350 fputs("\tnop\n", file);
4352 sparc_output_deferred_case_vectors ();
4355 /* Output a 'restore' instruction. */
4358 output_restore (rtx pat)
4364 fputs ("\t restore\n", asm_out_file);
4368 if (GET_CODE (pat) != SET)
4371 operands[0] = SET_DEST (pat);
4372 pat = SET_SRC (pat);
4374 switch (GET_CODE (pat))
4377 operands[1] = XEXP (pat, 0);
4378 operands[2] = XEXP (pat, 1);
4379 output_asm_insn (" restore %r1, %2, %Y0", operands);
4382 operands[1] = XEXP (pat, 0);
4383 operands[2] = XEXP (pat, 1);
4384 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4387 operands[1] = XEXP (pat, 0);
4388 if (XEXP (pat, 1) != const1_rtx)
4390 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4394 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4399 /* Output a return. */
4402 output_return (rtx insn)
4404 int leaf_function_p = current_function_uses_only_leaf_regs;
4405 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4406 /* True if the caller has placed an "unimp" insn immediately after the call.
4407 This insn is used in the 32-bit ABI when calling a function that returns
4408 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4409 to have this test be the same as that used on the call. */
4410 bool sparc_skip_caller_unimp
4412 && current_function_returns_struct
4413 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4415 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4417 if (leaf_function_p)
4419 /* This is a leaf function so we don't have to bother restoring the
4420 register window, which frees us from dealing with the convoluted
4421 semantics of restore/return. We simply output the jump to the
4422 return address and the insn in the delay slot, which usually is
4423 the substraction restoring the stack pointer %sp. */
4425 if (current_function_calls_eh_return)
4428 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4430 if (delay_slot_filled_p)
4432 rtx delay = NEXT_INSN (insn);
4436 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4437 PATTERN (delay) = gen_blockage ();
4438 INSN_CODE (delay) = -1;
4441 fputs ("\t nop\n", asm_out_file);
4445 /* This is a regular function so we have to restore the register window.
4446 We may have a pending insn for the delay slot, which will be either
4447 combined with the 'restore' instruction or put in the delay slot of
4448 the 'return' instruction. */
4450 if (current_function_calls_eh_return)
4452 /* If the function uses __builtin_eh_return, the eh_return
4453 machinery occupies the delay slot. */
4454 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4458 fputs ("\treturn\t%i7+8\n", asm_out_file);
4460 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4462 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4464 else if (delay_slot_filled_p)
4468 delay = NEXT_INSN (insn);
4472 pat = PATTERN (delay);
4474 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4476 epilogue_renumber (&pat, 0);
4477 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4478 sparc_skip_caller_unimp ? 12 : 8);
4479 final_scan_insn (delay, asm_out_file, 1, 0, 0, NULL);
4483 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4484 sparc_skip_caller_unimp ? 12 : 8);
4485 output_restore (pat);
4488 PATTERN (delay) = gen_blockage ();
4489 INSN_CODE (delay) = -1;
4493 /* The delay slot is empty. */
4495 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4496 sparc_skip_caller_unimp ? 12 : 8);
4498 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4499 sparc_skip_caller_unimp ? 12 : 8);
4506 /* Output a sibling call. */
4509 output_sibcall (rtx insn, rtx call_operand)
4511 int leaf_function_p = current_function_uses_only_leaf_regs;
4512 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4515 operands[0] = call_operand;
4517 if (leaf_function_p)
4519 /* This is a leaf function so we don't have to bother restoring the
4520 register window. We simply output the jump to the function and
4521 the insn in the delay slot (if any). */
4523 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4526 if (delay_slot_filled_p)
4528 rtx delay = NEXT_INSN (insn);
4532 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4533 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4534 final_scan_insn (delay, asm_out_file, 1, 0, 0, NULL);
4536 PATTERN (delay) = gen_blockage ();
4537 INSN_CODE (delay) = -1;
4541 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4542 it into branch if possible. */
4543 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4544 output_asm_insn ("call\t%a0, 0", operands);
4545 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4550 /* This is a regular function so we have to restore the register window.
4551 We may have a pending insn for the delay slot, which will be combined
4552 with the 'restore' instruction. */
4554 output_asm_insn ("call\t%a0, 0", operands);
4556 if (delay_slot_filled_p)
4558 rtx delay = NEXT_INSN (insn);
4562 output_restore (PATTERN (delay));
4564 PATTERN (delay) = gen_blockage ();
4565 INSN_CODE (delay) = -1;
4568 output_restore (NULL_RTX);
4574 /* Functions for handling argument passing.
4576 For 32-bit, the first 6 args are normally in registers and the rest are
4577 pushed. Any arg that starts within the first 6 words is at least
4578 partially passed in a register unless its data type forbids.
4580 For 64-bit, the argument registers are laid out as an array of 16 elements
4581 and arguments are added sequentially. The first 6 int args and up to the
4582 first 16 fp args (depending on size) are passed in regs.
4584 Slot Stack Integral Float Float in structure Double Long Double
4585 ---- ----- -------- ----- ------------------ ------ -----------
4586 15 [SP+248] %f31 %f30,%f31 %d30
4587 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4588 13 [SP+232] %f27 %f26,%f27 %d26
4589 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4590 11 [SP+216] %f23 %f22,%f23 %d22
4591 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4592 9 [SP+200] %f19 %f18,%f19 %d18
4593 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4594 7 [SP+184] %f15 %f14,%f15 %d14
4595 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4596 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4597 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4598 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4599 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4600 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4601 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4603 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4605 Integral arguments are always passed as 64-bit quantities appropriately
4608 Passing of floating point values is handled as follows.
4609 If a prototype is in scope:
4610 If the value is in a named argument (i.e. not a stdarg function or a
4611 value not part of the `...') then the value is passed in the appropriate
4613 If the value is part of the `...' and is passed in one of the first 6
4614 slots then the value is passed in the appropriate int reg.
4615 If the value is part of the `...' and is not passed in one of the first 6
4616 slots then the value is passed in memory.
4617 If a prototype is not in scope:
4618 If the value is one of the first 6 arguments the value is passed in the
4619 appropriate integer reg and the appropriate fp reg.
4620 If the value is not one of the first 6 arguments the value is passed in
4621 the appropriate fp reg and in memory.
4624 Summary of the calling conventions implemented by GCC on SPARC:
4627 size argument return value
4629 small integer <4 int. reg. int. reg.
4630 word 4 int. reg. int. reg.
4631 double word 8 int. reg. int. reg.
4633 _Complex small integer <8 int. reg. int. reg.
4634 _Complex word 8 int. reg. int. reg.
4635 _Complex double word 16 memory int. reg.
4637 vector integer <=8 int. reg. FP reg.
4638 vector integer >8 memory memory
4640 float 4 int. reg. FP reg.
4641 double 8 int. reg. FP reg.
4642 long double 16 memory memory
4644 _Complex float 8 memory FP reg.
4645 _Complex double 16 memory FP reg.
4646 _Complex long double 32 memory FP reg.
4648 vector float <=32 memory FP reg.
4649 vector float >32 memory memory
4651 aggregate any memory memory
4656 size argument return value
4658 small integer <8 int. reg. int. reg.
4659 word 8 int. reg. int. reg.
4660 double word 16 int. reg. int. reg.
4662 _Complex small integer <16 int. reg. int. reg.
4663 _Complex word 16 int. reg. int. reg.
4664 _Complex double word 32 memory int. reg.
4666 vector integer <=16 FP reg. FP reg.
4667 vector integer 16<s<=32 memory FP reg.
4668 vector integer >32 memory memory
4670 float 4 FP reg. FP reg.
4671 double 8 FP reg. FP reg.
4672 long double 16 FP reg. FP reg.
4674 _Complex float 8 FP reg. FP reg.
4675 _Complex double 16 FP reg. FP reg.
4676 _Complex long double 32 memory FP reg.
4678 vector float <=16 FP reg. FP reg.
4679 vector float 16<s<=32 memory FP reg.
4680 vector float >32 memory memory
4682 aggregate <=16 reg. reg.
4683 aggregate 16<s<=32 memory reg.
4684 aggregate >32 memory memory
4688 Note #1: complex floating-point types follow the extended SPARC ABIs as
4689 implemented by the Sun compiler.
4691 Note #2: integral vector types follow the scalar floating-point types
4692 conventions to match what is implemented by the Sun VIS SDK.
4694 Note #3: floating-point vector types follow the complex floating-point
4695 types conventions. */
4698 /* Maximum number of int regs for args. */
4699 #define SPARC_INT_ARG_MAX 6
4700 /* Maximum number of fp regs for args. */
4701 #define SPARC_FP_ARG_MAX 16
4703 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4705 /* Handle the INIT_CUMULATIVE_ARGS macro.
4706 Initialize a variable CUM of type CUMULATIVE_ARGS
4707 for a call to a function whose data type is FNTYPE.
4708 For a library call, FNTYPE is 0. */
4711 init_cumulative_args (struct sparc_args *cum, tree fntype,
4712 rtx libname ATTRIBUTE_UNUSED,
4713 tree fndecl ATTRIBUTE_UNUSED)
4716 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4717 cum->libcall_p = fntype == 0;
4720 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4721 When a prototype says `char' or `short', really pass an `int'. */
4724 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4726 return TARGET_ARCH32 ? true : false;
4729 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4732 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4734 return TARGET_ARCH64 ? true : false;
4737 /* Scan the record type TYPE and return the following predicates:
4738 - INTREGS_P: the record contains at least one field or sub-field
4739 that is eligible for promotion in integer registers.
4740 - FP_REGS_P: the record contains at least one field or sub-field
4741 that is eligible for promotion in floating-point registers.
4742 - PACKED_P: the record contains at least one field that is packed.
4744 Sub-fields are not taken into account for the PACKED_P predicate. */
4747 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4751 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4753 if (TREE_CODE (field) == FIELD_DECL)
4755 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4756 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4757 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4762 if (packed_p && DECL_PACKED (field))
4768 /* Compute the slot number to pass an argument in.
4769 Return the slot number or -1 if passing on the stack.
4771 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4772 the preceding args and about the function being called.
4773 MODE is the argument's machine mode.
4774 TYPE is the data type of the argument (as a tree).
4775 This is null for libcalls where that information may
4777 NAMED is nonzero if this argument is a named parameter
4778 (otherwise it is an extra parameter matching an ellipsis).
4779 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4780 *PREGNO records the register number to use if scalar type.
4781 *PPADDING records the amount of padding needed in words. */
4784 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4785 tree type, int named, int incoming_p,
4786 int *pregno, int *ppadding)
4788 int regbase = (incoming_p
4789 ? SPARC_INCOMING_INT_ARG_FIRST
4790 : SPARC_OUTGOING_INT_ARG_FIRST);
4791 int slotno = cum->words;
4796 if (type && TREE_ADDRESSABLE (type))
4802 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4805 /* For SPARC64, objects requiring 16-byte alignment get it. */
4807 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
4808 && (slotno & 1) != 0)
4809 slotno++, *ppadding = 1;
4811 switch (GET_MODE_CLASS (mode))
4814 case MODE_COMPLEX_FLOAT:
4815 case MODE_VECTOR_INT:
4816 case MODE_VECTOR_FLOAT:
4817 if (TARGET_ARCH64 && TARGET_FPU && named)
4819 if (slotno >= SPARC_FP_ARG_MAX)
4821 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4822 /* Arguments filling only one single FP register are
4823 right-justified in the outer double FP register. */
4824 if (GET_MODE_SIZE (mode) <= 4)
4831 case MODE_COMPLEX_INT:
4832 if (slotno >= SPARC_INT_ARG_MAX)
4834 regno = regbase + slotno;
4838 if (mode == VOIDmode)
4839 /* MODE is VOIDmode when generating the actual call. */
4842 if (mode != BLKmode)
4845 /* For SPARC64, objects requiring 16-byte alignment get it. */
4848 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4849 && (slotno & 1) != 0)
4850 slotno++, *ppadding = 1;
4852 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
4854 if (slotno >= SPARC_INT_ARG_MAX)
4856 regno = regbase + slotno;
4858 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
4860 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
4862 /* First see what kinds of registers we would need. */
4863 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
4865 /* The ABI obviously doesn't specify how packed structures
4866 are passed. These are defined to be passed in int regs
4867 if possible, otherwise memory. */
4868 if (packed_p || !named)
4869 fpregs_p = 0, intregs_p = 1;
4871 /* If all arg slots are filled, then must pass on stack. */
4872 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4875 /* If there are only int args and all int arg slots are filled,
4876 then must pass on stack. */
4877 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4880 /* Note that even if all int arg slots are filled, fp members may
4881 still be passed in regs if such regs are available.
4882 *PREGNO isn't set because there may be more than one, it's up
4883 to the caller to compute them. */
4896 /* Handle recursive register counting for structure field layout. */
4898 struct function_arg_record_value_parms
4900 rtx ret; /* return expression being built. */
4901 int slotno; /* slot number of the argument. */
4902 int named; /* whether the argument is named. */
4903 int regbase; /* regno of the base register. */
4904 int stack; /* 1 if part of the argument is on the stack. */
4905 int intoffset; /* offset of the first pending integer field. */
4906 unsigned int nregs; /* number of words passed in registers. */
4909 static void function_arg_record_value_3
4910 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
4911 static void function_arg_record_value_2
4912 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4913 static void function_arg_record_value_1
4914 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
4915 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
4916 static rtx function_arg_union_value (int, enum machine_mode, int);
4918 /* A subroutine of function_arg_record_value. Traverse the structure
4919 recursively and determine how many registers will be required. */
4922 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
4923 struct function_arg_record_value_parms *parms,
4928 /* We need to compute how many registers are needed so we can
4929 allocate the PARALLEL but before we can do that we need to know
4930 whether there are any packed fields. The ABI obviously doesn't
4931 specify how structures are passed in this case, so they are
4932 defined to be passed in int regs if possible, otherwise memory,
4933 regardless of whether there are fp values present. */
4936 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4938 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4945 /* Compute how many registers we need. */
4946 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4948 if (TREE_CODE (field) == FIELD_DECL)
4950 HOST_WIDE_INT bitpos = startbitpos;
4952 if (DECL_SIZE (field) != 0
4953 && host_integerp (bit_position (field), 1))
4954 bitpos += int_bit_position (field);
4956 /* ??? FIXME: else assume zero offset. */
4958 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4959 function_arg_record_value_1 (TREE_TYPE (field),
4963 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
4964 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
4969 if (parms->intoffset != -1)
4971 unsigned int startbit, endbit;
4972 int intslots, this_slotno;
4974 startbit = parms->intoffset & -BITS_PER_WORD;
4975 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4977 intslots = (endbit - startbit) / BITS_PER_WORD;
4978 this_slotno = parms->slotno + parms->intoffset
4981 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
4983 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
4984 /* We need to pass this field on the stack. */
4988 parms->nregs += intslots;
4989 parms->intoffset = -1;
4992 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4993 If it wasn't true we wouldn't be here. */
4995 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5000 if (parms->intoffset == -1)
5001 parms->intoffset = bitpos;
5007 /* A subroutine of function_arg_record_value. Assign the bits of the
5008 structure between parms->intoffset and bitpos to integer registers. */
5011 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5012 struct function_arg_record_value_parms *parms)
5014 enum machine_mode mode;
5016 unsigned int startbit, endbit;
5017 int this_slotno, intslots, intoffset;
5020 if (parms->intoffset == -1)
5023 intoffset = parms->intoffset;
5024 parms->intoffset = -1;
5026 startbit = intoffset & -BITS_PER_WORD;
5027 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5028 intslots = (endbit - startbit) / BITS_PER_WORD;
5029 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5031 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5035 /* If this is the trailing part of a word, only load that much into
5036 the register. Otherwise load the whole register. Note that in
5037 the latter case we may pick up unwanted bits. It's not a problem
5038 at the moment but may wish to revisit. */
5040 if (intoffset % BITS_PER_WORD != 0)
5041 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5046 intoffset /= BITS_PER_UNIT;
5049 regno = parms->regbase + this_slotno;
5050 reg = gen_rtx_REG (mode, regno);
5051 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5052 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5055 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5060 while (intslots > 0);
5063 /* A subroutine of function_arg_record_value. Traverse the structure
5064 recursively and assign bits to floating point registers. Track which
5065 bits in between need integer registers; invoke function_arg_record_value_3
5066 to make that happen. */
5069 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5070 struct function_arg_record_value_parms *parms,
5076 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5078 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5085 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5087 if (TREE_CODE (field) == FIELD_DECL)
5089 HOST_WIDE_INT bitpos = startbitpos;
5091 if (DECL_SIZE (field) != 0
5092 && host_integerp (bit_position (field), 1))
5093 bitpos += int_bit_position (field);
5095 /* ??? FIXME: else assume zero offset. */
5097 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5098 function_arg_record_value_2 (TREE_TYPE (field),
5102 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5103 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5108 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5110 enum machine_mode mode = DECL_MODE (field);
5113 function_arg_record_value_3 (bitpos, parms);
5116 case SCmode: mode = SFmode; break;
5117 case DCmode: mode = DFmode; break;
5118 case TCmode: mode = TFmode; break;
5121 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5122 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5124 reg = gen_rtx_REG (mode, regno);
5125 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5126 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5127 GEN_INT (bitpos / BITS_PER_UNIT));
5129 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5131 regno += GET_MODE_SIZE (mode) / 4;
5132 reg = gen_rtx_REG (mode, regno);
5133 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5134 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5135 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5142 if (parms->intoffset == -1)
5143 parms->intoffset = bitpos;
5149 /* Used by function_arg and function_value to implement the complex
5150 conventions of the 64-bit ABI for passing and returning structures.
5151 Return an expression valid as a return value for the two macros
5152 FUNCTION_ARG and FUNCTION_VALUE.
5154 TYPE is the data type of the argument (as a tree).
5155 This is null for libcalls where that information may
5157 MODE is the argument's machine mode.
5158 SLOTNO is the index number of the argument's slot in the parameter array.
5159 NAMED is nonzero if this argument is a named parameter
5160 (otherwise it is an extra parameter matching an ellipsis).
5161 REGBASE is the regno of the base register for the parameter array. */
5164 function_arg_record_value (tree type, enum machine_mode mode,
5165 int slotno, int named, int regbase)
5167 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5168 struct function_arg_record_value_parms parms;
5171 parms.ret = NULL_RTX;
5172 parms.slotno = slotno;
5173 parms.named = named;
5174 parms.regbase = regbase;
5177 /* Compute how many registers we need. */
5179 parms.intoffset = 0;
5180 function_arg_record_value_1 (type, 0, &parms, false);
5182 /* Take into account pending integer fields. */
5183 if (parms.intoffset != -1)
5185 unsigned int startbit, endbit;
5186 int intslots, this_slotno;
5188 startbit = parms.intoffset & -BITS_PER_WORD;
5189 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5190 intslots = (endbit - startbit) / BITS_PER_WORD;
5191 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5193 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5195 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5196 /* We need to pass this field on the stack. */
5200 parms.nregs += intslots;
5202 nregs = parms.nregs;
5204 /* Allocate the vector and handle some annoying special cases. */
5207 /* ??? Empty structure has no value? Duh? */
5210 /* Though there's nothing really to store, return a word register
5211 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5212 leads to breakage due to the fact that there are zero bytes to
5214 return gen_rtx_REG (mode, regbase);
5218 /* ??? C++ has structures with no fields, and yet a size. Give up
5219 for now and pass everything back in integer registers. */
5220 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5222 if (nregs + slotno > SPARC_INT_ARG_MAX)
5223 nregs = SPARC_INT_ARG_MAX - slotno;
5228 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5230 /* If at least one field must be passed on the stack, generate
5231 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5232 also be passed on the stack. We can't do much better because the
5233 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5234 of structures for which the fields passed exclusively in registers
5235 are not at the beginning of the structure. */
5237 XVECEXP (parms.ret, 0, 0)
5238 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5240 /* Fill in the entries. */
5242 parms.intoffset = 0;
5243 function_arg_record_value_2 (type, 0, &parms, false);
5244 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5246 if (parms.nregs != nregs)
5252 /* Used by function_arg and function_value to implement the conventions
5253 of the 64-bit ABI for passing and returning unions.
5254 Return an expression valid as a return value for the two macros
5255 FUNCTION_ARG and FUNCTION_VALUE.
5257 SIZE is the size in bytes of the union.
5258 MODE is the argument's machine mode.
5259 REGNO is the hard register the union will be passed in. */
5262 function_arg_union_value (int size, enum machine_mode mode, int regno)
5264 int nwords = ROUND_ADVANCE (size), i;
5267 /* Unions are passed left-justified. */
5268 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5270 for (i = 0; i < nwords; i++)
5271 XVECEXP (regs, 0, i)
5272 = gen_rtx_EXPR_LIST (VOIDmode,
5273 gen_rtx_REG (word_mode, regno + i),
5274 GEN_INT (UNITS_PER_WORD * i));
5279 /* Handle the FUNCTION_ARG macro.
5280 Determine where to put an argument to a function.
5281 Value is zero to push the argument on the stack,
5282 or a hard register in which to store the argument.
5284 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5285 the preceding args and about the function being called.
5286 MODE is the argument's machine mode.
5287 TYPE is the data type of the argument (as a tree).
5288 This is null for libcalls where that information may
5290 NAMED is nonzero if this argument is a named parameter
5291 (otherwise it is an extra parameter matching an ellipsis).
5292 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5295 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5296 tree type, int named, int incoming_p)
5298 int regbase = (incoming_p
5299 ? SPARC_INCOMING_INT_ARG_FIRST
5300 : SPARC_OUTGOING_INT_ARG_FIRST);
5301 int slotno, regno, padding;
5304 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5312 reg = gen_rtx_REG (mode, regno);
5316 if (type && TREE_CODE (type) == RECORD_TYPE)
5318 /* Structures up to 16 bytes in size are passed in arg slots on the
5319 stack and are promoted to registers where possible. */
5321 if (int_size_in_bytes (type) > 16)
5322 abort (); /* shouldn't get here */
5324 return function_arg_record_value (type, mode, slotno, named, regbase);
5326 else if (type && TREE_CODE (type) == UNION_TYPE)
5328 HOST_WIDE_INT size = int_size_in_bytes (type);
5331 abort (); /* shouldn't get here */
5333 return function_arg_union_value (size, mode, regno);
5335 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5336 but also have the slot allocated for them.
5337 If no prototype is in scope fp values in register slots get passed
5338 in two places, either fp regs and int regs or fp regs and memory. */
5339 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5340 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5341 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5342 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5343 && SPARC_FP_REG_P (regno))
5345 reg = gen_rtx_REG (mode, regno);
5346 if (cum->prototype_p || cum->libcall_p)
5348 /* "* 2" because fp reg numbers are recorded in 4 byte
5351 /* ??? This will cause the value to be passed in the fp reg and
5352 in the stack. When a prototype exists we want to pass the
5353 value in the reg but reserve space on the stack. That's an
5354 optimization, and is deferred [for a bit]. */
5355 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5356 return gen_rtx_PARALLEL (mode,
5358 gen_rtx_EXPR_LIST (VOIDmode,
5359 NULL_RTX, const0_rtx),
5360 gen_rtx_EXPR_LIST (VOIDmode,
5364 /* ??? It seems that passing back a register even when past
5365 the area declared by REG_PARM_STACK_SPACE will allocate
5366 space appropriately, and will not copy the data onto the
5367 stack, exactly as we desire.
5369 This is due to locate_and_pad_parm being called in
5370 expand_call whenever reg_parm_stack_space > 0, which
5371 while beneficial to our example here, would seem to be
5372 in error from what had been intended. Ho hum... -- r~ */
5380 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5384 /* On incoming, we don't need to know that the value
5385 is passed in %f0 and %i0, and it confuses other parts
5386 causing needless spillage even on the simplest cases. */
5390 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5391 + (regno - SPARC_FP_ARG_FIRST) / 2);
5393 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5394 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5396 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5400 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5401 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5402 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5408 /* Scalar or complex int. */
5409 reg = gen_rtx_REG (mode, regno);
5415 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5416 For an arg passed partly in registers and partly in memory,
5417 this is the number of registers used.
5418 For args passed entirely in registers or entirely in memory, zero.
5420 Any arg that starts in the first 6 regs but won't entirely fit in them
5421 needs partial registers on v8. On v9, structures with integer
5422 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5423 values that begin in the last fp reg [where "last fp reg" varies with the
5424 mode] will be split between that reg and memory. */
5427 function_arg_partial_nregs (const struct sparc_args *cum,
5428 enum machine_mode mode, tree type, int named)
5430 int slotno, regno, padding;
5432 /* We pass 0 for incoming_p here, it doesn't matter. */
5433 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5440 if ((slotno + (mode == BLKmode
5441 ? ROUND_ADVANCE (int_size_in_bytes (type))
5442 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5443 > SPARC_INT_ARG_MAX)
5444 return SPARC_INT_ARG_MAX - slotno;
5448 /* We are guaranteed by function_arg_pass_by_reference that the size
5449 of the argument is not greater than 16 bytes, so we only need to
5450 return 1 if the argument is partially passed in registers. */
5452 if (type && AGGREGATE_TYPE_P (type))
5454 int size = int_size_in_bytes (type);
5456 if (size > UNITS_PER_WORD
5457 && slotno == SPARC_INT_ARG_MAX - 1)
5460 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5461 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5462 && ! (TARGET_FPU && named)))
5464 /* The complex types are passed as packed types. */
5465 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5466 && slotno == SPARC_INT_ARG_MAX - 1)
5469 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5471 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5480 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5481 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5482 quad-precision floats by invisible reference.
5483 v9: Aggregates greater than 16 bytes are passed by reference.
5484 For Pascal, also pass arrays by reference. */
5487 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5488 enum machine_mode mode, tree type,
5489 int named ATTRIBUTE_UNUSED)
5493 return ((type && AGGREGATE_TYPE_P (type))
5494 /* Extended ABI (as implemented by the Sun compiler) says
5495 that all complex floats are passed in memory. */
5497 /* Enforce the 2-word cap for passing arguments in registers.
5498 This affects CDImode, TFmode, DCmode, TCmode and large
5500 || GET_MODE_SIZE (mode) > 8);
5504 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5506 && AGGREGATE_TYPE_P (type)
5507 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5508 /* Enforce the 2-word cap for passing arguments in registers.
5509 This affects CTImode, TCmode and large vector modes. */
5510 || GET_MODE_SIZE (mode) > 16);
5514 /* Handle the FUNCTION_ARG_ADVANCE macro.
5515 Update the data in CUM to advance over an argument
5516 of mode MODE and data type TYPE.
5517 TYPE is null for libcalls where that information may not be available. */
5520 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5521 tree type, int named)
5523 int slotno, regno, padding;
5525 /* We pass 0 for incoming_p here, it doesn't matter. */
5526 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5528 /* If register required leading padding, add it. */
5530 cum->words += padding;
5534 cum->words += (mode != BLKmode
5535 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5536 : ROUND_ADVANCE (int_size_in_bytes (type)));
5540 if (type && AGGREGATE_TYPE_P (type))
5542 int size = int_size_in_bytes (type);
5546 else if (size <= 16)
5548 else /* passed by reference */
5553 cum->words += (mode != BLKmode
5554 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5555 : ROUND_ADVANCE (int_size_in_bytes (type)));
5560 /* Handle the FUNCTION_ARG_PADDING macro.
5561 For the 64 bit ABI structs are always stored left shifted in their
5565 function_arg_padding (enum machine_mode mode, tree type)
5567 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5570 /* Fall back to the default. */
5571 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5574 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5575 Specify whether to return the return value in memory. */
5578 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5581 /* Original SPARC 32-bit ABI says that quad-precision floats
5582 and all structures are returned in memory. Extended ABI
5583 (as implemented by the Sun compiler) says that all complex
5584 floats are returned in registers (8 FP registers at most
5585 for '_Complex long double'). Return all complex integers
5586 in registers (4 at most for '_Complex long long'). */
5587 return (TYPE_MODE (type) == BLKmode
5588 || TYPE_MODE (type) == TFmode
5589 /* Integral vector types follow the scalar FP types conventions. */
5590 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5591 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5592 /* FP vector types follow the complex FP types conventions. */
5593 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5594 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5596 /* Original SPARC 64-bit ABI says that structures and unions
5597 smaller than 32 bytes are returned in registers. Extended
5598 ABI (as implemented by the Sun compiler) says that all complex
5599 floats are returned in registers (8 FP registers at most
5600 for '_Complex long double'). Return all complex integers
5601 in registers (4 at most for '_Complex TItype'). */
5602 return ((TYPE_MODE (type) == BLKmode
5603 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5604 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5607 /* Handle the TARGET_STRUCT_VALUE target hook.
5608 Return where to find the structure return value address. */
5611 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5618 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5619 STRUCT_VALUE_OFFSET));
5621 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5622 STRUCT_VALUE_OFFSET));
5626 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5627 For v9, function return values are subject to the same rules as arguments,
5628 except that up to 32 bytes may be returned in registers. */
5631 function_value (tree type, enum machine_mode mode, int incoming_p)
5633 /* Beware that the two values are swapped here wrt function_arg. */
5634 int regbase = (incoming_p
5635 ? SPARC_OUTGOING_INT_ARG_FIRST
5636 : SPARC_INCOMING_INT_ARG_FIRST);
5639 if (TARGET_ARCH64 && type)
5641 if (TREE_CODE (type) == RECORD_TYPE)
5643 /* Structures up to 32 bytes in size are passed in registers,
5644 promoted to fp registers where possible. */
5646 if (int_size_in_bytes (type) > 32)
5647 abort (); /* shouldn't get here */
5649 return function_arg_record_value (type, mode, 0, 1, regbase);
5651 else if (TREE_CODE (type) == UNION_TYPE)
5653 HOST_WIDE_INT size = int_size_in_bytes (type);
5656 abort (); /* shouldn't get here */
5658 return function_arg_union_value (size, mode, regbase);
5660 else if (AGGREGATE_TYPE_P (type))
5662 /* All other aggregate types are passed in an integer register
5663 in a mode corresponding to the size of the type. */
5664 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5667 abort (); /* shouldn't get here */
5669 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5671 else if (GET_MODE_CLASS (mode) == MODE_INT
5672 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5676 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5677 regno = SPARC_FP_ARG_FIRST;
5681 return gen_rtx_REG (mode, regno);
5684 /* Do what is necessary for `va_start'. We look at the current function
5685 to determine if stdarg or varargs is used and return the address of
5686 the first unnamed parameter. */
5689 sparc_builtin_saveregs (void)
5691 int first_reg = current_function_args_info.words;
5695 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5696 emit_move_insn (gen_rtx_MEM (word_mode,
5697 gen_rtx_PLUS (Pmode,
5699 GEN_INT (FIRST_PARM_OFFSET (0)
5702 gen_rtx_REG (word_mode,
5703 SPARC_INCOMING_INT_ARG_FIRST + regno));
5705 address = gen_rtx_PLUS (Pmode,
5707 GEN_INT (FIRST_PARM_OFFSET (0)
5708 + UNITS_PER_WORD * first_reg));
5713 /* Implement `va_start' for stdarg. */
5716 sparc_va_start (tree valist, rtx nextarg)
5718 nextarg = expand_builtin_saveregs ();
5719 std_expand_builtin_va_start (valist, nextarg);
5722 /* Implement `va_arg' for stdarg. */
5725 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5727 HOST_WIDE_INT size, rsize, align;
5730 tree ptrtype = build_pointer_type (type);
5732 if (function_arg_pass_by_reference (0, TYPE_MODE (type), type, 0))
5735 size = rsize = UNITS_PER_WORD;
5741 size = int_size_in_bytes (type);
5742 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5747 /* For SPARC64, objects requiring 16-byte alignment get it. */
5748 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5749 align = 2 * UNITS_PER_WORD;
5751 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5752 are given whole slots as needed. */
5753 if (AGGREGATE_TYPE_P (type))
5756 size = rsize = UNITS_PER_WORD;
5766 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5767 ssize_int (align - 1)));
5768 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
5769 ssize_int (-align)));
5772 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
5775 if (BYTES_BIG_ENDIAN && size < rsize)
5776 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
5777 ssize_int (rsize - size)));
5781 addr = fold_convert (build_pointer_type (ptrtype), addr);
5782 addr = build_fold_indirect_ref (addr);
5784 /* If the address isn't aligned properly for the type,
5785 we may need to copy to a temporary.
5786 FIXME: This is inefficient. Usually we can do this
5789 && TYPE_ALIGN (type) > BITS_PER_WORD)
5791 tree tmp = create_tmp_var (type, "va_arg_tmp");
5792 tree dest_addr = build_fold_addr_expr (tmp);
5794 tree copy = build_function_call_expr
5795 (implicit_built_in_decls[BUILT_IN_MEMCPY],
5796 tree_cons (NULL_TREE, dest_addr,
5797 tree_cons (NULL_TREE, addr,
5798 tree_cons (NULL_TREE, size_int (rsize),
5801 gimplify_and_add (copy, pre_p);
5805 addr = fold_convert (ptrtype, addr);
5807 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
5808 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
5809 gimplify_and_add (incr, post_p);
5811 return build_fold_indirect_ref (addr);
5814 /* Return the string to output a conditional branch to LABEL, which is
5815 the operand number of the label. OP is the conditional expression.
5816 XEXP (OP, 0) is assumed to be a condition code register (integer or
5817 floating point) and its mode specifies what kind of comparison we made.
5819 REVERSED is nonzero if we should reverse the sense of the comparison.
5821 ANNUL is nonzero if we should generate an annulling branch.
5823 NOOP is nonzero if we have to follow this branch by a noop.
5825 INSN, if set, is the insn. */
5828 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
5831 static char string[64];
5832 enum rtx_code code = GET_CODE (op);
5833 rtx cc_reg = XEXP (op, 0);
5834 enum machine_mode mode = GET_MODE (cc_reg);
5835 const char *labelno, *branch;
5836 int spaces = 8, far;
5839 /* v9 branches are limited to +-1MB. If it is too far away,
5852 fbne,a,pn %fcc2, .LC29
5860 far = get_attr_length (insn) >= 3;
5863 /* Reversal of FP compares takes care -- an ordered compare
5864 becomes an unordered compare and vice versa. */
5865 if (mode == CCFPmode || mode == CCFPEmode)
5866 code = reverse_condition_maybe_unordered (code);
5868 code = reverse_condition (code);
5871 /* Start by writing the branch condition. */
5872 if (mode == CCFPmode || mode == CCFPEmode)
5923 /* ??? !v9: FP branches cannot be preceded by another floating point
5924 insn. Because there is currently no concept of pre-delay slots,
5925 we can fix this only by always emitting a nop before a floating
5930 strcpy (string, "nop\n\t");
5931 strcat (string, branch);
5944 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5956 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5977 strcpy (string, branch);
5979 spaces -= strlen (branch);
5980 p = strchr (string, '\0');
5982 /* Now add the annulling, the label, and a possible noop. */
5997 if (! far && insn && INSN_ADDRESSES_SET_P ())
5999 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6000 - INSN_ADDRESSES (INSN_UID (insn)));
6001 /* Leave some instructions for "slop". */
6002 if (delta < -260000 || delta >= 260000)
6006 if (mode == CCFPmode || mode == CCFPEmode)
6008 static char v9_fcc_labelno[] = "%%fccX, ";
6009 /* Set the char indicating the number of the fcc reg to use. */
6010 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6011 labelno = v9_fcc_labelno;
6014 if (REGNO (cc_reg) == SPARC_FCC_REG)
6020 else if (mode == CCXmode || mode == CCX_NOOVmode)
6022 labelno = "%%xcc, ";
6028 labelno = "%%icc, ";
6033 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6036 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6046 strcpy (p, labelno);
6047 p = strchr (p, '\0');
6050 strcpy (p, ".+12\n\t nop\n\tb\t");
6057 /* Set the char indicating the number of the operand containing the
6062 strcpy (p, "\n\t nop");
6067 /* Emit a library call comparison between floating point X and Y.
6068 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6069 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6070 values as arguments instead of the TFmode registers themselves,
6071 that's why we cannot call emit_float_lib_cmp. */
6073 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6076 rtx slot0, slot1, result, tem, tem2;
6077 enum machine_mode mode;
6082 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6086 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6090 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6094 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6098 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6102 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6113 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6123 if (GET_CODE (x) != MEM)
6125 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6126 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6131 if (GET_CODE (y) != MEM)
6133 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6134 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6139 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6141 XEXP (slot0, 0), Pmode,
6142 XEXP (slot1, 0), Pmode);
6148 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6150 x, TFmode, y, TFmode);
6156 /* Immediately move the result of the libcall into a pseudo
6157 register so reload doesn't clobber the value if it needs
6158 the return register for a spill reg. */
6159 result = gen_reg_rtx (mode);
6160 emit_move_insn (result, hard_libcall_value (mode));
6165 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6169 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6174 emit_cmp_insn (result, const1_rtx,
6175 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6178 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6181 tem = gen_reg_rtx (mode);
6183 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6185 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6186 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6190 tem = gen_reg_rtx (mode);
6192 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6194 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6195 tem2 = gen_reg_rtx (mode);
6197 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6199 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6200 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6206 /* Generate an unsigned DImode to FP conversion. This is the same code
6207 optabs would emit if we didn't have TFmode patterns. */
6210 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6212 rtx neglab, donelab, i0, i1, f0, in, out;
6215 in = force_reg (DImode, operands[1]);
6216 neglab = gen_label_rtx ();
6217 donelab = gen_label_rtx ();
6218 i0 = gen_reg_rtx (DImode);
6219 i1 = gen_reg_rtx (DImode);
6220 f0 = gen_reg_rtx (mode);
6222 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6224 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6225 emit_jump_insn (gen_jump (donelab));
6228 emit_label (neglab);
6230 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6231 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6232 emit_insn (gen_iordi3 (i0, i0, i1));
6233 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6234 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6236 emit_label (donelab);
6239 /* Generate an FP to unsigned DImode conversion. This is the same code
6240 optabs would emit if we didn't have TFmode patterns. */
6243 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6245 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6248 in = force_reg (mode, operands[1]);
6249 neglab = gen_label_rtx ();
6250 donelab = gen_label_rtx ();
6251 i0 = gen_reg_rtx (DImode);
6252 i1 = gen_reg_rtx (DImode);
6253 limit = gen_reg_rtx (mode);
6254 f0 = gen_reg_rtx (mode);
6256 emit_move_insn (limit,
6257 CONST_DOUBLE_FROM_REAL_VALUE (
6258 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6259 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6261 emit_insn (gen_rtx_SET (VOIDmode,
6263 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6264 emit_jump_insn (gen_jump (donelab));
6267 emit_label (neglab);
6269 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6270 emit_insn (gen_rtx_SET (VOIDmode,
6272 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6273 emit_insn (gen_movdi (i1, const1_rtx));
6274 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6275 emit_insn (gen_xordi3 (out, i0, i1));
6277 emit_label (donelab);
6280 /* Return the string to output a conditional branch to LABEL, testing
6281 register REG. LABEL is the operand number of the label; REG is the
6282 operand number of the reg. OP is the conditional expression. The mode
6283 of REG says what kind of comparison we made.
6285 REVERSED is nonzero if we should reverse the sense of the comparison.
6287 ANNUL is nonzero if we should generate an annulling branch.
6289 NOOP is nonzero if we have to follow this branch by a noop. */
6292 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6293 int annul, int noop, rtx insn)
6295 static char string[64];
6296 enum rtx_code code = GET_CODE (op);
6297 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6302 /* branch on register are limited to +-128KB. If it is too far away,
6315 brgez,a,pn %o1, .LC29
6321 ba,pt %xcc, .LC29 */
6323 far = get_attr_length (insn) >= 3;
6325 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6327 code = reverse_condition (code);
6329 /* Only 64 bit versions of these instructions exist. */
6333 /* Start by writing the branch condition. */
6338 strcpy (string, "brnz");
6342 strcpy (string, "brz");
6346 strcpy (string, "brgez");
6350 strcpy (string, "brlz");
6354 strcpy (string, "brlez");
6358 strcpy (string, "brgz");
6365 p = strchr (string, '\0');
6367 /* Now add the annulling, reg, label, and nop. */
6374 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6377 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6382 *p = p < string + 8 ? '\t' : ' ';
6390 int veryfar = 1, delta;
6392 if (INSN_ADDRESSES_SET_P ())
6394 delta = (INSN_ADDRESSES (INSN_UID (dest))
6395 - INSN_ADDRESSES (INSN_UID (insn)));
6396 /* Leave some instructions for "slop". */
6397 if (delta >= -260000 && delta < 260000)
6401 strcpy (p, ".+12\n\t nop\n\t");
6412 strcpy (p, "ba,pt\t%%xcc, ");
6422 strcpy (p, "\n\t nop");
6427 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6428 Such instructions cannot be used in the delay slot of return insn on v9.
6429 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6433 epilogue_renumber (register rtx *where, int test)
6435 register const char *fmt;
6437 register enum rtx_code code;
6442 code = GET_CODE (*where);
6447 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6449 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6450 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6458 /* Do not replace the frame pointer with the stack pointer because
6459 it can cause the delayed instruction to load below the stack.
6460 This occurs when instructions like:
6462 (set (reg/i:SI 24 %i0)
6463 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6464 (const_int -20 [0xffffffec])) 0))
6466 are in the return delayed slot. */
6468 if (GET_CODE (XEXP (*where, 0)) == REG
6469 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6470 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6471 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6476 if (SPARC_STACK_BIAS
6477 && GET_CODE (XEXP (*where, 0)) == REG
6478 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6486 fmt = GET_RTX_FORMAT (code);
6488 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6493 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6494 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6497 else if (fmt[i] == 'e'
6498 && epilogue_renumber (&(XEXP (*where, i)), test))
6504 /* Leaf functions and non-leaf functions have different needs. */
6507 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6510 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6512 static const int *const reg_alloc_orders[] = {
6513 reg_leaf_alloc_order,
6514 reg_nonleaf_alloc_order};
6517 order_regs_for_local_alloc (void)
6519 static int last_order_nonleaf = 1;
6521 if (regs_ever_live[15] != last_order_nonleaf)
6523 last_order_nonleaf = !last_order_nonleaf;
6524 memcpy ((char *) reg_alloc_order,
6525 (const char *) reg_alloc_orders[last_order_nonleaf],
6526 FIRST_PSEUDO_REGISTER * sizeof (int));
6530 /* Return 1 if REG and MEM are legitimate enough to allow the various
6531 mem<-->reg splits to be run. */
6534 sparc_splitdi_legitimate (rtx reg, rtx mem)
6536 /* Punt if we are here by mistake. */
6537 if (! reload_completed)
6540 /* We must have an offsettable memory reference. */
6541 if (! offsettable_memref_p (mem))
6544 /* If we have legitimate args for ldd/std, we do not want
6545 the split to happen. */
6546 if ((REGNO (reg) % 2) == 0
6547 && mem_min_alignment (mem, 8))
6554 /* Return 1 if x and y are some kind of REG and they refer to
6555 different hard registers. This test is guaranteed to be
6556 run after reload. */
6559 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6561 if (GET_CODE (x) != REG)
6563 if (GET_CODE (y) != REG)
6565 if (REGNO (x) == REGNO (y))
6570 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6571 This makes them candidates for using ldd and std insns.
6573 Note reg1 and reg2 *must* be hard registers. */
6576 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6578 /* We might have been passed a SUBREG. */
6579 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6582 if (REGNO (reg1) % 2 != 0)
6585 /* Integer ldd is deprecated in SPARC V9 */
6586 if (TARGET_V9 && REGNO (reg1) < 32)
6589 return (REGNO (reg1) == REGNO (reg2) - 1);
6592 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6595 This can only happen when addr1 and addr2, the addresses in mem1
6596 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6597 addr1 must also be aligned on a 64-bit boundary.
6599 Also iff dependent_reg_rtx is not null it should not be used to
6600 compute the address for mem1, i.e. we cannot optimize a sequence
6612 But, note that the transformation from:
6617 is perfectly fine. Thus, the peephole2 patterns always pass us
6618 the destination register of the first load, never the second one.
6620 For stores we don't have a similar problem, so dependent_reg_rtx is
6624 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6628 HOST_WIDE_INT offset1;
6630 /* The mems cannot be volatile. */
6631 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6634 /* MEM1 should be aligned on a 64-bit boundary. */
6635 if (MEM_ALIGN (mem1) < 64)
6638 addr1 = XEXP (mem1, 0);
6639 addr2 = XEXP (mem2, 0);
6641 /* Extract a register number and offset (if used) from the first addr. */
6642 if (GET_CODE (addr1) == PLUS)
6644 /* If not a REG, return zero. */
6645 if (GET_CODE (XEXP (addr1, 0)) != REG)
6649 reg1 = REGNO (XEXP (addr1, 0));
6650 /* The offset must be constant! */
6651 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6653 offset1 = INTVAL (XEXP (addr1, 1));
6656 else if (GET_CODE (addr1) != REG)
6660 reg1 = REGNO (addr1);
6661 /* This was a simple (mem (reg)) expression. Offset is 0. */
6665 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6666 if (GET_CODE (addr2) != PLUS)
6669 if (GET_CODE (XEXP (addr2, 0)) != REG
6670 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6673 if (reg1 != REGNO (XEXP (addr2, 0)))
6676 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6679 /* The first offset must be evenly divisible by 8 to ensure the
6680 address is 64 bit aligned. */
6681 if (offset1 % 8 != 0)
6684 /* The offset for the second addr must be 4 more than the first addr. */
6685 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6688 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6693 /* Return 1 if reg is a pseudo, or is the first register in
6694 a hard register pair. This makes it a candidate for use in
6695 ldd and std insns. */
6698 register_ok_for_ldd (rtx reg)
6700 /* We might have been passed a SUBREG. */
6701 if (GET_CODE (reg) != REG)
6704 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6705 return (REGNO (reg) % 2 == 0);
6710 /* Print operand X (an rtx) in assembler syntax to file FILE.
6711 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6712 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6715 print_operand (FILE *file, rtx x, int code)
6720 /* Output a 'nop' if there's nothing for the delay slot. */
6721 if (dbr_sequence_length () == 0)
6722 fputs ("\n\t nop", file);
6725 /* Output an annul flag if there's nothing for the delay slot and we
6726 are optimizing. This is always used with '(' below. */
6727 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6728 this is a dbx bug. So, we only do this when optimizing. */
6729 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6730 Always emit a nop in case the next instruction is a branch. */
6731 if (dbr_sequence_length () == 0
6732 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6736 /* Output a 'nop' if there's nothing for the delay slot and we are
6737 not optimizing. This is always used with '*' above. */
6738 if (dbr_sequence_length () == 0
6739 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6740 fputs ("\n\t nop", file);
6743 /* Output the Embedded Medium/Anywhere code model base register. */
6744 fputs (EMBMEDANY_BASE_REG, file);
6747 /* Print out what we are using as the frame pointer. This might
6748 be %fp, or might be %sp+offset. */
6749 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6750 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
6751 reg_names[REGNO (frame_base_reg)], frame_base_offset);
6754 /* Print some local dynamic TLS name. */
6755 assemble_name (file, get_some_local_dynamic_name ());
6758 /* Adjust the operand to take into account a RESTORE operation. */
6759 if (GET_CODE (x) == CONST_INT)
6761 else if (GET_CODE (x) != REG)
6762 output_operand_lossage ("invalid %%Y operand");
6763 else if (REGNO (x) < 8)
6764 fputs (reg_names[REGNO (x)], file);
6765 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6766 fputs (reg_names[REGNO (x)-16], file);
6768 output_operand_lossage ("invalid %%Y operand");
6771 /* Print out the low order register name of a register pair. */
6772 if (WORDS_BIG_ENDIAN)
6773 fputs (reg_names[REGNO (x)+1], file);
6775 fputs (reg_names[REGNO (x)], file);
6778 /* Print out the high order register name of a register pair. */
6779 if (WORDS_BIG_ENDIAN)
6780 fputs (reg_names[REGNO (x)], file);
6782 fputs (reg_names[REGNO (x)+1], file);
6785 /* Print out the second register name of a register pair or quad.
6786 I.e., R (%o0) => %o1. */
6787 fputs (reg_names[REGNO (x)+1], file);
6790 /* Print out the third register name of a register quad.
6791 I.e., S (%o0) => %o2. */
6792 fputs (reg_names[REGNO (x)+2], file);
6795 /* Print out the fourth register name of a register quad.
6796 I.e., T (%o0) => %o3. */
6797 fputs (reg_names[REGNO (x)+3], file);
6800 /* Print a condition code register. */
6801 if (REGNO (x) == SPARC_ICC_REG)
6803 /* We don't handle CC[X]_NOOVmode because they're not supposed
6805 if (GET_MODE (x) == CCmode)
6806 fputs ("%icc", file);
6807 else if (GET_MODE (x) == CCXmode)
6808 fputs ("%xcc", file);
6813 /* %fccN register */
6814 fputs (reg_names[REGNO (x)], file);
6817 /* Print the operand's address only. */
6818 output_address (XEXP (x, 0));
6821 /* In this case we need a register. Use %g0 if the
6822 operand is const0_rtx. */
6824 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6826 fputs ("%g0", file);
6833 switch (GET_CODE (x))
6835 case IOR: fputs ("or", file); break;
6836 case AND: fputs ("and", file); break;
6837 case XOR: fputs ("xor", file); break;
6838 default: output_operand_lossage ("invalid %%A operand");
6843 switch (GET_CODE (x))
6845 case IOR: fputs ("orn", file); break;
6846 case AND: fputs ("andn", file); break;
6847 case XOR: fputs ("xnor", file); break;
6848 default: output_operand_lossage ("invalid %%B operand");
6852 /* These are used by the conditional move instructions. */
6856 enum rtx_code rc = GET_CODE (x);
6860 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6861 if (mode == CCFPmode || mode == CCFPEmode)
6862 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6864 rc = reverse_condition (GET_CODE (x));
6868 case NE: fputs ("ne", file); break;
6869 case EQ: fputs ("e", file); break;
6870 case GE: fputs ("ge", file); break;
6871 case GT: fputs ("g", file); break;
6872 case LE: fputs ("le", file); break;
6873 case LT: fputs ("l", file); break;
6874 case GEU: fputs ("geu", file); break;
6875 case GTU: fputs ("gu", file); break;
6876 case LEU: fputs ("leu", file); break;
6877 case LTU: fputs ("lu", file); break;
6878 case LTGT: fputs ("lg", file); break;
6879 case UNORDERED: fputs ("u", file); break;
6880 case ORDERED: fputs ("o", file); break;
6881 case UNLT: fputs ("ul", file); break;
6882 case UNLE: fputs ("ule", file); break;
6883 case UNGT: fputs ("ug", file); break;
6884 case UNGE: fputs ("uge", file); break;
6885 case UNEQ: fputs ("ue", file); break;
6886 default: output_operand_lossage (code == 'c'
6887 ? "invalid %%c operand"
6888 : "invalid %%C operand");
6893 /* These are used by the movr instruction pattern. */
6897 enum rtx_code rc = (code == 'd'
6898 ? reverse_condition (GET_CODE (x))
6902 case NE: fputs ("ne", file); break;
6903 case EQ: fputs ("e", file); break;
6904 case GE: fputs ("gez", file); break;
6905 case LT: fputs ("lz", file); break;
6906 case LE: fputs ("lez", file); break;
6907 case GT: fputs ("gz", file); break;
6908 default: output_operand_lossage (code == 'd'
6909 ? "invalid %%d operand"
6910 : "invalid %%D operand");
6917 /* Print a sign-extended character. */
6918 int i = trunc_int_for_mode (INTVAL (x), QImode);
6919 fprintf (file, "%d", i);
6924 /* Operand must be a MEM; write its address. */
6925 if (GET_CODE (x) != MEM)
6926 output_operand_lossage ("invalid %%f operand");
6927 output_address (XEXP (x, 0));
6932 /* Print a sign-extended 32-bit value. */
6934 if (GET_CODE(x) == CONST_INT)
6936 else if (GET_CODE(x) == CONST_DOUBLE)
6937 i = CONST_DOUBLE_LOW (x);
6940 output_operand_lossage ("invalid %%s operand");
6943 i = trunc_int_for_mode (i, SImode);
6944 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
6949 /* Do nothing special. */
6953 /* Undocumented flag. */
6954 output_operand_lossage ("invalid operand output code");
6957 if (GET_CODE (x) == REG)
6958 fputs (reg_names[REGNO (x)], file);
6959 else if (GET_CODE (x) == MEM)
6962 /* Poor Sun assembler doesn't understand absolute addressing. */
6963 if (CONSTANT_P (XEXP (x, 0)))
6964 fputs ("%g0+", file);
6965 output_address (XEXP (x, 0));
6968 else if (GET_CODE (x) == HIGH)
6970 fputs ("%hi(", file);
6971 output_addr_const (file, XEXP (x, 0));
6974 else if (GET_CODE (x) == LO_SUM)
6976 print_operand (file, XEXP (x, 0), 0);
6977 if (TARGET_CM_MEDMID)
6978 fputs ("+%l44(", file);
6980 fputs ("+%lo(", file);
6981 output_addr_const (file, XEXP (x, 1));
6984 else if (GET_CODE (x) == CONST_DOUBLE
6985 && (GET_MODE (x) == VOIDmode
6986 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6988 if (CONST_DOUBLE_HIGH (x) == 0)
6989 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6990 else if (CONST_DOUBLE_HIGH (x) == -1
6991 && CONST_DOUBLE_LOW (x) < 0)
6992 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6994 output_operand_lossage ("long long constant not a valid immediate operand");
6996 else if (GET_CODE (x) == CONST_DOUBLE)
6997 output_operand_lossage ("floating point constant not a valid immediate operand");
6998 else { output_addr_const (file, x); }
7001 /* Target hook for assembling integer objects. The sparc version has
7002 special handling for aligned DI-mode objects. */
7005 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7007 /* ??? We only output .xword's for symbols and only then in environments
7008 where the assembler can handle them. */
7009 if (aligned_p && size == 8
7010 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7014 assemble_integer_with_op ("\t.xword\t", x);
7019 assemble_aligned_integer (4, const0_rtx);
7020 assemble_aligned_integer (4, x);
7024 return default_assemble_integer (x, size, aligned_p);
7027 /* Return the value of a code used in the .proc pseudo-op that says
7028 what kind of result this function returns. For non-C types, we pick
7029 the closest C type. */
7031 #ifndef SHORT_TYPE_SIZE
7032 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7035 #ifndef INT_TYPE_SIZE
7036 #define INT_TYPE_SIZE BITS_PER_WORD
7039 #ifndef LONG_TYPE_SIZE
7040 #define LONG_TYPE_SIZE BITS_PER_WORD
7043 #ifndef LONG_LONG_TYPE_SIZE
7044 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7047 #ifndef FLOAT_TYPE_SIZE
7048 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7051 #ifndef DOUBLE_TYPE_SIZE
7052 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7055 #ifndef LONG_DOUBLE_TYPE_SIZE
7056 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7060 sparc_type_code (register tree type)
7062 register unsigned long qualifiers = 0;
7063 register unsigned shift;
7065 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7066 setting more, since some assemblers will give an error for this. Also,
7067 we must be careful to avoid shifts of 32 bits or more to avoid getting
7068 unpredictable results. */
7070 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7072 switch (TREE_CODE (type))
7078 qualifiers |= (3 << shift);
7083 qualifiers |= (2 << shift);
7087 case REFERENCE_TYPE:
7089 qualifiers |= (1 << shift);
7093 return (qualifiers | 8);
7096 case QUAL_UNION_TYPE:
7097 return (qualifiers | 9);
7100 return (qualifiers | 10);
7103 return (qualifiers | 16);
7106 /* If this is a range type, consider it to be the underlying
7108 if (TREE_TYPE (type) != 0)
7111 /* Carefully distinguish all the standard types of C,
7112 without messing up if the language is not C. We do this by
7113 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7114 look at both the names and the above fields, but that's redundant.
7115 Any type whose size is between two C types will be considered
7116 to be the wider of the two types. Also, we do not have a
7117 special code to use for "long long", so anything wider than
7118 long is treated the same. Note that we can't distinguish
7119 between "int" and "long" in this code if they are the same
7120 size, but that's fine, since neither can the assembler. */
7122 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7123 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7125 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7126 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7128 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7129 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7132 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7135 /* If this is a range type, consider it to be the underlying
7137 if (TREE_TYPE (type) != 0)
7140 /* Carefully distinguish all the standard types of C,
7141 without messing up if the language is not C. */
7143 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7144 return (qualifiers | 6);
7147 return (qualifiers | 7);
7149 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7150 /* ??? We need to distinguish between double and float complex types,
7151 but I don't know how yet because I can't reach this code from
7152 existing front-ends. */
7153 return (qualifiers | 7); /* Who knows? */
7156 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7157 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7158 case FILE_TYPE: /* GNU Pascal FILE type. */
7159 case SET_TYPE: /* GNU Pascal SET type. */
7160 case LANG_TYPE: /* ? */
7164 abort (); /* Not a type! */
7171 /* Nested function support. */
7173 /* Emit RTL insns to initialize the variable parts of a trampoline.
7174 FNADDR is an RTX for the address of the function's pure code.
7175 CXT is an RTX for the static chain value for the function.
7177 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7178 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7179 (to store insns). This is a bit excessive. Perhaps a different
7180 mechanism would be better here.
7182 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7185 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7187 /* SPARC 32-bit trampoline:
7190 sethi %hi(static), %g2
7192 or %g2, %lo(static), %g2
7194 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7195 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7199 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7200 expand_binop (SImode, ior_optab,
7201 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7202 size_int (10), 0, 1),
7203 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7204 NULL_RTX, 1, OPTAB_DIRECT));
7207 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7208 expand_binop (SImode, ior_optab,
7209 expand_shift (RSHIFT_EXPR, SImode, cxt,
7210 size_int (10), 0, 1),
7211 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7212 NULL_RTX, 1, OPTAB_DIRECT));
7215 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7216 expand_binop (SImode, ior_optab,
7217 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7218 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7219 NULL_RTX, 1, OPTAB_DIRECT));
7222 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7223 expand_binop (SImode, ior_optab,
7224 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7225 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7226 NULL_RTX, 1, OPTAB_DIRECT));
7228 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7229 aligned on a 16 byte boundary so one flush clears it all. */
7230 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7231 if (sparc_cpu != PROCESSOR_ULTRASPARC
7232 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7233 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7234 plus_constant (tramp, 8)))));
7236 /* Call __enable_execute_stack after writing onto the stack to make sure
7237 the stack address is accessible. */
7238 #ifdef TRANSFER_FROM_TRAMPOLINE
7239 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7240 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7245 /* The 64-bit version is simpler because it makes more sense to load the
7246 values as "immediate" data out of the trampoline. It's also easier since
7247 we can read the PC without clobbering a register. */
7250 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7252 /* SPARC 64-bit trampoline:
7261 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7262 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7263 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7264 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7265 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7266 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7267 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7268 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7269 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7270 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7271 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7273 if (sparc_cpu != PROCESSOR_ULTRASPARC
7274 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7275 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7277 /* Call __enable_execute_stack after writing onto the stack to make sure
7278 the stack address is accessible. */
7279 #ifdef TRANSFER_FROM_TRAMPOLINE
7280 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7281 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7285 /* Adjust the cost of a scheduling dependency. Return the new cost of
7286 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7289 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7291 enum attr_type insn_type;
7293 if (! recog_memoized (insn))
7296 insn_type = get_attr_type (insn);
7298 if (REG_NOTE_KIND (link) == 0)
7300 /* Data dependency; DEP_INSN writes a register that INSN reads some
7303 /* if a load, then the dependence must be on the memory address;
7304 add an extra "cycle". Note that the cost could be two cycles
7305 if the reg was written late in an instruction group; we ca not tell
7307 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7310 /* Get the delay only if the address of the store is the dependence. */
7311 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7313 rtx pat = PATTERN(insn);
7314 rtx dep_pat = PATTERN (dep_insn);
7316 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7317 return cost; /* This should not happen! */
7319 /* The dependency between the two instructions was on the data that
7320 is being stored. Assume that this implies that the address of the
7321 store is not dependent. */
7322 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7325 return cost + 3; /* An approximation. */
7328 /* A shift instruction cannot receive its data from an instruction
7329 in the same cycle; add a one cycle penalty. */
7330 if (insn_type == TYPE_SHIFT)
7331 return cost + 3; /* Split before cascade into shift. */
7335 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7336 INSN writes some cycles later. */
7338 /* These are only significant for the fpu unit; writing a fp reg before
7339 the fpu has finished with it stalls the processor. */
7341 /* Reusing an integer register causes no problems. */
7342 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7350 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7352 enum attr_type insn_type, dep_type;
7353 rtx pat = PATTERN(insn);
7354 rtx dep_pat = PATTERN (dep_insn);
7356 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7359 insn_type = get_attr_type (insn);
7360 dep_type = get_attr_type (dep_insn);
7362 switch (REG_NOTE_KIND (link))
7365 /* Data dependency; DEP_INSN writes a register that INSN reads some
7372 /* Get the delay iff the address of the store is the dependence. */
7373 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7376 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7383 /* If a load, then the dependence must be on the memory address. If
7384 the addresses aren't equal, then it might be a false dependency */
7385 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7387 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7388 || GET_CODE (SET_DEST (dep_pat)) != MEM
7389 || GET_CODE (SET_SRC (pat)) != MEM
7390 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7391 XEXP (SET_SRC (pat), 0)))
7399 /* Compare to branch latency is 0. There is no benefit from
7400 separating compare and branch. */
7401 if (dep_type == TYPE_COMPARE)
7403 /* Floating point compare to branch latency is less than
7404 compare to conditional move. */
7405 if (dep_type == TYPE_FPCMP)
7414 /* Anti-dependencies only penalize the fpu unit. */
7415 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7427 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7431 case PROCESSOR_SUPERSPARC:
7432 cost = supersparc_adjust_cost (insn, link, dep, cost);
7434 case PROCESSOR_HYPERSPARC:
7435 case PROCESSOR_SPARCLITE86X:
7436 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7445 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7446 int sched_verbose ATTRIBUTE_UNUSED,
7447 int max_ready ATTRIBUTE_UNUSED)
7452 sparc_use_dfa_pipeline_interface (void)
7454 if ((1 << sparc_cpu) &
7455 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7456 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7457 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7458 (1 << PROCESSOR_ULTRASPARC3)))
7464 sparc_use_sched_lookahead (void)
7466 if (sparc_cpu == PROCESSOR_ULTRASPARC
7467 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7469 if ((1 << sparc_cpu) &
7470 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7471 (1 << PROCESSOR_SPARCLITE86X)))
7477 sparc_issue_rate (void)
7484 /* Assume V9 processors are capable of at least dual-issue. */
7486 case PROCESSOR_SUPERSPARC:
7488 case PROCESSOR_HYPERSPARC:
7489 case PROCESSOR_SPARCLITE86X:
7491 case PROCESSOR_ULTRASPARC:
7492 case PROCESSOR_ULTRASPARC3:
7498 set_extends (rtx insn)
7500 register rtx pat = PATTERN (insn);
7502 switch (GET_CODE (SET_SRC (pat)))
7504 /* Load and some shift instructions zero extend. */
7507 /* sethi clears the high bits */
7509 /* LO_SUM is used with sethi. sethi cleared the high
7510 bits and the values used with lo_sum are positive */
7512 /* Store flag stores 0 or 1 */
7522 rtx op0 = XEXP (SET_SRC (pat), 0);
7523 rtx op1 = XEXP (SET_SRC (pat), 1);
7524 if (GET_CODE (op1) == CONST_INT)
7525 return INTVAL (op1) >= 0;
7526 if (GET_CODE (op0) != REG)
7528 if (sparc_check_64 (op0, insn) == 1)
7530 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7535 rtx op0 = XEXP (SET_SRC (pat), 0);
7536 rtx op1 = XEXP (SET_SRC (pat), 1);
7537 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7539 if (GET_CODE (op1) == CONST_INT)
7540 return INTVAL (op1) >= 0;
7541 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7544 return GET_MODE (SET_SRC (pat)) == SImode;
7545 /* Positive integers leave the high bits zero. */
7547 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7549 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7552 return - (GET_MODE (SET_SRC (pat)) == SImode);
7554 return sparc_check_64 (SET_SRC (pat), insn);
7560 /* We _ought_ to have only one kind per function, but... */
7561 static GTY(()) rtx sparc_addr_diff_list;
7562 static GTY(()) rtx sparc_addr_list;
7565 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7567 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7569 sparc_addr_diff_list
7570 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7572 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7576 sparc_output_addr_vec (rtx vec)
7578 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7579 int idx, vlen = XVECLEN (body, 0);
7581 #ifdef ASM_OUTPUT_ADDR_VEC_START
7582 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7585 #ifdef ASM_OUTPUT_CASE_LABEL
7586 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7589 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7592 for (idx = 0; idx < vlen; idx++)
7594 ASM_OUTPUT_ADDR_VEC_ELT
7595 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7598 #ifdef ASM_OUTPUT_ADDR_VEC_END
7599 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7604 sparc_output_addr_diff_vec (rtx vec)
7606 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7607 rtx base = XEXP (XEXP (body, 0), 0);
7608 int idx, vlen = XVECLEN (body, 1);
7610 #ifdef ASM_OUTPUT_ADDR_VEC_START
7611 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7614 #ifdef ASM_OUTPUT_CASE_LABEL
7615 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7618 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7621 for (idx = 0; idx < vlen; idx++)
7623 ASM_OUTPUT_ADDR_DIFF_ELT
7626 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7627 CODE_LABEL_NUMBER (base));
7630 #ifdef ASM_OUTPUT_ADDR_VEC_END
7631 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7636 sparc_output_deferred_case_vectors (void)
7641 if (sparc_addr_list == NULL_RTX
7642 && sparc_addr_diff_list == NULL_RTX)
7645 /* Align to cache line in the function's code section. */
7646 function_section (current_function_decl);
7648 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7650 ASM_OUTPUT_ALIGN (asm_out_file, align);
7652 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7653 sparc_output_addr_vec (XEXP (t, 0));
7654 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7655 sparc_output_addr_diff_vec (XEXP (t, 0));
7657 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7660 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7661 unknown. Return 1 if the high bits are zero, -1 if the register is
7664 sparc_check_64 (rtx x, rtx insn)
7666 /* If a register is set only once it is safe to ignore insns this
7667 code does not know how to handle. The loop will either recognize
7668 the single set and return the correct value or fail to recognize
7673 if (GET_CODE (x) != REG)
7676 if (GET_MODE (x) == DImode)
7677 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7679 if (flag_expensive_optimizations
7680 && REG_N_SETS (REGNO (y)) == 1)
7686 insn = get_last_insn_anywhere ();
7691 while ((insn = PREV_INSN (insn)))
7693 switch (GET_CODE (insn))
7706 rtx pat = PATTERN (insn);
7707 if (GET_CODE (pat) != SET)
7709 if (rtx_equal_p (x, SET_DEST (pat)))
7710 return set_extends (insn);
7711 if (y && rtx_equal_p (y, SET_DEST (pat)))
7712 return set_extends (insn);
7713 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7721 /* Returns assembly code to perform a DImode shift using
7722 a 64-bit global or out register on SPARC-V8+. */
7724 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7726 static char asm_code[60];
7728 /* The scratch register is only required when the destination
7729 register is not a 64-bit global or out register. */
7730 if (which_alternative != 2)
7731 operands[3] = operands[0];
7733 /* We can only shift by constants <= 63. */
7734 if (GET_CODE (operands[2]) == CONST_INT)
7735 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7737 if (GET_CODE (operands[1]) == CONST_INT)
7739 output_asm_insn ("mov\t%1, %3", operands);
7743 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7744 if (sparc_check_64 (operands[1], insn) <= 0)
7745 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7746 output_asm_insn ("or\t%L1, %3, %3", operands);
7749 strcpy(asm_code, opcode);
7751 if (which_alternative != 2)
7752 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7754 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7757 /* Output rtl to increment the profiler label LABELNO
7758 for profiling a function entry. */
7761 sparc_profile_hook (int labelno)
7766 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7767 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7768 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7770 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7773 #ifdef OBJECT_FORMAT_ELF
7775 sparc_elf_asm_named_section (const char *name, unsigned int flags)
7777 if (flags & SECTION_MERGE)
7779 /* entsize cannot be expressed in this section attributes
7781 default_elf_asm_named_section (name, flags);
7785 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
7787 if (!(flags & SECTION_DEBUG))
7788 fputs (",#alloc", asm_out_file);
7789 if (flags & SECTION_WRITE)
7790 fputs (",#write", asm_out_file);
7791 if (flags & SECTION_TLS)
7792 fputs (",#tls", asm_out_file);
7793 if (flags & SECTION_CODE)
7794 fputs (",#execinstr", asm_out_file);
7796 /* ??? Handle SECTION_BSS. */
7798 fputc ('\n', asm_out_file);
7800 #endif /* OBJECT_FORMAT_ELF */
7802 /* We do not allow indirect calls to be optimized into sibling calls.
7804 Also, on SPARC 32-bit we cannot emit a sibling call when the
7805 current function returns a structure. This is because the "unimp
7806 after call" convention would cause the callee to return to the
7807 wrong place. The generic code already disallows cases where the
7808 function being called returns a structure.
7810 It may seem strange how this last case could occur. Usually there
7811 is code after the call which jumps to epilogue code which dumps the
7812 return value into the struct return area. That ought to invalidate
7813 the sibling call right? Well, in the c++ case we can end up passing
7814 the pointer to the struct return area to a constructor (which returns
7815 void) and then nothing else happens. Such a sibling call would look
7816 valid without the added check here. */
7818 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7820 return (decl && (TARGET_ARCH64 || ! current_function_returns_struct));
7823 /* libfunc renaming. */
7824 #include "config/gofast.h"
7827 sparc_init_libfuncs (void)
7831 /* Use the subroutines that Sun's library provides for integer
7832 multiply and divide. The `*' prevents an underscore from
7833 being prepended by the compiler. .umul is a little faster
7835 set_optab_libfunc (smul_optab, SImode, "*.umul");
7836 set_optab_libfunc (sdiv_optab, SImode, "*.div");
7837 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
7838 set_optab_libfunc (smod_optab, SImode, "*.rem");
7839 set_optab_libfunc (umod_optab, SImode, "*.urem");
7841 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7842 set_optab_libfunc (add_optab, TFmode, "_Q_add");
7843 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
7844 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
7845 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
7846 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
7848 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7849 is because with soft-float, the SFmode and DFmode sqrt
7850 instructions will be absent, and the compiler will notice and
7851 try to use the TFmode sqrt instruction for calls to the
7852 builtin function sqrt, but this fails. */
7854 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
7856 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
7857 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
7858 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
7859 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
7860 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
7861 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
7863 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
7864 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
7865 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
7866 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
7868 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
7869 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
7870 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
7872 if (DITF_CONVERSION_LIBFUNCS)
7874 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
7875 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
7876 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
7879 if (SUN_CONVERSION_LIBFUNCS)
7881 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
7882 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
7883 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
7884 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
7889 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7890 do not exist in the library. Make sure the compiler does not
7891 emit calls to them by accident. (It should always use the
7892 hardware instructions.) */
7893 set_optab_libfunc (smul_optab, SImode, 0);
7894 set_optab_libfunc (sdiv_optab, SImode, 0);
7895 set_optab_libfunc (udiv_optab, SImode, 0);
7896 set_optab_libfunc (smod_optab, SImode, 0);
7897 set_optab_libfunc (umod_optab, SImode, 0);
7899 if (SUN_INTEGER_MULTIPLY_64)
7901 set_optab_libfunc (smul_optab, DImode, "__mul64");
7902 set_optab_libfunc (sdiv_optab, DImode, "__div64");
7903 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
7904 set_optab_libfunc (smod_optab, DImode, "__rem64");
7905 set_optab_libfunc (umod_optab, DImode, "__urem64");
7908 if (SUN_CONVERSION_LIBFUNCS)
7910 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
7911 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
7912 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
7913 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
7917 gofast_maybe_init_libfuncs ();
7921 sparc_extra_constraint_check (rtx op, int c, int strict)
7926 && (c == 'T' || c == 'U'))
7932 return fp_sethi_p (op);
7935 return fp_mov_p (op);
7938 return fp_high_losum_p (op);
7942 || (GET_CODE (op) == REG
7943 && (REGNO (op) < FIRST_PSEUDO_REGISTER
7944 || reg_renumber[REGNO (op)] >= 0)))
7945 return register_ok_for_ldd (op);
7957 /* Our memory extra constraints have to emulate the
7958 behavior of 'm' and 'o' in order for reload to work
7960 if (GET_CODE (op) == MEM)
7963 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
7965 || strict_memory_address_p (Pmode, XEXP (op, 0))))
7970 reload_ok_mem = (reload_in_progress
7971 && GET_CODE (op) == REG
7972 && REGNO (op) >= FIRST_PSEUDO_REGISTER
7973 && reg_renumber [REGNO (op)] < 0);
7976 return reload_ok_mem;
7979 /* ??? This duplicates information provided to the compiler by the
7980 ??? scheduler description. Some day, teach genautomata to output
7981 ??? the latencies and then CSE will just use that. */
7984 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
7988 case PLUS: case MINUS: case ABS: case NEG:
7989 case FLOAT: case UNSIGNED_FLOAT:
7990 case FIX: case UNSIGNED_FIX:
7991 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
7992 if (FLOAT_MODE_P (GET_MODE (x)))
7996 case PROCESSOR_ULTRASPARC:
7997 case PROCESSOR_ULTRASPARC3:
7998 *total = COSTS_N_INSNS (4);
8001 case PROCESSOR_SUPERSPARC:
8002 *total = COSTS_N_INSNS (3);
8005 case PROCESSOR_CYPRESS:
8006 *total = COSTS_N_INSNS (5);
8009 case PROCESSOR_HYPERSPARC:
8010 case PROCESSOR_SPARCLITE86X:
8012 *total = COSTS_N_INSNS (1);
8017 *total = COSTS_N_INSNS (1);
8023 case PROCESSOR_ULTRASPARC:
8024 if (GET_MODE (x) == SFmode)
8025 *total = COSTS_N_INSNS (13);
8027 *total = COSTS_N_INSNS (23);
8030 case PROCESSOR_ULTRASPARC3:
8031 if (GET_MODE (x) == SFmode)
8032 *total = COSTS_N_INSNS (20);
8034 *total = COSTS_N_INSNS (29);
8037 case PROCESSOR_SUPERSPARC:
8038 *total = COSTS_N_INSNS (12);
8041 case PROCESSOR_CYPRESS:
8042 *total = COSTS_N_INSNS (63);
8045 case PROCESSOR_HYPERSPARC:
8046 case PROCESSOR_SPARCLITE86X:
8047 *total = COSTS_N_INSNS (17);
8051 *total = COSTS_N_INSNS (30);
8056 if (FLOAT_MODE_P (GET_MODE (x)))
8060 case PROCESSOR_ULTRASPARC:
8061 case PROCESSOR_ULTRASPARC3:
8062 *total = COSTS_N_INSNS (1);
8065 case PROCESSOR_SUPERSPARC:
8066 *total = COSTS_N_INSNS (3);
8069 case PROCESSOR_CYPRESS:
8070 *total = COSTS_N_INSNS (5);
8073 case PROCESSOR_HYPERSPARC:
8074 case PROCESSOR_SPARCLITE86X:
8076 *total = COSTS_N_INSNS (1);
8081 /* ??? Maybe mark integer compares as zero cost on
8082 ??? all UltraSPARC processors because the result
8083 ??? can be bypassed to a branch in the same group. */
8085 *total = COSTS_N_INSNS (1);
8089 if (FLOAT_MODE_P (GET_MODE (x)))
8093 case PROCESSOR_ULTRASPARC:
8094 case PROCESSOR_ULTRASPARC3:
8095 *total = COSTS_N_INSNS (4);
8098 case PROCESSOR_SUPERSPARC:
8099 *total = COSTS_N_INSNS (3);
8102 case PROCESSOR_CYPRESS:
8103 *total = COSTS_N_INSNS (7);
8106 case PROCESSOR_HYPERSPARC:
8107 case PROCESSOR_SPARCLITE86X:
8108 *total = COSTS_N_INSNS (1);
8112 *total = COSTS_N_INSNS (5);
8117 /* The latency is actually variable for Ultra-I/II
8118 And if one of the inputs have a known constant
8119 value, we could calculate this precisely.
8121 However, for that to be useful we would need to
8122 add some machine description changes which would
8123 make sure small constants ended up in rs1 of the
8124 multiply instruction. This is because the multiply
8125 latency is determined by the number of clear (or
8126 set if the value is negative) bits starting from
8127 the most significant bit of the first input.
8129 The algorithm for computing num_cycles of a multiply
8133 highest_bit = highest_clear_bit(rs1);
8135 highest_bit = highest_set_bit(rs1);
8138 num_cycles = 4 + ((highest_bit - 3) / 2);
8140 If we did that we would have to also consider register
8141 allocation issues that would result from forcing such
8142 a value into a register.
8144 There are other similar tricks we could play if we
8145 knew, for example, that one input was an array index.
8147 Since we do not play any such tricks currently the
8148 safest thing to do is report the worst case latency. */
8149 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8151 *total = (GET_MODE (x) == DImode
8152 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8156 /* Multiply latency on Ultra-III, fortunately, is constant. */
8157 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8159 *total = COSTS_N_INSNS (6);
8163 if (sparc_cpu == PROCESSOR_HYPERSPARC
8164 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8166 *total = COSTS_N_INSNS (17);
8170 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8177 if (FLOAT_MODE_P (GET_MODE (x)))
8181 case PROCESSOR_ULTRASPARC:
8182 if (GET_MODE (x) == SFmode)
8183 *total = COSTS_N_INSNS (13);
8185 *total = COSTS_N_INSNS (23);
8188 case PROCESSOR_ULTRASPARC3:
8189 if (GET_MODE (x) == SFmode)
8190 *total = COSTS_N_INSNS (17);
8192 *total = COSTS_N_INSNS (20);
8195 case PROCESSOR_SUPERSPARC:
8196 if (GET_MODE (x) == SFmode)
8197 *total = COSTS_N_INSNS (6);
8199 *total = COSTS_N_INSNS (9);
8202 case PROCESSOR_HYPERSPARC:
8203 case PROCESSOR_SPARCLITE86X:
8204 if (GET_MODE (x) == SFmode)
8205 *total = COSTS_N_INSNS (8);
8207 *total = COSTS_N_INSNS (12);
8211 *total = COSTS_N_INSNS (7);
8216 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8217 *total = (GET_MODE (x) == DImode
8218 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8219 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8220 *total = (GET_MODE (x) == DImode
8221 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8223 *total = COSTS_N_INSNS (25);
8227 /* Conditional moves. */
8230 case PROCESSOR_ULTRASPARC:
8231 *total = COSTS_N_INSNS (2);
8234 case PROCESSOR_ULTRASPARC3:
8235 if (FLOAT_MODE_P (GET_MODE (x)))
8236 *total = COSTS_N_INSNS (3);
8238 *total = COSTS_N_INSNS (2);
8242 *total = COSTS_N_INSNS (1);
8247 /* If outer-code is SIGN/ZERO extension we have to subtract
8248 out COSTS_N_INSNS (1) from whatever we return in determining
8252 case PROCESSOR_ULTRASPARC:
8253 if (outer_code == ZERO_EXTEND)
8254 *total = COSTS_N_INSNS (1);
8256 *total = COSTS_N_INSNS (2);
8259 case PROCESSOR_ULTRASPARC3:
8260 if (outer_code == ZERO_EXTEND)
8262 if (GET_MODE (x) == QImode
8263 || GET_MODE (x) == HImode
8264 || outer_code == SIGN_EXTEND)
8265 *total = COSTS_N_INSNS (2);
8267 *total = COSTS_N_INSNS (1);
8271 /* This handles sign extension (3 cycles)
8272 and everything else (2 cycles). */
8273 *total = COSTS_N_INSNS (2);
8277 case PROCESSOR_SUPERSPARC:
8278 if (FLOAT_MODE_P (GET_MODE (x))
8279 || outer_code == ZERO_EXTEND
8280 || outer_code == SIGN_EXTEND)
8281 *total = COSTS_N_INSNS (0);
8283 *total = COSTS_N_INSNS (1);
8286 case PROCESSOR_TSC701:
8287 if (outer_code == ZERO_EXTEND
8288 || outer_code == SIGN_EXTEND)
8289 *total = COSTS_N_INSNS (2);
8291 *total = COSTS_N_INSNS (3);
8294 case PROCESSOR_CYPRESS:
8295 if (outer_code == ZERO_EXTEND
8296 || outer_code == SIGN_EXTEND)
8297 *total = COSTS_N_INSNS (1);
8299 *total = COSTS_N_INSNS (2);
8302 case PROCESSOR_HYPERSPARC:
8303 case PROCESSOR_SPARCLITE86X:
8305 if (outer_code == ZERO_EXTEND
8306 || outer_code == SIGN_EXTEND)
8307 *total = COSTS_N_INSNS (0);
8309 *total = COSTS_N_INSNS (1);
8314 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8332 if (GET_MODE (x) == DImode
8333 && ((XINT (x, 3) == 0
8334 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8335 || (XINT (x, 3) == -1
8337 && XINT (x, 2) >= -0x1000)))
8348 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8349 Used for C++ multiple inheritance. */
8352 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8353 HOST_WIDE_INT delta,
8354 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8357 rtx this, insn, funexp, delta_rtx, tmp;
8359 reload_completed = 1;
8360 epilogue_completed = 1;
8362 current_function_uses_only_leaf_regs = 1;
8363 reset_block_changes ();
8365 emit_note (NOTE_INSN_PROLOGUE_END);
8367 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8368 returns a structure, the structure return pointer is there instead. */
8369 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8370 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8372 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8374 /* Add DELTA. When possible use a plain add, otherwise load it into
8375 a register first. */
8376 delta_rtx = GEN_INT (delta);
8377 if (!SPARC_SIMM13_P (delta))
8379 rtx scratch = gen_rtx_REG (Pmode, 1);
8381 if (input_operand (delta_rtx, GET_MODE (scratch)))
8382 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8386 sparc_emit_set_const64 (scratch, delta_rtx);
8388 sparc_emit_set_const32 (scratch, delta_rtx);
8391 delta_rtx = scratch;
8394 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8395 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8397 /* Generate a tail call to the target function. */
8398 if (! TREE_USED (function))
8400 assemble_external (function);
8401 TREE_USED (function) = 1;
8403 funexp = XEXP (DECL_RTL (function), 0);
8404 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8405 insn = emit_call_insn (gen_sibcall (funexp));
8406 SIBLING_CALL_P (insn) = 1;
8409 /* Run just enough of rest_of_compilation to get the insns emitted.
8410 There's not really enough bulk here to make other passes such as
8411 instruction scheduling worth while. Note that use_thunk calls
8412 assemble_start_function and assemble_end_function. */
8413 insn = get_insns ();
8414 insn_locators_initialize ();
8415 shorten_branches (insn);
8416 final_start_function (insn, file, 1);
8417 final (insn, file, 1, 0);
8418 final_end_function ();
8420 reload_completed = 0;
8421 epilogue_completed = 0;
8425 /* How to allocate a 'struct machine_function'. */
8427 static struct machine_function *
8428 sparc_init_machine_status (void)
8430 return ggc_alloc_cleared (sizeof (struct machine_function));
8433 /* Locate some local-dynamic symbol still in use by this function
8434 so that we can print its name in local-dynamic base patterns. */
8437 get_some_local_dynamic_name (void)
8441 if (cfun->machine->some_ld_name)
8442 return cfun->machine->some_ld_name;
8444 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8446 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8447 return cfun->machine->some_ld_name;
8453 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8458 && GET_CODE (x) == SYMBOL_REF
8459 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8461 cfun->machine->some_ld_name = XSTR (x, 0);
8468 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8469 We need to emit DTP-relative relocations. */
8472 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8477 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8480 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8485 output_addr_const (file, x);
8489 #include "gt-sparc.h"