1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize;
69 static int actual_fsize;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0, sparc_compare_op1;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name;
126 static int frame_base_offset;
128 static void sparc_init_modes PARAMS ((void));
129 static int save_regs PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *,
134 enum machine_mode, tree, int, int,
137 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
138 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
140 static void sparc_output_addr_vec PARAMS ((rtx));
141 static void sparc_output_addr_diff_vec PARAMS ((rtx));
142 static void sparc_output_deferred_case_vectors PARAMS ((void));
143 static int check_return_regs PARAMS ((rtx));
144 static int epilogue_renumber PARAMS ((rtx *, int));
145 static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
146 static int set_extends PARAMS ((rtx));
147 static void output_restore_regs PARAMS ((FILE *, int));
148 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
149 static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
150 static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
151 static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
152 static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
154 static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
156 #ifdef OBJECT_FORMAT_ELF
157 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
159 static void sparc_aout_select_section PARAMS ((tree, int,
160 unsigned HOST_WIDE_INT))
162 static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx,
163 unsigned HOST_WIDE_INT))
166 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
167 static int sparc_issue_rate PARAMS ((void));
168 static void sparc_sched_init PARAMS ((FILE *, int, int));
169 static int sparc_use_dfa_pipeline_interface PARAMS ((void));
170 static int sparc_use_sched_lookahead PARAMS ((void));
172 static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
173 static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
174 static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
175 static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
176 static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
178 static void sparc_encode_section_info PARAMS ((tree, int));
179 static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, tree));
181 /* Option handling. */
183 /* Code model option as passed by user. */
184 const char *sparc_cmodel_string;
186 enum cmodel sparc_cmodel;
188 char sparc_hard_reg_printed[8];
190 struct sparc_cpu_select sparc_select[] =
192 /* switch name, tune arch */
193 { (char *)0, "default", 1, 1 },
194 { (char *)0, "-mcpu=", 1, 1 },
195 { (char *)0, "-mtune=", 1, 0 },
199 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
200 enum processor_type sparc_cpu;
202 /* Initialize the GCC target structure. */
204 /* The sparc default is to use .half rather than .short for aligned
205 HI objects. Use .word instead of .long on non-ELF systems. */
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
208 #ifndef OBJECT_FORMAT_ELF
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
213 #undef TARGET_ASM_UNALIGNED_HI_OP
214 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
215 #undef TARGET_ASM_UNALIGNED_SI_OP
216 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
217 #undef TARGET_ASM_UNALIGNED_DI_OP
218 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
220 /* The target hook has to handle DI-mode values. */
221 #undef TARGET_ASM_INTEGER
222 #define TARGET_ASM_INTEGER sparc_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
226 #undef TARGET_ASM_FUNCTION_EPILOGUE
227 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
231 #undef TARGET_SCHED_ISSUE_RATE
232 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
233 #undef TARGET_SCHED_INIT
234 #define TARGET_SCHED_INIT sparc_sched_init
235 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
236 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
237 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
238 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
240 #undef TARGET_ENCODE_SECTION_INFO
241 #define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info
243 #undef TARGET_ASM_OUTPUT_MI_THUNK
244 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
246 struct gcc_target targetm = TARGET_INITIALIZER;
248 /* Validate and override various options, and do some machine dependent
252 sparc_override_options ()
254 static struct code_model {
255 const char *const name;
257 } const cmodels[] = {
259 { "medlow", CM_MEDLOW },
260 { "medmid", CM_MEDMID },
261 { "medany", CM_MEDANY },
262 { "embmedany", CM_EMBMEDANY },
265 const struct code_model *cmodel;
266 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
267 static struct cpu_default {
269 const char *const name;
270 } const cpu_default[] = {
271 /* There must be one entry here for each TARGET_CPU value. */
272 { TARGET_CPU_sparc, "cypress" },
273 { TARGET_CPU_sparclet, "tsc701" },
274 { TARGET_CPU_sparclite, "f930" },
275 { TARGET_CPU_v8, "v8" },
276 { TARGET_CPU_hypersparc, "hypersparc" },
277 { TARGET_CPU_sparclite86x, "sparclite86x" },
278 { TARGET_CPU_supersparc, "supersparc" },
279 { TARGET_CPU_v9, "v9" },
280 { TARGET_CPU_ultrasparc, "ultrasparc" },
281 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
284 const struct cpu_default *def;
285 /* Table of values for -m{cpu,tune}=. */
286 static struct cpu_table {
287 const char *const name;
288 const enum processor_type processor;
291 } const cpu_table[] = {
292 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
293 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
294 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
295 /* TI TMS390Z55 supersparc */
296 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
297 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
298 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
299 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
300 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
301 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
302 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
303 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
305 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
307 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
308 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
309 /* TI ultrasparc I, II, IIi */
310 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
311 /* Although insns using %y are deprecated, it is a clear win on current
313 |MASK_DEPRECATED_V8_INSNS},
314 /* TI ultrasparc III */
315 /* ??? Check if %y issue still holds true in ultra3. */
316 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
319 const struct cpu_table *cpu;
320 const struct sparc_cpu_select *sel;
323 #ifndef SPARC_BI_ARCH
324 /* Check for unsupported architecture size. */
325 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
326 error ("%s is not supported by this configuration",
327 DEFAULT_ARCH32_P ? "-m64" : "-m32");
330 /* We force all 64bit archs to use 128 bit long double */
331 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
333 error ("-mlong-double-64 not allowed with -m64");
334 target_flags |= MASK_LONG_DOUBLE_128;
337 /* Code model selection. */
338 sparc_cmodel = SPARC_DEFAULT_CMODEL;
342 sparc_cmodel = CM_32;
345 if (sparc_cmodel_string != NULL)
349 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
350 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
352 if (cmodel->name == NULL)
353 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
355 sparc_cmodel = cmodel->value;
358 error ("-mcmodel= is not supported on 32 bit systems");
361 fpu = TARGET_FPU; /* save current -mfpu status */
363 /* Set the default CPU. */
364 for (def = &cpu_default[0]; def->name; ++def)
365 if (def->cpu == TARGET_CPU_DEFAULT)
369 sparc_select[0].string = def->name;
371 for (sel = &sparc_select[0]; sel->name; ++sel)
375 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
376 if (! strcmp (sel->string, cpu->name))
379 sparc_cpu = cpu->processor;
383 target_flags &= ~cpu->disable;
384 target_flags |= cpu->enable;
390 error ("bad value (%s) for %s switch", sel->string, sel->name);
394 /* If -mfpu or -mno-fpu was explicitly used, don't override with
395 the processor default. Clear MASK_FPU_SET to avoid confusing
396 the reverse mapping from switch values to names. */
399 target_flags = (target_flags & ~MASK_FPU) | fpu;
400 target_flags &= ~MASK_FPU_SET;
403 /* Don't allow -mvis if FPU is disabled. */
405 target_flags &= ~MASK_VIS;
407 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
409 -m64 also implies v9. */
410 if (TARGET_VIS || TARGET_ARCH64)
412 target_flags |= MASK_V9;
413 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
416 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
417 if (TARGET_V9 && TARGET_ARCH32)
418 target_flags |= MASK_DEPRECATED_V8_INSNS;
420 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
421 if (! TARGET_V9 || TARGET_ARCH64)
422 target_flags &= ~MASK_V8PLUS;
424 /* Don't use stack biasing in 32 bit mode. */
426 target_flags &= ~MASK_STACK_BIAS;
428 /* Supply a default value for align_functions. */
429 if (align_functions == 0
430 && (sparc_cpu == PROCESSOR_ULTRASPARC
431 || sparc_cpu == PROCESSOR_ULTRASPARC3))
432 align_functions = 32;
434 /* Validate PCC_STRUCT_RETURN. */
435 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
436 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
438 /* Only use .uaxword when compiling for a 64-bit target. */
440 targetm.asm_out.unaligned_op.di = NULL;
442 /* Do various machine dependent initializations. */
446 /* Miscellaneous utilities. */
448 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
449 or branch on register contents instructions. */
455 return (code == EQ || code == NE || code == GE || code == LT
456 || code == LE || code == GT);
460 /* Operand constraints. */
462 /* Return nonzero only if OP is a register of mode MODE,
466 reg_or_0_operand (op, mode)
468 enum machine_mode mode;
470 if (register_operand (op, mode))
472 if (op == const0_rtx)
474 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
475 && CONST_DOUBLE_HIGH (op) == 0
476 && CONST_DOUBLE_LOW (op) == 0)
478 if (fp_zero_operand (op, mode))
483 /* Return nonzero only if OP is const1_rtx. */
486 const1_operand (op, mode)
488 enum machine_mode mode ATTRIBUTE_UNUSED;
490 return op == const1_rtx;
493 /* Nonzero if OP is a floating point value with value 0.0. */
496 fp_zero_operand (op, mode)
498 enum machine_mode mode;
500 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
502 return op == CONST0_RTX (mode);
505 /* Nonzero if OP is a register operand in floating point register. */
508 fp_register_operand (op, mode)
510 enum machine_mode mode;
512 if (! register_operand (op, mode))
514 if (GET_CODE (op) == SUBREG)
515 op = SUBREG_REG (op);
516 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
519 /* Nonzero if OP is a floating point constant which can
520 be loaded into an integer register using a single
521 sethi instruction. */
527 if (GET_CODE (op) == CONST_DOUBLE)
532 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
533 if (REAL_VALUES_EQUAL (r, dconst0) &&
534 ! REAL_VALUE_MINUS_ZERO (r))
536 REAL_VALUE_TO_TARGET_SINGLE (r, i);
537 if (SPARC_SETHI_P (i))
544 /* Nonzero if OP is a floating point constant which can
545 be loaded into an integer register using a single
552 if (GET_CODE (op) == CONST_DOUBLE)
557 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
558 if (REAL_VALUES_EQUAL (r, dconst0) &&
559 ! REAL_VALUE_MINUS_ZERO (r))
561 REAL_VALUE_TO_TARGET_SINGLE (r, i);
562 if (SPARC_SIMM13_P (i))
569 /* Nonzero if OP is a floating point constant which can
570 be loaded into an integer register using a high/losum
571 instruction sequence. */
577 /* The constraints calling this should only be in
578 SFmode move insns, so any constant which cannot
579 be moved using a single insn will do. */
580 if (GET_CODE (op) == CONST_DOUBLE)
585 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
586 if (REAL_VALUES_EQUAL (r, dconst0) &&
587 ! REAL_VALUE_MINUS_ZERO (r))
589 REAL_VALUE_TO_TARGET_SINGLE (r, i);
590 if (! SPARC_SETHI_P (i)
591 && ! SPARC_SIMM13_P (i))
598 /* Nonzero if OP is an integer register. */
601 intreg_operand (op, mode)
603 enum machine_mode mode ATTRIBUTE_UNUSED;
605 return (register_operand (op, SImode)
606 || (TARGET_ARCH64 && register_operand (op, DImode)));
609 /* Nonzero if OP is a floating point condition code register. */
612 fcc_reg_operand (op, mode)
614 enum machine_mode mode;
616 /* This can happen when recog is called from combine. Op may be a MEM.
617 Fail instead of calling abort in this case. */
618 if (GET_CODE (op) != REG)
621 if (mode != VOIDmode && mode != GET_MODE (op))
624 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
627 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
628 if (reg_renumber == 0)
629 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
630 return REGNO_OK_FOR_CCFP_P (REGNO (op));
632 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
636 /* Nonzero if OP is a floating point condition code fcc0 register. */
639 fcc0_reg_operand (op, mode)
641 enum machine_mode mode;
643 /* This can happen when recog is called from combine. Op may be a MEM.
644 Fail instead of calling abort in this case. */
645 if (GET_CODE (op) != REG)
648 if (mode != VOIDmode && mode != GET_MODE (op))
651 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
654 return REGNO (op) == SPARC_FCC_REG;
657 /* Nonzero if OP is an integer or floating point condition code register. */
660 icc_or_fcc_reg_operand (op, mode)
662 enum machine_mode mode;
664 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
666 if (mode != VOIDmode && mode != GET_MODE (op))
669 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
674 return fcc_reg_operand (op, mode);
677 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
679 restore_operand (op, mode)
681 enum machine_mode mode;
683 return (GET_CODE (op) == REG && GET_MODE (op) == mode
684 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
687 /* Call insn on SPARC can take a PC-relative constant address, or any regular
691 call_operand (op, mode)
693 enum machine_mode mode;
695 if (GET_CODE (op) != MEM)
698 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
702 call_operand_address (op, mode)
704 enum machine_mode mode;
706 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
709 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
710 reference and a constant. */
713 symbolic_operand (op, mode)
715 enum machine_mode mode;
717 enum machine_mode omode = GET_MODE (op);
719 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
722 switch (GET_CODE (op))
730 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
731 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
732 && GET_CODE (XEXP (op, 1)) == CONST_INT);
739 /* Return truth value of statement that OP is a symbolic memory
740 operand of mode MODE. */
743 symbolic_memory_operand (op, mode)
745 enum machine_mode mode ATTRIBUTE_UNUSED;
747 if (GET_CODE (op) == SUBREG)
748 op = SUBREG_REG (op);
749 if (GET_CODE (op) != MEM)
752 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
753 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
756 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
759 label_ref_operand (op, mode)
761 enum machine_mode mode;
763 if (GET_CODE (op) != LABEL_REF)
765 if (GET_MODE (op) != mode)
770 /* Return 1 if the operand is an argument used in generating pic references
771 in either the medium/low or medium/anywhere code models of sparc64. */
774 sp64_medium_pic_operand (op, mode)
776 enum machine_mode mode ATTRIBUTE_UNUSED;
778 /* Check for (const (minus (symbol_ref:GOT)
779 (const (minus (label) (pc))))). */
780 if (GET_CODE (op) != CONST)
783 if (GET_CODE (op) != MINUS)
785 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
787 /* ??? Ensure symbol is GOT. */
788 if (GET_CODE (XEXP (op, 1)) != CONST)
790 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
795 /* Return 1 if the operand is a data segment reference. This includes
796 the readonly data segment, or in other words anything but the text segment.
797 This is needed in the medium/anywhere code model on v9. These values
798 are accessed with EMBMEDANY_BASE_REG. */
801 data_segment_operand (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 switch (GET_CODE (op))
808 return ! SYMBOL_REF_FLAG (op);
810 /* Assume canonical format of symbol + constant.
813 return data_segment_operand (XEXP (op, 0), VOIDmode);
819 /* Return 1 if the operand is a text segment reference.
820 This is needed in the medium/anywhere code model on v9. */
823 text_segment_operand (op, mode)
825 enum machine_mode mode ATTRIBUTE_UNUSED;
827 switch (GET_CODE (op))
832 return SYMBOL_REF_FLAG (op);
834 /* Assume canonical format of symbol + constant.
837 return text_segment_operand (XEXP (op, 0), VOIDmode);
843 /* Return 1 if the operand is either a register or a memory operand that is
847 reg_or_nonsymb_mem_operand (op, mode)
849 enum machine_mode mode;
851 if (register_operand (op, mode))
854 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
861 splittable_symbolic_memory_operand (op, mode)
863 enum machine_mode mode ATTRIBUTE_UNUSED;
865 if (GET_CODE (op) != MEM)
867 if (! symbolic_operand (XEXP (op, 0), Pmode))
873 splittable_immediate_memory_operand (op, mode)
875 enum machine_mode mode ATTRIBUTE_UNUSED;
877 if (GET_CODE (op) != MEM)
879 if (! immediate_operand (XEXP (op, 0), Pmode))
884 /* Return truth value of whether OP is EQ or NE. */
889 enum machine_mode mode ATTRIBUTE_UNUSED;
891 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
894 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
895 or LTU for non-floating-point. We handle those specially. */
898 normal_comp_operator (op, mode)
900 enum machine_mode mode ATTRIBUTE_UNUSED;
902 enum rtx_code code = GET_CODE (op);
904 if (GET_RTX_CLASS (code) != '<')
907 if (GET_MODE (XEXP (op, 0)) == CCFPmode
908 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
911 return (code != NE && code != EQ && code != GEU && code != LTU);
914 /* Return 1 if this is a comparison operator. This allows the use of
915 MATCH_OPERATOR to recognize all the branch insns. */
918 noov_compare_op (op, mode)
920 enum machine_mode mode ATTRIBUTE_UNUSED;
922 enum rtx_code code = GET_CODE (op);
924 if (GET_RTX_CLASS (code) != '<')
927 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
928 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
929 /* These are the only branches which work with CC_NOOVmode. */
930 return (code == EQ || code == NE || code == GE || code == LT);
934 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
935 MATCH_OPERATOR to recognize all the branch insns. */
938 noov_compare64_op (op, mode)
940 enum machine_mode mode ATTRIBUTE_UNUSED;
942 enum rtx_code code = GET_CODE (op);
947 if (GET_RTX_CLASS (code) != '<')
950 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
951 /* These are the only branches which work with CCX_NOOVmode. */
952 return (code == EQ || code == NE || code == GE || code == LT);
953 return (GET_MODE (XEXP (op, 0)) == CCXmode);
956 /* Nonzero if OP is a comparison operator suitable for use in v9
957 conditional move or branch on register contents instructions. */
960 v9_regcmp_op (op, mode)
962 enum machine_mode mode ATTRIBUTE_UNUSED;
964 enum rtx_code code = GET_CODE (op);
966 if (GET_RTX_CLASS (code) != '<')
969 return v9_regcmp_p (code);
972 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
977 enum machine_mode mode ATTRIBUTE_UNUSED;
979 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
982 /* Return nonzero if OP is an operator of mode MODE which can set
983 the condition codes explicitly. We do not include PLUS and MINUS
984 because these require CC_NOOVmode, which we handle explicitly. */
987 cc_arithop (op, mode)
989 enum machine_mode mode ATTRIBUTE_UNUSED;
991 if (GET_CODE (op) == AND
992 || GET_CODE (op) == IOR
993 || GET_CODE (op) == XOR)
999 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1000 complement its second operand and set the condition codes explicitly. */
1003 cc_arithopn (op, mode)
1005 enum machine_mode mode ATTRIBUTE_UNUSED;
1007 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1008 and (xor ... (not ...)) to (not (xor ...)). */
1009 return (GET_CODE (op) == AND
1010 || GET_CODE (op) == IOR);
1013 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1014 signed 13 bit immediate field. This is an acceptable SImode operand for
1015 most 3 address instructions. */
1018 arith_operand (op, mode)
1020 enum machine_mode mode;
1022 if (register_operand (op, mode))
1024 if (GET_CODE (op) != CONST_INT)
1026 return SMALL_INT32 (op);
1029 /* Return true if OP is a constant 4096 */
1032 arith_4096_operand (op, mode)
1034 enum machine_mode mode ATTRIBUTE_UNUSED;
1036 if (GET_CODE (op) != CONST_INT)
1039 return INTVAL (op) == 4096;
1042 /* Return true if OP is suitable as second operand for add/sub */
1045 arith_add_operand (op, mode)
1047 enum machine_mode mode;
1049 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1052 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1053 immediate field of OR and XOR instructions. Used for 64-bit
1054 constant formation patterns. */
1056 const64_operand (op, mode)
1058 enum machine_mode mode ATTRIBUTE_UNUSED;
1060 return ((GET_CODE (op) == CONST_INT
1061 && SPARC_SIMM13_P (INTVAL (op)))
1062 #if HOST_BITS_PER_WIDE_INT != 64
1063 || (GET_CODE (op) == CONST_DOUBLE
1064 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1065 && (CONST_DOUBLE_HIGH (op) ==
1066 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1067 (HOST_WIDE_INT)-1 : 0)))
1072 /* The same, but only for sethi instructions. */
1074 const64_high_operand (op, mode)
1076 enum machine_mode mode;
1078 return ((GET_CODE (op) == CONST_INT
1079 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1080 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1082 || (GET_CODE (op) == CONST_DOUBLE
1083 && CONST_DOUBLE_HIGH (op) == 0
1084 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1085 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1088 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1089 signed 11 bit immediate field. This is an acceptable SImode operand for
1090 the movcc instructions. */
1093 arith11_operand (op, mode)
1095 enum machine_mode mode;
1097 return (register_operand (op, mode)
1098 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1101 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1102 signed 10 bit immediate field. This is an acceptable SImode operand for
1103 the movrcc instructions. */
1106 arith10_operand (op, mode)
1108 enum machine_mode mode;
1110 return (register_operand (op, mode)
1111 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1114 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1115 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1117 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1118 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1119 for most 3 address instructions. */
1122 arith_double_operand (op, mode)
1124 enum machine_mode mode;
1126 return (register_operand (op, mode)
1127 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1129 && GET_CODE (op) == CONST_DOUBLE
1130 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1131 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1133 && GET_CODE (op) == CONST_DOUBLE
1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1135 && ((CONST_DOUBLE_HIGH (op) == -1
1136 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1137 || (CONST_DOUBLE_HIGH (op) == 0
1138 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1141 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1144 arith_double_4096_operand (op, mode)
1146 enum machine_mode mode ATTRIBUTE_UNUSED;
1148 return (TARGET_ARCH64 &&
1149 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1150 (GET_CODE (op) == CONST_DOUBLE &&
1151 CONST_DOUBLE_LOW (op) == 4096 &&
1152 CONST_DOUBLE_HIGH (op) == 0)));
1155 /* Return true if OP is suitable as second operand for add/sub in DImode */
1158 arith_double_add_operand (op, mode)
1160 enum machine_mode mode;
1162 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1165 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1166 can fit in an 11 bit immediate field. This is an acceptable DImode
1167 operand for the movcc instructions. */
1168 /* ??? Replace with arith11_operand? */
1171 arith11_double_operand (op, mode)
1173 enum machine_mode mode;
1175 return (register_operand (op, mode)
1176 || (GET_CODE (op) == CONST_DOUBLE
1177 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1178 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1179 && ((CONST_DOUBLE_HIGH (op) == -1
1180 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1181 || (CONST_DOUBLE_HIGH (op) == 0
1182 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1183 || (GET_CODE (op) == CONST_INT
1184 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1185 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1188 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1189 can fit in an 10 bit immediate field. This is an acceptable DImode
1190 operand for the movrcc instructions. */
1191 /* ??? Replace with arith10_operand? */
1194 arith10_double_operand (op, mode)
1196 enum machine_mode mode;
1198 return (register_operand (op, mode)
1199 || (GET_CODE (op) == CONST_DOUBLE
1200 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1201 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1202 && ((CONST_DOUBLE_HIGH (op) == -1
1203 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1204 || (CONST_DOUBLE_HIGH (op) == 0
1205 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1206 || (GET_CODE (op) == CONST_INT
1207 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1208 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1211 /* Return truth value of whether OP is an integer which fits the
1212 range constraining immediate operands in most three-address insns,
1213 which have a 13 bit immediate field. */
1216 small_int (op, mode)
1218 enum machine_mode mode ATTRIBUTE_UNUSED;
1220 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1224 small_int_or_double (op, mode)
1226 enum machine_mode mode ATTRIBUTE_UNUSED;
1228 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1229 || (GET_CODE (op) == CONST_DOUBLE
1230 && CONST_DOUBLE_HIGH (op) == 0
1231 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1234 /* Recognize operand values for the umul instruction. That instruction sign
1235 extends immediate values just like all other sparc instructions, but
1236 interprets the extended result as an unsigned number. */
1239 uns_small_int (op, mode)
1241 enum machine_mode mode ATTRIBUTE_UNUSED;
1243 #if HOST_BITS_PER_WIDE_INT > 32
1244 /* All allowed constants will fit a CONST_INT. */
1245 return (GET_CODE (op) == CONST_INT
1246 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1247 || (INTVAL (op) >= 0xFFFFF000
1248 && INTVAL (op) <= 0xFFFFFFFF)));
1250 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1251 || (GET_CODE (op) == CONST_DOUBLE
1252 && CONST_DOUBLE_HIGH (op) == 0
1253 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1258 uns_arith_operand (op, mode)
1260 enum machine_mode mode;
1262 return register_operand (op, mode) || uns_small_int (op, mode);
1265 /* Return truth value of statement that OP is a call-clobbered register. */
1267 clobbered_register (op, mode)
1269 enum machine_mode mode ATTRIBUTE_UNUSED;
1271 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1274 /* Return 1 if OP is a valid operand for the source of a move insn. */
1277 input_operand (op, mode)
1279 enum machine_mode mode;
1281 /* If both modes are non-void they must be the same. */
1282 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1285 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1286 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1289 /* Allow any one instruction integer constant, and all CONST_INT
1290 variants when we are working in DImode and !arch64. */
1291 if (GET_MODE_CLASS (mode) == MODE_INT
1292 && ((GET_CODE (op) == CONST_INT
1293 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1294 || SPARC_SIMM13_P (INTVAL (op))
1296 && ! TARGET_ARCH64)))
1298 && GET_CODE (op) == CONST_DOUBLE
1299 && ((CONST_DOUBLE_HIGH (op) == 0
1300 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1302 #if HOST_BITS_PER_WIDE_INT == 64
1303 (CONST_DOUBLE_HIGH (op) == 0
1304 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1306 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1307 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1308 && CONST_DOUBLE_HIGH (op) == 0)
1309 || (CONST_DOUBLE_HIGH (op) == -1
1310 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1315 /* If !arch64 and this is a DImode const, allow it so that
1316 the splits can be generated. */
1319 && GET_CODE (op) == CONST_DOUBLE)
1322 if (register_operand (op, mode))
1325 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1326 && GET_CODE (op) == CONST_DOUBLE)
1329 /* If this is a SUBREG, look inside so that we handle
1330 paradoxical ones. */
1331 if (GET_CODE (op) == SUBREG)
1332 op = SUBREG_REG (op);
1334 /* Check for valid MEM forms. */
1335 if (GET_CODE (op) == MEM)
1337 rtx inside = XEXP (op, 0);
1339 if (GET_CODE (inside) == LO_SUM)
1341 /* We can't allow these because all of the splits
1342 (eventually as they trickle down into DFmode
1343 splits) require offsettable memory references. */
1345 && GET_MODE (op) == TFmode)
1348 return (register_operand (XEXP (inside, 0), Pmode)
1349 && CONSTANT_P (XEXP (inside, 1)));
1351 return memory_address_p (mode, inside);
1358 /* We know it can't be done in one insn when we get here,
1359 the movsi expander guarentees this. */
1361 sparc_emit_set_const32 (op0, op1)
1365 enum machine_mode mode = GET_MODE (op0);
1368 if (GET_CODE (op1) == CONST_INT)
1370 HOST_WIDE_INT value = INTVAL (op1);
1372 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1373 || SPARC_SIMM13_P (value))
1377 /* Full 2-insn decomposition is needed. */
1378 if (reload_in_progress || reload_completed)
1381 temp = gen_reg_rtx (mode);
1383 if (GET_CODE (op1) == CONST_INT)
1385 /* Emit them as real moves instead of a HIGH/LO_SUM,
1386 this way CSE can see everything and reuse intermediate
1387 values if it wants. */
1389 && HOST_BITS_PER_WIDE_INT != 64
1390 && (INTVAL (op1) & 0x80000000) != 0)
1391 emit_insn (gen_rtx_SET
1393 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1396 emit_insn (gen_rtx_SET (VOIDmode, temp,
1397 GEN_INT (INTVAL (op1)
1398 & ~(HOST_WIDE_INT)0x3ff)));
1400 emit_insn (gen_rtx_SET (VOIDmode,
1402 gen_rtx_IOR (mode, temp,
1403 GEN_INT (INTVAL (op1) & 0x3ff))));
1407 /* A symbol, emit in the traditional way. */
1408 emit_insn (gen_rtx_SET (VOIDmode, temp,
1409 gen_rtx_HIGH (mode, op1)));
1410 emit_insn (gen_rtx_SET (VOIDmode,
1411 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1417 /* SPARC-v9 code-model support. */
1419 sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1426 if (temp1 && GET_MODE (temp1) == TImode)
1429 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1432 switch (sparc_cmodel)
1435 /* The range spanned by all instructions in the object is less
1436 than 2^31 bytes (2GB) and the distance from any instruction
1437 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1438 than 2^31 bytes (2GB).
1440 The executable must be in the low 4TB of the virtual address
1443 sethi %hi(symbol), %temp
1444 or %temp, %lo(symbol), %reg */
1445 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1446 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1450 /* The range spanned by all instructions in the object is less
1451 than 2^31 bytes (2GB) and the distance from any instruction
1452 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1453 than 2^31 bytes (2GB).
1455 The executable must be in the low 16TB of the virtual address
1458 sethi %h44(symbol), %temp1
1459 or %temp1, %m44(symbol), %temp2
1460 sllx %temp2, 12, %temp3
1461 or %temp3, %l44(symbol), %reg */
1462 emit_insn (gen_seth44 (op0, op1));
1463 emit_insn (gen_setm44 (op0, op0, op1));
1464 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1465 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1466 emit_insn (gen_setl44 (op0, temp1, op1));
1470 /* The range spanned by all instructions in the object is less
1471 than 2^31 bytes (2GB) and the distance from any instruction
1472 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1473 than 2^31 bytes (2GB).
1475 The executable can be placed anywhere in the virtual address
1478 sethi %hh(symbol), %temp1
1479 sethi %lm(symbol), %temp2
1480 or %temp1, %hm(symbol), %temp3
1481 or %temp2, %lo(symbol), %temp4
1482 sllx %temp3, 32, %temp5
1483 or %temp4, %temp5, %reg */
1485 /* It is possible that one of the registers we got for operands[2]
1486 might coincide with that of operands[0] (which is why we made
1487 it TImode). Pick the other one to use as our scratch. */
1488 if (rtx_equal_p (temp1, op0))
1491 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1496 emit_insn (gen_sethh (op0, op1));
1497 emit_insn (gen_setlm (temp1, op1));
1498 emit_insn (gen_sethm (op0, op0, op1));
1499 emit_insn (gen_rtx_SET (VOIDmode, op0,
1500 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1501 emit_insn (gen_rtx_SET (VOIDmode, op0,
1502 gen_rtx_PLUS (DImode, op0, temp1)));
1503 emit_insn (gen_setlo (op0, op0, op1));
1507 /* Old old old backwards compatibility kruft here.
1508 Essentially it is MEDLOW with a fixed 64-bit
1509 virtual base added to all data segment addresses.
1510 Text-segment stuff is computed like MEDANY, we can't
1511 reuse the code above because the relocation knobs
1514 Data segment: sethi %hi(symbol), %temp1
1515 or %temp1, %lo(symbol), %temp2
1516 add %temp2, EMBMEDANY_BASE_REG, %reg
1518 Text segment: sethi %uhi(symbol), %temp1
1519 sethi %hi(symbol), %temp2
1520 or %temp1, %ulo(symbol), %temp3
1521 or %temp2, %lo(symbol), %temp4
1522 sllx %temp3, 32, %temp5
1523 or %temp4, %temp5, %reg */
1524 if (data_segment_operand (op1, GET_MODE (op1)))
1526 emit_insn (gen_embmedany_sethi (temp1, op1));
1527 emit_insn (gen_embmedany_brsum (op0, temp1));
1528 emit_insn (gen_embmedany_losum (op0, op0, op1));
1532 /* It is possible that one of the registers we got for operands[2]
1533 might coincide with that of operands[0] (which is why we made
1534 it TImode). Pick the other one to use as our scratch. */
1535 if (rtx_equal_p (temp1, op0))
1538 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1543 emit_insn (gen_embmedany_textuhi (op0, op1));
1544 emit_insn (gen_embmedany_texthi (temp1, op1));
1545 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1546 emit_insn (gen_rtx_SET (VOIDmode, op0,
1547 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1548 emit_insn (gen_rtx_SET (VOIDmode, op0,
1549 gen_rtx_PLUS (DImode, op0, temp1)));
1550 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1559 /* These avoid problems when cross compiling. If we do not
1560 go through all this hair then the optimizer will see
1561 invalid REG_EQUAL notes or in some cases none at all. */
1562 static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
1563 static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
1564 static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
1565 static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
1567 #if HOST_BITS_PER_WIDE_INT == 64
1568 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1569 #define GEN_INT64(__x) GEN_INT (__x)
1571 #define GEN_HIGHINT64(__x) \
1572 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1573 #define GEN_INT64(__x) \
1574 immed_double_const ((__x) & 0xffffffff, \
1575 ((__x) & 0x80000000 ? -1 : 0), DImode)
1578 /* The optimizer is not to assume anything about exactly
1579 which bits are set for a HIGH, they are unspecified.
1580 Unfortunately this leads to many missed optimizations
1581 during CSE. We mask out the non-HIGH bits, and matches
1582 a plain movdi, to alleviate this problem. */
1584 sparc_emit_set_safe_HIGH64 (dest, val)
1588 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1592 gen_safe_SET64 (dest, val)
1596 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1600 gen_safe_OR64 (src, val)
1604 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1608 gen_safe_XOR64 (src, val)
1612 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1615 /* Worker routines for 64-bit constant formation on arch64.
1616 One of the key things to be doing in these emissions is
1617 to create as many temp REGs as possible. This makes it
1618 possible for half-built constants to be used later when
1619 such values are similar to something required later on.
1620 Without doing this, the optimizer cannot see such
1623 static void sparc_emit_set_const64_quick1
1624 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
1627 sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1630 unsigned HOST_WIDE_INT low_bits;
1633 unsigned HOST_WIDE_INT high_bits;
1636 high_bits = (~low_bits) & 0xffffffff;
1638 high_bits = low_bits;
1640 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1643 emit_insn (gen_rtx_SET (VOIDmode, op0,
1644 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1648 /* If we are XOR'ing with -1, then we should emit a one's complement
1649 instead. This way the combiner will notice logical operations
1650 such as ANDN later on and substitute. */
1651 if ((low_bits & 0x3ff) == 0x3ff)
1653 emit_insn (gen_rtx_SET (VOIDmode, op0,
1654 gen_rtx_NOT (DImode, temp)));
1658 emit_insn (gen_rtx_SET (VOIDmode, op0,
1659 gen_safe_XOR64 (temp,
1660 (-(HOST_WIDE_INT)0x400
1661 | (low_bits & 0x3ff)))));
1666 static void sparc_emit_set_const64_quick2
1667 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
1668 unsigned HOST_WIDE_INT, int));
1671 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1674 unsigned HOST_WIDE_INT high_bits;
1675 unsigned HOST_WIDE_INT low_immediate;
1680 if ((high_bits & 0xfffffc00) != 0)
1682 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1683 if ((high_bits & ~0xfffffc00) != 0)
1684 emit_insn (gen_rtx_SET (VOIDmode, op0,
1685 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1691 emit_insn (gen_safe_SET64 (temp, high_bits));
1695 /* Now shift it up into place. */
1696 emit_insn (gen_rtx_SET (VOIDmode, op0,
1697 gen_rtx_ASHIFT (DImode, temp2,
1698 GEN_INT (shift_count))));
1700 /* If there is a low immediate part piece, finish up by
1701 putting that in as well. */
1702 if (low_immediate != 0)
1703 emit_insn (gen_rtx_SET (VOIDmode, op0,
1704 gen_safe_OR64 (op0, low_immediate)));
1707 static void sparc_emit_set_const64_longway
1708 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1710 /* Full 64-bit constant decomposition. Even though this is the
1711 'worst' case, we still optimize a few things away. */
1713 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1716 unsigned HOST_WIDE_INT high_bits;
1717 unsigned HOST_WIDE_INT low_bits;
1721 if (reload_in_progress || reload_completed)
1724 sub_temp = gen_reg_rtx (DImode);
1726 if ((high_bits & 0xfffffc00) != 0)
1728 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1729 if ((high_bits & ~0xfffffc00) != 0)
1730 emit_insn (gen_rtx_SET (VOIDmode,
1732 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1738 emit_insn (gen_safe_SET64 (temp, high_bits));
1742 if (!reload_in_progress && !reload_completed)
1744 rtx temp2 = gen_reg_rtx (DImode);
1745 rtx temp3 = gen_reg_rtx (DImode);
1746 rtx temp4 = gen_reg_rtx (DImode);
1748 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1749 gen_rtx_ASHIFT (DImode, sub_temp,
1752 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1753 if ((low_bits & ~0xfffffc00) != 0)
1755 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1756 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1757 emit_insn (gen_rtx_SET (VOIDmode, op0,
1758 gen_rtx_PLUS (DImode, temp4, temp3)));
1762 emit_insn (gen_rtx_SET (VOIDmode, op0,
1763 gen_rtx_PLUS (DImode, temp4, temp2)));
1768 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1769 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1770 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1773 /* We are in the middle of reload, so this is really
1774 painful. However we do still make an attempt to
1775 avoid emitting truly stupid code. */
1776 if (low1 != const0_rtx)
1778 emit_insn (gen_rtx_SET (VOIDmode, op0,
1779 gen_rtx_ASHIFT (DImode, sub_temp,
1780 GEN_INT (to_shift))));
1781 emit_insn (gen_rtx_SET (VOIDmode, op0,
1782 gen_rtx_IOR (DImode, op0, low1)));
1790 if (low2 != const0_rtx)
1792 emit_insn (gen_rtx_SET (VOIDmode, op0,
1793 gen_rtx_ASHIFT (DImode, sub_temp,
1794 GEN_INT (to_shift))));
1795 emit_insn (gen_rtx_SET (VOIDmode, op0,
1796 gen_rtx_IOR (DImode, op0, low2)));
1804 emit_insn (gen_rtx_SET (VOIDmode, op0,
1805 gen_rtx_ASHIFT (DImode, sub_temp,
1806 GEN_INT (to_shift))));
1807 if (low3 != const0_rtx)
1808 emit_insn (gen_rtx_SET (VOIDmode, op0,
1809 gen_rtx_IOR (DImode, op0, low3)));
1814 /* Analyze a 64-bit constant for certain properties. */
1815 static void analyze_64bit_constant
1816 PARAMS ((unsigned HOST_WIDE_INT,
1817 unsigned HOST_WIDE_INT,
1818 int *, int *, int *));
1821 analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
1822 unsigned HOST_WIDE_INT high_bits, low_bits;
1823 int *hbsp, *lbsp, *abbasp;
1825 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1828 lowest_bit_set = highest_bit_set = -1;
1832 if ((lowest_bit_set == -1)
1833 && ((low_bits >> i) & 1))
1835 if ((highest_bit_set == -1)
1836 && ((high_bits >> (32 - i - 1)) & 1))
1837 highest_bit_set = (64 - i - 1);
1840 && ((highest_bit_set == -1)
1841 || (lowest_bit_set == -1)));
1847 if ((lowest_bit_set == -1)
1848 && ((high_bits >> i) & 1))
1849 lowest_bit_set = i + 32;
1850 if ((highest_bit_set == -1)
1851 && ((low_bits >> (32 - i - 1)) & 1))
1852 highest_bit_set = 32 - i - 1;
1855 && ((highest_bit_set == -1)
1856 || (lowest_bit_set == -1)));
1858 /* If there are no bits set this should have gone out
1859 as one instruction! */
1860 if (lowest_bit_set == -1
1861 || highest_bit_set == -1)
1863 all_bits_between_are_set = 1;
1864 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1868 if ((low_bits & (1 << i)) != 0)
1873 if ((high_bits & (1 << (i - 32))) != 0)
1876 all_bits_between_are_set = 0;
1879 *hbsp = highest_bit_set;
1880 *lbsp = lowest_bit_set;
1881 *abbasp = all_bits_between_are_set;
1884 static int const64_is_2insns
1885 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1888 const64_is_2insns (high_bits, low_bits)
1889 unsigned HOST_WIDE_INT high_bits, low_bits;
1891 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1894 || high_bits == 0xffffffff)
1897 analyze_64bit_constant (high_bits, low_bits,
1898 &highest_bit_set, &lowest_bit_set,
1899 &all_bits_between_are_set);
1901 if ((highest_bit_set == 63
1902 || lowest_bit_set == 0)
1903 && all_bits_between_are_set != 0)
1906 if ((highest_bit_set - lowest_bit_set) < 21)
1912 static unsigned HOST_WIDE_INT create_simple_focus_bits
1913 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
1916 static unsigned HOST_WIDE_INT
1917 create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
1918 unsigned HOST_WIDE_INT high_bits, low_bits;
1919 int lowest_bit_set, shift;
1921 HOST_WIDE_INT hi, lo;
1923 if (lowest_bit_set < 32)
1925 lo = (low_bits >> lowest_bit_set) << shift;
1926 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1931 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1938 /* Here we are sure to be arch64 and this is an integer constant
1939 being loaded into a register. Emit the most efficient
1940 insn sequence possible. Detection of all the 1-insn cases
1941 has been done already. */
1943 sparc_emit_set_const64 (op0, op1)
1947 unsigned HOST_WIDE_INT high_bits, low_bits;
1948 int lowest_bit_set, highest_bit_set;
1949 int all_bits_between_are_set;
1952 /* Sanity check that we know what we are working with. */
1953 if (! TARGET_ARCH64)
1956 if (GET_CODE (op0) != SUBREG)
1958 if (GET_CODE (op0) != REG
1959 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1960 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1964 if (reload_in_progress || reload_completed)
1967 temp = gen_reg_rtx (DImode);
1969 if (GET_CODE (op1) != CONST_DOUBLE
1970 && GET_CODE (op1) != CONST_INT)
1972 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1976 if (GET_CODE (op1) == CONST_DOUBLE)
1978 #if HOST_BITS_PER_WIDE_INT == 64
1979 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1980 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1982 high_bits = CONST_DOUBLE_HIGH (op1);
1983 low_bits = CONST_DOUBLE_LOW (op1);
1988 #if HOST_BITS_PER_WIDE_INT == 64
1989 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1990 low_bits = (INTVAL (op1) & 0xffffffff);
1992 high_bits = ((INTVAL (op1) < 0) ?
1995 low_bits = INTVAL (op1);
1999 /* low_bits bits 0 --> 31
2000 high_bits bits 32 --> 63 */
2002 analyze_64bit_constant (high_bits, low_bits,
2003 &highest_bit_set, &lowest_bit_set,
2004 &all_bits_between_are_set);
2006 /* First try for a 2-insn sequence. */
2008 /* These situations are preferred because the optimizer can
2009 * do more things with them:
2011 * sllx %reg, shift, %reg
2013 * srlx %reg, shift, %reg
2014 * 3) mov some_small_const, %reg
2015 * sllx %reg, shift, %reg
2017 if (((highest_bit_set == 63
2018 || lowest_bit_set == 0)
2019 && all_bits_between_are_set != 0)
2020 || ((highest_bit_set - lowest_bit_set) < 12))
2022 HOST_WIDE_INT the_const = -1;
2023 int shift = lowest_bit_set;
2025 if ((highest_bit_set != 63
2026 && lowest_bit_set != 0)
2027 || all_bits_between_are_set == 0)
2030 create_simple_focus_bits (high_bits, low_bits,
2033 else if (lowest_bit_set == 0)
2034 shift = -(63 - highest_bit_set);
2036 if (! SPARC_SIMM13_P (the_const))
2039 emit_insn (gen_safe_SET64 (temp, the_const));
2041 emit_insn (gen_rtx_SET (VOIDmode,
2043 gen_rtx_ASHIFT (DImode,
2047 emit_insn (gen_rtx_SET (VOIDmode,
2049 gen_rtx_LSHIFTRT (DImode,
2051 GEN_INT (-shift))));
2057 /* Now a range of 22 or less bits set somewhere.
2058 * 1) sethi %hi(focus_bits), %reg
2059 * sllx %reg, shift, %reg
2060 * 2) sethi %hi(focus_bits), %reg
2061 * srlx %reg, shift, %reg
2063 if ((highest_bit_set - lowest_bit_set) < 21)
2065 unsigned HOST_WIDE_INT focus_bits =
2066 create_simple_focus_bits (high_bits, low_bits,
2067 lowest_bit_set, 10);
2069 if (! SPARC_SETHI_P (focus_bits))
2072 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2074 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2075 if (lowest_bit_set < 10)
2076 emit_insn (gen_rtx_SET (VOIDmode,
2078 gen_rtx_LSHIFTRT (DImode, temp,
2079 GEN_INT (10 - lowest_bit_set))));
2080 else if (lowest_bit_set > 10)
2081 emit_insn (gen_rtx_SET (VOIDmode,
2083 gen_rtx_ASHIFT (DImode, temp,
2084 GEN_INT (lowest_bit_set - 10))));
2090 /* 1) sethi %hi(low_bits), %reg
2091 * or %reg, %lo(low_bits), %reg
2092 * 2) sethi %hi(~low_bits), %reg
2093 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2096 || high_bits == 0xffffffff)
2098 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2099 (high_bits == 0xffffffff));
2103 /* Now, try 3-insn sequences. */
2105 /* 1) sethi %hi(high_bits), %reg
2106 * or %reg, %lo(high_bits), %reg
2107 * sllx %reg, 32, %reg
2111 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2115 /* We may be able to do something quick
2116 when the constant is negated, so try that. */
2117 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2118 (~low_bits) & 0xfffffc00))
2120 /* NOTE: The trailing bits get XOR'd so we need the
2121 non-negated bits, not the negated ones. */
2122 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2124 if ((((~high_bits) & 0xffffffff) == 0
2125 && ((~low_bits) & 0x80000000) == 0)
2126 || (((~high_bits) & 0xffffffff) == 0xffffffff
2127 && ((~low_bits) & 0x80000000) != 0))
2129 int fast_int = (~low_bits & 0xffffffff);
2131 if ((SPARC_SETHI_P (fast_int)
2132 && (~high_bits & 0xffffffff) == 0)
2133 || SPARC_SIMM13_P (fast_int))
2134 emit_insn (gen_safe_SET64 (temp, fast_int));
2136 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2141 #if HOST_BITS_PER_WIDE_INT == 64
2142 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2143 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2145 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2146 (~high_bits) & 0xffffffff,
2149 sparc_emit_set_const64 (temp, negated_const);
2152 /* If we are XOR'ing with -1, then we should emit a one's complement
2153 instead. This way the combiner will notice logical operations
2154 such as ANDN later on and substitute. */
2155 if (trailing_bits == 0x3ff)
2157 emit_insn (gen_rtx_SET (VOIDmode, op0,
2158 gen_rtx_NOT (DImode, temp)));
2162 emit_insn (gen_rtx_SET (VOIDmode,
2164 gen_safe_XOR64 (temp,
2165 (-0x400 | trailing_bits))));
2170 /* 1) sethi %hi(xxx), %reg
2171 * or %reg, %lo(xxx), %reg
2172 * sllx %reg, yyy, %reg
2174 * ??? This is just a generalized version of the low_bits==0
2175 * thing above, FIXME...
2177 if ((highest_bit_set - lowest_bit_set) < 32)
2179 unsigned HOST_WIDE_INT focus_bits =
2180 create_simple_focus_bits (high_bits, low_bits,
2183 /* We can't get here in this state. */
2184 if (highest_bit_set < 32
2185 || lowest_bit_set >= 32)
2188 /* So what we know is that the set bits straddle the
2189 middle of the 64-bit word. */
2190 sparc_emit_set_const64_quick2 (op0, temp,
2196 /* 1) sethi %hi(high_bits), %reg
2197 * or %reg, %lo(high_bits), %reg
2198 * sllx %reg, 32, %reg
2199 * or %reg, low_bits, %reg
2201 if (SPARC_SIMM13_P(low_bits)
2202 && ((int)low_bits > 0))
2204 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2208 /* The easiest way when all else fails, is full decomposition. */
2210 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2211 high_bits, low_bits, ~high_bits, ~low_bits);
2213 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2216 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2217 return the mode to be used for the comparison. For floating-point,
2218 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2219 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2220 processing is needed. */
2223 select_cc_mode (op, x, y)
2226 rtx y ATTRIBUTE_UNUSED;
2228 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2254 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2255 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2257 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2258 return CCX_NOOVmode;
2264 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2271 /* X and Y are two things to compare using CODE. Emit the compare insn and
2272 return the rtx for the cc reg in the proper mode. */
2275 gen_compare_reg (code, x, y)
2279 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2282 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2283 fcc regs (cse can't tell they're really call clobbered regs and will
2284 remove a duplicate comparison even if there is an intervening function
2285 call - it will then try to reload the cc reg via an int reg which is why
2286 we need the movcc patterns). It is possible to provide the movcc
2287 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2288 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2289 to tell cse that CCFPE mode registers (even pseudos) are call
2292 /* ??? This is an experiment. Rather than making changes to cse which may
2293 or may not be easy/clean, we do our own cse. This is possible because
2294 we will generate hard registers. Cse knows they're call clobbered (it
2295 doesn't know the same thing about pseudos). If we guess wrong, no big
2296 deal, but if we win, great! */
2298 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2299 #if 1 /* experiment */
2302 /* We cycle through the registers to ensure they're all exercised. */
2303 static int next_fcc_reg = 0;
2304 /* Previous x,y for each fcc reg. */
2305 static rtx prev_args[4][2];
2307 /* Scan prev_args for x,y. */
2308 for (reg = 0; reg < 4; reg++)
2309 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2314 prev_args[reg][0] = x;
2315 prev_args[reg][1] = y;
2316 next_fcc_reg = (next_fcc_reg + 1) & 3;
2318 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2321 cc_reg = gen_reg_rtx (mode);
2322 #endif /* ! experiment */
2323 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2324 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2326 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2328 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2329 gen_rtx_COMPARE (mode, x, y)));
2334 /* This function is used for v9 only.
2335 CODE is the code for an Scc's comparison.
2336 OPERANDS[0] is the target of the Scc insn.
2337 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2338 been generated yet).
2340 This function is needed to turn
2343 (gt (reg:CCX 100 %icc)
2347 (gt:DI (reg:CCX 100 %icc)
2350 IE: The instruction recognizer needs to see the mode of the comparison to
2351 find the right instruction. We could use "gt:DI" right in the
2352 define_expand, but leaving it out allows us to handle DI, SI, etc.
2354 We refer to the global sparc compare operands sparc_compare_op0 and
2355 sparc_compare_op1. */
2358 gen_v9_scc (compare_code, operands)
2359 enum rtx_code compare_code;
2360 register rtx *operands;
2365 && (GET_MODE (sparc_compare_op0) == DImode
2366 || GET_MODE (operands[0]) == DImode))
2369 op0 = sparc_compare_op0;
2370 op1 = sparc_compare_op1;
2372 /* Try to use the movrCC insns. */
2374 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2375 && op1 == const0_rtx
2376 && v9_regcmp_p (compare_code))
2378 /* Special case for op0 != 0. This can be done with one instruction if
2379 operands[0] == sparc_compare_op0. */
2381 if (compare_code == NE
2382 && GET_MODE (operands[0]) == DImode
2383 && rtx_equal_p (op0, operands[0]))
2385 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2386 gen_rtx_IF_THEN_ELSE (DImode,
2387 gen_rtx_fmt_ee (compare_code, DImode,
2394 if (reg_overlap_mentioned_p (operands[0], op0))
2396 /* Handle the case where operands[0] == sparc_compare_op0.
2397 We "early clobber" the result. */
2398 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2399 emit_move_insn (op0, sparc_compare_op0);
2402 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2403 if (GET_MODE (op0) != DImode)
2405 temp = gen_reg_rtx (DImode);
2406 convert_move (temp, op0, 0);
2410 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2411 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2412 gen_rtx_fmt_ee (compare_code, DImode,
2420 operands[1] = gen_compare_reg (compare_code, op0, op1);
2422 switch (GET_MODE (operands[1]))
2432 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2433 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2434 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2435 gen_rtx_fmt_ee (compare_code,
2436 GET_MODE (operands[1]),
2437 operands[1], const0_rtx),
2438 const1_rtx, operands[0])));
2443 /* Emit a conditional jump insn for the v9 architecture using comparison code
2444 CODE and jump target LABEL.
2445 This function exists to take advantage of the v9 brxx insns. */
2448 emit_v9_brxx_insn (code, op0, label)
2452 emit_jump_insn (gen_rtx_SET (VOIDmode,
2454 gen_rtx_IF_THEN_ELSE (VOIDmode,
2455 gen_rtx_fmt_ee (code, GET_MODE (op0),
2457 gen_rtx_LABEL_REF (VOIDmode, label),
2461 /* Generate a DFmode part of a hard TFmode register.
2462 REG is the TFmode hard register, LOW is 1 for the
2463 low 64bit of the register and 0 otherwise.
2466 gen_df_reg (reg, low)
2470 int regno = REGNO (reg);
2472 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2473 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2474 return gen_rtx_REG (DFmode, regno);
2477 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2478 Unlike normal calls, TFmode operands are passed by reference. It is
2479 assumed that no more than 3 operands are required. */
2482 emit_soft_tfmode_libcall (func_name, nargs, operands)
2483 const char *func_name;
2487 rtx ret_slot = NULL, arg[3], func_sym;
2490 /* We only expect to be called for conversions, unary, and binary ops. */
2491 if (nargs < 2 || nargs > 3)
2494 for (i = 0; i < nargs; ++i)
2496 rtx this_arg = operands[i];
2499 /* TFmode arguments and return values are passed by reference. */
2500 if (GET_MODE (this_arg) == TFmode)
2502 int force_stack_temp;
2504 force_stack_temp = 0;
2505 if (TARGET_BUGGY_QP_LIB && i == 0)
2506 force_stack_temp = 1;
2508 if (GET_CODE (this_arg) == MEM
2509 && ! force_stack_temp)
2510 this_arg = XEXP (this_arg, 0);
2511 else if (CONSTANT_P (this_arg)
2512 && ! force_stack_temp)
2514 this_slot = force_const_mem (TFmode, this_arg);
2515 this_arg = XEXP (this_slot, 0);
2519 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2521 /* Operand 0 is the return value. We'll copy it out later. */
2523 emit_move_insn (this_slot, this_arg);
2525 ret_slot = this_slot;
2527 this_arg = XEXP (this_slot, 0);
2534 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2536 if (GET_MODE (operands[0]) == TFmode)
2539 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2540 arg[0], GET_MODE (arg[0]),
2541 arg[1], GET_MODE (arg[1]));
2543 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2544 arg[0], GET_MODE (arg[0]),
2545 arg[1], GET_MODE (arg[1]),
2546 arg[2], GET_MODE (arg[2]));
2549 emit_move_insn (operands[0], ret_slot);
2558 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2559 GET_MODE (operands[0]), 1,
2560 arg[1], GET_MODE (arg[1]));
2562 if (ret != operands[0])
2563 emit_move_insn (operands[0], ret);
2567 /* Expand soft-float TFmode calls to sparc abi routines. */
2570 emit_soft_tfmode_binop (code, operands)
2594 emit_soft_tfmode_libcall (func, 3, operands);
2598 emit_soft_tfmode_unop (code, operands)
2613 emit_soft_tfmode_libcall (func, 2, operands);
2617 emit_soft_tfmode_cvt (code, operands)
2626 switch (GET_MODE (operands[1]))
2639 case FLOAT_TRUNCATE:
2640 switch (GET_MODE (operands[0]))
2654 switch (GET_MODE (operands[1]))
2667 case UNSIGNED_FLOAT:
2668 switch (GET_MODE (operands[1]))
2682 switch (GET_MODE (operands[0]))
2696 switch (GET_MODE (operands[0]))
2713 emit_soft_tfmode_libcall (func, 2, operands);
2716 /* Expand a hard-float tfmode operation. All arguments must be in
2720 emit_hard_tfmode_operation (code, operands)
2726 if (GET_RTX_CLASS (code) == '1')
2728 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2729 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2733 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2734 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2735 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2736 operands[1], operands[2]);
2739 if (register_operand (operands[0], VOIDmode))
2742 dest = gen_reg_rtx (GET_MODE (operands[0]));
2744 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2746 if (dest != operands[0])
2747 emit_move_insn (operands[0], dest);
2751 emit_tfmode_binop (code, operands)
2755 if (TARGET_HARD_QUAD)
2756 emit_hard_tfmode_operation (code, operands);
2758 emit_soft_tfmode_binop (code, operands);
2762 emit_tfmode_unop (code, operands)
2766 if (TARGET_HARD_QUAD)
2767 emit_hard_tfmode_operation (code, operands);
2769 emit_soft_tfmode_unop (code, operands);
2773 emit_tfmode_cvt (code, operands)
2777 if (TARGET_HARD_QUAD)
2778 emit_hard_tfmode_operation (code, operands);
2780 emit_soft_tfmode_cvt (code, operands);
2783 /* Return nonzero if a return peephole merging return with
2784 setting of output register is ok. */
2786 leaf_return_peephole_ok ()
2788 return (actual_fsize == 0);
2791 /* Return nonzero if a branch/jump/call instruction will be emitting
2792 nop into its delay slot. */
2795 empty_delay_slot (insn)
2800 /* If no previous instruction (should not happen), return true. */
2801 if (PREV_INSN (insn) == NULL)
2804 seq = NEXT_INSN (PREV_INSN (insn));
2805 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2811 /* Return nonzero if TRIAL can go into the function epilogue's
2812 delay slot. SLOT is the slot we are trying to fill. */
2815 eligible_for_epilogue_delay (trial, slot)
2824 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2827 if (get_attr_length (trial) != 1)
2830 /* If there are any call-saved registers, we should scan TRIAL if it
2831 does not reference them. For now just make it easy. */
2835 /* If the function uses __builtin_eh_return, the eh_return machinery
2836 occupies the delay slot. */
2837 if (current_function_calls_eh_return)
2840 /* In the case of a true leaf function, anything can go into the delay slot.
2841 A delay slot only exists however if the frame size is zero, otherwise
2842 we will put an insn to adjust the stack after the return. */
2843 if (current_function_uses_only_leaf_regs)
2845 if (leaf_return_peephole_ok ())
2846 return ((get_attr_in_uncond_branch_delay (trial)
2847 == IN_BRANCH_DELAY_TRUE));
2851 pat = PATTERN (trial);
2853 /* Otherwise, only operations which can be done in tandem with
2854 a `restore' or `return' insn can go into the delay slot. */
2855 if (GET_CODE (SET_DEST (pat)) != REG
2856 || REGNO (SET_DEST (pat)) < 24)
2859 /* If this instruction sets up floating point register and we have a return
2860 instruction, it can probably go in. But restore will not work
2862 if (REGNO (SET_DEST (pat)) >= 32)
2864 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2865 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2870 /* The set of insns matched here must agree precisely with the set of
2871 patterns paired with a RETURN in sparc.md. */
2873 src = SET_SRC (pat);
2875 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2876 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2877 && arith_operand (src, GET_MODE (src)))
2880 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2882 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2885 /* This matches "*return_di". */
2886 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2887 && arith_double_operand (src, GET_MODE (src)))
2888 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2890 /* This matches "*return_sf_no_fpu". */
2891 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2892 && register_operand (src, SFmode))
2895 /* If we have return instruction, anything that does not use
2896 local or output registers and can go into a delay slot wins. */
2897 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2898 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2901 /* This matches "*return_addsi". */
2902 else if (GET_CODE (src) == PLUS
2903 && arith_operand (XEXP (src, 0), SImode)
2904 && arith_operand (XEXP (src, 1), SImode)
2905 && (register_operand (XEXP (src, 0), SImode)
2906 || register_operand (XEXP (src, 1), SImode)))
2909 /* This matches "*return_adddi". */
2910 else if (GET_CODE (src) == PLUS
2911 && arith_double_operand (XEXP (src, 0), DImode)
2912 && arith_double_operand (XEXP (src, 1), DImode)
2913 && (register_operand (XEXP (src, 0), DImode)
2914 || register_operand (XEXP (src, 1), DImode)))
2917 /* This can match "*return_losum_[sd]i".
2918 Catch only some cases, so that return_losum* don't have
2920 else if (GET_CODE (src) == LO_SUM
2921 && ! TARGET_CM_MEDMID
2922 && ((register_operand (XEXP (src, 0), SImode)
2923 && immediate_operand (XEXP (src, 1), SImode))
2925 && register_operand (XEXP (src, 0), DImode)
2926 && immediate_operand (XEXP (src, 1), DImode))))
2929 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2930 else if (GET_CODE (src) == ASHIFT
2931 && (register_operand (XEXP (src, 0), SImode)
2932 || register_operand (XEXP (src, 0), DImode))
2933 && XEXP (src, 1) == const1_rtx)
2939 /* Return nonzero if TRIAL can go into the sibling call
2943 eligible_for_sibcall_delay (trial)
2948 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2951 if (get_attr_length (trial) != 1)
2954 pat = PATTERN (trial);
2956 if (current_function_uses_only_leaf_regs)
2958 /* If the tail call is done using the call instruction,
2959 we have to restore %o7 in the delay slot. */
2960 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2963 /* %g1 is used to build the function address */
2964 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2970 /* Otherwise, only operations which can be done in tandem with
2971 a `restore' insn can go into the delay slot. */
2972 if (GET_CODE (SET_DEST (pat)) != REG
2973 || REGNO (SET_DEST (pat)) < 24
2974 || REGNO (SET_DEST (pat)) >= 32)
2977 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2979 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2982 src = SET_SRC (pat);
2984 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2985 && arith_operand (src, GET_MODE (src)))
2988 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2990 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2993 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2994 && arith_double_operand (src, GET_MODE (src)))
2995 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2997 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2998 && register_operand (src, SFmode))
3001 else if (GET_CODE (src) == PLUS
3002 && arith_operand (XEXP (src, 0), SImode)
3003 && arith_operand (XEXP (src, 1), SImode)
3004 && (register_operand (XEXP (src, 0), SImode)
3005 || register_operand (XEXP (src, 1), SImode)))
3008 else if (GET_CODE (src) == PLUS
3009 && arith_double_operand (XEXP (src, 0), DImode)
3010 && arith_double_operand (XEXP (src, 1), DImode)
3011 && (register_operand (XEXP (src, 0), DImode)
3012 || register_operand (XEXP (src, 1), DImode)))
3015 else if (GET_CODE (src) == LO_SUM
3016 && ! TARGET_CM_MEDMID
3017 && ((register_operand (XEXP (src, 0), SImode)
3018 && immediate_operand (XEXP (src, 1), SImode))
3020 && register_operand (XEXP (src, 0), DImode)
3021 && immediate_operand (XEXP (src, 1), DImode))))
3024 else if (GET_CODE (src) == ASHIFT
3025 && (register_operand (XEXP (src, 0), SImode)
3026 || register_operand (XEXP (src, 0), DImode))
3027 && XEXP (src, 1) == const1_rtx)
3034 check_return_regs (x)
3037 switch (GET_CODE (x))
3040 return IN_OR_GLOBAL_P (x);
3055 if (check_return_regs (XEXP (x, 1)) == 0)
3060 return check_return_regs (XEXP (x, 0));
3069 short_branch (uid1, uid2)
3072 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3074 /* Leave a few words of "slop". */
3075 if (delta >= -1023 && delta <= 1022)
3081 /* Return nonzero if REG is not used after INSN.
3082 We assume REG is a reload reg, and therefore does
3083 not live past labels or calls or jumps. */
3085 reg_unused_after (reg, insn)
3089 enum rtx_code code, prev_code = UNKNOWN;
3091 while ((insn = NEXT_INSN (insn)))
3093 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3096 code = GET_CODE (insn);
3097 if (GET_CODE (insn) == CODE_LABEL)
3100 if (GET_RTX_CLASS (code) == 'i')
3102 rtx set = single_set (insn);
3103 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3106 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3108 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3116 /* The table we use to reference PIC data. */
3117 static GTY(()) rtx global_offset_table;
3119 /* The function we use to get at it. */
3120 static GTY(()) rtx get_pc_symbol;
3121 static char get_pc_symbol_name[256];
3123 /* Ensure that we are not using patterns that are not OK with PIC. */
3132 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3133 || (GET_CODE (recog_data.operand[i]) == CONST
3134 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3135 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3136 == global_offset_table)
3137 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3146 /* Return true if X is an address which needs a temporary register when
3147 reloaded while generating PIC code. */
3150 pic_address_needs_scratch (x)
3153 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3154 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3155 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3156 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3157 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3163 /* Legitimize PIC addresses. If the address is already position-independent,
3164 we return ORIG. Newly generated position-independent addresses go into a
3165 reg. This is REG if nonzero, otherwise we allocate register(s) as
3169 legitimize_pic_address (orig, mode, reg)
3171 enum machine_mode mode ATTRIBUTE_UNUSED;
3174 if (GET_CODE (orig) == SYMBOL_REF)
3176 rtx pic_ref, address;
3181 if (reload_in_progress || reload_completed)
3184 reg = gen_reg_rtx (Pmode);
3189 /* If not during reload, allocate another temp reg here for loading
3190 in the address, so that these instructions can be optimized
3192 rtx temp_reg = ((reload_in_progress || reload_completed)
3193 ? reg : gen_reg_rtx (Pmode));
3195 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3196 won't get confused into thinking that these two instructions
3197 are loading in the true address of the symbol. If in the
3198 future a PIC rtx exists, that should be used instead. */
3199 if (Pmode == SImode)
3201 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3202 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3206 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3207 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3214 pic_ref = gen_rtx_MEM (Pmode,
3215 gen_rtx_PLUS (Pmode,
3216 pic_offset_table_rtx, address));
3217 current_function_uses_pic_offset_table = 1;
3218 RTX_UNCHANGING_P (pic_ref) = 1;
3219 insn = emit_move_insn (reg, pic_ref);
3220 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3222 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3226 else if (GET_CODE (orig) == CONST)
3230 if (GET_CODE (XEXP (orig, 0)) == PLUS
3231 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3236 if (reload_in_progress || reload_completed)
3239 reg = gen_reg_rtx (Pmode);
3242 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3244 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3245 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3246 base == reg ? 0 : reg);
3251 if (GET_CODE (offset) == CONST_INT)
3253 if (SMALL_INT (offset))
3254 return plus_constant (base, INTVAL (offset));
3255 else if (! reload_in_progress && ! reload_completed)
3256 offset = force_reg (Pmode, offset);
3258 /* If we reach here, then something is seriously wrong. */
3261 return gen_rtx_PLUS (Pmode, base, offset);
3263 else if (GET_CODE (orig) == LABEL_REF)
3264 /* ??? Why do we do this? */
3265 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3266 the register is live instead, in case it is eliminated. */
3267 current_function_uses_pic_offset_table = 1;
3272 /* Emit special PIC prologues. */
3275 load_pic_register ()
3277 /* Labels to get the PC in the prologue of this function. */
3278 int orig_flag_pic = flag_pic;
3283 /* If we haven't emitted the special get_pc helper function, do so now. */
3284 if (get_pc_symbol_name[0] == 0)
3288 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3291 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3293 ASM_OUTPUT_ALIGN (asm_out_file, align);
3294 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
3295 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3298 /* Initialize every time through, since we can't easily
3299 know this to be permanent. */
3300 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3301 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3304 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3307 flag_pic = orig_flag_pic;
3309 /* Need to emit this whether or not we obey regdecls,
3310 since setjmp/longjmp can cause life info to screw up.
3311 ??? In the case where we don't obey regdecls, this is not sufficient
3312 since we may not fall out the bottom. */
3313 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3316 /* Return 1 if RTX is a MEM which is known to be aligned to at
3317 least a DESIRED byte boundary. */
3320 mem_min_alignment (mem, desired)
3324 rtx addr, base, offset;
3326 /* If it's not a MEM we can't accept it. */
3327 if (GET_CODE (mem) != MEM)
3330 addr = XEXP (mem, 0);
3331 base = offset = NULL_RTX;
3332 if (GET_CODE (addr) == PLUS)
3334 if (GET_CODE (XEXP (addr, 0)) == REG)
3336 base = XEXP (addr, 0);
3338 /* What we are saying here is that if the base
3339 REG is aligned properly, the compiler will make
3340 sure any REG based index upon it will be so
3342 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3343 offset = XEXP (addr, 1);
3345 offset = const0_rtx;
3348 else if (GET_CODE (addr) == REG)
3351 offset = const0_rtx;
3354 if (base != NULL_RTX)
3356 int regno = REGNO (base);
3358 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3360 /* Check if the compiler has recorded some information
3361 about the alignment of the base REG. If reload has
3362 completed, we already matched with proper alignments.
3363 If not running global_alloc, reload might give us
3364 unaligned pointer to local stack though. */
3366 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3367 || (optimize && reload_completed))
3368 && (INTVAL (offset) & (desired - 1)) == 0)
3373 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3377 else if (! TARGET_UNALIGNED_DOUBLES
3378 || CONSTANT_P (addr)
3379 || GET_CODE (addr) == LO_SUM)
3381 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3382 is true, in which case we can only assume that an access is aligned if
3383 it is to a constant address, or the address involves a LO_SUM. */
3387 /* An obviously unaligned address. */
3392 /* Vectors to keep interesting information about registers where it can easily
3393 be got. We use to use the actual mode value as the bit number, but there
3394 are more than 32 modes now. Instead we use two tables: one indexed by
3395 hard register number, and one indexed by mode. */
3397 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3398 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3399 mapped into one sparc_mode_class mode. */
3401 enum sparc_mode_class {
3402 S_MODE, D_MODE, T_MODE, O_MODE,
3403 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3407 /* Modes for single-word and smaller quantities. */
3408 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3410 /* Modes for double-word and smaller quantities. */
3411 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3413 /* Modes for quad-word and smaller quantities. */
3414 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3416 /* Modes for 8-word and smaller quantities. */
3417 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3419 /* Modes for single-float quantities. We must allow any single word or
3420 smaller quantity. This is because the fix/float conversion instructions
3421 take integer inputs/outputs from the float registers. */
3422 #define SF_MODES (S_MODES)
3424 /* Modes for double-float and smaller quantities. */
3425 #define DF_MODES (S_MODES | D_MODES)
3427 /* Modes for double-float only quantities. */
3428 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3430 /* Modes for quad-float only quantities. */
3431 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3433 /* Modes for quad-float and smaller quantities. */
3434 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3436 /* Modes for quad-float and double-float quantities. */
3437 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3439 /* Modes for quad-float pair only quantities. */
3440 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3442 /* Modes for quad-float pairs and smaller quantities. */
3443 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3445 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3447 /* Modes for condition codes. */
3448 #define CC_MODES (1 << (int) CC_MODE)
3449 #define CCFP_MODES (1 << (int) CCFP_MODE)
3451 /* Value is 1 if register/mode pair is acceptable on sparc.
3452 The funny mixture of D and T modes is because integer operations
3453 do not specially operate on tetra quantities, so non-quad-aligned
3454 registers can hold quadword quantities (except %o4 and %i4 because
3455 they cross fixed registers). */
3457 /* This points to either the 32 bit or the 64 bit version. */
3458 const int *hard_regno_mode_classes;
3460 static const int hard_32bit_mode_classes[] = {
3461 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3462 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3463 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3464 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3466 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3467 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3468 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3469 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3471 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3472 and none can hold SFmode/SImode values. */
3473 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3474 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3475 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3476 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3479 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3485 static const int hard_64bit_mode_classes[] = {
3486 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3487 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3488 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3489 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3491 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3492 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3493 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3494 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3496 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3497 and none can hold SFmode/SImode values. */
3498 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3499 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3500 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3501 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3504 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3510 int sparc_mode_class [NUM_MACHINE_MODES];
3512 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3519 for (i = 0; i < NUM_MACHINE_MODES; i++)
3521 switch (GET_MODE_CLASS (i))
3524 case MODE_PARTIAL_INT:
3525 case MODE_COMPLEX_INT:
3526 if (GET_MODE_SIZE (i) <= 4)
3527 sparc_mode_class[i] = 1 << (int) S_MODE;
3528 else if (GET_MODE_SIZE (i) == 8)
3529 sparc_mode_class[i] = 1 << (int) D_MODE;
3530 else if (GET_MODE_SIZE (i) == 16)
3531 sparc_mode_class[i] = 1 << (int) T_MODE;
3532 else if (GET_MODE_SIZE (i) == 32)
3533 sparc_mode_class[i] = 1 << (int) O_MODE;
3535 sparc_mode_class[i] = 0;
3538 case MODE_COMPLEX_FLOAT:
3539 if (GET_MODE_SIZE (i) <= 4)
3540 sparc_mode_class[i] = 1 << (int) SF_MODE;
3541 else if (GET_MODE_SIZE (i) == 8)
3542 sparc_mode_class[i] = 1 << (int) DF_MODE;
3543 else if (GET_MODE_SIZE (i) == 16)
3544 sparc_mode_class[i] = 1 << (int) TF_MODE;
3545 else if (GET_MODE_SIZE (i) == 32)
3546 sparc_mode_class[i] = 1 << (int) OF_MODE;
3548 sparc_mode_class[i] = 0;
3552 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3553 we must explicitly check for them here. */
3554 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3555 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3556 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3557 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3558 sparc_mode_class[i] = 1 << (int) CC_MODE;
3560 sparc_mode_class[i] = 0;
3566 hard_regno_mode_classes = hard_64bit_mode_classes;
3568 hard_regno_mode_classes = hard_32bit_mode_classes;
3570 /* Initialize the array used by REGNO_REG_CLASS. */
3571 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3573 if (i < 16 && TARGET_V8PLUS)
3574 sparc_regno_reg_class[i] = I64_REGS;
3575 else if (i < 32 || i == FRAME_POINTER_REGNUM)
3576 sparc_regno_reg_class[i] = GENERAL_REGS;
3578 sparc_regno_reg_class[i] = FP_REGS;
3580 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3582 sparc_regno_reg_class[i] = FPCC_REGS;
3584 sparc_regno_reg_class[i] = NO_REGS;
3588 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3589 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3590 v9 int regs as it simplifies the code. */
3593 save_regs (file, low, high, base, offset, n_regs, real_offset)
3603 if (TARGET_ARCH64 && high <= 32)
3605 for (i = low; i < high; i++)
3607 if (regs_ever_live[i] && ! call_used_regs[i])
3609 fprintf (file, "\tstx\t%s, [%s+%d]\n",
3610 reg_names[i], base, offset + 4 * n_regs);
3611 if (dwarf2out_do_frame ())
3612 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3619 for (i = low; i < high; i += 2)
3621 if (regs_ever_live[i] && ! call_used_regs[i])
3623 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3625 fprintf (file, "\tstd\t%s, [%s+%d]\n",
3626 reg_names[i], base, offset + 4 * n_regs);
3627 if (dwarf2out_do_frame ())
3629 char *l = dwarf2out_cfi_label ();
3630 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3631 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3637 fprintf (file, "\tst\t%s, [%s+%d]\n",
3638 reg_names[i], base, offset + 4 * n_regs);
3639 if (dwarf2out_do_frame ())
3640 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3646 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3648 fprintf (file, "\tst\t%s, [%s+%d]\n",
3649 reg_names[i+1], base, offset + 4 * n_regs + 4);
3650 if (dwarf2out_do_frame ())
3651 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3660 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3662 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3663 v9 int regs as it simplifies the code. */
3666 restore_regs (file, low, high, base, offset, n_regs)
3675 if (TARGET_ARCH64 && high <= 32)
3677 for (i = low; i < high; i++)
3679 if (regs_ever_live[i] && ! call_used_regs[i])
3680 fprintf (file, "\tldx\t[%s+%d], %s\n",
3681 base, offset + 4 * n_regs, reg_names[i]),
3687 for (i = low; i < high; i += 2)
3689 if (regs_ever_live[i] && ! call_used_regs[i])
3690 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3691 fprintf (file, "\tldd\t[%s+%d], %s\n",
3692 base, offset + 4 * n_regs, reg_names[i]),
3695 fprintf (file, "\tld\t[%s+%d], %s\n",
3696 base, offset + 4 * n_regs, reg_names[i]),
3698 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3699 fprintf (file, "\tld\t[%s+%d], %s\n",
3700 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3707 /* Compute the frame size required by the function. This function is called
3708 during the reload pass and also by output_function_prologue(). */
3711 compute_frame_size (size, leaf_function)
3716 int outgoing_args_size = (current_function_outgoing_args_size
3717 + REG_PARM_STACK_SPACE (current_function_decl));
3719 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3720 even to v9 int regs to be consistent with save_regs/restore_regs. */
3724 for (i = 0; i < 8; i++)
3725 if (regs_ever_live[i] && ! call_used_regs[i])
3730 for (i = 0; i < 8; i += 2)
3731 if ((regs_ever_live[i] && ! call_used_regs[i])
3732 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3736 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3737 if ((regs_ever_live[i] && ! call_used_regs[i])
3738 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3741 /* Set up values for use in `function_epilogue'. */
3742 num_gfregs = n_regs;
3744 if (leaf_function && n_regs == 0
3745 && size == 0 && current_function_outgoing_args_size == 0)
3747 actual_fsize = apparent_fsize = 0;
3751 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3752 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
3753 apparent_fsize += n_regs * 4;
3754 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3757 /* Make sure nothing can clobber our register windows.
3758 If a SAVE must be done, or there is a stack-local variable,
3759 the register window area must be allocated.
3760 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3761 if (leaf_function == 0 || size > 0)
3762 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3764 return SPARC_STACK_ALIGN (actual_fsize);
3767 /* Build a (32 bit) big number in a register. */
3768 /* ??? We may be able to use the set macro here too. */
3771 build_big_number (file, num, reg)
3776 if (num >= 0 || ! TARGET_ARCH64)
3778 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
3779 if ((num & 0x3ff) != 0)
3780 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
3782 else /* num < 0 && TARGET_ARCH64 */
3784 /* Sethi does not sign extend, so we must use a little trickery
3785 to use it for negative numbers. Invert the constant before
3786 loading it in, then use xor immediate to invert the loaded bits
3787 (along with the upper 32 bits) to the desired constant. This
3788 works because the sethi and immediate fields overlap. */
3791 int low = -0x400 + (asize & 0x3FF);
3793 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3794 inv, reg, reg, low, reg);
3798 /* Output any necessary .register pseudo-ops. */
3800 sparc_output_scratch_registers (file)
3801 FILE *file ATTRIBUTE_UNUSED;
3803 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3809 /* Check if %g[2367] were used without
3810 .register being printed for them already. */
3811 for (i = 2; i < 8; i++)
3813 if (regs_ever_live [i]
3814 && ! sparc_hard_reg_printed [i])
3816 sparc_hard_reg_printed [i] = 1;
3817 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3824 /* This function generates the assembly code for function entry.
3825 FILE is a stdio stream to output the code to.
3826 SIZE is an int: how many units of temporary storage to allocate.
3827 Refer to the array `regs_ever_live' to determine which registers
3828 to save; `regs_ever_live[I]' is nonzero if register number I
3829 is ever used in the function. This macro is responsible for
3830 knowing which registers should not be saved even if used. */
3832 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3833 of memory. If any fpu reg is used in the function, we allocate
3834 such a block here, at the bottom of the frame, just in case it's needed.
3836 If this function is a leaf procedure, then we may choose not
3837 to do a "save" insn. The decision about whether or not
3838 to do this is made in regclass.c. */
3841 sparc_output_function_prologue (file, size)
3846 sparc_flat_function_prologue (file, size);
3848 sparc_nonflat_function_prologue (file, size,
3849 current_function_uses_only_leaf_regs);
3852 /* Output code for the function prologue. */
3855 sparc_nonflat_function_prologue (file, size, leaf_function)
3860 sparc_output_scratch_registers (file);
3862 /* Need to use actual_fsize, since we are also allocating
3863 space for our callee (and our own register save area). */
3864 actual_fsize = compute_frame_size (size, leaf_function);
3868 frame_base_name = "%sp";
3869 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3873 frame_base_name = "%fp";
3874 frame_base_offset = SPARC_STACK_BIAS;
3877 /* This is only for the human reader. */
3878 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3880 if (actual_fsize == 0)
3882 else if (! leaf_function)
3884 if (actual_fsize <= 4096)
3885 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3886 else if (actual_fsize <= 8192)
3888 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3889 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3893 build_big_number (file, -actual_fsize, "%g1");
3894 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
3897 else /* leaf function */
3899 if (actual_fsize <= 4096)
3900 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3901 else if (actual_fsize <= 8192)
3903 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3904 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3908 build_big_number (file, -actual_fsize, "%g1");
3909 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3913 if (dwarf2out_do_frame () && actual_fsize)
3915 char *label = dwarf2out_cfi_label ();
3917 /* The canonical frame address refers to the top of the frame. */
3918 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3919 : HARD_FRAME_POINTER_REGNUM),
3922 if (! leaf_function)
3924 /* Note the register window save. This tells the unwinder that
3925 it needs to restore the window registers from the previous
3926 frame's window save area at 0(cfa). */
3927 dwarf2out_window_save (label);
3929 /* The return address (-8) is now in %i7. */
3930 dwarf2out_return_reg (label, 31);
3934 /* If doing anything with PIC, do it now. */
3936 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3938 /* Call saved registers are saved just above the outgoing argument area. */
3941 int offset, real_offset, n_regs;
3944 real_offset = -apparent_fsize;
3945 offset = -apparent_fsize + frame_base_offset;
3946 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3948 /* ??? This might be optimized a little as %g1 might already have a
3949 value close enough that a single add insn will do. */
3950 /* ??? Although, all of this is probably only a temporary fix
3951 because if %g1 can hold a function result, then
3952 output_function_epilogue will lose (the result will get
3954 build_big_number (file, offset, "%g1");
3955 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3961 base = frame_base_name;
3964 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3965 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3970 /* Output code to restore any call saved registers. */
3973 output_restore_regs (file, leaf_function)
3975 int leaf_function ATTRIBUTE_UNUSED;
3980 offset = -apparent_fsize + frame_base_offset;
3981 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3983 build_big_number (file, offset, "%g1");
3984 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
3990 base = frame_base_name;
3993 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3994 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3997 /* This function generates the assembly code for function exit,
3998 on machines that need it.
4000 The function epilogue should not depend on the current stack pointer!
4001 It should use the frame pointer only. This is mandatory because
4002 of alloca; we also take advantage of it to omit stack adjustments
4003 before returning. */
4006 sparc_output_function_epilogue (file, size)
4011 sparc_flat_function_epilogue (file, size);
4013 sparc_nonflat_function_epilogue (file, size,
4014 current_function_uses_only_leaf_regs);
4017 /* Output code for the function epilogue. */
4020 sparc_nonflat_function_epilogue (file, size, leaf_function)
4022 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
4027 if (current_function_epilogue_delay_list == 0)
4029 /* If code does not drop into the epilogue, we need
4030 do nothing except output pending case vectors.
4032 We have to still output a dummy nop for the sake of
4033 sane backtraces. Otherwise, if the last two instructions
4034 of a function were call foo; dslot; this can make the return
4035 PC of foo (ie. address of call instruction plus 8) point to
4036 the first instruction in the next function. */
4039 fputs("\tnop\n", file);
4041 insn = get_last_insn ();
4042 if (GET_CODE (insn) == NOTE)
4043 insn = prev_nonnote_insn (insn);
4044 if (insn && GET_CODE (insn) == BARRIER)
4045 goto output_vectors;
4049 output_restore_regs (file, leaf_function);
4051 /* Work out how to skip the caller's unimp instruction if required. */
4053 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4055 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4057 if (! leaf_function)
4059 if (current_function_calls_eh_return)
4061 if (current_function_epilogue_delay_list)
4063 if (SKIP_CALLERS_UNIMP_P)
4066 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4068 /* If we wound up with things in our delay slot, flush them here. */
4069 else if (current_function_epilogue_delay_list)
4071 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4073 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4075 epilogue_renumber (&delay, 0);
4076 fputs (SKIP_CALLERS_UNIMP_P
4077 ? "\treturn\t%i7+12\n"
4078 : "\treturn\t%i7+8\n", file);
4079 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4086 if (GET_CODE (delay) != SET)
4089 src = SET_SRC (delay);
4090 if (GET_CODE (src) == ASHIFT)
4092 if (XEXP (src, 1) != const1_rtx)
4095 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4099 insn = gen_rtx_PARALLEL (VOIDmode,
4100 gen_rtvec (2, delay,
4101 gen_rtx_RETURN (VOIDmode)));
4102 insn = emit_jump_insn (insn);
4104 sparc_emitting_epilogue = true;
4105 final_scan_insn (insn, file, 1, 0, 1);
4106 sparc_emitting_epilogue = false;
4109 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4110 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4112 fprintf (file, "\t%s\n\trestore\n", ret);
4114 /* All of the following cases are for leaf functions. */
4115 else if (current_function_calls_eh_return)
4117 else if (current_function_epilogue_delay_list)
4119 /* eligible_for_epilogue_delay_slot ensures that if this is a
4120 leaf function, then we will only have insn in the delay slot
4121 if the frame size is zero, thus no adjust for the stack is
4123 if (actual_fsize != 0)
4125 fprintf (file, "\t%s\n", ret);
4126 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4129 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4130 avoid generating confusing assembly language output. */
4131 else if (actual_fsize == 0)
4132 fprintf (file, "\t%s\n\tnop\n", ret);
4133 else if (actual_fsize <= 4096)
4134 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
4135 else if (actual_fsize <= 8192)
4136 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4137 ret, actual_fsize - 4096);
4138 else if ((actual_fsize & 0x3ff) == 0)
4139 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4142 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4143 actual_fsize, actual_fsize, ret);
4146 sparc_output_deferred_case_vectors ();
4149 /* Output a sibling call. */
4152 output_sibcall (insn, call_operand)
4153 rtx insn, call_operand;
4155 int leaf_regs = current_function_uses_only_leaf_regs;
4157 int delay_slot = dbr_sequence_length () > 0;
4161 /* Call to restore global regs might clobber
4162 the delay slot. Instead of checking for this
4163 output the delay slot now. */
4166 rtx delay = NEXT_INSN (insn);
4171 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4172 PATTERN (delay) = gen_blockage ();
4173 INSN_CODE (delay) = -1;
4176 output_restore_regs (asm_out_file, leaf_regs);
4179 operands[0] = call_operand;
4183 #ifdef HAVE_AS_RELAX_OPTION
4184 /* If as and ld are relaxing tail call insns into branch always,
4185 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4186 be optimized. With sethi/jmpl as nor ld has no easy way how to
4187 find out if somebody does not branch between the sethi and jmpl. */
4190 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4194 if ((actual_fsize || ! spare_slot) && delay_slot)
4196 rtx delay = NEXT_INSN (insn);
4201 final_scan_insn (delay, asm_out_file, 1, 0, 1);
4202 PATTERN (delay) = gen_blockage ();
4203 INSN_CODE (delay) = -1;
4208 if (actual_fsize <= 4096)
4209 size = actual_fsize;
4210 else if (actual_fsize <= 8192)
4212 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4213 size = actual_fsize - 4096;
4215 else if ((actual_fsize & 0x3ff) == 0)
4216 fprintf (asm_out_file,
4217 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4221 fprintf (asm_out_file,
4222 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4223 actual_fsize, actual_fsize);
4224 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4229 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4230 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4232 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size);
4233 else if (! delay_slot)
4234 fputs ("\t nop\n", asm_out_file);
4239 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size);
4240 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4241 it into branch if possible. */
4242 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4243 output_asm_insn ("call\t%a0, 0", operands);
4244 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4249 output_asm_insn ("call\t%a0, 0", operands);
4252 rtx delay = NEXT_INSN (insn), pat;
4257 pat = PATTERN (delay);
4258 if (GET_CODE (pat) != SET)
4261 operands[0] = SET_DEST (pat);
4262 pat = SET_SRC (pat);
4263 switch (GET_CODE (pat))
4266 operands[1] = XEXP (pat, 0);
4267 operands[2] = XEXP (pat, 1);
4268 output_asm_insn (" restore %r1, %2, %Y0", operands);
4271 operands[1] = XEXP (pat, 0);
4272 operands[2] = XEXP (pat, 1);
4273 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4276 operands[1] = XEXP (pat, 0);
4277 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4281 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4284 PATTERN (delay) = gen_blockage ();
4285 INSN_CODE (delay) = -1;
4288 fputs ("\t restore\n", asm_out_file);
4292 /* Functions for handling argument passing.
4294 For v8 the first six args are normally in registers and the rest are
4295 pushed. Any arg that starts within the first 6 words is at least
4296 partially passed in a register unless its data type forbids.
4298 For v9, the argument registers are laid out as an array of 16 elements
4299 and arguments are added sequentially. The first 6 int args and up to the
4300 first 16 fp args (depending on size) are passed in regs.
4302 Slot Stack Integral Float Float in structure Double Long Double
4303 ---- ----- -------- ----- ------------------ ------ -----------
4304 15 [SP+248] %f31 %f30,%f31 %d30
4305 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4306 13 [SP+232] %f27 %f26,%f27 %d26
4307 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4308 11 [SP+216] %f23 %f22,%f23 %d22
4309 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4310 9 [SP+200] %f19 %f18,%f19 %d18
4311 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4312 7 [SP+184] %f15 %f14,%f15 %d14
4313 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4314 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4315 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4316 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4317 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4318 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4319 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4321 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4323 Integral arguments are always passed as 64 bit quantities appropriately
4326 Passing of floating point values is handled as follows.
4327 If a prototype is in scope:
4328 If the value is in a named argument (i.e. not a stdarg function or a
4329 value not part of the `...') then the value is passed in the appropriate
4331 If the value is part of the `...' and is passed in one of the first 6
4332 slots then the value is passed in the appropriate int reg.
4333 If the value is part of the `...' and is not passed in one of the first 6
4334 slots then the value is passed in memory.
4335 If a prototype is not in scope:
4336 If the value is one of the first 6 arguments the value is passed in the
4337 appropriate integer reg and the appropriate fp reg.
4338 If the value is not one of the first 6 arguments the value is passed in
4339 the appropriate fp reg and in memory.
4342 /* Maximum number of int regs for args. */
4343 #define SPARC_INT_ARG_MAX 6
4344 /* Maximum number of fp regs for args. */
4345 #define SPARC_FP_ARG_MAX 16
4347 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4349 /* Handle the INIT_CUMULATIVE_ARGS macro.
4350 Initialize a variable CUM of type CUMULATIVE_ARGS
4351 for a call to a function whose data type is FNTYPE.
4352 For a library call, FNTYPE is 0. */
4355 init_cumulative_args (cum, fntype, libname, indirect)
4356 CUMULATIVE_ARGS *cum;
4358 rtx libname ATTRIBUTE_UNUSED;
4359 int indirect ATTRIBUTE_UNUSED;
4362 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4363 cum->libcall_p = fntype == 0;
4366 /* Compute the slot number to pass an argument in.
4367 Returns the slot number or -1 if passing on the stack.
4369 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4370 the preceding args and about the function being called.
4371 MODE is the argument's machine mode.
4372 TYPE is the data type of the argument (as a tree).
4373 This is null for libcalls where that information may
4375 NAMED is nonzero if this argument is a named parameter
4376 (otherwise it is an extra parameter matching an ellipsis).
4377 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4378 *PREGNO records the register number to use if scalar type.
4379 *PPADDING records the amount of padding needed in words. */
4382 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
4383 const CUMULATIVE_ARGS *cum;
4384 enum machine_mode mode;
4391 int regbase = (incoming_p
4392 ? SPARC_INCOMING_INT_ARG_FIRST
4393 : SPARC_OUTGOING_INT_ARG_FIRST);
4394 int slotno = cum->words;
4399 if (type != 0 && TREE_ADDRESSABLE (type))
4402 && type != 0 && mode == BLKmode
4403 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4409 /* MODE is VOIDmode when generating the actual call.
4413 case QImode : case CQImode :
4414 case HImode : case CHImode :
4415 case SImode : case CSImode :
4416 case DImode : case CDImode :
4417 case TImode : case CTImode :
4418 if (slotno >= SPARC_INT_ARG_MAX)
4420 regno = regbase + slotno;
4423 case SFmode : case SCmode :
4424 case DFmode : case DCmode :
4425 case TFmode : case TCmode :
4428 if (slotno >= SPARC_INT_ARG_MAX)
4430 regno = regbase + slotno;
4434 if ((mode == TFmode || mode == TCmode)
4435 && (slotno & 1) != 0)
4436 slotno++, *ppadding = 1;
4437 if (TARGET_FPU && named)
4439 if (slotno >= SPARC_FP_ARG_MAX)
4441 regno = SPARC_FP_ARG_FIRST + slotno * 2;
4447 if (slotno >= SPARC_INT_ARG_MAX)
4449 regno = regbase + slotno;
4455 /* For sparc64, objects requiring 16 byte alignment get it. */
4458 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
4459 slotno++, *ppadding = 1;
4463 || (type && TREE_CODE (type) == UNION_TYPE))
4465 if (slotno >= SPARC_INT_ARG_MAX)
4467 regno = regbase + slotno;
4472 int intregs_p = 0, fpregs_p = 0;
4473 /* The ABI obviously doesn't specify how packed
4474 structures are passed. These are defined to be passed
4475 in int regs if possible, otherwise memory. */
4478 /* First see what kinds of registers we need. */
4479 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4481 if (TREE_CODE (field) == FIELD_DECL)
4483 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4488 if (DECL_PACKED (field))
4492 if (packed_p || !named)
4493 fpregs_p = 0, intregs_p = 1;
4495 /* If all arg slots are filled, then must pass on stack. */
4496 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
4498 /* If there are only int args and all int arg slots are filled,
4499 then must pass on stack. */
4500 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
4502 /* Note that even if all int arg slots are filled, fp members may
4503 still be passed in regs if such regs are available.
4504 *PREGNO isn't set because there may be more than one, it's up
4505 to the caller to compute them. */
4518 /* Handle recursive register counting for structure field layout. */
4520 struct function_arg_record_value_parms
4523 int slotno, named, regbase;
4528 static void function_arg_record_value_3
4529 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
4530 static void function_arg_record_value_2
4531 PARAMS ((tree, HOST_WIDE_INT,
4532 struct function_arg_record_value_parms *));
4533 static void function_arg_record_value_1
4534 PARAMS ((tree, HOST_WIDE_INT,
4535 struct function_arg_record_value_parms *));
4536 static rtx function_arg_record_value
4537 PARAMS ((tree, enum machine_mode, int, int, int));
4539 /* A subroutine of function_arg_record_value. Traverse the structure
4540 recusively and determine how many registers will be required. */
4543 function_arg_record_value_1 (type, startbitpos, parms)
4545 HOST_WIDE_INT startbitpos;
4546 struct function_arg_record_value_parms *parms;
4550 /* The ABI obviously doesn't specify how packed structures are
4551 passed. These are defined to be passed in int regs if possible,
4552 otherwise memory. */
4555 /* We need to compute how many registers are needed so we can
4556 allocate the PARALLEL but before we can do that we need to know
4557 whether there are any packed fields. If there are, int regs are
4558 used regardless of whether there are fp values present. */
4559 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4561 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4568 /* Compute how many registers we need. */
4569 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4571 if (TREE_CODE (field) == FIELD_DECL)
4573 HOST_WIDE_INT bitpos = startbitpos;
4575 if (DECL_SIZE (field) != 0
4576 && host_integerp (bit_position (field), 1))
4577 bitpos += int_bit_position (field);
4579 /* ??? FIXME: else assume zero offset. */
4581 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4582 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
4583 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4584 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4585 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4591 if (parms->intoffset != -1)
4593 int intslots, this_slotno;
4595 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
4597 this_slotno = parms->slotno + parms->intoffset
4600 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4601 intslots = MAX (intslots, 0);
4602 parms->nregs += intslots;
4603 parms->intoffset = -1;
4606 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4607 If it wasn't true we wouldn't be here. */
4609 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4614 if (parms->intoffset == -1)
4615 parms->intoffset = bitpos;
4621 /* A subroutine of function_arg_record_value. Assign the bits of the
4622 structure between parms->intoffset and bitpos to integer registers. */
4625 function_arg_record_value_3 (bitpos, parms)
4626 HOST_WIDE_INT bitpos;
4627 struct function_arg_record_value_parms *parms;
4629 enum machine_mode mode;
4631 unsigned int startbit, endbit;
4632 int this_slotno, intslots, intoffset;
4635 if (parms->intoffset == -1)
4638 intoffset = parms->intoffset;
4639 parms->intoffset = -1;
4641 startbit = intoffset & -BITS_PER_WORD;
4642 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4643 intslots = (endbit - startbit) / BITS_PER_WORD;
4644 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
4646 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4650 /* If this is the trailing part of a word, only load that much into
4651 the register. Otherwise load the whole register. Note that in
4652 the latter case we may pick up unwanted bits. It's not a problem
4653 at the moment but may wish to revisit. */
4655 if (intoffset % BITS_PER_WORD != 0)
4656 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4661 intoffset /= BITS_PER_UNIT;
4664 regno = parms->regbase + this_slotno;
4665 reg = gen_rtx_REG (mode, regno);
4666 XVECEXP (parms->ret, 0, parms->nregs)
4667 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4670 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4674 while (intslots > 0);
4677 /* A subroutine of function_arg_record_value. Traverse the structure
4678 recursively and assign bits to floating point registers. Track which
4679 bits in between need integer registers; invoke function_arg_record_value_3
4680 to make that happen. */
4683 function_arg_record_value_2 (type, startbitpos, parms)
4685 HOST_WIDE_INT startbitpos;
4686 struct function_arg_record_value_parms *parms;
4691 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4693 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
4700 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4702 if (TREE_CODE (field) == FIELD_DECL)
4704 HOST_WIDE_INT bitpos = startbitpos;
4706 if (DECL_SIZE (field) != 0
4707 && host_integerp (bit_position (field), 1))
4708 bitpos += int_bit_position (field);
4710 /* ??? FIXME: else assume zero offset. */
4712 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4713 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
4714 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4715 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE
4716 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field)))
4722 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
4724 enum machine_mode mode = DECL_MODE (field);
4727 function_arg_record_value_3 (bitpos, parms);
4728 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
4729 + ((mode == SFmode || mode == SCmode)
4730 && (bitpos & 32) != 0);
4733 case SCmode: mode = SFmode; break;
4734 case DCmode: mode = DFmode; break;
4735 case TCmode: mode = TFmode; break;
4738 reg = gen_rtx_REG (mode, regno);
4739 XVECEXP (parms->ret, 0, parms->nregs)
4740 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4741 GEN_INT (bitpos / BITS_PER_UNIT));
4743 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
4745 regno += GET_MODE_SIZE (mode) / 4;
4746 reg = gen_rtx_REG (mode, regno);
4747 XVECEXP (parms->ret, 0, parms->nregs)
4748 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4749 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
4756 if (parms->intoffset == -1)
4757 parms->intoffset = bitpos;
4763 /* Used by function_arg and function_value to implement the complex
4764 SPARC64 structure calling conventions. */
4767 function_arg_record_value (type, mode, slotno, named, regbase)
4769 enum machine_mode mode;
4770 int slotno, named, regbase;
4772 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4773 struct function_arg_record_value_parms parms;
4776 parms.ret = NULL_RTX;
4777 parms.slotno = slotno;
4778 parms.named = named;
4779 parms.regbase = regbase;
4781 /* Compute how many registers we need. */
4783 parms.intoffset = 0;
4784 function_arg_record_value_1 (type, 0, &parms);
4786 if (parms.intoffset != -1)
4788 unsigned int startbit, endbit;
4789 int intslots, this_slotno;
4791 startbit = parms.intoffset & -BITS_PER_WORD;
4792 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4793 intslots = (endbit - startbit) / BITS_PER_WORD;
4794 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
4796 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
4797 intslots = MAX (intslots, 0);
4799 parms.nregs += intslots;
4801 nregs = parms.nregs;
4803 /* Allocate the vector and handle some annoying special cases. */
4806 /* ??? Empty structure has no value? Duh? */
4809 /* Though there's nothing really to store, return a word register
4810 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4811 leads to breakage due to the fact that there are zero bytes to
4813 return gen_rtx_REG (mode, regbase);
4817 /* ??? C++ has structures with no fields, and yet a size. Give up
4818 for now and pass everything back in integer registers. */
4819 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4821 if (nregs + slotno > SPARC_INT_ARG_MAX)
4822 nregs = SPARC_INT_ARG_MAX - slotno;
4827 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
4829 /* Fill in the entries. */
4831 parms.intoffset = 0;
4832 function_arg_record_value_2 (type, 0, &parms);
4833 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
4835 if (parms.nregs != nregs)
4841 /* Handle the FUNCTION_ARG macro.
4842 Determine where to put an argument to a function.
4843 Value is zero to push the argument on the stack,
4844 or a hard register in which to store the argument.
4846 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4847 the preceding args and about the function being called.
4848 MODE is the argument's machine mode.
4849 TYPE is the data type of the argument (as a tree).
4850 This is null for libcalls where that information may
4852 NAMED is nonzero if this argument is a named parameter
4853 (otherwise it is an extra parameter matching an ellipsis).
4854 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4857 function_arg (cum, mode, type, named, incoming_p)
4858 const CUMULATIVE_ARGS *cum;
4859 enum machine_mode mode;
4864 int regbase = (incoming_p
4865 ? SPARC_INCOMING_INT_ARG_FIRST
4866 : SPARC_OUTGOING_INT_ARG_FIRST);
4867 int slotno, regno, padding;
4870 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
4878 reg = gen_rtx_REG (mode, regno);
4882 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4883 but also have the slot allocated for them.
4884 If no prototype is in scope fp values in register slots get passed
4885 in two places, either fp regs and int regs or fp regs and memory. */
4886 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4887 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4888 && SPARC_FP_REG_P (regno))
4890 reg = gen_rtx_REG (mode, regno);
4891 if (cum->prototype_p || cum->libcall_p)
4893 /* "* 2" because fp reg numbers are recorded in 4 byte
4896 /* ??? This will cause the value to be passed in the fp reg and
4897 in the stack. When a prototype exists we want to pass the
4898 value in the reg but reserve space on the stack. That's an
4899 optimization, and is deferred [for a bit]. */
4900 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
4901 return gen_rtx_PARALLEL (mode,
4903 gen_rtx_EXPR_LIST (VOIDmode,
4904 NULL_RTX, const0_rtx),
4905 gen_rtx_EXPR_LIST (VOIDmode,
4909 /* ??? It seems that passing back a register even when past
4910 the area declared by REG_PARM_STACK_SPACE will allocate
4911 space appropriately, and will not copy the data onto the
4912 stack, exactly as we desire.
4914 This is due to locate_and_pad_parm being called in
4915 expand_call whenever reg_parm_stack_space > 0, which
4916 while benefical to our example here, would seem to be
4917 in error from what had been intended. Ho hum... -- r~ */
4925 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
4929 /* On incoming, we don't need to know that the value
4930 is passed in %f0 and %i0, and it confuses other parts
4931 causing needless spillage even on the simplest cases. */
4935 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
4936 + (regno - SPARC_FP_ARG_FIRST) / 2);
4938 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4939 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
4941 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4945 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4946 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4947 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4951 else if (type && TREE_CODE (type) == RECORD_TYPE)
4953 /* Structures up to 16 bytes in size are passed in arg slots on the
4954 stack and are promoted to registers where possible. */
4956 if (int_size_in_bytes (type) > 16)
4957 abort (); /* shouldn't get here */
4959 return function_arg_record_value (type, mode, slotno, named, regbase);
4961 else if (type && TREE_CODE (type) == UNION_TYPE)
4963 enum machine_mode mode;
4964 int bytes = int_size_in_bytes (type);
4969 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4970 reg = gen_rtx_REG (mode, regno);
4974 /* Scalar or complex int. */
4975 reg = gen_rtx_REG (mode, regno);
4981 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4982 For an arg passed partly in registers and partly in memory,
4983 this is the number of registers used.
4984 For args passed entirely in registers or entirely in memory, zero.
4986 Any arg that starts in the first 6 regs but won't entirely fit in them
4987 needs partial registers on v8. On v9, structures with integer
4988 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4989 values that begin in the last fp reg [where "last fp reg" varies with the
4990 mode] will be split between that reg and memory. */
4993 function_arg_partial_nregs (cum, mode, type, named)
4994 const CUMULATIVE_ARGS *cum;
4995 enum machine_mode mode;
4999 int slotno, regno, padding;
5001 /* We pass 0 for incoming_p here, it doesn't matter. */
5002 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5009 if ((slotno + (mode == BLKmode
5010 ? ROUND_ADVANCE (int_size_in_bytes (type))
5011 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5012 > NPARM_REGS (SImode))
5013 return NPARM_REGS (SImode) - slotno;
5018 if (type && AGGREGATE_TYPE_P (type))
5020 int size = int_size_in_bytes (type);
5021 int align = TYPE_ALIGN (type);
5024 slotno += slotno & 1;
5025 if (size > 8 && size <= 16
5026 && slotno == SPARC_INT_ARG_MAX - 1)
5029 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5030 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5033 if (GET_MODE_ALIGNMENT (mode) == 128)
5035 slotno += slotno & 1;
5036 if (slotno == SPARC_INT_ARG_MAX - 2)
5041 if (slotno == SPARC_INT_ARG_MAX - 1)
5045 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5047 if (GET_MODE_ALIGNMENT (mode) == 128)
5048 slotno += slotno & 1;
5049 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5057 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5058 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5059 quad-precision floats by invisible reference.
5060 v9: Aggregates greater than 16 bytes are passed by reference.
5061 For Pascal, also pass arrays by reference. */
5064 function_arg_pass_by_reference (cum, mode, type, named)
5065 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
5066 enum machine_mode mode;
5068 int named ATTRIBUTE_UNUSED;
5072 return ((type && AGGREGATE_TYPE_P (type))
5073 || mode == TFmode || mode == TCmode);
5077 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5078 /* Consider complex values as aggregates, so care for TCmode. */
5079 || GET_MODE_SIZE (mode) > 16
5081 && AGGREGATE_TYPE_P (type)
5082 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5086 /* Handle the FUNCTION_ARG_ADVANCE macro.
5087 Update the data in CUM to advance over an argument
5088 of mode MODE and data type TYPE.
5089 TYPE is null for libcalls where that information may not be available. */
5092 function_arg_advance (cum, mode, type, named)
5093 CUMULATIVE_ARGS *cum;
5094 enum machine_mode mode;
5098 int slotno, regno, padding;
5100 /* We pass 0 for incoming_p here, it doesn't matter. */
5101 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5103 /* If register required leading padding, add it. */
5105 cum->words += padding;
5109 cum->words += (mode != BLKmode
5110 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5111 : ROUND_ADVANCE (int_size_in_bytes (type)));
5115 if (type && AGGREGATE_TYPE_P (type))
5117 int size = int_size_in_bytes (type);
5121 else if (size <= 16)
5123 else /* passed by reference */
5126 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
5130 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5132 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
5136 cum->words += (mode != BLKmode
5137 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5138 : ROUND_ADVANCE (int_size_in_bytes (type)));
5143 /* Handle the FUNCTION_ARG_PADDING macro.
5144 For the 64 bit ABI structs are always stored left shifted in their
5148 function_arg_padding (mode, type)
5149 enum machine_mode mode;
5152 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5155 /* This is the default definition. */
5156 return (! BYTES_BIG_ENDIAN
5159 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5160 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
5161 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5162 ? downward : upward));
5165 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5166 For v9, function return values are subject to the same rules as arguments,
5167 except that up to 32-bytes may be returned in registers. */
5170 function_value (type, mode, incoming_p)
5172 enum machine_mode mode;
5176 int regbase = (incoming_p
5177 ? SPARC_OUTGOING_INT_ARG_FIRST
5178 : SPARC_INCOMING_INT_ARG_FIRST);
5180 if (TARGET_ARCH64 && type)
5182 if (TREE_CODE (type) == RECORD_TYPE)
5184 /* Structures up to 32 bytes in size are passed in registers,
5185 promoted to fp registers where possible. */
5187 if (int_size_in_bytes (type) > 32)
5188 abort (); /* shouldn't get here */
5190 return function_arg_record_value (type, mode, 0, 1, regbase);
5192 else if (AGGREGATE_TYPE_P (type))
5194 /* All other aggregate types are passed in an integer register
5195 in a mode corresponding to the size of the type. */
5196 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5201 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5206 && GET_MODE_CLASS (mode) == MODE_INT
5207 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5208 && type && ! AGGREGATE_TYPE_P (type))
5212 regno = BASE_RETURN_VALUE_REG (mode);
5214 regno = BASE_OUTGOING_VALUE_REG (mode);
5216 return gen_rtx_REG (mode, regno);
5219 /* Do what is necessary for `va_start'. We look at the current function
5220 to determine if stdarg or varargs is used and return the address of
5221 the first unnamed parameter. */
5224 sparc_builtin_saveregs ()
5226 int first_reg = current_function_args_info.words;
5230 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5231 emit_move_insn (gen_rtx_MEM (word_mode,
5232 gen_rtx_PLUS (Pmode,
5234 GEN_INT (FIRST_PARM_OFFSET (0)
5237 gen_rtx_REG (word_mode,
5238 BASE_INCOMING_ARG_REG (word_mode) + regno));
5240 address = gen_rtx_PLUS (Pmode,
5242 GEN_INT (FIRST_PARM_OFFSET (0)
5243 + UNITS_PER_WORD * first_reg));
5248 /* Implement `va_start' for varargs and stdarg. */
5251 sparc_va_start (valist, nextarg)
5255 nextarg = expand_builtin_saveregs ();
5256 std_expand_builtin_va_start (valist, nextarg);
5259 /* Implement `va_arg'. */
5262 sparc_va_arg (valist, type)
5265 HOST_WIDE_INT size, rsize, align;
5270 /* Round up sizeof(type) to a word. */
5271 size = int_size_in_bytes (type);
5272 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5277 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5278 align = 2 * UNITS_PER_WORD;
5280 if (AGGREGATE_TYPE_P (type))
5282 if ((unsigned HOST_WIDE_INT) size > 16)
5285 size = rsize = UNITS_PER_WORD;
5287 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5288 given one 8 byte slot. */
5290 size = rsize = UNITS_PER_WORD;
5297 if (AGGREGATE_TYPE_P (type)
5298 || TYPE_MODE (type) == TFmode
5299 || TYPE_MODE (type) == TCmode)
5302 size = rsize = UNITS_PER_WORD;
5309 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5310 build_int_2 (align - 1, 0)));
5311 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5312 build_int_2 (-align, -1)));
5315 addr = incr = save_expr (incr);
5316 if (BYTES_BIG_ENDIAN && size < rsize)
5318 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5319 build_int_2 (rsize - size, 0)));
5321 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5322 build_int_2 (rsize, 0)));
5324 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5325 TREE_SIDE_EFFECTS (incr) = 1;
5326 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5328 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5330 /* If the address isn't aligned properly for the type,
5331 we may need to copy to a temporary.
5332 FIXME: This is inefficient. Usually we can do this
5335 && TYPE_ALIGN (type) > BITS_PER_WORD
5338 /* FIXME: We really need to specify that the temporary is live
5339 for the whole function because expand_builtin_va_arg wants
5340 the alias set to be get_varargs_alias_set (), but in this
5341 case the alias set is that for TYPE and if the memory gets
5342 reused it will be reused with alias set TYPE. */
5343 rtx tmp = assign_temp (type, 0, 1, 0);
5346 addr_rtx = force_reg (Pmode, addr_rtx);
5347 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5348 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5349 set_mem_align (addr_rtx, BITS_PER_WORD);
5350 tmp = shallow_copy_rtx (tmp);
5351 PUT_MODE (tmp, BLKmode);
5352 set_mem_alias_set (tmp, 0);
5354 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5356 if (dest_addr != NULL_RTX)
5357 addr_rtx = dest_addr;
5359 addr_rtx = XCEXP (tmp, 0, MEM);
5364 addr_rtx = force_reg (Pmode, addr_rtx);
5365 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5366 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5372 /* Return the string to output a conditional branch to LABEL, which is
5373 the operand number of the label. OP is the conditional expression.
5374 XEXP (OP, 0) is assumed to be a condition code register (integer or
5375 floating point) and its mode specifies what kind of comparison we made.
5377 REVERSED is nonzero if we should reverse the sense of the comparison.
5379 ANNUL is nonzero if we should generate an annulling branch.
5381 NOOP is nonzero if we have to follow this branch by a noop.
5383 INSN, if set, is the insn. */
5386 output_cbranch (op, dest, label, reversed, annul, noop, insn)
5389 int reversed, annul, noop;
5392 static char string[50];
5393 enum rtx_code code = GET_CODE (op);
5394 rtx cc_reg = XEXP (op, 0);
5395 enum machine_mode mode = GET_MODE (cc_reg);
5396 const char *labelno, *branch;
5397 int spaces = 8, far;
5400 /* v9 branches are limited to +-1MB. If it is too far away,
5413 fbne,a,pn %fcc2, .LC29
5421 far = get_attr_length (insn) >= 3;
5424 /* Reversal of FP compares takes care -- an ordered compare
5425 becomes an unordered compare and vice versa. */
5426 if (mode == CCFPmode || mode == CCFPEmode)
5427 code = reverse_condition_maybe_unordered (code);
5429 code = reverse_condition (code);
5432 /* Start by writing the branch condition. */
5433 if (mode == CCFPmode || mode == CCFPEmode)
5484 /* ??? !v9: FP branches cannot be preceded by another floating point
5485 insn. Because there is currently no concept of pre-delay slots,
5486 we can fix this only by always emitting a nop before a floating
5491 strcpy (string, "nop\n\t");
5492 strcat (string, branch);
5505 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5517 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
5538 strcpy (string, branch);
5540 spaces -= strlen (branch);
5541 p = strchr (string, '\0');
5543 /* Now add the annulling, the label, and a possible noop. */
5558 if (! far && insn && INSN_ADDRESSES_SET_P ())
5560 int delta = (INSN_ADDRESSES (INSN_UID (dest))
5561 - INSN_ADDRESSES (INSN_UID (insn)));
5562 /* Leave some instructions for "slop". */
5563 if (delta < -260000 || delta >= 260000)
5567 if (mode == CCFPmode || mode == CCFPEmode)
5569 static char v9_fcc_labelno[] = "%%fccX, ";
5570 /* Set the char indicating the number of the fcc reg to use. */
5571 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5572 labelno = v9_fcc_labelno;
5575 if (REGNO (cc_reg) == SPARC_FCC_REG)
5581 else if (mode == CCXmode || mode == CCX_NOOVmode)
5583 labelno = "%%xcc, ";
5589 labelno = "%%icc, ";
5594 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5597 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5607 strcpy (p, labelno);
5608 p = strchr (p, '\0');
5611 strcpy (p, ".+12\n\tnop\n\tb\t");
5618 /* Set the char indicating the number of the operand containing the
5623 strcpy (p, "\n\tnop");
5628 /* Emit a library call comparison between floating point X and Y.
5629 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5630 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5631 values as arguments instead of the TFmode registers themselves,
5632 that's why we cannot call emit_float_lib_cmp. */
5634 sparc_emit_float_lib_cmp (x, y, comparison)
5636 enum rtx_code comparison;
5639 rtx slot0, slot1, result, tem, tem2;
5640 enum machine_mode mode;
5645 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
5649 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
5653 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
5657 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
5661 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
5665 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
5676 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
5686 if (GET_CODE (x) != MEM)
5688 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5689 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
5694 if (GET_CODE (y) != MEM)
5696 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
5697 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
5702 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5704 XEXP (slot0, 0), Pmode,
5705 XEXP (slot1, 0), Pmode);
5711 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
5713 x, TFmode, y, TFmode);
5719 /* Immediately move the result of the libcall into a pseudo
5720 register so reload doesn't clobber the value if it needs
5721 the return register for a spill reg. */
5722 result = gen_reg_rtx (mode);
5723 emit_move_insn (result, hard_libcall_value (mode));
5728 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
5732 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
5737 emit_cmp_insn (result, const1_rtx,
5738 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
5741 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
5744 tem = gen_reg_rtx (mode);
5746 emit_insn (gen_andsi3 (tem, result, const1_rtx));
5748 emit_insn (gen_anddi3 (tem, result, const1_rtx));
5749 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
5753 tem = gen_reg_rtx (mode);
5755 emit_insn (gen_addsi3 (tem, result, const1_rtx));
5757 emit_insn (gen_adddi3 (tem, result, const1_rtx));
5758 tem2 = gen_reg_rtx (mode);
5760 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
5762 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
5763 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
5769 /* Generate an unsigned DImode to FP conversion. This is the same code
5770 optabs would emit if we didn't have TFmode patterns. */
5773 sparc_emit_floatunsdi (operands)
5776 rtx neglab, donelab, i0, i1, f0, in, out;
5777 enum machine_mode mode;
5780 in = force_reg (DImode, operands[1]);
5781 mode = GET_MODE (out);
5782 neglab = gen_label_rtx ();
5783 donelab = gen_label_rtx ();
5784 i0 = gen_reg_rtx (DImode);
5785 i1 = gen_reg_rtx (DImode);
5786 f0 = gen_reg_rtx (mode);
5788 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
5790 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
5791 emit_jump_insn (gen_jump (donelab));
5794 emit_label (neglab);
5796 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
5797 emit_insn (gen_anddi3 (i1, in, const1_rtx));
5798 emit_insn (gen_iordi3 (i0, i0, i1));
5799 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
5800 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
5802 emit_label (donelab);
5805 /* Return the string to output a conditional branch to LABEL, testing
5806 register REG. LABEL is the operand number of the label; REG is the
5807 operand number of the reg. OP is the conditional expression. The mode
5808 of REG says what kind of comparison we made.
5810 REVERSED is nonzero if we should reverse the sense of the comparison.
5812 ANNUL is nonzero if we should generate an annulling branch.
5814 NOOP is nonzero if we have to follow this branch by a noop. */
5817 output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
5820 int reversed, annul, noop;
5823 static char string[50];
5824 enum rtx_code code = GET_CODE (op);
5825 enum machine_mode mode = GET_MODE (XEXP (op, 0));
5830 /* branch on register are limited to +-128KB. If it is too far away,
5843 brgez,a,pn %o1, .LC29
5849 ba,pt %xcc, .LC29 */
5851 far = get_attr_length (insn) >= 3;
5853 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5855 code = reverse_condition (code);
5857 /* Only 64 bit versions of these instructions exist. */
5861 /* Start by writing the branch condition. */
5866 strcpy (string, "brnz");
5870 strcpy (string, "brz");
5874 strcpy (string, "brgez");
5878 strcpy (string, "brlz");
5882 strcpy (string, "brlez");
5886 strcpy (string, "brgz");
5893 p = strchr (string, '\0');
5895 /* Now add the annulling, reg, label, and nop. */
5902 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
5905 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
5910 *p = p < string + 8 ? '\t' : ' ';
5918 int veryfar = 1, delta;
5920 if (INSN_ADDRESSES_SET_P ())
5922 delta = (INSN_ADDRESSES (INSN_UID (dest))
5923 - INSN_ADDRESSES (INSN_UID (insn)));
5924 /* Leave some instructions for "slop". */
5925 if (delta >= -260000 && delta < 260000)
5929 strcpy (p, ".+12\n\tnop\n\t");
5940 strcpy (p, "ba,pt\t%%xcc, ");
5950 strcpy (p, "\n\tnop");
5955 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5956 Such instructions cannot be used in the delay slot of return insn on v9.
5957 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5961 epilogue_renumber (where, test)
5962 register rtx *where;
5965 register const char *fmt;
5967 register enum rtx_code code;
5972 code = GET_CODE (*where);
5977 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
5979 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
5980 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
5988 /* Do not replace the frame pointer with the stack pointer because
5989 it can cause the delayed instruction to load below the stack.
5990 This occurs when instructions like:
5992 (set (reg/i:SI 24 %i0)
5993 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
5994 (const_int -20 [0xffffffec])) 0))
5996 are in the return delayed slot. */
5998 if (GET_CODE (XEXP (*where, 0)) == REG
5999 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6000 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6001 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6006 if (SPARC_STACK_BIAS
6007 && GET_CODE (XEXP (*where, 0)) == REG
6008 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6016 fmt = GET_RTX_FORMAT (code);
6018 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6023 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6024 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6027 else if (fmt[i] == 'e'
6028 && epilogue_renumber (&(XEXP (*where, i)), test))
6034 /* Leaf functions and non-leaf functions have different needs. */
6037 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6040 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6042 static const int *const reg_alloc_orders[] = {
6043 reg_leaf_alloc_order,
6044 reg_nonleaf_alloc_order};
6047 order_regs_for_local_alloc ()
6049 static int last_order_nonleaf = 1;
6051 if (regs_ever_live[15] != last_order_nonleaf)
6053 last_order_nonleaf = !last_order_nonleaf;
6054 memcpy ((char *) reg_alloc_order,
6055 (const char *) reg_alloc_orders[last_order_nonleaf],
6056 FIRST_PSEUDO_REGISTER * sizeof (int));
6060 /* Return 1 if REG and MEM are legitimate enough to allow the various
6061 mem<-->reg splits to be run. */
6064 sparc_splitdi_legitimate (reg, mem)
6068 /* Punt if we are here by mistake. */
6069 if (! reload_completed)
6072 /* We must have an offsettable memory reference. */
6073 if (! offsettable_memref_p (mem))
6076 /* If we have legitimate args for ldd/std, we do not want
6077 the split to happen. */
6078 if ((REGNO (reg) % 2) == 0
6079 && mem_min_alignment (mem, 8))
6086 /* Return 1 if x and y are some kind of REG and they refer to
6087 different hard registers. This test is guarenteed to be
6088 run after reload. */
6091 sparc_absnegfloat_split_legitimate (x, y)
6094 if (GET_CODE (x) != REG)
6096 if (GET_CODE (y) != REG)
6098 if (REGNO (x) == REGNO (y))
6103 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6104 This makes them candidates for using ldd and std insns.
6106 Note reg1 and reg2 *must* be hard registers. */
6109 registers_ok_for_ldd_peep (reg1, reg2)
6112 /* We might have been passed a SUBREG. */
6113 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6116 if (REGNO (reg1) % 2 != 0)
6119 /* Integer ldd is deprecated in SPARC V9 */
6120 if (TARGET_V9 && REGNO (reg1) < 32)
6123 return (REGNO (reg1) == REGNO (reg2) - 1);
6126 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6129 This can only happen when addr1 and addr2, the addresses in mem1
6130 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6131 addr1 must also be aligned on a 64-bit boundary.
6133 Also iff dependent_reg_rtx is not null it should not be used to
6134 compute the address for mem1, i.e. we cannot optimize a sequence
6146 But, note that the transformation from:
6151 is perfectly fine. Thus, the peephole2 patterns always pass us
6152 the destination register of the first load, never the second one.
6154 For stores we don't have a similar problem, so dependent_reg_rtx is
6158 mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
6159 rtx mem1, mem2, dependent_reg_rtx;
6165 /* The mems cannot be volatile. */
6166 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6169 /* MEM1 should be aligned on a 64-bit boundary. */
6170 if (MEM_ALIGN (mem1) < 64)
6173 addr1 = XEXP (mem1, 0);
6174 addr2 = XEXP (mem2, 0);
6176 /* Extract a register number and offset (if used) from the first addr. */
6177 if (GET_CODE (addr1) == PLUS)
6179 /* If not a REG, return zero. */
6180 if (GET_CODE (XEXP (addr1, 0)) != REG)
6184 reg1 = REGNO (XEXP (addr1, 0));
6185 /* The offset must be constant! */
6186 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6188 offset1 = INTVAL (XEXP (addr1, 1));
6191 else if (GET_CODE (addr1) != REG)
6195 reg1 = REGNO (addr1);
6196 /* This was a simple (mem (reg)) expression. Offset is 0. */
6200 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6201 if (GET_CODE (addr2) != PLUS)
6204 if (GET_CODE (XEXP (addr2, 0)) != REG
6205 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6208 if (reg1 != REGNO (XEXP (addr2, 0)))
6211 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6214 /* The first offset must be evenly divisible by 8 to ensure the
6215 address is 64 bit aligned. */
6216 if (offset1 % 8 != 0)
6219 /* The offset for the second addr must be 4 more than the first addr. */
6220 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6223 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6228 /* Return 1 if reg is a pseudo, or is the first register in
6229 a hard register pair. This makes it a candidate for use in
6230 ldd and std insns. */
6233 register_ok_for_ldd (reg)
6236 /* We might have been passed a SUBREG. */
6237 if (GET_CODE (reg) != REG)
6240 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6241 return (REGNO (reg) % 2 == 0);
6246 /* Print operand X (an rtx) in assembler syntax to file FILE.
6247 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6248 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6251 print_operand (file, x, code)
6259 /* Output a 'nop' if there's nothing for the delay slot. */
6260 if (dbr_sequence_length () == 0)
6261 fputs ("\n\t nop", file);
6264 /* Output an annul flag if there's nothing for the delay slot and we
6265 are optimizing. This is always used with '(' below. */
6266 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6267 this is a dbx bug. So, we only do this when optimizing. */
6268 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6269 Always emit a nop in case the next instruction is a branch. */
6270 if (dbr_sequence_length () == 0
6271 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6275 /* Output a 'nop' if there's nothing for the delay slot and we are
6276 not optimizing. This is always used with '*' above. */
6277 if (dbr_sequence_length () == 0
6278 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6279 fputs ("\n\t nop", file);
6282 /* Output the Embedded Medium/Anywhere code model base register. */
6283 fputs (EMBMEDANY_BASE_REG, file);
6286 /* Print out what we are using as the frame pointer. This might
6287 be %fp, or might be %sp+offset. */
6288 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6289 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
6292 /* Adjust the operand to take into account a RESTORE operation. */
6293 if (GET_CODE (x) == CONST_INT)
6295 else if (GET_CODE (x) != REG)
6296 output_operand_lossage ("invalid %%Y operand");
6297 else if (REGNO (x) < 8)
6298 fputs (reg_names[REGNO (x)], file);
6299 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6300 fputs (reg_names[REGNO (x)-16], file);
6302 output_operand_lossage ("invalid %%Y operand");
6305 /* Print out the low order register name of a register pair. */
6306 if (WORDS_BIG_ENDIAN)
6307 fputs (reg_names[REGNO (x)+1], file);
6309 fputs (reg_names[REGNO (x)], file);
6312 /* Print out the high order register name of a register pair. */
6313 if (WORDS_BIG_ENDIAN)
6314 fputs (reg_names[REGNO (x)], file);
6316 fputs (reg_names[REGNO (x)+1], file);
6319 /* Print out the second register name of a register pair or quad.
6320 I.e., R (%o0) => %o1. */
6321 fputs (reg_names[REGNO (x)+1], file);
6324 /* Print out the third register name of a register quad.
6325 I.e., S (%o0) => %o2. */
6326 fputs (reg_names[REGNO (x)+2], file);
6329 /* Print out the fourth register name of a register quad.
6330 I.e., T (%o0) => %o3. */
6331 fputs (reg_names[REGNO (x)+3], file);
6334 /* Print a condition code register. */
6335 if (REGNO (x) == SPARC_ICC_REG)
6337 /* We don't handle CC[X]_NOOVmode because they're not supposed
6339 if (GET_MODE (x) == CCmode)
6340 fputs ("%icc", file);
6341 else if (GET_MODE (x) == CCXmode)
6342 fputs ("%xcc", file);
6347 /* %fccN register */
6348 fputs (reg_names[REGNO (x)], file);
6351 /* Print the operand's address only. */
6352 output_address (XEXP (x, 0));
6355 /* In this case we need a register. Use %g0 if the
6356 operand is const0_rtx. */
6358 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
6360 fputs ("%g0", file);
6367 switch (GET_CODE (x))
6369 case IOR: fputs ("or", file); break;
6370 case AND: fputs ("and", file); break;
6371 case XOR: fputs ("xor", file); break;
6372 default: output_operand_lossage ("invalid %%A operand");
6377 switch (GET_CODE (x))
6379 case IOR: fputs ("orn", file); break;
6380 case AND: fputs ("andn", file); break;
6381 case XOR: fputs ("xnor", file); break;
6382 default: output_operand_lossage ("invalid %%B operand");
6386 /* These are used by the conditional move instructions. */
6390 enum rtx_code rc = GET_CODE (x);
6394 enum machine_mode mode = GET_MODE (XEXP (x, 0));
6395 if (mode == CCFPmode || mode == CCFPEmode)
6396 rc = reverse_condition_maybe_unordered (GET_CODE (x));
6398 rc = reverse_condition (GET_CODE (x));
6402 case NE: fputs ("ne", file); break;
6403 case EQ: fputs ("e", file); break;
6404 case GE: fputs ("ge", file); break;
6405 case GT: fputs ("g", file); break;
6406 case LE: fputs ("le", file); break;
6407 case LT: fputs ("l", file); break;
6408 case GEU: fputs ("geu", file); break;
6409 case GTU: fputs ("gu", file); break;
6410 case LEU: fputs ("leu", file); break;
6411 case LTU: fputs ("lu", file); break;
6412 case LTGT: fputs ("lg", file); break;
6413 case UNORDERED: fputs ("u", file); break;
6414 case ORDERED: fputs ("o", file); break;
6415 case UNLT: fputs ("ul", file); break;
6416 case UNLE: fputs ("ule", file); break;
6417 case UNGT: fputs ("ug", file); break;
6418 case UNGE: fputs ("uge", file); break;
6419 case UNEQ: fputs ("ue", file); break;
6420 default: output_operand_lossage (code == 'c'
6421 ? "invalid %%c operand"
6422 : "invalid %%C operand");
6427 /* These are used by the movr instruction pattern. */
6431 enum rtx_code rc = (code == 'd'
6432 ? reverse_condition (GET_CODE (x))
6436 case NE: fputs ("ne", file); break;
6437 case EQ: fputs ("e", file); break;
6438 case GE: fputs ("gez", file); break;
6439 case LT: fputs ("lz", file); break;
6440 case LE: fputs ("lez", file); break;
6441 case GT: fputs ("gz", file); break;
6442 default: output_operand_lossage (code == 'd'
6443 ? "invalid %%d operand"
6444 : "invalid %%D operand");
6451 /* Print a sign-extended character. */
6452 int i = trunc_int_for_mode (INTVAL (x), QImode);
6453 fprintf (file, "%d", i);
6458 /* Operand must be a MEM; write its address. */
6459 if (GET_CODE (x) != MEM)
6460 output_operand_lossage ("invalid %%f operand");
6461 output_address (XEXP (x, 0));
6465 /* Do nothing special. */
6469 /* Undocumented flag. */
6470 output_operand_lossage ("invalid operand output code");
6473 if (GET_CODE (x) == REG)
6474 fputs (reg_names[REGNO (x)], file);
6475 else if (GET_CODE (x) == MEM)
6478 /* Poor Sun assembler doesn't understand absolute addressing. */
6479 if (CONSTANT_P (XEXP (x, 0)))
6480 fputs ("%g0+", file);
6481 output_address (XEXP (x, 0));
6484 else if (GET_CODE (x) == HIGH)
6486 fputs ("%hi(", file);
6487 output_addr_const (file, XEXP (x, 0));
6490 else if (GET_CODE (x) == LO_SUM)
6492 print_operand (file, XEXP (x, 0), 0);
6493 if (TARGET_CM_MEDMID)
6494 fputs ("+%l44(", file);
6496 fputs ("+%lo(", file);
6497 output_addr_const (file, XEXP (x, 1));
6500 else if (GET_CODE (x) == CONST_DOUBLE
6501 && (GET_MODE (x) == VOIDmode
6502 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
6504 if (CONST_DOUBLE_HIGH (x) == 0)
6505 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
6506 else if (CONST_DOUBLE_HIGH (x) == -1
6507 && CONST_DOUBLE_LOW (x) < 0)
6508 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
6510 output_operand_lossage ("long long constant not a valid immediate operand");
6512 else if (GET_CODE (x) == CONST_DOUBLE)
6513 output_operand_lossage ("floating point constant not a valid immediate operand");
6514 else { output_addr_const (file, x); }
6517 /* Target hook for assembling integer objects. The sparc version has
6518 special handling for aligned DI-mode objects. */
6521 sparc_assemble_integer (x, size, aligned_p)
6526 /* ??? We only output .xword's for symbols and only then in environments
6527 where the assembler can handle them. */
6528 if (aligned_p && size == 8
6529 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
6533 assemble_integer_with_op ("\t.xword\t", x);
6538 assemble_aligned_integer (4, const0_rtx);
6539 assemble_aligned_integer (4, x);
6543 return default_assemble_integer (x, size, aligned_p);
6546 /* Return the value of a code used in the .proc pseudo-op that says
6547 what kind of result this function returns. For non-C types, we pick
6548 the closest C type. */
6550 #ifndef SHORT_TYPE_SIZE
6551 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6554 #ifndef INT_TYPE_SIZE
6555 #define INT_TYPE_SIZE BITS_PER_WORD
6558 #ifndef LONG_TYPE_SIZE
6559 #define LONG_TYPE_SIZE BITS_PER_WORD
6562 #ifndef LONG_LONG_TYPE_SIZE
6563 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6566 #ifndef FLOAT_TYPE_SIZE
6567 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6570 #ifndef DOUBLE_TYPE_SIZE
6571 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6574 #ifndef LONG_DOUBLE_TYPE_SIZE
6575 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6579 sparc_type_code (type)
6582 register unsigned long qualifiers = 0;
6583 register unsigned shift;
6585 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6586 setting more, since some assemblers will give an error for this. Also,
6587 we must be careful to avoid shifts of 32 bits or more to avoid getting
6588 unpredictable results. */
6590 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
6592 switch (TREE_CODE (type))
6598 qualifiers |= (3 << shift);
6603 qualifiers |= (2 << shift);
6607 case REFERENCE_TYPE:
6609 qualifiers |= (1 << shift);
6613 return (qualifiers | 8);
6616 case QUAL_UNION_TYPE:
6617 return (qualifiers | 9);
6620 return (qualifiers | 10);
6623 return (qualifiers | 16);
6626 /* If this is a range type, consider it to be the underlying
6628 if (TREE_TYPE (type) != 0)
6631 /* Carefully distinguish all the standard types of C,
6632 without messing up if the language is not C. We do this by
6633 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6634 look at both the names and the above fields, but that's redundant.
6635 Any type whose size is between two C types will be considered
6636 to be the wider of the two types. Also, we do not have a
6637 special code to use for "long long", so anything wider than
6638 long is treated the same. Note that we can't distinguish
6639 between "int" and "long" in this code if they are the same
6640 size, but that's fine, since neither can the assembler. */
6642 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
6643 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
6645 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
6646 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
6648 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
6649 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
6652 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
6655 /* If this is a range type, consider it to be the underlying
6657 if (TREE_TYPE (type) != 0)
6660 /* Carefully distinguish all the standard types of C,
6661 without messing up if the language is not C. */
6663 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
6664 return (qualifiers | 6);
6667 return (qualifiers | 7);
6669 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
6670 /* ??? We need to distinguish between double and float complex types,
6671 but I don't know how yet because I can't reach this code from
6672 existing front-ends. */
6673 return (qualifiers | 7); /* Who knows? */
6675 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
6676 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
6677 case FILE_TYPE: /* GNU Pascal FILE type. */
6678 case SET_TYPE: /* GNU Pascal SET type. */
6679 case LANG_TYPE: /* ? */
6683 abort (); /* Not a type! */
6690 /* Nested function support. */
6692 /* Emit RTL insns to initialize the variable parts of a trampoline.
6693 FNADDR is an RTX for the address of the function's pure code.
6694 CXT is an RTX for the static chain value for the function.
6696 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6697 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6698 (to store insns). This is a bit excessive. Perhaps a different
6699 mechanism would be better here.
6701 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6704 sparc_initialize_trampoline (tramp, fnaddr, cxt)
6705 rtx tramp, fnaddr, cxt;
6707 /* SPARC 32 bit trampoline:
6710 sethi %hi(static), %g2
6712 or %g2, %lo(static), %g2
6714 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6715 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6717 #ifdef TRANSFER_FROM_TRAMPOLINE
6718 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6719 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6723 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
6724 expand_binop (SImode, ior_optab,
6725 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
6726 size_int (10), 0, 1),
6727 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
6728 NULL_RTX, 1, OPTAB_DIRECT));
6731 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6732 expand_binop (SImode, ior_optab,
6733 expand_shift (RSHIFT_EXPR, SImode, cxt,
6734 size_int (10), 0, 1),
6735 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
6736 NULL_RTX, 1, OPTAB_DIRECT));
6739 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6740 expand_binop (SImode, ior_optab,
6741 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
6742 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
6743 NULL_RTX, 1, OPTAB_DIRECT));
6746 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6747 expand_binop (SImode, ior_optab,
6748 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
6749 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
6750 NULL_RTX, 1, OPTAB_DIRECT));
6752 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6753 aligned on a 16 byte boundary so one flush clears it all. */
6754 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
6755 if (sparc_cpu != PROCESSOR_ULTRASPARC
6756 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6757 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
6758 plus_constant (tramp, 8)))));
6761 /* The 64 bit version is simpler because it makes more sense to load the
6762 values as "immediate" data out of the trampoline. It's also easier since
6763 we can read the PC without clobbering a register. */
6766 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
6767 rtx tramp, fnaddr, cxt;
6769 #ifdef TRANSFER_FROM_TRAMPOLINE
6770 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
6771 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
6782 emit_move_insn (gen_rtx_MEM (SImode, tramp),
6783 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
6784 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
6785 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
6786 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
6787 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
6788 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
6789 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
6790 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
6791 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
6792 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
6794 if (sparc_cpu != PROCESSOR_ULTRASPARC
6795 && sparc_cpu != PROCESSOR_ULTRASPARC3)
6796 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
6799 /* Subroutines to support a flat (single) register window calling
6802 /* Single-register window sparc stack frames look like:
6804 Before call After call
6805 +-----------------------+ +-----------------------+
6807 mem | caller's temps. | | caller's temps. |
6809 +-----------------------+ +-----------------------+
6811 | arguments on stack. | | arguments on stack. |
6813 +-----------------------+FP+92->+-----------------------+
6814 | 6 words to save | | 6 words to save |
6815 | arguments passed | | arguments passed |
6816 | in registers, even | | in registers, even |
6817 | if not passed. | | if not passed. |
6818 SP+68->+-----------------------+FP+68->+-----------------------+
6819 | 1 word struct addr | | 1 word struct addr |
6820 +-----------------------+FP+64->+-----------------------+
6822 | 16 word reg save area | | 16 word reg save area |
6824 SP->+-----------------------+ FP->+-----------------------+
6826 | fp/alu reg moves |
6827 FP-16->+-----------------------+
6831 +-----------------------+
6833 | fp register save |
6835 +-----------------------+
6837 | gp register save |
6839 +-----------------------+
6841 | alloca allocations |
6843 +-----------------------+
6845 | arguments on stack |
6847 SP+92->+-----------------------+
6849 | arguments passed |
6850 | in registers, even |
6851 low | if not passed. |
6852 memory SP+68->+-----------------------+
6853 | 1 word struct addr |
6854 SP+64->+-----------------------+
6856 I 16 word reg save area |
6858 SP->+-----------------------+ */
6860 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6861 save masks, and offsets for the current function. */
6863 struct sparc_frame_info
6865 unsigned long total_size; /* # bytes that the entire frame takes up. */
6866 unsigned long var_size; /* # bytes that variables take up. */
6867 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6868 unsigned long extra_size; /* # bytes of extra gunk. */
6869 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6870 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6871 unsigned long gmask; /* Mask of saved gp registers. */
6872 unsigned long fmask; /* Mask of saved fp registers. */
6873 unsigned long reg_offset; /* Offset from new sp to store regs. */
6874 int initialized; /* Nonzero if frame size already calculated. */
6877 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6878 struct sparc_frame_info current_frame_info;
6880 /* Zero structure to initialize current_frame_info. */
6881 struct sparc_frame_info zero_frame_info;
6883 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6885 #define RETURN_ADDR_REGNUM 15
6886 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6887 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6889 #define MUST_SAVE_REGISTER(regno) \
6890 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6891 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6892 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6894 /* Return the bytes needed to compute the frame pointer from the current
6898 sparc_flat_compute_frame_size (size)
6899 int size; /* # of var. bytes allocated. */
6902 unsigned long total_size; /* # bytes that the entire frame takes up. */
6903 unsigned long var_size; /* # bytes that variables take up. */
6904 unsigned long args_size; /* # bytes that outgoing arguments take up. */
6905 unsigned long extra_size; /* # extra bytes. */
6906 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
6907 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
6908 unsigned long gmask; /* Mask of saved gp registers. */
6909 unsigned long fmask; /* Mask of saved fp registers. */
6910 unsigned long reg_offset; /* Offset to register save area. */
6911 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
6913 /* This is the size of the 16 word reg save area, 1 word struct addr
6914 area, and 4 word fp/alu register copy area. */
6915 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
6925 if (!leaf_function_p ())
6927 /* Also include the size needed for the 6 parameter registers. */
6928 args_size = current_function_outgoing_args_size + 24;
6930 total_size = var_size + args_size;
6932 /* Calculate space needed for gp registers. */
6933 for (regno = 1; regno <= 31; regno++)
6935 if (MUST_SAVE_REGISTER (regno))
6937 /* If we need to save two regs in a row, ensure there's room to bump
6938 up the address to align it to a doubleword boundary. */
6939 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
6941 if (gp_reg_size % 8 != 0)
6943 gp_reg_size += 2 * UNITS_PER_WORD;
6944 gmask |= 3 << regno;
6950 gp_reg_size += UNITS_PER_WORD;
6951 gmask |= 1 << regno;
6956 /* Calculate space needed for fp registers. */
6957 for (regno = 32; regno <= 63; regno++)
6959 if (regs_ever_live[regno] && !call_used_regs[regno])
6961 fp_reg_size += UNITS_PER_WORD;
6962 fmask |= 1 << (regno - 32);
6969 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
6970 /* Ensure save area is 8 byte aligned if we need it. */
6972 if (need_aligned_p && n != 0)
6974 total_size += 8 - n;
6975 reg_offset += 8 - n;
6977 total_size += gp_reg_size + fp_reg_size;
6980 /* If we must allocate a stack frame at all, we must also allocate
6981 room for register window spillage, so as to be binary compatible
6982 with libraries and operating systems that do not use -mflat. */
6984 total_size += extra_size;
6988 total_size = SPARC_STACK_ALIGN (total_size);
6990 /* Save other computed information. */
6991 current_frame_info.total_size = total_size;
6992 current_frame_info.var_size = var_size;
6993 current_frame_info.args_size = args_size;
6994 current_frame_info.extra_size = extra_size;
6995 current_frame_info.gp_reg_size = gp_reg_size;
6996 current_frame_info.fp_reg_size = fp_reg_size;
6997 current_frame_info.gmask = gmask;
6998 current_frame_info.fmask = fmask;
6999 current_frame_info.reg_offset = reg_offset;
7000 current_frame_info.initialized = reload_completed;
7002 /* Ok, we're done. */
7006 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7009 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7010 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7011 [BASE_REG+OFFSET] will always be a valid address.
7013 WORD_OP is either "st" for save, "ld" for restore.
7014 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7017 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
7018 doubleword_op, base_offset)
7020 const char *base_reg;
7021 unsigned int offset;
7022 unsigned long gmask;
7023 unsigned long fmask;
7024 const char *word_op;
7025 const char *doubleword_op;
7026 unsigned long base_offset;
7030 if (gmask == 0 && fmask == 0)
7033 /* Save registers starting from high to low. We've already saved the
7034 previous frame pointer and previous return address for the debugger's
7035 sake. The debugger allows us to not need a nop in the epilog if at least
7036 one register is reloaded in addition to return address. */
7040 for (regno = 1; regno <= 31; regno++)
7042 if ((gmask & (1L << regno)) != 0)
7044 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7046 /* We can save two registers in a row. If we're not at a
7047 double word boundary, move to one.
7048 sparc_flat_compute_frame_size ensures there's room to do
7050 if (offset % 8 != 0)
7051 offset += UNITS_PER_WORD;
7053 if (word_op[0] == 's')
7055 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7056 doubleword_op, reg_names[regno],
7058 if (dwarf2out_do_frame ())
7060 char *l = dwarf2out_cfi_label ();
7061 dwarf2out_reg_save (l, regno, offset + base_offset);
7063 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7067 fprintf (file, "\t%s\t[%s+%d], %s\n",
7068 doubleword_op, base_reg, offset,
7071 offset += 2 * UNITS_PER_WORD;
7076 if (word_op[0] == 's')
7078 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7079 word_op, reg_names[regno],
7081 if (dwarf2out_do_frame ())
7082 dwarf2out_reg_save ("", regno, offset + base_offset);
7085 fprintf (file, "\t%s\t[%s+%d], %s\n",
7086 word_op, base_reg, offset, reg_names[regno]);
7088 offset += UNITS_PER_WORD;
7096 for (regno = 32; regno <= 63; regno++)
7098 if ((fmask & (1L << (regno - 32))) != 0)
7100 if (word_op[0] == 's')
7102 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7103 word_op, reg_names[regno],
7105 if (dwarf2out_do_frame ())
7106 dwarf2out_reg_save ("", regno, offset + base_offset);
7109 fprintf (file, "\t%s\t[%s+%d], %s\n",
7110 word_op, base_reg, offset, reg_names[regno]);
7112 offset += UNITS_PER_WORD;
7118 /* Set up the stack and frame (if desired) for the function. */
7121 sparc_flat_function_prologue (file, size)
7125 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7126 unsigned long gmask = current_frame_info.gmask;
7128 sparc_output_scratch_registers (file);
7130 /* This is only for the human reader. */
7131 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7132 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7134 current_frame_info.var_size,
7135 current_frame_info.gp_reg_size / 4,
7136 current_frame_info.fp_reg_size / 4,
7137 current_function_outgoing_args_size,
7138 current_frame_info.extra_size);
7140 size = SPARC_STACK_ALIGN (size);
7141 size = (! current_frame_info.initialized
7142 ? sparc_flat_compute_frame_size (size)
7143 : current_frame_info.total_size);
7145 /* These cases shouldn't happen. Catch them now. */
7146 if (size == 0 && (gmask || current_frame_info.fmask))
7149 /* Allocate our stack frame by decrementing %sp.
7150 At present, the only algorithm gdb can use to determine if this is a
7151 flat frame is if we always set %i7 if we set %sp. This can be optimized
7152 in the future by putting in some sort of debugging information that says
7153 this is a `flat' function. However, there is still the case of debugging
7154 code without such debugging information (including cases where most fns
7155 have such info, but there is one that doesn't). So, always do this now
7156 so we don't get a lot of code out there that gdb can't handle.
7157 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7158 distinguish us from a non-flat function but there won't (and shouldn't)
7159 be any differences anyway. The return pc is saved (if necessary) right
7160 after %i7 so gdb won't have to look too far to find it. */
7163 unsigned int reg_offset = current_frame_info.reg_offset;
7164 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7165 static const char *const t1_str = "%g1";
7167 /* Things get a little tricky if local variables take up more than ~4096
7168 bytes and outgoing arguments take up more than ~4096 bytes. When that
7169 happens, the register save area can't be accessed from either end of
7170 the frame. Handle this by decrementing %sp to the start of the gp
7171 register save area, save the regs, update %i7, and then set %sp to its
7172 final value. Given that we only have one scratch register to play
7173 with it is the cheapest solution, and it helps gdb out as it won't
7174 slow down recognition of flat functions.
7175 Don't change the order of insns emitted here without checking with
7176 the gdb folk first. */
7178 /* Is the entire register save area offsettable from %sp? */
7179 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7183 fprintf (file, "\tadd\t%s, %d, %s\n",
7184 sp_str, (int) -size, sp_str);
7185 if (gmask & HARD_FRAME_POINTER_MASK)
7187 fprintf (file, "\tst\t%s, [%s+%d]\n",
7188 fp_str, sp_str, reg_offset);
7189 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7190 sp_str, (int) -size, fp_str, ASM_COMMENT_START);
7196 fprintf (file, "\tset\t");
7197 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7198 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7199 t1_str, sp_str, t1_str, sp_str);
7200 if (gmask & HARD_FRAME_POINTER_MASK)
7202 fprintf (file, "\tst\t%s, [%s+%d]\n",
7203 fp_str, sp_str, reg_offset);
7204 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7205 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7209 if (dwarf2out_do_frame ())
7211 char *l = dwarf2out_cfi_label ();
7212 if (gmask & HARD_FRAME_POINTER_MASK)
7214 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7215 reg_offset - 4 - size);
7216 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7219 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7221 if (gmask & RETURN_ADDR_MASK)
7223 fprintf (file, "\tst\t%s, [%s+%d]\n",
7224 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7225 if (dwarf2out_do_frame ())
7226 dwarf2out_return_save ("", reg_offset - size);
7229 sparc_flat_save_restore (file, sp_str, reg_offset,
7230 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7231 current_frame_info.fmask,
7232 "st", "std", -size);
7236 /* Subtract %sp in two steps, but make sure there is always a
7237 64 byte register save area, and %sp is properly aligned. */
7238 /* Amount to decrement %sp by, the first time. */
7239 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7240 /* Offset to register save area from %sp. */
7241 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset);
7245 fprintf (file, "\tadd\t%s, %d, %s\n",
7246 sp_str, (int) -size1, sp_str);
7247 if (gmask & HARD_FRAME_POINTER_MASK)
7249 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7250 fp_str, sp_str, (int) offset, sp_str, (int) -size1,
7251 fp_str, ASM_COMMENT_START);
7257 fprintf (file, "\tset\t");
7258 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7259 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7260 t1_str, sp_str, t1_str, sp_str);
7261 if (gmask & HARD_FRAME_POINTER_MASK)
7263 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7264 fp_str, sp_str, (int) offset, sp_str, t1_str,
7265 fp_str, ASM_COMMENT_START);
7269 if (dwarf2out_do_frame ())
7271 char *l = dwarf2out_cfi_label ();
7272 if (gmask & HARD_FRAME_POINTER_MASK)
7274 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7275 offset - 4 - size1);
7276 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7279 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7281 if (gmask & RETURN_ADDR_MASK)
7283 fprintf (file, "\tst\t%s, [%s+%d]\n",
7284 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset);
7285 if (dwarf2out_do_frame ())
7286 /* offset - size1 == reg_offset - size
7287 if reg_offset were updated above like offset. */
7288 dwarf2out_return_save ("", offset - size1);
7291 sparc_flat_save_restore (file, sp_str, offset,
7292 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7293 current_frame_info.fmask,
7294 "st", "std", -size1);
7295 fprintf (file, "\tset\t");
7296 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1);
7297 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n",
7298 t1_str, sp_str, t1_str, sp_str);
7299 if (dwarf2out_do_frame ())
7300 if (! (gmask & HARD_FRAME_POINTER_MASK))
7301 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
7305 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
7308 /* Do any necessary cleanup after a function to restore stack, frame,
7312 sparc_flat_function_epilogue (file, size)
7316 rtx epilogue_delay = current_function_epilogue_delay_list;
7317 int noepilogue = FALSE;
7319 /* This is only for the human reader. */
7320 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
7322 /* The epilogue does not depend on any registers, but the stack
7323 registers, so we assume that if we have 1 pending nop, it can be
7324 ignored, and 2 it must be filled (2 nops occur for integer
7325 multiply and divide). */
7327 size = SPARC_STACK_ALIGN (size);
7328 size = (!current_frame_info.initialized
7329 ? sparc_flat_compute_frame_size (size)
7330 : current_frame_info.total_size);
7332 if (size == 0 && epilogue_delay == 0)
7334 rtx insn = get_last_insn ();
7336 /* If the last insn was a BARRIER, we don't have to write any code
7337 because a jump (aka return) was put there. */
7338 if (GET_CODE (insn) == NOTE)
7339 insn = prev_nonnote_insn (insn);
7340 if (insn && GET_CODE (insn) == BARRIER)
7346 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset;
7347 unsigned HOST_WIDE_INT size1;
7348 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7349 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7350 static const char *const t1_str = "%g1";
7352 /* In the reload sequence, we don't need to fill the load delay
7353 slots for most of the loads, also see if we can fill the final
7354 delay slot if not otherwise filled by the reload sequence. */
7358 fprintf (file, "\tset\t");
7359 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7360 fprintf (file, ", %s\n", t1_str);
7363 if (frame_pointer_needed)
7366 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7367 fp_str, t1_str, sp_str, ASM_COMMENT_START);
7369 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7370 fp_str, (int) size, sp_str, ASM_COMMENT_START);
7373 /* Is the entire register save area offsettable from %sp? */
7374 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD)
7380 /* Restore %sp in two steps, but make sure there is always a
7381 64 byte register save area, and %sp is properly aligned. */
7382 /* Amount to increment %sp by, the first time. */
7383 size1 = ((reg_offset - 64 - 16) + 15) & -16;
7384 /* Offset to register save area from %sp. */
7385 reg_offset = size1 - reg_offset;
7387 fprintf (file, "\tset\t");
7388 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1);
7389 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n",
7390 t1_str, sp_str, t1_str, sp_str);
7393 /* We must restore the frame pointer and return address reg first
7394 because they are treated specially by the prologue output code. */
7395 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
7397 fprintf (file, "\tld\t[%s+%d], %s\n",
7398 sp_str, (int) reg_offset, fp_str);
7401 if (current_frame_info.gmask & RETURN_ADDR_MASK)
7403 fprintf (file, "\tld\t[%s+%d], %s\n",
7404 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]);
7408 /* Restore any remaining saved registers. */
7409 sparc_flat_save_restore (file, sp_str, reg_offset,
7410 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7411 current_frame_info.fmask,
7414 /* If we had to increment %sp in two steps, record it so the second
7415 restoration in the epilogue finishes up. */
7421 fprintf (file, "\tset\t");
7422 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size);
7423 fprintf (file, ", %s\n", t1_str);
7427 if (current_function_returns_struct)
7428 fprintf (file, "\tjmp\t%%o7+12\n");
7430 fprintf (file, "\tretl\n");
7432 /* If the only register saved is the return address, we need a
7433 nop, unless we have an instruction to put into it. Otherwise
7434 we don't since reloading multiple registers doesn't reference
7435 the register being loaded. */
7441 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
7444 else if (size > 4095)
7445 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7448 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str);
7451 fprintf (file, "\tnop\n");
7454 /* Reset state info for each function. */
7455 current_frame_info = zero_frame_info;
7457 sparc_output_deferred_case_vectors ();
7460 /* Define the number of delay slots needed for the function epilogue.
7462 On the sparc, we need a slot if either no stack has been allocated,
7463 or the only register saved is the return register. */
7466 sparc_flat_epilogue_delay_slots ()
7468 if (!current_frame_info.initialized)
7469 (void) sparc_flat_compute_frame_size (get_frame_size ());
7471 if (current_frame_info.total_size == 0)
7477 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7478 Any single length instruction which doesn't reference the stack or frame
7482 sparc_flat_eligible_for_epilogue_delay (trial, slot)
7484 int slot ATTRIBUTE_UNUSED;
7486 rtx pat = PATTERN (trial);
7488 if (get_attr_length (trial) != 1)
7491 if (! reg_mentioned_p (stack_pointer_rtx, pat)
7492 && ! reg_mentioned_p (frame_pointer_rtx, pat))
7498 /* Adjust the cost of a scheduling dependency. Return the new cost of
7499 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7502 supersparc_adjust_cost (insn, link, dep_insn, cost)
7508 enum attr_type insn_type;
7510 if (! recog_memoized (insn))
7513 insn_type = get_attr_type (insn);
7515 if (REG_NOTE_KIND (link) == 0)
7517 /* Data dependency; DEP_INSN writes a register that INSN reads some
7520 /* if a load, then the dependence must be on the memory address;
7521 add an extra "cycle". Note that the cost could be two cycles
7522 if the reg was written late in an instruction group; we ca not tell
7524 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7527 /* Get the delay only if the address of the store is the dependence. */
7528 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7530 rtx pat = PATTERN(insn);
7531 rtx dep_pat = PATTERN (dep_insn);
7533 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7534 return cost; /* This should not happen! */
7536 /* The dependency between the two instructions was on the data that
7537 is being stored. Assume that this implies that the address of the
7538 store is not dependent. */
7539 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7542 return cost + 3; /* An approximation. */
7545 /* A shift instruction cannot receive its data from an instruction
7546 in the same cycle; add a one cycle penalty. */
7547 if (insn_type == TYPE_SHIFT)
7548 return cost + 3; /* Split before cascade into shift. */
7552 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7553 INSN writes some cycles later. */
7555 /* These are only significant for the fpu unit; writing a fp reg before
7556 the fpu has finished with it stalls the processor. */
7558 /* Reusing an integer register causes no problems. */
7559 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7567 hypersparc_adjust_cost (insn, link, dep_insn, cost)
7573 enum attr_type insn_type, dep_type;
7574 rtx pat = PATTERN(insn);
7575 rtx dep_pat = PATTERN (dep_insn);
7577 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7580 insn_type = get_attr_type (insn);
7581 dep_type = get_attr_type (dep_insn);
7583 switch (REG_NOTE_KIND (link))
7586 /* Data dependency; DEP_INSN writes a register that INSN reads some
7593 /* Get the delay iff the address of the store is the dependence. */
7594 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7597 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7604 /* If a load, then the dependence must be on the memory address. If
7605 the addresses aren't equal, then it might be a false dependency */
7606 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7608 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7609 || GET_CODE (SET_DEST (dep_pat)) != MEM
7610 || GET_CODE (SET_SRC (pat)) != MEM
7611 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7612 XEXP (SET_SRC (pat), 0)))
7620 /* Compare to branch latency is 0. There is no benefit from
7621 separating compare and branch. */
7622 if (dep_type == TYPE_COMPARE)
7624 /* Floating point compare to branch latency is less than
7625 compare to conditional move. */
7626 if (dep_type == TYPE_FPCMP)
7635 /* Anti-dependencies only penalize the fpu unit. */
7636 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7648 sparc_adjust_cost(insn, link, dep, cost)
7656 case PROCESSOR_SUPERSPARC:
7657 cost = supersparc_adjust_cost (insn, link, dep, cost);
7659 case PROCESSOR_HYPERSPARC:
7660 case PROCESSOR_SPARCLITE86X:
7661 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7670 sparc_sched_init (dump, sched_verbose, max_ready)
7671 FILE *dump ATTRIBUTE_UNUSED;
7672 int sched_verbose ATTRIBUTE_UNUSED;
7673 int max_ready ATTRIBUTE_UNUSED;
7678 sparc_use_dfa_pipeline_interface ()
7680 if ((1 << sparc_cpu) &
7681 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7682 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7683 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7684 (1 << PROCESSOR_ULTRASPARC3)))
7690 sparc_use_sched_lookahead ()
7692 if (sparc_cpu == PROCESSOR_ULTRASPARC
7693 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7695 if ((1 << sparc_cpu) &
7696 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7697 (1 << PROCESSOR_SPARCLITE86X)))
7710 /* Assume V9 processors are capable of at least dual-issue. */
7712 case PROCESSOR_SUPERSPARC:
7714 case PROCESSOR_HYPERSPARC:
7715 case PROCESSOR_SPARCLITE86X:
7717 case PROCESSOR_ULTRASPARC:
7718 case PROCESSOR_ULTRASPARC3:
7727 register rtx pat = PATTERN (insn);
7729 switch (GET_CODE (SET_SRC (pat)))
7731 /* Load and some shift instructions zero extend. */
7734 /* sethi clears the high bits */
7736 /* LO_SUM is used with sethi. sethi cleared the high
7737 bits and the values used with lo_sum are positive */
7739 /* Store flag stores 0 or 1 */
7749 rtx op0 = XEXP (SET_SRC (pat), 0);
7750 rtx op1 = XEXP (SET_SRC (pat), 1);
7751 if (GET_CODE (op1) == CONST_INT)
7752 return INTVAL (op1) >= 0;
7753 if (GET_CODE (op0) != REG)
7755 if (sparc_check_64 (op0, insn) == 1)
7757 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7762 rtx op0 = XEXP (SET_SRC (pat), 0);
7763 rtx op1 = XEXP (SET_SRC (pat), 1);
7764 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7766 if (GET_CODE (op1) == CONST_INT)
7767 return INTVAL (op1) >= 0;
7768 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7771 return GET_MODE (SET_SRC (pat)) == SImode;
7772 /* Positive integers leave the high bits zero. */
7774 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7776 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7779 return - (GET_MODE (SET_SRC (pat)) == SImode);
7781 return sparc_check_64 (SET_SRC (pat), insn);
7787 /* We _ought_ to have only one kind per function, but... */
7788 static GTY(()) rtx sparc_addr_diff_list;
7789 static GTY(()) rtx sparc_addr_list;
7792 sparc_defer_case_vector (lab, vec, diff)
7796 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7798 sparc_addr_diff_list
7799 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7801 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7805 sparc_output_addr_vec (vec)
7808 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7809 int idx, vlen = XVECLEN (body, 0);
7811 #ifdef ASM_OUTPUT_ADDR_VEC_START
7812 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7815 #ifdef ASM_OUTPUT_CASE_LABEL
7816 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7819 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7822 for (idx = 0; idx < vlen; idx++)
7824 ASM_OUTPUT_ADDR_VEC_ELT
7825 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7828 #ifdef ASM_OUTPUT_ADDR_VEC_END
7829 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7834 sparc_output_addr_diff_vec (vec)
7837 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7838 rtx base = XEXP (XEXP (body, 0), 0);
7839 int idx, vlen = XVECLEN (body, 1);
7841 #ifdef ASM_OUTPUT_ADDR_VEC_START
7842 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7845 #ifdef ASM_OUTPUT_CASE_LABEL
7846 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7849 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7852 for (idx = 0; idx < vlen; idx++)
7854 ASM_OUTPUT_ADDR_DIFF_ELT
7857 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7858 CODE_LABEL_NUMBER (base));
7861 #ifdef ASM_OUTPUT_ADDR_VEC_END
7862 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7867 sparc_output_deferred_case_vectors ()
7872 if (sparc_addr_list == NULL_RTX
7873 && sparc_addr_diff_list == NULL_RTX)
7876 /* Align to cache line in the function's code section. */
7877 function_section (current_function_decl);
7879 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7881 ASM_OUTPUT_ALIGN (asm_out_file, align);
7883 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7884 sparc_output_addr_vec (XEXP (t, 0));
7885 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7886 sparc_output_addr_diff_vec (XEXP (t, 0));
7888 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7891 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7892 unknown. Return 1 if the high bits are zero, -1 if the register is
7895 sparc_check_64 (x, insn)
7898 /* If a register is set only once it is safe to ignore insns this
7899 code does not know how to handle. The loop will either recognize
7900 the single set and return the correct value or fail to recognize
7905 if (GET_CODE (x) != REG)
7908 if (GET_MODE (x) == DImode)
7909 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7911 if (flag_expensive_optimizations
7912 && REG_N_SETS (REGNO (y)) == 1)
7918 insn = get_last_insn_anywhere ();
7923 while ((insn = PREV_INSN (insn)))
7925 switch (GET_CODE (insn))
7938 rtx pat = PATTERN (insn);
7939 if (GET_CODE (pat) != SET)
7941 if (rtx_equal_p (x, SET_DEST (pat)))
7942 return set_extends (insn);
7943 if (y && rtx_equal_p (y, SET_DEST (pat)))
7944 return set_extends (insn);
7945 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7954 sparc_v8plus_shift (operands, insn, opcode)
7959 static char asm_code[60];
7961 if (GET_CODE (operands[3]) == SCRATCH)
7962 operands[3] = operands[0];
7963 if (GET_CODE (operands[1]) == CONST_INT)
7965 output_asm_insn ("mov\t%1, %3", operands);
7969 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7970 if (sparc_check_64 (operands[1], insn) <= 0)
7971 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7972 output_asm_insn ("or\t%L1, %3, %3", operands);
7975 strcpy(asm_code, opcode);
7976 if (which_alternative != 2)
7977 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7979 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7982 /* Output rtl to increment the profiler label LABELNO
7983 for profiling a function entry. */
7986 sparc_profile_hook (labelno)
7992 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7993 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7994 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7996 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7999 #ifdef OBJECT_FORMAT_ELF
8001 sparc_elf_asm_named_section (name, flags)
8005 if (flags & SECTION_MERGE)
8007 /* entsize cannot be expressed in this section attributes
8009 default_elf_asm_named_section (name, flags);
8013 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8015 if (!(flags & SECTION_DEBUG))
8016 fputs (",#alloc", asm_out_file);
8017 if (flags & SECTION_WRITE)
8018 fputs (",#write", asm_out_file);
8019 if (flags & SECTION_CODE)
8020 fputs (",#execinstr", asm_out_file);
8022 /* ??? Handle SECTION_BSS. */
8024 fputc ('\n', asm_out_file);
8026 #endif /* OBJECT_FORMAT_ELF */
8028 /* ??? Similar to the standard section selection, but force reloc-y-ness
8029 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8030 pretending PIC always on), but that's what the old code did. */
8033 sparc_aout_select_section (t, reloc, align)
8036 unsigned HOST_WIDE_INT align;
8038 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8041 /* Use text section for a constant unless we need more alignment than
8045 sparc_aout_select_rtx_section (mode, x, align)
8046 enum machine_mode mode;
8048 unsigned HOST_WIDE_INT align;
8050 if (align <= MAX_TEXT_ALIGN
8051 && ! (flag_pic && (symbolic_operand (x, mode)
8052 || SUNOS4_SHARED_LIBRARIES)))
8053 readonly_data_section ();
8059 sparc_extra_constraint_check (op, c, strict)
8067 && (c == 'T' || c == 'U'))
8073 return fp_sethi_p (op);
8076 return fp_mov_p (op);
8079 return fp_high_losum_p (op);
8083 || (GET_CODE (op) == REG
8084 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8085 || reg_renumber[REGNO (op)] >= 0)))
8086 return register_ok_for_ldd (op);
8098 /* Our memory extra constraints have to emulate the
8099 behavior of 'm' and 'o' in order for reload to work
8101 if (GET_CODE (op) == MEM)
8104 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8106 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8111 reload_ok_mem = (reload_in_progress
8112 && GET_CODE (op) == REG
8113 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8114 && reg_renumber [REGNO (op)] < 0);
8117 return reload_ok_mem;
8120 /* ??? This duplicates information provided to the compiler by the
8121 ??? scheduler description. Some day, teach genautomata to output
8122 ??? the latencies and then CSE will just use that. */
8125 sparc_rtx_costs (x, code, outer_code)
8127 enum rtx_code code, outer_code;
8131 case PLUS: case MINUS: case ABS: case NEG:
8132 case FLOAT: case UNSIGNED_FLOAT:
8133 case FIX: case UNSIGNED_FIX:
8134 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8135 if (FLOAT_MODE_P (GET_MODE (x)))
8139 case PROCESSOR_ULTRASPARC:
8140 case PROCESSOR_ULTRASPARC3:
8141 return COSTS_N_INSNS (4);
8143 case PROCESSOR_SUPERSPARC:
8144 return COSTS_N_INSNS (3);
8146 case PROCESSOR_CYPRESS:
8147 return COSTS_N_INSNS (5);
8149 case PROCESSOR_HYPERSPARC:
8150 case PROCESSOR_SPARCLITE86X:
8152 return COSTS_N_INSNS (1);
8156 return COSTS_N_INSNS (1);
8161 case PROCESSOR_ULTRASPARC:
8162 if (GET_MODE (x) == SFmode)
8163 return COSTS_N_INSNS (13);
8165 return COSTS_N_INSNS (23);
8167 case PROCESSOR_ULTRASPARC3:
8168 if (GET_MODE (x) == SFmode)
8169 return COSTS_N_INSNS (20);
8171 return COSTS_N_INSNS (29);
8173 case PROCESSOR_SUPERSPARC:
8174 return COSTS_N_INSNS (12);
8176 case PROCESSOR_CYPRESS:
8177 return COSTS_N_INSNS (63);
8179 case PROCESSOR_HYPERSPARC:
8180 case PROCESSOR_SPARCLITE86X:
8181 return COSTS_N_INSNS (17);
8184 return COSTS_N_INSNS (30);
8188 if (FLOAT_MODE_P (GET_MODE (x)))
8192 case PROCESSOR_ULTRASPARC:
8193 case PROCESSOR_ULTRASPARC3:
8194 return COSTS_N_INSNS (1);
8196 case PROCESSOR_SUPERSPARC:
8197 return COSTS_N_INSNS (3);
8199 case PROCESSOR_CYPRESS:
8200 return COSTS_N_INSNS (5);
8202 case PROCESSOR_HYPERSPARC:
8203 case PROCESSOR_SPARCLITE86X:
8205 return COSTS_N_INSNS (1);
8209 /* ??? Maybe mark integer compares as zero cost on
8210 ??? all UltraSPARC processors because the result
8211 ??? can be bypassed to a branch in the same group. */
8213 return COSTS_N_INSNS (1);
8216 if (FLOAT_MODE_P (GET_MODE (x)))
8220 case PROCESSOR_ULTRASPARC:
8221 case PROCESSOR_ULTRASPARC3:
8222 return COSTS_N_INSNS (4);
8224 case PROCESSOR_SUPERSPARC:
8225 return COSTS_N_INSNS (3);
8227 case PROCESSOR_CYPRESS:
8228 return COSTS_N_INSNS (7);
8230 case PROCESSOR_HYPERSPARC:
8231 case PROCESSOR_SPARCLITE86X:
8232 return COSTS_N_INSNS (1);
8235 return COSTS_N_INSNS (5);
8239 /* The latency is actually variable for Ultra-I/II
8240 And if one of the inputs have a known constant
8241 value, we could calculate this precisely.
8243 However, for that to be useful we would need to
8244 add some machine description changes which would
8245 make sure small constants ended up in rs1 of the
8246 multiply instruction. This is because the multiply
8247 latency is determined by the number of clear (or
8248 set if the value is negative) bits starting from
8249 the most significant bit of the first input.
8251 The algorithm for computing num_cycles of a multiply
8255 highest_bit = highest_clear_bit(rs1);
8257 highest_bit = highest_set_bit(rs1);
8260 num_cycles = 4 + ((highest_bit - 3) / 2);
8262 If we did that we would have to also consider register
8263 allocation issues that would result from forcing such
8264 a value into a register.
8266 There are other similar tricks we could play if we
8267 knew, for example, that one input was an array index.
8269 Since we do not play any such tricks currently the
8270 safest thing to do is report the worst case latency. */
8271 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8272 return (GET_MODE (x) == DImode ?
8273 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8275 /* Multiply latency on Ultra-III, fortunately, is constant. */
8276 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8277 return COSTS_N_INSNS (6);
8279 if (sparc_cpu == PROCESSOR_HYPERSPARC
8280 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8281 return COSTS_N_INSNS (17);
8283 return (TARGET_HARD_MUL
8285 : COSTS_N_INSNS (25));
8291 if (FLOAT_MODE_P (GET_MODE (x)))
8295 case PROCESSOR_ULTRASPARC:
8296 if (GET_MODE (x) == SFmode)
8297 return COSTS_N_INSNS (13);
8299 return COSTS_N_INSNS (23);
8301 case PROCESSOR_ULTRASPARC3:
8302 if (GET_MODE (x) == SFmode)
8303 return COSTS_N_INSNS (17);
8305 return COSTS_N_INSNS (20);
8307 case PROCESSOR_SUPERSPARC:
8308 if (GET_MODE (x) == SFmode)
8309 return COSTS_N_INSNS (6);
8311 return COSTS_N_INSNS (9);
8313 case PROCESSOR_HYPERSPARC:
8314 case PROCESSOR_SPARCLITE86X:
8315 if (GET_MODE (x) == SFmode)
8316 return COSTS_N_INSNS (8);
8318 return COSTS_N_INSNS (12);
8321 return COSTS_N_INSNS (7);
8325 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8326 return (GET_MODE (x) == DImode ?
8327 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8328 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8329 return (GET_MODE (x) == DImode ?
8330 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8331 return COSTS_N_INSNS (25);
8334 /* Conditional moves. */
8337 case PROCESSOR_ULTRASPARC:
8338 return COSTS_N_INSNS (2);
8340 case PROCESSOR_ULTRASPARC3:
8341 if (FLOAT_MODE_P (GET_MODE (x)))
8342 return COSTS_N_INSNS (3);
8344 return COSTS_N_INSNS (2);
8347 return COSTS_N_INSNS (1);
8351 /* If outer-code is SIGN/ZERO extension we have to subtract
8352 out COSTS_N_INSNS (1) from whatever we return in determining
8356 case PROCESSOR_ULTRASPARC:
8357 if (outer_code == ZERO_EXTEND)
8358 return COSTS_N_INSNS (1);
8360 return COSTS_N_INSNS (2);
8362 case PROCESSOR_ULTRASPARC3:
8363 if (outer_code == ZERO_EXTEND)
8365 if (GET_MODE (x) == QImode
8366 || GET_MODE (x) == HImode
8367 || outer_code == SIGN_EXTEND)
8368 return COSTS_N_INSNS (2);
8370 return COSTS_N_INSNS (1);
8374 /* This handles sign extension (3 cycles)
8375 and everything else (2 cycles). */
8376 return COSTS_N_INSNS (2);
8379 case PROCESSOR_SUPERSPARC:
8380 if (FLOAT_MODE_P (GET_MODE (x))
8381 || outer_code == ZERO_EXTEND
8382 || outer_code == SIGN_EXTEND)
8383 return COSTS_N_INSNS (0);
8385 return COSTS_N_INSNS (1);
8387 case PROCESSOR_TSC701:
8388 if (outer_code == ZERO_EXTEND
8389 || outer_code == SIGN_EXTEND)
8390 return COSTS_N_INSNS (2);
8392 return COSTS_N_INSNS (3);
8394 case PROCESSOR_CYPRESS:
8395 if (outer_code == ZERO_EXTEND
8396 || outer_code == SIGN_EXTEND)
8397 return COSTS_N_INSNS (1);
8399 return COSTS_N_INSNS (2);
8401 case PROCESSOR_HYPERSPARC:
8402 case PROCESSOR_SPARCLITE86X:
8404 if (outer_code == ZERO_EXTEND
8405 || outer_code == SIGN_EXTEND)
8406 return COSTS_N_INSNS (0);
8408 return COSTS_N_INSNS (1);
8412 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8425 if (GET_MODE (x) == DImode)
8426 if ((XINT (x, 3) == 0
8427 && (unsigned) XINT (x, 2) < 0x1000)
8428 || (XINT (x, 3) == -1
8430 && XINT (x, 2) >= -0x1000))
8439 /* If we are referencing a function make the SYMBOL_REF special. In
8440 the Embedded Medium/Anywhere code model, %g4 points to the data
8441 segment so we must not add it to function addresses. */
8444 sparc_encode_section_info (decl, first)
8446 int first ATTRIBUTE_UNUSED;
8448 if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL)
8449 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8452 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8453 Used for C++ multiple inheritance. */
8456 sparc_output_mi_thunk (file, thunk_fndecl, delta, function)
8458 tree thunk_fndecl ATTRIBUTE_UNUSED;
8459 HOST_WIDE_INT delta;
8462 rtx this, insn, funexp, delta_rtx, tmp;
8464 reload_completed = 1;
8466 current_function_uses_only_leaf_regs = 1;
8468 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8470 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8471 returns a structure, the structure return pointer is there instead. */
8472 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
8473 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8475 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8477 /* Add DELTA. When possible use a plain add, otherwise load it into
8478 a register first. */
8479 delta_rtx = GEN_INT (delta);
8480 if (!SPARC_SIMM13_P (delta))
8482 rtx scratch = gen_rtx_REG (Pmode, 1);
8484 sparc_emit_set_const64 (scratch, delta_rtx);
8486 sparc_emit_set_const32 (scratch, delta_rtx);
8487 delta_rtx = scratch;
8490 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8491 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8493 /* Generate a tail call to the target function. */
8494 if (! TREE_USED (function))
8496 assemble_external (function);
8497 TREE_USED (function) = 1;
8499 funexp = XEXP (DECL_RTL (function), 0);
8500 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8501 insn = emit_call_insn (gen_sibcall (funexp));
8502 SIBLING_CALL_P (insn) = 1;
8505 /* Run just enough of rest_of_compilation to get the insns emitted.
8506 There's not really enough bulk here to make other passes such as
8507 instruction scheduling worth while. Note that use_thunk calls
8508 assemble_start_function and assemble_end_function. */
8509 insn = get_insns ();
8510 shorten_branches (insn);
8511 final_start_function (insn, file, 1);
8512 final (insn, file, 1, 0);
8513 final_end_function ();
8515 reload_completed = 0;
8519 #include "gt-sparc.h"