1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static void scan_record_type (tree, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static rtx sparc_builtin_saveregs (void);
152 static int epilogue_renumber (rtx *, int);
153 static bool sparc_assemble_integer (rtx, unsigned int, int);
154 static int set_extends (rtx);
155 static void output_restore_regs (FILE *, int);
156 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
157 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_function_epilogue (FILE *, HOST_WIDE_INT, int);
159 static void sparc_function_prologue (FILE *, HOST_WIDE_INT, int);
160 #ifdef OBJECT_FORMAT_ELF
161 static void sparc_elf_asm_named_section (const char *, unsigned int);
163 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
165 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
166 unsigned HOST_WIDE_INT)
169 static int sparc_adjust_cost (rtx, rtx, rtx, int);
170 static int sparc_issue_rate (void);
171 static void sparc_sched_init (FILE *, int, int);
172 static int sparc_use_dfa_pipeline_interface (void);
173 static int sparc_use_sched_lookahead (void);
175 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
176 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
177 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
178 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
179 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
181 static bool sparc_function_ok_for_sibcall (tree, tree);
182 static void sparc_init_libfuncs (void);
183 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
184 HOST_WIDE_INT, tree);
185 static struct machine_function * sparc_init_machine_status (void);
186 static bool sparc_cannot_force_const_mem (rtx);
187 static rtx sparc_tls_get_addr (void);
188 static rtx sparc_tls_got (void);
189 static const char *get_some_local_dynamic_name (void);
190 static int get_some_local_dynamic_name_1 (rtx *, void *);
191 static bool sparc_rtx_costs (rtx, int, int, int *);
192 static bool sparc_promote_prototypes (tree);
193 static rtx sparc_struct_value_rtx (tree, int);
194 static bool sparc_return_in_memory (tree, tree);
195 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
197 /* Option handling. */
199 /* Code model option as passed by user. */
200 const char *sparc_cmodel_string;
202 enum cmodel sparc_cmodel;
204 char sparc_hard_reg_printed[8];
206 struct sparc_cpu_select sparc_select[] =
208 /* switch name, tune arch */
209 { (char *)0, "default", 1, 1 },
210 { (char *)0, "-mcpu=", 1, 1 },
211 { (char *)0, "-mtune=", 1, 0 },
215 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
216 enum processor_type sparc_cpu;
218 /* Initialize the GCC target structure. */
220 /* The sparc default is to use .half rather than .short for aligned
221 HI objects. Use .word instead of .long on non-ELF systems. */
222 #undef TARGET_ASM_ALIGNED_HI_OP
223 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
224 #ifndef OBJECT_FORMAT_ELF
225 #undef TARGET_ASM_ALIGNED_SI_OP
226 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
229 #undef TARGET_ASM_UNALIGNED_HI_OP
230 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
231 #undef TARGET_ASM_UNALIGNED_SI_OP
232 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
233 #undef TARGET_ASM_UNALIGNED_DI_OP
234 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
236 /* The target hook has to handle DI-mode values. */
237 #undef TARGET_ASM_INTEGER
238 #define TARGET_ASM_INTEGER sparc_assemble_integer
240 #undef TARGET_ASM_FUNCTION_PROLOGUE
241 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
242 #undef TARGET_ASM_FUNCTION_EPILOGUE
243 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
247 #undef TARGET_SCHED_ISSUE_RATE
248 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
249 #undef TARGET_SCHED_INIT
250 #define TARGET_SCHED_INIT sparc_sched_init
251 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
252 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
253 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
254 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
256 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
257 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
259 #undef TARGET_INIT_LIBFUNCS
260 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
263 #undef TARGET_HAVE_TLS
264 #define TARGET_HAVE_TLS true
266 #undef TARGET_CANNOT_FORCE_CONST_MEM
267 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
269 #undef TARGET_ASM_OUTPUT_MI_THUNK
270 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
271 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
272 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
274 #undef TARGET_RTX_COSTS
275 #define TARGET_RTX_COSTS sparc_rtx_costs
276 #undef TARGET_ADDRESS_COST
277 #define TARGET_ADDRESS_COST hook_int_rtx_0
279 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
280 for outgoing function arguments.
281 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
282 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
284 #undef TARGET_PROMOTE_FUNCTION_ARGS
285 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
287 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
288 for the return value of functions. If this macro is defined, FUNCTION_VALUE
289 must perform the same promotions done by PROMOTE_MODE.
290 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
291 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
293 #undef TARGET_PROMOTE_FUNCTION_RETURN
294 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
296 #undef TARGET_PROMOTE_PROTOTYPES
297 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
299 #undef TARGET_STRUCT_VALUE_RTX
300 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
301 #undef TARGET_RETURN_IN_MEMORY
302 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
304 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
305 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
306 #undef TARGET_STRICT_ARGUMENT_NAMING
307 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
309 struct gcc_target targetm = TARGET_INITIALIZER;
311 /* Validate and override various options, and do some machine dependent
315 sparc_override_options (void)
317 static struct code_model {
318 const char *const name;
320 } const cmodels[] = {
322 { "medlow", CM_MEDLOW },
323 { "medmid", CM_MEDMID },
324 { "medany", CM_MEDANY },
325 { "embmedany", CM_EMBMEDANY },
328 const struct code_model *cmodel;
329 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
330 static struct cpu_default {
332 const char *const name;
333 } const cpu_default[] = {
334 /* There must be one entry here for each TARGET_CPU value. */
335 { TARGET_CPU_sparc, "cypress" },
336 { TARGET_CPU_sparclet, "tsc701" },
337 { TARGET_CPU_sparclite, "f930" },
338 { TARGET_CPU_v8, "v8" },
339 { TARGET_CPU_hypersparc, "hypersparc" },
340 { TARGET_CPU_sparclite86x, "sparclite86x" },
341 { TARGET_CPU_supersparc, "supersparc" },
342 { TARGET_CPU_v9, "v9" },
343 { TARGET_CPU_ultrasparc, "ultrasparc" },
344 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
347 const struct cpu_default *def;
348 /* Table of values for -m{cpu,tune}=. */
349 static struct cpu_table {
350 const char *const name;
351 const enum processor_type processor;
354 } const cpu_table[] = {
355 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
356 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
357 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
358 /* TI TMS390Z55 supersparc */
359 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
360 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
361 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
362 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
363 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
364 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
365 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
366 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
368 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
370 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
371 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
372 /* TI ultrasparc I, II, IIi */
373 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
374 /* Although insns using %y are deprecated, it is a clear win on current
376 |MASK_DEPRECATED_V8_INSNS},
377 /* TI ultrasparc III */
378 /* ??? Check if %y issue still holds true in ultra3. */
379 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
382 const struct cpu_table *cpu;
383 const struct sparc_cpu_select *sel;
386 #ifndef SPARC_BI_ARCH
387 /* Check for unsupported architecture size. */
388 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
389 error ("%s is not supported by this configuration",
390 DEFAULT_ARCH32_P ? "-m64" : "-m32");
393 /* We force all 64bit archs to use 128 bit long double */
394 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
396 error ("-mlong-double-64 not allowed with -m64");
397 target_flags |= MASK_LONG_DOUBLE_128;
400 /* Code model selection. */
401 sparc_cmodel = SPARC_DEFAULT_CMODEL;
405 sparc_cmodel = CM_32;
408 if (sparc_cmodel_string != NULL)
412 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
413 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
415 if (cmodel->name == NULL)
416 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
418 sparc_cmodel = cmodel->value;
421 error ("-mcmodel= is not supported on 32 bit systems");
424 fpu = TARGET_FPU; /* save current -mfpu status */
426 /* Set the default CPU. */
427 for (def = &cpu_default[0]; def->name; ++def)
428 if (def->cpu == TARGET_CPU_DEFAULT)
432 sparc_select[0].string = def->name;
434 for (sel = &sparc_select[0]; sel->name; ++sel)
438 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
439 if (! strcmp (sel->string, cpu->name))
442 sparc_cpu = cpu->processor;
446 target_flags &= ~cpu->disable;
447 target_flags |= cpu->enable;
453 error ("bad value (%s) for %s switch", sel->string, sel->name);
457 /* If -mfpu or -mno-fpu was explicitly used, don't override with
458 the processor default. Clear MASK_FPU_SET to avoid confusing
459 the reverse mapping from switch values to names. */
462 target_flags = (target_flags & ~MASK_FPU) | fpu;
463 target_flags &= ~MASK_FPU_SET;
466 /* Don't allow -mvis if FPU is disabled. */
468 target_flags &= ~MASK_VIS;
470 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
472 -m64 also implies v9. */
473 if (TARGET_VIS || TARGET_ARCH64)
475 target_flags |= MASK_V9;
476 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
479 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
480 if (TARGET_V9 && TARGET_ARCH32)
481 target_flags |= MASK_DEPRECATED_V8_INSNS;
483 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
484 if (! TARGET_V9 || TARGET_ARCH64)
485 target_flags &= ~MASK_V8PLUS;
487 /* Don't use stack biasing in 32 bit mode. */
489 target_flags &= ~MASK_STACK_BIAS;
491 /* Supply a default value for align_functions. */
492 if (align_functions == 0
493 && (sparc_cpu == PROCESSOR_ULTRASPARC
494 || sparc_cpu == PROCESSOR_ULTRASPARC3))
495 align_functions = 32;
497 /* Validate PCC_STRUCT_RETURN. */
498 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
499 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
501 /* Only use .uaxword when compiling for a 64-bit target. */
503 targetm.asm_out.unaligned_op.di = NULL;
505 /* Do various machine dependent initializations. */
508 /* Set up function hooks. */
509 init_machine_status = sparc_init_machine_status;
512 /* Miscellaneous utilities. */
514 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
515 or branch on register contents instructions. */
518 v9_regcmp_p (enum rtx_code code)
520 return (code == EQ || code == NE || code == GE || code == LT
521 || code == LE || code == GT);
525 /* Operand constraints. */
527 /* Return nonzero only if OP is a register of mode MODE,
531 reg_or_0_operand (rtx op, enum machine_mode mode)
533 if (register_operand (op, mode))
535 if (op == const0_rtx)
537 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
538 && CONST_DOUBLE_HIGH (op) == 0
539 && CONST_DOUBLE_LOW (op) == 0)
541 if (fp_zero_operand (op, mode))
546 /* Return nonzero only if OP is const1_rtx. */
549 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
551 return op == const1_rtx;
554 /* Nonzero if OP is a floating point value with value 0.0. */
557 fp_zero_operand (rtx op, enum machine_mode mode)
559 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
561 return op == CONST0_RTX (mode);
564 /* Nonzero if OP is a register operand in floating point register. */
567 fp_register_operand (rtx op, enum machine_mode mode)
569 if (! register_operand (op, mode))
571 if (GET_CODE (op) == SUBREG)
572 op = SUBREG_REG (op);
573 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
576 /* Nonzero if OP is a floating point constant which can
577 be loaded into an integer register using a single
578 sethi instruction. */
583 if (GET_CODE (op) == CONST_DOUBLE)
588 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
589 if (REAL_VALUES_EQUAL (r, dconst0) &&
590 ! REAL_VALUE_MINUS_ZERO (r))
592 REAL_VALUE_TO_TARGET_SINGLE (r, i);
593 if (SPARC_SETHI_P (i))
600 /* Nonzero if OP is a floating point constant which can
601 be loaded into an integer register using a single
607 if (GET_CODE (op) == CONST_DOUBLE)
612 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
613 if (REAL_VALUES_EQUAL (r, dconst0) &&
614 ! REAL_VALUE_MINUS_ZERO (r))
616 REAL_VALUE_TO_TARGET_SINGLE (r, i);
617 if (SPARC_SIMM13_P (i))
624 /* Nonzero if OP is a floating point constant which can
625 be loaded into an integer register using a high/losum
626 instruction sequence. */
629 fp_high_losum_p (rtx op)
631 /* The constraints calling this should only be in
632 SFmode move insns, so any constant which cannot
633 be moved using a single insn will do. */
634 if (GET_CODE (op) == CONST_DOUBLE)
639 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
640 if (REAL_VALUES_EQUAL (r, dconst0) &&
641 ! REAL_VALUE_MINUS_ZERO (r))
643 REAL_VALUE_TO_TARGET_SINGLE (r, i);
644 if (! SPARC_SETHI_P (i)
645 && ! SPARC_SIMM13_P (i))
652 /* Nonzero if OP is an integer register. */
655 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
657 return (register_operand (op, SImode)
658 || (TARGET_ARCH64 && register_operand (op, DImode)));
661 /* Nonzero if OP is a floating point condition code register. */
664 fcc_reg_operand (rtx op, enum machine_mode mode)
666 /* This can happen when recog is called from combine. Op may be a MEM.
667 Fail instead of calling abort in this case. */
668 if (GET_CODE (op) != REG)
671 if (mode != VOIDmode && mode != GET_MODE (op))
674 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
677 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
678 if (reg_renumber == 0)
679 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
680 return REGNO_OK_FOR_CCFP_P (REGNO (op));
682 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
686 /* Nonzero if OP is a floating point condition code fcc0 register. */
689 fcc0_reg_operand (rtx op, enum machine_mode mode)
691 /* This can happen when recog is called from combine. Op may be a MEM.
692 Fail instead of calling abort in this case. */
693 if (GET_CODE (op) != REG)
696 if (mode != VOIDmode && mode != GET_MODE (op))
699 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
702 return REGNO (op) == SPARC_FCC_REG;
705 /* Nonzero if OP is an integer or floating point condition code register. */
708 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
710 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
712 if (mode != VOIDmode && mode != GET_MODE (op))
715 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
720 return fcc_reg_operand (op, mode);
723 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
725 restore_operand (rtx op, enum machine_mode mode)
727 return (GET_CODE (op) == REG && GET_MODE (op) == mode
728 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
731 /* Call insn on SPARC can take a PC-relative constant address, or any regular
735 call_operand (rtx op, enum machine_mode mode)
737 if (GET_CODE (op) != MEM)
740 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
744 call_operand_address (rtx op, enum machine_mode mode)
746 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
749 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
750 otherwise return 0. */
753 tls_symbolic_operand (rtx op)
755 if (GET_CODE (op) != SYMBOL_REF)
757 return SYMBOL_REF_TLS_MODEL (op);
761 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
763 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
767 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
769 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
773 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
775 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
779 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
781 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
784 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
785 reference and a constant. */
788 symbolic_operand (register rtx op, enum machine_mode mode)
790 enum machine_mode omode = GET_MODE (op);
792 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
795 switch (GET_CODE (op))
798 return !SYMBOL_REF_TLS_MODEL (op);
805 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
806 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
807 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
808 && GET_CODE (XEXP (op, 1)) == CONST_INT);
815 /* Return truth value of statement that OP is a symbolic memory
816 operand of mode MODE. */
819 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
821 if (GET_CODE (op) == SUBREG)
822 op = SUBREG_REG (op);
823 if (GET_CODE (op) != MEM)
826 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
827 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
828 || GET_CODE (op) == LABEL_REF);
831 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
834 label_ref_operand (rtx op, enum machine_mode mode)
836 if (GET_CODE (op) != LABEL_REF)
838 if (GET_MODE (op) != mode)
843 /* Return 1 if the operand is an argument used in generating pic references
844 in either the medium/low or medium/anywhere code models of sparc64. */
847 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
849 /* Check for (const (minus (symbol_ref:GOT)
850 (const (minus (label) (pc))))). */
851 if (GET_CODE (op) != CONST)
854 if (GET_CODE (op) != MINUS)
856 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
858 /* ??? Ensure symbol is GOT. */
859 if (GET_CODE (XEXP (op, 1)) != CONST)
861 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
866 /* Return 1 if the operand is a data segment reference. This includes
867 the readonly data segment, or in other words anything but the text segment.
868 This is needed in the medium/anywhere code model on v9. These values
869 are accessed with EMBMEDANY_BASE_REG. */
872 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
874 switch (GET_CODE (op))
877 return ! SYMBOL_REF_FUNCTION_P (op);
879 /* Assume canonical format of symbol + constant.
882 return data_segment_operand (XEXP (op, 0), VOIDmode);
888 /* Return 1 if the operand is a text segment reference.
889 This is needed in the medium/anywhere code model on v9. */
892 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
894 switch (GET_CODE (op))
899 return SYMBOL_REF_FUNCTION_P (op);
901 /* Assume canonical format of symbol + constant.
904 return text_segment_operand (XEXP (op, 0), VOIDmode);
910 /* Return 1 if the operand is either a register or a memory operand that is
914 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
916 if (register_operand (op, mode))
919 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
926 splittable_symbolic_memory_operand (rtx op,
927 enum machine_mode mode ATTRIBUTE_UNUSED)
929 if (GET_CODE (op) != MEM)
931 if (! symbolic_operand (XEXP (op, 0), Pmode))
937 splittable_immediate_memory_operand (rtx op,
938 enum machine_mode mode ATTRIBUTE_UNUSED)
940 if (GET_CODE (op) != MEM)
942 if (! immediate_operand (XEXP (op, 0), Pmode))
947 /* Return truth value of whether OP is EQ or NE. */
950 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
952 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
955 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
956 or LTU for non-floating-point. We handle those specially. */
959 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
963 if (!COMPARISON_P (op))
966 if (GET_MODE (XEXP (op, 0)) == CCFPmode
967 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
970 code = GET_CODE (op);
971 return (code != NE && code != EQ && code != GEU && code != LTU);
974 /* Return 1 if this is a comparison operator. This allows the use of
975 MATCH_OPERATOR to recognize all the branch insns. */
978 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
982 if (!COMPARISON_P (op))
985 code = GET_CODE (op);
986 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
987 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
988 /* These are the only branches which work with CC_NOOVmode. */
989 return (code == EQ || code == NE || code == GE || code == LT);
993 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
994 MATCH_OPERATOR to recognize all the branch insns. */
997 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1004 if (!COMPARISON_P (op));
1007 code = GET_CODE (op);
1008 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1009 /* These are the only branches which work with CCX_NOOVmode. */
1010 return (code == EQ || code == NE || code == GE || code == LT);
1011 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1014 /* Nonzero if OP is a comparison operator suitable for use in v9
1015 conditional move or branch on register contents instructions. */
1018 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1022 if (!COMPARISON_P (op))
1025 code = GET_CODE (op);
1026 return v9_regcmp_p (code);
1029 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1032 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1034 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1037 /* Return nonzero if OP is an operator of mode MODE which can set
1038 the condition codes explicitly. We do not include PLUS and MINUS
1039 because these require CC_NOOVmode, which we handle explicitly. */
1042 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1044 if (GET_CODE (op) == AND
1045 || GET_CODE (op) == IOR
1046 || GET_CODE (op) == XOR)
1052 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1053 complement its second operand and set the condition codes explicitly. */
1056 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1058 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1059 and (xor ... (not ...)) to (not (xor ...)). */
1060 return (GET_CODE (op) == AND
1061 || GET_CODE (op) == IOR);
1064 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1065 signed 13 bit immediate field. This is an acceptable SImode operand for
1066 most 3 address instructions. */
1069 arith_operand (rtx op, enum machine_mode mode)
1071 if (register_operand (op, mode))
1073 if (GET_CODE (op) != CONST_INT)
1075 return SMALL_INT32 (op);
1078 /* Return true if OP is a constant 4096 */
1081 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1083 if (GET_CODE (op) != CONST_INT)
1086 return INTVAL (op) == 4096;
1089 /* Return true if OP is suitable as second operand for add/sub */
1092 arith_add_operand (rtx op, enum machine_mode mode)
1094 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1097 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1098 immediate field of OR and XOR instructions. Used for 64-bit
1099 constant formation patterns. */
1101 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1103 return ((GET_CODE (op) == CONST_INT
1104 && SPARC_SIMM13_P (INTVAL (op)))
1105 #if HOST_BITS_PER_WIDE_INT != 64
1106 || (GET_CODE (op) == CONST_DOUBLE
1107 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1108 && (CONST_DOUBLE_HIGH (op) ==
1109 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1110 (HOST_WIDE_INT)-1 : 0)))
1115 /* The same, but only for sethi instructions. */
1117 const64_high_operand (rtx op, enum machine_mode mode)
1119 return ((GET_CODE (op) == CONST_INT
1120 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1121 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1123 || (GET_CODE (op) == CONST_DOUBLE
1124 && CONST_DOUBLE_HIGH (op) == 0
1125 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1126 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1129 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1130 signed 11 bit immediate field. This is an acceptable SImode operand for
1131 the movcc instructions. */
1134 arith11_operand (rtx op, enum machine_mode mode)
1136 return (register_operand (op, mode)
1137 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1140 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1141 signed 10 bit immediate field. This is an acceptable SImode operand for
1142 the movrcc instructions. */
1145 arith10_operand (rtx op, enum machine_mode mode)
1147 return (register_operand (op, mode)
1148 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1151 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1152 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1154 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1155 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1156 for most 3 address instructions. */
1159 arith_double_operand (rtx op, enum machine_mode mode)
1161 return (register_operand (op, mode)
1162 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1164 && GET_CODE (op) == CONST_DOUBLE
1165 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1166 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1168 && GET_CODE (op) == CONST_DOUBLE
1169 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1170 && ((CONST_DOUBLE_HIGH (op) == -1
1171 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1172 || (CONST_DOUBLE_HIGH (op) == 0
1173 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1176 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1179 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1181 return (TARGET_ARCH64 &&
1182 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1183 (GET_CODE (op) == CONST_DOUBLE &&
1184 CONST_DOUBLE_LOW (op) == 4096 &&
1185 CONST_DOUBLE_HIGH (op) == 0)));
1188 /* Return true if OP is suitable as second operand for add/sub in DImode */
1191 arith_double_add_operand (rtx op, enum machine_mode mode)
1193 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1196 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1197 can fit in an 11 bit immediate field. This is an acceptable DImode
1198 operand for the movcc instructions. */
1199 /* ??? Replace with arith11_operand? */
1202 arith11_double_operand (rtx op, enum machine_mode mode)
1204 return (register_operand (op, mode)
1205 || (GET_CODE (op) == CONST_DOUBLE
1206 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1207 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1208 && ((CONST_DOUBLE_HIGH (op) == -1
1209 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1210 || (CONST_DOUBLE_HIGH (op) == 0
1211 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1212 || (GET_CODE (op) == CONST_INT
1213 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1214 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1217 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1218 can fit in an 10 bit immediate field. This is an acceptable DImode
1219 operand for the movrcc instructions. */
1220 /* ??? Replace with arith10_operand? */
1223 arith10_double_operand (rtx op, enum machine_mode mode)
1225 return (register_operand (op, mode)
1226 || (GET_CODE (op) == CONST_DOUBLE
1227 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1228 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1229 && ((CONST_DOUBLE_HIGH (op) == -1
1230 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1231 || (CONST_DOUBLE_HIGH (op) == 0
1232 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1233 || (GET_CODE (op) == CONST_INT
1234 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1235 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1238 /* Return truth value of whether OP is an integer which fits the
1239 range constraining immediate operands in most three-address insns,
1240 which have a 13 bit immediate field. */
1243 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1245 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1249 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1251 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1252 || (GET_CODE (op) == CONST_DOUBLE
1253 && CONST_DOUBLE_HIGH (op) == 0
1254 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1257 /* Recognize operand values for the umul instruction. That instruction sign
1258 extends immediate values just like all other sparc instructions, but
1259 interprets the extended result as an unsigned number. */
1262 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1264 #if HOST_BITS_PER_WIDE_INT > 32
1265 /* All allowed constants will fit a CONST_INT. */
1266 return (GET_CODE (op) == CONST_INT
1267 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1268 || (INTVAL (op) >= 0xFFFFF000
1269 && INTVAL (op) <= 0xFFFFFFFF)));
1271 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1272 || (GET_CODE (op) == CONST_DOUBLE
1273 && CONST_DOUBLE_HIGH (op) == 0
1274 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1279 uns_arith_operand (rtx op, enum machine_mode mode)
1281 return register_operand (op, mode) || uns_small_int (op, mode);
1284 /* Return truth value of statement that OP is a call-clobbered register. */
1286 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1288 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1291 /* Return 1 if OP is a valid operand for the source of a move insn. */
1294 input_operand (rtx op, enum machine_mode mode)
1296 /* If both modes are non-void they must be the same. */
1297 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1300 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1301 if (GET_CODE (op) == CONSTANT_P_RTX)
1304 /* Allow any one instruction integer constant, and all CONST_INT
1305 variants when we are working in DImode and !arch64. */
1306 if (GET_MODE_CLASS (mode) == MODE_INT
1307 && ((GET_CODE (op) == CONST_INT
1308 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1309 || SPARC_SIMM13_P (INTVAL (op))
1311 && ! TARGET_ARCH64)))
1313 && GET_CODE (op) == CONST_DOUBLE
1314 && ((CONST_DOUBLE_HIGH (op) == 0
1315 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1317 #if HOST_BITS_PER_WIDE_INT == 64
1318 (CONST_DOUBLE_HIGH (op) == 0
1319 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1321 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1322 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1323 && CONST_DOUBLE_HIGH (op) == 0)
1324 || (CONST_DOUBLE_HIGH (op) == -1
1325 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1330 /* If !arch64 and this is a DImode const, allow it so that
1331 the splits can be generated. */
1334 && GET_CODE (op) == CONST_DOUBLE)
1337 if (register_operand (op, mode))
1340 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1341 && GET_CODE (op) == CONST_DOUBLE)
1344 /* If this is a SUBREG, look inside so that we handle
1345 paradoxical ones. */
1346 if (GET_CODE (op) == SUBREG)
1347 op = SUBREG_REG (op);
1349 /* Check for valid MEM forms. */
1350 if (GET_CODE (op) == MEM)
1352 rtx inside = XEXP (op, 0);
1354 if (GET_CODE (inside) == LO_SUM)
1356 /* We can't allow these because all of the splits
1357 (eventually as they trickle down into DFmode
1358 splits) require offsettable memory references. */
1360 && GET_MODE (op) == TFmode)
1363 return (register_operand (XEXP (inside, 0), Pmode)
1364 && CONSTANT_P (XEXP (inside, 1)));
1366 return memory_address_p (mode, inside);
1373 /* We know it can't be done in one insn when we get here,
1374 the movsi expander guarantees this. */
1376 sparc_emit_set_const32 (rtx op0, rtx op1)
1378 enum machine_mode mode = GET_MODE (op0);
1381 if (GET_CODE (op1) == CONST_INT)
1383 HOST_WIDE_INT value = INTVAL (op1);
1385 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1386 || SPARC_SIMM13_P (value))
1390 /* Full 2-insn decomposition is needed. */
1391 if (reload_in_progress || reload_completed)
1394 temp = gen_reg_rtx (mode);
1396 if (GET_CODE (op1) == CONST_INT)
1398 /* Emit them as real moves instead of a HIGH/LO_SUM,
1399 this way CSE can see everything and reuse intermediate
1400 values if it wants. */
1402 && HOST_BITS_PER_WIDE_INT != 64
1403 && (INTVAL (op1) & 0x80000000) != 0)
1404 emit_insn (gen_rtx_SET
1406 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1409 emit_insn (gen_rtx_SET (VOIDmode, temp,
1410 GEN_INT (INTVAL (op1)
1411 & ~(HOST_WIDE_INT)0x3ff)));
1413 emit_insn (gen_rtx_SET (VOIDmode,
1415 gen_rtx_IOR (mode, temp,
1416 GEN_INT (INTVAL (op1) & 0x3ff))));
1420 /* A symbol, emit in the traditional way. */
1421 emit_insn (gen_rtx_SET (VOIDmode, temp,
1422 gen_rtx_HIGH (mode, op1)));
1423 emit_insn (gen_rtx_SET (VOIDmode,
1424 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1430 /* SPARC-v9 code-model support. */
1432 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
1436 if (temp1 && GET_MODE (temp1) == TImode)
1439 temp1 = gen_rtx_REG (DImode, REGNO (temp1));
1442 switch (sparc_cmodel)
1445 /* The range spanned by all instructions in the object is less
1446 than 2^31 bytes (2GB) and the distance from any instruction
1447 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1448 than 2^31 bytes (2GB).
1450 The executable must be in the low 4TB of the virtual address
1453 sethi %hi(symbol), %temp
1454 or %temp, %lo(symbol), %reg */
1455 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1456 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1460 /* The range spanned by all instructions in the object is less
1461 than 2^31 bytes (2GB) and the distance from any instruction
1462 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1463 than 2^31 bytes (2GB).
1465 The executable must be in the low 16TB of the virtual address
1468 sethi %h44(symbol), %temp1
1469 or %temp1, %m44(symbol), %temp2
1470 sllx %temp2, 12, %temp3
1471 or %temp3, %l44(symbol), %reg */
1472 emit_insn (gen_seth44 (op0, op1));
1473 emit_insn (gen_setm44 (op0, op0, op1));
1474 emit_insn (gen_rtx_SET (VOIDmode, temp1,
1475 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1476 emit_insn (gen_setl44 (op0, temp1, op1));
1480 /* The range spanned by all instructions in the object is less
1481 than 2^31 bytes (2GB) and the distance from any instruction
1482 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1483 than 2^31 bytes (2GB).
1485 The executable can be placed anywhere in the virtual address
1488 sethi %hh(symbol), %temp1
1489 sethi %lm(symbol), %temp2
1490 or %temp1, %hm(symbol), %temp3
1491 or %temp2, %lo(symbol), %temp4
1492 sllx %temp3, 32, %temp5
1493 or %temp4, %temp5, %reg */
1495 /* It is possible that one of the registers we got for operands[2]
1496 might coincide with that of operands[0] (which is why we made
1497 it TImode). Pick the other one to use as our scratch. */
1498 if (rtx_equal_p (temp1, op0))
1501 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1506 emit_insn (gen_sethh (op0, op1));
1507 emit_insn (gen_setlm (temp1, op1));
1508 emit_insn (gen_sethm (op0, op0, op1));
1509 emit_insn (gen_rtx_SET (VOIDmode, op0,
1510 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1511 emit_insn (gen_rtx_SET (VOIDmode, op0,
1512 gen_rtx_PLUS (DImode, op0, temp1)));
1513 emit_insn (gen_setlo (op0, op0, op1));
1517 /* Old old old backwards compatibility kruft here.
1518 Essentially it is MEDLOW with a fixed 64-bit
1519 virtual base added to all data segment addresses.
1520 Text-segment stuff is computed like MEDANY, we can't
1521 reuse the code above because the relocation knobs
1524 Data segment: sethi %hi(symbol), %temp1
1525 or %temp1, %lo(symbol), %temp2
1526 add %temp2, EMBMEDANY_BASE_REG, %reg
1528 Text segment: sethi %uhi(symbol), %temp1
1529 sethi %hi(symbol), %temp2
1530 or %temp1, %ulo(symbol), %temp3
1531 or %temp2, %lo(symbol), %temp4
1532 sllx %temp3, 32, %temp5
1533 or %temp4, %temp5, %reg */
1534 if (data_segment_operand (op1, GET_MODE (op1)))
1536 emit_insn (gen_embmedany_sethi (temp1, op1));
1537 emit_insn (gen_embmedany_brsum (op0, temp1));
1538 emit_insn (gen_embmedany_losum (op0, op0, op1));
1542 /* It is possible that one of the registers we got for operands[2]
1543 might coincide with that of operands[0] (which is why we made
1544 it TImode). Pick the other one to use as our scratch. */
1545 if (rtx_equal_p (temp1, op0))
1548 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
1553 emit_insn (gen_embmedany_textuhi (op0, op1));
1554 emit_insn (gen_embmedany_texthi (temp1, op1));
1555 emit_insn (gen_embmedany_textulo (op0, op0, op1));
1556 emit_insn (gen_rtx_SET (VOIDmode, op0,
1557 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
1558 emit_insn (gen_rtx_SET (VOIDmode, op0,
1559 gen_rtx_PLUS (DImode, op0, temp1)));
1560 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1569 /* These avoid problems when cross compiling. If we do not
1570 go through all this hair then the optimizer will see
1571 invalid REG_EQUAL notes or in some cases none at all. */
1572 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1573 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1574 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1575 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1577 #if HOST_BITS_PER_WIDE_INT == 64
1578 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1579 #define GEN_INT64(__x) GEN_INT (__x)
1581 #define GEN_HIGHINT64(__x) \
1582 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1583 #define GEN_INT64(__x) \
1584 immed_double_const ((__x) & 0xffffffff, \
1585 ((__x) & 0x80000000 ? -1 : 0), DImode)
1588 /* The optimizer is not to assume anything about exactly
1589 which bits are set for a HIGH, they are unspecified.
1590 Unfortunately this leads to many missed optimizations
1591 during CSE. We mask out the non-HIGH bits, and matches
1592 a plain movdi, to alleviate this problem. */
1594 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1596 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1600 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1602 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1606 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1608 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1612 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1614 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1617 /* Worker routines for 64-bit constant formation on arch64.
1618 One of the key things to be doing in these emissions is
1619 to create as many temp REGs as possible. This makes it
1620 possible for half-built constants to be used later when
1621 such values are similar to something required later on.
1622 Without doing this, the optimizer cannot see such
1625 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1626 unsigned HOST_WIDE_INT, int);
1629 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1630 unsigned HOST_WIDE_INT low_bits, int is_neg)
1632 unsigned HOST_WIDE_INT high_bits;
1635 high_bits = (~low_bits) & 0xffffffff;
1637 high_bits = low_bits;
1639 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1642 emit_insn (gen_rtx_SET (VOIDmode, op0,
1643 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1647 /* If we are XOR'ing with -1, then we should emit a one's complement
1648 instead. This way the combiner will notice logical operations
1649 such as ANDN later on and substitute. */
1650 if ((low_bits & 0x3ff) == 0x3ff)
1652 emit_insn (gen_rtx_SET (VOIDmode, op0,
1653 gen_rtx_NOT (DImode, temp)));
1657 emit_insn (gen_rtx_SET (VOIDmode, op0,
1658 gen_safe_XOR64 (temp,
1659 (-(HOST_WIDE_INT)0x400
1660 | (low_bits & 0x3ff)))));
1665 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1666 unsigned HOST_WIDE_INT, int);
1669 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1670 unsigned HOST_WIDE_INT high_bits,
1671 unsigned HOST_WIDE_INT low_immediate,
1676 if ((high_bits & 0xfffffc00) != 0)
1678 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1679 if ((high_bits & ~0xfffffc00) != 0)
1680 emit_insn (gen_rtx_SET (VOIDmode, op0,
1681 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1687 emit_insn (gen_safe_SET64 (temp, high_bits));
1691 /* Now shift it up into place. */
1692 emit_insn (gen_rtx_SET (VOIDmode, op0,
1693 gen_rtx_ASHIFT (DImode, temp2,
1694 GEN_INT (shift_count))));
1696 /* If there is a low immediate part piece, finish up by
1697 putting that in as well. */
1698 if (low_immediate != 0)
1699 emit_insn (gen_rtx_SET (VOIDmode, op0,
1700 gen_safe_OR64 (op0, low_immediate)));
1703 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1704 unsigned HOST_WIDE_INT);
1706 /* Full 64-bit constant decomposition. Even though this is the
1707 'worst' case, we still optimize a few things away. */
1709 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1710 unsigned HOST_WIDE_INT high_bits,
1711 unsigned HOST_WIDE_INT low_bits)
1715 if (reload_in_progress || reload_completed)
1718 sub_temp = gen_reg_rtx (DImode);
1720 if ((high_bits & 0xfffffc00) != 0)
1722 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1723 if ((high_bits & ~0xfffffc00) != 0)
1724 emit_insn (gen_rtx_SET (VOIDmode,
1726 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1732 emit_insn (gen_safe_SET64 (temp, high_bits));
1736 if (!reload_in_progress && !reload_completed)
1738 rtx temp2 = gen_reg_rtx (DImode);
1739 rtx temp3 = gen_reg_rtx (DImode);
1740 rtx temp4 = gen_reg_rtx (DImode);
1742 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1743 gen_rtx_ASHIFT (DImode, sub_temp,
1746 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1747 if ((low_bits & ~0xfffffc00) != 0)
1749 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1750 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1751 emit_insn (gen_rtx_SET (VOIDmode, op0,
1752 gen_rtx_PLUS (DImode, temp4, temp3)));
1756 emit_insn (gen_rtx_SET (VOIDmode, op0,
1757 gen_rtx_PLUS (DImode, temp4, temp2)));
1762 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1763 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1764 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1767 /* We are in the middle of reload, so this is really
1768 painful. However we do still make an attempt to
1769 avoid emitting truly stupid code. */
1770 if (low1 != const0_rtx)
1772 emit_insn (gen_rtx_SET (VOIDmode, op0,
1773 gen_rtx_ASHIFT (DImode, sub_temp,
1774 GEN_INT (to_shift))));
1775 emit_insn (gen_rtx_SET (VOIDmode, op0,
1776 gen_rtx_IOR (DImode, op0, low1)));
1784 if (low2 != const0_rtx)
1786 emit_insn (gen_rtx_SET (VOIDmode, op0,
1787 gen_rtx_ASHIFT (DImode, sub_temp,
1788 GEN_INT (to_shift))));
1789 emit_insn (gen_rtx_SET (VOIDmode, op0,
1790 gen_rtx_IOR (DImode, op0, low2)));
1798 emit_insn (gen_rtx_SET (VOIDmode, op0,
1799 gen_rtx_ASHIFT (DImode, sub_temp,
1800 GEN_INT (to_shift))));
1801 if (low3 != const0_rtx)
1802 emit_insn (gen_rtx_SET (VOIDmode, op0,
1803 gen_rtx_IOR (DImode, op0, low3)));
1808 /* Analyze a 64-bit constant for certain properties. */
1809 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1810 unsigned HOST_WIDE_INT,
1811 int *, int *, int *);
1814 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1815 unsigned HOST_WIDE_INT low_bits,
1816 int *hbsp, int *lbsp, int *abbasp)
1818 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1821 lowest_bit_set = highest_bit_set = -1;
1825 if ((lowest_bit_set == -1)
1826 && ((low_bits >> i) & 1))
1828 if ((highest_bit_set == -1)
1829 && ((high_bits >> (32 - i - 1)) & 1))
1830 highest_bit_set = (64 - i - 1);
1833 && ((highest_bit_set == -1)
1834 || (lowest_bit_set == -1)));
1840 if ((lowest_bit_set == -1)
1841 && ((high_bits >> i) & 1))
1842 lowest_bit_set = i + 32;
1843 if ((highest_bit_set == -1)
1844 && ((low_bits >> (32 - i - 1)) & 1))
1845 highest_bit_set = 32 - i - 1;
1848 && ((highest_bit_set == -1)
1849 || (lowest_bit_set == -1)));
1851 /* If there are no bits set this should have gone out
1852 as one instruction! */
1853 if (lowest_bit_set == -1
1854 || highest_bit_set == -1)
1856 all_bits_between_are_set = 1;
1857 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1861 if ((low_bits & (1 << i)) != 0)
1866 if ((high_bits & (1 << (i - 32))) != 0)
1869 all_bits_between_are_set = 0;
1872 *hbsp = highest_bit_set;
1873 *lbsp = lowest_bit_set;
1874 *abbasp = all_bits_between_are_set;
1877 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1880 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1881 unsigned HOST_WIDE_INT low_bits)
1883 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1886 || high_bits == 0xffffffff)
1889 analyze_64bit_constant (high_bits, low_bits,
1890 &highest_bit_set, &lowest_bit_set,
1891 &all_bits_between_are_set);
1893 if ((highest_bit_set == 63
1894 || lowest_bit_set == 0)
1895 && all_bits_between_are_set != 0)
1898 if ((highest_bit_set - lowest_bit_set) < 21)
1904 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1905 unsigned HOST_WIDE_INT,
1908 static unsigned HOST_WIDE_INT
1909 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1910 unsigned HOST_WIDE_INT low_bits,
1911 int lowest_bit_set, int shift)
1913 HOST_WIDE_INT hi, lo;
1915 if (lowest_bit_set < 32)
1917 lo = (low_bits >> lowest_bit_set) << shift;
1918 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1923 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1930 /* Here we are sure to be arch64 and this is an integer constant
1931 being loaded into a register. Emit the most efficient
1932 insn sequence possible. Detection of all the 1-insn cases
1933 has been done already. */
1935 sparc_emit_set_const64 (rtx op0, rtx op1)
1937 unsigned HOST_WIDE_INT high_bits, low_bits;
1938 int lowest_bit_set, highest_bit_set;
1939 int all_bits_between_are_set;
1942 /* Sanity check that we know what we are working with. */
1943 if (! TARGET_ARCH64)
1946 if (GET_CODE (op0) != SUBREG)
1948 if (GET_CODE (op0) != REG
1949 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1950 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
1954 if (reload_in_progress || reload_completed)
1957 temp = gen_reg_rtx (DImode);
1959 if (GET_CODE (op1) != CONST_DOUBLE
1960 && GET_CODE (op1) != CONST_INT)
1962 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1966 if (GET_CODE (op1) == CONST_DOUBLE)
1968 #if HOST_BITS_PER_WIDE_INT == 64
1969 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
1970 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1972 high_bits = CONST_DOUBLE_HIGH (op1);
1973 low_bits = CONST_DOUBLE_LOW (op1);
1978 #if HOST_BITS_PER_WIDE_INT == 64
1979 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
1980 low_bits = (INTVAL (op1) & 0xffffffff);
1982 high_bits = ((INTVAL (op1) < 0) ?
1985 low_bits = INTVAL (op1);
1989 /* low_bits bits 0 --> 31
1990 high_bits bits 32 --> 63 */
1992 analyze_64bit_constant (high_bits, low_bits,
1993 &highest_bit_set, &lowest_bit_set,
1994 &all_bits_between_are_set);
1996 /* First try for a 2-insn sequence. */
1998 /* These situations are preferred because the optimizer can
1999 * do more things with them:
2001 * sllx %reg, shift, %reg
2003 * srlx %reg, shift, %reg
2004 * 3) mov some_small_const, %reg
2005 * sllx %reg, shift, %reg
2007 if (((highest_bit_set == 63
2008 || lowest_bit_set == 0)
2009 && all_bits_between_are_set != 0)
2010 || ((highest_bit_set - lowest_bit_set) < 12))
2012 HOST_WIDE_INT the_const = -1;
2013 int shift = lowest_bit_set;
2015 if ((highest_bit_set != 63
2016 && lowest_bit_set != 0)
2017 || all_bits_between_are_set == 0)
2020 create_simple_focus_bits (high_bits, low_bits,
2023 else if (lowest_bit_set == 0)
2024 shift = -(63 - highest_bit_set);
2026 if (! SPARC_SIMM13_P (the_const))
2029 emit_insn (gen_safe_SET64 (temp, the_const));
2031 emit_insn (gen_rtx_SET (VOIDmode,
2033 gen_rtx_ASHIFT (DImode,
2037 emit_insn (gen_rtx_SET (VOIDmode,
2039 gen_rtx_LSHIFTRT (DImode,
2041 GEN_INT (-shift))));
2047 /* Now a range of 22 or less bits set somewhere.
2048 * 1) sethi %hi(focus_bits), %reg
2049 * sllx %reg, shift, %reg
2050 * 2) sethi %hi(focus_bits), %reg
2051 * srlx %reg, shift, %reg
2053 if ((highest_bit_set - lowest_bit_set) < 21)
2055 unsigned HOST_WIDE_INT focus_bits =
2056 create_simple_focus_bits (high_bits, low_bits,
2057 lowest_bit_set, 10);
2059 if (! SPARC_SETHI_P (focus_bits))
2062 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2064 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2065 if (lowest_bit_set < 10)
2066 emit_insn (gen_rtx_SET (VOIDmode,
2068 gen_rtx_LSHIFTRT (DImode, temp,
2069 GEN_INT (10 - lowest_bit_set))));
2070 else if (lowest_bit_set > 10)
2071 emit_insn (gen_rtx_SET (VOIDmode,
2073 gen_rtx_ASHIFT (DImode, temp,
2074 GEN_INT (lowest_bit_set - 10))));
2080 /* 1) sethi %hi(low_bits), %reg
2081 * or %reg, %lo(low_bits), %reg
2082 * 2) sethi %hi(~low_bits), %reg
2083 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2086 || high_bits == 0xffffffff)
2088 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2089 (high_bits == 0xffffffff));
2093 /* Now, try 3-insn sequences. */
2095 /* 1) sethi %hi(high_bits), %reg
2096 * or %reg, %lo(high_bits), %reg
2097 * sllx %reg, 32, %reg
2101 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2105 /* We may be able to do something quick
2106 when the constant is negated, so try that. */
2107 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2108 (~low_bits) & 0xfffffc00))
2110 /* NOTE: The trailing bits get XOR'd so we need the
2111 non-negated bits, not the negated ones. */
2112 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2114 if ((((~high_bits) & 0xffffffff) == 0
2115 && ((~low_bits) & 0x80000000) == 0)
2116 || (((~high_bits) & 0xffffffff) == 0xffffffff
2117 && ((~low_bits) & 0x80000000) != 0))
2119 int fast_int = (~low_bits & 0xffffffff);
2121 if ((SPARC_SETHI_P (fast_int)
2122 && (~high_bits & 0xffffffff) == 0)
2123 || SPARC_SIMM13_P (fast_int))
2124 emit_insn (gen_safe_SET64 (temp, fast_int));
2126 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2131 #if HOST_BITS_PER_WIDE_INT == 64
2132 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2133 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2135 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2136 (~high_bits) & 0xffffffff,
2139 sparc_emit_set_const64 (temp, negated_const);
2142 /* If we are XOR'ing with -1, then we should emit a one's complement
2143 instead. This way the combiner will notice logical operations
2144 such as ANDN later on and substitute. */
2145 if (trailing_bits == 0x3ff)
2147 emit_insn (gen_rtx_SET (VOIDmode, op0,
2148 gen_rtx_NOT (DImode, temp)));
2152 emit_insn (gen_rtx_SET (VOIDmode,
2154 gen_safe_XOR64 (temp,
2155 (-0x400 | trailing_bits))));
2160 /* 1) sethi %hi(xxx), %reg
2161 * or %reg, %lo(xxx), %reg
2162 * sllx %reg, yyy, %reg
2164 * ??? This is just a generalized version of the low_bits==0
2165 * thing above, FIXME...
2167 if ((highest_bit_set - lowest_bit_set) < 32)
2169 unsigned HOST_WIDE_INT focus_bits =
2170 create_simple_focus_bits (high_bits, low_bits,
2173 /* We can't get here in this state. */
2174 if (highest_bit_set < 32
2175 || lowest_bit_set >= 32)
2178 /* So what we know is that the set bits straddle the
2179 middle of the 64-bit word. */
2180 sparc_emit_set_const64_quick2 (op0, temp,
2186 /* 1) sethi %hi(high_bits), %reg
2187 * or %reg, %lo(high_bits), %reg
2188 * sllx %reg, 32, %reg
2189 * or %reg, low_bits, %reg
2191 if (SPARC_SIMM13_P(low_bits)
2192 && ((int)low_bits > 0))
2194 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2198 /* The easiest way when all else fails, is full decomposition. */
2200 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2201 high_bits, low_bits, ~high_bits, ~low_bits);
2203 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2206 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2207 return the mode to be used for the comparison. For floating-point,
2208 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2209 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2210 processing is needed. */
2213 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2215 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2241 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2242 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2244 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2245 return CCX_NOOVmode;
2251 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2258 /* X and Y are two things to compare using CODE. Emit the compare insn and
2259 return the rtx for the cc reg in the proper mode. */
2262 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2264 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2267 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2268 fcc regs (cse can't tell they're really call clobbered regs and will
2269 remove a duplicate comparison even if there is an intervening function
2270 call - it will then try to reload the cc reg via an int reg which is why
2271 we need the movcc patterns). It is possible to provide the movcc
2272 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2273 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2274 to tell cse that CCFPE mode registers (even pseudos) are call
2277 /* ??? This is an experiment. Rather than making changes to cse which may
2278 or may not be easy/clean, we do our own cse. This is possible because
2279 we will generate hard registers. Cse knows they're call clobbered (it
2280 doesn't know the same thing about pseudos). If we guess wrong, no big
2281 deal, but if we win, great! */
2283 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2284 #if 1 /* experiment */
2287 /* We cycle through the registers to ensure they're all exercised. */
2288 static int next_fcc_reg = 0;
2289 /* Previous x,y for each fcc reg. */
2290 static rtx prev_args[4][2];
2292 /* Scan prev_args for x,y. */
2293 for (reg = 0; reg < 4; reg++)
2294 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2299 prev_args[reg][0] = x;
2300 prev_args[reg][1] = y;
2301 next_fcc_reg = (next_fcc_reg + 1) & 3;
2303 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2306 cc_reg = gen_reg_rtx (mode);
2307 #endif /* ! experiment */
2308 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2309 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2311 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2313 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2314 gen_rtx_COMPARE (mode, x, y)));
2319 /* This function is used for v9 only.
2320 CODE is the code for an Scc's comparison.
2321 OPERANDS[0] is the target of the Scc insn.
2322 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2323 been generated yet).
2325 This function is needed to turn
2328 (gt (reg:CCX 100 %icc)
2332 (gt:DI (reg:CCX 100 %icc)
2335 IE: The instruction recognizer needs to see the mode of the comparison to
2336 find the right instruction. We could use "gt:DI" right in the
2337 define_expand, but leaving it out allows us to handle DI, SI, etc.
2339 We refer to the global sparc compare operands sparc_compare_op0 and
2340 sparc_compare_op1. */
2343 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2348 && (GET_MODE (sparc_compare_op0) == DImode
2349 || GET_MODE (operands[0]) == DImode))
2352 op0 = sparc_compare_op0;
2353 op1 = sparc_compare_op1;
2355 /* Try to use the movrCC insns. */
2357 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2358 && op1 == const0_rtx
2359 && v9_regcmp_p (compare_code))
2361 /* Special case for op0 != 0. This can be done with one instruction if
2362 operands[0] == sparc_compare_op0. */
2364 if (compare_code == NE
2365 && GET_MODE (operands[0]) == DImode
2366 && rtx_equal_p (op0, operands[0]))
2368 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2369 gen_rtx_IF_THEN_ELSE (DImode,
2370 gen_rtx_fmt_ee (compare_code, DImode,
2377 if (reg_overlap_mentioned_p (operands[0], op0))
2379 /* Handle the case where operands[0] == sparc_compare_op0.
2380 We "early clobber" the result. */
2381 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2382 emit_move_insn (op0, sparc_compare_op0);
2385 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2386 if (GET_MODE (op0) != DImode)
2388 temp = gen_reg_rtx (DImode);
2389 convert_move (temp, op0, 0);
2393 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2394 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2395 gen_rtx_fmt_ee (compare_code, DImode,
2403 operands[1] = gen_compare_reg (compare_code, op0, op1);
2405 switch (GET_MODE (operands[1]))
2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2416 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2417 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2418 gen_rtx_fmt_ee (compare_code,
2419 GET_MODE (operands[1]),
2420 operands[1], const0_rtx),
2421 const1_rtx, operands[0])));
2426 /* Emit a conditional jump insn for the v9 architecture using comparison code
2427 CODE and jump target LABEL.
2428 This function exists to take advantage of the v9 brxx insns. */
2431 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2433 emit_jump_insn (gen_rtx_SET (VOIDmode,
2435 gen_rtx_IF_THEN_ELSE (VOIDmode,
2436 gen_rtx_fmt_ee (code, GET_MODE (op0),
2438 gen_rtx_LABEL_REF (VOIDmode, label),
2442 /* Generate a DFmode part of a hard TFmode register.
2443 REG is the TFmode hard register, LOW is 1 for the
2444 low 64bit of the register and 0 otherwise.
2447 gen_df_reg (rtx reg, int low)
2449 int regno = REGNO (reg);
2451 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2452 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2453 return gen_rtx_REG (DFmode, regno);
2456 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2457 Unlike normal calls, TFmode operands are passed by reference. It is
2458 assumed that no more than 3 operands are required. */
2461 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2463 rtx ret_slot = NULL, arg[3], func_sym;
2466 /* We only expect to be called for conversions, unary, and binary ops. */
2467 if (nargs < 2 || nargs > 3)
2470 for (i = 0; i < nargs; ++i)
2472 rtx this_arg = operands[i];
2475 /* TFmode arguments and return values are passed by reference. */
2476 if (GET_MODE (this_arg) == TFmode)
2478 int force_stack_temp;
2480 force_stack_temp = 0;
2481 if (TARGET_BUGGY_QP_LIB && i == 0)
2482 force_stack_temp = 1;
2484 if (GET_CODE (this_arg) == MEM
2485 && ! force_stack_temp)
2486 this_arg = XEXP (this_arg, 0);
2487 else if (CONSTANT_P (this_arg)
2488 && ! force_stack_temp)
2490 this_slot = force_const_mem (TFmode, this_arg);
2491 this_arg = XEXP (this_slot, 0);
2495 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2497 /* Operand 0 is the return value. We'll copy it out later. */
2499 emit_move_insn (this_slot, this_arg);
2501 ret_slot = this_slot;
2503 this_arg = XEXP (this_slot, 0);
2510 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2512 if (GET_MODE (operands[0]) == TFmode)
2515 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2516 arg[0], GET_MODE (arg[0]),
2517 arg[1], GET_MODE (arg[1]));
2519 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2520 arg[0], GET_MODE (arg[0]),
2521 arg[1], GET_MODE (arg[1]),
2522 arg[2], GET_MODE (arg[2]));
2525 emit_move_insn (operands[0], ret_slot);
2534 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2535 GET_MODE (operands[0]), 1,
2536 arg[1], GET_MODE (arg[1]));
2538 if (ret != operands[0])
2539 emit_move_insn (operands[0], ret);
2543 /* Expand soft-float TFmode calls to sparc abi routines. */
2546 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2568 emit_soft_tfmode_libcall (func, 3, operands);
2572 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2585 emit_soft_tfmode_libcall (func, 2, operands);
2589 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2596 switch (GET_MODE (operands[1]))
2609 case FLOAT_TRUNCATE:
2610 switch (GET_MODE (operands[0]))
2624 switch (GET_MODE (operands[1]))
2637 case UNSIGNED_FLOAT:
2638 switch (GET_MODE (operands[1]))
2652 switch (GET_MODE (operands[0]))
2666 switch (GET_MODE (operands[0]))
2683 emit_soft_tfmode_libcall (func, 2, operands);
2686 /* Expand a hard-float tfmode operation. All arguments must be in
2690 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2694 if (GET_RTX_CLASS (code) == RTX_UNARY)
2696 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2697 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2701 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2702 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2703 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2704 operands[1], operands[2]);
2707 if (register_operand (operands[0], VOIDmode))
2710 dest = gen_reg_rtx (GET_MODE (operands[0]));
2712 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2714 if (dest != operands[0])
2715 emit_move_insn (operands[0], dest);
2719 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2721 if (TARGET_HARD_QUAD)
2722 emit_hard_tfmode_operation (code, operands);
2724 emit_soft_tfmode_binop (code, operands);
2728 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2730 if (TARGET_HARD_QUAD)
2731 emit_hard_tfmode_operation (code, operands);
2733 emit_soft_tfmode_unop (code, operands);
2737 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2739 if (TARGET_HARD_QUAD)
2740 emit_hard_tfmode_operation (code, operands);
2742 emit_soft_tfmode_cvt (code, operands);
2745 /* Return nonzero if a return peephole merging return with
2746 setting of output register is ok. */
2748 leaf_return_peephole_ok (void)
2750 return (actual_fsize == 0);
2753 /* Return nonzero if a branch/jump/call instruction will be emitting
2754 nop into its delay slot. */
2757 empty_delay_slot (rtx insn)
2761 /* If no previous instruction (should not happen), return true. */
2762 if (PREV_INSN (insn) == NULL)
2765 seq = NEXT_INSN (PREV_INSN (insn));
2766 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2772 /* Return nonzero if TRIAL can go into the function epilogue's
2773 delay slot. SLOT is the slot we are trying to fill. */
2776 eligible_for_epilogue_delay (rtx trial, int slot)
2783 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2786 if (get_attr_length (trial) != 1)
2789 /* If there are any call-saved registers, we should scan TRIAL if it
2790 does not reference them. For now just make it easy. */
2794 /* If the function uses __builtin_eh_return, the eh_return machinery
2795 occupies the delay slot. */
2796 if (current_function_calls_eh_return)
2799 /* In the case of a true leaf function, anything can go into the delay slot.
2800 A delay slot only exists however if the frame size is zero, otherwise
2801 we will put an insn to adjust the stack after the return. */
2802 if (current_function_uses_only_leaf_regs)
2804 if (leaf_return_peephole_ok ())
2805 return ((get_attr_in_uncond_branch_delay (trial)
2806 == IN_BRANCH_DELAY_TRUE));
2810 pat = PATTERN (trial);
2812 /* Otherwise, only operations which can be done in tandem with
2813 a `restore' or `return' insn can go into the delay slot. */
2814 if (GET_CODE (SET_DEST (pat)) != REG
2815 || REGNO (SET_DEST (pat)) < 24)
2818 /* If this instruction sets up floating point register and we have a return
2819 instruction, it can probably go in. But restore will not work
2821 if (REGNO (SET_DEST (pat)) >= 32)
2823 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2824 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2829 /* The set of insns matched here must agree precisely with the set of
2830 patterns paired with a RETURN in sparc.md. */
2832 src = SET_SRC (pat);
2834 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2835 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2836 && arith_operand (src, GET_MODE (src)))
2839 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2841 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2844 /* This matches "*return_di". */
2845 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2846 && arith_double_operand (src, GET_MODE (src)))
2847 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2849 /* This matches "*return_sf_no_fpu". */
2850 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2851 && register_operand (src, SFmode))
2854 /* If we have return instruction, anything that does not use
2855 local or output registers and can go into a delay slot wins. */
2856 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2857 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2860 /* This matches "*return_addsi". */
2861 else if (GET_CODE (src) == PLUS
2862 && arith_operand (XEXP (src, 0), SImode)
2863 && arith_operand (XEXP (src, 1), SImode)
2864 && (register_operand (XEXP (src, 0), SImode)
2865 || register_operand (XEXP (src, 1), SImode)))
2868 /* This matches "*return_adddi". */
2869 else if (GET_CODE (src) == PLUS
2870 && arith_double_operand (XEXP (src, 0), DImode)
2871 && arith_double_operand (XEXP (src, 1), DImode)
2872 && (register_operand (XEXP (src, 0), DImode)
2873 || register_operand (XEXP (src, 1), DImode)))
2876 /* This can match "*return_losum_[sd]i".
2877 Catch only some cases, so that return_losum* don't have
2879 else if (GET_CODE (src) == LO_SUM
2880 && ! TARGET_CM_MEDMID
2881 && ((register_operand (XEXP (src, 0), SImode)
2882 && immediate_operand (XEXP (src, 1), SImode))
2884 && register_operand (XEXP (src, 0), DImode)
2885 && immediate_operand (XEXP (src, 1), DImode))))
2888 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2889 else if (GET_CODE (src) == ASHIFT
2890 && (register_operand (XEXP (src, 0), SImode)
2891 || register_operand (XEXP (src, 0), DImode))
2892 && XEXP (src, 1) == const1_rtx)
2898 /* Return nonzero if TRIAL can go into the call delay slot. */
2900 tls_call_delay (rtx trial)
2905 call __tls_get_addr, %tgd_call (foo)
2906 add %l7, %o0, %o0, %tgd_add (foo)
2907 while Sun as/ld does not. */
2908 if (TARGET_GNU_TLS || !TARGET_TLS)
2911 pat = PATTERN (trial);
2912 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2915 unspec = XEXP (SET_DEST (pat), 1);
2916 if (GET_CODE (unspec) != UNSPEC
2917 || (XINT (unspec, 1) != UNSPEC_TLSGD
2918 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2924 /* Return nonzero if TRIAL can go into the sibling call
2928 eligible_for_sibcall_delay (rtx trial)
2932 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2935 if (get_attr_length (trial) != 1)
2938 pat = PATTERN (trial);
2940 if (current_function_uses_only_leaf_regs)
2942 /* If the tail call is done using the call instruction,
2943 we have to restore %o7 in the delay slot. */
2944 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2947 /* %g1 is used to build the function address */
2948 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
2954 /* Otherwise, only operations which can be done in tandem with
2955 a `restore' insn can go into the delay slot. */
2956 if (GET_CODE (SET_DEST (pat)) != REG
2957 || REGNO (SET_DEST (pat)) < 24
2958 || REGNO (SET_DEST (pat)) >= 32)
2961 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2963 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
2966 src = SET_SRC (pat);
2968 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2969 && arith_operand (src, GET_MODE (src)))
2972 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2974 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2977 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2978 && arith_double_operand (src, GET_MODE (src)))
2979 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2981 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2982 && register_operand (src, SFmode))
2985 else if (GET_CODE (src) == PLUS
2986 && arith_operand (XEXP (src, 0), SImode)
2987 && arith_operand (XEXP (src, 1), SImode)
2988 && (register_operand (XEXP (src, 0), SImode)
2989 || register_operand (XEXP (src, 1), SImode)))
2992 else if (GET_CODE (src) == PLUS
2993 && arith_double_operand (XEXP (src, 0), DImode)
2994 && arith_double_operand (XEXP (src, 1), DImode)
2995 && (register_operand (XEXP (src, 0), DImode)
2996 || register_operand (XEXP (src, 1), DImode)))
2999 else if (GET_CODE (src) == LO_SUM
3000 && ! TARGET_CM_MEDMID
3001 && ((register_operand (XEXP (src, 0), SImode)
3002 && immediate_operand (XEXP (src, 1), SImode))
3004 && register_operand (XEXP (src, 0), DImode)
3005 && immediate_operand (XEXP (src, 1), DImode))))
3008 else if (GET_CODE (src) == ASHIFT
3009 && (register_operand (XEXP (src, 0), SImode)
3010 || register_operand (XEXP (src, 0), DImode))
3011 && XEXP (src, 1) == const1_rtx)
3018 check_return_regs (rtx x)
3020 switch (GET_CODE (x))
3023 return IN_OR_GLOBAL_P (x);
3038 if (check_return_regs (XEXP (x, 1)) == 0)
3043 return check_return_regs (XEXP (x, 0));
3052 short_branch (int uid1, int uid2)
3054 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3056 /* Leave a few words of "slop". */
3057 if (delta >= -1023 && delta <= 1022)
3063 /* Return nonzero if REG is not used after INSN.
3064 We assume REG is a reload reg, and therefore does
3065 not live past labels or calls or jumps. */
3067 reg_unused_after (rtx reg, rtx insn)
3069 enum rtx_code code, prev_code = UNKNOWN;
3071 while ((insn = NEXT_INSN (insn)))
3073 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3076 code = GET_CODE (insn);
3077 if (GET_CODE (insn) == CODE_LABEL)
3082 rtx set = single_set (insn);
3083 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3086 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3088 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3096 /* Determine if it's legal to put X into the constant pool. This
3097 is not possible if X contains the address of a symbol that is
3098 not constant (TLS) or not known at final link time (PIC). */
3101 sparc_cannot_force_const_mem (rtx x)
3103 switch (GET_CODE (x))
3107 /* Accept all non-symbolic constants. */
3111 /* Labels are OK iff we are non-PIC. */
3112 return flag_pic != 0;
3115 /* 'Naked' TLS symbol references are never OK,
3116 non-TLS symbols are OK iff we are non-PIC. */
3117 if (SYMBOL_REF_TLS_MODEL (x))
3120 return flag_pic != 0;
3123 return sparc_cannot_force_const_mem (XEXP (x, 0));
3126 return sparc_cannot_force_const_mem (XEXP (x, 0))
3127 || sparc_cannot_force_const_mem (XEXP (x, 1));
3135 /* The table we use to reference PIC data. */
3136 static GTY(()) rtx global_offset_table;
3138 /* The function we use to get at it. */
3139 static GTY(()) rtx get_pc_symbol;
3140 static GTY(()) char get_pc_symbol_name[256];
3142 /* Ensure that we are not using patterns that are not OK with PIC. */
3150 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3151 || (GET_CODE (recog_data.operand[i]) == CONST
3152 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3153 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3154 == global_offset_table)
3155 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3164 /* Return true if X is an address which needs a temporary register when
3165 reloaded while generating PIC code. */
3168 pic_address_needs_scratch (rtx x)
3170 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3171 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3172 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3173 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3174 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3180 /* Determine if a given RTX is a valid constant. We already know this
3181 satisfies CONSTANT_P. */
3184 legitimate_constant_p (rtx x)
3188 switch (GET_CODE (x))
3191 /* TLS symbols are not constant. */
3192 if (SYMBOL_REF_TLS_MODEL (x))
3197 inner = XEXP (x, 0);
3199 /* Offsets of TLS symbols are never valid.
3200 Discourage CSE from creating them. */
3201 if (GET_CODE (inner) == PLUS
3202 && tls_symbolic_operand (XEXP (inner, 0)))
3207 if (GET_MODE (x) == VOIDmode)
3210 /* Floating point constants are generally not ok.
3211 The only exception is 0.0 in VIS. */
3213 && (GET_MODE (x) == SFmode
3214 || GET_MODE (x) == DFmode
3215 || GET_MODE (x) == TFmode)
3216 && fp_zero_operand (x, GET_MODE (x)))
3228 /* Determine if a given RTX is a valid constant address. */
3231 constant_address_p (rtx x)
3233 switch (GET_CODE (x))
3241 if (flag_pic && pic_address_needs_scratch (x))
3243 return legitimate_constant_p (x);
3246 return !flag_pic && legitimate_constant_p (x);
3253 /* Nonzero if the constant value X is a legitimate general operand
3254 when generating PIC code. It is given that flag_pic is on and
3255 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3258 legitimate_pic_operand_p (rtx x)
3260 if (pic_address_needs_scratch (x))
3262 if (tls_symbolic_operand (x)
3263 || (GET_CODE (x) == CONST
3264 && GET_CODE (XEXP (x, 0)) == PLUS
3265 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3270 /* Return nonzero if ADDR is a valid memory address.
3271 STRICT specifies whether strict register checking applies. */
3274 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3276 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3278 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3280 else if (GET_CODE (addr) == PLUS)
3282 rs1 = XEXP (addr, 0);
3283 rs2 = XEXP (addr, 1);
3285 /* Canonicalize. REG comes first, if there are no regs,
3286 LO_SUM comes first. */
3288 && GET_CODE (rs1) != SUBREG
3290 || GET_CODE (rs2) == SUBREG
3291 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3293 rs1 = XEXP (addr, 1);
3294 rs2 = XEXP (addr, 0);
3298 && rs1 == pic_offset_table_rtx
3300 && GET_CODE (rs2) != SUBREG
3301 && GET_CODE (rs2) != LO_SUM
3302 && GET_CODE (rs2) != MEM
3303 && !tls_symbolic_operand (rs2)
3304 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3305 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3307 || GET_CODE (rs1) == SUBREG)
3308 && RTX_OK_FOR_OFFSET_P (rs2)))
3313 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3314 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3316 /* We prohibit REG + REG for TFmode when there are no instructions
3317 which accept REG+REG instructions. We do this because REG+REG
3318 is not an offsetable address. If we get the situation in reload
3319 where source and destination of a movtf pattern are both MEMs with
3320 REG+REG address, then only one of them gets converted to an
3321 offsetable address. */
3323 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3324 && TARGET_HARD_QUAD))
3327 /* We prohibit REG + REG on ARCH32 if not optimizing for
3328 DFmode/DImode because then mem_min_alignment is likely to be zero
3329 after reload and the forced split would lack a matching splitter
3331 if (TARGET_ARCH32 && !optimize
3332 && (mode == DFmode || mode == DImode))
3335 else if (USE_AS_OFFSETABLE_LO10
3336 && GET_CODE (rs1) == LO_SUM
3338 && ! TARGET_CM_MEDMID
3339 && RTX_OK_FOR_OLO10_P (rs2))
3343 imm1 = XEXP (rs1, 1);
3344 rs1 = XEXP (rs1, 0);
3345 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3349 else if (GET_CODE (addr) == LO_SUM)
3351 rs1 = XEXP (addr, 0);
3352 imm1 = XEXP (addr, 1);
3354 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3357 /* We can't allow TFmode, because an offset greater than or equal to the
3358 alignment (8) may cause the LO_SUM to overflow if !v9. */
3359 if (mode == TFmode && !TARGET_V9)
3362 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3367 if (GET_CODE (rs1) == SUBREG)
3368 rs1 = SUBREG_REG (rs1);
3374 if (GET_CODE (rs2) == SUBREG)
3375 rs2 = SUBREG_REG (rs2);
3382 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3383 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3388 if ((REGNO (rs1) >= 32
3389 && REGNO (rs1) != FRAME_POINTER_REGNUM
3390 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3392 && (REGNO (rs2) >= 32
3393 && REGNO (rs2) != FRAME_POINTER_REGNUM
3394 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3400 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3402 static GTY(()) rtx sparc_tls_symbol;
3404 sparc_tls_get_addr (void)
3406 if (!sparc_tls_symbol)
3407 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3409 return sparc_tls_symbol;
3413 sparc_tls_got (void)
3418 current_function_uses_pic_offset_table = 1;
3419 return pic_offset_table_rtx;
3422 if (!global_offset_table)
3423 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3424 temp = gen_reg_rtx (Pmode);
3425 emit_move_insn (temp, global_offset_table);
3430 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3431 this (thread-local) address. */
3434 legitimize_tls_address (rtx addr)
3436 rtx temp1, temp2, temp3, ret, o0, got, insn;
3441 if (GET_CODE (addr) == SYMBOL_REF)
3442 switch (SYMBOL_REF_TLS_MODEL (addr))
3444 case TLS_MODEL_GLOBAL_DYNAMIC:
3446 temp1 = gen_reg_rtx (SImode);
3447 temp2 = gen_reg_rtx (SImode);
3448 ret = gen_reg_rtx (Pmode);
3449 o0 = gen_rtx_REG (Pmode, 8);
3450 got = sparc_tls_got ();
3451 emit_insn (gen_tgd_hi22 (temp1, addr));
3452 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3455 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3456 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3461 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3462 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3465 CALL_INSN_FUNCTION_USAGE (insn)
3466 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3467 CALL_INSN_FUNCTION_USAGE (insn));
3468 insn = get_insns ();
3470 emit_libcall_block (insn, ret, o0, addr);
3473 case TLS_MODEL_LOCAL_DYNAMIC:
3475 temp1 = gen_reg_rtx (SImode);
3476 temp2 = gen_reg_rtx (SImode);
3477 temp3 = gen_reg_rtx (Pmode);
3478 ret = gen_reg_rtx (Pmode);
3479 o0 = gen_rtx_REG (Pmode, 8);
3480 got = sparc_tls_got ();
3481 emit_insn (gen_tldm_hi22 (temp1));
3482 emit_insn (gen_tldm_lo10 (temp2, temp1));
3485 emit_insn (gen_tldm_add32 (o0, got, temp2));
3486 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3491 emit_insn (gen_tldm_add64 (o0, got, temp2));
3492 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3495 CALL_INSN_FUNCTION_USAGE (insn)
3496 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3497 CALL_INSN_FUNCTION_USAGE (insn));
3498 insn = get_insns ();
3500 emit_libcall_block (insn, temp3, o0,
3501 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3502 UNSPEC_TLSLD_BASE));
3503 temp1 = gen_reg_rtx (SImode);
3504 temp2 = gen_reg_rtx (SImode);
3505 emit_insn (gen_tldo_hix22 (temp1, addr));
3506 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3508 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3510 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3513 case TLS_MODEL_INITIAL_EXEC:
3514 temp1 = gen_reg_rtx (SImode);
3515 temp2 = gen_reg_rtx (SImode);
3516 temp3 = gen_reg_rtx (Pmode);
3517 got = sparc_tls_got ();
3518 emit_insn (gen_tie_hi22 (temp1, addr));
3519 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3521 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3523 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3526 ret = gen_reg_rtx (Pmode);
3528 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3531 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3535 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3538 case TLS_MODEL_LOCAL_EXEC:
3539 temp1 = gen_reg_rtx (Pmode);
3540 temp2 = gen_reg_rtx (Pmode);
3543 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3544 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3548 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3549 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3551 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3559 abort (); /* for now ... */
3565 /* Legitimize PIC addresses. If the address is already position-independent,
3566 we return ORIG. Newly generated position-independent addresses go into a
3567 reg. This is REG if nonzero, otherwise we allocate register(s) as
3571 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3574 if (GET_CODE (orig) == SYMBOL_REF)
3576 rtx pic_ref, address;
3581 if (reload_in_progress || reload_completed)
3584 reg = gen_reg_rtx (Pmode);
3589 /* If not during reload, allocate another temp reg here for loading
3590 in the address, so that these instructions can be optimized
3592 rtx temp_reg = ((reload_in_progress || reload_completed)
3593 ? reg : gen_reg_rtx (Pmode));
3595 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3596 won't get confused into thinking that these two instructions
3597 are loading in the true address of the symbol. If in the
3598 future a PIC rtx exists, that should be used instead. */
3599 if (Pmode == SImode)
3601 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3602 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3606 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3607 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3614 pic_ref = gen_rtx_MEM (Pmode,
3615 gen_rtx_PLUS (Pmode,
3616 pic_offset_table_rtx, address));
3617 current_function_uses_pic_offset_table = 1;
3618 RTX_UNCHANGING_P (pic_ref) = 1;
3619 insn = emit_move_insn (reg, pic_ref);
3620 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3622 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3626 else if (GET_CODE (orig) == CONST)
3630 if (GET_CODE (XEXP (orig, 0)) == PLUS
3631 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3636 if (reload_in_progress || reload_completed)
3639 reg = gen_reg_rtx (Pmode);
3642 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3644 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3645 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3646 base == reg ? 0 : reg);
3651 if (GET_CODE (offset) == CONST_INT)
3653 if (SMALL_INT (offset))
3654 return plus_constant (base, INTVAL (offset));
3655 else if (! reload_in_progress && ! reload_completed)
3656 offset = force_reg (Pmode, offset);
3658 /* If we reach here, then something is seriously wrong. */
3661 return gen_rtx_PLUS (Pmode, base, offset);
3663 else if (GET_CODE (orig) == LABEL_REF)
3664 /* ??? Why do we do this? */
3665 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3666 the register is live instead, in case it is eliminated. */
3667 current_function_uses_pic_offset_table = 1;
3672 /* Try machine-dependent ways of modifying an illegitimate address X
3673 to be legitimate. If we find one, return the new, valid address.
3675 OLDX is the address as it was before break_out_memory_refs was called.
3676 In some cases it is useful to look at this to decide what needs to be done.
3678 MODE is the mode of the operand pointed to by X. */
3681 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3685 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3686 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3687 force_operand (XEXP (x, 0), NULL_RTX));
3688 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3689 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3690 force_operand (XEXP (x, 1), NULL_RTX));
3691 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3692 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3694 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3695 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3696 force_operand (XEXP (x, 1), NULL_RTX));
3698 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3701 if (tls_symbolic_operand (x))
3702 x = legitimize_tls_address (x);
3704 x = legitimize_pic_address (x, mode, 0);
3705 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3706 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3707 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3708 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3709 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3710 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3711 else if (GET_CODE (x) == SYMBOL_REF
3712 || GET_CODE (x) == CONST
3713 || GET_CODE (x) == LABEL_REF)
3714 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3718 /* Emit special PIC prologues. */
3721 load_pic_register (void)
3723 /* Labels to get the PC in the prologue of this function. */
3724 int orig_flag_pic = flag_pic;
3729 /* If we haven't emitted the special get_pc helper function, do so now. */
3730 if (get_pc_symbol_name[0] == 0)
3734 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3737 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3739 ASM_OUTPUT_ALIGN (asm_out_file, align);
3740 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3741 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3744 /* Initialize every time through, since we can't easily
3745 know this to be permanent. */
3746 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3747 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3750 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3753 flag_pic = orig_flag_pic;
3755 /* Need to emit this whether or not we obey regdecls,
3756 since setjmp/longjmp can cause life info to screw up.
3757 ??? In the case where we don't obey regdecls, this is not sufficient
3758 since we may not fall out the bottom. */
3759 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3762 /* Return 1 if RTX is a MEM which is known to be aligned to at
3763 least a DESIRED byte boundary. */
3766 mem_min_alignment (rtx mem, int desired)
3768 rtx addr, base, offset;
3770 /* If it's not a MEM we can't accept it. */
3771 if (GET_CODE (mem) != MEM)
3774 addr = XEXP (mem, 0);
3775 base = offset = NULL_RTX;
3776 if (GET_CODE (addr) == PLUS)
3778 if (GET_CODE (XEXP (addr, 0)) == REG)
3780 base = XEXP (addr, 0);
3782 /* What we are saying here is that if the base
3783 REG is aligned properly, the compiler will make
3784 sure any REG based index upon it will be so
3786 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3787 offset = XEXP (addr, 1);
3789 offset = const0_rtx;
3792 else if (GET_CODE (addr) == REG)
3795 offset = const0_rtx;
3798 if (base != NULL_RTX)
3800 int regno = REGNO (base);
3802 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3804 /* Check if the compiler has recorded some information
3805 about the alignment of the base REG. If reload has
3806 completed, we already matched with proper alignments.
3807 If not running global_alloc, reload might give us
3808 unaligned pointer to local stack though. */
3810 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3811 || (optimize && reload_completed))
3812 && (INTVAL (offset) & (desired - 1)) == 0)
3817 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3821 else if (! TARGET_UNALIGNED_DOUBLES
3822 || CONSTANT_P (addr)
3823 || GET_CODE (addr) == LO_SUM)
3825 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3826 is true, in which case we can only assume that an access is aligned if
3827 it is to a constant address, or the address involves a LO_SUM. */
3831 /* An obviously unaligned address. */
3836 /* Vectors to keep interesting information about registers where it can easily
3837 be got. We used to use the actual mode value as the bit number, but there
3838 are more than 32 modes now. Instead we use two tables: one indexed by
3839 hard register number, and one indexed by mode. */
3841 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3842 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3843 mapped into one sparc_mode_class mode. */
3845 enum sparc_mode_class {
3846 S_MODE, D_MODE, T_MODE, O_MODE,
3847 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3851 /* Modes for single-word and smaller quantities. */
3852 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3854 /* Modes for double-word and smaller quantities. */
3855 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3857 /* Modes for quad-word and smaller quantities. */
3858 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3860 /* Modes for 8-word and smaller quantities. */
3861 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3863 /* Modes for single-float quantities. We must allow any single word or
3864 smaller quantity. This is because the fix/float conversion instructions
3865 take integer inputs/outputs from the float registers. */
3866 #define SF_MODES (S_MODES)
3868 /* Modes for double-float and smaller quantities. */
3869 #define DF_MODES (S_MODES | D_MODES)
3871 /* Modes for double-float only quantities. */
3872 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3874 /* Modes for quad-float only quantities. */
3875 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3877 /* Modes for quad-float and smaller quantities. */
3878 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3880 /* Modes for quad-float and double-float quantities. */
3881 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3883 /* Modes for quad-float pair only quantities. */
3884 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3886 /* Modes for quad-float pairs and smaller quantities. */
3887 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3889 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3891 /* Modes for condition codes. */
3892 #define CC_MODES (1 << (int) CC_MODE)
3893 #define CCFP_MODES (1 << (int) CCFP_MODE)
3895 /* Value is 1 if register/mode pair is acceptable on sparc.
3896 The funny mixture of D and T modes is because integer operations
3897 do not specially operate on tetra quantities, so non-quad-aligned
3898 registers can hold quadword quantities (except %o4 and %i4 because
3899 they cross fixed registers). */
3901 /* This points to either the 32 bit or the 64 bit version. */
3902 const int *hard_regno_mode_classes;
3904 static const int hard_32bit_mode_classes[] = {
3905 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3906 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3907 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3908 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3910 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3911 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3912 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3913 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3915 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3916 and none can hold SFmode/SImode values. */
3917 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3918 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3919 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3920 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3923 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3929 static const int hard_64bit_mode_classes[] = {
3930 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3931 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3932 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3933 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3935 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3936 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3937 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3938 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3940 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3941 and none can hold SFmode/SImode values. */
3942 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3943 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3944 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3945 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3948 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3954 int sparc_mode_class [NUM_MACHINE_MODES];
3956 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3959 sparc_init_modes (void)
3963 for (i = 0; i < NUM_MACHINE_MODES; i++)
3965 switch (GET_MODE_CLASS (i))
3968 case MODE_PARTIAL_INT:
3969 case MODE_COMPLEX_INT:
3970 if (GET_MODE_SIZE (i) <= 4)
3971 sparc_mode_class[i] = 1 << (int) S_MODE;
3972 else if (GET_MODE_SIZE (i) == 8)
3973 sparc_mode_class[i] = 1 << (int) D_MODE;
3974 else if (GET_MODE_SIZE (i) == 16)
3975 sparc_mode_class[i] = 1 << (int) T_MODE;
3976 else if (GET_MODE_SIZE (i) == 32)
3977 sparc_mode_class[i] = 1 << (int) O_MODE;
3979 sparc_mode_class[i] = 0;
3982 case MODE_COMPLEX_FLOAT:
3983 if (GET_MODE_SIZE (i) <= 4)
3984 sparc_mode_class[i] = 1 << (int) SF_MODE;
3985 else if (GET_MODE_SIZE (i) == 8)
3986 sparc_mode_class[i] = 1 << (int) DF_MODE;
3987 else if (GET_MODE_SIZE (i) == 16)
3988 sparc_mode_class[i] = 1 << (int) TF_MODE;
3989 else if (GET_MODE_SIZE (i) == 32)
3990 sparc_mode_class[i] = 1 << (int) OF_MODE;
3992 sparc_mode_class[i] = 0;
3995 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3996 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3998 sparc_mode_class[i] = 1 << (int) CC_MODE;
4001 sparc_mode_class[i] = 0;
4007 hard_regno_mode_classes = hard_64bit_mode_classes;
4009 hard_regno_mode_classes = hard_32bit_mode_classes;
4011 /* Initialize the array used by REGNO_REG_CLASS. */
4012 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4014 if (i < 16 && TARGET_V8PLUS)
4015 sparc_regno_reg_class[i] = I64_REGS;
4016 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4017 sparc_regno_reg_class[i] = GENERAL_REGS;
4019 sparc_regno_reg_class[i] = FP_REGS;
4021 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4023 sparc_regno_reg_class[i] = FPCC_REGS;
4025 sparc_regno_reg_class[i] = NO_REGS;
4029 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4030 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4031 v9 int regs as it simplifies the code. */
4034 save_regs (FILE *file, int low, int high, const char *base,
4035 int offset, int n_regs, HOST_WIDE_INT real_offset)
4039 if (TARGET_ARCH64 && high <= 32)
4041 for (i = low; i < high; i++)
4043 if (regs_ever_live[i] && ! call_used_regs[i])
4045 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4046 reg_names[i], base, offset + 4 * n_regs);
4047 if (dwarf2out_do_frame ())
4048 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4055 for (i = low; i < high; i += 2)
4057 if (regs_ever_live[i] && ! call_used_regs[i])
4059 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4061 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4062 reg_names[i], base, offset + 4 * n_regs);
4063 if (dwarf2out_do_frame ())
4065 char *l = dwarf2out_cfi_label ();
4066 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4067 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4073 fprintf (file, "\tst\t%s, [%s+%d]\n",
4074 reg_names[i], base, offset + 4 * n_regs);
4075 if (dwarf2out_do_frame ())
4076 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4082 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4084 fprintf (file, "\tst\t%s, [%s+%d]\n",
4085 reg_names[i+1], base, offset + 4 * n_regs + 4);
4086 if (dwarf2out_do_frame ())
4087 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4096 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4098 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4099 v9 int regs as it simplifies the code. */
4102 restore_regs (FILE *file, int low, int high, const char *base,
4103 int offset, int n_regs)
4107 if (TARGET_ARCH64 && high <= 32)
4109 for (i = low; i < high; i++)
4111 if (regs_ever_live[i] && ! call_used_regs[i])
4112 fprintf (file, "\tldx\t[%s+%d], %s\n",
4113 base, offset + 4 * n_regs, reg_names[i]),
4119 for (i = low; i < high; i += 2)
4121 if (regs_ever_live[i] && ! call_used_regs[i])
4122 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4123 fprintf (file, "\tldd\t[%s+%d], %s\n",
4124 base, offset + 4 * n_regs, reg_names[i]),
4127 fprintf (file, "\tld\t[%s+%d], %s\n",
4128 base, offset + 4 * n_regs, reg_names[i]),
4130 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4131 fprintf (file, "\tld\t[%s+%d], %s\n",
4132 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4139 /* Compute the frame size required by the function. This function is called
4140 during the reload pass and also by output_function_prologue(). */
4143 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4146 int outgoing_args_size = (current_function_outgoing_args_size
4147 + REG_PARM_STACK_SPACE (current_function_decl));
4149 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4150 even to v9 int regs to be consistent with save_regs/restore_regs. */
4154 for (i = 0; i < 8; i++)
4155 if (regs_ever_live[i] && ! call_used_regs[i])
4160 for (i = 0; i < 8; i += 2)
4161 if ((regs_ever_live[i] && ! call_used_regs[i])
4162 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4166 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4167 if ((regs_ever_live[i] && ! call_used_regs[i])
4168 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4171 /* Set up values for use in `function_epilogue'. */
4172 num_gfregs = n_regs;
4174 if (leaf_function && n_regs == 0
4175 && size == 0 && current_function_outgoing_args_size == 0)
4177 actual_fsize = apparent_fsize = 0;
4181 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4182 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4183 apparent_fsize += n_regs * 4;
4184 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4187 /* Make sure nothing can clobber our register windows.
4188 If a SAVE must be done, or there is a stack-local variable,
4189 the register window area must be allocated.
4190 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4191 if (leaf_function == 0 || size > 0)
4192 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4194 return SPARC_STACK_ALIGN (actual_fsize);
4197 /* Build big number NUM in register REG and output the result to FILE.
4198 REG is guaranteed to be the only clobbered register. The function
4199 will very likely emit several instructions, so it must not be called
4200 from within a delay slot. */
4203 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4205 #if HOST_BITS_PER_WIDE_INT == 64
4206 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4214 /* We don't use the 'set' macro because it appears to be broken
4215 in the Solaris 7 assembler. */
4216 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4218 if ((num & 0x3ff) != 0)
4219 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4222 #if HOST_BITS_PER_WIDE_INT == 64
4223 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4225 else /* num < 0 && TARGET_ARCH64 */
4228 /* Sethi does not sign extend, so we must use a little trickery
4229 to use it for negative numbers. Invert the constant before
4230 loading it in, then use xor immediate to invert the loaded bits
4231 (along with the upper 32 bits) to the desired constant. This
4232 works because the sethi and immediate fields overlap. */
4233 HOST_WIDE_INT inv = ~num;
4234 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4236 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4238 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4241 #if HOST_BITS_PER_WIDE_INT == 64
4242 else /* TARGET_ARCH64 */
4244 /* We don't use the 'setx' macro because if requires a scratch register.
4245 This is the translation of sparc_emit_set_const64_longway into asm.
4246 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4247 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4248 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4249 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4252 /* We don't use the 'set' macro because it appears to be broken
4253 in the Solaris 7 assembler. */
4254 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4256 if ((high_bits & 0x3ff) != 0)
4257 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4258 reg, high_bits, reg);
4262 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4263 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4273 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4274 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4282 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4284 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4290 /* Output any necessary .register pseudo-ops. */
4292 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4294 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4300 /* Check if %g[2367] were used without
4301 .register being printed for them already. */
4302 for (i = 2; i < 8; i++)
4304 if (regs_ever_live [i]
4305 && ! sparc_hard_reg_printed [i])
4307 sparc_hard_reg_printed [i] = 1;
4308 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4315 /* This function generates the assembly code for function entry.
4316 FILE is a stdio stream to output the code to.
4317 SIZE is an int: how many units of temporary storage to allocate.
4318 Refer to the array `regs_ever_live' to determine which registers
4319 to save; `regs_ever_live[I]' is nonzero if register number I
4320 is ever used in the function. This macro is responsible for
4321 knowing which registers should not be saved even if used. */
4323 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4324 of memory. If any fpu reg is used in the function, we allocate
4325 such a block here, at the bottom of the frame, just in case it's needed.
4327 If this function is a leaf procedure, then we may choose not
4328 to do a "save" insn. The decision about whether or not
4329 to do this is made in regclass.c. */
4332 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4334 sparc_function_prologue (file, size,
4335 current_function_uses_only_leaf_regs);
4338 /* Output code for the function prologue. */
4341 sparc_function_prologue (FILE *file, HOST_WIDE_INT size, int leaf_function)
4343 sparc_output_scratch_registers (file);
4345 /* Need to use actual_fsize, since we are also allocating
4346 space for our callee (and our own register save area). */
4347 actual_fsize = compute_frame_size (size, leaf_function);
4351 frame_base_name = "%sp";
4352 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4356 frame_base_name = "%fp";
4357 frame_base_offset = SPARC_STACK_BIAS;
4360 /* This is only for the human reader. */
4361 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4363 if (actual_fsize == 0)
4365 else if (! leaf_function)
4367 if (actual_fsize <= 4096)
4368 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4370 else if (actual_fsize <= 8192)
4372 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4373 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4374 actual_fsize - 4096);
4378 build_big_number (file, -actual_fsize, "%g1");
4379 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4382 else /* leaf function */
4384 if (actual_fsize <= 4096)
4385 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4387 else if (actual_fsize <= 8192)
4389 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4390 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4391 actual_fsize - 4096);
4395 build_big_number (file, -actual_fsize, "%g1");
4396 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4400 if (dwarf2out_do_frame () && actual_fsize)
4402 char *label = dwarf2out_cfi_label ();
4404 /* The canonical frame address refers to the top of the frame. */
4405 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4406 : HARD_FRAME_POINTER_REGNUM),
4409 if (! leaf_function)
4411 /* Note the register window save. This tells the unwinder that
4412 it needs to restore the window registers from the previous
4413 frame's window save area at 0(cfa). */
4414 dwarf2out_window_save (label);
4416 /* The return address (-8) is now in %i7. */
4417 dwarf2out_return_reg (label, 31);
4421 /* If doing anything with PIC, do it now. */
4423 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4425 /* Call saved registers are saved just above the outgoing argument area. */
4428 HOST_WIDE_INT offset, real_offset;
4432 real_offset = -apparent_fsize;
4433 offset = -apparent_fsize + frame_base_offset;
4434 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4436 /* ??? This might be optimized a little as %g1 might already have a
4437 value close enough that a single add insn will do. */
4438 /* ??? Although, all of this is probably only a temporary fix
4439 because if %g1 can hold a function result, then
4440 output_function_epilogue will lose (the result will get
4442 build_big_number (file, offset, "%g1");
4443 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4449 base = frame_base_name;
4452 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4453 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4458 /* Output code to restore any call saved registers. */
4461 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4463 HOST_WIDE_INT offset;
4467 offset = -apparent_fsize + frame_base_offset;
4468 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4470 build_big_number (file, offset, "%g1");
4471 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4477 base = frame_base_name;
4480 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4481 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4484 /* This function generates the assembly code for function exit,
4485 on machines that need it.
4487 The function epilogue should not depend on the current stack pointer!
4488 It should use the frame pointer only. This is mandatory because
4489 of alloca; we also take advantage of it to omit stack adjustments
4490 before returning. */
4493 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4495 sparc_function_epilogue (file, size,
4496 current_function_uses_only_leaf_regs);
4499 /* Output code for the function epilogue. */
4502 sparc_function_epilogue (FILE *file,
4503 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4508 if (current_function_epilogue_delay_list == 0)
4510 /* If code does not drop into the epilogue, we need
4511 do nothing except output pending case vectors.
4513 We have to still output a dummy nop for the sake of
4514 sane backtraces. Otherwise, if the last two instructions
4515 of a function were call foo; dslot; this can make the return
4516 PC of foo (ie. address of call instruction plus 8) point to
4517 the first instruction in the next function. */
4518 rtx insn, last_real_insn;
4520 insn = get_last_insn ();
4522 last_real_insn = prev_real_insn (insn);
4524 && GET_CODE (last_real_insn) == INSN
4525 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4526 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4528 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4529 fputs("\tnop\n", file);
4531 if (GET_CODE (insn) == NOTE)
4532 insn = prev_nonnote_insn (insn);
4533 if (insn && GET_CODE (insn) == BARRIER)
4534 goto output_vectors;
4538 output_restore_regs (file, leaf_function);
4540 /* Work out how to skip the caller's unimp instruction if required. */
4542 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4544 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4546 if (! leaf_function)
4548 if (current_function_calls_eh_return)
4550 if (current_function_epilogue_delay_list)
4552 if (SKIP_CALLERS_UNIMP_P)
4555 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4557 /* If we wound up with things in our delay slot, flush them here. */
4558 else if (current_function_epilogue_delay_list)
4560 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4562 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4564 epilogue_renumber (&delay, 0);
4565 fputs (SKIP_CALLERS_UNIMP_P
4566 ? "\treturn\t%i7+12\n"
4567 : "\treturn\t%i7+8\n", file);
4568 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4569 file, 1, 0, 0, NULL);
4575 if (GET_CODE (delay) != SET)
4578 src = SET_SRC (delay);
4579 if (GET_CODE (src) == ASHIFT)
4581 if (XEXP (src, 1) != const1_rtx)
4584 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4588 insn = gen_rtx_PARALLEL (VOIDmode,
4589 gen_rtvec (2, delay,
4590 gen_rtx_RETURN (VOIDmode)));
4591 insn = emit_jump_insn (insn);
4593 sparc_emitting_epilogue = true;
4594 final_scan_insn (insn, file, 1, 0, 1, NULL);
4595 sparc_emitting_epilogue = false;
4598 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4599 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4601 fprintf (file, "\t%s\n\trestore\n", ret);
4603 /* All of the following cases are for leaf functions. */
4604 else if (current_function_calls_eh_return)
4606 else if (current_function_epilogue_delay_list)
4608 /* eligible_for_epilogue_delay_slot ensures that if this is a
4609 leaf function, then we will only have insn in the delay slot
4610 if the frame size is zero, thus no adjust for the stack is
4612 if (actual_fsize != 0)
4614 fprintf (file, "\t%s\n", ret);
4615 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4616 file, 1, 0, 1, NULL);
4618 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4619 avoid generating confusing assembly language output. */
4620 else if (actual_fsize == 0)
4621 fprintf (file, "\t%s\n\tnop\n", ret);
4622 else if (actual_fsize <= 4096)
4623 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4625 else if (actual_fsize <= 8192)
4626 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4627 ret, actual_fsize - 4096);
4630 build_big_number (file, actual_fsize, "%g1");
4631 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4635 sparc_output_deferred_case_vectors ();
4638 /* Output a sibling call. */
4641 output_sibcall (rtx insn, rtx call_operand)
4643 int leaf_regs = current_function_uses_only_leaf_regs;
4645 int delay_slot = dbr_sequence_length () > 0;
4649 /* Call to restore global regs might clobber
4650 the delay slot. Instead of checking for this
4651 output the delay slot now. */
4654 rtx delay = NEXT_INSN (insn);
4659 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4660 PATTERN (delay) = gen_blockage ();
4661 INSN_CODE (delay) = -1;
4664 output_restore_regs (asm_out_file, leaf_regs);
4667 operands[0] = call_operand;
4671 #ifdef HAVE_AS_RELAX_OPTION
4672 /* If as and ld are relaxing tail call insns into branch always,
4673 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4674 be optimized. With sethi/jmpl as nor ld has no easy way how to
4675 find out if somebody does not branch between the sethi and jmpl. */
4678 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4680 HOST_WIDE_INT size = 0;
4682 if ((actual_fsize || ! spare_slot) && delay_slot)
4684 rtx delay = NEXT_INSN (insn);
4689 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4690 PATTERN (delay) = gen_blockage ();
4691 INSN_CODE (delay) = -1;
4696 if (actual_fsize <= 4096)
4697 size = actual_fsize;
4698 else if (actual_fsize <= 8192)
4700 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4701 size = actual_fsize - 4096;
4705 build_big_number (asm_out_file, actual_fsize, "%g1");
4706 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4711 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4712 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4714 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4715 else if (! delay_slot)
4716 fputs ("\t nop\n", asm_out_file);
4721 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4722 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4723 it into branch if possible. */
4724 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4725 output_asm_insn ("call\t%a0, 0", operands);
4726 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4731 output_asm_insn ("call\t%a0, 0", operands);
4734 rtx delay = NEXT_INSN (insn), pat;
4739 pat = PATTERN (delay);
4740 if (GET_CODE (pat) != SET)
4743 operands[0] = SET_DEST (pat);
4744 pat = SET_SRC (pat);
4745 switch (GET_CODE (pat))
4748 operands[1] = XEXP (pat, 0);
4749 operands[2] = XEXP (pat, 1);
4750 output_asm_insn (" restore %r1, %2, %Y0", operands);
4753 operands[1] = XEXP (pat, 0);
4754 operands[2] = XEXP (pat, 1);
4755 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4758 operands[1] = XEXP (pat, 0);
4759 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4763 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4766 PATTERN (delay) = gen_blockage ();
4767 INSN_CODE (delay) = -1;
4770 fputs ("\t restore\n", asm_out_file);
4774 /* Functions for handling argument passing.
4776 For 32-bit, the first 6 args are normally in registers and the rest are
4777 pushed. Any arg that starts within the first 6 words is at least
4778 partially passed in a register unless its data type forbids.
4780 For 64-bit, the argument registers are laid out as an array of 16 elements
4781 and arguments are added sequentially. The first 6 int args and up to the
4782 first 16 fp args (depending on size) are passed in regs.
4784 Slot Stack Integral Float Float in structure Double Long Double
4785 ---- ----- -------- ----- ------------------ ------ -----------
4786 15 [SP+248] %f31 %f30,%f31 %d30
4787 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4788 13 [SP+232] %f27 %f26,%f27 %d26
4789 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4790 11 [SP+216] %f23 %f22,%f23 %d22
4791 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4792 9 [SP+200] %f19 %f18,%f19 %d18
4793 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4794 7 [SP+184] %f15 %f14,%f15 %d14
4795 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4796 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4797 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4798 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4799 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4800 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4801 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4803 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4805 Integral arguments are always passed as 64-bit quantities appropriately
4808 Passing of floating point values is handled as follows.
4809 If a prototype is in scope:
4810 If the value is in a named argument (i.e. not a stdarg function or a
4811 value not part of the `...') then the value is passed in the appropriate
4813 If the value is part of the `...' and is passed in one of the first 6
4814 slots then the value is passed in the appropriate int reg.
4815 If the value is part of the `...' and is not passed in one of the first 6
4816 slots then the value is passed in memory.
4817 If a prototype is not in scope:
4818 If the value is one of the first 6 arguments the value is passed in the
4819 appropriate integer reg and the appropriate fp reg.
4820 If the value is not one of the first 6 arguments the value is passed in
4821 the appropriate fp reg and in memory.
4824 Summary of the calling conventions implemented by GCC on SPARC:
4827 size argument return value
4829 small integer <4 int. reg. int. reg.
4830 word 4 int. reg. int. reg.
4831 double word 8 int. reg. int. reg.
4833 _Complex small integer <8 int. reg. int. reg.
4834 _Complex word 8 int. reg. int. reg.
4835 _Complex double word 16 memory int. reg.
4837 vector integer <=8 int. reg. FP reg.
4838 vector integer >8 memory memory
4840 float 4 int. reg. FP reg.
4841 double 8 int. reg. FP reg.
4842 long double 16 memory memory
4844 _Complex float 8 memory FP reg.
4845 _Complex double 16 memory FP reg.
4846 _Complex long double 32 memory FP reg.
4848 vector float <=32 memory FP reg.
4849 vector float >32 memory memory
4851 aggregate any memory memory
4856 size argument return value
4858 small integer <8 int. reg. int. reg.
4859 word 8 int. reg. int. reg.
4860 double word 16 int. reg. int. reg.
4862 _Complex small integer <16 int. reg. int. reg.
4863 _Complex word 16 int. reg. int. reg.
4864 _Complex double word 32 memory int. reg.
4866 vector integer <=16 FP reg. FP reg.
4867 vector integer 16<s<=32 memory FP reg.
4868 vector integer >32 memory memory
4870 float 4 FP reg. FP reg.
4871 double 8 FP reg. FP reg.
4872 long double 16 FP reg. FP reg.
4874 _Complex float 8 FP reg. FP reg.
4875 _Complex double 16 FP reg. FP reg.
4876 _Complex long double 32 memory FP reg.
4878 vector float <=16 FP reg. FP reg.
4879 vector float 16<s<=32 memory FP reg.
4880 vector float >32 memory memory
4882 aggregate <=16 reg. reg.
4883 aggregate 16<s<=32 memory reg.
4884 aggregate >32 memory memory
4888 Note #1: complex floating-point types follow the extended SPARC ABIs as
4889 implemented by the Sun compiler.
4891 Note #2: integral vector types follow the scalar floating-point types
4892 conventions to match what is implemented by the Sun VIS SDK.
4894 Note #3: floating-point vector types follow the complex floating-point
4895 types conventions. */
4898 /* Maximum number of int regs for args. */
4899 #define SPARC_INT_ARG_MAX 6
4900 /* Maximum number of fp regs for args. */
4901 #define SPARC_FP_ARG_MAX 16
4903 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4905 /* Handle the INIT_CUMULATIVE_ARGS macro.
4906 Initialize a variable CUM of type CUMULATIVE_ARGS
4907 for a call to a function whose data type is FNTYPE.
4908 For a library call, FNTYPE is 0. */
4911 init_cumulative_args (struct sparc_args *cum, tree fntype,
4912 rtx libname ATTRIBUTE_UNUSED,
4913 tree fndecl ATTRIBUTE_UNUSED)
4916 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4917 cum->libcall_p = fntype == 0;
4920 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4921 When a prototype says `char' or `short', really pass an `int'. */
4924 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
4926 return TARGET_ARCH32 ? true : false;
4929 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4932 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4934 return TARGET_ARCH64 ? true : false;
4937 /* Scan the record type TYPE and return the following predicates:
4938 - INTREGS_P: the record contains at least one field or sub-field
4939 that is eligible for promotion in integer registers.
4940 - FP_REGS_P: the record contains at least one field or sub-field
4941 that is eligible for promotion in floating-point registers.
4942 - PACKED_P: the record contains at least one field that is packed.
4944 Sub-fields are not taken into account for the PACKED_P predicate. */
4947 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4951 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4953 if (TREE_CODE (field) == FIELD_DECL)
4955 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4956 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4957 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4962 if (packed_p && DECL_PACKED (field))
4968 /* Compute the slot number to pass an argument in.
4969 Return the slot number or -1 if passing on the stack.
4971 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4972 the preceding args and about the function being called.
4973 MODE is the argument's machine mode.
4974 TYPE is the data type of the argument (as a tree).
4975 This is null for libcalls where that information may
4977 NAMED is nonzero if this argument is a named parameter
4978 (otherwise it is an extra parameter matching an ellipsis).
4979 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4980 *PREGNO records the register number to use if scalar type.
4981 *PPADDING records the amount of padding needed in words. */
4984 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4985 tree type, int named, int incoming_p,
4986 int *pregno, int *ppadding)
4988 int regbase = (incoming_p
4989 ? SPARC_INCOMING_INT_ARG_FIRST
4990 : SPARC_OUTGOING_INT_ARG_FIRST);
4991 int slotno = cum->words;
4996 if (type && TREE_ADDRESSABLE (type))
5002 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5005 /* For SPARC64, objects requiring 16-byte alignment get it. */
5007 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5008 && (slotno & 1) != 0)
5009 slotno++, *ppadding = 1;
5011 switch (GET_MODE_CLASS (mode))
5014 case MODE_COMPLEX_FLOAT:
5015 case MODE_VECTOR_INT:
5016 case MODE_VECTOR_FLOAT:
5017 if (TARGET_ARCH64 && TARGET_FPU && named)
5019 if (slotno >= SPARC_FP_ARG_MAX)
5021 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5022 /* Arguments filling only one single FP register are
5023 right-justified in the outer double FP register. */
5024 if (GET_MODE_SIZE (mode) <= 4)
5031 case MODE_COMPLEX_INT:
5032 if (slotno >= SPARC_INT_ARG_MAX)
5034 regno = regbase + slotno;
5038 if (mode == VOIDmode)
5039 /* MODE is VOIDmode when generating the actual call. */
5042 if (mode != BLKmode)
5045 /* For SPARC64, objects requiring 16-byte alignment get it. */
5048 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5049 && (slotno & 1) != 0)
5050 slotno++, *ppadding = 1;
5052 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5054 if (slotno >= SPARC_INT_ARG_MAX)
5056 regno = regbase + slotno;
5058 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5060 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5062 /* First see what kinds of registers we would need. */
5063 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5065 /* The ABI obviously doesn't specify how packed structures
5066 are passed. These are defined to be passed in int regs
5067 if possible, otherwise memory. */
5068 if (packed_p || !named)
5069 fpregs_p = 0, intregs_p = 1;
5071 /* If all arg slots are filled, then must pass on stack. */
5072 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5075 /* If there are only int args and all int arg slots are filled,
5076 then must pass on stack. */
5077 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5080 /* Note that even if all int arg slots are filled, fp members may
5081 still be passed in regs if such regs are available.
5082 *PREGNO isn't set because there may be more than one, it's up
5083 to the caller to compute them. */
5096 /* Handle recursive register counting for structure field layout. */
5098 struct function_arg_record_value_parms
5100 rtx ret; /* return expression being built. */
5101 int slotno; /* slot number of the argument. */
5102 int named; /* whether the argument is named. */
5103 int regbase; /* regno of the base register. */
5104 int stack; /* 1 if part of the argument is on the stack. */
5105 int intoffset; /* offset of the first pending integer field. */
5106 unsigned int nregs; /* number of words passed in registers. */
5109 static void function_arg_record_value_3
5110 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5111 static void function_arg_record_value_2
5112 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5113 static void function_arg_record_value_1
5114 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5115 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5116 static rtx function_arg_union_value (int, int);
5118 /* A subroutine of function_arg_record_value. Traverse the structure
5119 recursively and determine how many registers will be required. */
5122 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5123 struct function_arg_record_value_parms *parms,
5128 /* We need to compute how many registers are needed so we can
5129 allocate the PARALLEL but before we can do that we need to know
5130 whether there are any packed fields. The ABI obviously doesn't
5131 specify how structures are passed in this case, so they are
5132 defined to be passed in int regs if possible, otherwise memory,
5133 regardless of whether there are fp values present. */
5136 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5138 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5145 /* Compute how many registers we need. */
5146 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5148 if (TREE_CODE (field) == FIELD_DECL)
5150 HOST_WIDE_INT bitpos = startbitpos;
5152 if (DECL_SIZE (field) != 0
5153 && host_integerp (bit_position (field), 1))
5154 bitpos += int_bit_position (field);
5156 /* ??? FIXME: else assume zero offset. */
5158 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5159 function_arg_record_value_1 (TREE_TYPE (field),
5163 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5164 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5169 if (parms->intoffset != -1)
5171 unsigned int startbit, endbit;
5172 int intslots, this_slotno;
5174 startbit = parms->intoffset & -BITS_PER_WORD;
5175 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5177 intslots = (endbit - startbit) / BITS_PER_WORD;
5178 this_slotno = parms->slotno + parms->intoffset
5181 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5183 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5184 /* We need to pass this field on the stack. */
5188 parms->nregs += intslots;
5189 parms->intoffset = -1;
5192 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5193 If it wasn't true we wouldn't be here. */
5195 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5200 if (parms->intoffset == -1)
5201 parms->intoffset = bitpos;
5207 /* A subroutine of function_arg_record_value. Assign the bits of the
5208 structure between parms->intoffset and bitpos to integer registers. */
5211 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5212 struct function_arg_record_value_parms *parms)
5214 enum machine_mode mode;
5216 unsigned int startbit, endbit;
5217 int this_slotno, intslots, intoffset;
5220 if (parms->intoffset == -1)
5223 intoffset = parms->intoffset;
5224 parms->intoffset = -1;
5226 startbit = intoffset & -BITS_PER_WORD;
5227 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5228 intslots = (endbit - startbit) / BITS_PER_WORD;
5229 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5231 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5235 /* If this is the trailing part of a word, only load that much into
5236 the register. Otherwise load the whole register. Note that in
5237 the latter case we may pick up unwanted bits. It's not a problem
5238 at the moment but may wish to revisit. */
5240 if (intoffset % BITS_PER_WORD != 0)
5241 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5246 intoffset /= BITS_PER_UNIT;
5249 regno = parms->regbase + this_slotno;
5250 reg = gen_rtx_REG (mode, regno);
5251 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5252 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5255 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5260 while (intslots > 0);
5263 /* A subroutine of function_arg_record_value. Traverse the structure
5264 recursively and assign bits to floating point registers. Track which
5265 bits in between need integer registers; invoke function_arg_record_value_3
5266 to make that happen. */
5269 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5270 struct function_arg_record_value_parms *parms,
5276 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5278 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5285 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5287 if (TREE_CODE (field) == FIELD_DECL)
5289 HOST_WIDE_INT bitpos = startbitpos;
5291 if (DECL_SIZE (field) != 0
5292 && host_integerp (bit_position (field), 1))
5293 bitpos += int_bit_position (field);
5295 /* ??? FIXME: else assume zero offset. */
5297 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5298 function_arg_record_value_2 (TREE_TYPE (field),
5302 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5303 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5308 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5310 enum machine_mode mode = DECL_MODE (field);
5313 function_arg_record_value_3 (bitpos, parms);
5316 case SCmode: mode = SFmode; break;
5317 case DCmode: mode = DFmode; break;
5318 case TCmode: mode = TFmode; break;
5321 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5322 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5324 reg = gen_rtx_REG (mode, regno);
5325 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5326 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5327 GEN_INT (bitpos / BITS_PER_UNIT));
5329 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5331 regno += GET_MODE_SIZE (mode) / 4;
5332 reg = gen_rtx_REG (mode, regno);
5333 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5334 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5335 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5342 if (parms->intoffset == -1)
5343 parms->intoffset = bitpos;
5349 /* Used by function_arg and function_value to implement the complex
5350 conventions of the 64-bit ABI for passing and returning structures.
5351 Return an expression valid as a return value for the two macros
5352 FUNCTION_ARG and FUNCTION_VALUE.
5354 TYPE is the data type of the argument (as a tree).
5355 This is null for libcalls where that information may
5357 MODE is the argument's machine mode.
5358 SLOTNO is the index number of the argument's slot in the parameter array.
5359 NAMED is nonzero if this argument is a named parameter
5360 (otherwise it is an extra parameter matching an ellipsis).
5361 REGBASE is the regno of the base register for the parameter array. */
5364 function_arg_record_value (tree type, enum machine_mode mode,
5365 int slotno, int named, int regbase)
5367 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5368 struct function_arg_record_value_parms parms;
5371 parms.ret = NULL_RTX;
5372 parms.slotno = slotno;
5373 parms.named = named;
5374 parms.regbase = regbase;
5377 /* Compute how many registers we need. */
5379 parms.intoffset = 0;
5380 function_arg_record_value_1 (type, 0, &parms, false);
5382 /* Take into account pending integer fields. */
5383 if (parms.intoffset != -1)
5385 unsigned int startbit, endbit;
5386 int intslots, this_slotno;
5388 startbit = parms.intoffset & -BITS_PER_WORD;
5389 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5390 intslots = (endbit - startbit) / BITS_PER_WORD;
5391 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5393 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5395 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5396 /* We need to pass this field on the stack. */
5400 parms.nregs += intslots;
5402 nregs = parms.nregs;
5404 /* Allocate the vector and handle some annoying special cases. */
5407 /* ??? Empty structure has no value? Duh? */
5410 /* Though there's nothing really to store, return a word register
5411 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5412 leads to breakage due to the fact that there are zero bytes to
5414 return gen_rtx_REG (mode, regbase);
5418 /* ??? C++ has structures with no fields, and yet a size. Give up
5419 for now and pass everything back in integer registers. */
5420 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5422 if (nregs + slotno > SPARC_INT_ARG_MAX)
5423 nregs = SPARC_INT_ARG_MAX - slotno;
5428 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5430 /* If at least one field must be passed on the stack, generate
5431 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5432 also be passed on the stack. We can't do much better because the
5433 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5434 of structures for which the fields passed exclusively in registers
5435 are not at the beginning of the structure. */
5437 XVECEXP (parms.ret, 0, 0)
5438 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5440 /* Fill in the entries. */
5442 parms.intoffset = 0;
5443 function_arg_record_value_2 (type, 0, &parms, false);
5444 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5446 if (parms.nregs != nregs)
5452 /* Used by function_arg and function_value to implement the conventions
5453 of the 64-bit ABI for passing and returning unions.
5454 Return an expression valid as a return value for the two macros
5455 FUNCTION_ARG and FUNCTION_VALUE.
5457 SIZE is the size in bytes of the union.
5458 REGNO is the hard register the union will be passed in. */
5461 function_arg_union_value (int size, int regno)
5463 enum machine_mode mode;
5466 if (size <= UNITS_PER_WORD)
5469 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5471 reg = gen_rtx_REG (mode, regno);
5473 /* Unions are passed left-justified. */
5474 return gen_rtx_PARALLEL (mode,
5475 gen_rtvec (1, gen_rtx_EXPR_LIST (VOIDmode,
5480 /* Handle the FUNCTION_ARG macro.
5481 Determine where to put an argument to a function.
5482 Value is zero to push the argument on the stack,
5483 or a hard register in which to store the argument.
5485 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5486 the preceding args and about the function being called.
5487 MODE is the argument's machine mode.
5488 TYPE is the data type of the argument (as a tree).
5489 This is null for libcalls where that information may
5491 NAMED is nonzero if this argument is a named parameter
5492 (otherwise it is an extra parameter matching an ellipsis).
5493 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5496 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5497 tree type, int named, int incoming_p)
5499 int regbase = (incoming_p
5500 ? SPARC_INCOMING_INT_ARG_FIRST
5501 : SPARC_OUTGOING_INT_ARG_FIRST);
5502 int slotno, regno, padding;
5505 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5513 reg = gen_rtx_REG (mode, regno);
5517 if (type && TREE_CODE (type) == RECORD_TYPE)
5519 /* Structures up to 16 bytes in size are passed in arg slots on the
5520 stack and are promoted to registers where possible. */
5522 if (int_size_in_bytes (type) > 16)
5523 abort (); /* shouldn't get here */
5525 return function_arg_record_value (type, mode, slotno, named, regbase);
5527 else if (type && TREE_CODE (type) == UNION_TYPE)
5529 HOST_WIDE_INT size = int_size_in_bytes (type);
5532 abort (); /* shouldn't get here */
5534 return function_arg_union_value (size, regno);
5536 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5537 but also have the slot allocated for them.
5538 If no prototype is in scope fp values in register slots get passed
5539 in two places, either fp regs and int regs or fp regs and memory. */
5540 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5541 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5542 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5543 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5544 && SPARC_FP_REG_P (regno))
5546 reg = gen_rtx_REG (mode, regno);
5547 if (cum->prototype_p || cum->libcall_p)
5549 /* "* 2" because fp reg numbers are recorded in 4 byte
5552 /* ??? This will cause the value to be passed in the fp reg and
5553 in the stack. When a prototype exists we want to pass the
5554 value in the reg but reserve space on the stack. That's an
5555 optimization, and is deferred [for a bit]. */
5556 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5557 return gen_rtx_PARALLEL (mode,
5559 gen_rtx_EXPR_LIST (VOIDmode,
5560 NULL_RTX, const0_rtx),
5561 gen_rtx_EXPR_LIST (VOIDmode,
5565 /* ??? It seems that passing back a register even when past
5566 the area declared by REG_PARM_STACK_SPACE will allocate
5567 space appropriately, and will not copy the data onto the
5568 stack, exactly as we desire.
5570 This is due to locate_and_pad_parm being called in
5571 expand_call whenever reg_parm_stack_space > 0, which
5572 while beneficial to our example here, would seem to be
5573 in error from what had been intended. Ho hum... -- r~ */
5581 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5585 /* On incoming, we don't need to know that the value
5586 is passed in %f0 and %i0, and it confuses other parts
5587 causing needless spillage even on the simplest cases. */
5591 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5592 + (regno - SPARC_FP_ARG_FIRST) / 2);
5594 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5595 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5597 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5601 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5602 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5603 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5609 /* Scalar or complex int. */
5610 reg = gen_rtx_REG (mode, regno);
5616 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5617 For an arg passed partly in registers and partly in memory,
5618 this is the number of registers used.
5619 For args passed entirely in registers or entirely in memory, zero.
5621 Any arg that starts in the first 6 regs but won't entirely fit in them
5622 needs partial registers on v8. On v9, structures with integer
5623 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5624 values that begin in the last fp reg [where "last fp reg" varies with the
5625 mode] will be split between that reg and memory. */
5628 function_arg_partial_nregs (const struct sparc_args *cum,
5629 enum machine_mode mode, tree type, int named)
5631 int slotno, regno, padding;
5633 /* We pass 0 for incoming_p here, it doesn't matter. */
5634 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5641 if ((slotno + (mode == BLKmode
5642 ? ROUND_ADVANCE (int_size_in_bytes (type))
5643 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5644 > SPARC_INT_ARG_MAX)
5645 return SPARC_INT_ARG_MAX - slotno;
5649 /* We are guaranteed by function_arg_pass_by_reference that the size
5650 of the argument is not greater than 16 bytes, so we only need to
5651 return 1 if the argument is partially passed in registers. */
5653 if (type && AGGREGATE_TYPE_P (type))
5655 int size = int_size_in_bytes (type);
5657 if (size > UNITS_PER_WORD
5658 && slotno == SPARC_INT_ARG_MAX - 1)
5661 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5662 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5663 && ! (TARGET_FPU && named)))
5665 /* The complex types are passed as packed types. */
5666 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5667 && slotno == SPARC_INT_ARG_MAX - 1)
5670 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5672 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5681 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5682 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5683 quad-precision floats by invisible reference.
5684 v9: Aggregates greater than 16 bytes are passed by reference.
5685 For Pascal, also pass arrays by reference. */
5688 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5689 enum machine_mode mode, tree type,
5690 int named ATTRIBUTE_UNUSED)
5694 return ((type && AGGREGATE_TYPE_P (type))
5695 /* Extended ABI (as implemented by the Sun compiler) says
5696 that all complex floats are passed in memory. */
5698 /* Enforce the 2-word cap for passing arguments in registers.
5699 This affects CDImode, TFmode, DCmode, TCmode and large
5701 || GET_MODE_SIZE (mode) > 8);
5705 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5707 && AGGREGATE_TYPE_P (type)
5708 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5709 /* Enforce the 2-word cap for passing arguments in registers.
5710 This affects CTImode, TCmode and large vector modes. */
5711 || GET_MODE_SIZE (mode) > 16);
5715 /* Handle the FUNCTION_ARG_ADVANCE macro.
5716 Update the data in CUM to advance over an argument
5717 of mode MODE and data type TYPE.
5718 TYPE is null for libcalls where that information may not be available. */
5721 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5722 tree type, int named)
5724 int slotno, regno, padding;
5726 /* We pass 0 for incoming_p here, it doesn't matter. */
5727 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5729 /* If register required leading padding, add it. */
5731 cum->words += padding;
5735 cum->words += (mode != BLKmode
5736 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5737 : ROUND_ADVANCE (int_size_in_bytes (type)));
5741 if (type && AGGREGATE_TYPE_P (type))
5743 int size = int_size_in_bytes (type);
5747 else if (size <= 16)
5749 else /* passed by reference */
5754 cum->words += (mode != BLKmode
5755 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5756 : ROUND_ADVANCE (int_size_in_bytes (type)));
5761 /* Handle the FUNCTION_ARG_PADDING macro.
5762 For the 64 bit ABI structs are always stored left shifted in their
5766 function_arg_padding (enum machine_mode mode, tree type)
5768 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5771 /* Fall back to the default. */
5772 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5775 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5776 Specify whether to return the return value in memory. */
5779 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5782 /* Original SPARC 32-bit ABI says that quad-precision floats
5783 and all structures are returned in memory. Extended ABI
5784 (as implemented by the Sun compiler) says that all complex
5785 floats are returned in registers (8 FP registers at most
5786 for '_Complex long double'). Return all complex integers
5787 in registers (4 at most for '_Complex long long'). */
5788 return (TYPE_MODE (type) == BLKmode
5789 || TYPE_MODE (type) == TFmode
5790 /* Integral vector types follow the scalar FP types conventions. */
5791 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5792 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5793 /* FP vector types follow the complex FP types conventions. */
5794 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5795 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5797 /* Original SPARC 64-bit ABI says that structures and unions
5798 smaller than 32 bytes are returned in registers. Extended
5799 ABI (as implemented by the Sun compiler) says that all complex
5800 floats are returned in registers (8 FP registers at most
5801 for '_Complex long double'). Return all complex integers
5802 in registers (4 at most for '_Complex TItype'). */
5803 return ((TYPE_MODE (type) == BLKmode
5804 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5805 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5808 /* Handle the TARGET_STRUCT_VALUE target hook.
5809 Return where to find the structure return value address. */
5812 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5819 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5820 STRUCT_VALUE_OFFSET));
5822 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5823 STRUCT_VALUE_OFFSET));
5827 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5828 For v9, function return values are subject to the same rules as arguments,
5829 except that up to 32 bytes may be returned in registers. */
5832 function_value (tree type, enum machine_mode mode, int incoming_p)
5834 /* Beware that the two values are swapped here wrt function_arg. */
5835 int regbase = (incoming_p
5836 ? SPARC_OUTGOING_INT_ARG_FIRST
5837 : SPARC_INCOMING_INT_ARG_FIRST);
5840 if (TARGET_ARCH64 && type)
5842 if (TREE_CODE (type) == RECORD_TYPE)
5844 /* Structures up to 32 bytes in size are passed in registers,
5845 promoted to fp registers where possible. */
5847 if (int_size_in_bytes (type) > 32)
5848 abort (); /* shouldn't get here */
5850 return function_arg_record_value (type, mode, 0, 1, regbase);
5852 else if (TREE_CODE (type) == UNION_TYPE)
5854 HOST_WIDE_INT size = int_size_in_bytes (type);
5857 abort (); /* shouldn't get here */
5859 return function_arg_union_value (size, regbase);
5861 else if (AGGREGATE_TYPE_P (type))
5863 /* All other aggregate types are passed in an integer register
5864 in a mode corresponding to the size of the type. */
5865 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5868 abort (); /* shouldn't get here */
5870 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5872 else if (GET_MODE_CLASS (mode) == MODE_INT
5873 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5877 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5878 regno = SPARC_FP_ARG_FIRST;
5882 return gen_rtx_REG (mode, regno);
5885 /* Do what is necessary for `va_start'. We look at the current function
5886 to determine if stdarg or varargs is used and return the address of
5887 the first unnamed parameter. */
5890 sparc_builtin_saveregs (void)
5892 int first_reg = current_function_args_info.words;
5896 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5897 emit_move_insn (gen_rtx_MEM (word_mode,
5898 gen_rtx_PLUS (Pmode,
5900 GEN_INT (FIRST_PARM_OFFSET (0)
5903 gen_rtx_REG (word_mode,
5904 SPARC_INCOMING_INT_ARG_FIRST + regno));
5906 address = gen_rtx_PLUS (Pmode,
5908 GEN_INT (FIRST_PARM_OFFSET (0)
5909 + UNITS_PER_WORD * first_reg));
5914 /* Implement `va_start' for stdarg. */
5917 sparc_va_start (tree valist, rtx nextarg)
5919 nextarg = expand_builtin_saveregs ();
5920 std_expand_builtin_va_start (valist, nextarg);
5923 /* Implement `va_arg' for stdarg. */
5926 sparc_va_arg (tree valist, tree type)
5928 HOST_WIDE_INT size, rsize, align;
5933 if (function_arg_pass_by_reference (0, TYPE_MODE (type), type, 0))
5936 size = rsize = UNITS_PER_WORD;
5942 size = int_size_in_bytes (type);
5943 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5948 /* For SPARC64, objects requiring 16-byte alignment get it. */
5949 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5950 align = 2 * UNITS_PER_WORD;
5952 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5953 are given whole slots as needed. */
5954 if (AGGREGATE_TYPE_P (type))
5957 size = rsize = UNITS_PER_WORD;
5967 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5968 build_int_2 (align - 1, 0)));
5969 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5970 build_int_2 (-align, -1)));
5973 addr = incr = save_expr (incr);
5974 if (BYTES_BIG_ENDIAN && size < rsize)
5976 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5977 build_int_2 (rsize - size, 0)));
5979 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5980 build_int_2 (rsize, 0)));
5982 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5983 TREE_SIDE_EFFECTS (incr) = 1;
5984 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5986 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5988 /* If the address isn't aligned properly for the type,
5989 we may need to copy to a temporary.
5990 FIXME: This is inefficient. Usually we can do this
5993 && TYPE_ALIGN (type) > BITS_PER_WORD
5996 /* FIXME: We really need to specify that the temporary is live
5997 for the whole function because expand_builtin_va_arg wants
5998 the alias set to be get_varargs_alias_set (), but in this
5999 case the alias set is that for TYPE and if the memory gets
6000 reused it will be reused with alias set TYPE. */
6001 rtx tmp = assign_temp (type, 0, 1, 0);
6004 addr_rtx = force_reg (Pmode, addr_rtx);
6005 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
6006 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
6007 set_mem_align (addr_rtx, BITS_PER_WORD);
6008 tmp = shallow_copy_rtx (tmp);
6009 PUT_MODE (tmp, BLKmode);
6010 set_mem_alias_set (tmp, 0);
6012 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
6014 if (dest_addr != NULL_RTX)
6015 addr_rtx = dest_addr;
6017 addr_rtx = XCEXP (tmp, 0, MEM);
6022 addr_rtx = force_reg (Pmode, addr_rtx);
6023 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
6024 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
6030 /* Return the string to output a conditional branch to LABEL, which is
6031 the operand number of the label. OP is the conditional expression.
6032 XEXP (OP, 0) is assumed to be a condition code register (integer or
6033 floating point) and its mode specifies what kind of comparison we made.
6035 REVERSED is nonzero if we should reverse the sense of the comparison.
6037 ANNUL is nonzero if we should generate an annulling branch.
6039 NOOP is nonzero if we have to follow this branch by a noop.
6041 INSN, if set, is the insn. */
6044 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6047 static char string[50];
6048 enum rtx_code code = GET_CODE (op);
6049 rtx cc_reg = XEXP (op, 0);
6050 enum machine_mode mode = GET_MODE (cc_reg);
6051 const char *labelno, *branch;
6052 int spaces = 8, far;
6055 /* v9 branches are limited to +-1MB. If it is too far away,
6068 fbne,a,pn %fcc2, .LC29
6076 far = get_attr_length (insn) >= 3;
6079 /* Reversal of FP compares takes care -- an ordered compare
6080 becomes an unordered compare and vice versa. */
6081 if (mode == CCFPmode || mode == CCFPEmode)
6082 code = reverse_condition_maybe_unordered (code);
6084 code = reverse_condition (code);
6087 /* Start by writing the branch condition. */
6088 if (mode == CCFPmode || mode == CCFPEmode)
6139 /* ??? !v9: FP branches cannot be preceded by another floating point
6140 insn. Because there is currently no concept of pre-delay slots,
6141 we can fix this only by always emitting a nop before a floating
6146 strcpy (string, "nop\n\t");
6147 strcat (string, branch);
6160 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6172 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6193 strcpy (string, branch);
6195 spaces -= strlen (branch);
6196 p = strchr (string, '\0');
6198 /* Now add the annulling, the label, and a possible noop. */
6213 if (! far && insn && INSN_ADDRESSES_SET_P ())
6215 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6216 - INSN_ADDRESSES (INSN_UID (insn)));
6217 /* Leave some instructions for "slop". */
6218 if (delta < -260000 || delta >= 260000)
6222 if (mode == CCFPmode || mode == CCFPEmode)
6224 static char v9_fcc_labelno[] = "%%fccX, ";
6225 /* Set the char indicating the number of the fcc reg to use. */
6226 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6227 labelno = v9_fcc_labelno;
6230 if (REGNO (cc_reg) == SPARC_FCC_REG)
6236 else if (mode == CCXmode || mode == CCX_NOOVmode)
6238 labelno = "%%xcc, ";
6244 labelno = "%%icc, ";
6249 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6252 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6262 strcpy (p, labelno);
6263 p = strchr (p, '\0');
6266 strcpy (p, ".+12\n\tnop\n\tb\t");
6273 /* Set the char indicating the number of the operand containing the
6278 strcpy (p, "\n\tnop");
6283 /* Emit a library call comparison between floating point X and Y.
6284 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6285 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6286 values as arguments instead of the TFmode registers themselves,
6287 that's why we cannot call emit_float_lib_cmp. */
6289 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6292 rtx slot0, slot1, result, tem, tem2;
6293 enum machine_mode mode;
6298 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6302 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6306 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6310 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6314 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6318 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6329 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6339 if (GET_CODE (x) != MEM)
6341 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6342 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6347 if (GET_CODE (y) != MEM)
6349 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6350 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6355 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6357 XEXP (slot0, 0), Pmode,
6358 XEXP (slot1, 0), Pmode);
6364 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6366 x, TFmode, y, TFmode);
6372 /* Immediately move the result of the libcall into a pseudo
6373 register so reload doesn't clobber the value if it needs
6374 the return register for a spill reg. */
6375 result = gen_reg_rtx (mode);
6376 emit_move_insn (result, hard_libcall_value (mode));
6381 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6385 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6390 emit_cmp_insn (result, const1_rtx,
6391 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6394 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6397 tem = gen_reg_rtx (mode);
6399 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6401 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6402 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6406 tem = gen_reg_rtx (mode);
6408 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6410 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6411 tem2 = gen_reg_rtx (mode);
6413 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6415 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6416 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6422 /* Generate an unsigned DImode to FP conversion. This is the same code
6423 optabs would emit if we didn't have TFmode patterns. */
6426 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6428 rtx neglab, donelab, i0, i1, f0, in, out;
6431 in = force_reg (DImode, operands[1]);
6432 neglab = gen_label_rtx ();
6433 donelab = gen_label_rtx ();
6434 i0 = gen_reg_rtx (DImode);
6435 i1 = gen_reg_rtx (DImode);
6436 f0 = gen_reg_rtx (mode);
6438 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6440 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6441 emit_jump_insn (gen_jump (donelab));
6444 emit_label (neglab);
6446 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6447 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6448 emit_insn (gen_iordi3 (i0, i0, i1));
6449 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6450 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6452 emit_label (donelab);
6455 /* Generate an FP to unsigned DImode conversion. This is the same code
6456 optabs would emit if we didn't have TFmode patterns. */
6459 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6461 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6464 in = force_reg (mode, operands[1]);
6465 neglab = gen_label_rtx ();
6466 donelab = gen_label_rtx ();
6467 i0 = gen_reg_rtx (DImode);
6468 i1 = gen_reg_rtx (DImode);
6469 limit = gen_reg_rtx (mode);
6470 f0 = gen_reg_rtx (mode);
6472 emit_move_insn (limit,
6473 CONST_DOUBLE_FROM_REAL_VALUE (
6474 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6475 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6477 emit_insn (gen_rtx_SET (VOIDmode,
6479 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6480 emit_jump_insn (gen_jump (donelab));
6483 emit_label (neglab);
6485 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6486 emit_insn (gen_rtx_SET (VOIDmode,
6488 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6489 emit_insn (gen_movdi (i1, const1_rtx));
6490 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6491 emit_insn (gen_xordi3 (out, i0, i1));
6493 emit_label (donelab);
6496 /* Return the string to output a conditional branch to LABEL, testing
6497 register REG. LABEL is the operand number of the label; REG is the
6498 operand number of the reg. OP is the conditional expression. The mode
6499 of REG says what kind of comparison we made.
6501 REVERSED is nonzero if we should reverse the sense of the comparison.
6503 ANNUL is nonzero if we should generate an annulling branch.
6505 NOOP is nonzero if we have to follow this branch by a noop. */
6508 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6509 int annul, int noop, rtx insn)
6511 static char string[50];
6512 enum rtx_code code = GET_CODE (op);
6513 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6518 /* branch on register are limited to +-128KB. If it is too far away,
6531 brgez,a,pn %o1, .LC29
6537 ba,pt %xcc, .LC29 */
6539 far = get_attr_length (insn) >= 3;
6541 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6543 code = reverse_condition (code);
6545 /* Only 64 bit versions of these instructions exist. */
6549 /* Start by writing the branch condition. */
6554 strcpy (string, "brnz");
6558 strcpy (string, "brz");
6562 strcpy (string, "brgez");
6566 strcpy (string, "brlz");
6570 strcpy (string, "brlez");
6574 strcpy (string, "brgz");
6581 p = strchr (string, '\0');
6583 /* Now add the annulling, reg, label, and nop. */
6590 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6593 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6598 *p = p < string + 8 ? '\t' : ' ';
6606 int veryfar = 1, delta;
6608 if (INSN_ADDRESSES_SET_P ())
6610 delta = (INSN_ADDRESSES (INSN_UID (dest))
6611 - INSN_ADDRESSES (INSN_UID (insn)));
6612 /* Leave some instructions for "slop". */
6613 if (delta >= -260000 && delta < 260000)
6617 strcpy (p, ".+12\n\tnop\n\t");
6628 strcpy (p, "ba,pt\t%%xcc, ");
6638 strcpy (p, "\n\tnop");
6643 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6644 Such instructions cannot be used in the delay slot of return insn on v9.
6645 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6649 epilogue_renumber (register rtx *where, int test)
6651 register const char *fmt;
6653 register enum rtx_code code;
6658 code = GET_CODE (*where);
6663 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6665 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6666 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6674 /* Do not replace the frame pointer with the stack pointer because
6675 it can cause the delayed instruction to load below the stack.
6676 This occurs when instructions like:
6678 (set (reg/i:SI 24 %i0)
6679 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6680 (const_int -20 [0xffffffec])) 0))
6682 are in the return delayed slot. */
6684 if (GET_CODE (XEXP (*where, 0)) == REG
6685 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6686 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6687 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6692 if (SPARC_STACK_BIAS
6693 && GET_CODE (XEXP (*where, 0)) == REG
6694 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6702 fmt = GET_RTX_FORMAT (code);
6704 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6709 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6710 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6713 else if (fmt[i] == 'e'
6714 && epilogue_renumber (&(XEXP (*where, i)), test))
6720 /* Leaf functions and non-leaf functions have different needs. */
6723 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6726 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6728 static const int *const reg_alloc_orders[] = {
6729 reg_leaf_alloc_order,
6730 reg_nonleaf_alloc_order};
6733 order_regs_for_local_alloc (void)
6735 static int last_order_nonleaf = 1;
6737 if (regs_ever_live[15] != last_order_nonleaf)
6739 last_order_nonleaf = !last_order_nonleaf;
6740 memcpy ((char *) reg_alloc_order,
6741 (const char *) reg_alloc_orders[last_order_nonleaf],
6742 FIRST_PSEUDO_REGISTER * sizeof (int));
6746 /* Return 1 if REG and MEM are legitimate enough to allow the various
6747 mem<-->reg splits to be run. */
6750 sparc_splitdi_legitimate (rtx reg, rtx mem)
6752 /* Punt if we are here by mistake. */
6753 if (! reload_completed)
6756 /* We must have an offsettable memory reference. */
6757 if (! offsettable_memref_p (mem))
6760 /* If we have legitimate args for ldd/std, we do not want
6761 the split to happen. */
6762 if ((REGNO (reg) % 2) == 0
6763 && mem_min_alignment (mem, 8))
6770 /* Return 1 if x and y are some kind of REG and they refer to
6771 different hard registers. This test is guaranteed to be
6772 run after reload. */
6775 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6777 if (GET_CODE (x) != REG)
6779 if (GET_CODE (y) != REG)
6781 if (REGNO (x) == REGNO (y))
6786 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6787 This makes them candidates for using ldd and std insns.
6789 Note reg1 and reg2 *must* be hard registers. */
6792 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6794 /* We might have been passed a SUBREG. */
6795 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6798 if (REGNO (reg1) % 2 != 0)
6801 /* Integer ldd is deprecated in SPARC V9 */
6802 if (TARGET_V9 && REGNO (reg1) < 32)
6805 return (REGNO (reg1) == REGNO (reg2) - 1);
6808 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6811 This can only happen when addr1 and addr2, the addresses in mem1
6812 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6813 addr1 must also be aligned on a 64-bit boundary.
6815 Also iff dependent_reg_rtx is not null it should not be used to
6816 compute the address for mem1, i.e. we cannot optimize a sequence
6828 But, note that the transformation from:
6833 is perfectly fine. Thus, the peephole2 patterns always pass us
6834 the destination register of the first load, never the second one.
6836 For stores we don't have a similar problem, so dependent_reg_rtx is
6840 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6844 HOST_WIDE_INT offset1;
6846 /* The mems cannot be volatile. */
6847 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6850 /* MEM1 should be aligned on a 64-bit boundary. */
6851 if (MEM_ALIGN (mem1) < 64)
6854 addr1 = XEXP (mem1, 0);
6855 addr2 = XEXP (mem2, 0);
6857 /* Extract a register number and offset (if used) from the first addr. */
6858 if (GET_CODE (addr1) == PLUS)
6860 /* If not a REG, return zero. */
6861 if (GET_CODE (XEXP (addr1, 0)) != REG)
6865 reg1 = REGNO (XEXP (addr1, 0));
6866 /* The offset must be constant! */
6867 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6869 offset1 = INTVAL (XEXP (addr1, 1));
6872 else if (GET_CODE (addr1) != REG)
6876 reg1 = REGNO (addr1);
6877 /* This was a simple (mem (reg)) expression. Offset is 0. */
6881 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6882 if (GET_CODE (addr2) != PLUS)
6885 if (GET_CODE (XEXP (addr2, 0)) != REG
6886 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6889 if (reg1 != REGNO (XEXP (addr2, 0)))
6892 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6895 /* The first offset must be evenly divisible by 8 to ensure the
6896 address is 64 bit aligned. */
6897 if (offset1 % 8 != 0)
6900 /* The offset for the second addr must be 4 more than the first addr. */
6901 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6904 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6909 /* Return 1 if reg is a pseudo, or is the first register in
6910 a hard register pair. This makes it a candidate for use in
6911 ldd and std insns. */
6914 register_ok_for_ldd (rtx reg)
6916 /* We might have been passed a SUBREG. */
6917 if (GET_CODE (reg) != REG)
6920 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6921 return (REGNO (reg) % 2 == 0);
6926 /* Print operand X (an rtx) in assembler syntax to file FILE.
6927 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6928 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6931 print_operand (FILE *file, rtx x, int code)
6936 /* Output a 'nop' if there's nothing for the delay slot. */
6937 if (dbr_sequence_length () == 0)
6938 fputs ("\n\t nop", file);
6941 /* Output an annul flag if there's nothing for the delay slot and we
6942 are optimizing. This is always used with '(' below. */
6943 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6944 this is a dbx bug. So, we only do this when optimizing. */
6945 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6946 Always emit a nop in case the next instruction is a branch. */
6947 if (dbr_sequence_length () == 0
6948 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6952 /* Output a 'nop' if there's nothing for the delay slot and we are
6953 not optimizing. This is always used with '*' above. */
6954 if (dbr_sequence_length () == 0
6955 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6956 fputs ("\n\t nop", file);
6959 /* Output the Embedded Medium/Anywhere code model base register. */
6960 fputs (EMBMEDANY_BASE_REG, file);
6963 /* Print out what we are using as the frame pointer. This might
6964 be %fp, or might be %sp+offset. */
6965 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6966 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6969 /* Print some local dynamic TLS name. */
6970 assemble_name (file, get_some_local_dynamic_name ());
6973 /* Adjust the operand to take into account a RESTORE operation. */
6974 if (GET_CODE (x) == CONST_INT)
6976 else if (GET_CODE (x) != REG)
6977 output_operand_lossage ("invalid %%Y operand");
6978 else if (REGNO (x) < 8)
6979 fputs (reg_names[REGNO (x)], file);
6980 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6981 fputs (reg_names[REGNO (x)-16], file);
6983 output_operand_lossage ("invalid %%Y operand");
6986 /* Print out the low order register name of a register pair. */
6987 if (WORDS_BIG_ENDIAN)
6988 fputs (reg_names[REGNO (x)+1], file);
6990 fputs (reg_names[REGNO (x)], file);
6993 /* Print out the high order register name of a register pair. */
6994 if (WORDS_BIG_ENDIAN)
6995 fputs (reg_names[REGNO (x)], file);
6997 fputs (reg_names[REGNO (x)+1], file);
7000 /* Print out the second register name of a register pair or quad.
7001 I.e., R (%o0) => %o1. */
7002 fputs (reg_names[REGNO (x)+1], file);
7005 /* Print out the third register name of a register quad.
7006 I.e., S (%o0) => %o2. */
7007 fputs (reg_names[REGNO (x)+2], file);
7010 /* Print out the fourth register name of a register quad.
7011 I.e., T (%o0) => %o3. */
7012 fputs (reg_names[REGNO (x)+3], file);
7015 /* Print a condition code register. */
7016 if (REGNO (x) == SPARC_ICC_REG)
7018 /* We don't handle CC[X]_NOOVmode because they're not supposed
7020 if (GET_MODE (x) == CCmode)
7021 fputs ("%icc", file);
7022 else if (GET_MODE (x) == CCXmode)
7023 fputs ("%xcc", file);
7028 /* %fccN register */
7029 fputs (reg_names[REGNO (x)], file);
7032 /* Print the operand's address only. */
7033 output_address (XEXP (x, 0));
7036 /* In this case we need a register. Use %g0 if the
7037 operand is const0_rtx. */
7039 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7041 fputs ("%g0", file);
7048 switch (GET_CODE (x))
7050 case IOR: fputs ("or", file); break;
7051 case AND: fputs ("and", file); break;
7052 case XOR: fputs ("xor", file); break;
7053 default: output_operand_lossage ("invalid %%A operand");
7058 switch (GET_CODE (x))
7060 case IOR: fputs ("orn", file); break;
7061 case AND: fputs ("andn", file); break;
7062 case XOR: fputs ("xnor", file); break;
7063 default: output_operand_lossage ("invalid %%B operand");
7067 /* These are used by the conditional move instructions. */
7071 enum rtx_code rc = GET_CODE (x);
7075 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7076 if (mode == CCFPmode || mode == CCFPEmode)
7077 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7079 rc = reverse_condition (GET_CODE (x));
7083 case NE: fputs ("ne", file); break;
7084 case EQ: fputs ("e", file); break;
7085 case GE: fputs ("ge", file); break;
7086 case GT: fputs ("g", file); break;
7087 case LE: fputs ("le", file); break;
7088 case LT: fputs ("l", file); break;
7089 case GEU: fputs ("geu", file); break;
7090 case GTU: fputs ("gu", file); break;
7091 case LEU: fputs ("leu", file); break;
7092 case LTU: fputs ("lu", file); break;
7093 case LTGT: fputs ("lg", file); break;
7094 case UNORDERED: fputs ("u", file); break;
7095 case ORDERED: fputs ("o", file); break;
7096 case UNLT: fputs ("ul", file); break;
7097 case UNLE: fputs ("ule", file); break;
7098 case UNGT: fputs ("ug", file); break;
7099 case UNGE: fputs ("uge", file); break;
7100 case UNEQ: fputs ("ue", file); break;
7101 default: output_operand_lossage (code == 'c'
7102 ? "invalid %%c operand"
7103 : "invalid %%C operand");
7108 /* These are used by the movr instruction pattern. */
7112 enum rtx_code rc = (code == 'd'
7113 ? reverse_condition (GET_CODE (x))
7117 case NE: fputs ("ne", file); break;
7118 case EQ: fputs ("e", file); break;
7119 case GE: fputs ("gez", file); break;
7120 case LT: fputs ("lz", file); break;
7121 case LE: fputs ("lez", file); break;
7122 case GT: fputs ("gz", file); break;
7123 default: output_operand_lossage (code == 'd'
7124 ? "invalid %%d operand"
7125 : "invalid %%D operand");
7132 /* Print a sign-extended character. */
7133 int i = trunc_int_for_mode (INTVAL (x), QImode);
7134 fprintf (file, "%d", i);
7139 /* Operand must be a MEM; write its address. */
7140 if (GET_CODE (x) != MEM)
7141 output_operand_lossage ("invalid %%f operand");
7142 output_address (XEXP (x, 0));
7147 /* Print a sign-extended 32-bit value. */
7149 if (GET_CODE(x) == CONST_INT)
7151 else if (GET_CODE(x) == CONST_DOUBLE)
7152 i = CONST_DOUBLE_LOW (x);
7155 output_operand_lossage ("invalid %%s operand");
7158 i = trunc_int_for_mode (i, SImode);
7159 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7164 /* Do nothing special. */
7168 /* Undocumented flag. */
7169 output_operand_lossage ("invalid operand output code");
7172 if (GET_CODE (x) == REG)
7173 fputs (reg_names[REGNO (x)], file);
7174 else if (GET_CODE (x) == MEM)
7177 /* Poor Sun assembler doesn't understand absolute addressing. */
7178 if (CONSTANT_P (XEXP (x, 0)))
7179 fputs ("%g0+", file);
7180 output_address (XEXP (x, 0));
7183 else if (GET_CODE (x) == HIGH)
7185 fputs ("%hi(", file);
7186 output_addr_const (file, XEXP (x, 0));
7189 else if (GET_CODE (x) == LO_SUM)
7191 print_operand (file, XEXP (x, 0), 0);
7192 if (TARGET_CM_MEDMID)
7193 fputs ("+%l44(", file);
7195 fputs ("+%lo(", file);
7196 output_addr_const (file, XEXP (x, 1));
7199 else if (GET_CODE (x) == CONST_DOUBLE
7200 && (GET_MODE (x) == VOIDmode
7201 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7203 if (CONST_DOUBLE_HIGH (x) == 0)
7204 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7205 else if (CONST_DOUBLE_HIGH (x) == -1
7206 && CONST_DOUBLE_LOW (x) < 0)
7207 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7209 output_operand_lossage ("long long constant not a valid immediate operand");
7211 else if (GET_CODE (x) == CONST_DOUBLE)
7212 output_operand_lossage ("floating point constant not a valid immediate operand");
7213 else { output_addr_const (file, x); }
7216 /* Target hook for assembling integer objects. The sparc version has
7217 special handling for aligned DI-mode objects. */
7220 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7222 /* ??? We only output .xword's for symbols and only then in environments
7223 where the assembler can handle them. */
7224 if (aligned_p && size == 8
7225 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7229 assemble_integer_with_op ("\t.xword\t", x);
7234 assemble_aligned_integer (4, const0_rtx);
7235 assemble_aligned_integer (4, x);
7239 return default_assemble_integer (x, size, aligned_p);
7242 /* Return the value of a code used in the .proc pseudo-op that says
7243 what kind of result this function returns. For non-C types, we pick
7244 the closest C type. */
7246 #ifndef SHORT_TYPE_SIZE
7247 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7250 #ifndef INT_TYPE_SIZE
7251 #define INT_TYPE_SIZE BITS_PER_WORD
7254 #ifndef LONG_TYPE_SIZE
7255 #define LONG_TYPE_SIZE BITS_PER_WORD
7258 #ifndef LONG_LONG_TYPE_SIZE
7259 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7262 #ifndef FLOAT_TYPE_SIZE
7263 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7266 #ifndef DOUBLE_TYPE_SIZE
7267 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7270 #ifndef LONG_DOUBLE_TYPE_SIZE
7271 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7275 sparc_type_code (register tree type)
7277 register unsigned long qualifiers = 0;
7278 register unsigned shift;
7280 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7281 setting more, since some assemblers will give an error for this. Also,
7282 we must be careful to avoid shifts of 32 bits or more to avoid getting
7283 unpredictable results. */
7285 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7287 switch (TREE_CODE (type))
7293 qualifiers |= (3 << shift);
7298 qualifiers |= (2 << shift);
7302 case REFERENCE_TYPE:
7304 qualifiers |= (1 << shift);
7308 return (qualifiers | 8);
7311 case QUAL_UNION_TYPE:
7312 return (qualifiers | 9);
7315 return (qualifiers | 10);
7318 return (qualifiers | 16);
7321 /* If this is a range type, consider it to be the underlying
7323 if (TREE_TYPE (type) != 0)
7326 /* Carefully distinguish all the standard types of C,
7327 without messing up if the language is not C. We do this by
7328 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7329 look at both the names and the above fields, but that's redundant.
7330 Any type whose size is between two C types will be considered
7331 to be the wider of the two types. Also, we do not have a
7332 special code to use for "long long", so anything wider than
7333 long is treated the same. Note that we can't distinguish
7334 between "int" and "long" in this code if they are the same
7335 size, but that's fine, since neither can the assembler. */
7337 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7338 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7340 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7341 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7343 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7344 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7347 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7350 /* If this is a range type, consider it to be the underlying
7352 if (TREE_TYPE (type) != 0)
7355 /* Carefully distinguish all the standard types of C,
7356 without messing up if the language is not C. */
7358 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7359 return (qualifiers | 6);
7362 return (qualifiers | 7);
7364 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7365 /* ??? We need to distinguish between double and float complex types,
7366 but I don't know how yet because I can't reach this code from
7367 existing front-ends. */
7368 return (qualifiers | 7); /* Who knows? */
7371 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7372 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7373 case FILE_TYPE: /* GNU Pascal FILE type. */
7374 case SET_TYPE: /* GNU Pascal SET type. */
7375 case LANG_TYPE: /* ? */
7379 abort (); /* Not a type! */
7386 /* Nested function support. */
7388 /* Emit RTL insns to initialize the variable parts of a trampoline.
7389 FNADDR is an RTX for the address of the function's pure code.
7390 CXT is an RTX for the static chain value for the function.
7392 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7393 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7394 (to store insns). This is a bit excessive. Perhaps a different
7395 mechanism would be better here.
7397 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7400 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7402 /* SPARC 32-bit trampoline:
7405 sethi %hi(static), %g2
7407 or %g2, %lo(static), %g2
7409 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7410 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7414 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7415 expand_binop (SImode, ior_optab,
7416 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7417 size_int (10), 0, 1),
7418 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7419 NULL_RTX, 1, OPTAB_DIRECT));
7422 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7423 expand_binop (SImode, ior_optab,
7424 expand_shift (RSHIFT_EXPR, SImode, cxt,
7425 size_int (10), 0, 1),
7426 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7427 NULL_RTX, 1, OPTAB_DIRECT));
7430 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7431 expand_binop (SImode, ior_optab,
7432 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7433 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7434 NULL_RTX, 1, OPTAB_DIRECT));
7437 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7438 expand_binop (SImode, ior_optab,
7439 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7440 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7441 NULL_RTX, 1, OPTAB_DIRECT));
7443 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7444 aligned on a 16 byte boundary so one flush clears it all. */
7445 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7446 if (sparc_cpu != PROCESSOR_ULTRASPARC
7447 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7448 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7449 plus_constant (tramp, 8)))));
7451 /* Call __enable_execute_stack after writing onto the stack to make sure
7452 the stack address is accessible. */
7453 #ifdef TRANSFER_FROM_TRAMPOLINE
7454 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7455 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7460 /* The 64-bit version is simpler because it makes more sense to load the
7461 values as "immediate" data out of the trampoline. It's also easier since
7462 we can read the PC without clobbering a register. */
7465 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7467 /* SPARC 64-bit trampoline:
7476 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7477 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7478 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7479 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7480 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7481 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7482 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7483 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7484 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7485 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7486 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7488 if (sparc_cpu != PROCESSOR_ULTRASPARC
7489 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7490 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7492 /* Call __enable_execute_stack after writing onto the stack to make sure
7493 the stack address is accessible. */
7494 #ifdef TRANSFER_FROM_TRAMPOLINE
7495 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7496 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7500 /* Adjust the cost of a scheduling dependency. Return the new cost of
7501 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7504 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7506 enum attr_type insn_type;
7508 if (! recog_memoized (insn))
7511 insn_type = get_attr_type (insn);
7513 if (REG_NOTE_KIND (link) == 0)
7515 /* Data dependency; DEP_INSN writes a register that INSN reads some
7518 /* if a load, then the dependence must be on the memory address;
7519 add an extra "cycle". Note that the cost could be two cycles
7520 if the reg was written late in an instruction group; we ca not tell
7522 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7525 /* Get the delay only if the address of the store is the dependence. */
7526 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7528 rtx pat = PATTERN(insn);
7529 rtx dep_pat = PATTERN (dep_insn);
7531 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7532 return cost; /* This should not happen! */
7534 /* The dependency between the two instructions was on the data that
7535 is being stored. Assume that this implies that the address of the
7536 store is not dependent. */
7537 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7540 return cost + 3; /* An approximation. */
7543 /* A shift instruction cannot receive its data from an instruction
7544 in the same cycle; add a one cycle penalty. */
7545 if (insn_type == TYPE_SHIFT)
7546 return cost + 3; /* Split before cascade into shift. */
7550 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7551 INSN writes some cycles later. */
7553 /* These are only significant for the fpu unit; writing a fp reg before
7554 the fpu has finished with it stalls the processor. */
7556 /* Reusing an integer register causes no problems. */
7557 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7565 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7567 enum attr_type insn_type, dep_type;
7568 rtx pat = PATTERN(insn);
7569 rtx dep_pat = PATTERN (dep_insn);
7571 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7574 insn_type = get_attr_type (insn);
7575 dep_type = get_attr_type (dep_insn);
7577 switch (REG_NOTE_KIND (link))
7580 /* Data dependency; DEP_INSN writes a register that INSN reads some
7587 /* Get the delay iff the address of the store is the dependence. */
7588 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7591 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7598 /* If a load, then the dependence must be on the memory address. If
7599 the addresses aren't equal, then it might be a false dependency */
7600 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7602 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7603 || GET_CODE (SET_DEST (dep_pat)) != MEM
7604 || GET_CODE (SET_SRC (pat)) != MEM
7605 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7606 XEXP (SET_SRC (pat), 0)))
7614 /* Compare to branch latency is 0. There is no benefit from
7615 separating compare and branch. */
7616 if (dep_type == TYPE_COMPARE)
7618 /* Floating point compare to branch latency is less than
7619 compare to conditional move. */
7620 if (dep_type == TYPE_FPCMP)
7629 /* Anti-dependencies only penalize the fpu unit. */
7630 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7642 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7646 case PROCESSOR_SUPERSPARC:
7647 cost = supersparc_adjust_cost (insn, link, dep, cost);
7649 case PROCESSOR_HYPERSPARC:
7650 case PROCESSOR_SPARCLITE86X:
7651 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7660 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7661 int sched_verbose ATTRIBUTE_UNUSED,
7662 int max_ready ATTRIBUTE_UNUSED)
7667 sparc_use_dfa_pipeline_interface (void)
7669 if ((1 << sparc_cpu) &
7670 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
7671 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7672 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
7673 (1 << PROCESSOR_ULTRASPARC3)))
7679 sparc_use_sched_lookahead (void)
7681 if (sparc_cpu == PROCESSOR_ULTRASPARC
7682 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7684 if ((1 << sparc_cpu) &
7685 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7686 (1 << PROCESSOR_SPARCLITE86X)))
7692 sparc_issue_rate (void)
7699 /* Assume V9 processors are capable of at least dual-issue. */
7701 case PROCESSOR_SUPERSPARC:
7703 case PROCESSOR_HYPERSPARC:
7704 case PROCESSOR_SPARCLITE86X:
7706 case PROCESSOR_ULTRASPARC:
7707 case PROCESSOR_ULTRASPARC3:
7713 set_extends (rtx insn)
7715 register rtx pat = PATTERN (insn);
7717 switch (GET_CODE (SET_SRC (pat)))
7719 /* Load and some shift instructions zero extend. */
7722 /* sethi clears the high bits */
7724 /* LO_SUM is used with sethi. sethi cleared the high
7725 bits and the values used with lo_sum are positive */
7727 /* Store flag stores 0 or 1 */
7737 rtx op0 = XEXP (SET_SRC (pat), 0);
7738 rtx op1 = XEXP (SET_SRC (pat), 1);
7739 if (GET_CODE (op1) == CONST_INT)
7740 return INTVAL (op1) >= 0;
7741 if (GET_CODE (op0) != REG)
7743 if (sparc_check_64 (op0, insn) == 1)
7745 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7750 rtx op0 = XEXP (SET_SRC (pat), 0);
7751 rtx op1 = XEXP (SET_SRC (pat), 1);
7752 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7754 if (GET_CODE (op1) == CONST_INT)
7755 return INTVAL (op1) >= 0;
7756 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7759 return GET_MODE (SET_SRC (pat)) == SImode;
7760 /* Positive integers leave the high bits zero. */
7762 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7764 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7767 return - (GET_MODE (SET_SRC (pat)) == SImode);
7769 return sparc_check_64 (SET_SRC (pat), insn);
7775 /* We _ought_ to have only one kind per function, but... */
7776 static GTY(()) rtx sparc_addr_diff_list;
7777 static GTY(()) rtx sparc_addr_list;
7780 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7782 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7784 sparc_addr_diff_list
7785 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7787 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7791 sparc_output_addr_vec (rtx vec)
7793 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7794 int idx, vlen = XVECLEN (body, 0);
7796 #ifdef ASM_OUTPUT_ADDR_VEC_START
7797 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7800 #ifdef ASM_OUTPUT_CASE_LABEL
7801 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7804 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7807 for (idx = 0; idx < vlen; idx++)
7809 ASM_OUTPUT_ADDR_VEC_ELT
7810 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7813 #ifdef ASM_OUTPUT_ADDR_VEC_END
7814 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7819 sparc_output_addr_diff_vec (rtx vec)
7821 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7822 rtx base = XEXP (XEXP (body, 0), 0);
7823 int idx, vlen = XVECLEN (body, 1);
7825 #ifdef ASM_OUTPUT_ADDR_VEC_START
7826 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7829 #ifdef ASM_OUTPUT_CASE_LABEL
7830 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7833 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7836 for (idx = 0; idx < vlen; idx++)
7838 ASM_OUTPUT_ADDR_DIFF_ELT
7841 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7842 CODE_LABEL_NUMBER (base));
7845 #ifdef ASM_OUTPUT_ADDR_VEC_END
7846 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7851 sparc_output_deferred_case_vectors (void)
7856 if (sparc_addr_list == NULL_RTX
7857 && sparc_addr_diff_list == NULL_RTX)
7860 /* Align to cache line in the function's code section. */
7861 function_section (current_function_decl);
7863 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7865 ASM_OUTPUT_ALIGN (asm_out_file, align);
7867 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7868 sparc_output_addr_vec (XEXP (t, 0));
7869 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7870 sparc_output_addr_diff_vec (XEXP (t, 0));
7872 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7875 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7876 unknown. Return 1 if the high bits are zero, -1 if the register is
7879 sparc_check_64 (rtx x, rtx insn)
7881 /* If a register is set only once it is safe to ignore insns this
7882 code does not know how to handle. The loop will either recognize
7883 the single set and return the correct value or fail to recognize
7888 if (GET_CODE (x) != REG)
7891 if (GET_MODE (x) == DImode)
7892 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7894 if (flag_expensive_optimizations
7895 && REG_N_SETS (REGNO (y)) == 1)
7901 insn = get_last_insn_anywhere ();
7906 while ((insn = PREV_INSN (insn)))
7908 switch (GET_CODE (insn))
7921 rtx pat = PATTERN (insn);
7922 if (GET_CODE (pat) != SET)
7924 if (rtx_equal_p (x, SET_DEST (pat)))
7925 return set_extends (insn);
7926 if (y && rtx_equal_p (y, SET_DEST (pat)))
7927 return set_extends (insn);
7928 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
7936 /* Returns assembly code to perform a DImode shift using
7937 a 64-bit global or out register on SPARC-V8+. */
7939 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
7941 static char asm_code[60];
7943 /* The scratch register is only required when the destination
7944 register is not a 64-bit global or out register. */
7945 if (which_alternative != 2)
7946 operands[3] = operands[0];
7948 /* We can only shift by constants <= 63. */
7949 if (GET_CODE (operands[2]) == CONST_INT)
7950 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7952 if (GET_CODE (operands[1]) == CONST_INT)
7954 output_asm_insn ("mov\t%1, %3", operands);
7958 output_asm_insn ("sllx\t%H1, 32, %3", operands);
7959 if (sparc_check_64 (operands[1], insn) <= 0)
7960 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7961 output_asm_insn ("or\t%L1, %3, %3", operands);
7964 strcpy(asm_code, opcode);
7966 if (which_alternative != 2)
7967 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7969 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7972 /* Output rtl to increment the profiler label LABELNO
7973 for profiling a function entry. */
7976 sparc_profile_hook (int labelno)
7981 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7982 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
7983 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
7985 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
7988 #ifdef OBJECT_FORMAT_ELF
7990 sparc_elf_asm_named_section (const char *name, unsigned int flags)
7992 if (flags & SECTION_MERGE)
7994 /* entsize cannot be expressed in this section attributes
7996 default_elf_asm_named_section (name, flags);
8000 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8002 if (!(flags & SECTION_DEBUG))
8003 fputs (",#alloc", asm_out_file);
8004 if (flags & SECTION_WRITE)
8005 fputs (",#write", asm_out_file);
8006 if (flags & SECTION_TLS)
8007 fputs (",#tls", asm_out_file);
8008 if (flags & SECTION_CODE)
8009 fputs (",#execinstr", asm_out_file);
8011 /* ??? Handle SECTION_BSS. */
8013 fputc ('\n', asm_out_file);
8015 #endif /* OBJECT_FORMAT_ELF */
8017 /* We do not allow indirect calls to be optimized into sibling calls.
8019 Also, on SPARC 32-bit we cannot emit a sibling call when the
8020 current function returns a structure. This is because the "unimp
8021 after call" convention would cause the callee to return to the
8022 wrong place. The generic code already disallows cases where the
8023 function being called returns a structure.
8025 It may seem strange how this last case could occur. Usually there
8026 is code after the call which jumps to epilogue code which dumps the
8027 return value into the struct return area. That ought to invalidate
8028 the sibling call right? Well, in the c++ case we can end up passing
8029 the pointer to the struct return area to a constructor (which returns
8030 void) and then nothing else happens. Such a sibling call would look
8031 valid without the added check here. */
8033 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8035 return (decl && (TARGET_ARCH64 || ! current_function_returns_struct));
8038 /* libfunc renaming. */
8039 #include "config/gofast.h"
8042 sparc_init_libfuncs (void)
8046 /* Use the subroutines that Sun's library provides for integer
8047 multiply and divide. The `*' prevents an underscore from
8048 being prepended by the compiler. .umul is a little faster
8050 set_optab_libfunc (smul_optab, SImode, "*.umul");
8051 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8052 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8053 set_optab_libfunc (smod_optab, SImode, "*.rem");
8054 set_optab_libfunc (umod_optab, SImode, "*.urem");
8056 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8057 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8058 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8059 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8060 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8061 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8063 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8064 is because with soft-float, the SFmode and DFmode sqrt
8065 instructions will be absent, and the compiler will notice and
8066 try to use the TFmode sqrt instruction for calls to the
8067 builtin function sqrt, but this fails. */
8069 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8071 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8072 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8073 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8074 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8075 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8076 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8078 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8079 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8080 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8081 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8083 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8084 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8085 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8087 if (SUN_CONVERSION_LIBFUNCS)
8089 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8090 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8091 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8092 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8097 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8098 do not exist in the library. Make sure the compiler does not
8099 emit calls to them by accident. (It should always use the
8100 hardware instructions.) */
8101 set_optab_libfunc (smul_optab, SImode, 0);
8102 set_optab_libfunc (sdiv_optab, SImode, 0);
8103 set_optab_libfunc (udiv_optab, SImode, 0);
8104 set_optab_libfunc (smod_optab, SImode, 0);
8105 set_optab_libfunc (umod_optab, SImode, 0);
8107 if (SUN_INTEGER_MULTIPLY_64)
8109 set_optab_libfunc (smul_optab, DImode, "__mul64");
8110 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8111 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8112 set_optab_libfunc (smod_optab, DImode, "__rem64");
8113 set_optab_libfunc (umod_optab, DImode, "__urem64");
8116 if (SUN_CONVERSION_LIBFUNCS)
8118 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8119 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8120 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8121 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8125 gofast_maybe_init_libfuncs ();
8128 /* ??? Similar to the standard section selection, but force reloc-y-ness
8129 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8130 pretending PIC always on), but that's what the old code did. */
8133 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8135 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8138 /* Use text section for a constant unless we need more alignment than
8142 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8143 unsigned HOST_WIDE_INT align)
8145 if (align <= MAX_TEXT_ALIGN
8146 && ! (flag_pic && (symbolic_operand (x, mode)
8147 || SUNOS4_SHARED_LIBRARIES)))
8148 readonly_data_section ();
8154 sparc_extra_constraint_check (rtx op, int c, int strict)
8159 && (c == 'T' || c == 'U'))
8165 return fp_sethi_p (op);
8168 return fp_mov_p (op);
8171 return fp_high_losum_p (op);
8175 || (GET_CODE (op) == REG
8176 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8177 || reg_renumber[REGNO (op)] >= 0)))
8178 return register_ok_for_ldd (op);
8190 /* Our memory extra constraints have to emulate the
8191 behavior of 'm' and 'o' in order for reload to work
8193 if (GET_CODE (op) == MEM)
8196 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8198 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8203 reload_ok_mem = (reload_in_progress
8204 && GET_CODE (op) == REG
8205 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8206 && reg_renumber [REGNO (op)] < 0);
8209 return reload_ok_mem;
8212 /* ??? This duplicates information provided to the compiler by the
8213 ??? scheduler description. Some day, teach genautomata to output
8214 ??? the latencies and then CSE will just use that. */
8217 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8221 case PLUS: case MINUS: case ABS: case NEG:
8222 case FLOAT: case UNSIGNED_FLOAT:
8223 case FIX: case UNSIGNED_FIX:
8224 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8225 if (FLOAT_MODE_P (GET_MODE (x)))
8229 case PROCESSOR_ULTRASPARC:
8230 case PROCESSOR_ULTRASPARC3:
8231 *total = COSTS_N_INSNS (4);
8234 case PROCESSOR_SUPERSPARC:
8235 *total = COSTS_N_INSNS (3);
8238 case PROCESSOR_CYPRESS:
8239 *total = COSTS_N_INSNS (5);
8242 case PROCESSOR_HYPERSPARC:
8243 case PROCESSOR_SPARCLITE86X:
8245 *total = COSTS_N_INSNS (1);
8250 *total = COSTS_N_INSNS (1);
8256 case PROCESSOR_ULTRASPARC:
8257 if (GET_MODE (x) == SFmode)
8258 *total = COSTS_N_INSNS (13);
8260 *total = COSTS_N_INSNS (23);
8263 case PROCESSOR_ULTRASPARC3:
8264 if (GET_MODE (x) == SFmode)
8265 *total = COSTS_N_INSNS (20);
8267 *total = COSTS_N_INSNS (29);
8270 case PROCESSOR_SUPERSPARC:
8271 *total = COSTS_N_INSNS (12);
8274 case PROCESSOR_CYPRESS:
8275 *total = COSTS_N_INSNS (63);
8278 case PROCESSOR_HYPERSPARC:
8279 case PROCESSOR_SPARCLITE86X:
8280 *total = COSTS_N_INSNS (17);
8284 *total = COSTS_N_INSNS (30);
8289 if (FLOAT_MODE_P (GET_MODE (x)))
8293 case PROCESSOR_ULTRASPARC:
8294 case PROCESSOR_ULTRASPARC3:
8295 *total = COSTS_N_INSNS (1);
8298 case PROCESSOR_SUPERSPARC:
8299 *total = COSTS_N_INSNS (3);
8302 case PROCESSOR_CYPRESS:
8303 *total = COSTS_N_INSNS (5);
8306 case PROCESSOR_HYPERSPARC:
8307 case PROCESSOR_SPARCLITE86X:
8309 *total = COSTS_N_INSNS (1);
8314 /* ??? Maybe mark integer compares as zero cost on
8315 ??? all UltraSPARC processors because the result
8316 ??? can be bypassed to a branch in the same group. */
8318 *total = COSTS_N_INSNS (1);
8322 if (FLOAT_MODE_P (GET_MODE (x)))
8326 case PROCESSOR_ULTRASPARC:
8327 case PROCESSOR_ULTRASPARC3:
8328 *total = COSTS_N_INSNS (4);
8331 case PROCESSOR_SUPERSPARC:
8332 *total = COSTS_N_INSNS (3);
8335 case PROCESSOR_CYPRESS:
8336 *total = COSTS_N_INSNS (7);
8339 case PROCESSOR_HYPERSPARC:
8340 case PROCESSOR_SPARCLITE86X:
8341 *total = COSTS_N_INSNS (1);
8345 *total = COSTS_N_INSNS (5);
8350 /* The latency is actually variable for Ultra-I/II
8351 And if one of the inputs have a known constant
8352 value, we could calculate this precisely.
8354 However, for that to be useful we would need to
8355 add some machine description changes which would
8356 make sure small constants ended up in rs1 of the
8357 multiply instruction. This is because the multiply
8358 latency is determined by the number of clear (or
8359 set if the value is negative) bits starting from
8360 the most significant bit of the first input.
8362 The algorithm for computing num_cycles of a multiply
8366 highest_bit = highest_clear_bit(rs1);
8368 highest_bit = highest_set_bit(rs1);
8371 num_cycles = 4 + ((highest_bit - 3) / 2);
8373 If we did that we would have to also consider register
8374 allocation issues that would result from forcing such
8375 a value into a register.
8377 There are other similar tricks we could play if we
8378 knew, for example, that one input was an array index.
8380 Since we do not play any such tricks currently the
8381 safest thing to do is report the worst case latency. */
8382 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8384 *total = (GET_MODE (x) == DImode
8385 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8389 /* Multiply latency on Ultra-III, fortunately, is constant. */
8390 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8392 *total = COSTS_N_INSNS (6);
8396 if (sparc_cpu == PROCESSOR_HYPERSPARC
8397 || sparc_cpu == PROCESSOR_SPARCLITE86X)
8399 *total = COSTS_N_INSNS (17);
8403 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8410 if (FLOAT_MODE_P (GET_MODE (x)))
8414 case PROCESSOR_ULTRASPARC:
8415 if (GET_MODE (x) == SFmode)
8416 *total = COSTS_N_INSNS (13);
8418 *total = COSTS_N_INSNS (23);
8421 case PROCESSOR_ULTRASPARC3:
8422 if (GET_MODE (x) == SFmode)
8423 *total = COSTS_N_INSNS (17);
8425 *total = COSTS_N_INSNS (20);
8428 case PROCESSOR_SUPERSPARC:
8429 if (GET_MODE (x) == SFmode)
8430 *total = COSTS_N_INSNS (6);
8432 *total = COSTS_N_INSNS (9);
8435 case PROCESSOR_HYPERSPARC:
8436 case PROCESSOR_SPARCLITE86X:
8437 if (GET_MODE (x) == SFmode)
8438 *total = COSTS_N_INSNS (8);
8440 *total = COSTS_N_INSNS (12);
8444 *total = COSTS_N_INSNS (7);
8449 if (sparc_cpu == PROCESSOR_ULTRASPARC)
8450 *total = (GET_MODE (x) == DImode
8451 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8452 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
8453 *total = (GET_MODE (x) == DImode
8454 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8456 *total = COSTS_N_INSNS (25);
8460 /* Conditional moves. */
8463 case PROCESSOR_ULTRASPARC:
8464 *total = COSTS_N_INSNS (2);
8467 case PROCESSOR_ULTRASPARC3:
8468 if (FLOAT_MODE_P (GET_MODE (x)))
8469 *total = COSTS_N_INSNS (3);
8471 *total = COSTS_N_INSNS (2);
8475 *total = COSTS_N_INSNS (1);
8480 /* If outer-code is SIGN/ZERO extension we have to subtract
8481 out COSTS_N_INSNS (1) from whatever we return in determining
8485 case PROCESSOR_ULTRASPARC:
8486 if (outer_code == ZERO_EXTEND)
8487 *total = COSTS_N_INSNS (1);
8489 *total = COSTS_N_INSNS (2);
8492 case PROCESSOR_ULTRASPARC3:
8493 if (outer_code == ZERO_EXTEND)
8495 if (GET_MODE (x) == QImode
8496 || GET_MODE (x) == HImode
8497 || outer_code == SIGN_EXTEND)
8498 *total = COSTS_N_INSNS (2);
8500 *total = COSTS_N_INSNS (1);
8504 /* This handles sign extension (3 cycles)
8505 and everything else (2 cycles). */
8506 *total = COSTS_N_INSNS (2);
8510 case PROCESSOR_SUPERSPARC:
8511 if (FLOAT_MODE_P (GET_MODE (x))
8512 || outer_code == ZERO_EXTEND
8513 || outer_code == SIGN_EXTEND)
8514 *total = COSTS_N_INSNS (0);
8516 *total = COSTS_N_INSNS (1);
8519 case PROCESSOR_TSC701:
8520 if (outer_code == ZERO_EXTEND
8521 || outer_code == SIGN_EXTEND)
8522 *total = COSTS_N_INSNS (2);
8524 *total = COSTS_N_INSNS (3);
8527 case PROCESSOR_CYPRESS:
8528 if (outer_code == ZERO_EXTEND
8529 || outer_code == SIGN_EXTEND)
8530 *total = COSTS_N_INSNS (1);
8532 *total = COSTS_N_INSNS (2);
8535 case PROCESSOR_HYPERSPARC:
8536 case PROCESSOR_SPARCLITE86X:
8538 if (outer_code == ZERO_EXTEND
8539 || outer_code == SIGN_EXTEND)
8540 *total = COSTS_N_INSNS (0);
8542 *total = COSTS_N_INSNS (1);
8547 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8565 if (GET_MODE (x) == DImode
8566 && ((XINT (x, 3) == 0
8567 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8568 || (XINT (x, 3) == -1
8570 && XINT (x, 2) >= -0x1000)))
8581 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8582 Used for C++ multiple inheritance. */
8585 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8586 HOST_WIDE_INT delta,
8587 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8590 rtx this, insn, funexp, delta_rtx, tmp;
8592 reload_completed = 1;
8593 epilogue_completed = 1;
8595 current_function_uses_only_leaf_regs = 1;
8597 emit_note (NOTE_INSN_PROLOGUE_END);
8599 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8600 returns a structure, the structure return pointer is there instead. */
8601 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8602 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
8604 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
8606 /* Add DELTA. When possible use a plain add, otherwise load it into
8607 a register first. */
8608 delta_rtx = GEN_INT (delta);
8609 if (!SPARC_SIMM13_P (delta))
8611 rtx scratch = gen_rtx_REG (Pmode, 1);
8613 if (input_operand (delta_rtx, GET_MODE (scratch)))
8614 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8618 sparc_emit_set_const64 (scratch, delta_rtx);
8620 sparc_emit_set_const32 (scratch, delta_rtx);
8623 delta_rtx = scratch;
8626 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
8627 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
8629 /* Generate a tail call to the target function. */
8630 if (! TREE_USED (function))
8632 assemble_external (function);
8633 TREE_USED (function) = 1;
8635 funexp = XEXP (DECL_RTL (function), 0);
8636 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8637 insn = emit_call_insn (gen_sibcall (funexp));
8638 SIBLING_CALL_P (insn) = 1;
8641 /* Run just enough of rest_of_compilation to get the insns emitted.
8642 There's not really enough bulk here to make other passes such as
8643 instruction scheduling worth while. Note that use_thunk calls
8644 assemble_start_function and assemble_end_function. */
8645 insn = get_insns ();
8646 insn_locators_initialize ();
8647 shorten_branches (insn);
8648 final_start_function (insn, file, 1);
8649 final (insn, file, 1, 0);
8650 final_end_function ();
8652 reload_completed = 0;
8653 epilogue_completed = 0;
8657 /* How to allocate a 'struct machine_function'. */
8659 static struct machine_function *
8660 sparc_init_machine_status (void)
8662 return ggc_alloc_cleared (sizeof (struct machine_function));
8665 /* Locate some local-dynamic symbol still in use by this function
8666 so that we can print its name in local-dynamic base patterns. */
8669 get_some_local_dynamic_name (void)
8673 if (cfun->machine->some_ld_name)
8674 return cfun->machine->some_ld_name;
8676 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8678 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8679 return cfun->machine->some_ld_name;
8685 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8690 && GET_CODE (x) == SYMBOL_REF
8691 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8693 cfun->machine->some_ld_name = XSTR (x, 0);
8700 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8701 We need to emit DTP-relative relocations. */
8704 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8709 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8712 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8717 output_addr_const (file, x);
8721 #include "gt-sparc.h"