1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-96, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
40 /* 1 if the caller has placed an "unimp" insn immediately after the call.
41 This is used in v8 code when calling a function that returns a structure.
42 v9 doesn't have this. Be careful to have this test be the same as that
45 #define SKIP_CALLERS_UNIMP_P \
46 (!TARGET_ARCH64 && current_function_returns_struct \
47 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
48 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
51 /* Global variables for machine-dependent things. */
53 /* Size of frame. Need to know this to emit return insns from leaf procedures.
54 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
55 reload pass. This is important as the value is later used in insn
56 scheduling (to see what can go in a delay slot).
57 APPARENT_FSIZE is the size of the stack less the register save area and less
58 the outgoing argument area. It is used when saving call preserved regs. */
59 static int apparent_fsize;
60 static int actual_fsize;
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx sparc_compare_op0, sparc_compare_op1;
67 /* We may need an epilogue if we spill too many registers.
68 If this is non-zero, then we branch here for the epilogue. */
69 static rtx leaf_label;
73 /* Vector to say how input registers are mapped to output
74 registers. FRAME_POINTER_REGNUM cannot be remapped by
75 this function to eliminate it. You must use -fomit-frame-pointer
77 char leaf_reg_remap[] =
78 { 0, 1, 2, 3, 4, 5, 6, 7,
79 -1, -1, -1, -1, -1, -1, 14, -1,
80 -1, -1, -1, -1, -1, -1, -1, -1,
81 8, 9, 10, 11, 12, 13, -1, 15,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 40, 41, 42, 43, 44, 45, 46, 47,
85 48, 49, 50, 51, 52, 53, 54, 55,
86 56, 57, 58, 59, 60, 61, 62, 63,
87 64, 65, 66, 67, 68, 69, 70, 71,
88 72, 73, 74, 75, 76, 77, 78, 79,
89 80, 81, 82, 83, 84, 85, 86, 87,
90 88, 89, 90, 91, 92, 93, 94, 95,
95 /* Name of where we pretend to think the frame pointer points.
96 Normally, this is "%fp", but if we are in a leaf procedure,
97 this is "%sp+something". We record "something" separately as it may be
98 too big for reg+constant addressing. */
100 static char *frame_base_name;
101 static int frame_base_offset;
103 static rtx find_addr_reg ();
104 static void sparc_init_modes ();
106 /* Option handling. */
108 /* Record options as passed by user. */
109 char *sparc_align_loops_string;
110 char *sparc_align_jumps_string;
111 char *sparc_align_funcs_string;
113 /* Parsed values, as a power of two. */
114 int sparc_align_loops;
115 int sparc_align_jumps;
116 int sparc_align_funcs;
118 struct sparc_cpu_select sparc_select[] =
120 /* switch name, tune arch */
121 { (char *)0, "default", 1, 1 },
122 { (char *)0, "-mcpu=", 1, 1 },
123 { (char *)0, "-mtune=", 1, 0 },
127 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
128 enum processor_type sparc_cpu;
130 /* Validate and override various options, and do some machine dependent
134 sparc_override_options ()
136 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
137 static struct cpu_default {
141 { TARGET_CPU_sparc, "cypress" },
142 { TARGET_CPU_v8, "v8" },
143 { TARGET_CPU_supersparc, "supersparc" },
144 { TARGET_CPU_sparclet, "tsc701" },
145 { TARGET_CPU_sparclite, "f930" },
146 { TARGET_CPU_ultrasparc, "ultrasparc" },
149 struct cpu_default *def;
150 /* Table of values for -m{cpu,tune}=. */
151 static struct cpu_table {
153 enum processor_type processor;
157 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
158 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
159 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
160 /* TI TMS390Z55 supersparc */
161 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
162 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
163 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
164 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
165 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
166 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
167 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
169 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
170 /* "v9" is used to specify a true 64 bit architecture.
171 "v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */
172 { "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 },
174 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
177 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
180 struct cpu_table *cpu;
181 struct sparc_cpu_select *sel;
183 int fpu = TARGET_FPU; /* save current -mfpu status */
185 /* Set the default. */
186 for (def = &cpu_default[0]; def->name; ++def)
187 if (def->cpu == TARGET_CPU_DEFAULT)
191 sparc_select[0].string = def->name;
193 for (sel = &sparc_select[0]; sel->name; ++sel)
197 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
198 if (! strcmp (sel->string, cpu->name))
201 sparc_cpu = cpu->processor;
205 target_flags &= ~cpu->disable;
206 target_flags |= cpu->enable;
212 error ("bad value (%s) for %s switch", sel->string, sel->name);
216 /* If -mfpu or -mno-fpu was explicitly used, don't override with
217 the processor default. */
219 target_flags = (target_flags & ~MASK_FPU) | fpu;
221 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
222 if (TARGET_V9 && TARGET_ARCH32)
223 target_flags |= MASK_DEPRECATED_V8_INSNS;
225 /* Validate -malign-loops= value, or provide default. */
226 if (sparc_align_loops_string)
228 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
229 if (sparc_align_loops < 2 || sparc_align_loops > 7)
230 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
231 sparc_align_loops_string);
235 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
236 its 0. This sounds a bit kludgey. */
237 sparc_align_loops = 0;
240 /* Validate -malign-jumps= value, or provide default. */
241 if (sparc_align_jumps_string)
243 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
244 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
245 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
246 sparc_align_jumps_string);
250 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
251 its 0. This sounds a bit kludgey. */
252 sparc_align_jumps = 0;
255 /* Validate -malign-functions= value, or provide default. */
256 if (sparc_align_funcs_string)
258 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
259 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
260 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
261 sparc_align_funcs_string);
264 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
266 /* Do various machine dependent initializations. */
270 /* Float conversions (v9 only).
272 The floating point registers cannot hold DImode values because SUBREG's
273 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
274 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
275 turn the "0" to a "1". Therefore, we must explicitly do the conversions
276 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
277 8 byte stack slot used during the transfer.
278 ??? I could have used [%fp-16] but I didn't want to add yet another
279 dependence on this. */
280 /* ??? Can we use assign_stack_temp here? */
282 static rtx fpconv_stack_temp;
284 /* Called once for each function. */
287 sparc64_init_expanders ()
289 fpconv_stack_temp = NULL_RTX;
292 /* Assign a stack temp for fp/int DImode conversions. */
295 sparc64_fpconv_stack_temp ()
297 if (fpconv_stack_temp == NULL_RTX)
299 assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
301 return fpconv_stack_temp;
304 /* Miscellaneous utilities. */
306 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
307 or branch on register contents instructions. */
313 return (code == EQ || code == NE || code == GE || code == LT
314 || code == LE || code == GT);
317 /* Operand constraints. */
319 /* Return non-zero only if OP is a register of mode MODE,
320 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
321 %g0 may contain anything. */
324 reg_or_0_operand (op, mode)
326 enum machine_mode mode;
328 if (register_operand (op, mode))
332 if (op == const0_rtx)
334 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
335 && CONST_DOUBLE_HIGH (op) == 0
336 && CONST_DOUBLE_LOW (op) == 0)
338 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
339 && GET_CODE (op) == CONST_DOUBLE
340 && fp_zero_operand (op))
345 /* Nonzero if OP is a floating point value with value 0.0. */
353 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
354 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
357 /* Nonzero if OP is an integer register. */
360 intreg_operand (op, mode)
362 enum machine_mode mode;
364 return (register_operand (op, SImode)
365 || (TARGET_ARCH64 && register_operand (op, DImode)));
368 /* Nonzero if OP is a floating point condition code register. */
371 fcc_reg_operand (op, mode)
373 enum machine_mode mode;
375 /* This can happen when recog is called from combine. Op may be a MEM.
376 Fail instead of calling abort in this case. */
377 if (GET_CODE (op) != REG)
380 if (mode != VOIDmode && mode != GET_MODE (op))
383 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
386 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
387 if (reg_renumber == 0)
388 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
389 return REGNO_OK_FOR_CCFP_P (REGNO (op));
391 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
395 /* Nonzero if OP is an integer or floating point condition code register. */
398 icc_or_fcc_reg_operand (op, mode)
400 enum machine_mode mode;
402 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
404 if (mode != VOIDmode && mode != GET_MODE (op))
407 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
412 return fcc_reg_operand (op, mode);
415 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
417 restore_operand (op, mode)
419 enum machine_mode mode;
421 return (GET_CODE (op) == REG && GET_MODE (op) == mode
422 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
425 /* Call insn on SPARC can take a PC-relative constant address, or any regular
429 call_operand (op, mode)
431 enum machine_mode mode;
433 if (GET_CODE (op) != MEM)
436 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
440 call_operand_address (op, mode)
442 enum machine_mode mode;
444 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
447 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
448 reference and a constant. */
451 symbolic_operand (op, mode)
453 enum machine_mode mode;
455 switch (GET_CODE (op))
463 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
464 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
465 && GET_CODE (XEXP (op, 1)) == CONST_INT);
467 /* ??? This clause seems to be irrelevant. */
469 return GET_MODE (op) == mode;
476 /* Return truth value of statement that OP is a symbolic memory
477 operand of mode MODE. */
480 symbolic_memory_operand (op, mode)
482 enum machine_mode mode;
484 if (GET_CODE (op) == SUBREG)
485 op = SUBREG_REG (op);
486 if (GET_CODE (op) != MEM)
489 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
490 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
493 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
496 label_ref_operand (op, mode)
498 enum machine_mode mode;
500 if (GET_CODE (op) != LABEL_REF)
502 if (GET_MODE (op) != mode)
507 /* Return 1 if the operand is an argument used in generating pic references
508 in either the medium/low or medium/anywhere code models of sparc64. */
511 sp64_medium_pic_operand (op, mode)
513 enum machine_mode mode;
515 /* Check for (const (minus (symbol_ref:GOT)
516 (const (minus (label) (pc))))). */
517 if (GET_CODE (op) != CONST)
520 if (GET_CODE (op) != MINUS)
522 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
524 /* ??? Ensure symbol is GOT. */
525 if (GET_CODE (XEXP (op, 1)) != CONST)
527 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
532 /* Return 1 if the operand is a data segment reference. This includes
533 the readonly data segment, or in other words anything but the text segment.
534 This is needed in the medium/anywhere code model on v9. These values
535 are accessed with MEDANY_BASE_REG. */
538 data_segment_operand (op, mode)
540 enum machine_mode mode;
542 switch (GET_CODE (op))
545 return ! SYMBOL_REF_FLAG (op);
547 /* Assume canonical format of symbol + constant.
550 return data_segment_operand (XEXP (op, 0));
556 /* Return 1 if the operand is a text segment reference.
557 This is needed in the medium/anywhere code model on v9. */
560 text_segment_operand (op, mode)
562 enum machine_mode mode;
564 switch (GET_CODE (op))
569 return SYMBOL_REF_FLAG (op);
571 /* Assume canonical format of symbol + constant.
574 return text_segment_operand (XEXP (op, 0));
580 /* Return 1 if the operand is either a register or a memory operand that is
584 reg_or_nonsymb_mem_operand (op, mode)
586 enum machine_mode mode;
588 if (register_operand (op, mode))
591 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
598 sparc_operand (op, mode)
600 enum machine_mode mode;
602 if (register_operand (op, mode))
604 if (GET_CODE (op) == CONST_INT)
605 return SMALL_INT (op);
606 if (GET_MODE (op) != mode)
608 if (GET_CODE (op) == SUBREG)
609 op = SUBREG_REG (op);
610 if (GET_CODE (op) != MEM)
614 if (GET_CODE (op) == LO_SUM)
615 return (GET_CODE (XEXP (op, 0)) == REG
616 && symbolic_operand (XEXP (op, 1), Pmode));
617 return memory_address_p (mode, op);
621 move_operand (op, mode)
623 enum machine_mode mode;
625 if (mode == DImode && arith_double_operand (op, mode))
627 if (register_operand (op, mode))
629 if (GET_CODE (op) == CONST_INT)
630 return SMALL_INT (op) || SPARC_SETHI_P (INTVAL (op));
632 if (GET_MODE (op) != mode)
634 if (GET_CODE (op) == SUBREG)
635 op = SUBREG_REG (op);
636 if (GET_CODE (op) != MEM)
639 if (GET_CODE (op) == LO_SUM)
640 return (register_operand (XEXP (op, 0), Pmode)
641 && CONSTANT_P (XEXP (op, 1)));
642 return memory_address_p (mode, op);
646 splittable_symbolic_memory_operand (op, mode)
648 enum machine_mode mode;
650 if (GET_CODE (op) != MEM)
652 if (! symbolic_operand (XEXP (op, 0), Pmode))
658 splittable_immediate_memory_operand (op, mode)
660 enum machine_mode mode;
662 if (GET_CODE (op) != MEM)
664 if (! immediate_operand (XEXP (op, 0), Pmode))
669 /* Return truth value of whether OP is EQ or NE. */
674 enum machine_mode mode;
676 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
679 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
680 or LTU for non-floating-point. We handle those specially. */
683 normal_comp_operator (op, mode)
685 enum machine_mode mode;
687 enum rtx_code code = GET_CODE (op);
689 if (GET_RTX_CLASS (code) != '<')
692 if (GET_MODE (XEXP (op, 0)) == CCFPmode
693 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
696 return (code != NE && code != EQ && code != GEU && code != LTU);
699 /* Return 1 if this is a comparison operator. This allows the use of
700 MATCH_OPERATOR to recognize all the branch insns. */
703 noov_compare_op (op, mode)
705 enum machine_mode mode;
707 enum rtx_code code = GET_CODE (op);
709 if (GET_RTX_CLASS (code) != '<')
712 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
713 /* These are the only branches which work with CC_NOOVmode. */
714 return (code == EQ || code == NE || code == GE || code == LT);
718 /* Nonzero if OP is a comparison operator suitable for use in v9
719 conditional move or branch on register contents instructions. */
722 v9_regcmp_op (op, mode)
724 enum machine_mode mode;
726 enum rtx_code code = GET_CODE (op);
728 if (GET_RTX_CLASS (code) != '<')
731 return v9_regcmp_p (code);
734 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
739 enum machine_mode mode;
741 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
744 /* Return nonzero if OP is an operator of mode MODE which can set
745 the condition codes explicitly. We do not include PLUS and MINUS
746 because these require CC_NOOVmode, which we handle explicitly. */
749 cc_arithop (op, mode)
751 enum machine_mode mode;
753 if (GET_CODE (op) == AND
754 || GET_CODE (op) == IOR
755 || GET_CODE (op) == XOR)
761 /* Return nonzero if OP is an operator of mode MODE which can bitwise
762 complement its second operand and set the condition codes explicitly. */
765 cc_arithopn (op, mode)
767 enum machine_mode mode;
769 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
770 and (xor ... (not ...)) to (not (xor ...)). */
771 return (GET_CODE (op) == AND
772 || GET_CODE (op) == IOR);
775 /* Return true if OP is a register, or is a CONST_INT that can fit in a
776 signed 13 bit immediate field. This is an acceptable SImode operand for
777 most 3 address instructions. */
780 arith_operand (op, mode)
782 enum machine_mode mode;
784 return (register_operand (op, mode)
785 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
788 /* Return true if OP is a register, or is a CONST_INT that can fit in a
789 signed 11 bit immediate field. This is an acceptable SImode operand for
790 the movcc instructions. */
793 arith11_operand (op, mode)
795 enum machine_mode mode;
797 return (register_operand (op, mode)
798 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
801 /* Return true if OP is a register, or is a CONST_INT that can fit in a
802 signed 10 bit immediate field. This is an acceptable SImode operand for
803 the movrcc instructions. */
806 arith10_operand (op, mode)
808 enum machine_mode mode;
810 return (register_operand (op, mode)
811 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
814 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
815 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
817 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
818 can fit in a 13 bit immediate field. This is an acceptable DImode operand
819 for most 3 address instructions. */
822 arith_double_operand (op, mode)
824 enum machine_mode mode;
826 return (register_operand (op, mode)
827 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
829 && GET_CODE (op) == CONST_DOUBLE
830 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
831 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
833 && GET_CODE (op) == CONST_DOUBLE
834 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
835 && ((CONST_DOUBLE_HIGH (op) == -1
836 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
837 || (CONST_DOUBLE_HIGH (op) == 0
838 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
841 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
842 can fit in an 11 bit immediate field. This is an acceptable DImode
843 operand for the movcc instructions. */
844 /* ??? Replace with arith11_operand? */
847 arith11_double_operand (op, mode)
849 enum machine_mode mode;
851 return (register_operand (op, mode)
852 || (GET_CODE (op) == CONST_DOUBLE
853 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
854 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
855 && ((CONST_DOUBLE_HIGH (op) == -1
856 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
857 || (CONST_DOUBLE_HIGH (op) == 0
858 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
859 || (GET_CODE (op) == CONST_INT
860 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
861 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
864 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
865 can fit in an 10 bit immediate field. This is an acceptable DImode
866 operand for the movrcc instructions. */
867 /* ??? Replace with arith10_operand? */
870 arith10_double_operand (op, mode)
872 enum machine_mode mode;
874 return (register_operand (op, mode)
875 || (GET_CODE (op) == CONST_DOUBLE
876 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
877 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
878 && ((CONST_DOUBLE_HIGH (op) == -1
879 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
880 || (CONST_DOUBLE_HIGH (op) == 0
881 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
882 || (GET_CODE (op) == CONST_INT
883 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
884 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
887 /* Return truth value of whether OP is a integer which fits the
888 range constraining immediate operands in most three-address insns,
889 which have a 13 bit immediate field. */
894 enum machine_mode mode;
896 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
899 /* Recognize operand values for the umul instruction. That instruction sign
900 extends immediate values just like all other sparc instructions, but
901 interprets the extended result as an unsigned number. */
904 uns_small_int (op, mode)
906 enum machine_mode mode;
908 #if HOST_BITS_PER_WIDE_INT > 32
909 /* All allowed constants will fit a CONST_INT. */
910 return (GET_CODE (op) == CONST_INT
911 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
912 || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L)));
914 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
915 || (GET_CODE (op) == CONST_DOUBLE
916 && CONST_DOUBLE_HIGH (op) == 0
917 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
922 uns_arith_operand (op, mode)
924 enum machine_mode mode;
926 return register_operand (op, mode) || uns_small_int (op, mode);
929 /* Return truth value of statement that OP is a call-clobbered register. */
931 clobbered_register (op, mode)
933 enum machine_mode mode;
935 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
938 /* X and Y are two things to compare using CODE. Emit the compare insn and
939 return the rtx for the cc reg in the proper mode. */
942 gen_compare_reg (code, x, y)
946 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
949 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
950 fcc regs (cse can't tell they're really call clobbered regs and will
951 remove a duplicate comparison even if there is an intervening function
952 call - it will then try to reload the cc reg via an int reg which is why
953 we need the movcc patterns). It is possible to provide the movcc
954 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
955 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
956 to tell cse that CCFPE mode registers (even pseudos) are call
959 /* ??? This is an experiment. Rather than making changes to cse which may
960 or may not be easy/clean, we do our own cse. This is possible because
961 we will generate hard registers. Cse knows they're call clobbered (it
962 doesn't know the same thing about pseudos). If we guess wrong, no big
963 deal, but if we win, great! */
965 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
966 #if 1 /* experiment */
969 /* We cycle through the registers to ensure they're all exercised. */
970 static int next_fcc_reg = 0;
971 /* Previous x,y for each fcc reg. */
972 static rtx prev_args[4][2];
974 /* Scan prev_args for x,y. */
975 for (reg = 0; reg < 4; reg++)
976 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
981 prev_args[reg][0] = x;
982 prev_args[reg][1] = y;
983 next_fcc_reg = (next_fcc_reg + 1) & 3;
985 cc_reg = gen_rtx (REG, mode, reg + SPARC_FIRST_V9_FCC_REG);
988 cc_reg = gen_reg_rtx (mode);
989 #endif /* ! experiment */
990 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
991 cc_reg = gen_rtx (REG, mode, SPARC_FCC_REG);
993 cc_reg = gen_rtx (REG, mode, SPARC_ICC_REG);
995 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
996 gen_rtx (COMPARE, mode, x, y)));
1001 /* This function is used for v9 only.
1002 CODE is the code for an Scc's comparison.
1003 OPERANDS[0] is the target of the Scc insn.
1004 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1005 been generated yet).
1007 This function is needed to turn
1010 (gt (reg:CCX 100 %icc)
1014 (gt:DI (reg:CCX 100 %icc)
1017 IE: The instruction recognizer needs to see the mode of the comparison to
1018 find the right instruction. We could use "gt:DI" right in the
1019 define_expand, but leaving it out allows us to handle DI, SI, etc.
1021 We refer to the global sparc compare operands sparc_compare_op0 and
1022 sparc_compare_op1. */
1025 gen_v9_scc (compare_code, operands)
1026 enum rtx_code compare_code;
1027 register rtx *operands;
1032 && (GET_MODE (sparc_compare_op0) == DImode
1033 || GET_MODE (operands[0]) == DImode))
1036 /* Handle the case where operands[0] == sparc_compare_op0.
1037 We "early clobber" the result. */
1038 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
1040 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
1041 emit_move_insn (op0, sparc_compare_op0);
1044 op0 = sparc_compare_op0;
1045 /* For consistency in the following. */
1046 op1 = sparc_compare_op1;
1048 /* Try to use the movrCC insns. */
1050 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1051 && op1 == const0_rtx
1052 && v9_regcmp_p (compare_code))
1054 /* Special case for op0 != 0. This can be done with one instruction if
1055 operands[0] == sparc_compare_op0. We don't assume they are equal
1058 if (compare_code == NE
1059 && GET_MODE (operands[0]) == DImode
1060 && GET_MODE (op0) == DImode)
1062 emit_insn (gen_rtx (SET, VOIDmode, operands[0], op0));
1063 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1064 gen_rtx (IF_THEN_ELSE, DImode,
1065 gen_rtx (compare_code, DImode,
1072 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1073 if (GET_MODE (op0) != DImode)
1075 temp = gen_reg_rtx (DImode);
1076 convert_move (temp, op0, 0);
1080 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1081 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1082 gen_rtx (compare_code, DImode,
1090 operands[1] = gen_compare_reg (compare_code, op0, op1);
1092 switch (GET_MODE (operands[1]))
1102 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1103 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1104 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1105 gen_rtx (compare_code,
1106 GET_MODE (operands[1]),
1107 operands[1], const0_rtx),
1108 const1_rtx, operands[0])));
1113 /* Emit a conditional jump insn for the v9 architecture using comparison code
1114 CODE and jump target LABEL.
1115 This function exists to take advantage of the v9 brxx insns. */
1118 emit_v9_brxx_insn (code, op0, label)
1122 emit_jump_insn (gen_rtx (SET, VOIDmode,
1124 gen_rtx (IF_THEN_ELSE, VOIDmode,
1125 gen_rtx (code, GET_MODE (op0),
1127 gen_rtx (LABEL_REF, VOIDmode, label),
1131 /* Return nonzero if a return peephole merging return with
1132 setting of output register is ok. */
1134 leaf_return_peephole_ok ()
1136 return (actual_fsize == 0);
1139 /* Return nonzero if TRIAL can go into the function epilogue's
1140 delay slot. SLOT is the slot we are trying to fill. */
1143 eligible_for_epilogue_delay (trial, slot)
1152 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
1155 if (get_attr_length (trial) != 1)
1158 /* If %g0 is live, there are lots of things we can't handle.
1159 Rather than trying to find them all now, let's punt and only
1160 optimize things as necessary. */
1164 /* In the case of a true leaf function, anything can go into the delay slot.
1165 A delay slot only exists however if the frame size is zero, otherwise
1166 we will put an insn to adjust the stack after the return. */
1169 if (leaf_return_peephole_ok ())
1170 return ((get_attr_in_uncond_branch_delay (trial)
1171 == IN_BRANCH_DELAY_TRUE));
1175 /* If only trivial `restore' insns work, nothing can go in the
1177 else if (TARGET_BROKEN_SAVERESTORE)
1180 pat = PATTERN (trial);
1182 /* Otherwise, only operations which can be done in tandem with
1183 a `restore' insn can go into the delay slot. */
1184 if (GET_CODE (SET_DEST (pat)) != REG
1185 || REGNO (SET_DEST (pat)) >= 32
1186 || REGNO (SET_DEST (pat)) < 24)
1189 /* The set of insns matched here must agree precisely with the set of
1190 patterns paired with a RETURN in sparc.md. */
1192 src = SET_SRC (pat);
1194 /* This matches "*return_[qhs]". */
1195 if (arith_operand (src, GET_MODE (src)))
1196 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
1198 /* This matches "*return_di". */
1199 else if (arith_double_operand (src, GET_MODE (src)))
1200 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
1202 /* This matches "*return_sf_no_fpu". */
1203 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
1204 && register_operand (src, SFmode))
1207 /* This matches "*return_addsi". */
1208 else if (GET_CODE (src) == PLUS
1209 && arith_operand (XEXP (src, 0), SImode)
1210 && arith_operand (XEXP (src, 1), SImode)
1211 && (register_operand (XEXP (src, 0), SImode)
1212 || register_operand (XEXP (src, 1), SImode)))
1215 /* This matches "*return_adddi". */
1216 else if (GET_CODE (src) == PLUS
1217 && arith_double_operand (XEXP (src, 0), DImode)
1218 && arith_double_operand (XEXP (src, 1), DImode)
1219 && (register_operand (XEXP (src, 0), DImode)
1220 || register_operand (XEXP (src, 1), DImode)))
1223 /* This matches "*return_subsi". */
1224 else if (GET_CODE (src) == MINUS
1225 && register_operand (XEXP (src, 0), SImode)
1226 && small_int (XEXP (src, 1), VOIDmode)
1227 && INTVAL (XEXP (src, 1)) != -4096)
1234 short_branch (uid1, uid2)
1237 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
1238 if (delta + 1024 < 2048)
1240 /* warning ("long branch, distance %d", delta); */
1244 /* Return non-zero if REG is not used after INSN.
1245 We assume REG is a reload reg, and therefore does
1246 not live past labels or calls or jumps. */
1248 reg_unused_after (reg, insn)
1252 enum rtx_code code, prev_code = UNKNOWN;
1254 while (insn = NEXT_INSN (insn))
1256 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
1259 code = GET_CODE (insn);
1260 if (GET_CODE (insn) == CODE_LABEL)
1263 if (GET_RTX_CLASS (code) == 'i')
1265 rtx set = single_set (insn);
1266 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
1269 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1271 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
1279 /* The rtx for the global offset table which is a special form
1280 that *is* a position independent symbolic constant. */
1281 static rtx pic_pc_rtx;
1283 /* Ensure that we are not using patterns that are not OK with PIC. */
1292 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
1293 || (GET_CODE (recog_operand[i]) == CONST
1294 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
1302 /* Return true if X is an address which needs a temporary register when
1303 reloaded while generating PIC code. */
1306 pic_address_needs_scratch (x)
1309 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1310 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1311 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1312 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1313 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1319 /* Legitimize PIC addresses. If the address is already position-independent,
1320 we return ORIG. Newly generated position-independent addresses go into a
1321 reg. This is REG if non zero, otherwise we allocate register(s) as
1325 legitimize_pic_address (orig, mode, reg)
1327 enum machine_mode mode;
1330 if (GET_CODE (orig) == SYMBOL_REF)
1332 rtx pic_ref, address;
1337 if (reload_in_progress || reload_completed)
1340 reg = gen_reg_rtx (Pmode);
1345 /* If not during reload, allocate another temp reg here for loading
1346 in the address, so that these instructions can be optimized
1348 rtx temp_reg = ((reload_in_progress || reload_completed)
1349 ? reg : gen_reg_rtx (Pmode));
1351 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1352 won't get confused into thinking that these two instructions
1353 are loading in the true address of the symbol. If in the
1354 future a PIC rtx exists, that should be used instead. */
1355 emit_insn (gen_pic_sethi_si (temp_reg, orig));
1356 emit_insn (gen_pic_lo_sum_si (temp_reg, temp_reg, orig));
1363 pic_ref = gen_rtx (MEM, Pmode,
1364 gen_rtx (PLUS, Pmode,
1365 pic_offset_table_rtx, address));
1366 current_function_uses_pic_offset_table = 1;
1367 RTX_UNCHANGING_P (pic_ref) = 1;
1368 insn = emit_move_insn (reg, pic_ref);
1369 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1371 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1375 else if (GET_CODE (orig) == CONST)
1379 if (GET_CODE (XEXP (orig, 0)) == PLUS
1380 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1385 if (reload_in_progress || reload_completed)
1388 reg = gen_reg_rtx (Pmode);
1391 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1393 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1394 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1395 base == reg ? 0 : reg);
1400 if (GET_CODE (offset) == CONST_INT)
1402 if (SMALL_INT (offset))
1403 return plus_constant_for_output (base, INTVAL (offset));
1404 else if (! reload_in_progress && ! reload_completed)
1405 offset = force_reg (Pmode, offset);
1407 /* If we reach here, then something is seriously wrong. */
1410 return gen_rtx (PLUS, Pmode, base, offset);
1412 else if (GET_CODE (orig) == LABEL_REF)
1413 /* ??? Why do we do this? */
1414 current_function_uses_pic_offset_table = 1;
1419 /* Set up PIC-specific rtl. This should not cause any insns
1427 /* Emit special PIC prologues and epilogues. */
1432 /* The table we use to reference PIC data. */
1433 rtx global_offset_table;
1434 /* Labels to get the PC in the prologue of this function. */
1437 int orig_flag_pic = flag_pic;
1439 if (current_function_uses_pic_offset_table == 0)
1449 l1 = gen_label_rtx ();
1451 /* Initialize every time through, since we can't easily
1452 know this to be permanent. */
1453 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1454 pic_pc_rtx = gen_rtx (CONST, Pmode,
1455 gen_rtx (MINUS, Pmode,
1456 global_offset_table,
1457 gen_rtx (CONST, Pmode,
1458 gen_rtx (MINUS, Pmode,
1459 gen_rtx (LABEL_REF, VOIDmode, l1),
1462 /* sparc64: the RDPC instruction doesn't pair, and puts 4 bubbles in the
1463 pipe to boot. So don't use it here, especially when we're
1464 doing a save anyway because of %l7. */
1466 l2 = gen_label_rtx ();
1469 /* Iff we are doing delay branch optimization, slot the sethi up
1470 here so that it will fill the delay slot of the call. */
1471 if (flag_delayed_branch)
1472 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1473 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1475 /* Note that we pun calls and jumps here! */
1476 emit_jump_insn (gen_get_pc_via_call (l2, l1));
1480 if (!flag_delayed_branch)
1481 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1482 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1484 emit_insn (gen_rtx (SET, VOIDmode,
1485 pic_offset_table_rtx,
1486 gen_rtx (LO_SUM, Pmode,
1487 pic_offset_table_rtx, pic_pc_rtx)));
1488 emit_insn (gen_rtx (SET, VOIDmode,
1489 pic_offset_table_rtx,
1490 gen_rtx (PLUS, Pmode,
1491 pic_offset_table_rtx,
1492 gen_rtx (REG, Pmode, 15))));
1494 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1495 LABEL_PRESERVE_P (l1) = 1;
1496 LABEL_PRESERVE_P (l2) = 1;
1498 flag_pic = orig_flag_pic;
1500 seq = gen_sequence ();
1502 emit_insn_after (seq, get_insns ());
1504 /* Need to emit this whether or not we obey regdecls,
1505 since setjmp/longjmp can cause life info to screw up. */
1506 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1509 /* Emit insns to move operands[1] into operands[0].
1511 Return 1 if we have written out everything that needs to be done to
1512 do the move. Otherwise, return 0 and the caller will emit the move
1516 emit_move_sequence (operands, mode)
1518 enum machine_mode mode;
1520 register rtx operand0 = operands[0];
1521 register rtx operand1 = operands[1];
1523 if (CONSTANT_P (operand1) && flag_pic
1524 && pic_address_needs_scratch (operand1))
1525 operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0);
1527 /* Handle most common case first: storing into a register. */
1528 if (register_operand (operand0, mode))
1530 if (register_operand (operand1, mode)
1531 || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
1532 || (GET_CODE (operand1) == CONST_DOUBLE
1533 && arith_double_operand (operand1, DImode))
1534 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode)
1535 /* Only `general_operands' can come here, so MEM is ok. */
1536 || GET_CODE (operand1) == MEM)
1538 /* Run this case quickly. */
1539 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1543 else if (GET_CODE (operand0) == MEM)
1545 if (register_operand (operand1, mode)
1546 || (operand1 == const0_rtx && ! TARGET_LIVE_G0))
1548 /* Run this case quickly. */
1549 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1552 if (! reload_in_progress)
1554 operands[0] = validize_mem (operand0);
1555 operands[1] = operand1 = force_reg (mode, operand1);
1559 if (GET_CODE (operand1) == LABEL_REF
1560 && mode == SImode && flag_pic)
1564 emit_insn (gen_move_pic_label_si (operand0, operand1));
1567 /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way,
1568 so always use special code. */
1569 else if (GET_CODE (operand1) == LABEL_REF
1572 if (! TARGET_ARCH64)
1574 emit_insn (gen_move_label_di (operand0, operand1));
1577 /* DImode HIGH values in sparc64 need a clobber added. */
1578 else if (TARGET_ARCH64
1579 && GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)
1581 emit_insn (gen_sethi_di_sp64 (operand0, XEXP (operand1, 0)));
1584 /* Simplify the source if we need to. */
1585 else if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1587 if (flag_pic && symbolic_operand (operand1, mode))
1589 rtx temp_reg = reload_in_progress ? operand0 : 0;
1591 operands[1] = legitimize_pic_address (operand1, mode, temp_reg);
1593 else if (GET_CODE (operand1) == CONST_INT
1594 ? (! SMALL_INT (operand1)
1595 && ! SPARC_SETHI_P (INTVAL (operand1)))
1596 : GET_CODE (operand1) == CONST_DOUBLE
1597 ? ! arith_double_operand (operand1, DImode)
1600 /* For DImode values, temp must be operand0 because of the way
1601 HI and LO_SUM work. The LO_SUM operator only copies half of
1602 the LSW from the dest of the HI operator. If the LO_SUM dest is
1603 not the same as the HI dest, then the MSW of the LO_SUM dest will
1606 ??? The real problem here is that the ...(HI:DImode pattern emits
1607 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1608 one instruction. This fails, because the compiler assumes that
1609 LO_SUM copies all bits of the first operand to its dest. Better
1610 would be to have the HI pattern emit one instruction and the
1611 LO_SUM pattern multiple instructions. Even better would be
1612 to use four rtl insns. */
1613 rtx temp = ((reload_in_progress || mode == DImode)
1614 ? operand0 : gen_reg_rtx (mode));
1616 if (TARGET_ARCH64 && mode == DImode)
1617 emit_insn (gen_sethi_di_sp64 (temp, operand1));
1619 emit_insn (gen_rtx (SET, VOIDmode, temp,
1620 gen_rtx (HIGH, mode, operand1)));
1622 if (GET_CODE (operand1) == CONST_INT)
1623 operand1 = GEN_INT (INTVAL (operand1) & 0xffffffff);
1624 else if (GET_CODE (operand1) == CONST_DOUBLE)
1625 operand1 = GEN_INT (CONST_DOUBLE_LOW (operand1) & 0xffffffff);
1626 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
1630 /* Now have insn-emit do whatever it normally does. */
1634 /* Return the best assembler insn template
1635 for moving operands[1] into operands[0] as a 4 byte quantity.
1637 This isn't intended to be very smart. It is up to the caller to
1638 choose the best way to do things.
1640 Note that OPERANDS may be modified to suit the returned string. */
1643 singlemove_string (operands)
1646 if (GET_CODE (operands[0]) == MEM)
1648 if (GET_CODE (operands[1]) != MEM)
1653 else if (GET_CODE (operands[1]) == MEM)
1655 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1660 /* Must be SFmode, otherwise this doesn't make sense. */
1661 if (GET_MODE (operands[1]) != SFmode)
1664 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1665 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1666 operands[1] = GEN_INT (i);
1668 if (CONST_OK_FOR_LETTER_P (i, 'I'))
1670 else if ((i & 0x000003FF) != 0)
1671 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1673 return "sethi %%hi(%a1),%0";
1675 else if (GET_CODE (operands[1]) == CONST_INT
1676 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
1678 HOST_WIDE_INT i = INTVAL (operands[1]);
1680 /* If all low order 10 bits are clear, then we only need a single
1681 sethi insn to load the constant. */
1682 /* FIXME: Use SETHI_P. */
1683 if ((i & 0x000003FF) != 0)
1684 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1686 return "sethi %%hi(%a1),%0";
1688 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1692 /* Return the best assembler insn template
1693 for moving operands[1] into operands[0] as an 8 byte quantity.
1695 This isn't intended to be very smart. It is up to the caller to
1696 choose the best way to do things.
1698 Note that OPERANDS may be modified to suit the returned string. */
1701 doublemove_string (operands)
1704 rtx op0 = operands[0], op1 = operands[1];
1706 if (GET_CODE (op0) == MEM)
1708 if (GET_CODE (op1) == REG)
1712 return TARGET_ARCH64 ? "stx %1,%0" : "std %1,%0";
1715 && (op1 == const0_rtx
1716 || (GET_MODE (op1) != VOIDmode
1717 && op1 == CONST0_RTX (GET_MODE (op1)))))
1718 return "stx %r1,%0";
1721 else if (GET_CODE (op1) == MEM)
1723 if (GET_CODE (op0) != REG)
1727 return TARGET_ARCH64 ? "ldx %1,%0" : "ldd %1,%0";
1729 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1731 /* ??? Unfinished, and maybe not needed. */
1734 else if (GET_CODE (operands[1]) == CONST_INT
1735 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
1737 /* ??? Unfinished, and maybe not needed. */
1740 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1744 /* Return non-zero if it is OK to assume that the given memory operand is
1745 aligned at least to a 8-byte boundary. This should only be called
1746 for memory accesses whose size is 8 bytes or larger. */
1754 register rtx offset;
1756 if (GET_CODE (mem) != MEM)
1757 return 0; /* It's gotta be a MEM! */
1759 addr = XEXP (mem, 0);
1761 /* Now that all misaligned double parms are copied on function entry,
1762 we can assume any 64-bit object is 64-bit aligned except those which
1763 are at unaligned offsets from the stack or frame pointer. If the
1764 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1767 /* See what register we use in the address. */
1769 if (GET_CODE (addr) == PLUS)
1771 if (GET_CODE (XEXP (addr, 0)) == REG
1772 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
1774 base = XEXP (addr, 0);
1775 offset = XEXP (addr, 1);
1778 else if (GET_CODE (addr) == REG)
1781 offset = const0_rtx;
1784 /* If it's the stack or frame pointer, check offset alignment.
1785 We can have improper alignment in the function entry code. */
1787 && (REGNO (base) == FRAME_POINTER_REGNUM
1788 || REGNO (base) == STACK_POINTER_REGNUM))
1790 if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0)
1793 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1794 is true, in which case we can only assume that an access is aligned if
1795 it is to a constant address, or the address involves a LO_SUM.
1797 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1798 That assumption was deleted so that gcc generated code can be used with
1799 memory allocators that only guarantee 4 byte alignment. */
1800 else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr)
1801 || GET_CODE (addr) == LO_SUM)
1804 /* An obviously unaligned address. */
1808 enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP };
1810 /* Output assembler code to perform a doubleword move insn
1811 with operands OPERANDS. This is very similar to the following
1812 output_move_quad function. */
1815 output_move_double (operands)
1818 register rtx op0 = operands[0];
1819 register rtx op1 = operands[1];
1820 register enum optype optype0;
1821 register enum optype optype1;
1825 int highest_first = 0;
1826 int no_addreg1_decrement = 0;
1828 /* First classify both operands. */
1832 else if (offsettable_memref_p (op0))
1834 else if (GET_CODE (op0) == MEM)
1841 else if (CONSTANT_P (op1))
1843 else if (offsettable_memref_p (op1))
1845 else if (GET_CODE (op1) == MEM)
1850 /* Check for the cases that the operand constraints are not
1851 supposed to allow to happen. Abort if we get one,
1852 because generating code for these cases is painful. */
1854 if (optype0 == RNDOP || optype1 == RNDOP
1855 || (optype0 == MEM && optype1 == MEM))
1858 /* If an operand is an unoffsettable memory ref, find a register
1859 we can increment temporarily to make it refer to the second word. */
1861 if (optype0 == MEMOP)
1862 addreg0 = find_addr_reg (XEXP (op0, 0));
1864 if (optype1 == MEMOP)
1865 addreg1 = find_addr_reg (XEXP (op1, 0));
1867 /* Ok, we can do one word at a time.
1868 Set up in LATEHALF the operands to use for the
1869 high-numbered (least significant) word and in some cases alter the
1870 operands in OPERANDS to be suitable for the low-numbered word. */
1872 if (optype0 == REGOP)
1873 latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1874 else if (optype0 == OFFSOP)
1875 latehalf[0] = adj_offsettable_operand (op0, 4);
1879 if (optype1 == REGOP)
1880 latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1881 else if (optype1 == OFFSOP)
1882 latehalf[1] = adj_offsettable_operand (op1, 4);
1883 else if (optype1 == CNSTOP)
1887 if (arith_double_operand (op1, DImode))
1889 operands[1] = gen_rtx (CONST_INT, VOIDmode,
1890 CONST_DOUBLE_LOW (op1));
1895 /* The only way to handle CONST_DOUBLEs or other 64 bit
1896 constants here is to use a temporary, such as is done
1897 for the V9 DImode sethi insn pattern. This is not
1898 a practical solution, so abort if we reach here.
1899 The md file should always force such constants to
1905 split_double (op1, &operands[1], &latehalf[1]);
1910 /* Easy case: try moving both words at once. Check for moving between
1911 an even/odd register pair and a memory location. */
1912 if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP
1913 && (TARGET_ARCH64 || (REGNO (op0) & 1) == 0))
1914 || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP
1915 && (TARGET_ARCH64 || (REGNO (op1) & 1) == 0)))
1917 register rtx mem,reg;
1919 if (optype0 == REGOP)
1920 mem = op1, reg = op0;
1922 mem = op0, reg = op1;
1924 /* In v9, ldd can be used for word aligned addresses, so technically
1925 some of this logic is unneeded. We still avoid ldd if the address
1926 is obviously unaligned though. */
1928 if (mem_aligned_8 (mem)
1929 /* If this is a floating point register higher than %f31,
1930 then we *must* use an aligned load, since `ld' will not accept
1931 the register number. */
1932 || (TARGET_V9 && REGNO (reg) >= 64))
1934 if (FP_REG_P (reg) || ! TARGET_ARCH64)
1935 return (mem == op1 ? "ldd %1,%0" : "std %1,%0");
1937 return (mem == op1 ? "ldx %1,%0" : "stx %1,%0");
1943 if (optype0 == REGOP && optype1 == REGOP)
1946 return "fmovd %1,%0";
1952 /* If the first move would clobber the source of the second one,
1953 do them in the other order. */
1955 /* Overlapping registers. */
1956 if (optype0 == REGOP && optype1 == REGOP
1957 && REGNO (op0) == REGNO (latehalf[1]))
1960 output_asm_insn (singlemove_string (latehalf), latehalf);
1961 /* Do low-numbered word. */
1962 return singlemove_string (operands);
1964 /* Loading into a register which overlaps a register used in the address. */
1965 else if (optype0 == REGOP && optype1 != REGOP
1966 && reg_overlap_mentioned_p (op0, op1))
1968 /* If both halves of dest are used in the src memory address,
1969 add the two regs and put them in the low reg (op0).
1970 Then it works to load latehalf first. */
1971 if (reg_mentioned_p (op0, XEXP (op1, 0))
1972 && reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1975 xops[0] = latehalf[0];
1977 output_asm_insn ("add %1,%0,%1", xops);
1978 operands[1] = gen_rtx (MEM, DImode, op0);
1979 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1983 /* Only one register in the dest is used in the src memory address,
1984 and this is the first register of the dest, so we want to do
1985 the late half first here also. */
1986 else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1988 /* Only one register in the dest is used in the src memory address,
1989 and this is the second register of the dest, so we want to do
1990 the late half last. If addreg1 is set, and addreg1 is the same
1991 register as latehalf, then we must suppress the trailing decrement,
1992 because it would clobber the value just loaded. */
1993 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
1994 no_addreg1_decrement = 1;
1997 /* Normal case: do the two words, low-numbered first.
1998 Overlap case (highest_first set): do high-numbered word first. */
2000 if (! highest_first)
2001 output_asm_insn (singlemove_string (operands), operands);
2003 /* Make any unoffsettable addresses point at high-numbered word. */
2005 output_asm_insn ("add %0,0x4,%0", &addreg0);
2007 output_asm_insn ("add %0,0x4,%0", &addreg1);
2010 output_asm_insn (singlemove_string (latehalf), latehalf);
2012 /* Undo the adds we just did. */
2014 output_asm_insn ("add %0,-0x4,%0", &addreg0);
2015 if (addreg1 && ! no_addreg1_decrement)
2016 output_asm_insn ("add %0,-0x4,%0", &addreg1);
2019 output_asm_insn (singlemove_string (operands), operands);
2024 /* Output assembler code to perform a quadword move insn
2025 with operands OPERANDS. This is very similar to the preceding
2026 output_move_double function. */
2029 output_move_quad (operands)
2032 register rtx op0 = operands[0];
2033 register rtx op1 = operands[1];
2034 register enum optype optype0;
2035 register enum optype optype1;
2040 /* First classify both operands. */
2044 else if (offsettable_memref_p (op0))
2046 else if (GET_CODE (op0) == MEM)
2053 else if (CONSTANT_P (op1))
2055 else if (offsettable_memref_p (op1))
2057 else if (GET_CODE (op1) == MEM)
2062 /* Check for the cases that the operand constraints are not
2063 supposed to allow to happen. Abort if we get one,
2064 because generating code for these cases is painful. */
2066 if (optype0 == RNDOP || optype1 == RNDOP
2067 || (optype0 == MEM && optype1 == MEM))
2070 /* If an operand is an unoffsettable memory ref, find a register
2071 we can increment temporarily to make it refer to the later words. */
2073 if (optype0 == MEMOP)
2074 addreg0 = find_addr_reg (XEXP (op0, 0));
2076 if (optype1 == MEMOP)
2077 addreg1 = find_addr_reg (XEXP (op1, 0));
2079 /* Ok, we can do one word at a time.
2080 Set up in wordpart the operands to use for each word of the arguments. */
2082 if (optype0 == REGOP)
2084 wordpart[0][0] = gen_rtx (REG, word_mode, REGNO (op0) + 0);
2085 wordpart[1][0] = gen_rtx (REG, word_mode, REGNO (op0) + 1);
2088 wordpart[2][0] = gen_rtx (REG, word_mode, REGNO (op0) + 2);
2089 wordpart[3][0] = gen_rtx (REG, word_mode, REGNO (op0) + 3);
2092 else if (optype0 == OFFSOP)
2094 wordpart[0][0] = adj_offsettable_operand (op0, 0);
2097 wordpart[1][0] = adj_offsettable_operand (op0, 4);
2098 wordpart[2][0] = adj_offsettable_operand (op0, 8);
2099 wordpart[3][0] = adj_offsettable_operand (op0, 12);
2102 wordpart[1][0] = adj_offsettable_operand (op0, 8);
2106 wordpart[0][0] = op0;
2107 wordpart[1][0] = op0;
2108 wordpart[2][0] = op0;
2109 wordpart[3][0] = op0;
2112 if (optype1 == REGOP)
2114 wordpart[0][1] = gen_rtx (REG, word_mode, REGNO (op1) + 0);
2115 wordpart[1][1] = gen_rtx (REG, word_mode, REGNO (op1) + 1);
2118 wordpart[2][1] = gen_rtx (REG, word_mode, REGNO (op1) + 2);
2119 wordpart[3][1] = gen_rtx (REG, word_mode, REGNO (op1) + 3);
2122 else if (optype1 == OFFSOP)
2124 wordpart[0][1] = adj_offsettable_operand (op1, 0);
2127 wordpart[1][1] = adj_offsettable_operand (op1, 4);
2128 wordpart[2][1] = adj_offsettable_operand (op1, 8);
2129 wordpart[3][1] = adj_offsettable_operand (op1, 12);
2132 wordpart[1][1] = adj_offsettable_operand (op1, 8);
2134 else if (optype1 == CNSTOP)
2139 /* This only works for TFmode floating point constants. */
2140 if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode)
2143 REAL_VALUE_FROM_CONST_DOUBLE (r, op1);
2144 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2146 wordpart[0][1] = GEN_INT (l[0]);
2147 wordpart[1][1] = GEN_INT (l[1]);
2148 wordpart[2][1] = GEN_INT (l[2]);
2149 wordpart[3][1] = GEN_INT (l[3]);
2153 wordpart[0][1] = op1;
2154 wordpart[1][1] = op1;
2155 wordpart[2][1] = op1;
2156 wordpart[3][1] = op1;
2159 /* Easy case: try moving the quad as two pairs. Check for moving between
2160 an even/odd register pair and a memory location.
2161 Also handle new v9 fp regs here. */
2162 /* ??? Should also handle the case of non-offsettable addresses here.
2163 We can at least do the first pair as a ldd/std, and then do the third
2164 and fourth words individually. */
2165 if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0)
2166 || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0))
2170 if (optype0 == REGOP)
2171 mem = op1, reg = op0;
2173 mem = op0, reg = op1;
2175 if (mem_aligned_8 (mem)
2176 /* If this is a floating point register higher than %f31,
2177 then we *must* use an aligned load, since `ld' will not accept
2178 the register number. */
2179 || (TARGET_V9 && REGNO (reg) >= SPARC_FIRST_V9_FP_REG))
2181 if (TARGET_V9 && FP_REG_P (reg) && TARGET_HARD_QUAD)
2183 if ((REGNO (reg) & 3) != 0)
2185 /* ??? Can `mem' have an inappropriate alignment here? */
2186 return (mem == op1 ? "ldq %1,%0" : "stq %1,%0");
2188 operands[2] = adj_offsettable_operand (mem, 8);
2189 /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */
2191 return TARGET_ARCH64 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
2193 return TARGET_ARCH64 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
2197 /* If the first move would clobber the source of the second one,
2198 do them in the other order. */
2200 /* Overlapping registers? */
2203 if (optype0 == REGOP && optype1 == REGOP
2204 && (REGNO (op0) == REGNO (wordpart[1][3])
2205 || REGNO (op0) == REGNO (wordpart[1][2])
2206 || REGNO (op0) == REGNO (wordpart[1][1])))
2208 /* Do fourth word. */
2209 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2210 /* Do the third word. */
2211 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2212 /* Do the second word. */
2213 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2214 /* Do lowest-numbered word. */
2215 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
2219 else /* TARGET_ARCH64 */
2221 if (optype0 == REGOP && optype1 == REGOP
2222 && REGNO (op0) == REGNO (wordpart[1][1]))
2224 output_asm_insn ("mov %1,%0", wordpart[1]);
2225 output_asm_insn ("mov %1,%0", wordpart[0]);
2230 /* Loading into a register which overlaps a register used in the address. */
2231 if (optype0 == REGOP && optype1 != REGOP
2232 && reg_overlap_mentioned_p (op0, op1))
2234 /* ??? Not implemented yet. This is a bit complicated, because we
2235 must load which ever part overlaps the address last. If the address
2236 is a double-reg address, then there are two parts which need to
2237 be done last, which is impossible. We would need a scratch register
2242 /* Normal case: move the words in lowest to highest address order. */
2246 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
2248 /* Make any unoffsettable addresses point at the second word. */
2250 output_asm_insn ("add %0,0x4,%0", &addreg0);
2252 output_asm_insn ("add %0,0x4,%0", &addreg1);
2254 /* Do the second word. */
2255 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2257 /* Make any unoffsettable addresses point at the third word. */
2259 output_asm_insn ("add %0,0x4,%0", &addreg0);
2261 output_asm_insn ("add %0,0x4,%0", &addreg1);
2263 /* Do the third word. */
2264 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2266 /* Make any unoffsettable addresses point at the fourth word. */
2268 output_asm_insn ("add %0,0x4,%0", &addreg0);
2270 output_asm_insn ("add %0,0x4,%0", &addreg1);
2272 /* Do the fourth word. */
2273 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2275 /* Undo the adds we just did. */
2277 output_asm_insn ("add %0,-0xc,%0", &addreg0);
2279 output_asm_insn ("add %0,-0xc,%0", &addreg1);
2281 else /* TARGET_ARCH64 */
2283 output_asm_insn (doublemove_string (wordpart[0]), wordpart[0]);
2285 /* Make any unoffsettable addresses point at the second word. */
2287 output_asm_insn ("add %0,0x8,%0", &addreg0);
2289 output_asm_insn ("add %0,0x8,%0", &addreg1);
2291 /* Do the second word. */
2292 output_asm_insn (doublemove_string (wordpart[1]), wordpart[1]);
2294 /* Undo the adds we just did. */
2296 output_asm_insn ("add %0,-0x8,%0", &addreg0);
2298 output_asm_insn ("add %0,-0x8,%0", &addreg1);
2304 /* Output assembler code to perform a doubleword move insn with operands
2305 OPERANDS, one of which must be a floating point register. */
2308 output_fp_move_double (operands)
2311 if (FP_REG_P (operands[0]))
2313 if (FP_REG_P (operands[1]))
2316 return "fmovd %1,%0";
2318 return "fmovs %1,%0\n\tfmovs %R1,%R0";
2320 else if (GET_CODE (operands[1]) == REG)
2323 return output_move_double (operands);
2325 else if (FP_REG_P (operands[1]))
2327 if (GET_CODE (operands[0]) == REG)
2330 return output_move_double (operands);
2335 /* Output assembler code to perform a quadword move insn with operands
2336 OPERANDS, one of which must be a floating point register. */
2339 output_fp_move_quad (operands)
2342 register rtx op0 = operands[0];
2343 register rtx op1 = operands[1];
2349 if (TARGET_V9 && TARGET_HARD_QUAD)
2350 return "fmovq %1,%0";
2352 return "fmovd %1,%0\n\tfmovd %S1,%S0";
2354 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2356 else if (GET_CODE (op1) == REG)
2359 return output_move_quad (operands);
2361 else if (FP_REG_P (op1))
2363 if (GET_CODE (op0) == REG)
2366 return output_move_quad (operands);
2372 /* Return a REG that occurs in ADDR with coefficient 1.
2373 ADDR can be effectively incremented by incrementing REG. */
2376 find_addr_reg (addr)
2379 while (GET_CODE (addr) == PLUS)
2381 /* We absolutely can not fudge the frame pointer here, because the
2382 frame pointer must always be 8 byte aligned. It also confuses
2384 if (GET_CODE (XEXP (addr, 0)) == REG
2385 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
2386 addr = XEXP (addr, 0);
2387 else if (GET_CODE (XEXP (addr, 1)) == REG
2388 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
2389 addr = XEXP (addr, 1);
2390 else if (CONSTANT_P (XEXP (addr, 0)))
2391 addr = XEXP (addr, 1);
2392 else if (CONSTANT_P (XEXP (addr, 1)))
2393 addr = XEXP (addr, 0);
2397 if (GET_CODE (addr) == REG)
2402 #if 0 /* not currently used */
2405 output_sized_memop (opname, mode, signedp)
2407 enum machine_mode mode;
2410 static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" };
2411 static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" };
2412 static char *st_size_suffix[] = { "b", "h", "", "?", "d" };
2413 char **opnametab, *modename;
2415 if (opname[0] == 'l')
2417 opnametab = ld_size_suffix_s;
2419 opnametab = ld_size_suffix_u;
2421 opnametab = st_size_suffix;
2422 modename = opnametab[GET_MODE_SIZE (mode) >> 1];
2424 fprintf (asm_out_file, "\t%s%s", opname, modename);
2428 output_move_with_extension (operands)
2431 if (GET_MODE (operands[2]) == HImode)
2432 output_asm_insn ("sll %2,0x10,%0", operands);
2433 else if (GET_MODE (operands[2]) == QImode)
2434 output_asm_insn ("sll %2,0x18,%0", operands);
2438 #endif /* not currently used */
2441 /* ??? These are only used by the movstrsi pattern, but we get better code
2442 in general without that, because emit_block_move can do just as good a
2443 job as this function does when alignment and size are known. When they
2444 aren't known, a call to strcpy may be faster anyways, because it is
2445 likely to be carefully crafted assembly language code, and below we just
2446 do a byte-wise copy.
2448 Also, emit_block_move expands into multiple read/write RTL insns, which
2449 can then be optimized, whereas our movstrsi pattern can not be optimized
2452 /* Load the address specified by OPERANDS[3] into the register
2453 specified by OPERANDS[0].
2455 OPERANDS[3] may be the result of a sum, hence it could either be:
2460 (3) REG + REG + CONST_INT
2461 (4) REG + REG (special case of 3).
2463 Note that (3) is not a legitimate address.
2464 All cases are handled here. */
2467 output_load_address (operands)
2472 if (CONSTANT_P (operands[3]))
2474 output_asm_insn ("set %3,%0", operands);
2478 if (REG_P (operands[3]))
2480 if (REGNO (operands[0]) != REGNO (operands[3]))
2481 output_asm_insn ("mov %3,%0", operands);
2485 if (GET_CODE (operands[3]) != PLUS)
2488 base = XEXP (operands[3], 0);
2489 offset = XEXP (operands[3], 1);
2491 if (GET_CODE (base) == CONST_INT)
2498 if (GET_CODE (offset) != CONST_INT)
2500 /* Operand is (PLUS (REG) (REG)). */
2502 offset = const0_rtx;
2508 operands[7] = offset;
2509 if (SMALL_INT (offset))
2510 output_asm_insn ("add %6,%7,%0", operands);
2512 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands);
2514 else if (GET_CODE (base) == PLUS)
2516 operands[6] = XEXP (base, 0);
2517 operands[7] = XEXP (base, 1);
2518 operands[8] = offset;
2520 if (SMALL_INT (offset))
2521 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands);
2523 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands);
2529 /* Output code to place a size count SIZE in register REG.
2530 ALIGN is the size of the unit of transfer.
2532 Because block moves are pipelined, we don't include the
2533 first element in the transfer of SIZE to REG. */
2536 output_size_for_block_move (size, reg, align)
2543 xoperands[1] = size;
2544 xoperands[2] = align;
2545 if (GET_CODE (size) == REG)
2546 output_asm_insn ("sub %1,%2,%0", xoperands);
2550 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
2551 output_asm_insn ("set %1,%0", xoperands);
2555 /* Emit code to perform a block move.
2557 OPERANDS[0] is the destination.
2558 OPERANDS[1] is the source.
2559 OPERANDS[2] is the size.
2560 OPERANDS[3] is the alignment safe to use.
2561 OPERANDS[4] is a register we can safely clobber as a temp. */
2564 output_block_move (operands)
2567 /* A vector for our computed operands. Note that load_output_address
2568 makes use of (and can clobber) up to the 8th element of this vector. */
2571 static int movstrsi_label = 0;
2573 rtx temp1 = operands[4];
2574 rtx sizertx = operands[2];
2575 rtx alignrtx = operands[3];
2576 int align = INTVAL (alignrtx);
2577 char label3[30], label5[30];
2579 xoperands[0] = operands[0];
2580 xoperands[1] = operands[1];
2581 xoperands[2] = temp1;
2583 /* We can't move more than this many bytes at a time because we have only
2584 one register, %g1, to move them through. */
2585 if (align > UNITS_PER_WORD)
2587 align = UNITS_PER_WORD;
2588 alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD);
2591 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2592 reasonable here. (Actually will emit a maximum of 18 inline insns for
2593 the case of size == 31 and align == 4). */
2595 if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8
2596 && memory_address_p (QImode, plus_constant_for_output (xoperands[0],
2598 && memory_address_p (QImode, plus_constant_for_output (xoperands[1],
2601 int size = INTVAL (sizertx);
2604 /* We will store different integers into this particular RTX. */
2605 xoperands[2] = rtx_alloc (CONST_INT);
2606 PUT_MODE (xoperands[2], VOIDmode);
2608 /* This case is currently not handled. Abort instead of generating
2610 if (align > UNITS_PER_WORD)
2613 if (TARGET_ARCH64 && align >= 8)
2615 for (i = (size >> 3) - 1; i >= 0; i--)
2617 INTVAL (xoperands[2]) = (i << 3) + offset;
2618 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2621 offset += (size & ~0x7);
2629 for (i = (size >> 2) - 1; i >= 0; i--)
2631 INTVAL (xoperands[2]) = (i << 2) + offset;
2632 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2635 offset += (size & ~0x3);
2643 for (i = (size >> 1) - 1; i >= 0; i--)
2645 INTVAL (xoperands[2]) = (i << 1) + offset;
2646 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2649 offset += (size & ~0x1);
2657 for (i = size - 1; i >= 0; i--)
2659 INTVAL (xoperands[2]) = i + offset;
2660 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2666 /* We should never reach here. */
2670 /* If the size isn't known to be a multiple of the alignment,
2671 we have to do it in smaller pieces. If we could determine that
2672 the size was a multiple of 2 (or whatever), we could be smarter
2674 if (GET_CODE (sizertx) != CONST_INT)
2678 int size = INTVAL (sizertx);
2679 while (size % align)
2683 if (align != INTVAL (alignrtx))
2684 alignrtx = gen_rtx (CONST_INT, VOIDmode, align);
2686 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2687 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align);
2688 xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2690 ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3]));
2691 ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5]));
2693 /* This is the size of the transfer. Emit code to decrement the size
2694 value by ALIGN, and store the result in the temp1 register. */
2695 output_size_for_block_move (sizertx, temp1, alignrtx);
2697 /* Must handle the case when the size is zero or negative, so the first thing
2698 we do is compare the size against zero, and only copy bytes if it is
2699 zero or greater. Note that we have already subtracted off the alignment
2700 once, so we must copy 1 alignment worth of bytes if the size is zero
2703 The SUN assembler complains about labels in branch delay slots, so we
2704 do this before outputting the load address, so that there will always
2705 be a harmless insn between the branch here and the next label emitted
2711 sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]);
2712 output_asm_insn (pattern, xoperands);
2715 zoperands[0] = operands[0];
2716 zoperands[3] = plus_constant_for_output (operands[0], align);
2717 output_load_address (zoperands);
2719 /* ??? This might be much faster if the loops below were preconditioned
2722 That is, at run time, copy enough bytes one at a time to ensure that the
2723 target and source addresses are aligned to the the largest possible
2724 alignment. Then use a preconditioned unrolled loop to copy say 16
2725 bytes at a time. Then copy bytes one at a time until finish the rest. */
2727 /* Output the first label separately, so that it is spaced properly. */
2729 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3]));
2733 register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh"
2734 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2735 register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h"
2736 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2738 sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]);
2739 output_asm_insn (pattern, xoperands);
2746 /* Output reasonable peephole for set-on-condition-code insns.
2747 Note that these insns assume a particular way of defining
2748 labels. Therefore, *both* sparc.h and this function must
2749 be changed if a new syntax is needed. */
2752 output_scc_insn (operands, insn)
2756 static char string[100];
2757 rtx label = 0, next = insn;
2760 /* Try doing a jump optimization which jump.c can't do for us
2761 because we did not expose that setcc works by using branches.
2763 If this scc insn is followed by an unconditional branch, then have
2764 the jump insn emitted here jump to that location, instead of to
2765 the end of the scc sequence as usual. */
2769 if (GET_CODE (next) == CODE_LABEL)
2771 next = NEXT_INSN (next);
2775 while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL);
2777 /* If we are in a sequence, and the following insn is a sequence also,
2778 then just following the current insn's next field will take us to the
2779 first insn of the next sequence, which is the wrong place. We don't
2780 want to optimize with a branch that has had its delay slot filled.
2781 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2782 which fails only if NEXT is such a branch. */
2784 if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)
2785 && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next))
2786 label = JUMP_LABEL (next);
2787 /* If not optimizing, jump label fields are not set. To be safe, always
2788 check here to whether label is still zero. */
2791 label = gen_label_rtx ();
2795 LABEL_NUSES (label) += 1;
2797 /* operands[3] is an unused slot. */
2798 operands[3] = label;
2800 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2801 insn since our type isn't allowed anywhere else. */
2803 /* ??? Fpcc instructions no longer have delay slots, so this code is
2804 probably obsolete. */
2806 /* The fastest way to emit code for this is an annulled branch followed
2807 by two move insns. This will take two cycles if the branch is taken,
2808 and three cycles if the branch is not taken.
2810 However, if we are in the delay slot of another branch, this won't work,
2811 because we can't put a branch in the delay slot of another branch.
2812 The above sequence would effectively take 3 or 4 cycles respectively
2813 since a no op would have be inserted between the two branches.
2814 In this case, we want to emit a move, annulled branch, and then the
2815 second move. This sequence always takes 3 cycles, and hence is faster
2816 when we are in a branch delay slot. */
2820 strcpy (string, "mov 0,%0\n\t");
2821 strcat (string, output_cbranch (operands[2], 3, 0, 1, 0));
2822 strcat (string, "\n\tmov 1,%0");
2826 strcpy (string, output_cbranch (operands[2], 3, 0, 1, 0));
2827 strcat (string, "\n\tmov 1,%0\n\tmov 0,%0");
2831 strcat (string, "\n%l3:");
2836 /* Vectors to keep interesting information about registers where it can easily
2837 be got. We use to use the actual mode value as the bit number, but there
2838 are more than 32 modes now. Instead we use two tables: one indexed by
2839 hard register number, and one indexed by mode. */
2841 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2842 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2843 mapped into one sparc_mode_class mode. */
2845 enum sparc_mode_class {
2846 S_MODE, D_MODE, T_MODE, O_MODE,
2847 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2851 /* Modes for single-word and smaller quantities. */
2852 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2854 /* Modes for double-word and smaller quantities. */
2855 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2857 /* Modes for quad-word and smaller quantities. */
2858 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2860 /* Modes for single-float quantities. We must allow any single word or
2861 smaller quantity. This is because the fix/float conversion instructions
2862 take integer inputs/outputs from the float registers. */
2863 #define SF_MODES (S_MODES)
2865 /* Modes for double-float and smaller quantities. */
2866 #define DF_MODES (S_MODES | D_MODES)
2868 /* ??? Sparc64 fp regs cannot hold DImode values. */
2869 #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/)
2871 /* Modes for double-float only quantities. */
2872 /* ??? Sparc64 fp regs cannot hold DImode values.
2873 See fix_truncsfdi2. */
2874 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2876 /* Modes for double-float and larger quantities. */
2877 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2879 /* Modes for quad-float only quantities. */
2880 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2882 /* Modes for quad-float and smaller quantities. */
2883 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2885 /* ??? Sparc64 fp regs cannot hold DImode values.
2886 See fix_truncsfdi2. */
2887 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2889 /* Modes for condition codes. */
2890 #define CC_MODES (1 << (int) CC_MODE)
2891 #define CCFP_MODES (1 << (int) CCFP_MODE)
2893 /* Value is 1 if register/mode pair is acceptable on sparc.
2894 The funny mixture of D and T modes is because integer operations
2895 do not specially operate on tetra quantities, so non-quad-aligned
2896 registers can hold quadword quantities (except %o4 and %i4 because
2897 they cross fixed registers). */
2899 /* This points to either the 32 bit or the 64 bit version. */
2900 int *hard_regno_mode_classes;
2902 static int hard_32bit_mode_classes[] = {
2903 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2904 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2905 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2906 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2908 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2909 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2910 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2911 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2913 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2914 and none can hold SFmode/SImode values. */
2915 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2916 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2917 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2918 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2921 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2927 static int hard_64bit_mode_classes[] = {
2928 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2929 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2930 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2931 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2933 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2934 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2935 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2936 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2938 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2939 and none can hold SFmode/SImode values. */
2940 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2941 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2942 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2943 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2946 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2952 int sparc_mode_class [NUM_MACHINE_MODES];
2954 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2961 for (i = 0; i < NUM_MACHINE_MODES; i++)
2963 switch (GET_MODE_CLASS (i))
2966 case MODE_PARTIAL_INT:
2967 case MODE_COMPLEX_INT:
2968 if (GET_MODE_SIZE (i) <= 4)
2969 sparc_mode_class[i] = 1 << (int) S_MODE;
2970 else if (GET_MODE_SIZE (i) == 8)
2971 sparc_mode_class[i] = 1 << (int) D_MODE;
2972 else if (GET_MODE_SIZE (i) == 16)
2973 sparc_mode_class[i] = 1 << (int) T_MODE;
2974 else if (GET_MODE_SIZE (i) == 32)
2975 sparc_mode_class[i] = 1 << (int) O_MODE;
2977 sparc_mode_class[i] = 0;
2980 case MODE_COMPLEX_FLOAT:
2981 if (GET_MODE_SIZE (i) <= 4)
2982 sparc_mode_class[i] = 1 << (int) SF_MODE;
2983 else if (GET_MODE_SIZE (i) == 8)
2984 sparc_mode_class[i] = 1 << (int) DF_MODE;
2985 else if (GET_MODE_SIZE (i) == 16)
2986 sparc_mode_class[i] = 1 << (int) TF_MODE;
2987 else if (GET_MODE_SIZE (i) == 32)
2988 sparc_mode_class[i] = 1 << (int) OF_MODE;
2990 sparc_mode_class[i] = 0;
2994 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2995 we must explicitly check for them here. */
2996 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2997 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2998 else if (i == (int) CCmode || i == (int) CC_NOOVmode
2999 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3000 sparc_mode_class[i] = 1 << (int) CC_MODE;
3002 sparc_mode_class[i] = 0;
3008 hard_regno_mode_classes = hard_64bit_mode_classes;
3010 hard_regno_mode_classes = hard_32bit_mode_classes;
3012 /* Initialize the array used by REGNO_REG_CLASS. */
3013 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3016 sparc_regno_reg_class[i] = GENERAL_REGS;
3018 sparc_regno_reg_class[i] = FP_REGS;
3020 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3022 sparc_regno_reg_class[i] = FPCC_REGS;
3024 sparc_regno_reg_class[i] = NO_REGS;
3028 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3029 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3030 v9 int regs as it simplifies the code. */
3033 save_regs (file, low, high, base, offset, n_regs, real_offset)
3043 if (TARGET_ARCH64 && high <= 32)
3045 for (i = low; i < high; i++)
3047 if (regs_ever_live[i] && ! call_used_regs[i])
3049 fprintf (file, "\tstx %s,[%s+%d]\n",
3050 reg_names[i], base, offset + 4 * n_regs);
3051 if (dwarf2out_do_frame ())
3052 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3059 for (i = low; i < high; i += 2)
3061 if (regs_ever_live[i] && ! call_used_regs[i])
3062 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3064 fprintf (file, "\tstd %s,[%s+%d]\n",
3065 reg_names[i], base, offset + 4 * n_regs);
3066 if (dwarf2out_do_frame ())
3068 char *l = dwarf2out_cfi_label ();
3069 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3070 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3076 fprintf (file, "\tst %s,[%s+%d]\n",
3077 reg_names[i], base, offset + 4 * n_regs);
3078 if (dwarf2out_do_frame ())
3079 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3082 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3084 fprintf (file, "\tst %s,[%s+%d]\n",
3085 reg_names[i+1], base, offset + 4 * n_regs + 4);
3086 if (dwarf2out_do_frame ())
3087 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3095 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3097 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3098 v9 int regs as it simplifies the code. */
3101 restore_regs (file, low, high, base, offset, n_regs)
3110 if (TARGET_ARCH64 && high <= 32)
3112 for (i = low; i < high; i++)
3114 if (regs_ever_live[i] && ! call_used_regs[i])
3115 fprintf (file, "\tldx [%s+%d], %s\n",
3116 base, offset + 4 * n_regs, reg_names[i]),
3122 for (i = low; i < high; i += 2)
3124 if (regs_ever_live[i] && ! call_used_regs[i])
3125 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3126 fprintf (file, "\tldd [%s+%d], %s\n",
3127 base, offset + 4 * n_regs, reg_names[i]),
3130 fprintf (file, "\tld [%s+%d],%s\n",
3131 base, offset + 4 * n_regs, reg_names[i]),
3133 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3134 fprintf (file, "\tld [%s+%d],%s\n",
3135 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3142 /* Static variables we want to share between prologue and epilogue. */
3144 /* Number of live general or floating point registers needed to be saved
3145 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
3146 static int num_gfregs;
3148 /* Compute the frame size required by the function. This function is called
3149 during the reload pass and also by output_function_prologue(). */
3152 compute_frame_size (size, leaf_function)
3157 int outgoing_args_size = (current_function_outgoing_args_size
3158 + REG_PARM_STACK_SPACE (current_function_decl));
3160 if (TARGET_EPILOGUE)
3162 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3163 even to v9 int regs to be consistent with save_regs/restore_regs. */
3167 for (i = 0; i < 8; i++)
3168 if (regs_ever_live[i] && ! call_used_regs[i])
3173 for (i = 0; i < 8; i += 2)
3174 if ((regs_ever_live[i] && ! call_used_regs[i])
3175 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3179 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3180 if ((regs_ever_live[i] && ! call_used_regs[i])
3181 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3185 /* Set up values for use in `function_epilogue'. */
3186 num_gfregs = n_regs;
3188 if (leaf_function && n_regs == 0
3189 && size == 0 && current_function_outgoing_args_size == 0)
3191 actual_fsize = apparent_fsize = 0;
3195 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3196 The stack bias (if any) is taken out to undo its effects. */
3197 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3198 apparent_fsize += n_regs * 4;
3199 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3202 /* Make sure nothing can clobber our register windows.
3203 If a SAVE must be done, or there is a stack-local variable,
3204 the register window area must be allocated.
3205 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3206 if (leaf_function == 0 || size > 0)
3207 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3209 return SPARC_STACK_ALIGN (actual_fsize);
3212 /* Build a (32 bit) big number in a register. */
3213 /* ??? We may be able to use the set macro here too. */
3216 build_big_number (file, num, reg)
3221 if (num >= 0 || ! TARGET_ARCH64)
3223 fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg);
3224 if ((num & 0x3ff) != 0)
3225 fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg);
3227 else /* num < 0 && TARGET_ARCH64 */
3229 /* Sethi does not sign extend, so we must use a little trickery
3230 to use it for negative numbers. Invert the constant before
3231 loading it in, then use xor immediate to invert the loaded bits
3232 (along with the upper 32 bits) to the desired constant. This
3233 works because the sethi and immediate fields overlap. */
3236 int low = -0x400 + (asize & 0x3FF);
3238 fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
3239 inv, reg, reg, low, reg);
3243 /* Output code for the function prologue. */
3246 output_function_prologue (file, size, leaf_function)
3251 /* Need to use actual_fsize, since we are also allocating
3252 space for our callee (and our own register save area). */
3253 actual_fsize = compute_frame_size (size, leaf_function);
3257 frame_base_name = "%sp";
3258 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3262 frame_base_name = "%fp";
3263 frame_base_offset = SPARC_STACK_BIAS;
3266 /* This is only for the human reader. */
3267 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3269 if (actual_fsize == 0)
3271 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3273 if (actual_fsize <= 4096)
3274 fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize);
3275 else if (actual_fsize <= 8192)
3277 fprintf (file, "\tsave %%sp,-4096,%%sp\n");
3278 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3282 build_big_number (file, -actual_fsize, "%g1");
3283 fprintf (file, "\tsave %%sp,%%g1,%%sp\n");
3286 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3288 /* We assume the environment will properly handle or otherwise avoid
3289 trouble associated with an interrupt occuring after the `save' or
3290 trap occuring during it. */
3291 fprintf (file, "\tsave\n");
3293 if (actual_fsize <= 4096)
3294 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize);
3295 else if (actual_fsize <= 8192)
3297 fprintf (file, "\tadd %%fp,-4096,%%sp\n");
3298 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize - 4096);
3302 build_big_number (file, -actual_fsize, "%g1");
3303 fprintf (file, "\tadd %%fp,%%g1,%%sp\n");
3306 else /* leaf function */
3308 if (actual_fsize <= 4096)
3309 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize);
3310 else if (actual_fsize <= 8192)
3312 fprintf (file, "\tadd %%sp,-4096,%%sp\n");
3313 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3317 build_big_number (file, -actual_fsize, "%g1");
3318 fprintf (file, "\tadd %%sp,%%g1,%%sp\n");
3322 if (dwarf2out_do_frame () && actual_fsize)
3324 char *label = dwarf2out_cfi_label ();
3326 /* The canonical frame address refers to the top of the frame. */
3327 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3328 : FRAME_POINTER_REGNUM),
3331 if (! leaf_function)
3333 /* Note the register window save. This tells the unwinder that
3334 it needs to restore the window registers from the previous
3335 frame's window save area at 0(cfa). */
3336 dwarf2out_window_save (label);
3338 /* The return address (-8) is now in %i7. */
3339 dwarf2out_return_reg (label, 31);
3343 /* If doing anything with PIC, do it now. */
3345 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3347 /* Call saved registers are saved just above the outgoing argument area. */
3350 int offset, real_offset, n_regs;
3353 real_offset = -apparent_fsize;
3354 offset = -apparent_fsize + frame_base_offset;
3355 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3357 /* ??? This might be optimized a little as %g1 might already have a
3358 value close enough that a single add insn will do. */
3359 /* ??? Although, all of this is probably only a temporary fix
3360 because if %g1 can hold a function result, then
3361 output_function_epilogue will lose (the result will get
3363 build_big_number (file, offset, "%g1");
3364 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3370 base = frame_base_name;
3373 if (TARGET_EPILOGUE && ! leaf_function)
3374 /* ??? Originally saved regs 0-15 here. */
3375 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3376 else if (leaf_function)
3377 /* ??? Originally saved regs 0-31 here. */
3378 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3379 if (TARGET_EPILOGUE)
3380 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3385 if (leaf_function && actual_fsize != 0)
3387 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3388 if (! TARGET_EPILOGUE)
3389 leaf_label = gen_label_rtx ();
3393 /* Output code for the function epilogue. */
3396 output_function_epilogue (file, size, leaf_function)
3405 emit_label_after (leaf_label, get_last_insn ());
3406 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3409 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3410 else if (profile_block_flag == 2)
3412 FUNCTION_BLOCK_PROFILER_EXIT(file);
3416 /* Restore any call saved registers. */
3422 offset = -apparent_fsize + frame_base_offset;
3423 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3425 build_big_number (file, offset, "%g1");
3426 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3432 base = frame_base_name;
3435 if (TARGET_EPILOGUE && ! leaf_function)
3436 /* ??? Originally saved regs 0-15 here. */
3437 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3438 else if (leaf_function)
3439 /* ??? Originally saved regs 0-31 here. */
3440 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3441 if (TARGET_EPILOGUE)
3442 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3445 /* Work out how to skip the caller's unimp instruction if required. */
3447 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl");
3449 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret");
3451 if (TARGET_EPILOGUE || leaf_label)
3453 int old_target_epilogue = TARGET_EPILOGUE;
3454 target_flags &= ~old_target_epilogue;
3456 if (! leaf_function)
3458 /* If we wound up with things in our delay slot, flush them here. */
3459 if (current_function_epilogue_delay_list)
3461 rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode),
3463 PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode,
3465 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3467 final_scan_insn (insn, file, 1, 0, 1);
3470 fprintf (file, "\t%s\n\trestore\n", ret);
3472 /* All of the following cases are for leaf functions. */
3473 else if (current_function_epilogue_delay_list)
3475 /* eligible_for_epilogue_delay_slot ensures that if this is a
3476 leaf function, then we will only have insn in the delay slot
3477 if the frame size is zero, thus no adjust for the stack is
3479 if (actual_fsize != 0)
3481 fprintf (file, "\t%s\n", ret);
3482 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3485 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3486 avoid generating confusing assembly language output. */
3487 else if (actual_fsize == 0)
3488 fprintf (file, "\t%s\n\tnop\n", ret);
3489 else if (actual_fsize <= 4096)
3490 fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize);
3491 else if (actual_fsize <= 8192)
3492 fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3493 ret, actual_fsize - 4096);
3494 else if ((actual_fsize & 0x3ff) == 0)
3495 fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3498 fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3499 actual_fsize, actual_fsize, ret);
3500 target_flags |= old_target_epilogue;
3504 /* Functions for handling argument passing.
3506 For v8 the first six args are normally in registers and the rest are
3507 pushed. Any arg that starts within the first 6 words is at least
3508 partially passed in a register unless its data type forbids.
3510 For v9, the argument registers are laid out as an array of 16 elements
3511 and arguments are added sequentially. The first 6 int args and up to the
3512 first 16 fp args (depending on size) are passed in regs.
3514 Slot Stack Integral Float Float in structure Double Long Double
3515 ---- ----- -------- ----- ------------------ ------ -----------
3516 15 [SP+248] %f31 %f30,%f31 %d30
3517 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3518 13 [SP+232] %f27 %f26,%f27 %d26
3519 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3520 11 [SP+216] %f23 %f22,%f23 %d22
3521 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3522 9 [SP+200] %f19 %f18,%f19 %d18
3523 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3524 7 [SP+184] %f15 %f14,%f15 %d14
3525 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3526 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3527 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3528 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3529 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3530 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3531 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3533 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3535 Integral arguments are always passed as 64 bit quantities appropriately
3538 Passing of floating point values is handled as follows.
3539 If a prototype is in scope:
3540 If the value is in a named argument (i.e. not a stdarg function or a
3541 value not part of the `...') then the value is passed in the appropriate
3543 If the value is part of the `...' and is passed in one of the first 6
3544 slots then the value is passed in the appropriate int reg.
3545 If the value is part of the `...' and is not passed in one of the first 6
3546 slots then the value is passed in memory.
3547 If a prototype is not in scope:
3548 If the value is one of the first 6 arguments the value is passed in the
3549 appropriate integer reg and the appropriate fp reg.
3550 If the value is not one of the first 6 arguments the value is passed in
3551 the appropriate fp reg and in memory.
3554 /* Maximum number of int regs for args. */
3555 #define SPARC_INT_ARG_MAX 6
3556 /* Maximum number of fp regs for args. */
3557 #define SPARC_FP_ARG_MAX 16
3559 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3561 /* Handle the INIT_CUMULATIVE_ARGS macro.
3562 Initialize a variable CUM of type CUMULATIVE_ARGS
3563 for a call to a function whose data type is FNTYPE.
3564 For a library call, FNTYPE is 0. */
3567 init_cumulative_args (cum, fntype, libname, indirect)
3568 CUMULATIVE_ARGS *cum;
3569 tree fntype, libname;
3573 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3574 cum->libcall_p = fntype == 0;
3577 /* Compute the slot number to pass an argument in.
3578 Returns the slot number or -1 if passing on the stack.
3580 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3581 the preceding args and about the function being called.
3582 MODE is the argument's machine mode.
3583 TYPE is the data type of the argument (as a tree).
3584 This is null for libcalls where that information may
3586 NAMED is nonzero if this argument is a named parameter
3587 (otherwise it is an extra parameter matching an ellipsis).
3588 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3589 *PREGNO records the register number to use if scalar type.
3590 *PPADDING records the amount of padding needed in words. */
3593 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3594 const CUMULATIVE_ARGS *cum;
3595 enum machine_mode mode;
3602 int regbase = (incoming_p
3603 ? SPARC_INCOMING_INT_ARG_FIRST
3604 : SPARC_OUTGOING_INT_ARG_FIRST);
3605 int slotno = cum->words;
3610 if (type != 0 && TREE_ADDRESSABLE (type))
3613 && type != 0 && mode == BLKmode
3614 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3620 /* MODE is VOIDmode when generating the actual call.
3624 case QImode : case CQImode :
3625 case HImode : case CHImode :
3626 case SImode : case CSImode :
3627 case DImode : case CDImode :
3628 if (slotno >= SPARC_INT_ARG_MAX)
3630 regno = regbase + slotno;
3633 case SFmode : case SCmode :
3634 case DFmode : case DCmode :
3635 case TFmode : case TCmode :
3638 if (slotno >= SPARC_INT_ARG_MAX)
3640 regno = regbase + slotno;
3644 if ((mode == TFmode || mode == TCmode)
3645 && (slotno & 1) != 0)
3646 slotno++, *ppadding = 1;
3647 if (TARGET_FPU && named)
3649 if (slotno >= SPARC_FP_ARG_MAX)
3651 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3657 if (slotno >= SPARC_INT_ARG_MAX)
3659 regno = regbase + slotno;
3665 /* For sparc64, objects requiring 16 byte alignment get it. */
3668 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3669 slotno++, *ppadding = 1;
3673 || type && TREE_CODE (type) == UNION_TYPE)
3675 if (slotno >= SPARC_INT_ARG_MAX)
3677 regno = regbase + slotno;
3682 int intregs_p = 0, fpregs_p = 0;
3683 /* The ABI obviously doesn't specify how packed
3684 structures are passed. These are defined to be passed
3685 in int regs if possible, otherwise memory. */
3688 /* First see what kinds of registers we need. */
3689 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3691 if (TREE_CODE (field) == FIELD_DECL)
3693 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3698 if (DECL_PACKED (field))
3702 if (packed_p || !named)
3703 fpregs_p = 0, intregs_p = 1;
3705 /* If all arg slots are filled, then must pass on stack. */
3706 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3708 /* If there are only int args and all int arg slots are filled,
3709 then must pass on stack. */
3710 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3712 /* Note that even if all int arg slots are filled, fp members may
3713 still be passed in regs if such regs are available.
3714 *PREGNO isn't set because there may be more than one, it's up
3715 to the caller to compute them. */
3728 /* Handle the FUNCTION_ARG macro.
3729 Determine where to put an argument to a function.
3730 Value is zero to push the argument on the stack,
3731 or a hard register in which to store the argument.
3733 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3734 the preceding args and about the function being called.
3735 MODE is the argument's machine mode.
3736 TYPE is the data type of the argument (as a tree).
3737 This is null for libcalls where that information may
3739 NAMED is nonzero if this argument is a named parameter
3740 (otherwise it is an extra parameter matching an ellipsis).
3741 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3744 function_arg (cum, mode, type, named, incoming_p)
3745 const CUMULATIVE_ARGS *cum;
3746 enum machine_mode mode;
3751 int regbase = (incoming_p
3752 ? SPARC_INCOMING_INT_ARG_FIRST
3753 : SPARC_OUTGOING_INT_ARG_FIRST);
3754 int slotno, regno, padding;
3757 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3765 reg = gen_rtx (REG, mode, regno);
3769 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3770 but also have the slot allocated for them.
3771 If no prototype is in scope fp values in register slots get passed
3772 in two places, either fp regs and int regs or fp regs and memory. */
3773 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3774 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3775 && SPARC_FP_REG_P (regno))
3777 reg = gen_rtx (REG, mode, regno);
3778 if (cum->prototype_p || cum->libcall_p)
3780 /* "* 2" because fp reg numbers are recorded in 4 byte
3782 /* ??? This will cause the value to be passed in the fp reg and
3783 in the stack. When a prototype exists we want to pass the
3784 value in the reg but reserve space on the stack. That's an
3785 optimization, and is defered [for a bit]. */
3786 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3787 return gen_rtx (PARALLEL, mode,
3789 gen_rtx (EXPR_LIST, VOIDmode,
3790 NULL_RTX, const0_rtx),
3791 gen_rtx (EXPR_LIST, VOIDmode,
3798 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3800 int regbase = (incoming_p
3801 ? SPARC_INCOMING_INT_ARG_FIRST
3802 : SPARC_OUTGOING_INT_ARG_FIRST);
3803 int intreg = regbase + (regno - SPARC_FP_ARG_FIRST) / 2;
3804 return gen_rtx (PARALLEL, mode,
3806 gen_rtx (EXPR_LIST, VOIDmode,
3807 gen_rtx (REG, mode, intreg),
3809 gen_rtx (EXPR_LIST, VOIDmode,
3813 return gen_rtx (PARALLEL, mode,
3815 gen_rtx (EXPR_LIST, VOIDmode,
3816 NULL_RTX, const0_rtx),
3817 gen_rtx (EXPR_LIST, VOIDmode,
3821 else if (type && TREE_CODE (type) == RECORD_TYPE)
3823 /* Structures up to 16 bytes in size are passed in arg slots on the
3824 stack and are promoted to registers where possible. */
3829 /* Starting bit position of a sequence of integer fields, counted from
3830 msb of left most byte, -1 if last field wasn't an int. */
3831 /* ??? This isn't entirely necessary, some simplification
3833 int start_int_bitpos;
3834 /* Current bitpos in struct, counted from msb of left most byte. */
3835 int bitpos, this_slotno;
3836 /* The ABI obviously doesn't specify how packed
3837 structures are passed. These are defined to be passed
3838 in int regs if possible, otherwise memory. */
3841 if (int_size_in_bytes (type) > 16)
3842 abort (); /* shouldn't get here */
3844 /* We need to compute how many registers are needed so we can allocate
3845 the PARALLEL but before we can do that we need to know whether there
3846 are any packed fields. If there are, int regs are used regardless of
3847 whether there are fp values present. */
3848 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3850 if (TREE_CODE (field) == FIELD_DECL
3851 && DECL_PACKED (field))
3858 /* Compute how many registers we need. */
3860 start_int_bitpos = -1;
3861 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3863 bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3864 this_slotno = slotno + bitpos / BITS_PER_WORD;
3865 if (TREE_CODE (field) == FIELD_DECL)
3867 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3872 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3873 If it wasn't true we wouldn't be here. */
3875 start_int_bitpos = -1;
3877 else if (this_slotno < SPARC_INT_ARG_MAX)
3879 if (start_int_bitpos == -1)
3882 start_int_bitpos = bitpos;
3886 if (bitpos % BITS_PER_WORD == 0)
3895 ret = gen_rtx (PARALLEL, BLKmode, rtvec_alloc (nregs + 1));
3897 /* ??? This causes the entire struct to be passed in memory.
3898 This isn't necessary, but is left for later. */
3899 XVECEXP (ret, 0, 0) = gen_rtx (EXPR_LIST, VOIDmode, NULL_RTX,
3902 /* Fill in the entries. */
3903 start_int_bitpos = -1;
3904 for (i = 1, field = TYPE_FIELDS (type);
3906 field = TREE_CHAIN (field))
3908 bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3909 this_slotno = slotno + bitpos / BITS_PER_WORD;
3910 if (TREE_CODE (field) == FIELD_DECL)
3912 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3917 reg = gen_rtx (REG, DECL_MODE (field),
3918 (SPARC_FP_ARG_FIRST + this_slotno * 2
3919 + (DECL_MODE (field) == SFmode
3920 && (bitpos & 32) != 0)));
3921 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3922 GEN_INT (bitpos / BITS_PER_UNIT));
3924 start_int_bitpos = -1;
3928 if (this_slotno < SPARC_INT_ARG_MAX
3929 && (start_int_bitpos == -1
3930 || bitpos % BITS_PER_WORD == 0))
3932 enum machine_mode mode;
3934 /* If this is the trailing part of a word, only load
3935 that much into the register. Otherwise load the
3936 whole register. Note that in the latter case we may
3937 pick up unwanted bits. It's not a problem at the
3938 moment but may wish to revisit. */
3939 if (bitpos % BITS_PER_WORD != 0)
3940 mode = mode_for_size (BITS_PER_WORD - bitpos % BITS_PER_WORD,
3945 regno = regbase + this_slotno;
3946 reg = gen_rtx (REG, mode, regno);
3947 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3948 GEN_INT (bitpos / BITS_PER_UNIT));
3950 if (start_int_bitpos == -1)
3951 start_int_bitpos = bitpos;
3961 else if (type && TREE_CODE (type) == UNION_TYPE)
3963 enum machine_mode mode;
3964 int bytes = int_size_in_bytes (type);
3969 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
3970 reg = gen_rtx (REG, mode, regno);
3974 /* Scalar or complex int. */
3975 reg = gen_rtx (REG, mode, regno);
3981 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3982 For an arg passed partly in registers and partly in memory,
3983 this is the number of registers used.
3984 For args passed entirely in registers or entirely in memory, zero.
3986 Any arg that starts in the first 6 regs but won't entirely fit in them
3987 needs partial registers on v8. On v9, structures with integer
3988 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
3989 values that begin in the last fp reg [where "last fp reg" varies with the
3990 mode] will be split between that reg and memory. */
3993 function_arg_partial_nregs (cum, mode, type, named)
3994 const CUMULATIVE_ARGS *cum;
3995 enum machine_mode mode;
3999 int slotno, regno, padding;
4001 /* We pass 0 for incoming_p here, it doesn't matter. */
4002 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4009 if ((slotno + (mode == BLKmode
4010 ? ROUND_ADVANCE (int_size_in_bytes (type))
4011 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4012 > NPARM_REGS (SImode))
4013 return NPARM_REGS (SImode) - slotno;
4018 if (type && AGGREGATE_TYPE_P (type))
4020 int size = int_size_in_bytes (type);
4021 int align = TYPE_ALIGN (type);
4024 slotno += slotno & 1;
4025 if (size > 8 && size <= 16
4026 && slotno == SPARC_INT_ARG_MAX - 1)
4029 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4030 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4033 if (GET_MODE_ALIGNMENT (mode) == 128)
4035 slotno += slotno & 1;
4036 if (slotno == SPARC_INT_ARG_MAX - 2)
4041 if (slotno == SPARC_INT_ARG_MAX - 1)
4045 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4047 if (GET_MODE_ALIGNMENT (mode) == 128)
4048 slotno += slotno & 1;
4049 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4057 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4058 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4059 quad-precision floats by invisible reference.
4060 v9: aggregates greater than 16 bytes are passed by reference.
4061 For Pascal, also pass arrays by reference. */
4064 function_arg_pass_by_reference (cum, mode, type, named)
4065 const CUMULATIVE_ARGS *cum;
4066 enum machine_mode mode;
4072 return (type && AGGREGATE_TYPE_P (type)
4073 || mode == TFmode || mode == TCmode);
4077 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4078 || (type && AGGREGATE_TYPE_P (type)
4079 && int_size_in_bytes (type) > 16));
4083 /* Handle the FUNCTION_ARG_ADVANCE macro.
4084 Update the data in CUM to advance over an argument
4085 of mode MODE and data type TYPE.
4086 TYPE is null for libcalls where that information may not be available. */
4089 function_arg_advance (cum, mode, type, named)
4090 CUMULATIVE_ARGS *cum;
4091 enum machine_mode mode;
4095 int slotno, regno, padding;
4097 /* We pass 0 for incoming_p here, it doesn't matter. */
4098 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4100 /* If register required leading padding, add it. */
4102 cum->words += padding;
4106 cum->words += (mode != BLKmode
4107 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4108 : ROUND_ADVANCE (int_size_in_bytes (type)));
4112 if (type && AGGREGATE_TYPE_P (type))
4114 int size = int_size_in_bytes (type);
4118 else if (size <= 16)
4120 else /* passed by reference */
4123 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4127 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4129 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4133 cum->words += (mode != BLKmode
4134 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4135 : ROUND_ADVANCE (int_size_in_bytes (type)));
4140 /* Handle the FUNCTION_ARG_PADDING macro.
4141 For the 64 bit ABI structs are always stored left shifted in their
4145 function_arg_padding (mode, type)
4146 enum machine_mode mode;
4149 if (TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE)
4154 /* This is the default definition. */
4155 return (! BYTES_BIG_ENDIAN
4158 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4159 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4160 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4161 ? downward : upward));
4164 /* Do what is necessary for `va_start'. The argument is ignored.
4166 We look at the current function to determine if stdarg or varargs
4167 is used and return the address of the first unnamed parameter. */
4170 sparc_builtin_saveregs (arglist)
4173 tree fntype = TREE_TYPE (current_function_decl);
4174 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
4175 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4176 != void_type_node));
4177 int first_reg = current_function_args_info.words;
4181 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4182 emit_move_insn (gen_rtx (MEM, word_mode,
4183 gen_rtx (PLUS, Pmode,
4185 GEN_INT (STACK_POINTER_OFFSET
4186 + UNITS_PER_WORD * regno))),
4187 gen_rtx (REG, word_mode,
4188 BASE_INCOMING_ARG_REG (word_mode) + regno));
4190 address = gen_rtx (PLUS, Pmode,
4192 GEN_INT (STACK_POINTER_OFFSET
4193 + UNITS_PER_WORD * first_reg));
4195 if (flag_check_memory_usage
4196 && first_reg < NPARM_REGS (word_mode))
4197 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4199 GEN_INT (UNITS_PER_WORD
4200 * (NPARM_REGS (word_mode) - first_reg)),
4201 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), QImode);
4206 /* Return the string to output a conditional branch to LABEL, which is
4207 the operand number of the label. OP is the conditional expression.
4208 XEXP (OP, 0) is assumed to be a condition code register (integer or
4209 floating point) and its mode specifies what kind of comparison we made.
4211 REVERSED is non-zero if we should reverse the sense of the comparison.
4213 ANNUL is non-zero if we should generate an annulling branch.
4215 NOOP is non-zero if we have to follow this branch by a noop. */
4218 output_cbranch (op, label, reversed, annul, noop)
4221 int reversed, annul, noop;
4223 static char string[20];
4224 enum rtx_code code = GET_CODE (op);
4225 rtx cc_reg = XEXP (op, 0);
4226 enum machine_mode mode = GET_MODE (cc_reg);
4227 static char v8_labelno[] = " %lX";
4228 static char v9_icc_labelno[] = " %%icc,%lX";
4229 static char v9_xcc_labelno[] = " %%xcc,%lX";
4230 static char v9_fcc_labelno[] = " %%fccX,%lY";
4234 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4235 Because there is currently no concept of pre-delay slots, we can fix
4236 this only by always emitting a nop before a floating point branch. */
4238 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4239 strcpy (string, "nop\n\t");
4243 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4245 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4246 code = reverse_condition (code), reversed = 0;
4248 /* Start by writing the branch condition. */
4252 if (mode == CCFPmode || mode == CCFPEmode)
4253 strcat (string, "fbne");
4255 strcpy (string, "bne");
4259 if (mode == CCFPmode || mode == CCFPEmode)
4260 strcat (string, "fbe");
4262 strcpy (string, "be");
4266 if (mode == CCFPmode || mode == CCFPEmode)
4269 strcat (string, "fbul");
4271 strcat (string, "fbge");
4273 else if (mode == CC_NOOVmode)
4274 strcpy (string, "bpos");
4276 strcpy (string, "bge");
4280 if (mode == CCFPmode || mode == CCFPEmode)
4283 strcat (string, "fbule");
4285 strcat (string, "fbg");
4288 strcpy (string, "bg");
4292 if (mode == CCFPmode || mode == CCFPEmode)
4295 strcat (string, "fbug");
4297 strcat (string, "fble");
4300 strcpy (string, "ble");
4304 if (mode == CCFPmode || mode == CCFPEmode)
4307 strcat (string, "fbuge");
4309 strcat (string, "fbl");
4311 else if (mode == CC_NOOVmode)
4312 strcpy (string, "bneg");
4314 strcpy (string, "bl");
4318 strcpy (string, "bgeu");
4322 strcpy (string, "bgu");
4326 strcpy (string, "bleu");
4330 strcpy (string, "blu");
4334 /* Now add the annulling, the label, and a possible noop. */
4336 strcat (string, ",a");
4338 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
4343 labelno = v8_labelno;
4348 if (mode == CCFPmode || mode == CCFPEmode)
4351 labelno = v9_fcc_labelno;
4352 /* Set the char indicating the number of the fcc reg to use. */
4353 labelno[6] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4355 else if (mode == CCXmode || mode == CCX_NOOVmode)
4356 labelno = v9_xcc_labelno;
4358 labelno = v9_icc_labelno;
4360 /* Set the char indicating the number of the operand containing the
4362 labelno[labeloff] = label + '0';
4363 strcat (string, labelno);
4366 strcat (string, "\n\tnop");
4371 /* Return the string to output a conditional branch to LABEL, testing
4372 register REG. LABEL is the operand number of the label; REG is the
4373 operand number of the reg. OP is the conditional expression. The mode
4374 of REG says what kind of comparison we made.
4376 REVERSED is non-zero if we should reverse the sense of the comparison.
4378 ANNUL is non-zero if we should generate an annulling branch.
4380 NOOP is non-zero if we have to follow this branch by a noop. */
4383 output_v9branch (op, reg, label, reversed, annul, noop)
4386 int reversed, annul, noop;
4388 static char string[20];
4389 enum rtx_code code = GET_CODE (op);
4390 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4391 static char labelno[] = " %X,%lX";
4393 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4395 code = reverse_condition (code), reversed = 0;
4397 /* Only 64 bit versions of these instructions exist. */
4401 /* Start by writing the branch condition. */
4406 strcpy (string, "brnz");
4410 strcpy (string, "brz");
4414 strcpy (string, "brgez");
4418 strcpy (string, "brlz");
4422 strcpy (string, "brlez");
4426 strcpy (string, "brgz");
4433 /* Now add the annulling, reg, label, and nop. */
4435 strcat (string, ",a");
4437 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
4439 labelno[2] = reg + '0';
4440 labelno[6] = label + '0';
4441 strcat (string, labelno);
4444 strcat (string, "\n\tnop");
4449 /* Output assembler code to return from a function. */
4451 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
4452 md file for the `return' instruction. */
4455 output_return (operands)
4460 operands[0] = leaf_label;
4463 else if (leaf_function)
4465 /* If we didn't allocate a frame pointer for the current function,
4466 the stack pointer might have been adjusted. Output code to
4469 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize);
4471 /* Use sub of negated value in first two cases instead of add to
4472 allow actual_fsize == 4096. */
4474 if (actual_fsize <= 4096)
4476 if (SKIP_CALLERS_UNIMP_P)
4477 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4479 return "retl\n\tsub %%sp,-%0,%%sp";
4481 else if (actual_fsize <= 8192)
4483 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096);
4484 if (SKIP_CALLERS_UNIMP_P)
4485 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4487 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
4489 else if (SKIP_CALLERS_UNIMP_P)
4491 if ((actual_fsize & 0x3ff) != 0)
4492 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4494 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4498 if ((actual_fsize & 0x3ff) != 0)
4499 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4501 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4506 if (SKIP_CALLERS_UNIMP_P)
4507 return "jmp %%i7+12\n\trestore";
4509 return "ret\n\trestore";
4513 /* Leaf functions and non-leaf functions have different needs. */
4516 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4519 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4521 static int *reg_alloc_orders[] = {
4522 reg_leaf_alloc_order,
4523 reg_nonleaf_alloc_order};
4526 order_regs_for_local_alloc ()
4528 static int last_order_nonleaf = 1;
4530 if (regs_ever_live[15] != last_order_nonleaf)
4532 last_order_nonleaf = !last_order_nonleaf;
4533 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4534 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4538 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4539 This makes them candidates for using ldd and std insns.
4541 Note reg1 and reg2 *must* be hard registers. To be sure we will
4542 abort if we are passed pseudo registers. */
4545 registers_ok_for_ldd_peep (reg1, reg2)
4548 /* We might have been passed a SUBREG. */
4549 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4552 if (REGNO (reg1) % 2 != 0)
4555 return (REGNO (reg1) == REGNO (reg2) - 1);
4558 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4561 This can only happen when addr1 and addr2 are consecutive memory
4562 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4563 64 bit boundary (addr1 % 8 == 0).
4565 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4566 registers are assumed to *never* be properly aligned and are
4569 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4570 need only check that the offset for addr1 % 8 == 0. */
4573 addrs_ok_for_ldd_peep (addr1, addr2)
4578 /* Extract a register number and offset (if used) from the first addr. */
4579 if (GET_CODE (addr1) == PLUS)
4581 /* If not a REG, return zero. */
4582 if (GET_CODE (XEXP (addr1, 0)) != REG)
4586 reg1 = REGNO (XEXP (addr1, 0));
4587 /* The offset must be constant! */
4588 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4590 offset1 = INTVAL (XEXP (addr1, 1));
4593 else if (GET_CODE (addr1) != REG)
4597 reg1 = REGNO (addr1);
4598 /* This was a simple (mem (reg)) expression. Offset is 0. */
4602 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4603 if (GET_CODE (addr2) != PLUS)
4606 if (GET_CODE (XEXP (addr2, 0)) != REG
4607 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4610 /* Only %fp and %sp are allowed. Additionally both addresses must
4611 use the same register. */
4612 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4615 if (reg1 != REGNO (XEXP (addr2, 0)))
4618 /* The first offset must be evenly divisible by 8 to ensure the
4619 address is 64 bit aligned. */
4620 if (offset1 % 8 != 0)
4623 /* The offset for the second addr must be 4 more than the first addr. */
4624 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4627 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4632 /* Return 1 if reg is a pseudo, or is the first register in
4633 a hard register pair. This makes it a candidate for use in
4634 ldd and std insns. */
4637 register_ok_for_ldd (reg)
4640 /* We might have been passed a SUBREG. */
4641 if (GET_CODE (reg) != REG)
4644 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4645 return (REGNO (reg) % 2 == 0);
4650 /* Print operand X (an rtx) in assembler syntax to file FILE.
4651 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4652 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4655 print_operand (file, x, code)
4663 /* Output a 'nop' if there's nothing for the delay slot. */
4664 if (dbr_sequence_length () == 0)
4665 fputs ("\n\tnop", file);
4668 /* Output an annul flag if there's nothing for the delay slot and we
4669 are optimizing. This is always used with '(' below. */
4670 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4671 this is a dbx bug. So, we only do this when optimizing. */
4672 if (dbr_sequence_length () == 0 && optimize)
4676 /* Output a 'nop' if there's nothing for the delay slot and we are
4677 not optimizing. This is always used with '*' above. */
4678 if (dbr_sequence_length () == 0 && ! optimize)
4679 fputs ("\n\tnop", file);
4682 /* Output the Medium/Anywhere code model base register. */
4683 fputs (MEDANY_BASE_REG, file);
4686 /* Print out what we are using as the frame pointer. This might
4687 be %fp, or might be %sp+offset. */
4688 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4689 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4692 /* Adjust the operand to take into account a RESTORE operation. */
4693 if (GET_CODE (x) != REG)
4694 output_operand_lossage ("Invalid %%Y operand");
4695 else if (REGNO (x) < 8)
4696 fputs (reg_names[REGNO (x)], file);
4697 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4698 fputs (reg_names[REGNO (x)-16], file);
4700 output_operand_lossage ("Invalid %%Y operand");
4703 /* Print out the low order register name of a register pair. */
4704 if (WORDS_BIG_ENDIAN)
4705 fputs (reg_names[REGNO (x)+1], file);
4707 fputs (reg_names[REGNO (x)], file);
4710 /* Print out the high order register name of a register pair. */
4711 if (WORDS_BIG_ENDIAN)
4712 fputs (reg_names[REGNO (x)], file);
4714 fputs (reg_names[REGNO (x)+1], file);
4717 /* Print out the second register name of a register pair or quad.
4718 I.e., R (%o0) => %o1. */
4719 fputs (reg_names[REGNO (x)+1], file);
4722 /* Print out the third register name of a register quad.
4723 I.e., S (%o0) => %o2. */
4724 fputs (reg_names[REGNO (x)+2], file);
4727 /* Print out the fourth register name of a register quad.
4728 I.e., T (%o0) => %o3. */
4729 fputs (reg_names[REGNO (x)+3], file);
4732 /* Print a condition code register. */
4733 if (REGNO (x) == SPARC_ICC_REG)
4735 /* We don't handle CC[X]_NOOVmode because they're not supposed
4737 if (GET_MODE (x) == CCmode)
4738 fputs ("%icc", file);
4739 else if (GET_MODE (x) == CCXmode)
4740 fputs ("%xcc", file);
4745 /* %fccN register */
4746 fputs (reg_names[REGNO (x)], file);
4749 /* Print the operand's address only. */
4750 output_address (XEXP (x, 0));
4753 /* In this case we need a register. Use %g0 if the
4754 operand is const0_rtx. */
4756 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
4758 fputs ("%g0", file);
4765 switch (GET_CODE (x))
4767 case IOR: fputs ("or", file); break;
4768 case AND: fputs ("and", file); break;
4769 case XOR: fputs ("xor", file); break;
4770 default: output_operand_lossage ("Invalid %%A operand");
4775 switch (GET_CODE (x))
4777 case IOR: fputs ("orn", file); break;
4778 case AND: fputs ("andn", file); break;
4779 case XOR: fputs ("xnor", file); break;
4780 default: output_operand_lossage ("Invalid %%B operand");
4784 /* These are used by the conditional move instructions. */
4788 enum rtx_code rc = (code == 'c'
4789 ? reverse_condition (GET_CODE (x))
4793 case NE: fputs ("ne", file); break;
4794 case EQ: fputs ("e", file); break;
4795 case GE: fputs ("ge", file); break;
4796 case GT: fputs ("g", file); break;
4797 case LE: fputs ("le", file); break;
4798 case LT: fputs ("l", file); break;
4799 case GEU: fputs ("geu", file); break;
4800 case GTU: fputs ("gu", file); break;
4801 case LEU: fputs ("leu", file); break;
4802 case LTU: fputs ("lu", file); break;
4803 default: output_operand_lossage (code == 'c'
4804 ? "Invalid %%c operand"
4805 : "Invalid %%C operand");
4810 /* These are used by the movr instruction pattern. */
4814 enum rtx_code rc = (code == 'd'
4815 ? reverse_condition (GET_CODE (x))
4819 case NE: fputs ("ne", file); break;
4820 case EQ: fputs ("e", file); break;
4821 case GE: fputs ("gez", file); break;
4822 case LT: fputs ("lz", file); break;
4823 case LE: fputs ("lez", file); break;
4824 case GT: fputs ("gz", file); break;
4825 default: output_operand_lossage (code == 'd'
4826 ? "Invalid %%d operand"
4827 : "Invalid %%D operand");
4834 /* Print a sign-extended character. */
4835 int i = INTVAL (x) & 0xff;
4838 fprintf (file, "%d", i);
4843 /* Operand must be a MEM; write its address. */
4844 if (GET_CODE (x) != MEM)
4845 output_operand_lossage ("Invalid %%f operand");
4846 output_address (XEXP (x, 0));
4850 /* Do nothing special. */
4854 /* Undocumented flag. */
4855 output_operand_lossage ("invalid operand output code");
4858 if (GET_CODE (x) == REG)
4859 fputs (reg_names[REGNO (x)], file);
4860 else if (GET_CODE (x) == MEM)
4863 /* Poor Sun assembler doesn't understand absolute addressing. */
4864 if (CONSTANT_P (XEXP (x, 0))
4865 && ! TARGET_LIVE_G0)
4866 fputs ("%g0+", file);
4867 output_address (XEXP (x, 0));
4870 else if (GET_CODE (x) == HIGH)
4872 fputs ("%hi(", file);
4873 output_addr_const (file, XEXP (x, 0));
4876 else if (GET_CODE (x) == LO_SUM)
4878 print_operand (file, XEXP (x, 0), 0);
4879 fputs ("+%lo(", file);
4880 output_addr_const (file, XEXP (x, 1));
4883 else if (GET_CODE (x) == CONST_DOUBLE
4884 && (GET_MODE (x) == VOIDmode
4885 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
4887 if (CONST_DOUBLE_HIGH (x) == 0)
4888 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
4889 else if (CONST_DOUBLE_HIGH (x) == -1
4890 && CONST_DOUBLE_LOW (x) < 0)
4891 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
4893 output_operand_lossage ("long long constant not a valid immediate operand");
4895 else if (GET_CODE (x) == CONST_DOUBLE)
4896 output_operand_lossage ("floating point constant not a valid immediate operand");
4897 else { output_addr_const (file, x); }
4900 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4901 a 64 bit (DImode) value. */
4903 /* ??? If there is a 64 bit counterpart to .word that the assembler
4904 understands, then using that would simply this code greatly. */
4905 /* ??? We only output .xword's for symbols and only then in environments
4906 where the assembler can handle them. */
4909 output_double_int (file, value)
4913 if (GET_CODE (value) == CONST_INT)
4915 /* ??? This has endianness issues. */
4916 #if HOST_BITS_PER_WIDE_INT == 64
4917 HOST_WIDE_INT xword = INTVAL (value);
4918 HOST_WIDE_INT high, low;
4920 high = (xword >> 32) & 0xffffffff;
4921 low = xword & 0xffffffff;
4922 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, high));
4923 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, low));
4925 if (INTVAL (value) < 0)
4926 ASM_OUTPUT_INT (file, constm1_rtx);
4928 ASM_OUTPUT_INT (file, const0_rtx);
4929 ASM_OUTPUT_INT (file, value);
4932 else if (GET_CODE (value) == CONST_DOUBLE)
4934 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4935 CONST_DOUBLE_HIGH (value)));
4936 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4937 CONST_DOUBLE_LOW (value)));
4939 else if (GET_CODE (value) == SYMBOL_REF
4940 || GET_CODE (value) == CONST
4941 || GET_CODE (value) == PLUS
4942 || (TARGET_ARCH64 &&
4943 (GET_CODE (value) == LABEL_REF
4944 || GET_CODE (value) == CODE_LABEL
4945 || GET_CODE (value) == MINUS)))
4947 if (!TARGET_V9 || TARGET_MEDLOW)
4949 ASM_OUTPUT_INT (file, const0_rtx);
4950 ASM_OUTPUT_INT (file, value);
4954 fprintf (file, "\t%s\t", ASM_LONGLONG);
4955 output_addr_const (file, value);
4956 fprintf (file, "\n");
4963 /* Return the value of a code used in the .proc pseudo-op that says
4964 what kind of result this function returns. For non-C types, we pick
4965 the closest C type. */
4967 #ifndef CHAR_TYPE_SIZE
4968 #define CHAR_TYPE_SIZE BITS_PER_UNIT
4971 #ifndef SHORT_TYPE_SIZE
4972 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
4975 #ifndef INT_TYPE_SIZE
4976 #define INT_TYPE_SIZE BITS_PER_WORD
4979 #ifndef LONG_TYPE_SIZE
4980 #define LONG_TYPE_SIZE BITS_PER_WORD
4983 #ifndef LONG_LONG_TYPE_SIZE
4984 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
4987 #ifndef FLOAT_TYPE_SIZE
4988 #define FLOAT_TYPE_SIZE BITS_PER_WORD
4991 #ifndef DOUBLE_TYPE_SIZE
4992 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
4995 #ifndef LONG_DOUBLE_TYPE_SIZE
4996 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5000 sparc_type_code (type)
5003 register unsigned long qualifiers = 0;
5004 register unsigned shift = 6;
5006 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5007 setting more, since some assemblers will give an error for this. Also,
5008 we must be careful to avoid shifts of 32 bits or more to avoid getting
5009 unpredictable results. */
5013 switch (TREE_CODE (type))
5020 qualifiers |= (3 << shift);
5022 type = TREE_TYPE (type);
5028 qualifiers |= (2 << shift);
5030 type = TREE_TYPE (type);
5034 case REFERENCE_TYPE:
5037 qualifiers |= (1 << shift);
5039 type = TREE_TYPE (type);
5043 return (qualifiers | 8);
5046 case QUAL_UNION_TYPE:
5047 return (qualifiers | 9);
5050 return (qualifiers | 10);
5053 return (qualifiers | 16);
5056 /* If this is a range type, consider it to be the underlying
5058 if (TREE_TYPE (type) != 0)
5060 type = TREE_TYPE (type);
5064 /* Carefully distinguish all the standard types of C,
5065 without messing up if the language is not C. We do this by
5066 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5067 look at both the names and the above fields, but that's redundant.
5068 Any type whose size is between two C types will be considered
5069 to be the wider of the two types. Also, we do not have a
5070 special code to use for "long long", so anything wider than
5071 long is treated the same. Note that we can't distinguish
5072 between "int" and "long" in this code if they are the same
5073 size, but that's fine, since neither can the assembler. */
5075 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5076 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5078 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5079 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5081 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5082 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5085 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5088 /* Carefully distinguish all the standard types of C,
5089 without messing up if the language is not C. */
5091 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5092 return (qualifiers | 6);
5095 return (qualifiers | 7);
5097 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5098 /* ??? We need to distinguish between double and float complex types,
5099 but I don't know how yet because I can't reach this code from
5100 existing front-ends. */
5101 return (qualifiers | 7); /* Who knows? */
5103 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5104 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5105 case FILE_TYPE: /* GNU Pascal FILE type. */
5106 case SET_TYPE: /* GNU Pascal SET type. */
5107 case LANG_TYPE: /* ? */
5111 abort (); /* Not a type! */
5116 /* Nested function support. */
5118 /* Emit RTL insns to initialize the variable parts of a trampoline.
5119 FNADDR is an RTX for the address of the function's pure code.
5120 CXT is an RTX for the static chain value for the function.
5122 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5123 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5124 (to store insns). This is a bit excessive. Perhaps a different
5125 mechanism would be better here.
5127 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5130 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5131 rtx tramp, fnaddr, cxt;
5133 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt,
5134 size_int (10), 0, 1);
5135 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5136 size_int (10), 0, 1);
5137 rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
5138 rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
5139 rtx g1_sethi = gen_rtx (HIGH, SImode,
5140 gen_rtx (CONST_INT, VOIDmode, 0x03000000));
5141 rtx g2_sethi = gen_rtx (HIGH, SImode,
5142 gen_rtx (CONST_INT, VOIDmode, 0x05000000));
5143 rtx g1_ori = gen_rtx (HIGH, SImode,
5144 gen_rtx (CONST_INT, VOIDmode, 0x82106000));
5145 rtx g2_ori = gen_rtx (HIGH, SImode,
5146 gen_rtx (CONST_INT, VOIDmode, 0x8410A000));
5147 rtx tem = gen_reg_rtx (SImode);
5148 emit_move_insn (tem, g1_sethi);
5149 emit_insn (gen_iorsi3 (high_fn, high_fn, tem));
5150 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn);
5151 emit_move_insn (tem, g1_ori);
5152 emit_insn (gen_iorsi3 (low_fn, low_fn, tem));
5153 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn);
5154 emit_move_insn (tem, g2_sethi);
5155 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem));
5156 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt);
5157 emit_move_insn (tem, g2_ori);
5158 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem));
5159 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt);
5160 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, tramp))));
5161 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
5162 plus_constant (tramp, 8)))));
5163 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
5164 plus_constant (tramp, 16)))));
5167 /* The 64 bit version is simpler because it makes more sense to load the
5168 values as "immediate" data out of the trampoline. It's also easier since
5169 we can read the PC without clobbering a register. */
5172 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5173 rtx tramp, fnaddr, cxt;
5175 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 24)), cxt);
5176 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 32)), fnaddr);
5177 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, tramp))));
5178 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5179 plus_constant (tramp, 8)))));
5180 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5181 plus_constant (tramp, 16)))));
5182 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5183 plus_constant (tramp, 24)))));
5184 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5185 plus_constant (tramp, 32)))));
5188 /* Subroutines to support a flat (single) register window calling
5191 /* Single-register window sparc stack frames look like:
5193 Before call After call
5194 +-----------------------+ +-----------------------+
5196 mem | caller's temps. | | caller's temps. |
5198 +-----------------------+ +-----------------------+
5200 | arguments on stack. | | arguments on stack. |
5202 +-----------------------+FP+92->+-----------------------+
5203 | 6 words to save | | 6 words to save |
5204 | arguments passed | | arguments passed |
5205 | in registers, even | | in registers, even |
5206 | if not passed. | | if not passed. |
5207 SP+68->+-----------------------+FP+68->+-----------------------+
5208 | 1 word struct addr | | 1 word struct addr |
5209 +-----------------------+FP+64->+-----------------------+
5211 | 16 word reg save area | | 16 word reg save area |
5213 SP->+-----------------------+ FP->+-----------------------+
5215 | fp/alu reg moves |
5216 FP-16->+-----------------------+
5220 +-----------------------+
5222 | fp register save |
5224 +-----------------------+
5226 | gp register save |
5228 +-----------------------+
5230 | alloca allocations |
5232 +-----------------------+
5234 | arguments on stack |
5236 SP+92->+-----------------------+
5238 | arguments passed |
5239 | in registers, even |
5240 low | if not passed. |
5241 memory SP+68->+-----------------------+
5242 | 1 word struct addr |
5243 SP+64->+-----------------------+
5245 I 16 word reg save area |
5247 SP->+-----------------------+ */
5249 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5250 save masks, and offsets for the current function. */
5252 struct sparc_frame_info
5254 unsigned long total_size; /* # bytes that the entire frame takes up. */
5255 unsigned long var_size; /* # bytes that variables take up. */
5256 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5257 unsigned long extra_size; /* # bytes of extra gunk. */
5258 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5259 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5260 unsigned long gmask; /* Mask of saved gp registers. */
5261 unsigned long fmask; /* Mask of saved fp registers. */
5262 unsigned long reg_offset; /* Offset from new sp to store regs. */
5263 int initialized; /* Nonzero if frame size already calculated. */
5266 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5267 struct sparc_frame_info current_frame_info;
5269 /* Zero structure to initialize current_frame_info. */
5270 struct sparc_frame_info zero_frame_info;
5272 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5274 #define RETURN_ADDR_REGNUM 15
5275 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5276 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5278 #define MUST_SAVE_REGISTER(regno) \
5279 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5280 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5281 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5283 /* Return the bytes needed to compute the frame pointer from the current
5287 sparc_flat_compute_frame_size (size)
5288 int size; /* # of var. bytes allocated. */
5291 unsigned long total_size; /* # bytes that the entire frame takes up. */
5292 unsigned long var_size; /* # bytes that variables take up. */
5293 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5294 unsigned long extra_size; /* # extra bytes. */
5295 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5296 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5297 unsigned long gmask; /* Mask of saved gp registers. */
5298 unsigned long fmask; /* Mask of saved fp registers. */
5299 unsigned long reg_offset; /* Offset to register save area. */
5300 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5302 /* This is the size of the 16 word reg save area, 1 word struct addr
5303 area, and 4 word fp/alu register copy area. */
5304 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5306 /* Also include the size needed for the 6 parameter registers. */
5307 args_size = current_function_outgoing_args_size + 24;
5308 total_size = var_size + args_size + extra_size;
5316 /* Calculate space needed for gp registers. */
5317 for (regno = 1; regno <= 31; regno++)
5319 if (MUST_SAVE_REGISTER (regno))
5321 /* If we need to save two regs in a row, ensure there's room to bump
5322 up the address to align it to a doubleword boundary. */
5323 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5325 if (gp_reg_size % 8 != 0)
5327 gp_reg_size += 2 * UNITS_PER_WORD;
5328 gmask |= 3 << regno;
5334 gp_reg_size += UNITS_PER_WORD;
5335 gmask |= 1 << regno;
5340 /* Calculate space needed for fp registers. */
5341 for (regno = 32; regno <= 63; regno++)
5343 if (regs_ever_live[regno] && !call_used_regs[regno])
5345 fp_reg_size += UNITS_PER_WORD;
5346 fmask |= 1 << (regno - 32);
5353 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5354 /* Ensure save area is 8 byte aligned if we need it. */
5356 if (need_aligned_p && n != 0)
5358 total_size += 8 - n;
5359 reg_offset += 8 - n;
5361 total_size += gp_reg_size + fp_reg_size;
5364 /* ??? This looks a little suspicious. Clarify. */
5365 if (total_size == extra_size)
5366 total_size = extra_size = 0;
5368 total_size = SPARC_STACK_ALIGN (total_size);
5370 /* Save other computed information. */
5371 current_frame_info.total_size = total_size;
5372 current_frame_info.var_size = var_size;
5373 current_frame_info.args_size = args_size;
5374 current_frame_info.extra_size = extra_size;
5375 current_frame_info.gp_reg_size = gp_reg_size;
5376 current_frame_info.fp_reg_size = fp_reg_size;
5377 current_frame_info.gmask = gmask;
5378 current_frame_info.fmask = fmask;
5379 current_frame_info.reg_offset = reg_offset;
5380 current_frame_info.initialized = reload_completed;
5382 /* Ok, we're done. */
5386 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5389 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5390 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5391 [BASE_REG+OFFSET] will always be a valid address.
5393 WORD_OP is either "st" for save, "ld" for restore.
5394 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5397 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5398 doubleword_op, base_offset)
5401 unsigned int offset;
5402 unsigned long gmask;
5403 unsigned long fmask;
5405 char *doubleword_op;
5406 unsigned long base_offset;
5410 if (gmask == 0 && fmask == 0)
5413 /* Save registers starting from high to low. We've already saved the
5414 previous frame pointer and previous return address for the debugger's
5415 sake. The debugger allows us to not need a nop in the epilog if at least
5416 one register is reloaded in addition to return address. */
5420 for (regno = 1; regno <= 31; regno++)
5422 if ((gmask & (1L << regno)) != 0)
5424 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5426 /* We can save two registers in a row. If we're not at a
5427 double word boundary, move to one.
5428 sparc_flat_compute_frame_size ensures there's room to do
5430 if (offset % 8 != 0)
5431 offset += UNITS_PER_WORD;
5433 if (word_op[0] == 's')
5435 fprintf (file, "\t%s %s,[%s+%d]\n",
5436 doubleword_op, reg_names[regno],
5438 if (dwarf2out_do_frame ())
5440 char *l = dwarf2out_cfi_label ();
5441 dwarf2out_reg_save (l, regno, offset + base_offset);
5443 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5447 fprintf (file, "\t%s [%s+%d],%s\n",
5448 doubleword_op, base_reg, offset,
5451 offset += 2 * UNITS_PER_WORD;
5456 if (word_op[0] == 's')
5458 fprintf (file, "\t%s %s,[%s+%d]\n",
5459 word_op, reg_names[regno],
5461 if (dwarf2out_do_frame ())
5462 dwarf2out_reg_save ("", regno, offset + base_offset);
5465 fprintf (file, "\t%s [%s+%d],%s\n",
5466 word_op, base_reg, offset, reg_names[regno]);
5468 offset += UNITS_PER_WORD;
5476 for (regno = 32; regno <= 63; regno++)
5478 if ((fmask & (1L << (regno - 32))) != 0)
5480 if (word_op[0] == 's')
5482 fprintf (file, "\t%s %s,[%s+%d]\n",
5483 word_op, reg_names[regno],
5485 if (dwarf2out_do_frame ())
5486 dwarf2out_reg_save ("", regno, offset + base_offset);
5489 fprintf (file, "\t%s [%s+%d],%s\n",
5490 word_op, base_reg, offset, reg_names[regno]);
5492 offset += UNITS_PER_WORD;
5498 /* Set up the stack and frame (if desired) for the function. */
5501 sparc_flat_output_function_prologue (file, size)
5505 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5506 unsigned long gmask = current_frame_info.gmask;
5508 /* This is only for the human reader. */
5509 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5510 fprintf (file, "\t%s# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5512 current_frame_info.var_size,
5513 current_frame_info.gp_reg_size / 4,
5514 current_frame_info.fp_reg_size / 4,
5515 current_function_outgoing_args_size,
5516 current_frame_info.extra_size);
5518 size = SPARC_STACK_ALIGN (size);
5519 size = (! current_frame_info.initialized
5520 ? sparc_flat_compute_frame_size (size)
5521 : current_frame_info.total_size);
5523 /* These cases shouldn't happen. Catch them now. */
5524 if (size == 0 && (gmask || current_frame_info.fmask))
5527 /* Allocate our stack frame by decrementing %sp.
5528 At present, the only algorithm gdb can use to determine if this is a
5529 flat frame is if we always set %i7 if we set %sp. This can be optimized
5530 in the future by putting in some sort of debugging information that says
5531 this is a `flat' function. However, there is still the case of debugging
5532 code without such debugging information (including cases where most fns
5533 have such info, but there is one that doesn't). So, always do this now
5534 so we don't get a lot of code out there that gdb can't handle.
5535 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5536 distinguish us from a non-flat function but there won't (and shouldn't)
5537 be any differences anyway. The return pc is saved (if necessary) right
5538 after %i7 so gdb won't have to look too far to find it. */
5541 unsigned int reg_offset = current_frame_info.reg_offset;
5542 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5543 char *t1_str = "%g1";
5545 /* Things get a little tricky if local variables take up more than ~4096
5546 bytes and outgoing arguments take up more than ~4096 bytes. When that
5547 happens, the register save area can't be accessed from either end of
5548 the frame. Handle this by decrementing %sp to the start of the gp
5549 register save area, save the regs, update %i7, and then set %sp to its
5550 final value. Given that we only have one scratch register to play
5551 with it is the cheapest solution, and it helps gdb out as it won't
5552 slow down recognition of flat functions.
5553 Don't change the order of insns emitted here without checking with
5554 the gdb folk first. */
5556 /* Is the entire register save area offsettable from %sp? */
5557 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5561 fprintf (file, "\tadd %s,%d,%s\n",
5562 sp_str, -size, sp_str);
5563 if (gmask & FRAME_POINTER_MASK)
5565 fprintf (file, "\tst %s,[%s+%d]\n",
5566 fp_str, sp_str, reg_offset);
5567 fprintf (file, "\tsub %s,%d,%s\t%s# set up frame pointer\n",
5568 sp_str, -size, fp_str, ASM_COMMENT_START);
5574 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5575 size, t1_str, sp_str, t1_str, sp_str);
5576 if (gmask & FRAME_POINTER_MASK)
5578 fprintf (file, "\tst %s,[%s+%d]\n",
5579 fp_str, sp_str, reg_offset);
5580 fprintf (file, "\tadd %s,%s,%s\t%s# set up frame pointer\n",
5581 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5585 if (dwarf2out_do_frame ())
5587 char *l = dwarf2out_cfi_label ();
5588 if (gmask & FRAME_POINTER_MASK)
5590 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5591 reg_offset - 4 - size);
5592 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5595 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5597 if (gmask & RETURN_ADDR_MASK)
5599 fprintf (file, "\tst %s,[%s+%d]\n",
5600 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5601 if (dwarf2out_do_frame ())
5602 dwarf2out_return_save ("", reg_offset - size);
5605 sparc_flat_save_restore (file, sp_str, reg_offset,
5606 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5607 current_frame_info.fmask,
5608 "st", "std", -size);
5612 /* Subtract %sp in two steps, but make sure there is always a
5613 64 byte register save area, and %sp is properly aligned. */
5614 /* Amount to decrement %sp by, the first time. */
5615 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5616 /* Offset to register save area from %sp. */
5617 unsigned int offset = size1 - (size - reg_offset);
5621 fprintf (file, "\tadd %s,%d,%s\n",
5622 sp_str, -size1, sp_str);
5623 if (gmask & FRAME_POINTER_MASK)
5625 fprintf (file, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t%s# set up frame pointer\n",
5626 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5633 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5634 size1, t1_str, sp_str, t1_str, sp_str);
5635 if (gmask & FRAME_POINTER_MASK)
5637 fprintf (file, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t%s# set up frame pointer\n",
5638 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5643 if (dwarf2out_do_frame ())
5645 char *l = dwarf2out_cfi_label ();
5646 if (gmask & FRAME_POINTER_MASK)
5648 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5649 offset - 4 - size1);
5650 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5653 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5655 if (gmask & RETURN_ADDR_MASK)
5657 fprintf (file, "\tst %s,[%s+%d]\n",
5658 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5659 if (dwarf2out_do_frame ())
5660 /* offset - size1 == reg_offset - size
5661 if reg_offset were updated above like offset. */
5662 dwarf2out_return_save ("", offset - size1);
5665 sparc_flat_save_restore (file, sp_str, offset,
5666 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5667 current_frame_info.fmask,
5668 "st", "std", -size1);
5669 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5670 size - size1, t1_str, sp_str, t1_str, sp_str);
5671 if (dwarf2out_do_frame ())
5672 if (! (gmask & FRAME_POINTER_MASK))
5673 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5677 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5680 /* Do any necessary cleanup after a function to restore stack, frame,
5684 sparc_flat_output_function_epilogue (file, size)
5688 rtx epilogue_delay = current_function_epilogue_delay_list;
5689 int noepilogue = FALSE;
5691 /* This is only for the human reader. */
5692 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5694 /* The epilogue does not depend on any registers, but the stack
5695 registers, so we assume that if we have 1 pending nop, it can be
5696 ignored, and 2 it must be filled (2 nops occur for integer
5697 multiply and divide). */
5699 size = SPARC_STACK_ALIGN (size);
5700 size = (!current_frame_info.initialized
5701 ? sparc_flat_compute_frame_size (size)
5702 : current_frame_info.total_size);
5704 if (size == 0 && epilogue_delay == 0)
5706 rtx insn = get_last_insn ();
5708 /* If the last insn was a BARRIER, we don't have to write any code
5709 because a jump (aka return) was put there. */
5710 if (GET_CODE (insn) == NOTE)
5711 insn = prev_nonnote_insn (insn);
5712 if (insn && GET_CODE (insn) == BARRIER)
5718 unsigned int reg_offset = current_frame_info.reg_offset;
5720 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5721 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5722 char *t1_str = "%g1";
5724 /* In the reload sequence, we don't need to fill the load delay
5725 slots for most of the loads, also see if we can fill the final
5726 delay slot if not otherwise filled by the reload sequence. */
5729 fprintf (file, "\tset %d,%s\n", size, t1_str);
5731 if (frame_pointer_needed)
5734 fprintf (file,"\tsub %s,%s,%s\t\t%s# sp not trusted here\n",
5735 fp_str, t1_str, sp_str, ASM_COMMENT_START);
5737 fprintf (file,"\tsub %s,%d,%s\t\t%s# sp not trusted here\n",
5738 fp_str, size, sp_str, ASM_COMMENT_START);
5741 /* Is the entire register save area offsettable from %sp? */
5742 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5748 /* Restore %sp in two steps, but make sure there is always a
5749 64 byte register save area, and %sp is properly aligned. */
5750 /* Amount to increment %sp by, the first time. */
5751 size1 = ((reg_offset - 64 - 16) + 15) & -16;
5752 /* Offset to register save area from %sp. */
5753 reg_offset = size1 - reg_offset;
5755 fprintf (file, "\tset %d,%s\n\tadd %s,%s,%s\n",
5756 size1, t1_str, sp_str, t1_str, sp_str);
5759 /* We must restore the frame pointer and return address reg first
5760 because they are treated specially by the prologue output code. */
5761 if (current_frame_info.gmask & FRAME_POINTER_MASK)
5763 fprintf (file, "\tld [%s+%d],%s\n",
5764 sp_str, reg_offset, fp_str);
5767 if (current_frame_info.gmask & RETURN_ADDR_MASK)
5769 fprintf (file, "\tld [%s+%d],%s\n",
5770 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
5774 /* Restore any remaining saved registers. */
5775 sparc_flat_save_restore (file, sp_str, reg_offset,
5776 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5777 current_frame_info.fmask,
5780 /* If we had to increment %sp in two steps, record it so the second
5781 restoration in the epilogue finishes up. */
5786 fprintf (file, "\tset %d,%s\n",
5790 if (current_function_returns_struct)
5791 fprintf (file, "\tjmp %%o7+12\n");
5793 fprintf (file, "\tretl\n");
5795 /* If the only register saved is the return address, we need a
5796 nop, unless we have an instruction to put into it. Otherwise
5797 we don't since reloading multiple registers doesn't reference
5798 the register being loaded. */
5804 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
5807 else if (size > 4095)
5808 fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str);
5811 fprintf (file, "\tadd %s,%d,%s\n", sp_str, size, sp_str);
5814 fprintf (file, "\tnop\n");
5817 /* Reset state info for each function. */
5818 current_frame_info = zero_frame_info;
5821 /* Define the number of delay slots needed for the function epilogue.
5823 On the sparc, we need a slot if either no stack has been allocated,
5824 or the only register saved is the return register. */
5827 sparc_flat_epilogue_delay_slots ()
5829 if (!current_frame_info.initialized)
5830 (void) sparc_flat_compute_frame_size (get_frame_size ());
5832 if (current_frame_info.total_size == 0)
5838 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5839 Any single length instruction which doesn't reference the stack or frame
5843 sparc_flat_eligible_for_epilogue_delay (trial, slot)
5847 rtx pat = PATTERN (trial);
5849 if (get_attr_length (trial) != 1)
5852 /* If %g0 is live, there are lots of things we can't handle.
5853 Rather than trying to find them all now, let's punt and only
5854 optimize things as necessary. */
5858 if (! reg_mentioned_p (stack_pointer_rtx, pat)
5859 && ! reg_mentioned_p (frame_pointer_rtx, pat))
5865 /* Adjust the cost of a scheduling dependency. Return the new cost of
5866 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5869 supersparc_adjust_cost (insn, link, dep_insn, cost)
5875 enum attr_type insn_type;
5877 if (! recog_memoized (insn))
5880 insn_type = get_attr_type (insn);
5882 if (REG_NOTE_KIND (link) == 0)
5884 /* Data dependency; DEP_INSN writes a register that INSN reads some
5887 /* if a load, then the dependence must be on the memory address;
5888 add an extra 'cycle'. Note that the cost could be two cycles
5889 if the reg was written late in an instruction group; we can't tell
5891 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
5894 /* Get the delay only if the address of the store is the dependence. */
5895 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
5897 rtx pat = PATTERN(insn);
5898 rtx dep_pat = PATTERN (dep_insn);
5900 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
5901 return cost; /* This shouldn't happen! */
5903 /* The dependency between the two instructions was on the data that
5904 is being stored. Assume that this implies that the address of the
5905 store is not dependent. */
5906 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
5909 return cost + 3; /* An approximation. */
5912 /* A shift instruction cannot receive its data from an instruction
5913 in the same cycle; add a one cycle penalty. */
5914 if (insn_type == TYPE_SHIFT)
5915 return cost + 3; /* Split before cascade into shift. */
5919 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5920 INSN writes some cycles later. */
5922 /* These are only significant for the fpu unit; writing a fp reg before
5923 the fpu has finished with it stalls the processor. */
5925 /* Reusing an integer register causes no problems. */
5926 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)