1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-96, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
40 /* 1 if the caller has placed an "unimp" insn immediately after the call.
41 This is used in v8 code when calling a function that returns a structure.
42 v9 doesn't have this. Be careful to have this test be the same as that
45 #define SKIP_CALLERS_UNIMP_P \
46 (!TARGET_ARCH64 && current_function_returns_struct \
47 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
48 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
51 /* Global variables for machine-dependent things. */
53 /* Size of frame. Need to know this to emit return insns from leaf procedures.
54 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
55 reload pass. This is important as the value is later used in insn
56 scheduling (to see what can go in a delay slot).
57 APPARENT_FSIZE is the size of the stack less the register save area and less
58 the outgoing argument area. It is used when saving call preserved regs. */
59 static int apparent_fsize;
60 static int actual_fsize;
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx sparc_compare_op0, sparc_compare_op1;
67 /* We may need an epilogue if we spill too many registers.
68 If this is non-zero, then we branch here for the epilogue. */
69 static rtx leaf_label;
73 /* Vector to say how input registers are mapped to output
74 registers. FRAME_POINTER_REGNUM cannot be remapped by
75 this function to eliminate it. You must use -fomit-frame-pointer
77 char leaf_reg_remap[] =
78 { 0, 1, 2, 3, 4, 5, 6, 7,
79 -1, -1, -1, -1, -1, -1, 14, -1,
80 -1, -1, -1, -1, -1, -1, -1, -1,
81 8, 9, 10, 11, 12, 13, -1, 15,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 40, 41, 42, 43, 44, 45, 46, 47,
85 48, 49, 50, 51, 52, 53, 54, 55,
86 56, 57, 58, 59, 60, 61, 62, 63,
87 64, 65, 66, 67, 68, 69, 70, 71,
88 72, 73, 74, 75, 76, 77, 78, 79,
89 80, 81, 82, 83, 84, 85, 86, 87,
90 88, 89, 90, 91, 92, 93, 94, 95,
95 /* Name of where we pretend to think the frame pointer points.
96 Normally, this is "%fp", but if we are in a leaf procedure,
97 this is "%sp+something". We record "something" separately as it may be
98 too big for reg+constant addressing. */
100 static char *frame_base_name;
101 static int frame_base_offset;
103 static rtx find_addr_reg ();
104 static void sparc_init_modes ();
106 #ifdef DWARF2_DEBUGGING_INFO
107 extern char *dwarf2out_cfi_label ();
110 /* Option handling. */
112 /* Code model option as passed by user. */
113 char *sparc_cmodel_string;
115 enum cmodel sparc_cmodel;
117 /* Record alignment options as passed by user. */
118 char *sparc_align_loops_string;
119 char *sparc_align_jumps_string;
120 char *sparc_align_funcs_string;
122 /* Parsed values, as a power of two. */
123 int sparc_align_loops;
124 int sparc_align_jumps;
125 int sparc_align_funcs;
127 struct sparc_cpu_select sparc_select[] =
129 /* switch name, tune arch */
130 { (char *)0, "default", 1, 1 },
131 { (char *)0, "-mcpu=", 1, 1 },
132 { (char *)0, "-mtune=", 1, 0 },
136 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
137 enum processor_type sparc_cpu;
139 /* Validate and override various options, and do some machine dependent
143 sparc_override_options ()
145 static struct code_model {
150 { "medlow", CM_MEDLOW },
151 { "medmid", CM_MEDMID },
152 { "medany", CM_MEDANY },
153 { "embmedany", CM_EMBMEDANY },
156 struct code_model *cmodel;
157 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
158 static struct cpu_default {
162 /* There must be one entry here for each TARGET_CPU value. */
163 { TARGET_CPU_sparc, "cypress" },
164 { TARGET_CPU_sparclet, "tsc701" },
165 { TARGET_CPU_sparclite, "f930" },
166 { TARGET_CPU_v8, "v8" },
167 { TARGET_CPU_supersparc, "supersparc" },
168 { TARGET_CPU_v9, "v9" },
169 { TARGET_CPU_ultrasparc, "ultrasparc" },
172 struct cpu_default *def;
173 /* Table of values for -m{cpu,tune}=. */
174 static struct cpu_table {
176 enum processor_type processor;
180 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
181 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
182 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
183 /* TI TMS390Z55 supersparc */
184 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
185 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
186 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
187 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
188 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
189 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
190 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
192 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
193 /* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */
194 { "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 },
195 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
197 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
200 struct cpu_table *cpu;
201 struct sparc_cpu_select *sel;
204 #ifndef SPARC_BI_ARCH
205 /* Check for unsupported architecture size. */
206 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
208 error ("%s is not supported by this configuration",
209 DEFAULT_ARCH32_P ? "-m64" : "-m32");
213 /* Code model selection. */
214 sparc_cmodel = SPARC_DEFAULT_CMODEL;
215 if (sparc_cmodel_string != NULL)
219 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
220 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
222 if (cmodel->name == NULL)
223 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
225 sparc_cmodel = cmodel->value;
228 error ("-mcmodel= is not supported on 32 bit systems");
231 fpu = TARGET_FPU; /* save current -mfpu status */
233 /* Set the default CPU. */
234 for (def = &cpu_default[0]; def->name; ++def)
235 if (def->cpu == TARGET_CPU_DEFAULT)
239 sparc_select[0].string = def->name;
241 for (sel = &sparc_select[0]; sel->name; ++sel)
245 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
246 if (! strcmp (sel->string, cpu->name))
249 sparc_cpu = cpu->processor;
253 target_flags &= ~cpu->disable;
254 target_flags |= cpu->enable;
260 error ("bad value (%s) for %s switch", sel->string, sel->name);
264 /* If -mfpu or -mno-fpu was explicitly used, don't override with
265 the processor default. */
267 target_flags = (target_flags & ~MASK_FPU) | fpu;
269 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
270 if (TARGET_V9 && TARGET_ARCH32)
271 target_flags |= MASK_DEPRECATED_V8_INSNS;
273 /* Validate -malign-loops= value, or provide default. */
274 if (sparc_align_loops_string)
276 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
277 if (sparc_align_loops < 2 || sparc_align_loops > 7)
278 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
279 sparc_align_loops_string);
283 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
284 its 0. This sounds a bit kludgey. */
285 sparc_align_loops = 0;
288 /* Validate -malign-jumps= value, or provide default. */
289 if (sparc_align_jumps_string)
291 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
292 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
293 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
294 sparc_align_jumps_string);
298 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
299 its 0. This sounds a bit kludgey. */
300 sparc_align_jumps = 0;
303 /* Validate -malign-functions= value, or provide default. */
304 if (sparc_align_funcs_string)
306 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
307 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
308 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
309 sparc_align_funcs_string);
312 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
314 /* Do various machine dependent initializations. */
318 /* Float conversions (v9 only).
320 The floating point registers cannot hold DImode values because SUBREG's
321 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
322 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
323 turn the "0" to a "1". Therefore, we must explicitly do the conversions
324 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
325 8 byte stack slot used during the transfer.
326 ??? I could have used [%fp-16] but I didn't want to add yet another
327 dependence on this. */
328 /* ??? Can we use assign_stack_temp here? */
330 static rtx fpconv_stack_temp;
332 /* Called once for each function. */
335 sparc_init_expanders ()
337 fpconv_stack_temp = NULL_RTX;
340 /* Assign a stack temp for fp/int DImode conversions. */
343 sparc64_fpconv_stack_temp ()
345 if (fpconv_stack_temp == NULL_RTX)
347 assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0);
349 return fpconv_stack_temp;
352 /* Miscellaneous utilities. */
354 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
355 or branch on register contents instructions. */
361 return (code == EQ || code == NE || code == GE || code == LT
362 || code == LE || code == GT);
365 /* Operand constraints. */
367 /* Return non-zero only if OP is a register of mode MODE,
368 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
369 %g0 may contain anything. */
372 reg_or_0_operand (op, mode)
374 enum machine_mode mode;
376 if (register_operand (op, mode))
380 if (op == const0_rtx)
382 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
383 && CONST_DOUBLE_HIGH (op) == 0
384 && CONST_DOUBLE_LOW (op) == 0)
386 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
387 && GET_CODE (op) == CONST_DOUBLE
388 && fp_zero_operand (op))
393 /* Nonzero if OP is a floating point value with value 0.0. */
401 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
402 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
405 /* Nonzero if OP is an integer register. */
408 intreg_operand (op, mode)
410 enum machine_mode mode;
412 return (register_operand (op, SImode)
413 || (TARGET_ARCH64 && register_operand (op, DImode)));
416 /* Nonzero if OP is a floating point condition code register. */
419 fcc_reg_operand (op, mode)
421 enum machine_mode mode;
423 /* This can happen when recog is called from combine. Op may be a MEM.
424 Fail instead of calling abort in this case. */
425 if (GET_CODE (op) != REG)
428 if (mode != VOIDmode && mode != GET_MODE (op))
431 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
434 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
435 if (reg_renumber == 0)
436 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
437 return REGNO_OK_FOR_CCFP_P (REGNO (op));
439 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
443 /* Nonzero if OP is an integer or floating point condition code register. */
446 icc_or_fcc_reg_operand (op, mode)
448 enum machine_mode mode;
450 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
452 if (mode != VOIDmode && mode != GET_MODE (op))
455 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
460 return fcc_reg_operand (op, mode);
463 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
465 restore_operand (op, mode)
467 enum machine_mode mode;
469 return (GET_CODE (op) == REG && GET_MODE (op) == mode
470 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
473 /* Call insn on SPARC can take a PC-relative constant address, or any regular
477 call_operand (op, mode)
479 enum machine_mode mode;
481 if (GET_CODE (op) != MEM)
484 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
488 call_operand_address (op, mode)
490 enum machine_mode mode;
492 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
495 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
496 reference and a constant. */
499 symbolic_operand (op, mode)
501 enum machine_mode mode;
503 switch (GET_CODE (op))
511 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
512 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
513 && GET_CODE (XEXP (op, 1)) == CONST_INT);
515 /* ??? This clause seems to be irrelevant. */
517 return GET_MODE (op) == mode;
524 /* Return truth value of statement that OP is a symbolic memory
525 operand of mode MODE. */
528 symbolic_memory_operand (op, mode)
530 enum machine_mode mode;
532 if (GET_CODE (op) == SUBREG)
533 op = SUBREG_REG (op);
534 if (GET_CODE (op) != MEM)
537 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
538 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
541 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
544 label_ref_operand (op, mode)
546 enum machine_mode mode;
548 if (GET_CODE (op) != LABEL_REF)
550 if (GET_MODE (op) != mode)
555 /* Return 1 if the operand is an argument used in generating pic references
556 in either the medium/low or medium/anywhere code models of sparc64. */
559 sp64_medium_pic_operand (op, mode)
561 enum machine_mode mode;
563 /* Check for (const (minus (symbol_ref:GOT)
564 (const (minus (label) (pc))))). */
565 if (GET_CODE (op) != CONST)
568 if (GET_CODE (op) != MINUS)
570 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
572 /* ??? Ensure symbol is GOT. */
573 if (GET_CODE (XEXP (op, 1)) != CONST)
575 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
580 /* Return 1 if the operand is a data segment reference. This includes
581 the readonly data segment, or in other words anything but the text segment.
582 This is needed in the medium/anywhere code model on v9. These values
583 are accessed with EMBMEDANY_BASE_REG. */
586 data_segment_operand (op, mode)
588 enum machine_mode mode;
590 switch (GET_CODE (op))
593 return ! SYMBOL_REF_FLAG (op);
595 /* Assume canonical format of symbol + constant.
598 return data_segment_operand (XEXP (op, 0));
604 /* Return 1 if the operand is a text segment reference.
605 This is needed in the medium/anywhere code model on v9. */
608 text_segment_operand (op, mode)
610 enum machine_mode mode;
612 switch (GET_CODE (op))
617 return SYMBOL_REF_FLAG (op);
619 /* Assume canonical format of symbol + constant.
622 return text_segment_operand (XEXP (op, 0));
628 /* Return 1 if the operand is either a register or a memory operand that is
632 reg_or_nonsymb_mem_operand (op, mode)
634 enum machine_mode mode;
636 if (register_operand (op, mode))
639 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
646 sparc_operand (op, mode)
648 enum machine_mode mode;
650 if (register_operand (op, mode))
652 if (GET_CODE (op) == CONST_INT)
653 return SMALL_INT (op);
654 if (GET_MODE (op) != mode)
656 if (GET_CODE (op) == SUBREG)
657 op = SUBREG_REG (op);
658 if (GET_CODE (op) != MEM)
662 if (GET_CODE (op) == LO_SUM)
663 return (GET_CODE (XEXP (op, 0)) == REG
664 && symbolic_operand (XEXP (op, 1), Pmode));
665 return memory_address_p (mode, op);
669 move_operand (op, mode)
671 enum machine_mode mode;
673 if (mode == DImode && arith_double_operand (op, mode))
675 if (register_operand (op, mode))
677 if (GET_CODE (op) == CONST_INT)
678 return SMALL_INT (op) || SPARC_SETHI_P (INTVAL (op));
680 if (GET_MODE (op) != mode)
682 if (GET_CODE (op) == SUBREG)
683 op = SUBREG_REG (op);
684 if (GET_CODE (op) != MEM)
687 if (GET_CODE (op) == LO_SUM)
688 return (register_operand (XEXP (op, 0), Pmode)
689 && CONSTANT_P (XEXP (op, 1)));
690 return memory_address_p (mode, op);
694 splittable_symbolic_memory_operand (op, mode)
696 enum machine_mode mode;
698 if (GET_CODE (op) != MEM)
700 if (! symbolic_operand (XEXP (op, 0), Pmode))
706 splittable_immediate_memory_operand (op, mode)
708 enum machine_mode mode;
710 if (GET_CODE (op) != MEM)
712 if (! immediate_operand (XEXP (op, 0), Pmode))
717 /* Return truth value of whether OP is EQ or NE. */
722 enum machine_mode mode;
724 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
727 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
728 or LTU for non-floating-point. We handle those specially. */
731 normal_comp_operator (op, mode)
733 enum machine_mode mode;
735 enum rtx_code code = GET_CODE (op);
737 if (GET_RTX_CLASS (code) != '<')
740 if (GET_MODE (XEXP (op, 0)) == CCFPmode
741 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
744 return (code != NE && code != EQ && code != GEU && code != LTU);
747 /* Return 1 if this is a comparison operator. This allows the use of
748 MATCH_OPERATOR to recognize all the branch insns. */
751 noov_compare_op (op, mode)
753 enum machine_mode mode;
755 enum rtx_code code = GET_CODE (op);
757 if (GET_RTX_CLASS (code) != '<')
760 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
761 /* These are the only branches which work with CC_NOOVmode. */
762 return (code == EQ || code == NE || code == GE || code == LT);
766 /* Nonzero if OP is a comparison operator suitable for use in v9
767 conditional move or branch on register contents instructions. */
770 v9_regcmp_op (op, mode)
772 enum machine_mode mode;
774 enum rtx_code code = GET_CODE (op);
776 if (GET_RTX_CLASS (code) != '<')
779 return v9_regcmp_p (code);
782 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
787 enum machine_mode mode;
789 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
792 /* Return nonzero if OP is an operator of mode MODE which can set
793 the condition codes explicitly. We do not include PLUS and MINUS
794 because these require CC_NOOVmode, which we handle explicitly. */
797 cc_arithop (op, mode)
799 enum machine_mode mode;
801 if (GET_CODE (op) == AND
802 || GET_CODE (op) == IOR
803 || GET_CODE (op) == XOR)
809 /* Return nonzero if OP is an operator of mode MODE which can bitwise
810 complement its second operand and set the condition codes explicitly. */
813 cc_arithopn (op, mode)
815 enum machine_mode mode;
817 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
818 and (xor ... (not ...)) to (not (xor ...)). */
819 return (GET_CODE (op) == AND
820 || GET_CODE (op) == IOR);
823 /* Return true if OP is a register, or is a CONST_INT that can fit in a
824 signed 13 bit immediate field. This is an acceptable SImode operand for
825 most 3 address instructions. */
828 arith_operand (op, mode)
830 enum machine_mode mode;
832 return (register_operand (op, mode)
833 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
836 /* Return true if OP is a register, or is a CONST_INT that can fit in a
837 signed 11 bit immediate field. This is an acceptable SImode operand for
838 the movcc instructions. */
841 arith11_operand (op, mode)
843 enum machine_mode mode;
845 return (register_operand (op, mode)
846 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
849 /* Return true if OP is a register, or is a CONST_INT that can fit in a
850 signed 10 bit immediate field. This is an acceptable SImode operand for
851 the movrcc instructions. */
854 arith10_operand (op, mode)
856 enum machine_mode mode;
858 return (register_operand (op, mode)
859 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
862 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
863 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
865 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
866 can fit in a 13 bit immediate field. This is an acceptable DImode operand
867 for most 3 address instructions. */
870 arith_double_operand (op, mode)
872 enum machine_mode mode;
874 return (register_operand (op, mode)
875 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
877 && GET_CODE (op) == CONST_DOUBLE
878 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
879 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
881 && GET_CODE (op) == CONST_DOUBLE
882 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
883 && ((CONST_DOUBLE_HIGH (op) == -1
884 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
885 || (CONST_DOUBLE_HIGH (op) == 0
886 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
889 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
890 can fit in an 11 bit immediate field. This is an acceptable DImode
891 operand for the movcc instructions. */
892 /* ??? Replace with arith11_operand? */
895 arith11_double_operand (op, mode)
897 enum machine_mode mode;
899 return (register_operand (op, mode)
900 || (GET_CODE (op) == CONST_DOUBLE
901 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
902 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
903 && ((CONST_DOUBLE_HIGH (op) == -1
904 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
905 || (CONST_DOUBLE_HIGH (op) == 0
906 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
907 || (GET_CODE (op) == CONST_INT
908 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
909 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
912 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
913 can fit in an 10 bit immediate field. This is an acceptable DImode
914 operand for the movrcc instructions. */
915 /* ??? Replace with arith10_operand? */
918 arith10_double_operand (op, mode)
920 enum machine_mode mode;
922 return (register_operand (op, mode)
923 || (GET_CODE (op) == CONST_DOUBLE
924 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
925 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
926 && ((CONST_DOUBLE_HIGH (op) == -1
927 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
928 || (CONST_DOUBLE_HIGH (op) == 0
929 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
930 || (GET_CODE (op) == CONST_INT
931 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
932 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
935 /* Return truth value of whether OP is a integer which fits the
936 range constraining immediate operands in most three-address insns,
937 which have a 13 bit immediate field. */
942 enum machine_mode mode;
944 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
947 /* Recognize operand values for the umul instruction. That instruction sign
948 extends immediate values just like all other sparc instructions, but
949 interprets the extended result as an unsigned number. */
952 uns_small_int (op, mode)
954 enum machine_mode mode;
956 #if HOST_BITS_PER_WIDE_INT > 32
957 /* All allowed constants will fit a CONST_INT. */
958 return (GET_CODE (op) == CONST_INT
959 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
960 || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L)));
962 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
963 || (GET_CODE (op) == CONST_DOUBLE
964 && CONST_DOUBLE_HIGH (op) == 0
965 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
970 uns_arith_operand (op, mode)
972 enum machine_mode mode;
974 return register_operand (op, mode) || uns_small_int (op, mode);
977 /* Return truth value of statement that OP is a call-clobbered register. */
979 clobbered_register (op, mode)
981 enum machine_mode mode;
983 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
986 /* X and Y are two things to compare using CODE. Emit the compare insn and
987 return the rtx for the cc reg in the proper mode. */
990 gen_compare_reg (code, x, y)
994 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
997 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
998 fcc regs (cse can't tell they're really call clobbered regs and will
999 remove a duplicate comparison even if there is an intervening function
1000 call - it will then try to reload the cc reg via an int reg which is why
1001 we need the movcc patterns). It is possible to provide the movcc
1002 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1003 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1004 to tell cse that CCFPE mode registers (even pseudos) are call
1007 /* ??? This is an experiment. Rather than making changes to cse which may
1008 or may not be easy/clean, we do our own cse. This is possible because
1009 we will generate hard registers. Cse knows they're call clobbered (it
1010 doesn't know the same thing about pseudos). If we guess wrong, no big
1011 deal, but if we win, great! */
1013 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1014 #if 1 /* experiment */
1017 /* We cycle through the registers to ensure they're all exercised. */
1018 static int next_fcc_reg = 0;
1019 /* Previous x,y for each fcc reg. */
1020 static rtx prev_args[4][2];
1022 /* Scan prev_args for x,y. */
1023 for (reg = 0; reg < 4; reg++)
1024 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
1029 prev_args[reg][0] = x;
1030 prev_args[reg][1] = y;
1031 next_fcc_reg = (next_fcc_reg + 1) & 3;
1033 cc_reg = gen_rtx (REG, mode, reg + SPARC_FIRST_V9_FCC_REG);
1036 cc_reg = gen_reg_rtx (mode);
1037 #endif /* ! experiment */
1038 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1039 cc_reg = gen_rtx (REG, mode, SPARC_FCC_REG);
1041 cc_reg = gen_rtx (REG, mode, SPARC_ICC_REG);
1043 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
1044 gen_rtx (COMPARE, mode, x, y)));
1049 /* This function is used for v9 only.
1050 CODE is the code for an Scc's comparison.
1051 OPERANDS[0] is the target of the Scc insn.
1052 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1053 been generated yet).
1055 This function is needed to turn
1058 (gt (reg:CCX 100 %icc)
1062 (gt:DI (reg:CCX 100 %icc)
1065 IE: The instruction recognizer needs to see the mode of the comparison to
1066 find the right instruction. We could use "gt:DI" right in the
1067 define_expand, but leaving it out allows us to handle DI, SI, etc.
1069 We refer to the global sparc compare operands sparc_compare_op0 and
1070 sparc_compare_op1. */
1073 gen_v9_scc (compare_code, operands)
1074 enum rtx_code compare_code;
1075 register rtx *operands;
1080 && (GET_MODE (sparc_compare_op0) == DImode
1081 || GET_MODE (operands[0]) == DImode))
1084 /* Handle the case where operands[0] == sparc_compare_op0.
1085 We "early clobber" the result. */
1086 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
1088 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
1089 emit_move_insn (op0, sparc_compare_op0);
1092 op0 = sparc_compare_op0;
1093 /* For consistency in the following. */
1094 op1 = sparc_compare_op1;
1096 /* Try to use the movrCC insns. */
1098 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1099 && op1 == const0_rtx
1100 && v9_regcmp_p (compare_code))
1102 /* Special case for op0 != 0. This can be done with one instruction if
1103 operands[0] == sparc_compare_op0. We don't assume they are equal
1106 if (compare_code == NE
1107 && GET_MODE (operands[0]) == DImode
1108 && GET_MODE (op0) == DImode)
1110 emit_insn (gen_rtx (SET, VOIDmode, operands[0], op0));
1111 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1112 gen_rtx (IF_THEN_ELSE, DImode,
1113 gen_rtx (compare_code, DImode,
1120 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1121 if (GET_MODE (op0) != DImode)
1123 temp = gen_reg_rtx (DImode);
1124 convert_move (temp, op0, 0);
1128 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1129 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1130 gen_rtx (compare_code, DImode,
1138 operands[1] = gen_compare_reg (compare_code, op0, op1);
1140 switch (GET_MODE (operands[1]))
1150 emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx));
1151 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1152 gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]),
1153 gen_rtx (compare_code,
1154 GET_MODE (operands[1]),
1155 operands[1], const0_rtx),
1156 const1_rtx, operands[0])));
1161 /* Emit a conditional jump insn for the v9 architecture using comparison code
1162 CODE and jump target LABEL.
1163 This function exists to take advantage of the v9 brxx insns. */
1166 emit_v9_brxx_insn (code, op0, label)
1170 emit_jump_insn (gen_rtx (SET, VOIDmode,
1172 gen_rtx (IF_THEN_ELSE, VOIDmode,
1173 gen_rtx (code, GET_MODE (op0),
1175 gen_rtx (LABEL_REF, VOIDmode, label),
1179 /* Return nonzero if a return peephole merging return with
1180 setting of output register is ok. */
1182 leaf_return_peephole_ok ()
1184 return (actual_fsize == 0);
1187 /* Return nonzero if TRIAL can go into the function epilogue's
1188 delay slot. SLOT is the slot we are trying to fill. */
1191 eligible_for_epilogue_delay (trial, slot)
1200 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
1203 if (get_attr_length (trial) != 1)
1206 /* If %g0 is live, there are lots of things we can't handle.
1207 Rather than trying to find them all now, let's punt and only
1208 optimize things as necessary. */
1212 /* In the case of a true leaf function, anything can go into the delay slot.
1213 A delay slot only exists however if the frame size is zero, otherwise
1214 we will put an insn to adjust the stack after the return. */
1217 if (leaf_return_peephole_ok ())
1218 return ((get_attr_in_uncond_branch_delay (trial)
1219 == IN_BRANCH_DELAY_TRUE));
1223 /* If only trivial `restore' insns work, nothing can go in the
1225 else if (TARGET_BROKEN_SAVERESTORE)
1228 pat = PATTERN (trial);
1230 /* Otherwise, only operations which can be done in tandem with
1231 a `restore' insn can go into the delay slot. */
1232 if (GET_CODE (SET_DEST (pat)) != REG
1233 || REGNO (SET_DEST (pat)) >= 32
1234 || REGNO (SET_DEST (pat)) < 24)
1237 /* The set of insns matched here must agree precisely with the set of
1238 patterns paired with a RETURN in sparc.md. */
1240 src = SET_SRC (pat);
1242 /* This matches "*return_[qhs]". */
1243 if (arith_operand (src, GET_MODE (src)))
1244 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
1246 /* This matches "*return_di". */
1247 else if (arith_double_operand (src, GET_MODE (src)))
1248 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
1250 /* This matches "*return_sf_no_fpu". */
1251 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
1252 && register_operand (src, SFmode))
1255 /* This matches "*return_addsi". */
1256 else if (GET_CODE (src) == PLUS
1257 && arith_operand (XEXP (src, 0), SImode)
1258 && arith_operand (XEXP (src, 1), SImode)
1259 && (register_operand (XEXP (src, 0), SImode)
1260 || register_operand (XEXP (src, 1), SImode)))
1263 /* This matches "*return_adddi". */
1264 else if (GET_CODE (src) == PLUS
1265 && arith_double_operand (XEXP (src, 0), DImode)
1266 && arith_double_operand (XEXP (src, 1), DImode)
1267 && (register_operand (XEXP (src, 0), DImode)
1268 || register_operand (XEXP (src, 1), DImode)))
1271 /* This matches "*return_subsi". */
1272 else if (GET_CODE (src) == MINUS
1273 && register_operand (XEXP (src, 0), SImode)
1274 && small_int (XEXP (src, 1), VOIDmode)
1275 && INTVAL (XEXP (src, 1)) != -4096)
1282 short_branch (uid1, uid2)
1285 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
1286 if (delta + 1024 < 2048)
1288 /* warning ("long branch, distance %d", delta); */
1292 /* Return non-zero if REG is not used after INSN.
1293 We assume REG is a reload reg, and therefore does
1294 not live past labels or calls or jumps. */
1296 reg_unused_after (reg, insn)
1300 enum rtx_code code, prev_code = UNKNOWN;
1302 while (insn = NEXT_INSN (insn))
1304 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
1307 code = GET_CODE (insn);
1308 if (GET_CODE (insn) == CODE_LABEL)
1311 if (GET_RTX_CLASS (code) == 'i')
1313 rtx set = single_set (insn);
1314 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
1317 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1319 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
1327 /* The rtx for the global offset table which is a special form
1328 that *is* a position independent symbolic constant. */
1329 static rtx pic_pc_rtx;
1331 /* Ensure that we are not using patterns that are not OK with PIC. */
1340 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
1341 || (GET_CODE (recog_operand[i]) == CONST
1342 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
1350 /* Return true if X is an address which needs a temporary register when
1351 reloaded while generating PIC code. */
1354 pic_address_needs_scratch (x)
1357 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1358 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1359 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1360 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1361 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1367 /* Legitimize PIC addresses. If the address is already position-independent,
1368 we return ORIG. Newly generated position-independent addresses go into a
1369 reg. This is REG if non zero, otherwise we allocate register(s) as
1373 legitimize_pic_address (orig, mode, reg)
1375 enum machine_mode mode;
1378 if (GET_CODE (orig) == SYMBOL_REF)
1380 rtx pic_ref, address;
1385 if (reload_in_progress || reload_completed)
1388 reg = gen_reg_rtx (Pmode);
1393 /* If not during reload, allocate another temp reg here for loading
1394 in the address, so that these instructions can be optimized
1396 rtx temp_reg = ((reload_in_progress || reload_completed)
1397 ? reg : gen_reg_rtx (Pmode));
1399 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1400 won't get confused into thinking that these two instructions
1401 are loading in the true address of the symbol. If in the
1402 future a PIC rtx exists, that should be used instead. */
1403 emit_insn (gen_pic_sethi_si (temp_reg, orig));
1404 emit_insn (gen_pic_lo_sum_si (temp_reg, temp_reg, orig));
1411 pic_ref = gen_rtx (MEM, Pmode,
1412 gen_rtx (PLUS, Pmode,
1413 pic_offset_table_rtx, address));
1414 current_function_uses_pic_offset_table = 1;
1415 RTX_UNCHANGING_P (pic_ref) = 1;
1416 insn = emit_move_insn (reg, pic_ref);
1417 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1419 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1423 else if (GET_CODE (orig) == CONST)
1427 if (GET_CODE (XEXP (orig, 0)) == PLUS
1428 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1433 if (reload_in_progress || reload_completed)
1436 reg = gen_reg_rtx (Pmode);
1439 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1441 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1442 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1443 base == reg ? 0 : reg);
1448 if (GET_CODE (offset) == CONST_INT)
1450 if (SMALL_INT (offset))
1451 return plus_constant_for_output (base, INTVAL (offset));
1452 else if (! reload_in_progress && ! reload_completed)
1453 offset = force_reg (Pmode, offset);
1455 /* If we reach here, then something is seriously wrong. */
1458 return gen_rtx (PLUS, Pmode, base, offset);
1460 else if (GET_CODE (orig) == LABEL_REF)
1461 /* ??? Why do we do this? */
1462 current_function_uses_pic_offset_table = 1;
1467 /* Set up PIC-specific rtl. This should not cause any insns
1475 /* Emit special PIC prologues and epilogues. */
1480 /* The table we use to reference PIC data. */
1481 rtx global_offset_table;
1482 /* Labels to get the PC in the prologue of this function. */
1485 int orig_flag_pic = flag_pic;
1487 if (current_function_uses_pic_offset_table == 0)
1497 l1 = gen_label_rtx ();
1499 /* Initialize every time through, since we can't easily
1500 know this to be permanent. */
1501 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1502 pic_pc_rtx = gen_rtx (CONST, Pmode,
1503 gen_rtx (MINUS, Pmode,
1504 global_offset_table,
1505 gen_rtx (CONST, Pmode,
1506 gen_rtx (MINUS, Pmode,
1507 gen_rtx (LABEL_REF, VOIDmode, l1),
1510 /* sparc64: the RDPC instruction doesn't pair, and puts 4 bubbles in the
1511 pipe to boot. So don't use it here, especially when we're
1512 doing a save anyway because of %l7. */
1514 l2 = gen_label_rtx ();
1517 /* Iff we are doing delay branch optimization, slot the sethi up
1518 here so that it will fill the delay slot of the call. */
1519 if (flag_delayed_branch)
1520 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1521 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1523 /* Note that we pun calls and jumps here! */
1524 emit_jump_insn (gen_get_pc_via_call (l2, l1));
1528 if (!flag_delayed_branch)
1529 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
1530 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
1532 emit_insn (gen_rtx (SET, VOIDmode,
1533 pic_offset_table_rtx,
1534 gen_rtx (LO_SUM, Pmode,
1535 pic_offset_table_rtx, pic_pc_rtx)));
1536 emit_insn (gen_rtx (SET, VOIDmode,
1537 pic_offset_table_rtx,
1538 gen_rtx (PLUS, Pmode,
1539 pic_offset_table_rtx,
1540 gen_rtx (REG, Pmode, 15))));
1542 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1543 LABEL_PRESERVE_P (l1) = 1;
1544 LABEL_PRESERVE_P (l2) = 1;
1546 flag_pic = orig_flag_pic;
1548 seq = gen_sequence ();
1550 emit_insn_after (seq, get_insns ());
1552 /* Need to emit this whether or not we obey regdecls,
1553 since setjmp/longjmp can cause life info to screw up. */
1554 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1557 /* Emit insns to move operands[1] into operands[0].
1559 Return 1 if we have written out everything that needs to be done to
1560 do the move. Otherwise, return 0 and the caller will emit the move
1564 emit_move_sequence (operands, mode)
1566 enum machine_mode mode;
1568 register rtx operand0 = operands[0];
1569 register rtx operand1 = operands[1];
1571 if (CONSTANT_P (operand1) && flag_pic
1572 && pic_address_needs_scratch (operand1))
1573 operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0);
1575 /* Handle most common case first: storing into a register. */
1576 if (register_operand (operand0, mode))
1578 if (register_operand (operand1, mode)
1579 || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
1580 || (GET_CODE (operand1) == CONST_DOUBLE
1581 && arith_double_operand (operand1, DImode))
1582 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode)
1583 /* Only `general_operands' can come here, so MEM is ok. */
1584 || GET_CODE (operand1) == MEM)
1586 /* Run this case quickly. */
1587 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1591 else if (GET_CODE (operand0) == MEM)
1593 if (register_operand (operand1, mode)
1594 || (operand1 == const0_rtx && ! TARGET_LIVE_G0))
1596 /* Run this case quickly. */
1597 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
1600 if (! reload_in_progress)
1602 operands[0] = validize_mem (operand0);
1603 operands[1] = operand1 = force_reg (mode, operand1);
1607 if (GET_CODE (operand1) == LABEL_REF
1608 && mode == SImode && flag_pic)
1612 emit_insn (gen_move_pic_label_si (operand0, operand1));
1615 /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way,
1616 so always use special code. */
1617 else if (GET_CODE (operand1) == LABEL_REF
1620 if (! TARGET_ARCH64)
1622 emit_insn (gen_move_label_di (operand0, operand1));
1625 /* DImode HIGH values in sparc64 need a clobber added. */
1626 else if (TARGET_ARCH64
1627 && GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)
1629 emit_insn (gen_sethi_di_sp64 (operand0, XEXP (operand1, 0)));
1632 /* Simplify the source if we need to. */
1633 else if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1635 if (flag_pic && symbolic_operand (operand1, mode))
1637 rtx temp_reg = reload_in_progress ? operand0 : 0;
1639 operands[1] = legitimize_pic_address (operand1, mode, temp_reg);
1641 else if (GET_CODE (operand1) == CONST_INT
1642 ? (! SMALL_INT (operand1)
1643 && ! SPARC_SETHI_P (INTVAL (operand1)))
1644 : GET_CODE (operand1) == CONST_DOUBLE
1645 ? ! arith_double_operand (operand1, DImode)
1648 /* For DImode values, temp must be operand0 because of the way
1649 HI and LO_SUM work. The LO_SUM operator only copies half of
1650 the LSW from the dest of the HI operator. If the LO_SUM dest is
1651 not the same as the HI dest, then the MSW of the LO_SUM dest will
1654 ??? The real problem here is that the ...(HI:DImode pattern emits
1655 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1656 one instruction. This fails, because the compiler assumes that
1657 LO_SUM copies all bits of the first operand to its dest. Better
1658 would be to have the HI pattern emit one instruction and the
1659 LO_SUM pattern multiple instructions. Even better would be
1660 to use four rtl insns. */
1661 rtx temp = ((reload_in_progress || mode == DImode)
1662 ? operand0 : gen_reg_rtx (mode));
1664 if (TARGET_ARCH64 && mode == DImode)
1665 emit_insn (gen_sethi_di_sp64 (temp, operand1));
1667 emit_insn (gen_rtx (SET, VOIDmode, temp,
1668 gen_rtx (HIGH, mode, operand1)));
1670 if (GET_CODE (operand1) == CONST_INT)
1671 operand1 = GEN_INT (INTVAL (operand1) & 0xffffffff);
1672 else if (GET_CODE (operand1) == CONST_DOUBLE)
1673 operand1 = GEN_INT (CONST_DOUBLE_LOW (operand1) & 0xffffffff);
1674 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
1678 /* Now have insn-emit do whatever it normally does. */
1682 /* Return the best assembler insn template
1683 for moving operands[1] into operands[0] as a 4 byte quantity.
1685 This isn't intended to be very smart. It is up to the caller to
1686 choose the best way to do things.
1688 Note that OPERANDS may be modified to suit the returned string. */
1691 singlemove_string (operands)
1694 if (GET_CODE (operands[0]) == MEM)
1696 if (GET_CODE (operands[1]) != MEM)
1701 else if (GET_CODE (operands[1]) == MEM)
1703 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1708 /* Must be SFmode, otherwise this doesn't make sense. */
1709 if (GET_MODE (operands[1]) != SFmode)
1712 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1713 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1714 operands[1] = GEN_INT (i);
1716 if (CONST_OK_FOR_LETTER_P (i, 'I'))
1718 else if ((i & 0x000003FF) != 0)
1719 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1721 return "sethi %%hi(%a1),%0";
1723 else if (GET_CODE (operands[1]) == CONST_INT
1724 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
1726 HOST_WIDE_INT i = INTVAL (operands[1]);
1728 /* If all low order 10 bits are clear, then we only need a single
1729 sethi insn to load the constant. */
1730 /* FIXME: Use SETHI_P. */
1731 if ((i & 0x000003FF) != 0)
1732 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1734 return "sethi %%hi(%a1),%0";
1736 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1740 /* Return the best assembler insn template
1741 for moving operands[1] into operands[0] as an 8 byte quantity.
1743 This isn't intended to be very smart. It is up to the caller to
1744 choose the best way to do things.
1746 Note that OPERANDS may be modified to suit the returned string. */
1749 doublemove_string (operands)
1752 rtx op0 = operands[0], op1 = operands[1];
1754 if (GET_CODE (op0) == MEM)
1756 if (GET_CODE (op1) == REG)
1760 return TARGET_ARCH64 ? "stx %1,%0" : "std %1,%0";
1763 && (op1 == const0_rtx
1764 || (GET_MODE (op1) != VOIDmode
1765 && op1 == CONST0_RTX (GET_MODE (op1)))))
1766 return "stx %r1,%0";
1769 else if (GET_CODE (op1) == MEM)
1771 if (GET_CODE (op0) != REG)
1775 return TARGET_ARCH64 ? "ldx %1,%0" : "ldd %1,%0";
1777 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1779 /* ??? Unfinished, and maybe not needed. */
1782 else if (GET_CODE (operands[1]) == CONST_INT
1783 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
1785 /* ??? Unfinished, and maybe not needed. */
1788 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1792 /* Return non-zero if it is OK to assume that the given memory operand is
1793 aligned at least to a 8-byte boundary. This should only be called
1794 for memory accesses whose size is 8 bytes or larger. */
1802 register rtx offset;
1804 if (GET_CODE (mem) != MEM)
1805 return 0; /* It's gotta be a MEM! */
1807 addr = XEXP (mem, 0);
1809 /* Now that all misaligned double parms are copied on function entry,
1810 we can assume any 64-bit object is 64-bit aligned except those which
1811 are at unaligned offsets from the stack or frame pointer. If the
1812 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1815 /* See what register we use in the address. */
1817 if (GET_CODE (addr) == PLUS)
1819 if (GET_CODE (XEXP (addr, 0)) == REG
1820 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
1822 base = XEXP (addr, 0);
1823 offset = XEXP (addr, 1);
1826 else if (GET_CODE (addr) == REG)
1829 offset = const0_rtx;
1832 /* If it's the stack or frame pointer, check offset alignment.
1833 We can have improper alignment in the function entry code. */
1835 && (REGNO (base) == FRAME_POINTER_REGNUM
1836 || REGNO (base) == STACK_POINTER_REGNUM))
1838 if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0)
1841 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1842 is true, in which case we can only assume that an access is aligned if
1843 it is to a constant address, or the address involves a LO_SUM.
1845 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1846 That assumption was deleted so that gcc generated code can be used with
1847 memory allocators that only guarantee 4 byte alignment. */
1848 else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr)
1849 || GET_CODE (addr) == LO_SUM)
1852 /* An obviously unaligned address. */
1856 enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP };
1858 /* Output assembler code to perform a doubleword move insn
1859 with operands OPERANDS. This is very similar to the following
1860 output_move_quad function. */
1863 output_move_double (operands)
1866 register rtx op0 = operands[0];
1867 register rtx op1 = operands[1];
1868 register enum optype optype0;
1869 register enum optype optype1;
1873 int highest_first = 0;
1874 int no_addreg1_decrement = 0;
1876 /* First classify both operands. */
1880 else if (offsettable_memref_p (op0))
1882 else if (GET_CODE (op0) == MEM)
1889 else if (CONSTANT_P (op1))
1891 else if (offsettable_memref_p (op1))
1893 else if (GET_CODE (op1) == MEM)
1898 /* Check for the cases that the operand constraints are not
1899 supposed to allow to happen. Abort if we get one,
1900 because generating code for these cases is painful. */
1902 if (optype0 == RNDOP || optype1 == RNDOP
1903 || (optype0 == MEM && optype1 == MEM))
1906 /* If an operand is an unoffsettable memory ref, find a register
1907 we can increment temporarily to make it refer to the second word. */
1909 if (optype0 == MEMOP)
1910 addreg0 = find_addr_reg (XEXP (op0, 0));
1912 if (optype1 == MEMOP)
1913 addreg1 = find_addr_reg (XEXP (op1, 0));
1915 /* Ok, we can do one word at a time.
1916 Set up in LATEHALF the operands to use for the
1917 high-numbered (least significant) word and in some cases alter the
1918 operands in OPERANDS to be suitable for the low-numbered word. */
1920 if (optype0 == REGOP)
1921 latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1922 else if (optype0 == OFFSOP)
1923 latehalf[0] = adj_offsettable_operand (op0, 4);
1927 if (optype1 == REGOP)
1928 latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1929 else if (optype1 == OFFSOP)
1930 latehalf[1] = adj_offsettable_operand (op1, 4);
1931 else if (optype1 == CNSTOP)
1935 if (arith_double_operand (op1, DImode))
1937 operands[1] = gen_rtx (CONST_INT, VOIDmode,
1938 CONST_DOUBLE_LOW (op1));
1943 /* The only way to handle CONST_DOUBLEs or other 64 bit
1944 constants here is to use a temporary, such as is done
1945 for the V9 DImode sethi insn pattern. This is not
1946 a practical solution, so abort if we reach here.
1947 The md file should always force such constants to
1953 split_double (op1, &operands[1], &latehalf[1]);
1958 /* Easy case: try moving both words at once. Check for moving between
1959 an even/odd register pair and a memory location. */
1960 if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP
1961 && (TARGET_ARCH64 || (REGNO (op0) & 1) == 0))
1962 || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP
1963 && (TARGET_ARCH64 || (REGNO (op1) & 1) == 0)))
1965 register rtx mem,reg;
1967 if (optype0 == REGOP)
1968 mem = op1, reg = op0;
1970 mem = op0, reg = op1;
1972 /* In v9, ldd can be used for word aligned addresses, so technically
1973 some of this logic is unneeded. We still avoid ldd if the address
1974 is obviously unaligned though. */
1976 if (mem_aligned_8 (mem)
1977 /* If this is a floating point register higher than %f31,
1978 then we *must* use an aligned load, since `ld' will not accept
1979 the register number. */
1980 || (TARGET_V9 && REGNO (reg) >= 64))
1982 if (FP_REG_P (reg) || ! TARGET_ARCH64)
1983 return (mem == op1 ? "ldd %1,%0" : "std %1,%0");
1985 return (mem == op1 ? "ldx %1,%0" : "stx %1,%0");
1991 if (optype0 == REGOP && optype1 == REGOP)
1994 return "fmovd %1,%0";
2000 /* If the first move would clobber the source of the second one,
2001 do them in the other order. */
2003 /* Overlapping registers. */
2004 if (optype0 == REGOP && optype1 == REGOP
2005 && REGNO (op0) == REGNO (latehalf[1]))
2008 output_asm_insn (singlemove_string (latehalf), latehalf);
2009 /* Do low-numbered word. */
2010 return singlemove_string (operands);
2012 /* Loading into a register which overlaps a register used in the address. */
2013 else if (optype0 == REGOP && optype1 != REGOP
2014 && reg_overlap_mentioned_p (op0, op1))
2016 /* If both halves of dest are used in the src memory address,
2017 add the two regs and put them in the low reg (op0).
2018 Then it works to load latehalf first. */
2019 if (reg_mentioned_p (op0, XEXP (op1, 0))
2020 && reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
2023 xops[0] = latehalf[0];
2025 output_asm_insn ("add %1,%0,%1", xops);
2026 operands[1] = gen_rtx (MEM, DImode, op0);
2027 latehalf[1] = adj_offsettable_operand (operands[1], 4);
2031 /* Only one register in the dest is used in the src memory address,
2032 and this is the first register of the dest, so we want to do
2033 the late half first here also. */
2034 else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
2036 /* Only one register in the dest is used in the src memory address,
2037 and this is the second register of the dest, so we want to do
2038 the late half last. If addreg1 is set, and addreg1 is the same
2039 register as latehalf, then we must suppress the trailing decrement,
2040 because it would clobber the value just loaded. */
2041 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
2042 no_addreg1_decrement = 1;
2045 /* Normal case: do the two words, low-numbered first.
2046 Overlap case (highest_first set): do high-numbered word first. */
2048 if (! highest_first)
2049 output_asm_insn (singlemove_string (operands), operands);
2051 /* Make any unoffsettable addresses point at high-numbered word. */
2053 output_asm_insn ("add %0,0x4,%0", &addreg0);
2055 output_asm_insn ("add %0,0x4,%0", &addreg1);
2058 output_asm_insn (singlemove_string (latehalf), latehalf);
2060 /* Undo the adds we just did. */
2062 output_asm_insn ("add %0,-0x4,%0", &addreg0);
2063 if (addreg1 && ! no_addreg1_decrement)
2064 output_asm_insn ("add %0,-0x4,%0", &addreg1);
2067 output_asm_insn (singlemove_string (operands), operands);
2072 /* Output assembler code to perform a quadword move insn
2073 with operands OPERANDS. This is very similar to the preceding
2074 output_move_double function. */
2077 output_move_quad (operands)
2080 register rtx op0 = operands[0];
2081 register rtx op1 = operands[1];
2082 register enum optype optype0;
2083 register enum optype optype1;
2088 /* First classify both operands. */
2092 else if (offsettable_memref_p (op0))
2094 else if (GET_CODE (op0) == MEM)
2101 else if (CONSTANT_P (op1))
2103 else if (offsettable_memref_p (op1))
2105 else if (GET_CODE (op1) == MEM)
2110 /* Check for the cases that the operand constraints are not
2111 supposed to allow to happen. Abort if we get one,
2112 because generating code for these cases is painful. */
2114 if (optype0 == RNDOP || optype1 == RNDOP
2115 || (optype0 == MEM && optype1 == MEM))
2118 /* If an operand is an unoffsettable memory ref, find a register
2119 we can increment temporarily to make it refer to the later words. */
2121 if (optype0 == MEMOP)
2122 addreg0 = find_addr_reg (XEXP (op0, 0));
2124 if (optype1 == MEMOP)
2125 addreg1 = find_addr_reg (XEXP (op1, 0));
2127 /* Ok, we can do one word at a time.
2128 Set up in wordpart the operands to use for each word of the arguments. */
2130 if (optype0 == REGOP)
2132 wordpart[0][0] = gen_rtx (REG, word_mode, REGNO (op0) + 0);
2133 wordpart[1][0] = gen_rtx (REG, word_mode, REGNO (op0) + 1);
2136 wordpart[2][0] = gen_rtx (REG, word_mode, REGNO (op0) + 2);
2137 wordpart[3][0] = gen_rtx (REG, word_mode, REGNO (op0) + 3);
2140 else if (optype0 == OFFSOP)
2142 wordpart[0][0] = adj_offsettable_operand (op0, 0);
2145 wordpart[1][0] = adj_offsettable_operand (op0, 4);
2146 wordpart[2][0] = adj_offsettable_operand (op0, 8);
2147 wordpart[3][0] = adj_offsettable_operand (op0, 12);
2150 wordpart[1][0] = adj_offsettable_operand (op0, 8);
2154 wordpart[0][0] = op0;
2155 wordpart[1][0] = op0;
2156 wordpart[2][0] = op0;
2157 wordpart[3][0] = op0;
2160 if (optype1 == REGOP)
2162 wordpart[0][1] = gen_rtx (REG, word_mode, REGNO (op1) + 0);
2163 wordpart[1][1] = gen_rtx (REG, word_mode, REGNO (op1) + 1);
2166 wordpart[2][1] = gen_rtx (REG, word_mode, REGNO (op1) + 2);
2167 wordpart[3][1] = gen_rtx (REG, word_mode, REGNO (op1) + 3);
2170 else if (optype1 == OFFSOP)
2172 wordpart[0][1] = adj_offsettable_operand (op1, 0);
2175 wordpart[1][1] = adj_offsettable_operand (op1, 4);
2176 wordpart[2][1] = adj_offsettable_operand (op1, 8);
2177 wordpart[3][1] = adj_offsettable_operand (op1, 12);
2180 wordpart[1][1] = adj_offsettable_operand (op1, 8);
2182 else if (optype1 == CNSTOP)
2187 /* This only works for TFmode floating point constants. */
2188 if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode)
2191 REAL_VALUE_FROM_CONST_DOUBLE (r, op1);
2192 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2194 wordpart[0][1] = GEN_INT (l[0]);
2195 wordpart[1][1] = GEN_INT (l[1]);
2196 wordpart[2][1] = GEN_INT (l[2]);
2197 wordpart[3][1] = GEN_INT (l[3]);
2201 wordpart[0][1] = op1;
2202 wordpart[1][1] = op1;
2203 wordpart[2][1] = op1;
2204 wordpart[3][1] = op1;
2207 /* Easy case: try moving the quad as two pairs. Check for moving between
2208 an even/odd register pair and a memory location.
2209 Also handle new v9 fp regs here. */
2210 /* ??? Should also handle the case of non-offsettable addresses here.
2211 We can at least do the first pair as a ldd/std, and then do the third
2212 and fourth words individually. */
2213 if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0)
2214 || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0))
2218 if (optype0 == REGOP)
2219 mem = op1, reg = op0;
2221 mem = op0, reg = op1;
2223 if (mem_aligned_8 (mem)
2224 /* If this is a floating point register higher than %f31,
2225 then we *must* use an aligned load, since `ld' will not accept
2226 the register number. */
2227 || (TARGET_V9 && REGNO (reg) >= SPARC_FIRST_V9_FP_REG))
2229 if (TARGET_V9 && FP_REG_P (reg) && TARGET_HARD_QUAD)
2231 if ((REGNO (reg) & 3) != 0)
2233 /* ??? Can `mem' have an inappropriate alignment here? */
2234 return (mem == op1 ? "ldq %1,%0" : "stq %1,%0");
2236 operands[2] = adj_offsettable_operand (mem, 8);
2237 /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */
2239 return TARGET_ARCH64 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
2241 return TARGET_ARCH64 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
2245 /* If the first move would clobber the source of the second one,
2246 do them in the other order. */
2248 /* Overlapping registers? */
2251 if (optype0 == REGOP && optype1 == REGOP
2252 && (REGNO (op0) == REGNO (wordpart[1][3])
2253 || REGNO (op0) == REGNO (wordpart[1][2])
2254 || REGNO (op0) == REGNO (wordpart[1][1])))
2256 /* Do fourth word. */
2257 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2258 /* Do the third word. */
2259 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2260 /* Do the second word. */
2261 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2262 /* Do lowest-numbered word. */
2263 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
2267 else /* TARGET_ARCH64 */
2269 if (optype0 == REGOP && optype1 == REGOP
2270 && REGNO (op0) == REGNO (wordpart[1][1]))
2272 output_asm_insn ("mov %1,%0", wordpart[1]);
2273 output_asm_insn ("mov %1,%0", wordpart[0]);
2278 /* Loading into a register which overlaps a register used in the address. */
2279 if (optype0 == REGOP && optype1 != REGOP
2280 && reg_overlap_mentioned_p (op0, op1))
2282 /* ??? Not implemented yet. This is a bit complicated, because we
2283 must load which ever part overlaps the address last. If the address
2284 is a double-reg address, then there are two parts which need to
2285 be done last, which is impossible. We would need a scratch register
2290 /* Normal case: move the words in lowest to highest address order. */
2294 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
2296 /* Make any unoffsettable addresses point at the second word. */
2298 output_asm_insn ("add %0,0x4,%0", &addreg0);
2300 output_asm_insn ("add %0,0x4,%0", &addreg1);
2302 /* Do the second word. */
2303 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
2305 /* Make any unoffsettable addresses point at the third word. */
2307 output_asm_insn ("add %0,0x4,%0", &addreg0);
2309 output_asm_insn ("add %0,0x4,%0", &addreg1);
2311 /* Do the third word. */
2312 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
2314 /* Make any unoffsettable addresses point at the fourth word. */
2316 output_asm_insn ("add %0,0x4,%0", &addreg0);
2318 output_asm_insn ("add %0,0x4,%0", &addreg1);
2320 /* Do the fourth word. */
2321 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
2323 /* Undo the adds we just did. */
2325 output_asm_insn ("add %0,-0xc,%0", &addreg0);
2327 output_asm_insn ("add %0,-0xc,%0", &addreg1);
2329 else /* TARGET_ARCH64 */
2331 output_asm_insn (doublemove_string (wordpart[0]), wordpart[0]);
2333 /* Make any unoffsettable addresses point at the second word. */
2335 output_asm_insn ("add %0,0x8,%0", &addreg0);
2337 output_asm_insn ("add %0,0x8,%0", &addreg1);
2339 /* Do the second word. */
2340 output_asm_insn (doublemove_string (wordpart[1]), wordpart[1]);
2342 /* Undo the adds we just did. */
2344 output_asm_insn ("add %0,-0x8,%0", &addreg0);
2346 output_asm_insn ("add %0,-0x8,%0", &addreg1);
2352 /* Output assembler code to perform a doubleword move insn with operands
2353 OPERANDS, one of which must be a floating point register. */
2356 output_fp_move_double (operands)
2359 if (FP_REG_P (operands[0]))
2361 if (FP_REG_P (operands[1]))
2364 return "fmovd %1,%0";
2366 return "fmovs %1,%0\n\tfmovs %R1,%R0";
2368 else if (GET_CODE (operands[1]) == REG)
2371 return output_move_double (operands);
2373 else if (FP_REG_P (operands[1]))
2375 if (GET_CODE (operands[0]) == REG)
2378 return output_move_double (operands);
2383 /* Output assembler code to perform a quadword move insn with operands
2384 OPERANDS, one of which must be a floating point register. */
2387 output_fp_move_quad (operands)
2390 register rtx op0 = operands[0];
2391 register rtx op1 = operands[1];
2397 if (TARGET_V9 && TARGET_HARD_QUAD)
2398 return "fmovq %1,%0";
2400 return "fmovd %1,%0\n\tfmovd %S1,%S0";
2402 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2404 else if (GET_CODE (op1) == REG)
2407 return output_move_quad (operands);
2409 else if (FP_REG_P (op1))
2411 if (GET_CODE (op0) == REG)
2414 return output_move_quad (operands);
2420 /* Return a REG that occurs in ADDR with coefficient 1.
2421 ADDR can be effectively incremented by incrementing REG. */
2424 find_addr_reg (addr)
2427 while (GET_CODE (addr) == PLUS)
2429 /* We absolutely can not fudge the frame pointer here, because the
2430 frame pointer must always be 8 byte aligned. It also confuses
2432 if (GET_CODE (XEXP (addr, 0)) == REG
2433 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
2434 addr = XEXP (addr, 0);
2435 else if (GET_CODE (XEXP (addr, 1)) == REG
2436 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
2437 addr = XEXP (addr, 1);
2438 else if (CONSTANT_P (XEXP (addr, 0)))
2439 addr = XEXP (addr, 1);
2440 else if (CONSTANT_P (XEXP (addr, 1)))
2441 addr = XEXP (addr, 0);
2445 if (GET_CODE (addr) == REG)
2450 #if 0 /* not currently used */
2453 output_sized_memop (opname, mode, signedp)
2455 enum machine_mode mode;
2458 static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" };
2459 static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" };
2460 static char *st_size_suffix[] = { "b", "h", "", "?", "d" };
2461 char **opnametab, *modename;
2463 if (opname[0] == 'l')
2465 opnametab = ld_size_suffix_s;
2467 opnametab = ld_size_suffix_u;
2469 opnametab = st_size_suffix;
2470 modename = opnametab[GET_MODE_SIZE (mode) >> 1];
2472 fprintf (asm_out_file, "\t%s%s", opname, modename);
2476 output_move_with_extension (operands)
2479 if (GET_MODE (operands[2]) == HImode)
2480 output_asm_insn ("sll %2,0x10,%0", operands);
2481 else if (GET_MODE (operands[2]) == QImode)
2482 output_asm_insn ("sll %2,0x18,%0", operands);
2486 #endif /* not currently used */
2489 /* ??? These are only used by the movstrsi pattern, but we get better code
2490 in general without that, because emit_block_move can do just as good a
2491 job as this function does when alignment and size are known. When they
2492 aren't known, a call to strcpy may be faster anyways, because it is
2493 likely to be carefully crafted assembly language code, and below we just
2494 do a byte-wise copy.
2496 Also, emit_block_move expands into multiple read/write RTL insns, which
2497 can then be optimized, whereas our movstrsi pattern can not be optimized
2500 /* Load the address specified by OPERANDS[3] into the register
2501 specified by OPERANDS[0].
2503 OPERANDS[3] may be the result of a sum, hence it could either be:
2508 (3) REG + REG + CONST_INT
2509 (4) REG + REG (special case of 3).
2511 Note that (3) is not a legitimate address.
2512 All cases are handled here. */
2515 output_load_address (operands)
2520 if (CONSTANT_P (operands[3]))
2522 output_asm_insn ("set %3,%0", operands);
2526 if (REG_P (operands[3]))
2528 if (REGNO (operands[0]) != REGNO (operands[3]))
2529 output_asm_insn ("mov %3,%0", operands);
2533 if (GET_CODE (operands[3]) != PLUS)
2536 base = XEXP (operands[3], 0);
2537 offset = XEXP (operands[3], 1);
2539 if (GET_CODE (base) == CONST_INT)
2546 if (GET_CODE (offset) != CONST_INT)
2548 /* Operand is (PLUS (REG) (REG)). */
2550 offset = const0_rtx;
2556 operands[7] = offset;
2557 if (SMALL_INT (offset))
2558 output_asm_insn ("add %6,%7,%0", operands);
2560 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands);
2562 else if (GET_CODE (base) == PLUS)
2564 operands[6] = XEXP (base, 0);
2565 operands[7] = XEXP (base, 1);
2566 operands[8] = offset;
2568 if (SMALL_INT (offset))
2569 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands);
2571 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands);
2577 /* Output code to place a size count SIZE in register REG.
2578 ALIGN is the size of the unit of transfer.
2580 Because block moves are pipelined, we don't include the
2581 first element in the transfer of SIZE to REG. */
2584 output_size_for_block_move (size, reg, align)
2591 xoperands[1] = size;
2592 xoperands[2] = align;
2593 if (GET_CODE (size) == REG)
2594 output_asm_insn ("sub %1,%2,%0", xoperands);
2598 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
2599 output_asm_insn ("set %1,%0", xoperands);
2603 /* Emit code to perform a block move.
2605 OPERANDS[0] is the destination.
2606 OPERANDS[1] is the source.
2607 OPERANDS[2] is the size.
2608 OPERANDS[3] is the alignment safe to use.
2609 OPERANDS[4] is a register we can safely clobber as a temp. */
2612 output_block_move (operands)
2615 /* A vector for our computed operands. Note that load_output_address
2616 makes use of (and can clobber) up to the 8th element of this vector. */
2619 static int movstrsi_label = 0;
2621 rtx temp1 = operands[4];
2622 rtx sizertx = operands[2];
2623 rtx alignrtx = operands[3];
2624 int align = INTVAL (alignrtx);
2625 char label3[30], label5[30];
2627 xoperands[0] = operands[0];
2628 xoperands[1] = operands[1];
2629 xoperands[2] = temp1;
2631 /* We can't move more than this many bytes at a time because we have only
2632 one register, %g1, to move them through. */
2633 if (align > UNITS_PER_WORD)
2635 align = UNITS_PER_WORD;
2636 alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD);
2639 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2640 reasonable here. (Actually will emit a maximum of 18 inline insns for
2641 the case of size == 31 and align == 4). */
2643 if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8
2644 && memory_address_p (QImode, plus_constant_for_output (xoperands[0],
2646 && memory_address_p (QImode, plus_constant_for_output (xoperands[1],
2649 int size = INTVAL (sizertx);
2652 /* We will store different integers into this particular RTX. */
2653 xoperands[2] = rtx_alloc (CONST_INT);
2654 PUT_MODE (xoperands[2], VOIDmode);
2656 /* This case is currently not handled. Abort instead of generating
2658 if (align > UNITS_PER_WORD)
2661 if (TARGET_ARCH64 && align >= 8)
2663 for (i = (size >> 3) - 1; i >= 0; i--)
2665 INTVAL (xoperands[2]) = (i << 3) + offset;
2666 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2669 offset += (size & ~0x7);
2677 for (i = (size >> 2) - 1; i >= 0; i--)
2679 INTVAL (xoperands[2]) = (i << 2) + offset;
2680 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2683 offset += (size & ~0x3);
2691 for (i = (size >> 1) - 1; i >= 0; i--)
2693 INTVAL (xoperands[2]) = (i << 1) + offset;
2694 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2697 offset += (size & ~0x1);
2705 for (i = size - 1; i >= 0; i--)
2707 INTVAL (xoperands[2]) = i + offset;
2708 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2714 /* We should never reach here. */
2718 /* If the size isn't known to be a multiple of the alignment,
2719 we have to do it in smaller pieces. If we could determine that
2720 the size was a multiple of 2 (or whatever), we could be smarter
2722 if (GET_CODE (sizertx) != CONST_INT)
2726 int size = INTVAL (sizertx);
2727 while (size % align)
2731 if (align != INTVAL (alignrtx))
2732 alignrtx = gen_rtx (CONST_INT, VOIDmode, align);
2734 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2735 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align);
2736 xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
2738 ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3]));
2739 ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5]));
2741 /* This is the size of the transfer. Emit code to decrement the size
2742 value by ALIGN, and store the result in the temp1 register. */
2743 output_size_for_block_move (sizertx, temp1, alignrtx);
2745 /* Must handle the case when the size is zero or negative, so the first thing
2746 we do is compare the size against zero, and only copy bytes if it is
2747 zero or greater. Note that we have already subtracted off the alignment
2748 once, so we must copy 1 alignment worth of bytes if the size is zero
2751 The SUN assembler complains about labels in branch delay slots, so we
2752 do this before outputting the load address, so that there will always
2753 be a harmless insn between the branch here and the next label emitted
2759 sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]);
2760 output_asm_insn (pattern, xoperands);
2763 zoperands[0] = operands[0];
2764 zoperands[3] = plus_constant_for_output (operands[0], align);
2765 output_load_address (zoperands);
2767 /* ??? This might be much faster if the loops below were preconditioned
2770 That is, at run time, copy enough bytes one at a time to ensure that the
2771 target and source addresses are aligned to the the largest possible
2772 alignment. Then use a preconditioned unrolled loop to copy say 16
2773 bytes at a time. Then copy bytes one at a time until finish the rest. */
2775 /* Output the first label separately, so that it is spaced properly. */
2777 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3]));
2781 register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh"
2782 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2783 register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h"
2784 : (align == 8 && TARGET_ARCH64) ? "x" : "");
2786 sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]);
2787 output_asm_insn (pattern, xoperands);
2794 /* Output reasonable peephole for set-on-condition-code insns.
2795 Note that these insns assume a particular way of defining
2796 labels. Therefore, *both* sparc.h and this function must
2797 be changed if a new syntax is needed. */
2800 output_scc_insn (operands, insn)
2804 static char string[100];
2805 rtx label = 0, next = insn;
2808 /* Try doing a jump optimization which jump.c can't do for us
2809 because we did not expose that setcc works by using branches.
2811 If this scc insn is followed by an unconditional branch, then have
2812 the jump insn emitted here jump to that location, instead of to
2813 the end of the scc sequence as usual. */
2817 if (GET_CODE (next) == CODE_LABEL)
2819 next = NEXT_INSN (next);
2823 while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL);
2825 /* If we are in a sequence, and the following insn is a sequence also,
2826 then just following the current insn's next field will take us to the
2827 first insn of the next sequence, which is the wrong place. We don't
2828 want to optimize with a branch that has had its delay slot filled.
2829 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2830 which fails only if NEXT is such a branch. */
2832 if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)
2833 && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next))
2834 label = JUMP_LABEL (next);
2835 /* If not optimizing, jump label fields are not set. To be safe, always
2836 check here to whether label is still zero. */
2839 label = gen_label_rtx ();
2843 LABEL_NUSES (label) += 1;
2845 /* operands[3] is an unused slot. */
2846 operands[3] = label;
2848 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2849 insn since our type isn't allowed anywhere else. */
2851 /* ??? Fpcc instructions no longer have delay slots, so this code is
2852 probably obsolete. */
2854 /* The fastest way to emit code for this is an annulled branch followed
2855 by two move insns. This will take two cycles if the branch is taken,
2856 and three cycles if the branch is not taken.
2858 However, if we are in the delay slot of another branch, this won't work,
2859 because we can't put a branch in the delay slot of another branch.
2860 The above sequence would effectively take 3 or 4 cycles respectively
2861 since a no op would have be inserted between the two branches.
2862 In this case, we want to emit a move, annulled branch, and then the
2863 second move. This sequence always takes 3 cycles, and hence is faster
2864 when we are in a branch delay slot. */
2868 strcpy (string, "mov 0,%0\n\t");
2869 strcat (string, output_cbranch (operands[2], 3, 0, 1, 0));
2870 strcat (string, "\n\tmov 1,%0");
2874 strcpy (string, output_cbranch (operands[2], 3, 0, 1, 0));
2875 strcat (string, "\n\tmov 1,%0\n\tmov 0,%0");
2879 strcat (string, "\n%l3:");
2884 /* Vectors to keep interesting information about registers where it can easily
2885 be got. We use to use the actual mode value as the bit number, but there
2886 are more than 32 modes now. Instead we use two tables: one indexed by
2887 hard register number, and one indexed by mode. */
2889 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2890 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2891 mapped into one sparc_mode_class mode. */
2893 enum sparc_mode_class {
2894 S_MODE, D_MODE, T_MODE, O_MODE,
2895 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2899 /* Modes for single-word and smaller quantities. */
2900 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2902 /* Modes for double-word and smaller quantities. */
2903 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2905 /* Modes for quad-word and smaller quantities. */
2906 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2908 /* Modes for single-float quantities. We must allow any single word or
2909 smaller quantity. This is because the fix/float conversion instructions
2910 take integer inputs/outputs from the float registers. */
2911 #define SF_MODES (S_MODES)
2913 /* Modes for double-float and smaller quantities. */
2914 #define DF_MODES (S_MODES | D_MODES)
2916 /* ??? Sparc64 fp regs cannot hold DImode values. */
2917 #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/)
2919 /* Modes for double-float only quantities. */
2920 /* ??? Sparc64 fp regs cannot hold DImode values.
2921 See fix_truncsfdi2. */
2922 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2924 /* Modes for double-float and larger quantities. */
2925 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2927 /* Modes for quad-float only quantities. */
2928 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2930 /* Modes for quad-float and smaller quantities. */
2931 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2933 /* ??? Sparc64 fp regs cannot hold DImode values.
2934 See fix_truncsfdi2. */
2935 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2937 /* Modes for condition codes. */
2938 #define CC_MODES (1 << (int) CC_MODE)
2939 #define CCFP_MODES (1 << (int) CCFP_MODE)
2941 /* Value is 1 if register/mode pair is acceptable on sparc.
2942 The funny mixture of D and T modes is because integer operations
2943 do not specially operate on tetra quantities, so non-quad-aligned
2944 registers can hold quadword quantities (except %o4 and %i4 because
2945 they cross fixed registers). */
2947 /* This points to either the 32 bit or the 64 bit version. */
2948 int *hard_regno_mode_classes;
2950 static int hard_32bit_mode_classes[] = {
2951 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2952 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2953 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2954 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2956 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2957 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2958 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2959 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2961 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2962 and none can hold SFmode/SImode values. */
2963 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2964 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2965 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2966 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2969 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2975 static int hard_64bit_mode_classes[] = {
2976 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2977 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2978 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2979 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2981 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2982 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2983 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2984 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2986 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2987 and none can hold SFmode/SImode values. */
2988 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2989 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2990 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2991 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2994 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3000 int sparc_mode_class [NUM_MACHINE_MODES];
3002 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
3009 for (i = 0; i < NUM_MACHINE_MODES; i++)
3011 switch (GET_MODE_CLASS (i))
3014 case MODE_PARTIAL_INT:
3015 case MODE_COMPLEX_INT:
3016 if (GET_MODE_SIZE (i) <= 4)
3017 sparc_mode_class[i] = 1 << (int) S_MODE;
3018 else if (GET_MODE_SIZE (i) == 8)
3019 sparc_mode_class[i] = 1 << (int) D_MODE;
3020 else if (GET_MODE_SIZE (i) == 16)
3021 sparc_mode_class[i] = 1 << (int) T_MODE;
3022 else if (GET_MODE_SIZE (i) == 32)
3023 sparc_mode_class[i] = 1 << (int) O_MODE;
3025 sparc_mode_class[i] = 0;
3028 case MODE_COMPLEX_FLOAT:
3029 if (GET_MODE_SIZE (i) <= 4)
3030 sparc_mode_class[i] = 1 << (int) SF_MODE;
3031 else if (GET_MODE_SIZE (i) == 8)
3032 sparc_mode_class[i] = 1 << (int) DF_MODE;
3033 else if (GET_MODE_SIZE (i) == 16)
3034 sparc_mode_class[i] = 1 << (int) TF_MODE;
3035 else if (GET_MODE_SIZE (i) == 32)
3036 sparc_mode_class[i] = 1 << (int) OF_MODE;
3038 sparc_mode_class[i] = 0;
3042 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3043 we must explicitly check for them here. */
3044 if (i == (int) CCFPmode || i == (int) CCFPEmode)
3045 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
3046 else if (i == (int) CCmode || i == (int) CC_NOOVmode
3047 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
3048 sparc_mode_class[i] = 1 << (int) CC_MODE;
3050 sparc_mode_class[i] = 0;
3056 hard_regno_mode_classes = hard_64bit_mode_classes;
3058 hard_regno_mode_classes = hard_32bit_mode_classes;
3060 /* Initialize the array used by REGNO_REG_CLASS. */
3061 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3064 sparc_regno_reg_class[i] = GENERAL_REGS;
3066 sparc_regno_reg_class[i] = FP_REGS;
3068 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
3070 sparc_regno_reg_class[i] = FPCC_REGS;
3072 sparc_regno_reg_class[i] = NO_REGS;
3076 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3077 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3078 v9 int regs as it simplifies the code. */
3081 save_regs (file, low, high, base, offset, n_regs, real_offset)
3091 if (TARGET_ARCH64 && high <= 32)
3093 for (i = low; i < high; i++)
3095 if (regs_ever_live[i] && ! call_used_regs[i])
3097 fprintf (file, "\tstx %s,[%s+%d]\n",
3098 reg_names[i], base, offset + 4 * n_regs);
3099 if (dwarf2out_do_frame ())
3100 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3107 for (i = low; i < high; i += 2)
3109 if (regs_ever_live[i] && ! call_used_regs[i])
3110 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3112 fprintf (file, "\tstd %s,[%s+%d]\n",
3113 reg_names[i], base, offset + 4 * n_regs);
3114 if (dwarf2out_do_frame ())
3116 char *l = dwarf2out_cfi_label ();
3117 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
3118 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
3124 fprintf (file, "\tst %s,[%s+%d]\n",
3125 reg_names[i], base, offset + 4 * n_regs);
3126 if (dwarf2out_do_frame ())
3127 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
3130 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3132 fprintf (file, "\tst %s,[%s+%d]\n",
3133 reg_names[i+1], base, offset + 4 * n_regs + 4);
3134 if (dwarf2out_do_frame ())
3135 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
3143 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3145 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3146 v9 int regs as it simplifies the code. */
3149 restore_regs (file, low, high, base, offset, n_regs)
3158 if (TARGET_ARCH64 && high <= 32)
3160 for (i = low; i < high; i++)
3162 if (regs_ever_live[i] && ! call_used_regs[i])
3163 fprintf (file, "\tldx [%s+%d], %s\n",
3164 base, offset + 4 * n_regs, reg_names[i]),
3170 for (i = low; i < high; i += 2)
3172 if (regs_ever_live[i] && ! call_used_regs[i])
3173 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3174 fprintf (file, "\tldd [%s+%d], %s\n",
3175 base, offset + 4 * n_regs, reg_names[i]),
3178 fprintf (file, "\tld [%s+%d],%s\n",
3179 base, offset + 4 * n_regs, reg_names[i]),
3181 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
3182 fprintf (file, "\tld [%s+%d],%s\n",
3183 base, offset + 4 * n_regs + 4, reg_names[i+1]),
3190 /* Static variables we want to share between prologue and epilogue. */
3192 /* Number of live general or floating point registers needed to be saved
3193 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
3194 static int num_gfregs;
3196 /* Compute the frame size required by the function. This function is called
3197 during the reload pass and also by output_function_prologue(). */
3200 compute_frame_size (size, leaf_function)
3205 int outgoing_args_size = (current_function_outgoing_args_size
3206 + REG_PARM_STACK_SPACE (current_function_decl));
3208 if (TARGET_EPILOGUE)
3210 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3211 even to v9 int regs to be consistent with save_regs/restore_regs. */
3215 for (i = 0; i < 8; i++)
3216 if (regs_ever_live[i] && ! call_used_regs[i])
3221 for (i = 0; i < 8; i += 2)
3222 if ((regs_ever_live[i] && ! call_used_regs[i])
3223 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3227 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
3228 if ((regs_ever_live[i] && ! call_used_regs[i])
3229 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3233 /* Set up values for use in `function_epilogue'. */
3234 num_gfregs = n_regs;
3236 if (leaf_function && n_regs == 0
3237 && size == 0 && current_function_outgoing_args_size == 0)
3239 actual_fsize = apparent_fsize = 0;
3243 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3244 The stack bias (if any) is taken out to undo its effects. */
3245 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3246 apparent_fsize += n_regs * 4;
3247 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3250 /* Make sure nothing can clobber our register windows.
3251 If a SAVE must be done, or there is a stack-local variable,
3252 the register window area must be allocated.
3253 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3254 if (leaf_function == 0 || size > 0)
3255 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
3257 return SPARC_STACK_ALIGN (actual_fsize);
3260 /* Build a (32 bit) big number in a register. */
3261 /* ??? We may be able to use the set macro here too. */
3264 build_big_number (file, num, reg)
3269 if (num >= 0 || ! TARGET_ARCH64)
3271 fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg);
3272 if ((num & 0x3ff) != 0)
3273 fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg);
3275 else /* num < 0 && TARGET_ARCH64 */
3277 /* Sethi does not sign extend, so we must use a little trickery
3278 to use it for negative numbers. Invert the constant before
3279 loading it in, then use xor immediate to invert the loaded bits
3280 (along with the upper 32 bits) to the desired constant. This
3281 works because the sethi and immediate fields overlap. */
3284 int low = -0x400 + (asize & 0x3FF);
3286 fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
3287 inv, reg, reg, low, reg);
3291 /* Output code for the function prologue. */
3294 output_function_prologue (file, size, leaf_function)
3299 /* Need to use actual_fsize, since we are also allocating
3300 space for our callee (and our own register save area). */
3301 actual_fsize = compute_frame_size (size, leaf_function);
3305 frame_base_name = "%sp";
3306 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3310 frame_base_name = "%fp";
3311 frame_base_offset = SPARC_STACK_BIAS;
3314 /* This is only for the human reader. */
3315 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
3317 if (actual_fsize == 0)
3319 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
3321 if (actual_fsize <= 4096)
3322 fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize);
3323 else if (actual_fsize <= 8192)
3325 fprintf (file, "\tsave %%sp,-4096,%%sp\n");
3326 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3330 build_big_number (file, -actual_fsize, "%g1");
3331 fprintf (file, "\tsave %%sp,%%g1,%%sp\n");
3334 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
3336 /* We assume the environment will properly handle or otherwise avoid
3337 trouble associated with an interrupt occuring after the `save' or
3338 trap occuring during it. */
3339 fprintf (file, "\tsave\n");
3341 if (actual_fsize <= 4096)
3342 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize);
3343 else if (actual_fsize <= 8192)
3345 fprintf (file, "\tadd %%fp,-4096,%%sp\n");
3346 fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize - 4096);
3350 build_big_number (file, -actual_fsize, "%g1");
3351 fprintf (file, "\tadd %%fp,%%g1,%%sp\n");
3354 else /* leaf function */
3356 if (actual_fsize <= 4096)
3357 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize);
3358 else if (actual_fsize <= 8192)
3360 fprintf (file, "\tadd %%sp,-4096,%%sp\n");
3361 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
3365 build_big_number (file, -actual_fsize, "%g1");
3366 fprintf (file, "\tadd %%sp,%%g1,%%sp\n");
3370 if (dwarf2out_do_frame () && actual_fsize)
3372 char *label = dwarf2out_cfi_label ();
3374 /* The canonical frame address refers to the top of the frame. */
3375 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3376 : FRAME_POINTER_REGNUM),
3379 if (! leaf_function)
3381 /* Note the register window save. This tells the unwinder that
3382 it needs to restore the window registers from the previous
3383 frame's window save area at 0(cfa). */
3384 dwarf2out_window_save (label);
3386 /* The return address (-8) is now in %i7. */
3387 dwarf2out_return_reg (label, 31);
3391 /* If doing anything with PIC, do it now. */
3393 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
3395 /* Call saved registers are saved just above the outgoing argument area. */
3398 int offset, real_offset, n_regs;
3401 real_offset = -apparent_fsize;
3402 offset = -apparent_fsize + frame_base_offset;
3403 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3405 /* ??? This might be optimized a little as %g1 might already have a
3406 value close enough that a single add insn will do. */
3407 /* ??? Although, all of this is probably only a temporary fix
3408 because if %g1 can hold a function result, then
3409 output_function_epilogue will lose (the result will get
3411 build_big_number (file, offset, "%g1");
3412 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3418 base = frame_base_name;
3421 if (TARGET_EPILOGUE && ! leaf_function)
3422 /* ??? Originally saved regs 0-15 here. */
3423 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3424 else if (leaf_function)
3425 /* ??? Originally saved regs 0-31 here. */
3426 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
3427 if (TARGET_EPILOGUE)
3428 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3433 if (leaf_function && actual_fsize != 0)
3435 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3436 if (! TARGET_EPILOGUE)
3437 leaf_label = gen_label_rtx ();
3441 /* Output code for the function epilogue. */
3444 output_function_epilogue (file, size, leaf_function)
3453 emit_label_after (leaf_label, get_last_insn ());
3454 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3457 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3458 else if (profile_block_flag == 2)
3460 FUNCTION_BLOCK_PROFILER_EXIT(file);
3464 /* Restore any call saved registers. */
3470 offset = -apparent_fsize + frame_base_offset;
3471 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3473 build_big_number (file, offset, "%g1");
3474 fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name);
3480 base = frame_base_name;
3483 if (TARGET_EPILOGUE && ! leaf_function)
3484 /* ??? Originally saved regs 0-15 here. */
3485 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3486 else if (leaf_function)
3487 /* ??? Originally saved regs 0-31 here. */
3488 n_regs = restore_regs (file, 0, 8, base, offset, 0);
3489 if (TARGET_EPILOGUE)
3490 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
3493 /* Work out how to skip the caller's unimp instruction if required. */
3495 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl");
3497 ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret");
3499 if (TARGET_EPILOGUE || leaf_label)
3501 int old_target_epilogue = TARGET_EPILOGUE;
3502 target_flags &= ~old_target_epilogue;
3504 if (! leaf_function)
3506 /* If we wound up with things in our delay slot, flush them here. */
3507 if (current_function_epilogue_delay_list)
3509 rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode),
3511 PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode,
3513 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3515 final_scan_insn (insn, file, 1, 0, 1);
3518 fprintf (file, "\t%s\n\trestore\n", ret);
3520 /* All of the following cases are for leaf functions. */
3521 else if (current_function_epilogue_delay_list)
3523 /* eligible_for_epilogue_delay_slot ensures that if this is a
3524 leaf function, then we will only have insn in the delay slot
3525 if the frame size is zero, thus no adjust for the stack is
3527 if (actual_fsize != 0)
3529 fprintf (file, "\t%s\n", ret);
3530 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3533 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3534 avoid generating confusing assembly language output. */
3535 else if (actual_fsize == 0)
3536 fprintf (file, "\t%s\n\tnop\n", ret);
3537 else if (actual_fsize <= 4096)
3538 fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize);
3539 else if (actual_fsize <= 8192)
3540 fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3541 ret, actual_fsize - 4096);
3542 else if ((actual_fsize & 0x3ff) == 0)
3543 fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3546 fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3547 actual_fsize, actual_fsize, ret);
3548 target_flags |= old_target_epilogue;
3552 /* Functions for handling argument passing.
3554 For v8 the first six args are normally in registers and the rest are
3555 pushed. Any arg that starts within the first 6 words is at least
3556 partially passed in a register unless its data type forbids.
3558 For v9, the argument registers are laid out as an array of 16 elements
3559 and arguments are added sequentially. The first 6 int args and up to the
3560 first 16 fp args (depending on size) are passed in regs.
3562 Slot Stack Integral Float Float in structure Double Long Double
3563 ---- ----- -------- ----- ------------------ ------ -----------
3564 15 [SP+248] %f31 %f30,%f31 %d30
3565 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3566 13 [SP+232] %f27 %f26,%f27 %d26
3567 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3568 11 [SP+216] %f23 %f22,%f23 %d22
3569 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3570 9 [SP+200] %f19 %f18,%f19 %d18
3571 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3572 7 [SP+184] %f15 %f14,%f15 %d14
3573 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3574 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3575 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3576 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3577 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3578 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3579 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3581 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3583 Integral arguments are always passed as 64 bit quantities appropriately
3586 Passing of floating point values is handled as follows.
3587 If a prototype is in scope:
3588 If the value is in a named argument (i.e. not a stdarg function or a
3589 value not part of the `...') then the value is passed in the appropriate
3591 If the value is part of the `...' and is passed in one of the first 6
3592 slots then the value is passed in the appropriate int reg.
3593 If the value is part of the `...' and is not passed in one of the first 6
3594 slots then the value is passed in memory.
3595 If a prototype is not in scope:
3596 If the value is one of the first 6 arguments the value is passed in the
3597 appropriate integer reg and the appropriate fp reg.
3598 If the value is not one of the first 6 arguments the value is passed in
3599 the appropriate fp reg and in memory.
3602 /* Maximum number of int regs for args. */
3603 #define SPARC_INT_ARG_MAX 6
3604 /* Maximum number of fp regs for args. */
3605 #define SPARC_FP_ARG_MAX 16
3607 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3609 /* Handle the INIT_CUMULATIVE_ARGS macro.
3610 Initialize a variable CUM of type CUMULATIVE_ARGS
3611 for a call to a function whose data type is FNTYPE.
3612 For a library call, FNTYPE is 0. */
3615 init_cumulative_args (cum, fntype, libname, indirect)
3616 CUMULATIVE_ARGS *cum;
3617 tree fntype, libname;
3621 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3622 cum->libcall_p = fntype == 0;
3625 /* Compute the slot number to pass an argument in.
3626 Returns the slot number or -1 if passing on the stack.
3628 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3629 the preceding args and about the function being called.
3630 MODE is the argument's machine mode.
3631 TYPE is the data type of the argument (as a tree).
3632 This is null for libcalls where that information may
3634 NAMED is nonzero if this argument is a named parameter
3635 (otherwise it is an extra parameter matching an ellipsis).
3636 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3637 *PREGNO records the register number to use if scalar type.
3638 *PPADDING records the amount of padding needed in words. */
3641 function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3642 const CUMULATIVE_ARGS *cum;
3643 enum machine_mode mode;
3650 int regbase = (incoming_p
3651 ? SPARC_INCOMING_INT_ARG_FIRST
3652 : SPARC_OUTGOING_INT_ARG_FIRST);
3653 int slotno = cum->words;
3658 if (type != 0 && TREE_ADDRESSABLE (type))
3661 && type != 0 && mode == BLKmode
3662 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3668 /* MODE is VOIDmode when generating the actual call.
3672 case QImode : case CQImode :
3673 case HImode : case CHImode :
3674 case SImode : case CSImode :
3675 case DImode : case CDImode :
3676 if (slotno >= SPARC_INT_ARG_MAX)
3678 regno = regbase + slotno;
3681 case SFmode : case SCmode :
3682 case DFmode : case DCmode :
3683 case TFmode : case TCmode :
3686 if (slotno >= SPARC_INT_ARG_MAX)
3688 regno = regbase + slotno;
3692 if ((mode == TFmode || mode == TCmode)
3693 && (slotno & 1) != 0)
3694 slotno++, *ppadding = 1;
3695 if (TARGET_FPU && named)
3697 if (slotno >= SPARC_FP_ARG_MAX)
3699 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3705 if (slotno >= SPARC_INT_ARG_MAX)
3707 regno = regbase + slotno;
3713 /* For sparc64, objects requiring 16 byte alignment get it. */
3716 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3717 slotno++, *ppadding = 1;
3721 || type && TREE_CODE (type) == UNION_TYPE)
3723 if (slotno >= SPARC_INT_ARG_MAX)
3725 regno = regbase + slotno;
3730 int intregs_p = 0, fpregs_p = 0;
3731 /* The ABI obviously doesn't specify how packed
3732 structures are passed. These are defined to be passed
3733 in int regs if possible, otherwise memory. */
3736 /* First see what kinds of registers we need. */
3737 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3739 if (TREE_CODE (field) == FIELD_DECL)
3741 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3746 if (DECL_PACKED (field))
3750 if (packed_p || !named)
3751 fpregs_p = 0, intregs_p = 1;
3753 /* If all arg slots are filled, then must pass on stack. */
3754 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3756 /* If there are only int args and all int arg slots are filled,
3757 then must pass on stack. */
3758 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3760 /* Note that even if all int arg slots are filled, fp members may
3761 still be passed in regs if such regs are available.
3762 *PREGNO isn't set because there may be more than one, it's up
3763 to the caller to compute them. */
3776 /* Handle the FUNCTION_ARG macro.
3777 Determine where to put an argument to a function.
3778 Value is zero to push the argument on the stack,
3779 or a hard register in which to store the argument.
3781 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3782 the preceding args and about the function being called.
3783 MODE is the argument's machine mode.
3784 TYPE is the data type of the argument (as a tree).
3785 This is null for libcalls where that information may
3787 NAMED is nonzero if this argument is a named parameter
3788 (otherwise it is an extra parameter matching an ellipsis).
3789 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3792 function_arg (cum, mode, type, named, incoming_p)
3793 const CUMULATIVE_ARGS *cum;
3794 enum machine_mode mode;
3799 int regbase = (incoming_p
3800 ? SPARC_INCOMING_INT_ARG_FIRST
3801 : SPARC_OUTGOING_INT_ARG_FIRST);
3802 int slotno, regno, padding;
3805 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3813 reg = gen_rtx (REG, mode, regno);
3817 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3818 but also have the slot allocated for them.
3819 If no prototype is in scope fp values in register slots get passed
3820 in two places, either fp regs and int regs or fp regs and memory. */
3821 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3822 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3823 && SPARC_FP_REG_P (regno))
3825 reg = gen_rtx (REG, mode, regno);
3826 if (cum->prototype_p || cum->libcall_p)
3828 /* "* 2" because fp reg numbers are recorded in 4 byte
3830 /* ??? This will cause the value to be passed in the fp reg and
3831 in the stack. When a prototype exists we want to pass the
3832 value in the reg but reserve space on the stack. That's an
3833 optimization, and is defered [for a bit]. */
3834 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
3835 return gen_rtx (PARALLEL, mode,
3837 gen_rtx (EXPR_LIST, VOIDmode,
3838 NULL_RTX, const0_rtx),
3839 gen_rtx (EXPR_LIST, VOIDmode,
3846 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3848 int regbase = (incoming_p
3849 ? SPARC_INCOMING_INT_ARG_FIRST
3850 : SPARC_OUTGOING_INT_ARG_FIRST);
3851 int intreg = regbase + (regno - SPARC_FP_ARG_FIRST) / 2;
3852 return gen_rtx (PARALLEL, mode,
3854 gen_rtx (EXPR_LIST, VOIDmode,
3855 gen_rtx (REG, mode, intreg),
3857 gen_rtx (EXPR_LIST, VOIDmode,
3861 return gen_rtx (PARALLEL, mode,
3863 gen_rtx (EXPR_LIST, VOIDmode,
3864 NULL_RTX, const0_rtx),
3865 gen_rtx (EXPR_LIST, VOIDmode,
3869 else if (type && TREE_CODE (type) == RECORD_TYPE)
3871 /* Structures up to 16 bytes in size are passed in arg slots on the
3872 stack and are promoted to registers where possible. */
3877 /* Starting bit position of a sequence of integer fields, counted from
3878 msb of left most byte, -1 if last field wasn't an int. */
3879 /* ??? This isn't entirely necessary, some simplification
3881 int start_int_bitpos;
3882 /* Current bitpos in struct, counted from msb of left most byte. */
3883 int bitpos, this_slotno;
3884 /* The ABI obviously doesn't specify how packed
3885 structures are passed. These are defined to be passed
3886 in int regs if possible, otherwise memory. */
3889 if (int_size_in_bytes (type) > 16)
3890 abort (); /* shouldn't get here */
3892 /* We need to compute how many registers are needed so we can allocate
3893 the PARALLEL but before we can do that we need to know whether there
3894 are any packed fields. If there are, int regs are used regardless of
3895 whether there are fp values present. */
3896 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3898 if (TREE_CODE (field) == FIELD_DECL
3899 && DECL_PACKED (field))
3906 /* Compute how many registers we need. */
3908 start_int_bitpos = -1;
3909 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3911 bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3912 this_slotno = slotno + bitpos / BITS_PER_WORD;
3913 if (TREE_CODE (field) == FIELD_DECL)
3915 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3920 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3921 If it wasn't true we wouldn't be here. */
3923 start_int_bitpos = -1;
3925 else if (this_slotno < SPARC_INT_ARG_MAX)
3927 if (start_int_bitpos == -1)
3930 start_int_bitpos = bitpos;
3934 if (bitpos % BITS_PER_WORD == 0)
3943 ret = gen_rtx (PARALLEL, BLKmode, rtvec_alloc (nregs + 1));
3945 /* ??? This causes the entire struct to be passed in memory.
3946 This isn't necessary, but is left for later. */
3947 XVECEXP (ret, 0, 0) = gen_rtx (EXPR_LIST, VOIDmode, NULL_RTX,
3950 /* Fill in the entries. */
3951 start_int_bitpos = -1;
3952 for (i = 1, field = TYPE_FIELDS (type);
3954 field = TREE_CHAIN (field))
3956 bitpos = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3957 this_slotno = slotno + bitpos / BITS_PER_WORD;
3958 if (TREE_CODE (field) == FIELD_DECL)
3960 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3965 reg = gen_rtx (REG, DECL_MODE (field),
3966 (SPARC_FP_ARG_FIRST + this_slotno * 2
3967 + (DECL_MODE (field) == SFmode
3968 && (bitpos & 32) != 0)));
3969 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3970 GEN_INT (bitpos / BITS_PER_UNIT));
3972 start_int_bitpos = -1;
3976 if (this_slotno < SPARC_INT_ARG_MAX
3977 && (start_int_bitpos == -1
3978 || bitpos % BITS_PER_WORD == 0))
3980 enum machine_mode mode;
3982 /* If this is the trailing part of a word, only load
3983 that much into the register. Otherwise load the
3984 whole register. Note that in the latter case we may
3985 pick up unwanted bits. It's not a problem at the
3986 moment but may wish to revisit. */
3987 if (bitpos % BITS_PER_WORD != 0)
3988 mode = mode_for_size (BITS_PER_WORD - bitpos % BITS_PER_WORD,
3993 regno = regbase + this_slotno;
3994 reg = gen_rtx (REG, mode, regno);
3995 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3996 GEN_INT (bitpos / BITS_PER_UNIT));
3998 if (start_int_bitpos == -1)
3999 start_int_bitpos = bitpos;
4009 else if (type && TREE_CODE (type) == UNION_TYPE)
4011 enum machine_mode mode;
4012 int bytes = int_size_in_bytes (type);
4017 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4018 reg = gen_rtx (REG, mode, regno);
4022 /* Scalar or complex int. */
4023 reg = gen_rtx (REG, mode, regno);
4029 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4030 For an arg passed partly in registers and partly in memory,
4031 this is the number of registers used.
4032 For args passed entirely in registers or entirely in memory, zero.
4034 Any arg that starts in the first 6 regs but won't entirely fit in them
4035 needs partial registers on v8. On v9, structures with integer
4036 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4037 values that begin in the last fp reg [where "last fp reg" varies with the
4038 mode] will be split between that reg and memory. */
4041 function_arg_partial_nregs (cum, mode, type, named)
4042 const CUMULATIVE_ARGS *cum;
4043 enum machine_mode mode;
4047 int slotno, regno, padding;
4049 /* We pass 0 for incoming_p here, it doesn't matter. */
4050 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4057 if ((slotno + (mode == BLKmode
4058 ? ROUND_ADVANCE (int_size_in_bytes (type))
4059 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4060 > NPARM_REGS (SImode))
4061 return NPARM_REGS (SImode) - slotno;
4066 if (type && AGGREGATE_TYPE_P (type))
4068 int size = int_size_in_bytes (type);
4069 int align = TYPE_ALIGN (type);
4072 slotno += slotno & 1;
4073 if (size > 8 && size <= 16
4074 && slotno == SPARC_INT_ARG_MAX - 1)
4077 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4078 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4081 if (GET_MODE_ALIGNMENT (mode) == 128)
4083 slotno += slotno & 1;
4084 if (slotno == SPARC_INT_ARG_MAX - 2)
4089 if (slotno == SPARC_INT_ARG_MAX - 1)
4093 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4095 if (GET_MODE_ALIGNMENT (mode) == 128)
4096 slotno += slotno & 1;
4097 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4105 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4106 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4107 quad-precision floats by invisible reference.
4108 v9: aggregates greater than 16 bytes are passed by reference.
4109 For Pascal, also pass arrays by reference. */
4112 function_arg_pass_by_reference (cum, mode, type, named)
4113 const CUMULATIVE_ARGS *cum;
4114 enum machine_mode mode;
4120 return (type && AGGREGATE_TYPE_P (type)
4121 || mode == TFmode || mode == TCmode);
4125 return ((type && TREE_CODE (type) == ARRAY_TYPE)
4126 || (type && AGGREGATE_TYPE_P (type)
4127 && int_size_in_bytes (type) > 16));
4131 /* Handle the FUNCTION_ARG_ADVANCE macro.
4132 Update the data in CUM to advance over an argument
4133 of mode MODE and data type TYPE.
4134 TYPE is null for libcalls where that information may not be available. */
4137 function_arg_advance (cum, mode, type, named)
4138 CUMULATIVE_ARGS *cum;
4139 enum machine_mode mode;
4143 int slotno, regno, padding;
4145 /* We pass 0 for incoming_p here, it doesn't matter. */
4146 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
4148 /* If register required leading padding, add it. */
4150 cum->words += padding;
4154 cum->words += (mode != BLKmode
4155 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4156 : ROUND_ADVANCE (int_size_in_bytes (type)));
4160 if (type && AGGREGATE_TYPE_P (type))
4162 int size = int_size_in_bytes (type);
4166 else if (size <= 16)
4168 else /* passed by reference */
4171 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4175 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4177 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4181 cum->words += (mode != BLKmode
4182 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4183 : ROUND_ADVANCE (int_size_in_bytes (type)));
4188 /* Handle the FUNCTION_ARG_PADDING macro.
4189 For the 64 bit ABI structs are always stored left shifted in their
4193 function_arg_padding (mode, type)
4194 enum machine_mode mode;
4197 if (TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE)
4202 /* This is the default definition. */
4203 return (! BYTES_BIG_ENDIAN
4206 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4207 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4208 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4209 ? downward : upward));
4212 /* Do what is necessary for `va_start'. The argument is ignored.
4214 We look at the current function to determine if stdarg or varargs
4215 is used and return the address of the first unnamed parameter. */
4218 sparc_builtin_saveregs (arglist)
4221 tree fntype = TREE_TYPE (current_function_decl);
4222 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
4223 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4224 != void_type_node));
4225 int first_reg = current_function_args_info.words;
4229 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
4230 emit_move_insn (gen_rtx (MEM, word_mode,
4231 gen_rtx (PLUS, Pmode,
4233 GEN_INT (STACK_POINTER_OFFSET
4234 + UNITS_PER_WORD * regno))),
4235 gen_rtx (REG, word_mode,
4236 BASE_INCOMING_ARG_REG (word_mode) + regno));
4238 address = gen_rtx (PLUS, Pmode,
4240 GEN_INT (STACK_POINTER_OFFSET
4241 + UNITS_PER_WORD * first_reg));
4243 if (flag_check_memory_usage
4244 && first_reg < NPARM_REGS (word_mode))
4245 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4247 GEN_INT (UNITS_PER_WORD
4248 * (NPARM_REGS (word_mode) - first_reg)),
4249 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), QImode);
4254 /* Return the string to output a conditional branch to LABEL, which is
4255 the operand number of the label. OP is the conditional expression.
4256 XEXP (OP, 0) is assumed to be a condition code register (integer or
4257 floating point) and its mode specifies what kind of comparison we made.
4259 REVERSED is non-zero if we should reverse the sense of the comparison.
4261 ANNUL is non-zero if we should generate an annulling branch.
4263 NOOP is non-zero if we have to follow this branch by a noop. */
4266 output_cbranch (op, label, reversed, annul, noop)
4269 int reversed, annul, noop;
4271 static char string[20];
4272 enum rtx_code code = GET_CODE (op);
4273 rtx cc_reg = XEXP (op, 0);
4274 enum machine_mode mode = GET_MODE (cc_reg);
4275 static char v8_labelno[] = " %lX";
4276 static char v9_icc_labelno[] = " %%icc,%lX";
4277 static char v9_xcc_labelno[] = " %%xcc,%lX";
4278 static char v9_fcc_labelno[] = " %%fccX,%lY";
4282 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4283 Because there is currently no concept of pre-delay slots, we can fix
4284 this only by always emitting a nop before a floating point branch. */
4286 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
4287 strcpy (string, "nop\n\t");
4291 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4293 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
4294 code = reverse_condition (code), reversed = 0;
4296 /* Start by writing the branch condition. */
4300 if (mode == CCFPmode || mode == CCFPEmode)
4301 strcat (string, "fbne");
4303 strcpy (string, "bne");
4307 if (mode == CCFPmode || mode == CCFPEmode)
4308 strcat (string, "fbe");
4310 strcpy (string, "be");
4314 if (mode == CCFPmode || mode == CCFPEmode)
4317 strcat (string, "fbul");
4319 strcat (string, "fbge");
4321 else if (mode == CC_NOOVmode)
4322 strcpy (string, "bpos");
4324 strcpy (string, "bge");
4328 if (mode == CCFPmode || mode == CCFPEmode)
4331 strcat (string, "fbule");
4333 strcat (string, "fbg");
4336 strcpy (string, "bg");
4340 if (mode == CCFPmode || mode == CCFPEmode)
4343 strcat (string, "fbug");
4345 strcat (string, "fble");
4348 strcpy (string, "ble");
4352 if (mode == CCFPmode || mode == CCFPEmode)
4355 strcat (string, "fbuge");
4357 strcat (string, "fbl");
4359 else if (mode == CC_NOOVmode)
4360 strcpy (string, "bneg");
4362 strcpy (string, "bl");
4366 strcpy (string, "bgeu");
4370 strcpy (string, "bgu");
4374 strcpy (string, "bleu");
4378 strcpy (string, "blu");
4382 /* Now add the annulling, the label, and a possible noop. */
4384 strcat (string, ",a");
4386 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
4391 labelno = v8_labelno;
4396 if (mode == CCFPmode || mode == CCFPEmode)
4399 labelno = v9_fcc_labelno;
4400 /* Set the char indicating the number of the fcc reg to use. */
4401 labelno[6] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
4403 else if (mode == CCXmode || mode == CCX_NOOVmode)
4404 labelno = v9_xcc_labelno;
4406 labelno = v9_icc_labelno;
4408 /* Set the char indicating the number of the operand containing the
4410 labelno[labeloff] = label + '0';
4411 strcat (string, labelno);
4414 strcat (string, "\n\tnop");
4419 /* Return the string to output a conditional branch to LABEL, testing
4420 register REG. LABEL is the operand number of the label; REG is the
4421 operand number of the reg. OP is the conditional expression. The mode
4422 of REG says what kind of comparison we made.
4424 REVERSED is non-zero if we should reverse the sense of the comparison.
4426 ANNUL is non-zero if we should generate an annulling branch.
4428 NOOP is non-zero if we have to follow this branch by a noop. */
4431 output_v9branch (op, reg, label, reversed, annul, noop)
4434 int reversed, annul, noop;
4436 static char string[20];
4437 enum rtx_code code = GET_CODE (op);
4438 enum machine_mode mode = GET_MODE (XEXP (op, 0));
4439 static char labelno[] = " %X,%lX";
4441 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4443 code = reverse_condition (code), reversed = 0;
4445 /* Only 64 bit versions of these instructions exist. */
4449 /* Start by writing the branch condition. */
4454 strcpy (string, "brnz");
4458 strcpy (string, "brz");
4462 strcpy (string, "brgez");
4466 strcpy (string, "brlz");
4470 strcpy (string, "brlez");
4474 strcpy (string, "brgz");
4481 /* Now add the annulling, reg, label, and nop. */
4483 strcat (string, ",a");
4485 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
4487 labelno[2] = reg + '0';
4488 labelno[6] = label + '0';
4489 strcat (string, labelno);
4492 strcat (string, "\n\tnop");
4497 /* Output assembler code to return from a function. */
4499 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
4500 md file for the `return' instruction. */
4503 output_return (operands)
4508 operands[0] = leaf_label;
4511 else if (leaf_function)
4513 /* If we didn't allocate a frame pointer for the current function,
4514 the stack pointer might have been adjusted. Output code to
4517 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize);
4519 /* Use sub of negated value in first two cases instead of add to
4520 allow actual_fsize == 4096. */
4522 if (actual_fsize <= 4096)
4524 if (SKIP_CALLERS_UNIMP_P)
4525 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4527 return "retl\n\tsub %%sp,-%0,%%sp";
4529 else if (actual_fsize <= 8192)
4531 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096);
4532 if (SKIP_CALLERS_UNIMP_P)
4533 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4535 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
4537 else if (SKIP_CALLERS_UNIMP_P)
4539 if ((actual_fsize & 0x3ff) != 0)
4540 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4542 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4546 if ((actual_fsize & 0x3ff) != 0)
4547 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4549 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4554 if (SKIP_CALLERS_UNIMP_P)
4555 return "jmp %%i7+12\n\trestore";
4557 return "ret\n\trestore";
4561 /* Leaf functions and non-leaf functions have different needs. */
4564 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4567 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4569 static int *reg_alloc_orders[] = {
4570 reg_leaf_alloc_order,
4571 reg_nonleaf_alloc_order};
4574 order_regs_for_local_alloc ()
4576 static int last_order_nonleaf = 1;
4578 if (regs_ever_live[15] != last_order_nonleaf)
4580 last_order_nonleaf = !last_order_nonleaf;
4581 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4582 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
4586 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4587 This makes them candidates for using ldd and std insns.
4589 Note reg1 and reg2 *must* be hard registers. To be sure we will
4590 abort if we are passed pseudo registers. */
4593 registers_ok_for_ldd_peep (reg1, reg2)
4596 /* We might have been passed a SUBREG. */
4597 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4600 if (REGNO (reg1) % 2 != 0)
4603 return (REGNO (reg1) == REGNO (reg2) - 1);
4606 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4609 This can only happen when addr1 and addr2 are consecutive memory
4610 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4611 64 bit boundary (addr1 % 8 == 0).
4613 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4614 registers are assumed to *never* be properly aligned and are
4617 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4618 need only check that the offset for addr1 % 8 == 0. */
4621 addrs_ok_for_ldd_peep (addr1, addr2)
4626 /* Extract a register number and offset (if used) from the first addr. */
4627 if (GET_CODE (addr1) == PLUS)
4629 /* If not a REG, return zero. */
4630 if (GET_CODE (XEXP (addr1, 0)) != REG)
4634 reg1 = REGNO (XEXP (addr1, 0));
4635 /* The offset must be constant! */
4636 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4638 offset1 = INTVAL (XEXP (addr1, 1));
4641 else if (GET_CODE (addr1) != REG)
4645 reg1 = REGNO (addr1);
4646 /* This was a simple (mem (reg)) expression. Offset is 0. */
4650 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4651 if (GET_CODE (addr2) != PLUS)
4654 if (GET_CODE (XEXP (addr2, 0)) != REG
4655 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4658 /* Only %fp and %sp are allowed. Additionally both addresses must
4659 use the same register. */
4660 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4663 if (reg1 != REGNO (XEXP (addr2, 0)))
4666 /* The first offset must be evenly divisible by 8 to ensure the
4667 address is 64 bit aligned. */
4668 if (offset1 % 8 != 0)
4671 /* The offset for the second addr must be 4 more than the first addr. */
4672 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4675 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4680 /* Return 1 if reg is a pseudo, or is the first register in
4681 a hard register pair. This makes it a candidate for use in
4682 ldd and std insns. */
4685 register_ok_for_ldd (reg)
4688 /* We might have been passed a SUBREG. */
4689 if (GET_CODE (reg) != REG)
4692 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4693 return (REGNO (reg) % 2 == 0);
4698 /* Print operand X (an rtx) in assembler syntax to file FILE.
4699 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4700 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4703 print_operand (file, x, code)
4711 /* Output a 'nop' if there's nothing for the delay slot. */
4712 if (dbr_sequence_length () == 0)
4713 fputs ("\n\tnop", file);
4716 /* Output an annul flag if there's nothing for the delay slot and we
4717 are optimizing. This is always used with '(' below. */
4718 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4719 this is a dbx bug. So, we only do this when optimizing. */
4720 if (dbr_sequence_length () == 0 && optimize)
4724 /* Output a 'nop' if there's nothing for the delay slot and we are
4725 not optimizing. This is always used with '*' above. */
4726 if (dbr_sequence_length () == 0 && ! optimize)
4727 fputs ("\n\tnop", file);
4730 /* Output the Embedded Medium/Anywhere code model base register. */
4731 fputs (EMBMEDANY_BASE_REG, file);
4734 /* Print out what we are using as the frame pointer. This might
4735 be %fp, or might be %sp+offset. */
4736 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4737 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4740 /* Adjust the operand to take into account a RESTORE operation. */
4741 if (GET_CODE (x) != REG)
4742 output_operand_lossage ("Invalid %%Y operand");
4743 else if (REGNO (x) < 8)
4744 fputs (reg_names[REGNO (x)], file);
4745 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4746 fputs (reg_names[REGNO (x)-16], file);
4748 output_operand_lossage ("Invalid %%Y operand");
4751 /* Print out the low order register name of a register pair. */
4752 if (WORDS_BIG_ENDIAN)
4753 fputs (reg_names[REGNO (x)+1], file);
4755 fputs (reg_names[REGNO (x)], file);
4758 /* Print out the high order register name of a register pair. */
4759 if (WORDS_BIG_ENDIAN)
4760 fputs (reg_names[REGNO (x)], file);
4762 fputs (reg_names[REGNO (x)+1], file);
4765 /* Print out the second register name of a register pair or quad.
4766 I.e., R (%o0) => %o1. */
4767 fputs (reg_names[REGNO (x)+1], file);
4770 /* Print out the third register name of a register quad.
4771 I.e., S (%o0) => %o2. */
4772 fputs (reg_names[REGNO (x)+2], file);
4775 /* Print out the fourth register name of a register quad.
4776 I.e., T (%o0) => %o3. */
4777 fputs (reg_names[REGNO (x)+3], file);
4780 /* Print a condition code register. */
4781 if (REGNO (x) == SPARC_ICC_REG)
4783 /* We don't handle CC[X]_NOOVmode because they're not supposed
4785 if (GET_MODE (x) == CCmode)
4786 fputs ("%icc", file);
4787 else if (GET_MODE (x) == CCXmode)
4788 fputs ("%xcc", file);
4793 /* %fccN register */
4794 fputs (reg_names[REGNO (x)], file);
4797 /* Print the operand's address only. */
4798 output_address (XEXP (x, 0));
4801 /* In this case we need a register. Use %g0 if the
4802 operand is const0_rtx. */
4804 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
4806 fputs ("%g0", file);
4813 switch (GET_CODE (x))
4815 case IOR: fputs ("or", file); break;
4816 case AND: fputs ("and", file); break;
4817 case XOR: fputs ("xor", file); break;
4818 default: output_operand_lossage ("Invalid %%A operand");
4823 switch (GET_CODE (x))
4825 case IOR: fputs ("orn", file); break;
4826 case AND: fputs ("andn", file); break;
4827 case XOR: fputs ("xnor", file); break;
4828 default: output_operand_lossage ("Invalid %%B operand");
4832 /* These are used by the conditional move instructions. */
4836 enum rtx_code rc = (code == 'c'
4837 ? reverse_condition (GET_CODE (x))
4841 case NE: fputs ("ne", file); break;
4842 case EQ: fputs ("e", file); break;
4843 case GE: fputs ("ge", file); break;
4844 case GT: fputs ("g", file); break;
4845 case LE: fputs ("le", file); break;
4846 case LT: fputs ("l", file); break;
4847 case GEU: fputs ("geu", file); break;
4848 case GTU: fputs ("gu", file); break;
4849 case LEU: fputs ("leu", file); break;
4850 case LTU: fputs ("lu", file); break;
4851 default: output_operand_lossage (code == 'c'
4852 ? "Invalid %%c operand"
4853 : "Invalid %%C operand");
4858 /* These are used by the movr instruction pattern. */
4862 enum rtx_code rc = (code == 'd'
4863 ? reverse_condition (GET_CODE (x))
4867 case NE: fputs ("ne", file); break;
4868 case EQ: fputs ("e", file); break;
4869 case GE: fputs ("gez", file); break;
4870 case LT: fputs ("lz", file); break;
4871 case LE: fputs ("lez", file); break;
4872 case GT: fputs ("gz", file); break;
4873 default: output_operand_lossage (code == 'd'
4874 ? "Invalid %%d operand"
4875 : "Invalid %%D operand");
4882 /* Print a sign-extended character. */
4883 int i = INTVAL (x) & 0xff;
4886 fprintf (file, "%d", i);
4891 /* Operand must be a MEM; write its address. */
4892 if (GET_CODE (x) != MEM)
4893 output_operand_lossage ("Invalid %%f operand");
4894 output_address (XEXP (x, 0));
4898 /* Do nothing special. */
4902 /* Undocumented flag. */
4903 output_operand_lossage ("invalid operand output code");
4906 if (GET_CODE (x) == REG)
4907 fputs (reg_names[REGNO (x)], file);
4908 else if (GET_CODE (x) == MEM)
4911 /* Poor Sun assembler doesn't understand absolute addressing. */
4912 if (CONSTANT_P (XEXP (x, 0))
4913 && ! TARGET_LIVE_G0)
4914 fputs ("%g0+", file);
4915 output_address (XEXP (x, 0));
4918 else if (GET_CODE (x) == HIGH)
4920 fputs ("%hi(", file);
4921 output_addr_const (file, XEXP (x, 0));
4924 else if (GET_CODE (x) == LO_SUM)
4926 print_operand (file, XEXP (x, 0), 0);
4927 fputs ("+%lo(", file);
4928 output_addr_const (file, XEXP (x, 1));
4931 else if (GET_CODE (x) == CONST_DOUBLE
4932 && (GET_MODE (x) == VOIDmode
4933 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
4935 if (CONST_DOUBLE_HIGH (x) == 0)
4936 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
4937 else if (CONST_DOUBLE_HIGH (x) == -1
4938 && CONST_DOUBLE_LOW (x) < 0)
4939 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
4941 output_operand_lossage ("long long constant not a valid immediate operand");
4943 else if (GET_CODE (x) == CONST_DOUBLE)
4944 output_operand_lossage ("floating point constant not a valid immediate operand");
4945 else { output_addr_const (file, x); }
4948 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4949 a 64 bit (DImode) value. */
4951 /* ??? If there is a 64 bit counterpart to .word that the assembler
4952 understands, then using that would simply this code greatly. */
4953 /* ??? We only output .xword's for symbols and only then in environments
4954 where the assembler can handle them. */
4957 output_double_int (file, value)
4961 if (GET_CODE (value) == CONST_INT)
4963 /* ??? This has endianness issues. */
4964 #if HOST_BITS_PER_WIDE_INT == 64
4965 HOST_WIDE_INT xword = INTVAL (value);
4966 HOST_WIDE_INT high, low;
4968 high = (xword >> 32) & 0xffffffff;
4969 low = xword & 0xffffffff;
4970 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, high));
4971 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, low));
4973 if (INTVAL (value) < 0)
4974 ASM_OUTPUT_INT (file, constm1_rtx);
4976 ASM_OUTPUT_INT (file, const0_rtx);
4977 ASM_OUTPUT_INT (file, value);
4980 else if (GET_CODE (value) == CONST_DOUBLE)
4982 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4983 CONST_DOUBLE_HIGH (value)));
4984 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
4985 CONST_DOUBLE_LOW (value)));
4987 else if (GET_CODE (value) == SYMBOL_REF
4988 || GET_CODE (value) == CONST
4989 || GET_CODE (value) == PLUS
4990 || (TARGET_ARCH64 &&
4991 (GET_CODE (value) == LABEL_REF
4992 || GET_CODE (value) == CODE_LABEL
4993 || GET_CODE (value) == MINUS)))
4995 if (!TARGET_V9 || TARGET_CM_MEDLOW)
4997 ASM_OUTPUT_INT (file, const0_rtx);
4998 ASM_OUTPUT_INT (file, value);
5002 fprintf (file, "\t%s\t", ASM_LONGLONG);
5003 output_addr_const (file, value);
5004 fprintf (file, "\n");
5011 /* Return the value of a code used in the .proc pseudo-op that says
5012 what kind of result this function returns. For non-C types, we pick
5013 the closest C type. */
5015 #ifndef CHAR_TYPE_SIZE
5016 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5019 #ifndef SHORT_TYPE_SIZE
5020 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5023 #ifndef INT_TYPE_SIZE
5024 #define INT_TYPE_SIZE BITS_PER_WORD
5027 #ifndef LONG_TYPE_SIZE
5028 #define LONG_TYPE_SIZE BITS_PER_WORD
5031 #ifndef LONG_LONG_TYPE_SIZE
5032 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5035 #ifndef FLOAT_TYPE_SIZE
5036 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5039 #ifndef DOUBLE_TYPE_SIZE
5040 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5043 #ifndef LONG_DOUBLE_TYPE_SIZE
5044 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5048 sparc_type_code (type)
5051 register unsigned long qualifiers = 0;
5052 register unsigned shift = 6;
5054 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5055 setting more, since some assemblers will give an error for this. Also,
5056 we must be careful to avoid shifts of 32 bits or more to avoid getting
5057 unpredictable results. */
5061 switch (TREE_CODE (type))
5068 qualifiers |= (3 << shift);
5070 type = TREE_TYPE (type);
5076 qualifiers |= (2 << shift);
5078 type = TREE_TYPE (type);
5082 case REFERENCE_TYPE:
5085 qualifiers |= (1 << shift);
5087 type = TREE_TYPE (type);
5091 return (qualifiers | 8);
5094 case QUAL_UNION_TYPE:
5095 return (qualifiers | 9);
5098 return (qualifiers | 10);
5101 return (qualifiers | 16);
5104 /* If this is a range type, consider it to be the underlying
5106 if (TREE_TYPE (type) != 0)
5108 type = TREE_TYPE (type);
5112 /* Carefully distinguish all the standard types of C,
5113 without messing up if the language is not C. We do this by
5114 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5115 look at both the names and the above fields, but that's redundant.
5116 Any type whose size is between two C types will be considered
5117 to be the wider of the two types. Also, we do not have a
5118 special code to use for "long long", so anything wider than
5119 long is treated the same. Note that we can't distinguish
5120 between "int" and "long" in this code if they are the same
5121 size, but that's fine, since neither can the assembler. */
5123 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5124 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
5126 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5127 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
5129 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
5130 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5133 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5136 /* Carefully distinguish all the standard types of C,
5137 without messing up if the language is not C. */
5139 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
5140 return (qualifiers | 6);
5143 return (qualifiers | 7);
5145 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
5146 /* ??? We need to distinguish between double and float complex types,
5147 but I don't know how yet because I can't reach this code from
5148 existing front-ends. */
5149 return (qualifiers | 7); /* Who knows? */
5151 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5152 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5153 case FILE_TYPE: /* GNU Pascal FILE type. */
5154 case SET_TYPE: /* GNU Pascal SET type. */
5155 case LANG_TYPE: /* ? */
5159 abort (); /* Not a type! */
5164 /* Nested function support. */
5166 /* Emit RTL insns to initialize the variable parts of a trampoline.
5167 FNADDR is an RTX for the address of the function's pure code.
5168 CXT is an RTX for the static chain value for the function.
5170 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5171 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5172 (to store insns). This is a bit excessive. Perhaps a different
5173 mechanism would be better here.
5175 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5178 sparc_initialize_trampoline (tramp, fnaddr, cxt)
5179 rtx tramp, fnaddr, cxt;
5181 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt,
5182 size_int (10), 0, 1);
5183 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5184 size_int (10), 0, 1);
5185 rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
5186 rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0);
5187 rtx g1_sethi = gen_rtx (HIGH, SImode,
5188 gen_rtx (CONST_INT, VOIDmode, 0x03000000));
5189 rtx g2_sethi = gen_rtx (HIGH, SImode,
5190 gen_rtx (CONST_INT, VOIDmode, 0x05000000));
5191 rtx g1_ori = gen_rtx (HIGH, SImode,
5192 gen_rtx (CONST_INT, VOIDmode, 0x82106000));
5193 rtx g2_ori = gen_rtx (HIGH, SImode,
5194 gen_rtx (CONST_INT, VOIDmode, 0x8410A000));
5195 rtx tem = gen_reg_rtx (SImode);
5196 emit_move_insn (tem, g1_sethi);
5197 emit_insn (gen_iorsi3 (high_fn, high_fn, tem));
5198 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn);
5199 emit_move_insn (tem, g1_ori);
5200 emit_insn (gen_iorsi3 (low_fn, low_fn, tem));
5201 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn);
5202 emit_move_insn (tem, g2_sethi);
5203 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem));
5204 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt);
5205 emit_move_insn (tem, g2_ori);
5206 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem));
5207 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt);
5208 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, tramp))));
5209 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
5210 plus_constant (tramp, 8)))));
5211 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode,
5212 plus_constant (tramp, 16)))));
5215 /* The 64 bit version is simpler because it makes more sense to load the
5216 values as "immediate" data out of the trampoline. It's also easier since
5217 we can read the PC without clobbering a register. */
5220 sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5221 rtx tramp, fnaddr, cxt;
5223 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 24)), cxt);
5224 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 32)), fnaddr);
5225 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, tramp))));
5226 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5227 plus_constant (tramp, 8)))));
5228 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5229 plus_constant (tramp, 16)))));
5230 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5231 plus_constant (tramp, 24)))));
5232 emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode,
5233 plus_constant (tramp, 32)))));
5236 /* Subroutines to support a flat (single) register window calling
5239 /* Single-register window sparc stack frames look like:
5241 Before call After call
5242 +-----------------------+ +-----------------------+
5244 mem | caller's temps. | | caller's temps. |
5246 +-----------------------+ +-----------------------+
5248 | arguments on stack. | | arguments on stack. |
5250 +-----------------------+FP+92->+-----------------------+
5251 | 6 words to save | | 6 words to save |
5252 | arguments passed | | arguments passed |
5253 | in registers, even | | in registers, even |
5254 | if not passed. | | if not passed. |
5255 SP+68->+-----------------------+FP+68->+-----------------------+
5256 | 1 word struct addr | | 1 word struct addr |
5257 +-----------------------+FP+64->+-----------------------+
5259 | 16 word reg save area | | 16 word reg save area |
5261 SP->+-----------------------+ FP->+-----------------------+
5263 | fp/alu reg moves |
5264 FP-16->+-----------------------+
5268 +-----------------------+
5270 | fp register save |
5272 +-----------------------+
5274 | gp register save |
5276 +-----------------------+
5278 | alloca allocations |
5280 +-----------------------+
5282 | arguments on stack |
5284 SP+92->+-----------------------+
5286 | arguments passed |
5287 | in registers, even |
5288 low | if not passed. |
5289 memory SP+68->+-----------------------+
5290 | 1 word struct addr |
5291 SP+64->+-----------------------+
5293 I 16 word reg save area |
5295 SP->+-----------------------+ */
5297 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5298 save masks, and offsets for the current function. */
5300 struct sparc_frame_info
5302 unsigned long total_size; /* # bytes that the entire frame takes up. */
5303 unsigned long var_size; /* # bytes that variables take up. */
5304 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5305 unsigned long extra_size; /* # bytes of extra gunk. */
5306 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5307 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5308 unsigned long gmask; /* Mask of saved gp registers. */
5309 unsigned long fmask; /* Mask of saved fp registers. */
5310 unsigned long reg_offset; /* Offset from new sp to store regs. */
5311 int initialized; /* Nonzero if frame size already calculated. */
5314 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5315 struct sparc_frame_info current_frame_info;
5317 /* Zero structure to initialize current_frame_info. */
5318 struct sparc_frame_info zero_frame_info;
5320 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5322 #define RETURN_ADDR_REGNUM 15
5323 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5324 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5326 #define MUST_SAVE_REGISTER(regno) \
5327 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5328 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5329 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5331 /* Return the bytes needed to compute the frame pointer from the current
5335 sparc_flat_compute_frame_size (size)
5336 int size; /* # of var. bytes allocated. */
5339 unsigned long total_size; /* # bytes that the entire frame takes up. */
5340 unsigned long var_size; /* # bytes that variables take up. */
5341 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5342 unsigned long extra_size; /* # extra bytes. */
5343 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5344 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
5345 unsigned long gmask; /* Mask of saved gp registers. */
5346 unsigned long fmask; /* Mask of saved fp registers. */
5347 unsigned long reg_offset; /* Offset to register save area. */
5348 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
5350 /* This is the size of the 16 word reg save area, 1 word struct addr
5351 area, and 4 word fp/alu register copy area. */
5352 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5354 /* Also include the size needed for the 6 parameter registers. */
5355 args_size = current_function_outgoing_args_size + 24;
5356 total_size = var_size + args_size + extra_size;
5364 /* Calculate space needed for gp registers. */
5365 for (regno = 1; regno <= 31; regno++)
5367 if (MUST_SAVE_REGISTER (regno))
5369 /* If we need to save two regs in a row, ensure there's room to bump
5370 up the address to align it to a doubleword boundary. */
5371 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5373 if (gp_reg_size % 8 != 0)
5375 gp_reg_size += 2 * UNITS_PER_WORD;
5376 gmask |= 3 << regno;
5382 gp_reg_size += UNITS_PER_WORD;
5383 gmask |= 1 << regno;
5388 /* Calculate space needed for fp registers. */
5389 for (regno = 32; regno <= 63; regno++)
5391 if (regs_ever_live[regno] && !call_used_regs[regno])
5393 fp_reg_size += UNITS_PER_WORD;
5394 fmask |= 1 << (regno - 32);
5401 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5402 /* Ensure save area is 8 byte aligned if we need it. */
5404 if (need_aligned_p && n != 0)
5406 total_size += 8 - n;
5407 reg_offset += 8 - n;
5409 total_size += gp_reg_size + fp_reg_size;
5412 /* ??? This looks a little suspicious. Clarify. */
5413 if (total_size == extra_size)
5414 total_size = extra_size = 0;
5416 total_size = SPARC_STACK_ALIGN (total_size);
5418 /* Save other computed information. */
5419 current_frame_info.total_size = total_size;
5420 current_frame_info.var_size = var_size;
5421 current_frame_info.args_size = args_size;
5422 current_frame_info.extra_size = extra_size;
5423 current_frame_info.gp_reg_size = gp_reg_size;
5424 current_frame_info.fp_reg_size = fp_reg_size;
5425 current_frame_info.gmask = gmask;
5426 current_frame_info.fmask = fmask;
5427 current_frame_info.reg_offset = reg_offset;
5428 current_frame_info.initialized = reload_completed;
5430 /* Ok, we're done. */
5434 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5437 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5438 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5439 [BASE_REG+OFFSET] will always be a valid address.
5441 WORD_OP is either "st" for save, "ld" for restore.
5442 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5445 sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5446 doubleword_op, base_offset)
5449 unsigned int offset;
5450 unsigned long gmask;
5451 unsigned long fmask;
5453 char *doubleword_op;
5454 unsigned long base_offset;
5458 if (gmask == 0 && fmask == 0)
5461 /* Save registers starting from high to low. We've already saved the
5462 previous frame pointer and previous return address for the debugger's
5463 sake. The debugger allows us to not need a nop in the epilog if at least
5464 one register is reloaded in addition to return address. */
5468 for (regno = 1; regno <= 31; regno++)
5470 if ((gmask & (1L << regno)) != 0)
5472 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
5474 /* We can save two registers in a row. If we're not at a
5475 double word boundary, move to one.
5476 sparc_flat_compute_frame_size ensures there's room to do
5478 if (offset % 8 != 0)
5479 offset += UNITS_PER_WORD;
5481 if (word_op[0] == 's')
5483 fprintf (file, "\t%s %s,[%s+%d]\n",
5484 doubleword_op, reg_names[regno],
5486 if (dwarf2out_do_frame ())
5488 char *l = dwarf2out_cfi_label ();
5489 dwarf2out_reg_save (l, regno, offset + base_offset);
5491 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5495 fprintf (file, "\t%s [%s+%d],%s\n",
5496 doubleword_op, base_reg, offset,
5499 offset += 2 * UNITS_PER_WORD;
5504 if (word_op[0] == 's')
5506 fprintf (file, "\t%s %s,[%s+%d]\n",
5507 word_op, reg_names[regno],
5509 if (dwarf2out_do_frame ())
5510 dwarf2out_reg_save ("", regno, offset + base_offset);
5513 fprintf (file, "\t%s [%s+%d],%s\n",
5514 word_op, base_reg, offset, reg_names[regno]);
5516 offset += UNITS_PER_WORD;
5524 for (regno = 32; regno <= 63; regno++)
5526 if ((fmask & (1L << (regno - 32))) != 0)
5528 if (word_op[0] == 's')
5530 fprintf (file, "\t%s %s,[%s+%d]\n",
5531 word_op, reg_names[regno],
5533 if (dwarf2out_do_frame ())
5534 dwarf2out_reg_save ("", regno, offset + base_offset);
5537 fprintf (file, "\t%s [%s+%d],%s\n",
5538 word_op, base_reg, offset, reg_names[regno]);
5540 offset += UNITS_PER_WORD;
5546 /* Set up the stack and frame (if desired) for the function. */
5549 sparc_flat_output_function_prologue (file, size)
5553 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5554 unsigned long gmask = current_frame_info.gmask;
5556 /* This is only for the human reader. */
5557 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5558 fprintf (file, "\t%s# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5560 current_frame_info.var_size,
5561 current_frame_info.gp_reg_size / 4,
5562 current_frame_info.fp_reg_size / 4,
5563 current_function_outgoing_args_size,
5564 current_frame_info.extra_size);
5566 size = SPARC_STACK_ALIGN (size);
5567 size = (! current_frame_info.initialized
5568 ? sparc_flat_compute_frame_size (size)
5569 : current_frame_info.total_size);
5571 /* These cases shouldn't happen. Catch them now. */
5572 if (size == 0 && (gmask || current_frame_info.fmask))
5575 /* Allocate our stack frame by decrementing %sp.
5576 At present, the only algorithm gdb can use to determine if this is a
5577 flat frame is if we always set %i7 if we set %sp. This can be optimized
5578 in the future by putting in some sort of debugging information that says
5579 this is a `flat' function. However, there is still the case of debugging
5580 code without such debugging information (including cases where most fns
5581 have such info, but there is one that doesn't). So, always do this now
5582 so we don't get a lot of code out there that gdb can't handle.
5583 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5584 distinguish us from a non-flat function but there won't (and shouldn't)
5585 be any differences anyway. The return pc is saved (if necessary) right
5586 after %i7 so gdb won't have to look too far to find it. */
5589 unsigned int reg_offset = current_frame_info.reg_offset;
5590 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5591 char *t1_str = "%g1";
5593 /* Things get a little tricky if local variables take up more than ~4096
5594 bytes and outgoing arguments take up more than ~4096 bytes. When that
5595 happens, the register save area can't be accessed from either end of
5596 the frame. Handle this by decrementing %sp to the start of the gp
5597 register save area, save the regs, update %i7, and then set %sp to its
5598 final value. Given that we only have one scratch register to play
5599 with it is the cheapest solution, and it helps gdb out as it won't
5600 slow down recognition of flat functions.
5601 Don't change the order of insns emitted here without checking with
5602 the gdb folk first. */
5604 /* Is the entire register save area offsettable from %sp? */
5605 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5609 fprintf (file, "\tadd %s,%d,%s\n",
5610 sp_str, -size, sp_str);
5611 if (gmask & FRAME_POINTER_MASK)
5613 fprintf (file, "\tst %s,[%s+%d]\n",
5614 fp_str, sp_str, reg_offset);
5615 fprintf (file, "\tsub %s,%d,%s\t%s# set up frame pointer\n",
5616 sp_str, -size, fp_str, ASM_COMMENT_START);
5622 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5623 size, t1_str, sp_str, t1_str, sp_str);
5624 if (gmask & FRAME_POINTER_MASK)
5626 fprintf (file, "\tst %s,[%s+%d]\n",
5627 fp_str, sp_str, reg_offset);
5628 fprintf (file, "\tadd %s,%s,%s\t%s# set up frame pointer\n",
5629 sp_str, t1_str, fp_str, ASM_COMMENT_START);
5633 if (dwarf2out_do_frame ())
5635 char *l = dwarf2out_cfi_label ();
5636 if (gmask & FRAME_POINTER_MASK)
5638 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5639 reg_offset - 4 - size);
5640 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5643 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5645 if (gmask & RETURN_ADDR_MASK)
5647 fprintf (file, "\tst %s,[%s+%d]\n",
5648 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
5649 if (dwarf2out_do_frame ())
5650 dwarf2out_return_save ("", reg_offset - size);
5653 sparc_flat_save_restore (file, sp_str, reg_offset,
5654 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5655 current_frame_info.fmask,
5656 "st", "std", -size);
5660 /* Subtract %sp in two steps, but make sure there is always a
5661 64 byte register save area, and %sp is properly aligned. */
5662 /* Amount to decrement %sp by, the first time. */
5663 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5664 /* Offset to register save area from %sp. */
5665 unsigned int offset = size1 - (size - reg_offset);
5669 fprintf (file, "\tadd %s,%d,%s\n",
5670 sp_str, -size1, sp_str);
5671 if (gmask & FRAME_POINTER_MASK)
5673 fprintf (file, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t%s# set up frame pointer\n",
5674 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5681 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5682 size1, t1_str, sp_str, t1_str, sp_str);
5683 if (gmask & FRAME_POINTER_MASK)
5685 fprintf (file, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t%s# set up frame pointer\n",
5686 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5691 if (dwarf2out_do_frame ())
5693 char *l = dwarf2out_cfi_label ();
5694 if (gmask & FRAME_POINTER_MASK)
5696 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5697 offset - 4 - size1);
5698 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5701 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5703 if (gmask & RETURN_ADDR_MASK)
5705 fprintf (file, "\tst %s,[%s+%d]\n",
5706 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
5707 if (dwarf2out_do_frame ())
5708 /* offset - size1 == reg_offset - size
5709 if reg_offset were updated above like offset. */
5710 dwarf2out_return_save ("", offset - size1);
5713 sparc_flat_save_restore (file, sp_str, offset,
5714 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5715 current_frame_info.fmask,
5716 "st", "std", -size1);
5717 fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n",
5718 size - size1, t1_str, sp_str, t1_str, sp_str);
5719 if (dwarf2out_do_frame ())
5720 if (! (gmask & FRAME_POINTER_MASK))
5721 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
5725 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
5728 /* Do any necessary cleanup after a function to restore stack, frame,
5732 sparc_flat_output_function_epilogue (file, size)
5736 rtx epilogue_delay = current_function_epilogue_delay_list;
5737 int noepilogue = FALSE;
5739 /* This is only for the human reader. */
5740 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
5742 /* The epilogue does not depend on any registers, but the stack
5743 registers, so we assume that if we have 1 pending nop, it can be
5744 ignored, and 2 it must be filled (2 nops occur for integer
5745 multiply and divide). */
5747 size = SPARC_STACK_ALIGN (size);
5748 size = (!current_frame_info.initialized
5749 ? sparc_flat_compute_frame_size (size)
5750 : current_frame_info.total_size);
5752 if (size == 0 && epilogue_delay == 0)
5754 rtx insn = get_last_insn ();
5756 /* If the last insn was a BARRIER, we don't have to write any code
5757 because a jump (aka return) was put there. */
5758 if (GET_CODE (insn) == NOTE)
5759 insn = prev_nonnote_insn (insn);
5760 if (insn && GET_CODE (insn) == BARRIER)
5766 unsigned int reg_offset = current_frame_info.reg_offset;
5768 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5769 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
5770 char *t1_str = "%g1";
5772 /* In the reload sequence, we don't need to fill the load delay
5773 slots for most of the loads, also see if we can fill the final
5774 delay slot if not otherwise filled by the reload sequence. */
5777 fprintf (file, "\tset %d,%s\n", size, t1_str);
5779 if (frame_pointer_needed)
5782 fprintf (file,"\tsub %s,%s,%s\t\t%s# sp not trusted here\n",
5783 fp_str, t1_str, sp_str, ASM_COMMENT_START);
5785 fprintf (file,"\tsub %s,%d,%s\t\t%s# sp not trusted here\n",
5786 fp_str, size, sp_str, ASM_COMMENT_START);
5789 /* Is the entire register save area offsettable from %sp? */
5790 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5796 /* Restore %sp in two steps, but make sure there is always a
5797 64 byte register save area, and %sp is properly aligned. */
5798 /* Amount to increment %sp by, the first time. */
5799 size1 = ((reg_offset - 64 - 16) + 15) & -16;
5800 /* Offset to register save area from %sp. */
5801 reg_offset = size1 - reg_offset;
5803 fprintf (file, "\tset %d,%s\n\tadd %s,%s,%s\n",
5804 size1, t1_str, sp_str, t1_str, sp_str);
5807 /* We must restore the frame pointer and return address reg first
5808 because they are treated specially by the prologue output code. */
5809 if (current_frame_info.gmask & FRAME_POINTER_MASK)
5811 fprintf (file, "\tld [%s+%d],%s\n",
5812 sp_str, reg_offset, fp_str);
5815 if (current_frame_info.gmask & RETURN_ADDR_MASK)
5817 fprintf (file, "\tld [%s+%d],%s\n",
5818 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
5822 /* Restore any remaining saved registers. */
5823 sparc_flat_save_restore (file, sp_str, reg_offset,
5824 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5825 current_frame_info.fmask,
5828 /* If we had to increment %sp in two steps, record it so the second
5829 restoration in the epilogue finishes up. */
5834 fprintf (file, "\tset %d,%s\n",
5838 if (current_function_returns_struct)
5839 fprintf (file, "\tjmp %%o7+12\n");
5841 fprintf (file, "\tretl\n");
5843 /* If the only register saved is the return address, we need a
5844 nop, unless we have an instruction to put into it. Otherwise
5845 we don't since reloading multiple registers doesn't reference
5846 the register being loaded. */
5852 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
5855 else if (size > 4095)
5856 fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str);
5859 fprintf (file, "\tadd %s,%d,%s\n", sp_str, size, sp_str);
5862 fprintf (file, "\tnop\n");
5865 /* Reset state info for each function. */
5866 current_frame_info = zero_frame_info;
5869 /* Define the number of delay slots needed for the function epilogue.
5871 On the sparc, we need a slot if either no stack has been allocated,
5872 or the only register saved is the return register. */
5875 sparc_flat_epilogue_delay_slots ()
5877 if (!current_frame_info.initialized)
5878 (void) sparc_flat_compute_frame_size (get_frame_size ());
5880 if (current_frame_info.total_size == 0)
5886 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5887 Any single length instruction which doesn't reference the stack or frame
5891 sparc_flat_eligible_for_epilogue_delay (trial, slot)
5895 rtx pat = PATTERN (trial);
5897 if (get_attr_length (trial) != 1)
5900 /* If %g0 is live, there are lots of things we can't handle.
5901 Rather than trying to find them all now, let's punt and only
5902 optimize things as necessary. */
5906 if (! reg_mentioned_p (stack_pointer_rtx, pat)
5907 && ! reg_mentioned_p (frame_pointer_rtx, pat))
5913 /* Adjust the cost of a scheduling dependency. Return the new cost of
5914 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5917 supersparc_adjust_cost (insn, link, dep_insn, cost)
5923 enum attr_type insn_type;
5925 if (! recog_memoized (insn))
5928 insn_type = get_attr_type (insn);
5930 if (REG_NOTE_KIND (link) == 0)
5932 /* Data dependency; DEP_INSN writes a register that INSN reads some
5935 /* if a load, then the dependence must be on the memory address;
5936 add an extra 'cycle'. Note that the cost could be two cycles
5937 if the reg was written late in an instruction group; we can't tell
5939 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
5942 /* Get the delay only if the address of the store is the dependence. */
5943 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
5945 rtx pat = PATTERN(insn);
5946 rtx dep_pat = PATTERN (dep_insn);
5948 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
5949 return cost; /* This shouldn't happen! */
5951 /* The dependency between the two instructions was on the data that
5952 is being stored. Assume that this implies that the address of the
5953 store is not dependent. */
5954 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
5957 return cost + 3; /* An approximation. */
5960 /* A shift instruction cannot receive its data from an instruction
5961 in the same cycle; add a one cycle penalty. */
5962 if (insn_type == TYPE_SHIFT)
5963 return cost + 3; /* Split before cascade into shift. */
5967 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5968 INSN writes some cycles later. */
5970 /* These are only significant for the fpu unit; writing a fp reg before
5971 the fpu has finished with it stalls the processor. */
5973 /* Reusing an integer register causes no problems. */
5974 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)