2008-04-03 Jan Hubicka <jh@suse.cz>

[pf3gnuchains/gcc-fork.git] / gcc / config / sparc / sparc.c

/* Subroutines for insn-output.c for SPARC.
   Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   Free Software Foundation, Inc.
   Contributed by Michael Tiemann (tiemann@cygnus.com)
   64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
   at Cygnus Support.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "tree.h"
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"
#include "insn-codes.h"
#include "conditions.h"
#include "output.h"
#include "insn-attr.h"
#include "flags.h"
#include "function.h"
#include "expr.h"
#include "optabs.h"
#include "recog.h"
#include "toplev.h"
#include "ggc.h"
#include "tm_p.h"
#include "debug.h"
#include "target.h"
#include "target-def.h"
#include "cfglayout.h"
#include "tree-gimple.h"
#include "langhooks.h"
#include "params.h"
#include "df.h"

/* Processor costs */
static const
struct processor_costs cypress_costs = {
  COSTS_N_INSNS (2), /* int load */
  COSTS_N_INSNS (2), /* int signed load */
  COSTS_N_INSNS (2), /* int zeroed load */
  COSTS_N_INSNS (2), /* float load */
  COSTS_N_INSNS (5), /* fmov, fneg, fabs */
  COSTS_N_INSNS (5), /* fadd, fsub */
  COSTS_N_INSNS (1), /* fcmp */
  COSTS_N_INSNS (1), /* fmov, fmovr */
  COSTS_N_INSNS (7), /* fmul */
  COSTS_N_INSNS (37), /* fdivs */
  COSTS_N_INSNS (37), /* fdivd */
  COSTS_N_INSNS (63), /* fsqrts */
  COSTS_N_INSNS (63), /* fsqrtd */
  COSTS_N_INSNS (1), /* imul */
  COSTS_N_INSNS (1), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (1), /* idiv */
  COSTS_N_INSNS (1), /* idivX */
  COSTS_N_INSNS (1), /* movcc/movr */
  0, /* shift penalty */
};

static const
struct processor_costs supersparc_costs = {
  COSTS_N_INSNS (1), /* int load */
  COSTS_N_INSNS (1), /* int signed load */
  COSTS_N_INSNS (1), /* int zeroed load */
  COSTS_N_INSNS (0), /* float load */
  COSTS_N_INSNS (3), /* fmov, fneg, fabs */
  COSTS_N_INSNS (3), /* fadd, fsub */
  COSTS_N_INSNS (3), /* fcmp */
  COSTS_N_INSNS (1), /* fmov, fmovr */
  COSTS_N_INSNS (3), /* fmul */
  COSTS_N_INSNS (6), /* fdivs */
  COSTS_N_INSNS (9), /* fdivd */
  COSTS_N_INSNS (12), /* fsqrts */
  COSTS_N_INSNS (12), /* fsqrtd */
  COSTS_N_INSNS (4), /* imul */
  COSTS_N_INSNS (4), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (4), /* idiv */
  COSTS_N_INSNS (4), /* idivX */
  COSTS_N_INSNS (1), /* movcc/movr */
  1, /* shift penalty */
};

static const
struct processor_costs hypersparc_costs = {
  COSTS_N_INSNS (1), /* int load */
  COSTS_N_INSNS (1), /* int signed load */
  COSTS_N_INSNS (1), /* int zeroed load */
  COSTS_N_INSNS (1), /* float load */
  COSTS_N_INSNS (1), /* fmov, fneg, fabs */
  COSTS_N_INSNS (1), /* fadd, fsub */
  COSTS_N_INSNS (1), /* fcmp */
  COSTS_N_INSNS (1), /* fmov, fmovr */
  COSTS_N_INSNS (1), /* fmul */
  COSTS_N_INSNS (8), /* fdivs */
  COSTS_N_INSNS (12), /* fdivd */
  COSTS_N_INSNS (17), /* fsqrts */
  COSTS_N_INSNS (17), /* fsqrtd */
  COSTS_N_INSNS (17), /* imul */
  COSTS_N_INSNS (17), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (17), /* idiv */
  COSTS_N_INSNS (17), /* idivX */
  COSTS_N_INSNS (1), /* movcc/movr */
  0, /* shift penalty */
};

static const
struct processor_costs sparclet_costs = {
  COSTS_N_INSNS (3), /* int load */
  COSTS_N_INSNS (3), /* int signed load */
  COSTS_N_INSNS (1), /* int zeroed load */
  COSTS_N_INSNS (1), /* float load */
  COSTS_N_INSNS (1), /* fmov, fneg, fabs */
  COSTS_N_INSNS (1), /* fadd, fsub */
  COSTS_N_INSNS (1), /* fcmp */
  COSTS_N_INSNS (1), /* fmov, fmovr */
  COSTS_N_INSNS (1), /* fmul */
  COSTS_N_INSNS (1), /* fdivs */
  COSTS_N_INSNS (1), /* fdivd */
  COSTS_N_INSNS (1), /* fsqrts */
  COSTS_N_INSNS (1), /* fsqrtd */
  COSTS_N_INSNS (5), /* imul */
  COSTS_N_INSNS (5), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (5), /* idiv */
  COSTS_N_INSNS (5), /* idivX */
  COSTS_N_INSNS (1), /* movcc/movr */
  0, /* shift penalty */
};

static const
struct processor_costs ultrasparc_costs = {
  COSTS_N_INSNS (2), /* int load */
  COSTS_N_INSNS (3), /* int signed load */
  COSTS_N_INSNS (2), /* int zeroed load */
  COSTS_N_INSNS (2), /* float load */
  COSTS_N_INSNS (1), /* fmov, fneg, fabs */
  COSTS_N_INSNS (4), /* fadd, fsub */
  COSTS_N_INSNS (1), /* fcmp */
  COSTS_N_INSNS (2), /* fmov, fmovr */
  COSTS_N_INSNS (4), /* fmul */
  COSTS_N_INSNS (13), /* fdivs */
  COSTS_N_INSNS (23), /* fdivd */
  COSTS_N_INSNS (13), /* fsqrts */
  COSTS_N_INSNS (23), /* fsqrtd */
  COSTS_N_INSNS (4), /* imul */
  COSTS_N_INSNS (4), /* imulX */
  2, /* imul bit factor */
  COSTS_N_INSNS (37), /* idiv */
  COSTS_N_INSNS (68), /* idivX */
  COSTS_N_INSNS (2), /* movcc/movr */
  2, /* shift penalty */
};

static const
struct processor_costs ultrasparc3_costs = {
  COSTS_N_INSNS (2), /* int load */
  COSTS_N_INSNS (3), /* int signed load */
  COSTS_N_INSNS (3), /* int zeroed load */
  COSTS_N_INSNS (2), /* float load */
  COSTS_N_INSNS (3), /* fmov, fneg, fabs */
  COSTS_N_INSNS (4), /* fadd, fsub */
  COSTS_N_INSNS (5), /* fcmp */
  COSTS_N_INSNS (3), /* fmov, fmovr */
  COSTS_N_INSNS (4), /* fmul */
  COSTS_N_INSNS (17), /* fdivs */
  COSTS_N_INSNS (20), /* fdivd */
  COSTS_N_INSNS (20), /* fsqrts */
  COSTS_N_INSNS (29), /* fsqrtd */
  COSTS_N_INSNS (6), /* imul */
  COSTS_N_INSNS (6), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (40), /* idiv */
  COSTS_N_INSNS (71), /* idivX */
  COSTS_N_INSNS (2), /* movcc/movr */
  0, /* shift penalty */
};

static const
struct processor_costs niagara_costs = {
  COSTS_N_INSNS (3), /* int load */
  COSTS_N_INSNS (3), /* int signed load */
  COSTS_N_INSNS (3), /* int zeroed load */
  COSTS_N_INSNS (9), /* float load */
  COSTS_N_INSNS (8), /* fmov, fneg, fabs */
  COSTS_N_INSNS (8), /* fadd, fsub */
  COSTS_N_INSNS (26), /* fcmp */
  COSTS_N_INSNS (8), /* fmov, fmovr */
  COSTS_N_INSNS (29), /* fmul */
  COSTS_N_INSNS (54), /* fdivs */
  COSTS_N_INSNS (83), /* fdivd */
  COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
  COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
  COSTS_N_INSNS (11), /* imul */
  COSTS_N_INSNS (11), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (72), /* idiv */
  COSTS_N_INSNS (72), /* idivX */
  COSTS_N_INSNS (1), /* movcc/movr */
  0, /* shift penalty */
};

static const
struct processor_costs niagara2_costs = {
  COSTS_N_INSNS (3), /* int load */
  COSTS_N_INSNS (3), /* int signed load */
  COSTS_N_INSNS (3), /* int zeroed load */
  COSTS_N_INSNS (3), /* float load */
  COSTS_N_INSNS (6), /* fmov, fneg, fabs */
  COSTS_N_INSNS (6), /* fadd, fsub */
  COSTS_N_INSNS (6), /* fcmp */
  COSTS_N_INSNS (6), /* fmov, fmovr */
  COSTS_N_INSNS (6), /* fmul */
  COSTS_N_INSNS (19), /* fdivs */
  COSTS_N_INSNS (33), /* fdivd */
  COSTS_N_INSNS (19), /* fsqrts */
  COSTS_N_INSNS (33), /* fsqrtd */
  COSTS_N_INSNS (5), /* imul */
  COSTS_N_INSNS (5), /* imulX */
  0, /* imul bit factor */
  COSTS_N_INSNS (31), /* idiv, average of 12 - 41 cycle range */
  COSTS_N_INSNS (31), /* idivX, average of 12 - 41 cycle range */
  COSTS_N_INSNS (1), /* movcc/movr */
  0, /* shift penalty */
};

const struct processor_costs *sparc_costs = &cypress_costs;

#ifdef HAVE_AS_RELAX_OPTION
/* If 'as' and 'ld' are relaxing tail call insns into branch always, use
   "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
   With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
   somebody does not branch between the sethi and jmp.  */
#define LEAF_SIBCALL_SLOT_RESERVED_P 1
#else
#define LEAF_SIBCALL_SLOT_RESERVED_P \
  ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
#endif

/* Global variables for machine-dependent things.  */

/* Size of frame.  Need to know this to emit return insns from leaf procedures.
   ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
   reload pass.  This is important as the value is later used for scheduling
   (to see what can go in a delay slot).
   APPARENT_FSIZE is the size of the stack less the register save area and less
   the outgoing argument area.  It is used when saving call preserved regs.  */
static HOST_WIDE_INT apparent_fsize;
static HOST_WIDE_INT actual_fsize;

/* Number of live general or floating point registers needed to be
   saved (as 4-byte quantities).  */
static int num_gfregs;

/* The alias set for prologue/epilogue register save/restore.  */
static GTY(()) alias_set_type sparc_sr_alias_set;

/* The alias set for the structure return value.  */
static GTY(()) alias_set_type struct_value_alias_set;

/* Save the operands last given to a compare for use when we
   generate a scc or bcc insn.  */
rtx sparc_compare_op0, sparc_compare_op1, sparc_compare_emitted;

/* Vector to say how input registers are mapped to output registers.
   HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
   eliminate it.  You must use -fomit-frame-pointer to get that.  */
char leaf_reg_remap[] =
{ 0, 1, 2, 3, 4, 5, 6, 7,
  -1, -1, -1, -1, -1, -1, 14, -1,
  -1, -1, -1, -1, -1, -1, -1, -1,
  8, 9, 10, 11, 12, 13, -1, 15,

  32, 33, 34, 35, 36, 37, 38, 39,
  40, 41, 42, 43, 44, 45, 46, 47,
  48, 49, 50, 51, 52, 53, 54, 55,
  56, 57, 58, 59, 60, 61, 62, 63,
  64, 65, 66, 67, 68, 69, 70, 71,
  72, 73, 74, 75, 76, 77, 78, 79,
  80, 81, 82, 83, 84, 85, 86, 87,
  88, 89, 90, 91, 92, 93, 94, 95,
  96, 97, 98, 99, 100};

/* Vector, indexed by hard register number, which contains 1
   for a register that is allowable in a candidate for leaf
   function treatment.  */
char sparc_leaf_regs[] =
{ 1, 1, 1, 1, 1, 1, 1, 1,
  0, 0, 0, 0, 0, 0, 1, 0,
  0, 0, 0, 0, 0, 0, 0, 0,
  1, 1, 1, 1, 1, 1, 0, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1, 1, 1, 1,
  1, 1, 1, 1, 1};

struct machine_function GTY(())
{
  /* Some local-dynamic TLS symbol name.  */
  const char *some_ld_name;

  /* True if the current function is leaf and uses only leaf regs,
     so that the SPARC leaf function optimization can be applied.
     Private version of current_function_uses_only_leaf_regs, see
     sparc_expand_prologue for the rationale.  */
  int leaf_function_p;

  /* True if the data calculated by sparc_expand_prologue are valid.  */
  bool prologue_data_valid_p;
};

#define sparc_leaf_function_p  cfun->machine->leaf_function_p
#define sparc_prologue_data_valid_p  cfun->machine->prologue_data_valid_p

/* Register we pretend to think the frame pointer is allocated to.
   Normally, this is %fp, but if we are in a leaf procedure, this
   is %sp+"something".  We record "something" separately as it may
   be too big for reg+constant addressing.  */
static rtx frame_base_reg;
static HOST_WIDE_INT frame_base_offset;

/* 1 if the next opcode is to be specially indented.  */
int sparc_indent_opcode = 0;

static bool sparc_handle_option (size_t, const char *, int);
static void sparc_init_modes (void);
static void scan_record_type (tree, int *, int *, int *);
static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
                                tree, int, int, int *, int *);

static int supersparc_adjust_cost (rtx, rtx, rtx, int);
static int hypersparc_adjust_cost (rtx, rtx, rtx, int);

static void sparc_output_addr_vec (rtx);
static void sparc_output_addr_diff_vec (rtx);
static void sparc_output_deferred_case_vectors (void);
static rtx sparc_builtin_saveregs (void);
static int epilogue_renumber (rtx *, int);
static bool sparc_assemble_integer (rtx, unsigned int, int);
static int set_extends (rtx);
static void emit_pic_helper (void);
static void load_pic_register (bool);
static int save_or_restore_regs (int, int, rtx, int, int);
static void emit_save_or_restore_regs (int);
static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
#ifdef OBJECT_FORMAT_ELF
static void sparc_elf_asm_named_section (const char *, unsigned int, tree);
#endif

static int sparc_adjust_cost (rtx, rtx, rtx, int);
static int sparc_issue_rate (void);
static void sparc_sched_init (FILE *, int, int);
static int sparc_use_sched_lookahead (void);

static void emit_soft_tfmode_libcall (const char *, int, rtx *);
static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
static void emit_hard_tfmode_operation (enum rtx_code, rtx *);

static bool sparc_function_ok_for_sibcall (tree, tree);
static void sparc_init_libfuncs (void);
static void sparc_init_builtins (void);
static void sparc_vis_init_builtins (void);
static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static tree sparc_fold_builtin (tree, tree, bool);
static int sparc_vis_mul8x16 (int, int);
static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
                                   HOST_WIDE_INT, tree);
static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
                                       HOST_WIDE_INT, const_tree);
static struct machine_function * sparc_init_machine_status (void);
static bool sparc_cannot_force_const_mem (rtx);
static rtx sparc_tls_get_addr (void);
static rtx sparc_tls_got (void);
static const char *get_some_local_dynamic_name (void);
static int get_some_local_dynamic_name_1 (rtx *, void *);
static bool sparc_rtx_costs (rtx, int, int, int *);
static bool sparc_promote_prototypes (const_tree);
static rtx sparc_struct_value_rtx (tree, int);
static bool sparc_return_in_memory (const_tree, const_tree);
static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
static void sparc_va_start (tree, rtx);
static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
static bool sparc_vector_mode_supported_p (enum machine_mode);
static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
                                     enum machine_mode, const_tree, bool);
static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
                                    enum machine_mode, tree, bool);
static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
static void sparc_file_end (void);
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
static const char *sparc_mangle_type (const_tree);
#endif
#ifdef SUBTARGET_ATTRIBUTE_TABLE
const struct attribute_spec sparc_attribute_table[];
#endif
\f
/* Option handling.  */

/* Parsed value.  */
enum cmodel sparc_cmodel;

char sparc_hard_reg_printed[8];

struct sparc_cpu_select sparc_select[] =
{
  /* switch     name,           tune    arch */
  { (char *)0,  "default",      1,      1 },
  { (char *)0,  "-mcpu=",       1,      1 },
  { (char *)0,  "-mtune=",      1,      0 },
  { 0, 0, 0, 0 }
};

/* CPU type.  This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx.  */
enum processor_type sparc_cpu;

/* Whether\fan FPU option was specified.  */
static bool fpu_option_set = false;

/* Initialize the GCC target structure.  */

/* The sparc default is to use .half rather than .short for aligned
   HI objects.  Use .word instead of .long on non-ELF systems.  */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
#ifndef OBJECT_FORMAT_ELF
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
#endif

#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"

/* The target hook has to handle DI-mode values.  */
#undef TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER sparc_assemble_integer

#undef TARGET_ASM_FUNCTION_PROLOGUE
#define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue

#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
#undef TARGET_SCHED_INIT
#define TARGET_SCHED_INIT sparc_sched_init
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead

#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall

#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS sparc_init_builtins

#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN sparc_expand_builtin
#undef TARGET_FOLD_BUILTIN
#define TARGET_FOLD_BUILTIN sparc_fold_builtin

#if TARGET_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#endif

#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem

#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk

#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS sparc_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_0

/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
   no-op for TARGET_ARCH32 this is ok.  Otherwise we'd need to add a runtime
   test for this value.  */
#undef TARGET_PROMOTE_FUNCTION_ARGS
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true

/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
   no-op for TARGET_ARCH32 this is ok.  Otherwise we'd need to add a runtime
   test for this value.  */
#undef TARGET_PROMOTE_FUNCTION_RETURN
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true

#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes

#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes

#undef TARGET_EXPAND_BUILTIN_SAVEREGS
#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming

#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg

#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p

#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec

#ifdef SUBTARGET_INSERT_ATTRIBUTES
#undef TARGET_INSERT_ATTRIBUTES
#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
#endif

#ifdef SUBTARGET_ATTRIBUTE_TABLE
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
#endif

#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING

#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION sparc_handle_option

#if TARGET_GNU_TLS
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
#define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
#endif

#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_END sparc_file_end

#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
#undef TARGET_MANGLE_TYPE
#define TARGET_MANGLE_TYPE sparc_mangle_type
#endif

struct gcc_target targetm = TARGET_INITIALIZER;

/* Implement TARGET_HANDLE_OPTION.  */

static bool
sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
{
  switch (code)
    {
    case OPT_mfpu:
    case OPT_mhard_float:
    case OPT_msoft_float:
      fpu_option_set = true;
      break;

    case OPT_mcpu_:
      sparc_select[1].string = arg;
      break;

    case OPT_mtune_:
      sparc_select[2].string = arg;
      break;
    }

  return true;
}

/* Validate and override various options, and do some machine dependent
   initialization.  */

void
sparc_override_options (void)
{
  static struct code_model {
    const char *const name;
    const int value;
  } const cmodels[] = {
    { "32", CM_32 },
    { "medlow", CM_MEDLOW },
    { "medmid", CM_MEDMID },
    { "medany", CM_MEDANY },
    { "embmedany", CM_EMBMEDANY },
    { 0, 0 }
  };
  const struct code_model *cmodel;
  /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=.  */
  static struct cpu_default {
    const int cpu;
    const char *const name;
  } const cpu_default[] = {
    /* There must be one entry here for each TARGET_CPU value.  */
    { TARGET_CPU_sparc, "cypress" },
    { TARGET_CPU_sparclet, "tsc701" },
    { TARGET_CPU_sparclite, "f930" },
    { TARGET_CPU_v8, "v8" },
    { TARGET_CPU_hypersparc, "hypersparc" },
    { TARGET_CPU_sparclite86x, "sparclite86x" },
    { TARGET_CPU_supersparc, "supersparc" },
    { TARGET_CPU_v9, "v9" },
    { TARGET_CPU_ultrasparc, "ultrasparc" },
    { TARGET_CPU_ultrasparc3, "ultrasparc3" },
    { TARGET_CPU_niagara, "niagara" },
    { TARGET_CPU_niagara2, "niagara2" },
    { 0, 0 }
  };
  const struct cpu_default *def;
  /* Table of values for -m{cpu,tune}=.  */
  static struct cpu_table {
    const char *const name;
    const enum processor_type processor;
    const int disable;
    const int enable;
  } const cpu_table[] = {
    { "v7",         PROCESSOR_V7, MASK_ISA, 0 },
    { "cypress",    PROCESSOR_CYPRESS, MASK_ISA, 0 },
    { "v8",         PROCESSOR_V8, MASK_ISA, MASK_V8 },
    /* TI TMS390Z55 supersparc */
    { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
    { "sparclite",  PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
    /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
       The Fujitsu MB86934 is the recent sparclite chip, with an fpu.  */
    { "f930",       PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
    { "f934",       PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
    { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
    { "sparclite86x",  PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
      MASK_SPARCLITE },
    { "sparclet",   PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
    /* TEMIC sparclet */
    { "tsc701",     PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
    { "v9",         PROCESSOR_V9, MASK_ISA, MASK_V9 },
    /* TI ultrasparc I, II, IIi */
    { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
    /* Although insns using %y are deprecated, it is a clear win on current
       ultrasparcs.  */
                                                    |MASK_DEPRECATED_V8_INSNS},
    /* TI ultrasparc III */
    /* ??? Check if %y issue still holds true in ultra3.  */
    { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
    /* UltraSPARC T1 */
    { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
    { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9},
    { 0, 0, 0, 0 }
  };
  const struct cpu_table *cpu;
  const struct sparc_cpu_select *sel;
  int fpu;
  
#ifndef SPARC_BI_ARCH
  /* Check for unsupported architecture size.  */
  if (! TARGET_64BIT != DEFAULT_ARCH32_P)
    error ("%s is not supported by this configuration",
           DEFAULT_ARCH32_P ? "-m64" : "-m32");
#endif

  /* We force all 64bit archs to use 128 bit long double */
  if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
    {
      error ("-mlong-double-64 not allowed with -m64");
      target_flags |= MASK_LONG_DOUBLE_128;
    }

  /* Code model selection.  */
  sparc_cmodel = SPARC_DEFAULT_CMODEL;
  
#ifdef SPARC_BI_ARCH
  if (TARGET_ARCH32)
    sparc_cmodel = CM_32;
#endif

  if (sparc_cmodel_string != NULL)
    {
      if (TARGET_ARCH64)
        {
          for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
            if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
              break;
          if (cmodel->name == NULL)
            error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
          else
            sparc_cmodel = cmodel->value;
        }
      else
        error ("-mcmodel= is not supported on 32 bit systems");
    }

  fpu = target_flags & MASK_FPU; /* save current -mfpu status */

  /* Set the default CPU.  */
  for (def = &cpu_default[0]; def->name; ++def)
    if (def->cpu == TARGET_CPU_DEFAULT)
      break;
  gcc_assert (def->name);
  sparc_select[0].string = def->name;

  for (sel = &sparc_select[0]; sel->name; ++sel)
    {
      if (sel->string)
        {
          for (cpu = &cpu_table[0]; cpu->name; ++cpu)
            if (! strcmp (sel->string, cpu->name))
              {
                if (sel->set_tune_p)
                  sparc_cpu = cpu->processor;

                if (sel->set_arch_p)
                  {
                    target_flags &= ~cpu->disable;
                    target_flags |= cpu->enable;
                  }
                break;
              }

          if (! cpu->name)
            error ("bad value (%s) for %s switch", sel->string, sel->name);
        }
    }

  /* If -mfpu or -mno-fpu was explicitly used, don't override with
     the processor default.  */
  if (fpu_option_set)
    target_flags = (target_flags & ~MASK_FPU) | fpu;

  /* Don't allow -mvis if FPU is disabled.  */
  if (! TARGET_FPU)
    target_flags &= ~MASK_VIS;

  /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
     are available.
     -m64 also implies v9.  */
  if (TARGET_VIS || TARGET_ARCH64)
    {
      target_flags |= MASK_V9;
      target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
    }

  /* Use the deprecated v8 insns for sparc64 in 32 bit mode.  */
  if (TARGET_V9 && TARGET_ARCH32)
    target_flags |= MASK_DEPRECATED_V8_INSNS;

  /* V8PLUS requires V9, makes no sense in 64 bit mode.  */
  if (! TARGET_V9 || TARGET_ARCH64)
    target_flags &= ~MASK_V8PLUS;

  /* Don't use stack biasing in 32 bit mode.  */
  if (TARGET_ARCH32)
    target_flags &= ~MASK_STACK_BIAS;
    
  /* Supply a default value for align_functions.  */
  if (align_functions == 0
      && (sparc_cpu == PROCESSOR_ULTRASPARC
          || sparc_cpu == PROCESSOR_ULTRASPARC3
          || sparc_cpu == PROCESSOR_NIAGARA
          || sparc_cpu == PROCESSOR_NIAGARA2))
    align_functions = 32;

  /* Validate PCC_STRUCT_RETURN.  */
  if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
    flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);

  /* Only use .uaxword when compiling for a 64-bit target.  */
  if (!TARGET_ARCH64)
    targetm.asm_out.unaligned_op.di = NULL;

  /* Do various machine dependent initializations.  */
  sparc_init_modes ();

  /* Acquire unique alias sets for our private stuff.  */
  sparc_sr_alias_set = new_alias_set ();
  struct_value_alias_set = new_alias_set ();

  /* Set up function hooks.  */
  init_machine_status = sparc_init_machine_status;

  switch (sparc_cpu)
    {
    case PROCESSOR_V7:
    case PROCESSOR_CYPRESS:
      sparc_costs = &cypress_costs;
      break;
    case PROCESSOR_V8:
    case PROCESSOR_SPARCLITE:
    case PROCESSOR_SUPERSPARC:
      sparc_costs = &supersparc_costs;
      break;
    case PROCESSOR_F930:
    case PROCESSOR_F934:
    case PROCESSOR_HYPERSPARC:
    case PROCESSOR_SPARCLITE86X:
      sparc_costs = &hypersparc_costs;
      break;
    case PROCESSOR_SPARCLET:
    case PROCESSOR_TSC701:
      sparc_costs = &sparclet_costs;
      break;
    case PROCESSOR_V9:
    case PROCESSOR_ULTRASPARC:
      sparc_costs = &ultrasparc_costs;
      break;
    case PROCESSOR_ULTRASPARC3:
      sparc_costs = &ultrasparc3_costs;
      break;
    case PROCESSOR_NIAGARA:
      sparc_costs = &niagara_costs;
      break;
    case PROCESSOR_NIAGARA2:
      sparc_costs = &niagara2_costs;
      break;
    };

#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
  if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
    target_flags |= MASK_LONG_DOUBLE_128;
#endif

  if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
    set_param_value ("simultaneous-prefetches",
                     ((sparc_cpu == PROCESSOR_ULTRASPARC
                       || sparc_cpu == PROCESSOR_NIAGARA
                       || sparc_cpu == PROCESSOR_NIAGARA2)
                      ? 2
                      : (sparc_cpu == PROCESSOR_ULTRASPARC3
                         ? 8 : 3)));
  if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
    set_param_value ("l1-cache-line-size", 
                     ((sparc_cpu == PROCESSOR_ULTRASPARC
                       || sparc_cpu == PROCESSOR_ULTRASPARC3
                       || sparc_cpu == PROCESSOR_NIAGARA
                       || sparc_cpu == PROCESSOR_NIAGARA2)
                      ? 64 : 32));
}
\f
#ifdef SUBTARGET_ATTRIBUTE_TABLE
/* Table of valid machine attributes.  */
const struct attribute_spec sparc_attribute_table[] =
{
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
  SUBTARGET_ATTRIBUTE_TABLE,
  { NULL,        0, 0, false, false, false, NULL }
};
#endif
\f
/* Miscellaneous utilities.  */

/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
   or branch on register contents instructions.  */

int
v9_regcmp_p (enum rtx_code code)
{
  return (code == EQ || code == NE || code == GE || code == LT
          || code == LE || code == GT);
}

/* Nonzero if OP is a floating point constant which can
   be loaded into an integer register using a single
   sethi instruction.  */

int
fp_sethi_p (rtx op)
{
  if (GET_CODE (op) == CONST_DOUBLE)
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
    }

  return 0;
}

/* Nonzero if OP is a floating point constant which can
   be loaded into an integer register using a single
   mov instruction.  */

int
fp_mov_p (rtx op)
{
  if (GET_CODE (op) == CONST_DOUBLE)
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      return SPARC_SIMM13_P (i);
    }

  return 0;
}

/* Nonzero if OP is a floating point constant which can
   be loaded into an integer register using a high/losum
   instruction sequence.  */

int
fp_high_losum_p (rtx op)
{
  /* The constraints calling this should only be in
     SFmode move insns, so any constant which cannot
     be moved using a single insn will do.  */
  if (GET_CODE (op) == CONST_DOUBLE)
    {
      REAL_VALUE_TYPE r;
      long i;

      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
      REAL_VALUE_TO_TARGET_SINGLE (r, i);
      return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
    }

  return 0;
}

/* Expand a move instruction.  Return true if all work is done.  */

bool
sparc_expand_move (enum machine_mode mode, rtx *operands)
{
  /* Handle sets of MEM first.  */
  if (GET_CODE (operands[0]) == MEM)
    {
      /* 0 is a register (or a pair of registers) on SPARC.  */
      if (register_or_zero_operand (operands[1], mode))
        return false;

      if (!reload_in_progress)
        {
          operands[0] = validize_mem (operands[0]);
          operands[1] = force_reg (mode, operands[1]);
        }
    }

  /* Fixup TLS cases.  */
  if (TARGET_HAVE_TLS
      && CONSTANT_P (operands[1])
      && GET_CODE (operands[1]) != HIGH
      && sparc_tls_referenced_p (operands [1]))
    {
      rtx sym = operands[1];
      rtx addend = NULL;

      if (GET_CODE (sym) == CONST && GET_CODE (XEXP (sym, 0)) == PLUS)
        {
          addend = XEXP (XEXP (sym, 0), 1);
          sym = XEXP (XEXP (sym, 0), 0);
        }

      gcc_assert (SPARC_SYMBOL_REF_TLS_P (sym));

      sym = legitimize_tls_address (sym);
      if (addend)
        {
          sym = gen_rtx_PLUS (mode, sym, addend);
          sym = force_operand (sym, operands[0]);
        }
      operands[1] = sym;
    }
 
  /* Fixup PIC cases.  */
  if (flag_pic && CONSTANT_P (operands[1]))
    {
      if (pic_address_needs_scratch (operands[1]))
        operands[1] = legitimize_pic_address (operands[1], mode, 0);

      /* VxWorks does not impose a fixed gap between segments; the run-time
         gap can be different from the object-file gap.  We therefore can't
         assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
         are absolutely sure that X is in the same segment as the GOT.
         Unfortunately, the flexibility of linker scripts means that we
         can't be sure of that in general, so assume that _G_O_T_-relative
         accesses are never valid on VxWorks.  */
      if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP)
        {
          if (mode == SImode)
            {
              emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
              return true;
            }

          if (mode == DImode)
            {
              gcc_assert (TARGET_ARCH64);
              emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
              return true;
            }
        }

      if (symbolic_operand (operands[1], mode))
        {
          operands[1] = legitimize_pic_address (operands[1],
                                                mode,
                                                (reload_in_progress ?
                                                 operands[0] :
                                                 NULL_RTX));
          return false;
        }
    }

  /* If we are trying to toss an integer constant into FP registers,
     or loading a FP or vector constant, force it into memory.  */
  if (CONSTANT_P (operands[1])
      && REG_P (operands[0])
      && (SPARC_FP_REG_P (REGNO (operands[0]))
          || SCALAR_FLOAT_MODE_P (mode)
          || VECTOR_MODE_P (mode)))
    {
      /* emit_group_store will send such bogosity to us when it is
         not storing directly into memory.  So fix this up to avoid
         crashes in output_constant_pool.  */
      if (operands [1] == const0_rtx)
        operands[1] = CONST0_RTX (mode);

      /* We can clear FP registers if TARGET_VIS, and always other regs.  */
      if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
          && const_zero_operand (operands[1], mode))
        return false;

      if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
          /* We are able to build any SF constant in integer registers
             with at most 2 instructions.  */
          && (mode == SFmode
              /* And any DF constant in integer registers.  */
              || (mode == DFmode
                  && (reload_completed || reload_in_progress))))
        return false;

      operands[1] = force_const_mem (mode, operands[1]);
      if (!reload_in_progress)
        operands[1] = validize_mem (operands[1]);
      return false;
    }

  /* Accept non-constants and valid constants unmodified.  */
  if (!CONSTANT_P (operands[1])
      || GET_CODE (operands[1]) == HIGH
      || input_operand (operands[1], mode))
    return false;

  switch (mode)
    {
    case QImode:
      /* All QImode constants require only one insn, so proceed.  */
      break;

    case HImode:
    case SImode:
      sparc_emit_set_const32 (operands[0], operands[1]);
      return true;

    case DImode:
      /* input_operand should have filtered out 32-bit mode.  */
      sparc_emit_set_const64 (operands[0], operands[1]);
      return true;
    
    default:
      gcc_unreachable ();
    }

  return false;
}

/* Load OP1, a 32-bit constant, into OP0, a register.
   We know it can't be done in one insn when we get
   here, the move expander guarantees this.  */

void
sparc_emit_set_const32 (rtx op0, rtx op1)
{
  enum machine_mode mode = GET_MODE (op0);
  rtx temp;

  if (reload_in_progress || reload_completed)
    temp = op0;
  else
    temp = gen_reg_rtx (mode);

  if (GET_CODE (op1) == CONST_INT)
    {
      gcc_assert (!small_int_operand (op1, mode)
                  && !const_high_operand (op1, mode));

      /* Emit them as real moves instead of a HIGH/LO_SUM,
         this way CSE can see everything and reuse intermediate
         values if it wants.  */
      emit_insn (gen_rtx_SET (VOIDmode, temp,
                              GEN_INT (INTVAL (op1)
                                & ~(HOST_WIDE_INT)0x3ff)));

      emit_insn (gen_rtx_SET (VOIDmode,
                              op0,
                              gen_rtx_IOR (mode, temp,
                                           GEN_INT (INTVAL (op1) & 0x3ff))));
    }
  else
    {
      /* A symbol, emit in the traditional way.  */
      emit_insn (gen_rtx_SET (VOIDmode, temp,
                              gen_rtx_HIGH (mode, op1)));
      emit_insn (gen_rtx_SET (VOIDmode,
                              op0, gen_rtx_LO_SUM (mode, temp, op1)));
    }
}

/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
   If TEMP is nonzero, we are forbidden to use any other scratch
   registers.  Otherwise, we are allowed to generate them as needed.

   Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
   or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns).  */

void
sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
{
  rtx temp1, temp2, temp3, temp4, temp5;
  rtx ti_temp = 0;

  if (temp && GET_MODE (temp) == TImode)
    {
      ti_temp = temp;
      temp = gen_rtx_REG (DImode, REGNO (temp));
    }

  /* SPARC-V9 code-model support.  */
  switch (sparc_cmodel)
    {
    case CM_MEDLOW:
      /* The range spanned by all instructions in the object is less
         than 2^31 bytes (2GB) and the distance from any instruction
         to the location of the label _GLOBAL_OFFSET_TABLE_ is less
         than 2^31 bytes (2GB).

         The executable must be in the low 4TB of the virtual address
         space.

         sethi  %hi(symbol), %temp1
         or     %temp1, %lo(symbol), %reg  */
      if (temp)
        temp1 = temp;  /* op0 is allowed.  */
      else
        temp1 = gen_reg_rtx (DImode);

      emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
      emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
      break;

    case CM_MEDMID:
      /* The range spanned by all instructions in the object is less
         than 2^31 bytes (2GB) and the distance from any instruction
         to the location of the label _GLOBAL_OFFSET_TABLE_ is less
         than 2^31 bytes (2GB).

         The executable must be in the low 16TB of the virtual address
         space.

         sethi  %h44(symbol), %temp1
         or     %temp1, %m44(symbol), %temp2
         sllx   %temp2, 12, %temp3
         or     %temp3, %l44(symbol), %reg  */
      if (temp)
        {
          temp1 = op0;
          temp2 = op0;
          temp3 = temp;  /* op0 is allowed.  */
        }
      else
        {
          temp1 = gen_reg_rtx (DImode);
          temp2 = gen_reg_rtx (DImode);
          temp3 = gen_reg_rtx (DImode);
        }

      emit_insn (gen_seth44 (temp1, op1));
      emit_insn (gen_setm44 (temp2, temp1, op1));
      emit_insn (gen_rtx_SET (VOIDmode, temp3,
                              gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
      emit_insn (gen_setl44 (op0, temp3, op1));
      break;

    case CM_MEDANY:
      /* The range spanned by all instructions in the object is less
         than 2^31 bytes (2GB) and the distance from any instruction
         to the location of the label _GLOBAL_OFFSET_TABLE_ is less
         than 2^31 bytes (2GB).

         The executable can be placed anywhere in the virtual address
         space.

         sethi  %hh(symbol), %temp1
         sethi  %lm(symbol), %temp2
         or     %temp1, %hm(symbol), %temp3
         sllx   %temp3, 32, %temp4
         or     %temp4, %temp2, %temp5
         or     %temp5, %lo(symbol), %reg  */
      if (temp)
        {
          /* It is possible that one of the registers we got for operands[2]
             might coincide with that of operands[0] (which is why we made
             it TImode).  Pick the other one to use as our scratch.  */
          if (rtx_equal_p (temp, op0))
            {
              gcc_assert (ti_temp);
              temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
            }
          temp1 = op0;
          temp2 = temp;  /* op0 is _not_ allowed, see above.  */
          temp3 = op0;
          temp4 = op0;
          temp5 = op0;
        }
      else
        {
          temp1 = gen_reg_rtx (DImode);
          temp2 = gen_reg_rtx (DImode);
          temp3 = gen_reg_rtx (DImode);
          temp4 = gen_reg_rtx (DImode);
          temp5 = gen_reg_rtx (DImode);
        }

      emit_insn (gen_sethh (temp1, op1));
      emit_insn (gen_setlm (temp2, op1));
      emit_insn (gen_sethm (temp3, temp1, op1));
      emit_insn (gen_rtx_SET (VOIDmode, temp4,
                              gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
      emit_insn (gen_rtx_SET (VOIDmode, temp5,
                              gen_rtx_PLUS (DImode, temp4, temp2)));
      emit_insn (gen_setlo (op0, temp5, op1));
      break;

    case CM_EMBMEDANY:
      /* Old old old backwards compatibility kruft here.
         Essentially it is MEDLOW with a fixed 64-bit
         virtual base added to all data segment addresses.
         Text-segment stuff is computed like MEDANY, we can't
         reuse the code above because the relocation knobs
         look different.

         Data segment:  sethi   %hi(symbol), %temp1
                        add     %temp1, EMBMEDANY_BASE_REG, %temp2
                        or      %temp2, %lo(symbol), %reg  */
      if (data_segment_operand (op1, GET_MODE (op1)))
        {
          if (temp)
            {
              temp1 = temp;  /* op0 is allowed.  */
              temp2 = op0;
            }
          else
            {
              temp1 = gen_reg_rtx (DImode);
              temp2 = gen_reg_rtx (DImode);
            }

          emit_insn (gen_embmedany_sethi (temp1, op1));
          emit_insn (gen_embmedany_brsum (temp2, temp1));
          emit_insn (gen_embmedany_losum (op0, temp2, op1));
        }

      /* Text segment:  sethi   %uhi(symbol), %temp1
                        sethi   %hi(symbol), %temp2
                        or      %temp1, %ulo(symbol), %temp3
                        sllx    %temp3, 32, %temp4
                        or      %temp4, %temp2, %temp5
                        or      %temp5, %lo(symbol), %reg  */
      else
        {
          if (temp)
            {
              /* It is possible that one of the registers we got for operands[2]
                 might coincide with that of operands[0] (which is why we made
                 it TImode).  Pick the other one to use as our scratch.  */
              if (rtx_equal_p (temp, op0))
                {
                  gcc_assert (ti_temp);
                  temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
                }
              temp1 = op0;
              temp2 = temp;  /* op0 is _not_ allowed, see above.  */
              temp3 = op0;
              temp4 = op0;
              temp5 = op0;
            }
          else
            {
              temp1 = gen_reg_rtx (DImode);
              temp2 = gen_reg_rtx (DImode);
              temp3 = gen_reg_rtx (DImode);
              temp4 = gen_reg_rtx (DImode);
              temp5 = gen_reg_rtx (DImode);
            }

          emit_insn (gen_embmedany_textuhi (temp1, op1));
          emit_insn (gen_embmedany_texthi  (temp2, op1));
          emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
          emit_insn (gen_rtx_SET (VOIDmode, temp4,
                                  gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
          emit_insn (gen_rtx_SET (VOIDmode, temp5,
                                  gen_rtx_PLUS (DImode, temp4, temp2)));
          emit_insn (gen_embmedany_textlo  (op0, temp5, op1));
        }
      break;

    default:
      gcc_unreachable ();
    }
}

#if HOST_BITS_PER_WIDE_INT == 32
void
sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
{
  gcc_unreachable ();
}
#else
/* These avoid problems when cross compiling.  If we do not
   go through all this hair then the optimizer will see
   invalid REG_EQUAL notes or in some cases none at all.  */
static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);

/* The optimizer is not to assume anything about exactly
   which bits are set for a HIGH, they are unspecified.
   Unfortunately this leads to many missed optimizations
   during CSE.  We mask out the non-HIGH bits, and matches
   a plain movdi, to alleviate this problem.  */
static rtx
gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
{
  return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
}

static rtx
gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
{
  return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
}

static rtx
gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
{
  return gen_rtx_IOR (DImode, src, GEN_INT (val));
}

static rtx
gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
{
  return gen_rtx_XOR (DImode, src, GEN_INT (val));
}

/* Worker routines for 64-bit constant formation on arch64.
   One of the key things to be doing in these emissions is
   to create as many temp REGs as possible.  This makes it
   possible for half-built constants to be used later when
   such values are similar to something required later on.
   Without doing this, the optimizer cannot see such
   opportunities.  */

static void sparc_emit_set_const64_quick1 (rtx, rtx,
                                           unsigned HOST_WIDE_INT, int);

static void
sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
                               unsigned HOST_WIDE_INT low_bits, int is_neg)
{
  unsigned HOST_WIDE_INT high_bits;

  if (is_neg)
    high_bits = (~low_bits) & 0xffffffff;
  else
    high_bits = low_bits;

  emit_insn (gen_safe_HIGH64 (temp, high_bits));
  if (!is_neg)
    {
      emit_insn (gen_rtx_SET (VOIDmode, op0,
                              gen_safe_OR64 (temp, (high_bits & 0x3ff))));
    }
  else
    {
      /* If we are XOR'ing with -1, then we should emit a one's complement
         instead.  This way the combiner will notice logical operations
         such as ANDN later on and substitute.  */
      if ((low_bits & 0x3ff) == 0x3ff)
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_NOT (DImode, temp)));
        }
      else
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_safe_XOR64 (temp,
                                                  (-(HOST_WIDE_INT)0x400
                                                   | (low_bits & 0x3ff)))));
        }
    }
}

static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
                                           unsigned HOST_WIDE_INT, int);

static void
sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
                               unsigned HOST_WIDE_INT high_bits,
                               unsigned HOST_WIDE_INT low_immediate,
                               int shift_count)
{
  rtx temp2 = op0;

  if ((high_bits & 0xfffffc00) != 0)
    {
      emit_insn (gen_safe_HIGH64 (temp, high_bits));
      if ((high_bits & ~0xfffffc00) != 0)
        emit_insn (gen_rtx_SET (VOIDmode, op0,
                                gen_safe_OR64 (temp, (high_bits & 0x3ff))));
      else
        temp2 = temp;
    }
  else
    {
      emit_insn (gen_safe_SET64 (temp, high_bits));
      temp2 = temp;
    }

  /* Now shift it up into place.  */
  emit_insn (gen_rtx_SET (VOIDmode, op0,
                          gen_rtx_ASHIFT (DImode, temp2,
                                          GEN_INT (shift_count))));

  /* If there is a low immediate part piece, finish up by
     putting that in as well.  */
  if (low_immediate != 0)
    emit_insn (gen_rtx_SET (VOIDmode, op0,
                            gen_safe_OR64 (op0, low_immediate)));
}

static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
                                            unsigned HOST_WIDE_INT);

/* Full 64-bit constant decomposition.  Even though this is the
   'worst' case, we still optimize a few things away.  */
static void
sparc_emit_set_const64_longway (rtx op0, rtx temp,
                                unsigned HOST_WIDE_INT high_bits,
                                unsigned HOST_WIDE_INT low_bits)
{
  rtx sub_temp;

  if (reload_in_progress || reload_completed)
    sub_temp = op0;
  else
    sub_temp = gen_reg_rtx (DImode);

  if ((high_bits & 0xfffffc00) != 0)
    {
      emit_insn (gen_safe_HIGH64 (temp, high_bits));
      if ((high_bits & ~0xfffffc00) != 0)
        emit_insn (gen_rtx_SET (VOIDmode,
                                sub_temp,
                                gen_safe_OR64 (temp, (high_bits & 0x3ff))));
      else
        sub_temp = temp;
    }
  else
    {
      emit_insn (gen_safe_SET64 (temp, high_bits));
      sub_temp = temp;
    }

  if (!reload_in_progress && !reload_completed)
    {
      rtx temp2 = gen_reg_rtx (DImode);
      rtx temp3 = gen_reg_rtx (DImode);
      rtx temp4 = gen_reg_rtx (DImode);

      emit_insn (gen_rtx_SET (VOIDmode, temp4,
                              gen_rtx_ASHIFT (DImode, sub_temp,
                                              GEN_INT (32))));

      emit_insn (gen_safe_HIGH64 (temp2, low_bits));
      if ((low_bits & ~0xfffffc00) != 0)
        {
          emit_insn (gen_rtx_SET (VOIDmode, temp3,
                                  gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_PLUS (DImode, temp4, temp3)));
        }
      else
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_PLUS (DImode, temp4, temp2)));
        }
    }
  else
    {
      rtx low1 = GEN_INT ((low_bits >> (32 - 12))          & 0xfff);
      rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12))     & 0xfff);
      rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
      int to_shift = 12;

      /* We are in the middle of reload, so this is really
         painful.  However we do still make an attempt to
         avoid emitting truly stupid code.  */
      if (low1 != const0_rtx)
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_ASHIFT (DImode, sub_temp,
                                                  GEN_INT (to_shift))));
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_IOR (DImode, op0, low1)));
          sub_temp = op0;
          to_shift = 12;
        }
      else
        {
          to_shift += 12;
        }
      if (low2 != const0_rtx)
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_ASHIFT (DImode, sub_temp,
                                                  GEN_INT (to_shift))));
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_IOR (DImode, op0, low2)));
          sub_temp = op0;
          to_shift = 8;
        }
      else
        {
          to_shift += 8;
        }
      emit_insn (gen_rtx_SET (VOIDmode, op0,
                              gen_rtx_ASHIFT (DImode, sub_temp,
                                              GEN_INT (to_shift))));
      if (low3 != const0_rtx)
        emit_insn (gen_rtx_SET (VOIDmode, op0,
                                gen_rtx_IOR (DImode, op0, low3)));
      /* phew...  */
    }
}

/* Analyze a 64-bit constant for certain properties.  */
static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
                                    unsigned HOST_WIDE_INT,
                                    int *, int *, int *);

static void
analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
                        unsigned HOST_WIDE_INT low_bits,
                        int *hbsp, int *lbsp, int *abbasp)
{
  int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
  int i;

  lowest_bit_set = highest_bit_set = -1;
  i = 0;
  do
    {
      if ((lowest_bit_set == -1)
          && ((low_bits >> i) & 1))
        lowest_bit_set = i;
      if ((highest_bit_set == -1)
          && ((high_bits >> (32 - i - 1)) & 1))
        highest_bit_set = (64 - i - 1);
    }
  while (++i < 32
         && ((highest_bit_set == -1)
             || (lowest_bit_set == -1)));
  if (i == 32)
    {
      i = 0;
      do
        {
          if ((lowest_bit_set == -1)
              && ((high_bits >> i) & 1))
            lowest_bit_set = i + 32;
          if ((highest_bit_set == -1)
              && ((low_bits >> (32 - i - 1)) & 1))
            highest_bit_set = 32 - i - 1;
        }
      while (++i < 32
             && ((highest_bit_set == -1)
                 || (lowest_bit_set == -1)));
    }
  /* If there are no bits set this should have gone out
     as one instruction!  */
  gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
  all_bits_between_are_set = 1;
  for (i = lowest_bit_set; i <= highest_bit_set; i++)
    {
      if (i < 32)
        {
          if ((low_bits & (1 << i)) != 0)
            continue;
        }
      else
        {
          if ((high_bits & (1 << (i - 32))) != 0)
            continue;
        }
      all_bits_between_are_set = 0;
      break;
    }
  *hbsp = highest_bit_set;
  *lbsp = lowest_bit_set;
  *abbasp = all_bits_between_are_set;
}

static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);

static int
const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
                   unsigned HOST_WIDE_INT low_bits)
{
  int highest_bit_set, lowest_bit_set, all_bits_between_are_set;

  if (high_bits == 0
      || high_bits == 0xffffffff)
    return 1;

  analyze_64bit_constant (high_bits, low_bits,
                          &highest_bit_set, &lowest_bit_set,
                          &all_bits_between_are_set);

  if ((highest_bit_set == 63
       || lowest_bit_set == 0)
      && all_bits_between_are_set != 0)
    return 1;

  if ((highest_bit_set - lowest_bit_set) < 21)
    return 1;

  return 0;
}

static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
                                                        unsigned HOST_WIDE_INT,
                                                        int, int);

static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
                          unsigned HOST_WIDE_INT low_bits,
                          int lowest_bit_set, int shift)
{
  HOST_WIDE_INT hi, lo;

  if (lowest_bit_set < 32)
    {
      lo = (low_bits >> lowest_bit_set) << shift;
      hi = ((high_bits << (32 - lowest_bit_set)) << shift);
    }
  else
    {
      lo = 0;
      hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
    }
  gcc_assert (! (hi & lo));
  return (hi | lo);
}

/* Here we are sure to be arch64 and this is an integer constant
   being loaded into a register.  Emit the most efficient
   insn sequence possible.  Detection of all the 1-insn cases
   has been done already.  */
void
sparc_emit_set_const64 (rtx op0, rtx op1)
{
  unsigned HOST_WIDE_INT high_bits, low_bits;
  int lowest_bit_set, highest_bit_set;
  int all_bits_between_are_set;
  rtx temp = 0;

  /* Sanity check that we know what we are working with.  */
  gcc_assert (TARGET_ARCH64
              && (GET_CODE (op0) == SUBREG
                  || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));

  if (reload_in_progress || reload_completed)
    temp = op0;

  if (GET_CODE (op1) != CONST_INT)
    {
      sparc_emit_set_symbolic_const64 (op0, op1, temp);
      return;
    }

  if (! temp)
    temp = gen_reg_rtx (DImode);

  high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
  low_bits = (INTVAL (op1) & 0xffffffff);

  /* low_bits   bits 0  --> 31
     high_bits  bits 32 --> 63  */

  analyze_64bit_constant (high_bits, low_bits,
                          &highest_bit_set, &lowest_bit_set,
                          &all_bits_between_are_set);

  /* First try for a 2-insn sequence.  */

  /* These situations are preferred because the optimizer can
   * do more things with them:
   * 1) mov     -1, %reg
   *    sllx    %reg, shift, %reg
   * 2) mov     -1, %reg
   *    srlx    %reg, shift, %reg
   * 3) mov     some_small_const, %reg
   *    sllx    %reg, shift, %reg
   */
  if (((highest_bit_set == 63
        || lowest_bit_set == 0)
       && all_bits_between_are_set != 0)
      || ((highest_bit_set - lowest_bit_set) < 12))
    {
      HOST_WIDE_INT the_const = -1;
      int shift = lowest_bit_set;

      if ((highest_bit_set != 63
           && lowest_bit_set != 0)
          || all_bits_between_are_set == 0)
        {
          the_const =
            create_simple_focus_bits (high_bits, low_bits,
                                      lowest_bit_set, 0);
        }
      else if (lowest_bit_set == 0)
        shift = -(63 - highest_bit_set);

      gcc_assert (SPARC_SIMM13_P (the_const));
      gcc_assert (shift != 0);

      emit_insn (gen_safe_SET64 (temp, the_const));
      if (shift > 0)
        emit_insn (gen_rtx_SET (VOIDmode,
                                op0,
                                gen_rtx_ASHIFT (DImode,
                                                temp,
                                                GEN_INT (shift))));
      else if (shift < 0)
        emit_insn (gen_rtx_SET (VOIDmode,
                                op0,
                                gen_rtx_LSHIFTRT (DImode,
                                                  temp,
                                                  GEN_INT (-shift))));
      return;
    }

  /* Now a range of 22 or less bits set somewhere.
   * 1) sethi   %hi(focus_bits), %reg
   *    sllx    %reg, shift, %reg
   * 2) sethi   %hi(focus_bits), %reg
   *    srlx    %reg, shift, %reg
   */
  if ((highest_bit_set - lowest_bit_set) < 21)
    {
      unsigned HOST_WIDE_INT focus_bits =
        create_simple_focus_bits (high_bits, low_bits,
                                  lowest_bit_set, 10);

      gcc_assert (SPARC_SETHI_P (focus_bits));
      gcc_assert (lowest_bit_set != 10);

      emit_insn (gen_safe_HIGH64 (temp, focus_bits));

      /* If lowest_bit_set == 10 then a sethi alone could have done it.  */
      if (lowest_bit_set < 10)
        emit_insn (gen_rtx_SET (VOIDmode,
                                op0,
                                gen_rtx_LSHIFTRT (DImode, temp,
                                                  GEN_INT (10 - lowest_bit_set))));
      else if (lowest_bit_set > 10)
        emit_insn (gen_rtx_SET (VOIDmode,
                                op0,
                                gen_rtx_ASHIFT (DImode, temp,
                                                GEN_INT (lowest_bit_set - 10))));
      return;
    }

  /* 1) sethi   %hi(low_bits), %reg
   *    or      %reg, %lo(low_bits), %reg
   * 2) sethi   %hi(~low_bits), %reg
   *    xor     %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
   */
  if (high_bits == 0
      || high_bits == 0xffffffff)
    {
      sparc_emit_set_const64_quick1 (op0, temp, low_bits,
                                     (high_bits == 0xffffffff));
      return;
    }

  /* Now, try 3-insn sequences.  */

  /* 1) sethi   %hi(high_bits), %reg
   *    or      %reg, %lo(high_bits), %reg
   *    sllx    %reg, 32, %reg
   */
  if (low_bits == 0)
    {
      sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
      return;
    }

  /* We may be able to do something quick
     when the constant is negated, so try that.  */
  if (const64_is_2insns ((~high_bits) & 0xffffffff,
                         (~low_bits) & 0xfffffc00))
    {
      /* NOTE: The trailing bits get XOR'd so we need the
         non-negated bits, not the negated ones.  */
      unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;

      if ((((~high_bits) & 0xffffffff) == 0
           && ((~low_bits) & 0x80000000) == 0)
          || (((~high_bits) & 0xffffffff) == 0xffffffff
              && ((~low_bits) & 0x80000000) != 0))
        {
          unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);

          if ((SPARC_SETHI_P (fast_int)
               && (~high_bits & 0xffffffff) == 0)
              || SPARC_SIMM13_P (fast_int))
            emit_insn (gen_safe_SET64 (temp, fast_int));
          else
            sparc_emit_set_const64 (temp, GEN_INT (fast_int));
        }
      else
        {
          rtx negated_const;
          negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
                                   (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
          sparc_emit_set_const64 (temp, negated_const);
        }

      /* If we are XOR'ing with -1, then we should emit a one's complement
         instead.  This way the combiner will notice logical operations
         such as ANDN later on and substitute.  */
      if (trailing_bits == 0x3ff)
        {
          emit_insn (gen_rtx_SET (VOIDmode, op0,
                                  gen_rtx_NOT (DImode, temp)));
        }
      else
        {
          emit_insn (gen_rtx_SET (VOIDmode,
                                  op0,
                                  gen_safe_XOR64 (temp,
                                                  (-0x400 | trailing_bits))));
        }
      return;
    }

  /* 1) sethi   %hi(xxx), %reg
   *    or      %reg, %lo(xxx), %reg
   *    sllx    %reg, yyy, %reg
   *
   * ??? This is just a generalized version of the low_bits==0
   * thing above, FIXME...
   */
  if ((highest_bit_set - lowest_bit_set) < 32)
    {
      unsigned HOST_WIDE_INT focus_bits =
        create_simple_focus_bits (high_bits, low_bits,
                                  lowest_bit_set, 0);

      /* We can't get here in this state.  */
      gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);

      /* So what we know is that the set bits straddle the
         middle of the 64-bit word.  */
      sparc_emit_set_const64_quick2 (op0, temp,
                                     focus_bits, 0,
                                     lowest_bit_set);
      return;
    }

  /* 1) sethi   %hi(high_bits), %reg
   *    or      %reg, %lo(high_bits), %reg
   *    sllx    %reg, 32, %reg
   *    or      %reg, low_bits, %reg
   */
  if (SPARC_SIMM13_P(low_bits)
      && ((int)low_bits > 0))
    {
      sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
      return;
    }

  /* The easiest way when all else fails, is full decomposition.  */
#if 0
  printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
          high_bits, low_bits, ~high_bits, ~low_bits);
#endif
  sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
}
#endif /* HOST_BITS_PER_WIDE_INT == 32 */

/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
   return the mode to be used for the comparison.  For floating-point,
   CCFP[E]mode is used.  CC_NOOVmode should be used when the first operand
   is a PLUS, MINUS, NEG, or ASHIFT.  CCmode should be used when no special
   processing is needed.  */

enum machine_mode
select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
{
  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
    {
      switch (op)
        {
        case EQ:
        case NE:
        case UNORDERED:
        case ORDERED:
        case UNLT:
        case UNLE:
        case UNGT:
        case UNGE:
        case UNEQ:
        case LTGT:
          return CCFPmode;

        case LT:
        case LE:
        case GT:
        case GE:
          return CCFPEmode;

        default:
          gcc_unreachable ();
        }
    }
  else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
           || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
    {
      if (TARGET_ARCH64 && GET_MODE (x) == DImode)
        return CCX_NOOVmode;
      else
        return CC_NOOVmode;
    }
  else
    {
      if (TARGET_ARCH64 && GET_MODE (x) == DImode)
        return CCXmode;
      else
        return CCmode;
    }
}

/* X and Y are two things to compare using CODE.  Emit the compare insn and
   return the rtx for the cc reg in the proper mode.  */

rtx
gen_compare_reg (enum rtx_code code)
{
  rtx x = sparc_compare_op0;
  rtx y = sparc_compare_op1;
  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
  rtx cc_reg;

  if (sparc_compare_emitted != NULL_RTX)
    {
      cc_reg = sparc_compare_emitted;
      sparc_compare_emitted = NULL_RTX;
      return cc_reg;
    }

  /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
     fcc regs (cse can't tell they're really call clobbered regs and will
     remove a duplicate comparison even if there is an intervening function
     call - it will then try to reload the cc reg via an int reg which is why
     we need the movcc patterns).  It is possible to provide the movcc
     patterns by using the ldxfsr/stxfsr v9 insns.  I tried it: you need two
     registers (say %g1,%g5) and it takes about 6 insns.  A better fix would be
     to tell cse that CCFPE mode registers (even pseudos) are call
     clobbered.  */

  /* ??? This is an experiment.  Rather than making changes to cse which may
     or may not be easy/clean, we do our own cse.  This is possible because
     we will generate hard registers.  Cse knows they're call clobbered (it
     doesn't know the same thing about pseudos). If we guess wrong, no big
     deal, but if we win, great!  */

  if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
#if 1 /* experiment */
    {
      int reg;
      /* We cycle through the registers to ensure they're all exercised.  */
      static int next_fcc_reg = 0;
      /* Previous x,y for each fcc reg.  */
      static rtx prev_args[4][2];

      /* Scan prev_args for x,y.  */
      for (reg = 0; reg < 4; reg++)
        if (prev_args[reg][0] == x && prev_args[reg][1] == y)
          break;
      if (reg == 4)
        {
          reg = next_fcc_reg;
          prev_args[reg][0] = x;
          prev_args[reg][1] = y;
          next_fcc_reg = (next_fcc_reg + 1) & 3;
        }
      cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
    }
#else
    cc_reg = gen_reg_rtx (mode);
#endif /* ! experiment */
  else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
    cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
  else
    cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);

  emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
                          gen_rtx_COMPARE (mode, x, y)));

  return cc_reg;
}

/* This function is used for v9 only.
   CODE is the code for an Scc's comparison.
   OPERANDS[0] is the target of the Scc insn.
   OPERANDS[1] is the value we compare against const0_rtx (which hasn't
   been generated yet).

   This function is needed to turn

           (set (reg:SI 110)
               (gt (reg:CCX 100 %icc)
                   (const_int 0)))
   into
           (set (reg:SI 110)
               (gt:DI (reg:CCX 100 %icc)
                   (const_int 0)))

   IE: The instruction recognizer needs to see the mode of the comparison to
   find the right instruction. We could use "gt:DI" right in the
   define_expand, but leaving it out allows us to handle DI, SI, etc.

   We refer to the global sparc compare operands sparc_compare_op0 and
   sparc_compare_op1.  */

int
gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
{
  if (! TARGET_ARCH64
      && (GET_MODE (sparc_compare_op0) == DImode
          || GET_MODE (operands[0]) == DImode))
    return 0;

  /* Try to use the movrCC insns.  */
  if (TARGET_ARCH64
      && GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT
      && sparc_compare_op1 == const0_rtx
      && v9_regcmp_p (compare_code))
    {
      rtx op0 = sparc_compare_op0;
      rtx temp;

      /* Special case for op0 != 0.  This can be done with one instruction if
         operands[0] == sparc_compare_op0.  */

      if (compare_code == NE
          && GET_MODE (operands[0]) == DImode
          && rtx_equal_p (op0, operands[0]))
        {
          emit_insn (gen_rtx_SET (VOIDmode, operands[0],
                              gen_rtx_IF_THEN_ELSE (DImode,
                                       gen_rtx_fmt_ee (compare_code, DImode,
                                                       op0, const0_rtx),
                                       const1_rtx,
                                       operands[0])));
          return 1;
        }

      if (reg_overlap_mentioned_p (operands[0], op0))
        {
          /* Handle the case where operands[0] == sparc_compare_op0.
             We "early clobber" the result.  */
          op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
          emit_move_insn (op0, sparc_compare_op0);
        }

      emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
      if (GET_MODE (op0) != DImode)
        {
          temp = gen_reg_rtx (DImode);
          convert_move (temp, op0, 0);
        }
      else
        temp = op0;
      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
                          gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
                                   gen_rtx_fmt_ee (compare_code, DImode,
                                                   temp, const0_rtx),
                                   const1_rtx,
                                   operands[0])));
      return 1;
    }
  else
    {
      operands[1] = gen_compare_reg (compare_code);

      switch (GET_MODE (operands[1]))
        {
          case CCmode :
          case CCXmode :
          case CCFPEmode :
          case CCFPmode :
            break;
          default :
            gcc_unreachable ();
        }
      emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
                          gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
                                   gen_rtx_fmt_ee (compare_code,
                                                   GET_MODE (operands[1]),
                                                   operands[1], const0_rtx),
                                    const1_rtx, operands[0])));
      return 1;
    }
}

/* Emit a conditional jump insn for the v9 architecture using comparison code
   CODE and jump target LABEL.
   This function exists to take advantage of the v9 brxx insns.  */

void
emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
{
  gcc_assert (sparc_compare_emitted == NULL_RTX);
  emit_jump_insn (gen_rtx_SET (VOIDmode,
                           pc_rtx,
                           gen_rtx_IF_THEN_ELSE (VOIDmode,
                                    gen_rtx_fmt_ee (code, GET_MODE (op0),
                                                    op0, const0_rtx),
                                    gen_rtx_LABEL_REF (VOIDmode, label),
                                    pc_rtx)));
}

/* Generate a DFmode part of a hard TFmode register.
   REG is the TFmode hard register, LOW is 1 for the
   low 64bit of the register and 0 otherwise.
 */
rtx
gen_df_reg (rtx reg, int low)
{
  int regno = REGNO (reg);

  if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
    regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
  return gen_rtx_REG (DFmode, regno);
}
\f
/* Generate a call to FUNC with OPERANDS.  Operand 0 is the return value.
   Unlike normal calls, TFmode operands are passed by reference.  It is
   assumed that no more than 3 operands are required.  */

static void
emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
{
  rtx ret_slot = NULL, arg[3], func_sym;
  int i;

  /* We only expect to be called for conversions, unary, and binary ops.  */
  gcc_assert (nargs == 2 || nargs == 3);

  for (i = 0; i < nargs; ++i)
    {
      rtx this_arg = operands[i];
      rtx this_slot;

      /* TFmode arguments and return values are passed by reference.  */
      if (GET_MODE (this_arg) == TFmode)
        {
          int force_stack_temp;

          force_stack_temp = 0;
          if (TARGET_BUGGY_QP_LIB && i == 0)
            force_stack_temp = 1;

          if (GET_CODE (this_arg) == MEM
              && ! force_stack_temp)
            this_arg = XEXP (this_arg, 0);
          else if (CONSTANT_P (this_arg)
                   && ! force_stack_temp)
            {
              this_slot = force_const_mem (TFmode, this_arg);
              this_arg = XEXP (this_slot, 0);
            }
          else
            {
              this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);

              /* Operand 0 is the return value.  We'll copy it out later.  */
              if (i > 0)
                emit_move_insn (this_slot, this_arg);
              else
                ret_slot = this_slot;

              this_arg = XEXP (this_slot, 0);
            }
        }

      arg[i] = this_arg;
    }

  func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);

  if (GET_MODE (operands[0]) == TFmode)
    {
      if (nargs == 2)
        emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
                           arg[0], GET_MODE (arg[0]),
                           arg[1], GET_MODE (arg[1]));
      else
        emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
                           arg[0], GET_MODE (arg[0]),
                           arg[1], GET_MODE (arg[1]),
                           arg[2], GET_MODE (arg[2]));

      if (ret_slot)
        emit_move_insn (operands[0], ret_slot);
    }
  else
    {
      rtx ret;

      gcc_assert (nargs == 2);

      ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
                                     GET_MODE (operands[0]), 1,
                                     arg[1], GET_MODE (arg[1]));

      if (ret != operands[0])
        emit_move_insn (operands[0], ret);
    }
}

/* Expand soft-float TFmode calls to sparc abi routines.  */

static void
emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
{
  const char *func;

  switch (code)
    {
    case PLUS:
      func = "_Qp_add";
      break;
    case MINUS:
      func = "_Qp_sub";
      break;
    case MULT:
      func = "_Qp_mul";
      break;
    case DIV:
      func = "_Qp_div";
      break;
    default:
      gcc_unreachable ();
    }

  emit_soft_tfmode_libcall (func, 3, operands);
}

static void
emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
{
  const char *func;

  gcc_assert (code == SQRT);
  func = "_Qp_sqrt";

  emit_soft_tfmode_libcall (func, 2, operands);
}

static void
emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
{
  const char *func;

  switch (code)
    {
    case FLOAT_EXTEND:
      switch (GET_MODE (operands[1]))
        {
        case SFmode:
          func = "_Qp_stoq";
          break;
        case DFmode:
          func = "_Qp_dtoq";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    case FLOAT_TRUNCATE:
      switch (GET_MODE (operands[0]))
        {
        case SFmode:
          func = "_Qp_qtos";
          break;
        case DFmode:
          func = "_Qp_qtod";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    case FLOAT:
      switch (GET_MODE (operands[1]))
        {
        case SImode:
          func = "_Qp_itoq";
          break;
        case DImode:
          func = "_Qp_xtoq";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    case UNSIGNED_FLOAT:
      switch (GET_MODE (operands[1]))
        {
        case SImode:
          func = "_Qp_uitoq";
          break;
        case DImode:
          func = "_Qp_uxtoq";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    case FIX:
      switch (GET_MODE (operands[0]))
        {
        case SImode:
          func = "_Qp_qtoi";
          break;
        case DImode:
          func = "_Qp_qtox";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    case UNSIGNED_FIX:
      switch (GET_MODE (operands[0]))
        {
        case SImode:
          func = "_Qp_qtoui";
          break;
        case DImode:
          func = "_Qp_qtoux";
          break;
        default:
          gcc_unreachable ();
        }
      break;

    default:
      gcc_unreachable ();
    }

  emit_soft_tfmode_libcall (func, 2, operands);
}

/* Expand a hard-float tfmode operation.  All arguments must be in
   registers.  */

static void
emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
{
  rtx op, dest;

  if (GET_RTX_CLASS (code) == RTX_UNARY)
    {
      operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
      op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
    }
  else
    {
      operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
      operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
      op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
                           operands[1], operands[2]);
    }

  if (register_operand (operands[0], VOIDmode))
    dest = operands[0];
  else
    dest = gen_reg_rtx (GET_MODE (operands[0]));

  emit_insn (gen_rtx_SET (VOIDmode, dest, op));

  if (dest != operands[0])
    emit_move_insn (operands[0], dest);
}

void
emit_tfmode_binop (enum rtx_code code, rtx *operands)
{
  if (TARGET_HARD_QUAD)
    emit_hard_tfmode_operation (code, operands);
  else
    emit_soft_tfmode_binop (code, operands);
}

void
emit_tfmode_unop (enum rtx_code code, rtx *operands)
{
  if (TARGET_HARD_QUAD)
    emit_hard_tfmode_operation (code, operands);
  else
    emit_soft_tfmode_unop (code, operands);
}

void
emit_tfmode_cvt (enum rtx_code code, rtx *operands)
{
  if (TARGET_HARD_QUAD)
    emit_hard_tfmode_operation (code, operands);
  else
    emit_soft_tfmode_cvt (code, operands);
}
\f
/* Return nonzero if a branch/jump/call instruction will be emitting
   nop into its delay slot.  */

int
empty_delay_slot (rtx insn)
{
  rtx seq;

  /* If no previous instruction (should not happen), return true.  */
  if (PREV_INSN (insn) == NULL)
    return 1;

  seq = NEXT_INSN (PREV_INSN (insn));
  if (GET_CODE (PATTERN (seq)) == SEQUENCE)
    return 0;

  return 1;
}

/* Return nonzero if TRIAL can go into the call delay slot.  */

int
tls_call_delay (rtx trial)
{
  rtx pat;

  /* Binutils allows
       call __tls_get_addr, %tgd_call (foo)
        add %l7, %o0, %o0, %tgd_add (foo)
     while Sun as/ld does not.  */
  if (TARGET_GNU_TLS || !TARGET_TLS)
    return 1;

  pat = PATTERN (trial);

  /* We must reject tgd_add{32|64}, i.e.
       (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
     and tldm_add{32|64}, i.e.
       (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
     for Sun as/ld.  */
  if (GET_CODE (pat) == SET
      && GET_CODE (SET_SRC (pat)) == PLUS)
    {
      rtx unspec = XEXP (SET_SRC (pat), 1);

      if (GET_CODE (unspec) == UNSPEC
          && (XINT (unspec, 1) == UNSPEC_TLSGD
              || XINT (unspec, 1) == UNSPEC_TLSLDM))
        return 0;
    }

  return 1;
}

/* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
   instruction.  RETURN_P is true if the v9 variant 'return' is to be
   considered in the test too.

   TRIAL must be a SET whose destination is a REG appropriate for the
   'restore' instruction or, if RETURN_P is true, for the 'return'
   instruction.  */

static int
eligible_for_restore_insn (rtx trial, bool return_p)
{
  rtx pat = PATTERN (trial);
  rtx src = SET_SRC (pat);

  /* The 'restore src,%g0,dest' pattern for word mode and below.  */
  if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
      && arith_operand (src, GET_MODE (src)))
    {
      if (TARGET_ARCH64)
        return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
      else
        return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
    }

  /* The 'restore src,%g0,dest' pattern for double-word mode.  */
  else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
           && arith_double_operand (src, GET_MODE (src)))
    return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);

  /* The 'restore src,%g0,dest' pattern for float if no FPU.  */
  else if (! TARGET_FPU && register_operand (src, SFmode))
    return 1;

  /* The 'restore src,%g0,dest' pattern for double if no FPU.  */
  else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
    return 1;

  /* If we have the 'return' instruction, anything that does not use
     local or output registers and can go into a delay slot wins.  */
  else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
           && (get_attr_in_uncond_branch_delay (trial)
               == IN_UNCOND_BRANCH_DELAY_TRUE))
    return 1;

  /* The 'restore src1,src2,dest' pattern for SImode.  */
  else if (GET_CODE (src) == PLUS
           && register_operand (XEXP (src, 0), SImode)
           && arith_operand (XEXP (src, 1), SImode))
    return 1;

  /* The 'restore src1,src2,dest' pattern for DImode.  */
  else if (GET_CODE (src) == PLUS
           && register_operand (XEXP (src, 0), DImode)
           && arith_double_operand (XEXP (src, 1), DImode))
    return 1;

  /* The 'restore src1,%lo(src2),dest' pattern.  */
  else if (GET_CODE (src) == LO_SUM
           && ! TARGET_CM_MEDMID
           && ((register_operand (XEXP (src, 0), SImode)
                && immediate_operand (XEXP (src, 1), SImode))
               || (TARGET_ARCH64
                   && register_operand (XEXP (src, 0), DImode)
                   && immediate_operand (XEXP (src, 1), DImode))))
    return 1;

  /* The 'restore src,src,dest' pattern.  */
  else if (GET_CODE (src) == ASHIFT
           && (register_operand (XEXP (src, 0), SImode)
               || register_operand (XEXP (src, 0), DImode))
           && XEXP (src, 1) == const1_rtx)
    return 1;

  return 0;
}

/* Return nonzero if TRIAL can go into the function return's
   delay slot.  */

int
eligible_for_return_delay (rtx trial)
{
  rtx pat;

  if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
    return 0;

  if (get_attr_length (trial) != 1)
    return 0;

  /* If there are any call-saved registers, we should scan TRIAL if it
     does not reference them.  For now just make it easy.  */
  if (num_gfregs)
    return 0;

  /* If the function uses __builtin_eh_return, the eh_return machinery
     occupies the delay slot.  */
  if (current_function_calls_eh_return)
    return 0;

  /* In the case of a true leaf function, anything can go into the slot.  */
  if (sparc_leaf_function_p)
    return get_attr_in_uncond_branch_delay (trial)
           == IN_UNCOND_BRANCH_DELAY_TRUE;

  pat = PATTERN (trial);

  /* Otherwise, only operations which can be done in tandem with
     a `restore' or `return' insn can go into the delay slot.  */
  if (GET_CODE (SET_DEST (pat)) != REG
      || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
    return 0;

  /* If this instruction sets up floating point register and we have a return
     instruction, it can probably go in.  But restore will not work
     with FP_REGS.  */
  if (REGNO (SET_DEST (pat)) >= 32)
    return (TARGET_V9
            && ! epilogue_renumber (&pat, 1)
            && (get_attr_in_uncond_branch_delay (trial)
                == IN_UNCOND_BRANCH_DELAY_TRUE));

  return eligible_for_restore_insn (trial, true);
}

/* Return nonzero if TRIAL can go into the sibling call's
   delay slot.  */

int
eligible_for_sibcall_delay (rtx trial)
{
  rtx pat;

  if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
    return 0;

  if (get_attr_length (trial) != 1)
    return 0;

  pat = PATTERN (trial);

  if (sparc_leaf_function_p)
    {
      /* If the tail call is done using the call instruction,
         we have to restore %o7 in the delay slot.  */
      if (LEAF_SIBCALL_SLOT_RESERVED_P)
        return 0;

      /* %g1 is used to build the function address */
      if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
        return 0;

      return 1;
    }

  /* Otherwise, only operations which can be done in tandem with
     a `restore' insn can go into the delay slot.  */
  if (GET_CODE (SET_DEST (pat)) != REG
      || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
      || REGNO (SET_DEST (pat)) >= 32)
    return 0;

  /* If it mentions %o7, it can't go in, because sibcall will clobber it
     in most cases.  */
  if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
    return 0;

  return eligible_for_restore_insn (trial, false);
}

int
short_branch (int uid1, int uid2)
{
  int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);

  /* Leave a few words of "slop".  */
  if (delta >= -1023 && delta <= 1022)
    return 1;

  return 0;
}

/* Return nonzero if REG is not used after INSN.
   We assume REG is a reload reg, and therefore does
   not live past labels or calls or jumps.  */
int
reg_unused_after (rtx reg, rtx insn)
{
  enum rtx_code code, prev_code = UNKNOWN;

  while ((insn = NEXT_INSN (insn)))
    {
      if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
        return 1;

      code = GET_CODE (insn);
      if (GET_CODE (insn) == CODE_LABEL)
        return 1;

      if (INSN_P (insn))
        {
          rtx set = single_set (insn);
          int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
          if (set && in_src)
            return 0;
          if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
            return 1;
          if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
            return 0;
        }
      prev_code = code;
    }
  return 1;
}
\f
/* Determine if it's legal to put X into the constant pool.  This
   is not possible if X contains the address of a symbol that is
   not constant (TLS) or not known at final link time (PIC).  */

static bool
sparc_cannot_force_const_mem (rtx x)
{
  switch (GET_CODE (x))
    {
    case CONST_INT:
    case CONST_DOUBLE:
    case CONST_VECTOR:
      /* Accept all non-symbolic constants.  */
      return false;

    case LABEL_REF:
      /* Labels are OK iff we are non-PIC.  */
      return flag_pic != 0;

    case SYMBOL_REF:
      /* 'Naked' TLS symbol references are never OK,
         non-TLS symbols are OK iff we are non-PIC.  */
      if (SYMBOL_REF_TLS_MODEL (x))
        return true;
      else
        return flag_pic != 0;

    case CONST:
      return sparc_cannot_force_const_mem (XEXP (x, 0));
    case PLUS:
    case MINUS:
      return sparc_cannot_force_const_mem (XEXP (x, 0))
         || sparc_cannot_force_const_mem (XEXP (x, 1));
    case UNSPEC:
      return true;
    default:
      gcc_unreachable ();
    }
}
\f
/* PIC support.  */
static GTY(()) char pic_helper_symbol_name[256];
static GTY(()) rtx pic_helper_symbol;
static GTY(()) bool pic_helper_emitted_p = false;
static GTY(()) rtx global_offset_table;

/* Ensure that we are not using patterns that are not OK with PIC.  */

int
check_pic (int i)
{
  switch (flag_pic)
    {
    case 1:
      gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
                  && (GET_CODE (recog_data.operand[i]) != CONST
                  || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
                      && (XEXP (XEXP (recog_data.operand[i], 0), 0)
                          == global_offset_table)
                      && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
                          == CONST))));
    case 2:
    default:
      return 1;
    }
}

/* Return true if X is an address which needs a temporary register when 
   reloaded while generating PIC code.  */

int
pic_address_needs_scratch (rtx x)
{
  /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
  if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
      && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
    return 1;

  return 0;
}

/* Determine if a given RTX is a valid constant.  We already know this
   satisfies CONSTANT_P.  */

bool
legitimate_constant_p (rtx x)
{
  rtx inner;

  switch (GET_CODE (x))
    {
    case SYMBOL_REF:
      /* TLS symbols are not constant.  */
      if (SYMBOL_REF_TLS_MODEL (x))
        return false;
      break;

    case CONST:
      inner = XEXP (x, 0);

      /* Offsets of TLS symbols are never valid.
         Discourage CSE from creating them.  */
      if (GET_CODE (inner) == PLUS
          && SPARC_SYMBOL_REF_TLS_P (XEXP (inner, 0)))
        return false;
      break;

    case CONST_DOUBLE:
      if (GET_MODE (x) == VOIDmode)
        return true;

      /* Floating point constants are generally not ok.
         The only exception is 0.0 in VIS.  */
      if (TARGET_VIS
          && SCALAR_FLOAT_MODE_P (GET_MODE (x))
          && const_zero_operand (x, GET_MODE (x)))
        return true;

      return false;

    case CONST_VECTOR:
      /* Vector constants are generally not ok.
         The only exception is 0 in VIS.  */
      if (TARGET_VIS
          && const_zero_operand (x, GET_MODE (x)))
        return true;

      return false;

    default:
      break;
    }

  return true;
}

/* Determine if a given RTX is a valid constant address.  */

bool
constant_address_p (rtx x)
{
  switch (GET_CODE (x))
    {
    case LABEL_REF:
    case CONST_INT:
    case HIGH:
      return true;

    case CONST:
      if (flag_pic && pic_address_needs_scratch (x))
        return false;
      return legitimate_constant_p (x);

    case SYMBOL_REF:
      return !flag_pic && legitimate_constant_p (x);

    default:
      return false;
    }
}

/* Nonzero if the constant value X is a legitimate general operand
   when generating PIC code.  It is given that flag_pic is on and
   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */

bool
legitimate_pic_operand_p (rtx x)
{
  if (pic_address_needs_scratch (x))
    return false;
  if (SPARC_SYMBOL_REF_TLS_P (x)
      || (GET_CODE (x) == CONST
          && GET_CODE (XEXP (x, 0)) == PLUS
          && SPARC_SYMBOL_REF_TLS_P (XEXP (XEXP (x, 0), 0))))
    return false;
  return true;
}

/* Return nonzero if ADDR is a valid memory address.
   STRICT specifies whether strict register checking applies.  */
   
int
legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
{
  rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;

  if (REG_P (addr) || GET_CODE (addr) == SUBREG)
    rs1 = addr;
  else if (GET_CODE (addr) == PLUS)
    {
      rs1 = XEXP (addr, 0);
      rs2 = XEXP (addr, 1);

      /* Canonicalize.  REG comes first, if there are no regs,
         LO_SUM comes first.  */
      if (!REG_P (rs1)
          && GET_CODE (rs1) != SUBREG
          && (REG_P (rs2)
              || GET_CODE (rs2) == SUBREG
              || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
        {
          rs1 = XEXP (addr, 1);
          rs2 = XEXP (addr, 0);
        }

      if ((flag_pic == 1
           && rs1 == pic_offset_table_rtx
           && !REG_P (rs2)
           && GET_CODE (rs2) != SUBREG
           && GET_CODE (rs2) != LO_SUM
           && GET_CODE (rs2) != MEM
           && ! SPARC_SYMBOL_REF_TLS_P (rs2)
           && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
           && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
          || ((REG_P (rs1)
               || GET_CODE (rs1) == SUBREG)
              && RTX_OK_FOR_OFFSET_P (rs2)))
        {
          imm1 = rs2;
          rs2 = NULL;
        }
      else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
               && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
        {
          /* We prohibit REG + REG for TFmode when there are no quad move insns
             and we consequently need to split.  We do this because REG+REG
             is not an offsettable address.  If we get the situation in reload
             where source and destination of a movtf pattern are both MEMs with
             REG+REG address, then only one of them gets converted to an
             offsettable address.  */
          if (mode == TFmode
              && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
            return 0;

          /* We prohibit REG + REG on ARCH32 if not optimizing for
             DFmode/DImode because then mem_min_alignment is likely to be zero
             after reload and the  forced split would lack a matching splitter
             pattern.  */
          if (TARGET_ARCH32 && !optimize
              && (mode == DFmode || mode == DImode))
            return 0;
        }
      else if (USE_AS_OFFSETABLE_LO10
               && GET_CODE (rs1) == LO_SUM
               && TARGET_ARCH64
               && ! TARGET_CM_MEDMID
               && RTX_OK_FOR_OLO10_P (rs2))
        {
          rs2 = NULL;
          imm1 = XEXP (rs1, 1);
          rs1 = XEXP (rs1, 0);
          if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1))
            return 0;
        }
    }
  else if (GET_CODE (addr) == LO_SUM)
    {
      rs1 = XEXP (addr, 0);
      imm1 = XEXP (addr, 1);

      if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1))
        return 0;

      /* We can't allow TFmode in 32-bit mode, because an offset greater
         than the alignment (8) may cause the LO_SUM to overflow.  */
      if (mode == TFmode && TARGET_ARCH32)
        return 0;
    }
  else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
    return 1;
  else
    return 0;

  if (GET_CODE (rs1) == SUBREG)
    rs1 = SUBREG_REG (rs1);
  if (!REG_P (rs1))
    return 0;

  if (rs2)
    {
      if (GET_CODE (rs2) == SUBREG)
        rs2 = SUBREG_REG (rs2);
      if (!REG_P (rs2))
        return 0;
    }

  if (strict)
    {
      if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
          || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
        return 0;
    }
  else
    {
      if ((REGNO (rs1) >= 32
           && REGNO (rs1) != FRAME_POINTER_REGNUM
           && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
          || (rs2
              && (REGNO (rs2) >= 32
                  && REGNO (rs2) != FRAME_POINTER_REGNUM
                  && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
        return 0;
    }
  return 1;
}

/* Construct the SYMBOL_REF for the tls_get_offset function.  */

static GTY(()) rtx sparc_tls_symbol;

static rtx
sparc_tls_get_addr (void)
{
  if (!sparc_tls_symbol)
    sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");

  return sparc_tls_symbol;
}

static rtx
sparc_tls_got (void)
{
  rtx temp;
  if (flag_pic)
    {
      current_function_uses_pic_offset_table = 1;
      return pic_offset_table_rtx;
    }

  if (!global_offset_table)
    global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
  temp = gen_reg_rtx (Pmode);
  emit_move_insn (temp, global_offset_table);
  return temp;
}

/* Return 1 if *X is a thread-local symbol.  */

static int
sparc_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
{
  return SPARC_SYMBOL_REF_TLS_P (*x);
}

/* Return 1 if X contains a thread-local symbol.  */

bool
sparc_tls_referenced_p (rtx x)
{
  if (!TARGET_HAVE_TLS)
    return false;

  return for_each_rtx (&x, &sparc_tls_symbol_ref_1, 0);
}

/* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
   this (thread-local) address.  */

rtx
legitimize_tls_address (rtx addr)
{
  rtx temp1, temp2, temp3, ret, o0, got, insn;

  gcc_assert (can_create_pseudo_p ());

  if (GET_CODE (addr) == SYMBOL_REF)
    switch (SYMBOL_REF_TLS_MODEL (addr))
      {
      case TLS_MODEL_GLOBAL_DYNAMIC:
        start_sequence ();
        temp1 = gen_reg_rtx (SImode);
        temp2 = gen_reg_rtx (SImode);
        ret = gen_reg_rtx (Pmode);
        o0 = gen_rtx_REG (Pmode, 8);
        got = sparc_tls_got ();
        emit_insn (gen_tgd_hi22 (temp1, addr));
        emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
        if (TARGET_ARCH32)
          {
            emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
            insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
                                                   addr, const1_rtx));
          }
        else
          {
            emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
            insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
                                                   addr, const1_rtx));
          }
        CALL_INSN_FUNCTION_USAGE (insn)
          = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
                               CALL_INSN_FUNCTION_USAGE (insn));
        insn = get_insns ();
        end_sequence ();
        emit_libcall_block (insn, ret, o0, addr);
        break;

      case TLS_MODEL_LOCAL_DYNAMIC:
        start_sequence ();
        temp1 = gen_reg_rtx (SImode);
        temp2 = gen_reg_rtx (SImode);
        temp3 = gen_reg_rtx (Pmode);
        ret = gen_reg_rtx (Pmode);
        o0 = gen_rtx_REG (Pmode, 8);
        got = sparc_tls_got ();
        emit_insn (gen_tldm_hi22 (temp1));
        emit_insn (gen_tldm_lo10 (temp2, temp1));
        if (TARGET_ARCH32)
          {
            emit_insn (gen_tldm_add32 (o0, got, temp2));
            insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
                                                    const1_rtx));
          }
        else
          {
            emit_insn (gen_tldm_add64 (o0, got, temp2));
            insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
                                                    const1_rtx));
          }
        CALL_INSN_FUNCTION_USAGE (insn)
          = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
                               CALL_INSN_FUNCTION_USAGE (insn));
        insn = get_insns ();
        end_sequence ();
        emit_libcall_block (insn, temp3, o0,
                            gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
                                            UNSPEC_TLSLD_BASE));
        temp1 = gen_reg_rtx (SImode);
        temp2 = gen_reg_rtx (SImode);
        emit_insn (gen_tldo_hix22 (temp1, addr));
        emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
        if (TARGET_ARCH32)
          emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
        else
          emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
        break;

      case TLS_MODEL_INITIAL_EXEC:
        temp1 = gen_reg_rtx (SImode);
        temp2 = gen_reg_rtx (SImode);
        temp3 = gen_reg_rtx (Pmode);
        got = sparc_tls_got ();
        emit_insn (gen_tie_hi22 (temp1, addr));
        emit_insn (gen_tie_lo10 (temp2, temp1, addr));
        if (TARGET_ARCH32)
          emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
        else
          emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
        if (TARGET_SUN_TLS)
          {
            ret = gen_reg_rtx (Pmode);
            if (TARGET_ARCH32)
              emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
                                        temp3, addr));
            else
              emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
                                        temp3, addr));
          }
        else
          ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
        break;

      case TLS_MODEL_LOCAL_EXEC:
        temp1 = gen_reg_rtx (Pmode);
        temp2 = gen_reg_rtx (Pmode);
        if (TARGET_ARCH32)
          {
            emit_insn (gen_tle_hix22_sp32 (temp1, addr));
            emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
          }
        else
          {
            emit_insn (gen_tle_hix22_sp64 (temp1, addr));
            emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
          }
        ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
        break;

      default:
        gcc_unreachable ();
      }

  else
    gcc_unreachable ();  /* for now ... */

  return ret;
}


/* Legitimize PIC addresses.  If the address is already position-independent,
   we return ORIG.  Newly generated position-independent addresses go into a
   reg.  This is REG if nonzero, otherwise we allocate register(s) as
   necessary.  */

rtx
legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
                        rtx reg)
{
  if (GET_CODE (orig) == SYMBOL_REF
      /* See the comment in sparc_expand_move.  */
      || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF))
    {
      rtx pic_ref, address;
      rtx insn;

      if (reg == 0)
        {
          gcc_assert (! reload_in_progress && ! reload_completed);
          reg = gen_reg_rtx (Pmode);
        }

      if (flag_pic == 2)
        {
          /* If not during reload, allocate another temp reg here for loading
             in the address, so that these instructions can be optimized
             properly.  */
          rtx temp_reg = ((reload_in_progress || reload_completed)
                          ? reg : gen_reg_rtx (Pmode));

          /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
             won't get confused into thinking that these two instructions
             are loading in the true address of the symbol.  If in the
             future a PIC rtx exists, that should be used instead.  */
          if (TARGET_ARCH64)
            {
              emit_insn (gen_movdi_high_pic (temp_reg, orig));
              emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
            }
          else
            {
              emit_insn (gen_movsi_high_pic (temp_reg, orig));
              emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
            }
          address = temp_reg;
        }
      else
        address = orig;

      pic_ref = gen_const_mem (Pmode,
                               gen_rtx_PLUS (Pmode,
                                             pic_offset_table_rtx, address));
      current_function_uses_pic_offset_table = 1;
      insn = emit_move_insn (reg, pic_ref);
      /* Put a REG_EQUAL note on this insn, so that it can be optimized
         by loop.  */
      set_unique_reg_note (insn, REG_EQUAL, orig);
      return reg;
    }
  else if (GET_CODE (orig) == CONST)
    {
      rtx base, offset;

      if (GET_CODE (XEXP (orig, 0)) == PLUS
          && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
        return orig;

      if (reg == 0)
        {
          gcc_assert (! reload_in_progress && ! reload_completed);
          reg = gen_reg_rtx (Pmode);
        }

      gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
      base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
      offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
                                       base == reg ? 0 : reg);

      if (GET_CODE (offset) == CONST_INT)
        {
          if (SMALL_INT (offset))
            return plus_constant (base, INTVAL (offset));
          else if (! reload_in_progress && ! reload_completed)
            offset = force_reg (Pmode, offset);
          else
            /* If we reach here, then something is seriously wrong.  */
            gcc_unreachable ();
        }
      return gen_rtx_PLUS (Pmode, base, offset);
    }
  else if (GET_CODE (orig) == LABEL_REF)
    /* ??? Why do we do this?  */
    /* Now movsi_pic_label_ref uses it, but we ought to be checking that
       the register is live instead, in case it is eliminated.  */
    current_function_uses_pic_offset_table = 1;

  return orig;
}

/* Try machine-dependent ways of modifying an illegitimate address X
   to be legitimate.  If we find one, return the new, valid address.

   OLDX is the address as it was before break_out_memory_refs was called.
   In some cases it is useful to look at this to decide what needs to be done.

   MODE is the mode of the operand pointed to by X.  */

rtx
legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
{
  rtx orig_x = x;

  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
    x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
                      force_operand (XEXP (x, 0), NULL_RTX));
  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
                      force_operand (XEXP (x, 1), NULL_RTX));
  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
    x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
                      XEXP (x, 1));
  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
                      force_operand (XEXP (x, 1), NULL_RTX));

  if (x != orig_x && legitimate_address_p (mode, x, FALSE))
    return x;

  if (SPARC_SYMBOL_REF_TLS_P (x))
    x = legitimize_tls_address (x);
  else if (flag_pic)
    x = legitimize_pic_address (x, mode, 0);
  else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
                      copy_to_mode_reg (Pmode, XEXP (x, 1)));
  else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
    x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
                      copy_to_mode_reg (Pmode, XEXP (x, 0)));
  else if (GET_CODE (x) == SYMBOL_REF
           || GET_CODE (x) == CONST
           || GET_CODE (x) == LABEL_REF)
    x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
  return x;
}

/* Emit the special PIC helper function.  */

static void
emit_pic_helper (void)
{
  const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
  int align;

  switch_to_section (text_section);

  align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
  if (align > 0)
    ASM_OUTPUT_ALIGN (asm_out_file, align);
  ASM_OUTPUT_LABEL (asm_out_file, pic_helper_symbol_name);
  if (flag_delayed_branch)
    fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
            pic_name, pic_name);
  else
    fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
            pic_name, pic_name);

  pic_helper_emitted_p = true;
}

/* Emit code to load the PIC register.  */

static void
load_pic_register (bool delay_pic_helper)
{
  int orig_flag_pic = flag_pic;

  if (TARGET_VXWORKS_RTP)
    {
      emit_insn (gen_vxworks_load_got ());
      emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
      return;
    }

  /* If we haven't initialized the special PIC symbols, do so now.  */
  if (!pic_helper_symbol_name[0])
    {
      ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name, "LADDPC", 0);
      pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, pic_helper_symbol_name);
      global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
    }

  /* If we haven't emitted the special PIC helper function, do so now unless
     we are requested to delay it.  */
  if (!delay_pic_helper && !pic_helper_emitted_p)
    emit_pic_helper ();

  flag_pic = 0;