1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "cfglayout.h"
51 #include "tree-gimple.h"
52 #include "langhooks.h"
56 struct processor_costs cypress_costs = {
57 COSTS_N_INSNS (2), /* int load */
58 COSTS_N_INSNS (2), /* int signed load */
59 COSTS_N_INSNS (2), /* int zeroed load */
60 COSTS_N_INSNS (2), /* float load */
61 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
62 COSTS_N_INSNS (5), /* fadd, fsub */
63 COSTS_N_INSNS (1), /* fcmp */
64 COSTS_N_INSNS (1), /* fmov, fmovr */
65 COSTS_N_INSNS (7), /* fmul */
66 COSTS_N_INSNS (37), /* fdivs */
67 COSTS_N_INSNS (37), /* fdivd */
68 COSTS_N_INSNS (63), /* fsqrts */
69 COSTS_N_INSNS (63), /* fsqrtd */
70 COSTS_N_INSNS (1), /* imul */
71 COSTS_N_INSNS (1), /* imulX */
72 0, /* imul bit factor */
73 COSTS_N_INSNS (1), /* idiv */
74 COSTS_N_INSNS (1), /* idivX */
75 COSTS_N_INSNS (1), /* movcc/movr */
76 0, /* shift penalty */
80 struct processor_costs supersparc_costs = {
81 COSTS_N_INSNS (1), /* int load */
82 COSTS_N_INSNS (1), /* int signed load */
83 COSTS_N_INSNS (1), /* int zeroed load */
84 COSTS_N_INSNS (0), /* float load */
85 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
86 COSTS_N_INSNS (3), /* fadd, fsub */
87 COSTS_N_INSNS (3), /* fcmp */
88 COSTS_N_INSNS (1), /* fmov, fmovr */
89 COSTS_N_INSNS (3), /* fmul */
90 COSTS_N_INSNS (6), /* fdivs */
91 COSTS_N_INSNS (9), /* fdivd */
92 COSTS_N_INSNS (12), /* fsqrts */
93 COSTS_N_INSNS (12), /* fsqrtd */
94 COSTS_N_INSNS (4), /* imul */
95 COSTS_N_INSNS (4), /* imulX */
96 0, /* imul bit factor */
97 COSTS_N_INSNS (4), /* idiv */
98 COSTS_N_INSNS (4), /* idivX */
99 COSTS_N_INSNS (1), /* movcc/movr */
100 1, /* shift penalty */
104 struct processor_costs hypersparc_costs = {
105 COSTS_N_INSNS (1), /* int load */
106 COSTS_N_INSNS (1), /* int signed load */
107 COSTS_N_INSNS (1), /* int zeroed load */
108 COSTS_N_INSNS (1), /* float load */
109 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
110 COSTS_N_INSNS (1), /* fadd, fsub */
111 COSTS_N_INSNS (1), /* fcmp */
112 COSTS_N_INSNS (1), /* fmov, fmovr */
113 COSTS_N_INSNS (1), /* fmul */
114 COSTS_N_INSNS (8), /* fdivs */
115 COSTS_N_INSNS (12), /* fdivd */
116 COSTS_N_INSNS (17), /* fsqrts */
117 COSTS_N_INSNS (17), /* fsqrtd */
118 COSTS_N_INSNS (17), /* imul */
119 COSTS_N_INSNS (17), /* imulX */
120 0, /* imul bit factor */
121 COSTS_N_INSNS (17), /* idiv */
122 COSTS_N_INSNS (17), /* idivX */
123 COSTS_N_INSNS (1), /* movcc/movr */
124 0, /* shift penalty */
128 struct processor_costs sparclet_costs = {
129 COSTS_N_INSNS (3), /* int load */
130 COSTS_N_INSNS (3), /* int signed load */
131 COSTS_N_INSNS (1), /* int zeroed load */
132 COSTS_N_INSNS (1), /* float load */
133 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
134 COSTS_N_INSNS (1), /* fadd, fsub */
135 COSTS_N_INSNS (1), /* fcmp */
136 COSTS_N_INSNS (1), /* fmov, fmovr */
137 COSTS_N_INSNS (1), /* fmul */
138 COSTS_N_INSNS (1), /* fdivs */
139 COSTS_N_INSNS (1), /* fdivd */
140 COSTS_N_INSNS (1), /* fsqrts */
141 COSTS_N_INSNS (1), /* fsqrtd */
142 COSTS_N_INSNS (5), /* imul */
143 COSTS_N_INSNS (5), /* imulX */
144 0, /* imul bit factor */
145 COSTS_N_INSNS (5), /* idiv */
146 COSTS_N_INSNS (5), /* idivX */
147 COSTS_N_INSNS (1), /* movcc/movr */
148 0, /* shift penalty */
152 struct processor_costs ultrasparc_costs = {
153 COSTS_N_INSNS (2), /* int load */
154 COSTS_N_INSNS (3), /* int signed load */
155 COSTS_N_INSNS (2), /* int zeroed load */
156 COSTS_N_INSNS (2), /* float load */
157 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
158 COSTS_N_INSNS (4), /* fadd, fsub */
159 COSTS_N_INSNS (1), /* fcmp */
160 COSTS_N_INSNS (2), /* fmov, fmovr */
161 COSTS_N_INSNS (4), /* fmul */
162 COSTS_N_INSNS (13), /* fdivs */
163 COSTS_N_INSNS (23), /* fdivd */
164 COSTS_N_INSNS (13), /* fsqrts */
165 COSTS_N_INSNS (23), /* fsqrtd */
166 COSTS_N_INSNS (4), /* imul */
167 COSTS_N_INSNS (4), /* imulX */
168 2, /* imul bit factor */
169 COSTS_N_INSNS (37), /* idiv */
170 COSTS_N_INSNS (68), /* idivX */
171 COSTS_N_INSNS (2), /* movcc/movr */
172 2, /* shift penalty */
176 struct processor_costs ultrasparc3_costs = {
177 COSTS_N_INSNS (2), /* int load */
178 COSTS_N_INSNS (3), /* int signed load */
179 COSTS_N_INSNS (3), /* int zeroed load */
180 COSTS_N_INSNS (2), /* float load */
181 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
182 COSTS_N_INSNS (4), /* fadd, fsub */
183 COSTS_N_INSNS (5), /* fcmp */
184 COSTS_N_INSNS (3), /* fmov, fmovr */
185 COSTS_N_INSNS (4), /* fmul */
186 COSTS_N_INSNS (17), /* fdivs */
187 COSTS_N_INSNS (20), /* fdivd */
188 COSTS_N_INSNS (20), /* fsqrts */
189 COSTS_N_INSNS (29), /* fsqrtd */
190 COSTS_N_INSNS (6), /* imul */
191 COSTS_N_INSNS (6), /* imulX */
192 0, /* imul bit factor */
193 COSTS_N_INSNS (40), /* idiv */
194 COSTS_N_INSNS (71), /* idivX */
195 COSTS_N_INSNS (2), /* movcc/movr */
196 0, /* shift penalty */
199 const struct processor_costs *sparc_costs = &cypress_costs;
201 #ifdef HAVE_AS_RELAX_OPTION
202 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
203 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
204 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
205 somebody does not branch between the sethi and jmp. */
206 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
208 #define LEAF_SIBCALL_SLOT_RESERVED_P \
209 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
212 /* Global variables for machine-dependent things. */
214 /* Size of frame. Need to know this to emit return insns from leaf procedures.
215 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
216 reload pass. This is important as the value is later used for scheduling
217 (to see what can go in a delay slot).
218 APPARENT_FSIZE is the size of the stack less the register save area and less
219 the outgoing argument area. It is used when saving call preserved regs. */
220 static HOST_WIDE_INT apparent_fsize;
221 static HOST_WIDE_INT actual_fsize;
223 /* Number of live general or floating point registers needed to be
224 saved (as 4-byte quantities). */
225 static int num_gfregs;
227 /* The alias set for prologue/epilogue register save/restore. */
228 static GTY(()) int sparc_sr_alias_set;
230 /* The alias set for the structure return value. */
231 static GTY(()) int struct_value_alias_set;
233 /* Save the operands last given to a compare for use when we
234 generate a scc or bcc insn. */
235 rtx sparc_compare_op0, sparc_compare_op1;
237 /* Vector to say how input registers are mapped to output registers.
238 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
239 eliminate it. You must use -fomit-frame-pointer to get that. */
240 char leaf_reg_remap[] =
241 { 0, 1, 2, 3, 4, 5, 6, 7,
242 -1, -1, -1, -1, -1, -1, 14, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1,
244 8, 9, 10, 11, 12, 13, -1, 15,
246 32, 33, 34, 35, 36, 37, 38, 39,
247 40, 41, 42, 43, 44, 45, 46, 47,
248 48, 49, 50, 51, 52, 53, 54, 55,
249 56, 57, 58, 59, 60, 61, 62, 63,
250 64, 65, 66, 67, 68, 69, 70, 71,
251 72, 73, 74, 75, 76, 77, 78, 79,
252 80, 81, 82, 83, 84, 85, 86, 87,
253 88, 89, 90, 91, 92, 93, 94, 95,
254 96, 97, 98, 99, 100};
256 /* Vector, indexed by hard register number, which contains 1
257 for a register that is allowable in a candidate for leaf
258 function treatment. */
259 char sparc_leaf_regs[] =
260 { 1, 1, 1, 1, 1, 1, 1, 1,
261 0, 0, 0, 0, 0, 0, 1, 0,
262 0, 0, 0, 0, 0, 0, 0, 0,
263 1, 1, 1, 1, 1, 1, 0, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1, 1, 1, 1,
268 1, 1, 1, 1, 1, 1, 1, 1,
269 1, 1, 1, 1, 1, 1, 1, 1,
270 1, 1, 1, 1, 1, 1, 1, 1,
271 1, 1, 1, 1, 1, 1, 1, 1,
274 struct machine_function GTY(())
276 /* Some local-dynamic TLS symbol name. */
277 const char *some_ld_name;
279 /* True if the current function is leaf and uses only leaf regs,
280 so that the SPARC leaf function optimization can be applied.
281 Private version of current_function_uses_only_leaf_regs, see
282 sparc_expand_prologue for the rationale. */
285 /* True if the data calculated by sparc_expand_prologue are valid. */
286 bool prologue_data_valid_p;
289 #define sparc_leaf_function_p cfun->machine->leaf_function_p
290 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
292 /* Register we pretend to think the frame pointer is allocated to.
293 Normally, this is %fp, but if we are in a leaf procedure, this
294 is %sp+"something". We record "something" separately as it may
295 be too big for reg+constant addressing. */
296 static rtx frame_base_reg;
297 static HOST_WIDE_INT frame_base_offset;
299 /* 1 if the next opcode is to be specially indented. */
300 int sparc_indent_opcode = 0;
302 static void sparc_init_modes (void);
303 static void scan_record_type (tree, int *, int *, int *);
304 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
305 tree, int, int, int *, int *);
307 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
308 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
310 static void sparc_output_addr_vec (rtx);
311 static void sparc_output_addr_diff_vec (rtx);
312 static void sparc_output_deferred_case_vectors (void);
313 static rtx sparc_builtin_saveregs (void);
314 static int epilogue_renumber (rtx *, int);
315 static bool sparc_assemble_integer (rtx, unsigned int, int);
316 static int set_extends (rtx);
317 static void emit_pic_helper (void);
318 static void load_pic_register (bool);
319 static int save_or_restore_regs (int, int, rtx, int, int);
320 static void emit_save_regs (void);
321 static void emit_restore_regs (void);
322 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
323 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
324 #ifdef OBJECT_FORMAT_ELF
325 static void sparc_elf_asm_named_section (const char *, unsigned int, tree);
328 static int sparc_adjust_cost (rtx, rtx, rtx, int);
329 static int sparc_issue_rate (void);
330 static void sparc_sched_init (FILE *, int, int);
331 static int sparc_use_sched_lookahead (void);
333 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
334 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
335 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
336 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
337 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
339 static bool sparc_function_ok_for_sibcall (tree, tree);
340 static void sparc_init_libfuncs (void);
341 static void sparc_init_builtins (void);
342 static void sparc_vis_init_builtins (void);
343 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
344 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
345 HOST_WIDE_INT, tree);
346 static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
347 HOST_WIDE_INT, tree);
348 static struct machine_function * sparc_init_machine_status (void);
349 static bool sparc_cannot_force_const_mem (rtx);
350 static rtx sparc_tls_get_addr (void);
351 static rtx sparc_tls_got (void);
352 static const char *get_some_local_dynamic_name (void);
353 static int get_some_local_dynamic_name_1 (rtx *, void *);
354 static bool sparc_rtx_costs (rtx, int, int, int *);
355 static bool sparc_promote_prototypes (tree);
356 static rtx sparc_struct_value_rtx (tree, int);
357 static bool sparc_return_in_memory (tree, tree);
358 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
359 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
360 static bool sparc_vector_mode_supported_p (enum machine_mode);
361 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
362 enum machine_mode, tree, bool);
363 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *,
364 enum machine_mode, tree, bool);
365 static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int);
366 static void sparc_file_end (void);
367 #ifdef SUBTARGET_ATTRIBUTE_TABLE
368 const struct attribute_spec sparc_attribute_table[];
371 /* Option handling. */
373 /* Code model option as passed by user. */
374 const char *sparc_cmodel_string;
376 enum cmodel sparc_cmodel;
378 char sparc_hard_reg_printed[8];
380 struct sparc_cpu_select sparc_select[] =
382 /* switch name, tune arch */
383 { (char *)0, "default", 1, 1 },
384 { (char *)0, "-mcpu=", 1, 1 },
385 { (char *)0, "-mtune=", 1, 0 },
389 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
390 enum processor_type sparc_cpu;
392 /* Initialize the GCC target structure. */
394 /* The sparc default is to use .half rather than .short for aligned
395 HI objects. Use .word instead of .long on non-ELF systems. */
396 #undef TARGET_ASM_ALIGNED_HI_OP
397 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
398 #ifndef OBJECT_FORMAT_ELF
399 #undef TARGET_ASM_ALIGNED_SI_OP
400 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
403 #undef TARGET_ASM_UNALIGNED_HI_OP
404 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
405 #undef TARGET_ASM_UNALIGNED_SI_OP
406 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
407 #undef TARGET_ASM_UNALIGNED_DI_OP
408 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
410 /* The target hook has to handle DI-mode values. */
411 #undef TARGET_ASM_INTEGER
412 #define TARGET_ASM_INTEGER sparc_assemble_integer
414 #undef TARGET_ASM_FUNCTION_PROLOGUE
415 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
416 #undef TARGET_ASM_FUNCTION_EPILOGUE
417 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
419 #undef TARGET_SCHED_ADJUST_COST
420 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
421 #undef TARGET_SCHED_ISSUE_RATE
422 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
423 #undef TARGET_SCHED_INIT
424 #define TARGET_SCHED_INIT sparc_sched_init
425 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
426 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
428 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
429 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
431 #undef TARGET_INIT_LIBFUNCS
432 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
433 #undef TARGET_INIT_BUILTINS
434 #define TARGET_INIT_BUILTINS sparc_init_builtins
436 #undef TARGET_EXPAND_BUILTIN
437 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
440 #undef TARGET_HAVE_TLS
441 #define TARGET_HAVE_TLS true
443 #undef TARGET_CANNOT_FORCE_CONST_MEM
444 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
446 #undef TARGET_ASM_OUTPUT_MI_THUNK
447 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
448 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
449 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
451 #undef TARGET_RTX_COSTS
452 #define TARGET_RTX_COSTS sparc_rtx_costs
453 #undef TARGET_ADDRESS_COST
454 #define TARGET_ADDRESS_COST hook_int_rtx_0
456 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
457 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
458 test for this value. */
459 #undef TARGET_PROMOTE_FUNCTION_ARGS
460 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
462 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
463 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
464 test for this value. */
465 #undef TARGET_PROMOTE_FUNCTION_RETURN
466 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
468 #undef TARGET_PROMOTE_PROTOTYPES
469 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
471 #undef TARGET_STRUCT_VALUE_RTX
472 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
473 #undef TARGET_RETURN_IN_MEMORY
474 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
475 #undef TARGET_MUST_PASS_IN_STACK
476 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
477 #undef TARGET_PASS_BY_REFERENCE
478 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
479 #undef TARGET_ARG_PARTIAL_BYTES
480 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
482 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
483 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
484 #undef TARGET_STRICT_ARGUMENT_NAMING
485 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
487 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
488 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
490 #undef TARGET_VECTOR_MODE_SUPPORTED_P
491 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
493 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
494 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
496 #ifdef SUBTARGET_INSERT_ATTRIBUTES
497 #undef TARGET_INSERT_ATTRIBUTES
498 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
501 #ifdef SUBTARGET_ATTRIBUTE_TABLE
502 #undef TARGET_ATTRIBUTE_TABLE
503 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
506 #undef TARGET_RELAXED_ORDERING
507 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
509 #undef TARGET_ASM_FILE_END
510 #define TARGET_ASM_FILE_END sparc_file_end
512 struct gcc_target targetm = TARGET_INITIALIZER;
514 /* Validate and override various options, and do some machine dependent
518 sparc_override_options (void)
520 static struct code_model {
521 const char *const name;
523 } const cmodels[] = {
525 { "medlow", CM_MEDLOW },
526 { "medmid", CM_MEDMID },
527 { "medany", CM_MEDANY },
528 { "embmedany", CM_EMBMEDANY },
531 const struct code_model *cmodel;
532 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
533 static struct cpu_default {
535 const char *const name;
536 } const cpu_default[] = {
537 /* There must be one entry here for each TARGET_CPU value. */
538 { TARGET_CPU_sparc, "cypress" },
539 { TARGET_CPU_sparclet, "tsc701" },
540 { TARGET_CPU_sparclite, "f930" },
541 { TARGET_CPU_v8, "v8" },
542 { TARGET_CPU_hypersparc, "hypersparc" },
543 { TARGET_CPU_sparclite86x, "sparclite86x" },
544 { TARGET_CPU_supersparc, "supersparc" },
545 { TARGET_CPU_v9, "v9" },
546 { TARGET_CPU_ultrasparc, "ultrasparc" },
547 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
550 const struct cpu_default *def;
551 /* Table of values for -m{cpu,tune}=. */
552 static struct cpu_table {
553 const char *const name;
554 const enum processor_type processor;
557 } const cpu_table[] = {
558 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
559 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
560 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
561 /* TI TMS390Z55 supersparc */
562 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
563 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
564 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
565 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
566 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
567 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
568 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
569 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
571 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
573 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
574 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
575 /* TI ultrasparc I, II, IIi */
576 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
577 /* Although insns using %y are deprecated, it is a clear win on current
579 |MASK_DEPRECATED_V8_INSNS},
580 /* TI ultrasparc III */
581 /* ??? Check if %y issue still holds true in ultra3. */
582 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
585 const struct cpu_table *cpu;
586 const struct sparc_cpu_select *sel;
589 #ifndef SPARC_BI_ARCH
590 /* Check for unsupported architecture size. */
591 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
592 error ("%s is not supported by this configuration",
593 DEFAULT_ARCH32_P ? "-m64" : "-m32");
596 /* We force all 64bit archs to use 128 bit long double */
597 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
599 error ("-mlong-double-64 not allowed with -m64");
600 target_flags |= MASK_LONG_DOUBLE_128;
603 /* Code model selection. */
604 sparc_cmodel = SPARC_DEFAULT_CMODEL;
608 sparc_cmodel = CM_32;
611 if (sparc_cmodel_string != NULL)
615 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
616 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
618 if (cmodel->name == NULL)
619 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
621 sparc_cmodel = cmodel->value;
624 error ("-mcmodel= is not supported on 32 bit systems");
627 fpu = TARGET_FPU; /* save current -mfpu status */
629 /* Set the default CPU. */
630 for (def = &cpu_default[0]; def->name; ++def)
631 if (def->cpu == TARGET_CPU_DEFAULT)
635 sparc_select[0].string = def->name;
637 for (sel = &sparc_select[0]; sel->name; ++sel)
641 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
642 if (! strcmp (sel->string, cpu->name))
645 sparc_cpu = cpu->processor;
649 target_flags &= ~cpu->disable;
650 target_flags |= cpu->enable;
656 error ("bad value (%s) for %s switch", sel->string, sel->name);
660 /* If -mfpu or -mno-fpu was explicitly used, don't override with
661 the processor default. Clear MASK_FPU_SET to avoid confusing
662 the reverse mapping from switch values to names. */
665 target_flags = (target_flags & ~MASK_FPU) | fpu;
666 target_flags &= ~MASK_FPU_SET;
669 /* Don't allow -mvis if FPU is disabled. */
671 target_flags &= ~MASK_VIS;
673 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
675 -m64 also implies v9. */
676 if (TARGET_VIS || TARGET_ARCH64)
678 target_flags |= MASK_V9;
679 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
682 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
683 if (TARGET_V9 && TARGET_ARCH32)
684 target_flags |= MASK_DEPRECATED_V8_INSNS;
686 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
687 if (! TARGET_V9 || TARGET_ARCH64)
688 target_flags &= ~MASK_V8PLUS;
690 /* Don't use stack biasing in 32 bit mode. */
692 target_flags &= ~MASK_STACK_BIAS;
694 /* Supply a default value for align_functions. */
695 if (align_functions == 0
696 && (sparc_cpu == PROCESSOR_ULTRASPARC
697 || sparc_cpu == PROCESSOR_ULTRASPARC3))
698 align_functions = 32;
700 /* Validate PCC_STRUCT_RETURN. */
701 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
702 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
704 /* Only use .uaxword when compiling for a 64-bit target. */
706 targetm.asm_out.unaligned_op.di = NULL;
708 /* Do various machine dependent initializations. */
711 /* Acquire unique alias sets for our private stuff. */
712 sparc_sr_alias_set = new_alias_set ();
713 struct_value_alias_set = new_alias_set ();
715 /* Set up function hooks. */
716 init_machine_status = sparc_init_machine_status;
721 case PROCESSOR_CYPRESS:
722 sparc_costs = &cypress_costs;
725 case PROCESSOR_SPARCLITE:
726 case PROCESSOR_SUPERSPARC:
727 sparc_costs = &supersparc_costs;
731 case PROCESSOR_HYPERSPARC:
732 case PROCESSOR_SPARCLITE86X:
733 sparc_costs = &hypersparc_costs;
735 case PROCESSOR_SPARCLET:
736 case PROCESSOR_TSC701:
737 sparc_costs = &sparclet_costs;
740 case PROCESSOR_ULTRASPARC:
741 sparc_costs = &ultrasparc_costs;
743 case PROCESSOR_ULTRASPARC3:
744 sparc_costs = &ultrasparc3_costs;
749 #ifdef SUBTARGET_ATTRIBUTE_TABLE
750 /* Table of valid machine attributes. */
751 const struct attribute_spec sparc_attribute_table[] =
753 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
754 SUBTARGET_ATTRIBUTE_TABLE,
755 { NULL, 0, 0, false, false, false, NULL }
759 /* Miscellaneous utilities. */
761 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
762 or branch on register contents instructions. */
765 v9_regcmp_p (enum rtx_code code)
767 return (code == EQ || code == NE || code == GE || code == LT
768 || code == LE || code == GT);
772 /* Operand constraints. */
774 /* Return nonzero only if OP is a register of mode MODE,
778 reg_or_0_operand (rtx op, enum machine_mode mode)
780 if (register_operand (op, mode))
782 if (op == const0_rtx)
784 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
785 && CONST_DOUBLE_HIGH (op) == 0
786 && CONST_DOUBLE_LOW (op) == 0)
788 if (fp_zero_operand (op, mode))
793 /* Return nonzero only if OP is const1_rtx. */
796 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
798 return op == const1_rtx;
801 /* Nonzero if OP is a floating point value with value 0.0. */
804 fp_zero_operand (rtx op, enum machine_mode mode)
806 enum mode_class mclass = GET_MODE_CLASS (GET_MODE (op));
807 if (mclass != MODE_FLOAT && mclass != MODE_VECTOR_INT)
809 return op == CONST0_RTX (mode);
812 /* Nonzero if OP is a register operand in floating point register. */
815 fp_register_operand (rtx op, enum machine_mode mode)
817 if (! register_operand (op, mode))
819 if (GET_CODE (op) == SUBREG)
820 op = SUBREG_REG (op);
821 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
824 /* Nonzero if OP is a floating point constant which can
825 be loaded into an integer register using a single
826 sethi instruction. */
831 if (GET_CODE (op) == CONST_DOUBLE)
836 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
837 if (REAL_VALUES_EQUAL (r, dconst0) &&
838 ! REAL_VALUE_MINUS_ZERO (r))
840 REAL_VALUE_TO_TARGET_SINGLE (r, i);
841 if (SPARC_SETHI_P (i))
848 /* Nonzero if OP is a floating point constant which can
849 be loaded into an integer register using a single
855 if (GET_CODE (op) == CONST_DOUBLE)
860 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
861 if (REAL_VALUES_EQUAL (r, dconst0) &&
862 ! REAL_VALUE_MINUS_ZERO (r))
864 REAL_VALUE_TO_TARGET_SINGLE (r, i);
865 if (SPARC_SIMM13_P (i))
872 /* Nonzero if OP is a floating point constant which can
873 be loaded into an integer register using a high/losum
874 instruction sequence. */
877 fp_high_losum_p (rtx op)
879 /* The constraints calling this should only be in
880 SFmode move insns, so any constant which cannot
881 be moved using a single insn will do. */
882 if (GET_CODE (op) == CONST_DOUBLE)
887 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
888 if (REAL_VALUES_EQUAL (r, dconst0) &&
889 ! REAL_VALUE_MINUS_ZERO (r))
891 REAL_VALUE_TO_TARGET_SINGLE (r, i);
892 if (! SPARC_SETHI_P (i)
893 && ! SPARC_SIMM13_P (i))
900 /* Nonzero if OP is an integer register. */
903 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
905 return (register_operand (op, SImode)
906 || (TARGET_ARCH64 && register_operand (op, DImode)));
909 /* Nonzero if OP is a floating point condition code register. */
912 fcc_reg_operand (rtx op, enum machine_mode mode)
914 /* This can happen when recog is called from combine. Op may be a MEM.
915 Fail instead of calling abort in this case. */
916 if (GET_CODE (op) != REG)
919 if (mode != VOIDmode && mode != GET_MODE (op))
922 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
925 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
926 if (reg_renumber == 0)
927 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
928 return REGNO_OK_FOR_CCFP_P (REGNO (op));
930 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
934 /* Nonzero if OP is a floating point condition code fcc0 register. */
937 fcc0_reg_operand (rtx op, enum machine_mode mode)
939 /* This can happen when recog is called from combine. Op may be a MEM.
940 Fail instead of calling abort in this case. */
941 if (GET_CODE (op) != REG)
944 if (mode != VOIDmode && mode != GET_MODE (op))
947 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
950 return REGNO (op) == SPARC_FCC_REG;
953 /* Nonzero if OP is an integer or floating point condition code register. */
956 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
958 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
960 if (mode != VOIDmode && mode != GET_MODE (op))
963 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
968 return fcc_reg_operand (op, mode);
971 /* Call insn on SPARC can take a PC-relative constant address, or any regular
975 call_operand (rtx op, enum machine_mode mode)
977 if (GET_CODE (op) != MEM)
980 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
984 call_operand_address (rtx op, enum machine_mode mode)
986 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
989 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
990 otherwise return 0. */
993 tls_symbolic_operand (rtx op)
995 if (GET_CODE (op) != SYMBOL_REF)
997 return SYMBOL_REF_TLS_MODEL (op);
1001 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1003 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
1007 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1009 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
1013 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1015 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
1019 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1021 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
1024 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1025 reference and a constant. */
1028 symbolic_operand (register rtx op, enum machine_mode mode)
1030 enum machine_mode omode = GET_MODE (op);
1032 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
1035 switch (GET_CODE (op))
1038 return !SYMBOL_REF_TLS_MODEL (op);
1045 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1046 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
1047 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1048 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1055 /* Return truth value of statement that OP is a symbolic memory
1056 operand of mode MODE. */
1059 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1061 if (GET_CODE (op) == SUBREG)
1062 op = SUBREG_REG (op);
1063 if (GET_CODE (op) != MEM)
1066 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
1067 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
1068 || GET_CODE (op) == LABEL_REF);
1071 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1074 label_ref_operand (rtx op, enum machine_mode mode)
1076 if (GET_CODE (op) != LABEL_REF)
1078 if (GET_MODE (op) != mode)
1083 /* Return 1 if the operand is an argument used in generating pic references
1084 in either the medium/low or medium/anywhere code models of sparc64. */
1087 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1089 /* Check for (const (minus (symbol_ref:GOT)
1090 (const (minus (label) (pc))))). */
1091 if (GET_CODE (op) != CONST)
1094 if (GET_CODE (op) != MINUS)
1096 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1098 /* ??? Ensure symbol is GOT. */
1099 if (GET_CODE (XEXP (op, 1)) != CONST)
1101 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1106 /* Return 1 if the operand is a data segment reference. This includes
1107 the readonly data segment, or in other words anything but the text segment.
1108 This is needed in the medium/anywhere code model on v9. These values
1109 are accessed with EMBMEDANY_BASE_REG. */
1112 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1114 switch (GET_CODE (op))
1117 return ! SYMBOL_REF_FUNCTION_P (op);
1119 /* Assume canonical format of symbol + constant.
1122 return data_segment_operand (XEXP (op, 0), VOIDmode);
1128 /* Return 1 if the operand is a text segment reference.
1129 This is needed in the medium/anywhere code model on v9. */
1132 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1134 switch (GET_CODE (op))
1139 return SYMBOL_REF_FUNCTION_P (op);
1141 /* Assume canonical format of symbol + constant.
1144 return text_segment_operand (XEXP (op, 0), VOIDmode);
1150 /* Return 1 if the operand is either a register or a memory operand that is
1154 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1156 if (register_operand (op, mode))
1159 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1166 splittable_symbolic_memory_operand (rtx op,
1167 enum machine_mode mode ATTRIBUTE_UNUSED)
1169 if (GET_CODE (op) != MEM)
1171 if (! symbolic_operand (XEXP (op, 0), Pmode))
1177 splittable_immediate_memory_operand (rtx op,
1178 enum machine_mode mode ATTRIBUTE_UNUSED)
1180 if (GET_CODE (op) != MEM)
1182 if (! immediate_operand (XEXP (op, 0), Pmode))
1187 /* Return truth value of whether OP is EQ or NE. */
1190 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1192 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1195 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1196 or LTU for non-floating-point. We handle those specially. */
1199 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1203 if (!COMPARISON_P (op))
1206 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1207 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1210 code = GET_CODE (op);
1211 return (code != NE && code != EQ && code != GEU && code != LTU);
1214 /* Return 1 if this is a comparison operator. This allows the use of
1215 MATCH_OPERATOR to recognize all the branch insns. */
1218 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1222 if (!COMPARISON_P (op))
1225 code = GET_CODE (op);
1226 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1227 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1228 /* These are the only branches which work with CC_NOOVmode. */
1229 return (code == EQ || code == NE || code == GE || code == LT);
1233 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1234 MATCH_OPERATOR to recognize all the branch insns. */
1237 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1244 if (!COMPARISON_P (op))
1247 code = GET_CODE (op);
1248 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1249 /* These are the only branches which work with CCX_NOOVmode. */
1250 return (code == EQ || code == NE || code == GE || code == LT);
1251 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1254 /* Nonzero if OP is a comparison operator suitable for use in v9
1255 conditional move or branch on register contents instructions. */
1258 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1262 if (!COMPARISON_P (op))
1265 code = GET_CODE (op);
1266 return v9_regcmp_p (code);
1269 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1272 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1274 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1277 /* Return nonzero if OP is an operator of mode MODE which can set
1278 the condition codes explicitly. We do not include PLUS and MINUS
1279 because these require CC_NOOVmode, which we handle explicitly. */
1282 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1284 if (GET_CODE (op) == AND
1285 || GET_CODE (op) == IOR
1286 || GET_CODE (op) == XOR)
1292 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1293 complement its second operand and set the condition codes explicitly. */
1296 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1298 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1299 and (xor ... (not ...)) to (not (xor ...)). */
1300 return (GET_CODE (op) == AND
1301 || GET_CODE (op) == IOR);
1304 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1305 signed 13 bit immediate field. This is an acceptable SImode operand for
1306 most 3 address instructions. */
1309 arith_operand (rtx op, enum machine_mode mode)
1311 if (register_operand (op, mode))
1313 if (GET_CODE (op) != CONST_INT)
1315 return SMALL_INT32 (op);
1318 /* Return true if OP is a constant 4096 */
1321 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1323 if (GET_CODE (op) != CONST_INT)
1326 return INTVAL (op) == 4096;
1329 /* Return true if OP is suitable as second operand for add/sub */
1332 arith_add_operand (rtx op, enum machine_mode mode)
1334 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1337 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1338 immediate field of OR and XOR instructions. Used for 64-bit
1339 constant formation patterns. */
1341 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1343 return ((GET_CODE (op) == CONST_INT
1344 && SPARC_SIMM13_P (INTVAL (op)))
1345 #if HOST_BITS_PER_WIDE_INT != 64
1346 || (GET_CODE (op) == CONST_DOUBLE
1347 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1348 && (CONST_DOUBLE_HIGH (op) ==
1349 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1350 (HOST_WIDE_INT)-1 : 0)))
1355 /* The same, but only for sethi instructions. */
1357 const64_high_operand (rtx op, enum machine_mode mode)
1359 return ((GET_CODE (op) == CONST_INT
1360 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1361 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1363 || (GET_CODE (op) == CONST_DOUBLE
1364 && CONST_DOUBLE_HIGH (op) == 0
1365 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1366 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1369 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1370 signed 11 bit immediate field. This is an acceptable SImode operand for
1371 the movcc instructions. */
1374 arith11_operand (rtx op, enum machine_mode mode)
1376 return (register_operand (op, mode)
1377 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1380 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1381 signed 10 bit immediate field. This is an acceptable SImode operand for
1382 the movrcc instructions. */
1385 arith10_operand (rtx op, enum machine_mode mode)
1387 return (register_operand (op, mode)
1388 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1391 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1392 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1394 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1395 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1396 for most 3 address instructions. */
1399 arith_double_operand (rtx op, enum machine_mode mode)
1401 return (register_operand (op, mode)
1402 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1404 && GET_CODE (op) == CONST_DOUBLE
1405 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1406 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1408 && GET_CODE (op) == CONST_DOUBLE
1409 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1410 && ((CONST_DOUBLE_HIGH (op) == -1
1411 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1412 || (CONST_DOUBLE_HIGH (op) == 0
1413 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1416 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1419 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1421 return (TARGET_ARCH64 &&
1422 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1423 (GET_CODE (op) == CONST_DOUBLE &&
1424 CONST_DOUBLE_LOW (op) == 4096 &&
1425 CONST_DOUBLE_HIGH (op) == 0)));
1428 /* Return true if OP is suitable as second operand for add/sub in DImode */
1431 arith_double_add_operand (rtx op, enum machine_mode mode)
1433 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1436 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1437 can fit in an 11 bit immediate field. This is an acceptable DImode
1438 operand for the movcc instructions. */
1439 /* ??? Replace with arith11_operand? */
1442 arith11_double_operand (rtx op, enum machine_mode mode)
1444 return (register_operand (op, mode)
1445 || (GET_CODE (op) == CONST_DOUBLE
1446 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1447 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1448 && ((CONST_DOUBLE_HIGH (op) == -1
1449 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1450 || (CONST_DOUBLE_HIGH (op) == 0
1451 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1452 || (GET_CODE (op) == CONST_INT
1453 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1454 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1457 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1458 can fit in an 10 bit immediate field. This is an acceptable DImode
1459 operand for the movrcc instructions. */
1460 /* ??? Replace with arith10_operand? */
1463 arith10_double_operand (rtx op, enum machine_mode mode)
1465 return (register_operand (op, mode)
1466 || (GET_CODE (op) == CONST_DOUBLE
1467 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1468 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1469 && ((CONST_DOUBLE_HIGH (op) == -1
1470 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1471 || (CONST_DOUBLE_HIGH (op) == 0
1472 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1473 || (GET_CODE (op) == CONST_INT
1474 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1475 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1478 /* Return truth value of whether OP is an integer which fits the
1479 range constraining immediate operands in most three-address insns,
1480 which have a 13 bit immediate field. */
1483 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1485 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1489 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1491 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1492 || (GET_CODE (op) == CONST_DOUBLE
1493 && CONST_DOUBLE_HIGH (op) == 0
1494 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1497 /* Recognize operand values for the umul instruction. That instruction sign
1498 extends immediate values just like all other sparc instructions, but
1499 interprets the extended result as an unsigned number. */
1502 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1504 #if HOST_BITS_PER_WIDE_INT > 32
1505 /* All allowed constants will fit a CONST_INT. */
1506 return (GET_CODE (op) == CONST_INT
1507 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1508 || (INTVAL (op) >= 0xFFFFF000
1509 && INTVAL (op) <= 0xFFFFFFFF)));
1511 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1512 || (GET_CODE (op) == CONST_DOUBLE
1513 && CONST_DOUBLE_HIGH (op) == 0
1514 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1519 uns_arith_operand (rtx op, enum machine_mode mode)
1521 return register_operand (op, mode) || uns_small_int (op, mode);
1524 /* Return truth value of statement that OP is a call-clobbered register. */
1526 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1528 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1531 /* Return 1 if OP is a valid operand for the source of a move insn. */
1534 input_operand (rtx op, enum machine_mode mode)
1536 enum mode_class mclass;
1538 /* If both modes are non-void they must be the same. */
1539 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1542 /* Allow any one instruction integer constant, and all CONST_INT
1543 variants when we are working in DImode and !arch64. */
1544 if (GET_MODE_CLASS (mode) == MODE_INT
1545 && ((GET_CODE (op) == CONST_INT
1546 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1547 || SPARC_SIMM13_P (INTVAL (op))
1549 && ! TARGET_ARCH64)))
1551 && GET_CODE (op) == CONST_DOUBLE
1552 && ((CONST_DOUBLE_HIGH (op) == 0
1553 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1555 #if HOST_BITS_PER_WIDE_INT == 64
1556 (CONST_DOUBLE_HIGH (op) == 0
1557 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1559 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1560 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1561 && CONST_DOUBLE_HIGH (op) == 0)
1562 || (CONST_DOUBLE_HIGH (op) == -1
1563 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1568 /* If !arch64 and this is a DImode const, allow it so that
1569 the splits can be generated. */
1572 && GET_CODE (op) == CONST_DOUBLE)
1575 if (register_operand (op, mode))
1578 mclass = GET_MODE_CLASS (mode);
1579 if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
1580 || (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
1583 /* If this is a SUBREG, look inside so that we handle
1584 paradoxical ones. */
1585 if (GET_CODE (op) == SUBREG)
1586 op = SUBREG_REG (op);
1588 /* Check for valid MEM forms. */
1589 if (GET_CODE (op) == MEM)
1590 return memory_address_p (mode, XEXP (op, 0));
1595 /* Return 1 if OP is valid for the lhs of a compare insn. */
1598 compare_operand (rtx op, enum machine_mode mode)
1600 if (GET_CODE (op) == ZERO_EXTRACT)
1601 return (register_operand (XEXP (op, 0), mode)
1602 && small_int_or_double (XEXP (op, 1), mode)
1603 && small_int_or_double (XEXP (op, 2), mode)
1604 /* This matches cmp_zero_extract. */
1606 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1607 && INTVAL (XEXP (op, 2)) > 19)
1608 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1609 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1610 /* This matches cmp_zero_extract_sp64. */
1613 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1614 && INTVAL (XEXP (op, 2)) > 51)
1615 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1616 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1618 return register_operand (op, mode);
1622 /* We know it can't be done in one insn when we get here,
1623 the movsi expander guarantees this. */
1625 sparc_emit_set_const32 (rtx op0, rtx op1)
1627 enum machine_mode mode = GET_MODE (op0);
1630 if (GET_CODE (op1) == CONST_INT)
1632 HOST_WIDE_INT value = INTVAL (op1);
1634 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1635 || SPARC_SIMM13_P (value))
1639 /* Full 2-insn decomposition is needed. */
1640 if (reload_in_progress || reload_completed)
1643 temp = gen_reg_rtx (mode);
1645 if (GET_CODE (op1) == CONST_INT)
1647 /* Emit them as real moves instead of a HIGH/LO_SUM,
1648 this way CSE can see everything and reuse intermediate
1649 values if it wants. */
1651 && HOST_BITS_PER_WIDE_INT != 64
1652 && (INTVAL (op1) & 0x80000000) != 0)
1653 emit_insn (gen_rtx_SET
1655 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1658 emit_insn (gen_rtx_SET (VOIDmode, temp,
1659 GEN_INT (INTVAL (op1)
1660 & ~(HOST_WIDE_INT)0x3ff)));
1662 emit_insn (gen_rtx_SET (VOIDmode,
1664 gen_rtx_IOR (mode, temp,
1665 GEN_INT (INTVAL (op1) & 0x3ff))));
1669 /* A symbol, emit in the traditional way. */
1670 emit_insn (gen_rtx_SET (VOIDmode, temp,
1671 gen_rtx_HIGH (mode, op1)));
1672 emit_insn (gen_rtx_SET (VOIDmode,
1673 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1679 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1680 If TEMP is nonzero, we are forbidden to use any other scratch
1681 registers. Otherwise, we are allowed to generate them as needed.
1683 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1684 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1686 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1688 rtx temp1, temp2, temp3, temp4, temp5;
1691 if (temp && GET_MODE (temp) == TImode)
1694 temp = gen_rtx_REG (DImode, REGNO (temp));
1697 /* SPARC-V9 code-model support. */
1698 switch (sparc_cmodel)
1701 /* The range spanned by all instructions in the object is less
1702 than 2^31 bytes (2GB) and the distance from any instruction
1703 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1704 than 2^31 bytes (2GB).
1706 The executable must be in the low 4TB of the virtual address
1709 sethi %hi(symbol), %temp1
1710 or %temp1, %lo(symbol), %reg */
1712 temp1 = temp; /* op0 is allowed. */
1714 temp1 = gen_reg_rtx (DImode);
1716 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1717 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1721 /* The range spanned by all instructions in the object is less
1722 than 2^31 bytes (2GB) and the distance from any instruction
1723 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1724 than 2^31 bytes (2GB).
1726 The executable must be in the low 16TB of the virtual address
1729 sethi %h44(symbol), %temp1
1730 or %temp1, %m44(symbol), %temp2
1731 sllx %temp2, 12, %temp3
1732 or %temp3, %l44(symbol), %reg */
1737 temp3 = temp; /* op0 is allowed. */
1741 temp1 = gen_reg_rtx (DImode);
1742 temp2 = gen_reg_rtx (DImode);
1743 temp3 = gen_reg_rtx (DImode);
1746 emit_insn (gen_seth44 (temp1, op1));
1747 emit_insn (gen_setm44 (temp2, temp1, op1));
1748 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1749 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1750 emit_insn (gen_setl44 (op0, temp3, op1));
1754 /* The range spanned by all instructions in the object is less
1755 than 2^31 bytes (2GB) and the distance from any instruction
1756 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1757 than 2^31 bytes (2GB).
1759 The executable can be placed anywhere in the virtual address
1762 sethi %hh(symbol), %temp1
1763 sethi %lm(symbol), %temp2
1764 or %temp1, %hm(symbol), %temp3
1765 sllx %temp3, 32, %temp4
1766 or %temp4, %temp2, %temp5
1767 or %temp5, %lo(symbol), %reg */
1770 /* It is possible that one of the registers we got for operands[2]
1771 might coincide with that of operands[0] (which is why we made
1772 it TImode). Pick the other one to use as our scratch. */
1773 if (rtx_equal_p (temp, op0))
1776 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1781 temp2 = temp; /* op0 is _not_ allowed, see above. */
1788 temp1 = gen_reg_rtx (DImode);
1789 temp2 = gen_reg_rtx (DImode);
1790 temp3 = gen_reg_rtx (DImode);
1791 temp4 = gen_reg_rtx (DImode);
1792 temp5 = gen_reg_rtx (DImode);
1795 emit_insn (gen_sethh (temp1, op1));
1796 emit_insn (gen_setlm (temp2, op1));
1797 emit_insn (gen_sethm (temp3, temp1, op1));
1798 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1799 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1800 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1801 gen_rtx_PLUS (DImode, temp4, temp2)));
1802 emit_insn (gen_setlo (op0, temp5, op1));
1806 /* Old old old backwards compatibility kruft here.
1807 Essentially it is MEDLOW with a fixed 64-bit
1808 virtual base added to all data segment addresses.
1809 Text-segment stuff is computed like MEDANY, we can't
1810 reuse the code above because the relocation knobs
1813 Data segment: sethi %hi(symbol), %temp1
1814 add %temp1, EMBMEDANY_BASE_REG, %temp2
1815 or %temp2, %lo(symbol), %reg */
1816 if (data_segment_operand (op1, GET_MODE (op1)))
1820 temp1 = temp; /* op0 is allowed. */
1825 temp1 = gen_reg_rtx (DImode);
1826 temp2 = gen_reg_rtx (DImode);
1829 emit_insn (gen_embmedany_sethi (temp1, op1));
1830 emit_insn (gen_embmedany_brsum (temp2, temp1));
1831 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1834 /* Text segment: sethi %uhi(symbol), %temp1
1835 sethi %hi(symbol), %temp2
1836 or %temp1, %ulo(symbol), %temp3
1837 sllx %temp3, 32, %temp4
1838 or %temp4, %temp2, %temp5
1839 or %temp5, %lo(symbol), %reg */
1844 /* It is possible that one of the registers we got for operands[2]
1845 might coincide with that of operands[0] (which is why we made
1846 it TImode). Pick the other one to use as our scratch. */
1847 if (rtx_equal_p (temp, op0))
1850 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1855 temp2 = temp; /* op0 is _not_ allowed, see above. */
1862 temp1 = gen_reg_rtx (DImode);
1863 temp2 = gen_reg_rtx (DImode);
1864 temp3 = gen_reg_rtx (DImode);
1865 temp4 = gen_reg_rtx (DImode);
1866 temp5 = gen_reg_rtx (DImode);
1869 emit_insn (gen_embmedany_textuhi (temp1, op1));
1870 emit_insn (gen_embmedany_texthi (temp2, op1));
1871 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1872 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1873 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1874 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1875 gen_rtx_PLUS (DImode, temp4, temp2)));
1876 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1885 /* These avoid problems when cross compiling. If we do not
1886 go through all this hair then the optimizer will see
1887 invalid REG_EQUAL notes or in some cases none at all. */
1888 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1889 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1890 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1891 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1893 #if HOST_BITS_PER_WIDE_INT == 64
1894 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1895 #define GEN_INT64(__x) GEN_INT (__x)
1897 #define GEN_HIGHINT64(__x) \
1898 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1899 #define GEN_INT64(__x) \
1900 immed_double_const ((__x) & 0xffffffff, \
1901 ((__x) & 0x80000000 ? -1 : 0), DImode)
1904 /* The optimizer is not to assume anything about exactly
1905 which bits are set for a HIGH, they are unspecified.
1906 Unfortunately this leads to many missed optimizations
1907 during CSE. We mask out the non-HIGH bits, and matches
1908 a plain movdi, to alleviate this problem. */
1910 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1912 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1916 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1918 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1922 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1924 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1928 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1930 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1933 /* Worker routines for 64-bit constant formation on arch64.
1934 One of the key things to be doing in these emissions is
1935 to create as many temp REGs as possible. This makes it
1936 possible for half-built constants to be used later when
1937 such values are similar to something required later on.
1938 Without doing this, the optimizer cannot see such
1941 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1942 unsigned HOST_WIDE_INT, int);
1945 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1946 unsigned HOST_WIDE_INT low_bits, int is_neg)
1948 unsigned HOST_WIDE_INT high_bits;
1951 high_bits = (~low_bits) & 0xffffffff;
1953 high_bits = low_bits;
1955 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1958 emit_insn (gen_rtx_SET (VOIDmode, op0,
1959 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1963 /* If we are XOR'ing with -1, then we should emit a one's complement
1964 instead. This way the combiner will notice logical operations
1965 such as ANDN later on and substitute. */
1966 if ((low_bits & 0x3ff) == 0x3ff)
1968 emit_insn (gen_rtx_SET (VOIDmode, op0,
1969 gen_rtx_NOT (DImode, temp)));
1973 emit_insn (gen_rtx_SET (VOIDmode, op0,
1974 gen_safe_XOR64 (temp,
1975 (-(HOST_WIDE_INT)0x400
1976 | (low_bits & 0x3ff)))));
1981 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1982 unsigned HOST_WIDE_INT, int);
1985 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1986 unsigned HOST_WIDE_INT high_bits,
1987 unsigned HOST_WIDE_INT low_immediate,
1992 if ((high_bits & 0xfffffc00) != 0)
1994 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1995 if ((high_bits & ~0xfffffc00) != 0)
1996 emit_insn (gen_rtx_SET (VOIDmode, op0,
1997 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2003 emit_insn (gen_safe_SET64 (temp, high_bits));
2007 /* Now shift it up into place. */
2008 emit_insn (gen_rtx_SET (VOIDmode, op0,
2009 gen_rtx_ASHIFT (DImode, temp2,
2010 GEN_INT (shift_count))));
2012 /* If there is a low immediate part piece, finish up by
2013 putting that in as well. */
2014 if (low_immediate != 0)
2015 emit_insn (gen_rtx_SET (VOIDmode, op0,
2016 gen_safe_OR64 (op0, low_immediate)));
2019 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
2020 unsigned HOST_WIDE_INT);
2022 /* Full 64-bit constant decomposition. Even though this is the
2023 'worst' case, we still optimize a few things away. */
2025 sparc_emit_set_const64_longway (rtx op0, rtx temp,
2026 unsigned HOST_WIDE_INT high_bits,
2027 unsigned HOST_WIDE_INT low_bits)
2031 if (reload_in_progress || reload_completed)
2034 sub_temp = gen_reg_rtx (DImode);
2036 if ((high_bits & 0xfffffc00) != 0)
2038 sparc_emit_set_safe_HIGH64 (temp, high_bits);
2039 if ((high_bits & ~0xfffffc00) != 0)
2040 emit_insn (gen_rtx_SET (VOIDmode,
2042 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2048 emit_insn (gen_safe_SET64 (temp, high_bits));
2052 if (!reload_in_progress && !reload_completed)
2054 rtx temp2 = gen_reg_rtx (DImode);
2055 rtx temp3 = gen_reg_rtx (DImode);
2056 rtx temp4 = gen_reg_rtx (DImode);
2058 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2059 gen_rtx_ASHIFT (DImode, sub_temp,
2062 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2063 if ((low_bits & ~0xfffffc00) != 0)
2065 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2066 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2067 emit_insn (gen_rtx_SET (VOIDmode, op0,
2068 gen_rtx_PLUS (DImode, temp4, temp3)));
2072 emit_insn (gen_rtx_SET (VOIDmode, op0,
2073 gen_rtx_PLUS (DImode, temp4, temp2)));
2078 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2079 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2080 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2083 /* We are in the middle of reload, so this is really
2084 painful. However we do still make an attempt to
2085 avoid emitting truly stupid code. */
2086 if (low1 != const0_rtx)
2088 emit_insn (gen_rtx_SET (VOIDmode, op0,
2089 gen_rtx_ASHIFT (DImode, sub_temp,
2090 GEN_INT (to_shift))));
2091 emit_insn (gen_rtx_SET (VOIDmode, op0,
2092 gen_rtx_IOR (DImode, op0, low1)));
2100 if (low2 != const0_rtx)
2102 emit_insn (gen_rtx_SET (VOIDmode, op0,
2103 gen_rtx_ASHIFT (DImode, sub_temp,
2104 GEN_INT (to_shift))));
2105 emit_insn (gen_rtx_SET (VOIDmode, op0,
2106 gen_rtx_IOR (DImode, op0, low2)));
2114 emit_insn (gen_rtx_SET (VOIDmode, op0,
2115 gen_rtx_ASHIFT (DImode, sub_temp,
2116 GEN_INT (to_shift))));
2117 if (low3 != const0_rtx)
2118 emit_insn (gen_rtx_SET (VOIDmode, op0,
2119 gen_rtx_IOR (DImode, op0, low3)));
2124 /* Analyze a 64-bit constant for certain properties. */
2125 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2126 unsigned HOST_WIDE_INT,
2127 int *, int *, int *);
2130 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2131 unsigned HOST_WIDE_INT low_bits,
2132 int *hbsp, int *lbsp, int *abbasp)
2134 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2137 lowest_bit_set = highest_bit_set = -1;
2141 if ((lowest_bit_set == -1)
2142 && ((low_bits >> i) & 1))
2144 if ((highest_bit_set == -1)
2145 && ((high_bits >> (32 - i - 1)) & 1))
2146 highest_bit_set = (64 - i - 1);
2149 && ((highest_bit_set == -1)
2150 || (lowest_bit_set == -1)));
2156 if ((lowest_bit_set == -1)
2157 && ((high_bits >> i) & 1))
2158 lowest_bit_set = i + 32;
2159 if ((highest_bit_set == -1)
2160 && ((low_bits >> (32 - i - 1)) & 1))
2161 highest_bit_set = 32 - i - 1;
2164 && ((highest_bit_set == -1)
2165 || (lowest_bit_set == -1)));
2167 /* If there are no bits set this should have gone out
2168 as one instruction! */
2169 if (lowest_bit_set == -1
2170 || highest_bit_set == -1)
2172 all_bits_between_are_set = 1;
2173 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2177 if ((low_bits & (1 << i)) != 0)
2182 if ((high_bits & (1 << (i - 32))) != 0)
2185 all_bits_between_are_set = 0;
2188 *hbsp = highest_bit_set;
2189 *lbsp = lowest_bit_set;
2190 *abbasp = all_bits_between_are_set;
2193 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2196 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2197 unsigned HOST_WIDE_INT low_bits)
2199 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2202 || high_bits == 0xffffffff)
2205 analyze_64bit_constant (high_bits, low_bits,
2206 &highest_bit_set, &lowest_bit_set,
2207 &all_bits_between_are_set);
2209 if ((highest_bit_set == 63
2210 || lowest_bit_set == 0)
2211 && all_bits_between_are_set != 0)
2214 if ((highest_bit_set - lowest_bit_set) < 21)
2220 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2221 unsigned HOST_WIDE_INT,
2224 static unsigned HOST_WIDE_INT
2225 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2226 unsigned HOST_WIDE_INT low_bits,
2227 int lowest_bit_set, int shift)
2229 HOST_WIDE_INT hi, lo;
2231 if (lowest_bit_set < 32)
2233 lo = (low_bits >> lowest_bit_set) << shift;
2234 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2239 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2246 /* Here we are sure to be arch64 and this is an integer constant
2247 being loaded into a register. Emit the most efficient
2248 insn sequence possible. Detection of all the 1-insn cases
2249 has been done already. */
2251 sparc_emit_set_const64 (rtx op0, rtx op1)
2253 unsigned HOST_WIDE_INT high_bits, low_bits;
2254 int lowest_bit_set, highest_bit_set;
2255 int all_bits_between_are_set;
2258 /* Sanity check that we know what we are working with. */
2259 if (! TARGET_ARCH64)
2262 if (GET_CODE (op0) != SUBREG)
2264 if (GET_CODE (op0) != REG
2265 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2266 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2270 if (reload_in_progress || reload_completed)
2273 if (GET_CODE (op1) != CONST_DOUBLE
2274 && GET_CODE (op1) != CONST_INT)
2276 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2281 temp = gen_reg_rtx (DImode);
2283 if (GET_CODE (op1) == CONST_DOUBLE)
2285 #if HOST_BITS_PER_WIDE_INT == 64
2286 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2287 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2289 high_bits = CONST_DOUBLE_HIGH (op1);
2290 low_bits = CONST_DOUBLE_LOW (op1);
2295 #if HOST_BITS_PER_WIDE_INT == 64
2296 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2297 low_bits = (INTVAL (op1) & 0xffffffff);
2299 high_bits = ((INTVAL (op1) < 0) ?
2302 low_bits = INTVAL (op1);
2306 /* low_bits bits 0 --> 31
2307 high_bits bits 32 --> 63 */
2309 analyze_64bit_constant (high_bits, low_bits,
2310 &highest_bit_set, &lowest_bit_set,
2311 &all_bits_between_are_set);
2313 /* First try for a 2-insn sequence. */
2315 /* These situations are preferred because the optimizer can
2316 * do more things with them:
2318 * sllx %reg, shift, %reg
2320 * srlx %reg, shift, %reg
2321 * 3) mov some_small_const, %reg
2322 * sllx %reg, shift, %reg
2324 if (((highest_bit_set == 63
2325 || lowest_bit_set == 0)
2326 && all_bits_between_are_set != 0)
2327 || ((highest_bit_set - lowest_bit_set) < 12))
2329 HOST_WIDE_INT the_const = -1;
2330 int shift = lowest_bit_set;
2332 if ((highest_bit_set != 63
2333 && lowest_bit_set != 0)
2334 || all_bits_between_are_set == 0)
2337 create_simple_focus_bits (high_bits, low_bits,
2340 else if (lowest_bit_set == 0)
2341 shift = -(63 - highest_bit_set);
2343 if (! SPARC_SIMM13_P (the_const))
2346 emit_insn (gen_safe_SET64 (temp, the_const));
2348 emit_insn (gen_rtx_SET (VOIDmode,
2350 gen_rtx_ASHIFT (DImode,
2354 emit_insn (gen_rtx_SET (VOIDmode,
2356 gen_rtx_LSHIFTRT (DImode,
2358 GEN_INT (-shift))));
2364 /* Now a range of 22 or less bits set somewhere.
2365 * 1) sethi %hi(focus_bits), %reg
2366 * sllx %reg, shift, %reg
2367 * 2) sethi %hi(focus_bits), %reg
2368 * srlx %reg, shift, %reg
2370 if ((highest_bit_set - lowest_bit_set) < 21)
2372 unsigned HOST_WIDE_INT focus_bits =
2373 create_simple_focus_bits (high_bits, low_bits,
2374 lowest_bit_set, 10);
2376 if (! SPARC_SETHI_P (focus_bits))
2379 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2381 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2382 if (lowest_bit_set < 10)
2383 emit_insn (gen_rtx_SET (VOIDmode,
2385 gen_rtx_LSHIFTRT (DImode, temp,
2386 GEN_INT (10 - lowest_bit_set))));
2387 else if (lowest_bit_set > 10)
2388 emit_insn (gen_rtx_SET (VOIDmode,
2390 gen_rtx_ASHIFT (DImode, temp,
2391 GEN_INT (lowest_bit_set - 10))));
2397 /* 1) sethi %hi(low_bits), %reg
2398 * or %reg, %lo(low_bits), %reg
2399 * 2) sethi %hi(~low_bits), %reg
2400 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2403 || high_bits == 0xffffffff)
2405 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2406 (high_bits == 0xffffffff));
2410 /* Now, try 3-insn sequences. */
2412 /* 1) sethi %hi(high_bits), %reg
2413 * or %reg, %lo(high_bits), %reg
2414 * sllx %reg, 32, %reg
2418 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2422 /* We may be able to do something quick
2423 when the constant is negated, so try that. */
2424 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2425 (~low_bits) & 0xfffffc00))
2427 /* NOTE: The trailing bits get XOR'd so we need the
2428 non-negated bits, not the negated ones. */
2429 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2431 if ((((~high_bits) & 0xffffffff) == 0
2432 && ((~low_bits) & 0x80000000) == 0)
2433 || (((~high_bits) & 0xffffffff) == 0xffffffff
2434 && ((~low_bits) & 0x80000000) != 0))
2436 int fast_int = (~low_bits & 0xffffffff);
2438 if ((SPARC_SETHI_P (fast_int)
2439 && (~high_bits & 0xffffffff) == 0)
2440 || SPARC_SIMM13_P (fast_int))
2441 emit_insn (gen_safe_SET64 (temp, fast_int));
2443 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2448 #if HOST_BITS_PER_WIDE_INT == 64
2449 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2450 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2452 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2453 (~high_bits) & 0xffffffff,
2456 sparc_emit_set_const64 (temp, negated_const);
2459 /* If we are XOR'ing with -1, then we should emit a one's complement
2460 instead. This way the combiner will notice logical operations
2461 such as ANDN later on and substitute. */
2462 if (trailing_bits == 0x3ff)
2464 emit_insn (gen_rtx_SET (VOIDmode, op0,
2465 gen_rtx_NOT (DImode, temp)));
2469 emit_insn (gen_rtx_SET (VOIDmode,
2471 gen_safe_XOR64 (temp,
2472 (-0x400 | trailing_bits))));
2477 /* 1) sethi %hi(xxx), %reg
2478 * or %reg, %lo(xxx), %reg
2479 * sllx %reg, yyy, %reg
2481 * ??? This is just a generalized version of the low_bits==0
2482 * thing above, FIXME...
2484 if ((highest_bit_set - lowest_bit_set) < 32)
2486 unsigned HOST_WIDE_INT focus_bits =
2487 create_simple_focus_bits (high_bits, low_bits,
2490 /* We can't get here in this state. */
2491 if (highest_bit_set < 32
2492 || lowest_bit_set >= 32)
2495 /* So what we know is that the set bits straddle the
2496 middle of the 64-bit word. */
2497 sparc_emit_set_const64_quick2 (op0, temp,
2503 /* 1) sethi %hi(high_bits), %reg
2504 * or %reg, %lo(high_bits), %reg
2505 * sllx %reg, 32, %reg
2506 * or %reg, low_bits, %reg
2508 if (SPARC_SIMM13_P(low_bits)
2509 && ((int)low_bits > 0))
2511 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2515 /* The easiest way when all else fails, is full decomposition. */
2517 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2518 high_bits, low_bits, ~high_bits, ~low_bits);
2520 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2523 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2524 return the mode to be used for the comparison. For floating-point,
2525 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2526 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2527 processing is needed. */
2530 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2532 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2558 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2559 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2561 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2562 return CCX_NOOVmode;
2568 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2575 /* X and Y are two things to compare using CODE. Emit the compare insn and
2576 return the rtx for the cc reg in the proper mode. */
2579 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2581 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2584 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2585 fcc regs (cse can't tell they're really call clobbered regs and will
2586 remove a duplicate comparison even if there is an intervening function
2587 call - it will then try to reload the cc reg via an int reg which is why
2588 we need the movcc patterns). It is possible to provide the movcc
2589 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2590 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2591 to tell cse that CCFPE mode registers (even pseudos) are call
2594 /* ??? This is an experiment. Rather than making changes to cse which may
2595 or may not be easy/clean, we do our own cse. This is possible because
2596 we will generate hard registers. Cse knows they're call clobbered (it
2597 doesn't know the same thing about pseudos). If we guess wrong, no big
2598 deal, but if we win, great! */
2600 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2601 #if 1 /* experiment */
2604 /* We cycle through the registers to ensure they're all exercised. */
2605 static int next_fcc_reg = 0;
2606 /* Previous x,y for each fcc reg. */
2607 static rtx prev_args[4][2];
2609 /* Scan prev_args for x,y. */
2610 for (reg = 0; reg < 4; reg++)
2611 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2616 prev_args[reg][0] = x;
2617 prev_args[reg][1] = y;
2618 next_fcc_reg = (next_fcc_reg + 1) & 3;
2620 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2623 cc_reg = gen_reg_rtx (mode);
2624 #endif /* ! experiment */
2625 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2626 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2628 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2630 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2631 gen_rtx_COMPARE (mode, x, y)));
2636 /* This function is used for v9 only.
2637 CODE is the code for an Scc's comparison.
2638 OPERANDS[0] is the target of the Scc insn.
2639 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2640 been generated yet).
2642 This function is needed to turn
2645 (gt (reg:CCX 100 %icc)
2649 (gt:DI (reg:CCX 100 %icc)
2652 IE: The instruction recognizer needs to see the mode of the comparison to
2653 find the right instruction. We could use "gt:DI" right in the
2654 define_expand, but leaving it out allows us to handle DI, SI, etc.
2656 We refer to the global sparc compare operands sparc_compare_op0 and
2657 sparc_compare_op1. */
2660 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2665 && (GET_MODE (sparc_compare_op0) == DImode
2666 || GET_MODE (operands[0]) == DImode))
2669 op0 = sparc_compare_op0;
2670 op1 = sparc_compare_op1;
2672 /* Try to use the movrCC insns. */
2674 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2675 && op1 == const0_rtx
2676 && v9_regcmp_p (compare_code))
2678 /* Special case for op0 != 0. This can be done with one instruction if
2679 operands[0] == sparc_compare_op0. */
2681 if (compare_code == NE
2682 && GET_MODE (operands[0]) == DImode
2683 && rtx_equal_p (op0, operands[0]))
2685 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2686 gen_rtx_IF_THEN_ELSE (DImode,
2687 gen_rtx_fmt_ee (compare_code, DImode,
2694 if (reg_overlap_mentioned_p (operands[0], op0))
2696 /* Handle the case where operands[0] == sparc_compare_op0.
2697 We "early clobber" the result. */
2698 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2699 emit_move_insn (op0, sparc_compare_op0);
2702 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2703 if (GET_MODE (op0) != DImode)
2705 temp = gen_reg_rtx (DImode);
2706 convert_move (temp, op0, 0);
2710 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2711 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2712 gen_rtx_fmt_ee (compare_code, DImode,
2720 operands[1] = gen_compare_reg (compare_code, op0, op1);
2722 switch (GET_MODE (operands[1]))
2732 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2733 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2734 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2735 gen_rtx_fmt_ee (compare_code,
2736 GET_MODE (operands[1]),
2737 operands[1], const0_rtx),
2738 const1_rtx, operands[0])));
2743 /* Emit a conditional jump insn for the v9 architecture using comparison code
2744 CODE and jump target LABEL.
2745 This function exists to take advantage of the v9 brxx insns. */
2748 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2750 emit_jump_insn (gen_rtx_SET (VOIDmode,
2752 gen_rtx_IF_THEN_ELSE (VOIDmode,
2753 gen_rtx_fmt_ee (code, GET_MODE (op0),
2755 gen_rtx_LABEL_REF (VOIDmode, label),
2759 /* Generate a DFmode part of a hard TFmode register.
2760 REG is the TFmode hard register, LOW is 1 for the
2761 low 64bit of the register and 0 otherwise.
2764 gen_df_reg (rtx reg, int low)
2766 int regno = REGNO (reg);
2768 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2769 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2770 return gen_rtx_REG (DFmode, regno);
2773 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2774 Unlike normal calls, TFmode operands are passed by reference. It is
2775 assumed that no more than 3 operands are required. */
2778 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2780 rtx ret_slot = NULL, arg[3], func_sym;
2783 /* We only expect to be called for conversions, unary, and binary ops. */
2784 if (nargs < 2 || nargs > 3)
2787 for (i = 0; i < nargs; ++i)
2789 rtx this_arg = operands[i];
2792 /* TFmode arguments and return values are passed by reference. */
2793 if (GET_MODE (this_arg) == TFmode)
2795 int force_stack_temp;
2797 force_stack_temp = 0;
2798 if (TARGET_BUGGY_QP_LIB && i == 0)
2799 force_stack_temp = 1;
2801 if (GET_CODE (this_arg) == MEM
2802 && ! force_stack_temp)
2803 this_arg = XEXP (this_arg, 0);
2804 else if (CONSTANT_P (this_arg)
2805 && ! force_stack_temp)
2807 this_slot = force_const_mem (TFmode, this_arg);
2808 this_arg = XEXP (this_slot, 0);
2812 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2814 /* Operand 0 is the return value. We'll copy it out later. */
2816 emit_move_insn (this_slot, this_arg);
2818 ret_slot = this_slot;
2820 this_arg = XEXP (this_slot, 0);
2827 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2829 if (GET_MODE (operands[0]) == TFmode)
2832 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2833 arg[0], GET_MODE (arg[0]),
2834 arg[1], GET_MODE (arg[1]));
2836 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2837 arg[0], GET_MODE (arg[0]),
2838 arg[1], GET_MODE (arg[1]),
2839 arg[2], GET_MODE (arg[2]));
2842 emit_move_insn (operands[0], ret_slot);
2851 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2852 GET_MODE (operands[0]), 1,
2853 arg[1], GET_MODE (arg[1]));
2855 if (ret != operands[0])
2856 emit_move_insn (operands[0], ret);
2860 /* Expand soft-float TFmode calls to sparc abi routines. */
2863 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2885 emit_soft_tfmode_libcall (func, 3, operands);
2889 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2902 emit_soft_tfmode_libcall (func, 2, operands);
2906 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2913 switch (GET_MODE (operands[1]))
2926 case FLOAT_TRUNCATE:
2927 switch (GET_MODE (operands[0]))
2941 switch (GET_MODE (operands[1]))
2954 case UNSIGNED_FLOAT:
2955 switch (GET_MODE (operands[1]))
2969 switch (GET_MODE (operands[0]))
2983 switch (GET_MODE (operands[0]))
3000 emit_soft_tfmode_libcall (func, 2, operands);
3003 /* Expand a hard-float tfmode operation. All arguments must be in
3007 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
3011 if (GET_RTX_CLASS (code) == RTX_UNARY)
3013 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3014 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
3018 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
3019 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
3020 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
3021 operands[1], operands[2]);
3024 if (register_operand (operands[0], VOIDmode))
3027 dest = gen_reg_rtx (GET_MODE (operands[0]));
3029 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
3031 if (dest != operands[0])
3032 emit_move_insn (operands[0], dest);
3036 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3038 if (TARGET_HARD_QUAD)
3039 emit_hard_tfmode_operation (code, operands);
3041 emit_soft_tfmode_binop (code, operands);
3045 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3047 if (TARGET_HARD_QUAD)
3048 emit_hard_tfmode_operation (code, operands);
3050 emit_soft_tfmode_unop (code, operands);
3054 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3056 if (TARGET_HARD_QUAD)
3057 emit_hard_tfmode_operation (code, operands);
3059 emit_soft_tfmode_cvt (code, operands);
3062 /* Return nonzero if a branch/jump/call instruction will be emitting
3063 nop into its delay slot. */
3066 empty_delay_slot (rtx insn)
3070 /* If no previous instruction (should not happen), return true. */
3071 if (PREV_INSN (insn) == NULL)
3074 seq = NEXT_INSN (PREV_INSN (insn));
3075 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3081 /* Return nonzero if TRIAL can go into the call delay slot. */
3084 tls_call_delay (rtx trial)
3089 call __tls_get_addr, %tgd_call (foo)
3090 add %l7, %o0, %o0, %tgd_add (foo)
3091 while Sun as/ld does not. */
3092 if (TARGET_GNU_TLS || !TARGET_TLS)
3095 pat = PATTERN (trial);
3096 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3099 unspec = XEXP (SET_DEST (pat), 1);
3100 if (GET_CODE (unspec) != UNSPEC
3101 || (XINT (unspec, 1) != UNSPEC_TLSGD
3102 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3108 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3109 instruction. RETURN_P is true if the v9 variant 'return' is to be
3110 considered in the test too.
3112 TRIAL must be a SET whose destination is a REG appropriate for the
3113 'restore' instruction or, if RETURN_P is true, for the 'return'
3117 eligible_for_restore_insn (rtx trial, bool return_p)
3119 rtx pat = PATTERN (trial);
3120 rtx src = SET_SRC (pat);
3122 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3123 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3124 && arith_operand (src, GET_MODE (src)))
3127 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3129 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3132 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3133 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3134 && arith_double_operand (src, GET_MODE (src)))
3135 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3137 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3138 else if (! TARGET_FPU && register_operand (src, SFmode))
3141 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3142 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3145 /* If we have the 'return' instruction, anything that does not use
3146 local or output registers and can go into a delay slot wins. */
3147 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3148 && (get_attr_in_uncond_branch_delay (trial)
3149 == IN_UNCOND_BRANCH_DELAY_TRUE))
3152 /* The 'restore src1,src2,dest' pattern for SImode. */
3153 else if (GET_CODE (src) == PLUS
3154 && register_operand (XEXP (src, 0), SImode)
3155 && arith_operand (XEXP (src, 1), SImode))
3158 /* The 'restore src1,src2,dest' pattern for DImode. */
3159 else if (GET_CODE (src) == PLUS
3160 && register_operand (XEXP (src, 0), DImode)
3161 && arith_double_operand (XEXP (src, 1), DImode))
3164 /* The 'restore src1,%lo(src2),dest' pattern. */
3165 else if (GET_CODE (src) == LO_SUM
3166 && ! TARGET_CM_MEDMID
3167 && ((register_operand (XEXP (src, 0), SImode)
3168 && immediate_operand (XEXP (src, 1), SImode))
3170 && register_operand (XEXP (src, 0), DImode)
3171 && immediate_operand (XEXP (src, 1), DImode))))
3174 /* The 'restore src,src,dest' pattern. */
3175 else if (GET_CODE (src) == ASHIFT
3176 && (register_operand (XEXP (src, 0), SImode)
3177 || register_operand (XEXP (src, 0), DImode))
3178 && XEXP (src, 1) == const1_rtx)
3184 /* Return nonzero if TRIAL can go into the function return's
3188 eligible_for_return_delay (rtx trial)
3192 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3195 if (get_attr_length (trial) != 1)
3198 /* If there are any call-saved registers, we should scan TRIAL if it
3199 does not reference them. For now just make it easy. */
3203 /* If the function uses __builtin_eh_return, the eh_return machinery
3204 occupies the delay slot. */
3205 if (current_function_calls_eh_return)
3208 /* In the case of a true leaf function, anything can go into the slot. */
3209 if (sparc_leaf_function_p)
3210 return get_attr_in_uncond_branch_delay (trial)
3211 == IN_UNCOND_BRANCH_DELAY_TRUE;
3213 pat = PATTERN (trial);
3215 /* Otherwise, only operations which can be done in tandem with
3216 a `restore' or `return' insn can go into the delay slot. */
3217 if (GET_CODE (SET_DEST (pat)) != REG
3218 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3221 /* If this instruction sets up floating point register and we have a return
3222 instruction, it can probably go in. But restore will not work
3224 if (REGNO (SET_DEST (pat)) >= 32)
3226 && ! epilogue_renumber (&pat, 1)
3227 && (get_attr_in_uncond_branch_delay (trial)
3228 == IN_UNCOND_BRANCH_DELAY_TRUE));
3230 return eligible_for_restore_insn (trial, true);
3233 /* Return nonzero if TRIAL can go into the sibling call's
3237 eligible_for_sibcall_delay (rtx trial)
3241 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3244 if (get_attr_length (trial) != 1)
3247 pat = PATTERN (trial);
3249 if (sparc_leaf_function_p)
3251 /* If the tail call is done using the call instruction,
3252 we have to restore %o7 in the delay slot. */
3253 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3256 /* %g1 is used to build the function address */
3257 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3263 /* Otherwise, only operations which can be done in tandem with
3264 a `restore' insn can go into the delay slot. */
3265 if (GET_CODE (SET_DEST (pat)) != REG
3266 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3267 || REGNO (SET_DEST (pat)) >= 32)
3270 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3272 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3275 return eligible_for_restore_insn (trial, false);
3279 short_branch (int uid1, int uid2)
3281 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3283 /* Leave a few words of "slop". */
3284 if (delta >= -1023 && delta <= 1022)
3290 /* Return nonzero if REG is not used after INSN.
3291 We assume REG is a reload reg, and therefore does
3292 not live past labels or calls or jumps. */
3294 reg_unused_after (rtx reg, rtx insn)
3296 enum rtx_code code, prev_code = UNKNOWN;
3298 while ((insn = NEXT_INSN (insn)))
3300 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3303 code = GET_CODE (insn);
3304 if (GET_CODE (insn) == CODE_LABEL)
3309 rtx set = single_set (insn);
3310 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3313 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3315 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3323 /* Determine if it's legal to put X into the constant pool. This
3324 is not possible if X contains the address of a symbol that is
3325 not constant (TLS) or not known at final link time (PIC). */
3328 sparc_cannot_force_const_mem (rtx x)
3330 switch (GET_CODE (x))
3335 /* Accept all non-symbolic constants. */
3339 /* Labels are OK iff we are non-PIC. */
3340 return flag_pic != 0;
3343 /* 'Naked' TLS symbol references are never OK,
3344 non-TLS symbols are OK iff we are non-PIC. */
3345 if (SYMBOL_REF_TLS_MODEL (x))
3348 return flag_pic != 0;
3351 return sparc_cannot_force_const_mem (XEXP (x, 0));
3354 return sparc_cannot_force_const_mem (XEXP (x, 0))
3355 || sparc_cannot_force_const_mem (XEXP (x, 1));
3364 static GTY(()) char pic_helper_symbol_name[256];
3365 static GTY(()) rtx pic_helper_symbol;
3366 static GTY(()) bool pic_helper_emitted_p = false;
3367 static GTY(()) rtx global_offset_table;
3369 /* Ensure that we are not using patterns that are not OK with PIC. */
3377 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3378 || (GET_CODE (recog_data.operand[i]) == CONST
3379 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3380 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3381 == global_offset_table)
3382 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3391 /* Return true if X is an address which needs a temporary register when
3392 reloaded while generating PIC code. */
3395 pic_address_needs_scratch (rtx x)
3397 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3398 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3399 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3400 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3401 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3407 /* Determine if a given RTX is a valid constant. We already know this
3408 satisfies CONSTANT_P. */
3411 legitimate_constant_p (rtx x)
3415 switch (GET_CODE (x))
3418 /* TLS symbols are not constant. */
3419 if (SYMBOL_REF_TLS_MODEL (x))
3424 inner = XEXP (x, 0);
3426 /* Offsets of TLS symbols are never valid.
3427 Discourage CSE from creating them. */
3428 if (GET_CODE (inner) == PLUS
3429 && tls_symbolic_operand (XEXP (inner, 0)))
3434 if (GET_MODE (x) == VOIDmode)
3437 /* Floating point constants are generally not ok.
3438 The only exception is 0.0 in VIS. */
3440 && (GET_MODE (x) == SFmode
3441 || GET_MODE (x) == DFmode
3442 || GET_MODE (x) == TFmode)
3443 && fp_zero_operand (x, GET_MODE (x)))
3455 /* Determine if a given RTX is a valid constant address. */
3458 constant_address_p (rtx x)
3460 switch (GET_CODE (x))
3468 if (flag_pic && pic_address_needs_scratch (x))
3470 return legitimate_constant_p (x);
3473 return !flag_pic && legitimate_constant_p (x);
3480 /* Nonzero if the constant value X is a legitimate general operand
3481 when generating PIC code. It is given that flag_pic is on and
3482 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3485 legitimate_pic_operand_p (rtx x)
3487 if (pic_address_needs_scratch (x))
3489 if (tls_symbolic_operand (x)
3490 || (GET_CODE (x) == CONST
3491 && GET_CODE (XEXP (x, 0)) == PLUS
3492 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3497 /* Return nonzero if ADDR is a valid memory address.
3498 STRICT specifies whether strict register checking applies. */
3501 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3503 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3505 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3507 else if (GET_CODE (addr) == PLUS)
3509 rs1 = XEXP (addr, 0);
3510 rs2 = XEXP (addr, 1);
3512 /* Canonicalize. REG comes first, if there are no regs,
3513 LO_SUM comes first. */
3515 && GET_CODE (rs1) != SUBREG
3517 || GET_CODE (rs2) == SUBREG
3518 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3520 rs1 = XEXP (addr, 1);
3521 rs2 = XEXP (addr, 0);
3525 && rs1 == pic_offset_table_rtx
3527 && GET_CODE (rs2) != SUBREG
3528 && GET_CODE (rs2) != LO_SUM
3529 && GET_CODE (rs2) != MEM
3530 && !tls_symbolic_operand (rs2)
3531 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3532 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3534 || GET_CODE (rs1) == SUBREG)
3535 && RTX_OK_FOR_OFFSET_P (rs2)))
3540 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3541 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3543 /* We prohibit REG + REG for TFmode when there are no quad move insns
3544 and we consequently need to split. We do this because REG+REG
3545 is not an offsettable address. If we get the situation in reload
3546 where source and destination of a movtf pattern are both MEMs with
3547 REG+REG address, then only one of them gets converted to an
3548 offsettable address. */
3550 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3553 /* We prohibit REG + REG on ARCH32 if not optimizing for
3554 DFmode/DImode because then mem_min_alignment is likely to be zero
3555 after reload and the forced split would lack a matching splitter
3557 if (TARGET_ARCH32 && !optimize
3558 && (mode == DFmode || mode == DImode))
3561 else if (USE_AS_OFFSETABLE_LO10
3562 && GET_CODE (rs1) == LO_SUM
3564 && ! TARGET_CM_MEDMID
3565 && RTX_OK_FOR_OLO10_P (rs2))
3568 imm1 = XEXP (rs1, 1);
3569 rs1 = XEXP (rs1, 0);
3570 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3574 else if (GET_CODE (addr) == LO_SUM)
3576 rs1 = XEXP (addr, 0);
3577 imm1 = XEXP (addr, 1);
3579 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3582 /* We can't allow TFmode in 32-bit mode, because an offset greater
3583 than the alignment (8) may cause the LO_SUM to overflow. */
3584 if (mode == TFmode && !TARGET_64BIT)
3587 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3592 if (GET_CODE (rs1) == SUBREG)
3593 rs1 = SUBREG_REG (rs1);
3599 if (GET_CODE (rs2) == SUBREG)
3600 rs2 = SUBREG_REG (rs2);
3607 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3608 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3613 if ((REGNO (rs1) >= 32
3614 && REGNO (rs1) != FRAME_POINTER_REGNUM
3615 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3617 && (REGNO (rs2) >= 32
3618 && REGNO (rs2) != FRAME_POINTER_REGNUM
3619 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3625 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3627 static GTY(()) rtx sparc_tls_symbol;
3629 sparc_tls_get_addr (void)
3631 if (!sparc_tls_symbol)
3632 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3634 return sparc_tls_symbol;
3638 sparc_tls_got (void)
3643 current_function_uses_pic_offset_table = 1;
3644 return pic_offset_table_rtx;
3647 if (!global_offset_table)
3648 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3649 temp = gen_reg_rtx (Pmode);
3650 emit_move_insn (temp, global_offset_table);
3655 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3656 this (thread-local) address. */
3659 legitimize_tls_address (rtx addr)
3661 rtx temp1, temp2, temp3, ret, o0, got, insn;
3666 if (GET_CODE (addr) == SYMBOL_REF)
3667 switch (SYMBOL_REF_TLS_MODEL (addr))
3669 case TLS_MODEL_GLOBAL_DYNAMIC:
3671 temp1 = gen_reg_rtx (SImode);
3672 temp2 = gen_reg_rtx (SImode);
3673 ret = gen_reg_rtx (Pmode);
3674 o0 = gen_rtx_REG (Pmode, 8);
3675 got = sparc_tls_got ();
3676 emit_insn (gen_tgd_hi22 (temp1, addr));
3677 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3680 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3681 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3686 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3687 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3690 CALL_INSN_FUNCTION_USAGE (insn)
3691 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3692 CALL_INSN_FUNCTION_USAGE (insn));
3693 insn = get_insns ();
3695 emit_libcall_block (insn, ret, o0, addr);
3698 case TLS_MODEL_LOCAL_DYNAMIC:
3700 temp1 = gen_reg_rtx (SImode);
3701 temp2 = gen_reg_rtx (SImode);
3702 temp3 = gen_reg_rtx (Pmode);
3703 ret = gen_reg_rtx (Pmode);
3704 o0 = gen_rtx_REG (Pmode, 8);
3705 got = sparc_tls_got ();
3706 emit_insn (gen_tldm_hi22 (temp1));
3707 emit_insn (gen_tldm_lo10 (temp2, temp1));
3710 emit_insn (gen_tldm_add32 (o0, got, temp2));
3711 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3716 emit_insn (gen_tldm_add64 (o0, got, temp2));
3717 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3720 CALL_INSN_FUNCTION_USAGE (insn)
3721 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3722 CALL_INSN_FUNCTION_USAGE (insn));
3723 insn = get_insns ();
3725 emit_libcall_block (insn, temp3, o0,
3726 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3727 UNSPEC_TLSLD_BASE));
3728 temp1 = gen_reg_rtx (SImode);
3729 temp2 = gen_reg_rtx (SImode);
3730 emit_insn (gen_tldo_hix22 (temp1, addr));
3731 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3733 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3735 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3738 case TLS_MODEL_INITIAL_EXEC:
3739 temp1 = gen_reg_rtx (SImode);
3740 temp2 = gen_reg_rtx (SImode);
3741 temp3 = gen_reg_rtx (Pmode);
3742 got = sparc_tls_got ();
3743 emit_insn (gen_tie_hi22 (temp1, addr));
3744 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3746 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3748 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3751 ret = gen_reg_rtx (Pmode);
3753 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3756 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3760 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3763 case TLS_MODEL_LOCAL_EXEC:
3764 temp1 = gen_reg_rtx (Pmode);
3765 temp2 = gen_reg_rtx (Pmode);
3768 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3769 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3773 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3774 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3776 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3784 abort (); /* for now ... */
3790 /* Legitimize PIC addresses. If the address is already position-independent,
3791 we return ORIG. Newly generated position-independent addresses go into a
3792 reg. This is REG if nonzero, otherwise we allocate register(s) as
3796 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3799 if (GET_CODE (orig) == SYMBOL_REF)
3801 rtx pic_ref, address;
3806 if (reload_in_progress || reload_completed)
3809 reg = gen_reg_rtx (Pmode);
3814 /* If not during reload, allocate another temp reg here for loading
3815 in the address, so that these instructions can be optimized
3817 rtx temp_reg = ((reload_in_progress || reload_completed)
3818 ? reg : gen_reg_rtx (Pmode));
3820 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3821 won't get confused into thinking that these two instructions
3822 are loading in the true address of the symbol. If in the
3823 future a PIC rtx exists, that should be used instead. */
3824 if (Pmode == SImode)
3826 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3827 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3831 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3832 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3839 pic_ref = gen_const_mem (Pmode,
3840 gen_rtx_PLUS (Pmode,
3841 pic_offset_table_rtx, address));
3842 current_function_uses_pic_offset_table = 1;
3843 insn = emit_move_insn (reg, pic_ref);
3844 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3846 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3850 else if (GET_CODE (orig) == CONST)
3854 if (GET_CODE (XEXP (orig, 0)) == PLUS
3855 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3860 if (reload_in_progress || reload_completed)
3863 reg = gen_reg_rtx (Pmode);
3866 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3868 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3869 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3870 base == reg ? 0 : reg);
3875 if (GET_CODE (offset) == CONST_INT)
3877 if (SMALL_INT (offset))
3878 return plus_constant (base, INTVAL (offset));
3879 else if (! reload_in_progress && ! reload_completed)
3880 offset = force_reg (Pmode, offset);
3882 /* If we reach here, then something is seriously wrong. */
3885 return gen_rtx_PLUS (Pmode, base, offset);
3887 else if (GET_CODE (orig) == LABEL_REF)
3888 /* ??? Why do we do this? */
3889 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3890 the register is live instead, in case it is eliminated. */
3891 current_function_uses_pic_offset_table = 1;
3896 /* Try machine-dependent ways of modifying an illegitimate address X
3897 to be legitimate. If we find one, return the new, valid address.
3899 OLDX is the address as it was before break_out_memory_refs was called.
3900 In some cases it is useful to look at this to decide what needs to be done.
3902 MODE is the mode of the operand pointed to by X. */
3905 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3909 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3910 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3911 force_operand (XEXP (x, 0), NULL_RTX));
3912 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3913 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3914 force_operand (XEXP (x, 1), NULL_RTX));
3915 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3916 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3918 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3919 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3920 force_operand (XEXP (x, 1), NULL_RTX));
3922 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3925 if (tls_symbolic_operand (x))
3926 x = legitimize_tls_address (x);
3928 x = legitimize_pic_address (x, mode, 0);
3929 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3930 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3931 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3932 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3933 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3934 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3935 else if (GET_CODE (x) == SYMBOL_REF
3936 || GET_CODE (x) == CONST
3937 || GET_CODE (x) == LABEL_REF)
3938 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3942 /* Emit the special PIC helper function. */
3945 emit_pic_helper (void)
3947 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3952 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3954 ASM_OUTPUT_ALIGN (asm_out_file, align);
3955 ASM_OUTPUT_LABEL (asm_out_file, pic_helper_symbol_name);
3956 if (flag_delayed_branch)
3957 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
3958 pic_name, pic_name);
3960 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
3961 pic_name, pic_name);
3963 pic_helper_emitted_p = true;
3966 /* Emit code to load the PIC register. */
3969 load_pic_register (bool delay_pic_helper)
3971 int orig_flag_pic = flag_pic;
3973 /* If we haven't initialized the special PIC symbols, do so now. */
3974 if (!pic_helper_symbol_name[0])
3976 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name, "LADDPC", 0);
3977 pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, pic_helper_symbol_name);
3978 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3981 /* If we haven't emitted the special PIC helper function, do so now unless
3982 we are requested to delay it. */
3983 if (!delay_pic_helper && !pic_helper_emitted_p)
3988 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
3989 pic_helper_symbol));
3991 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
3992 pic_helper_symbol));
3993 flag_pic = orig_flag_pic;
3995 /* Need to emit this whether or not we obey regdecls,
3996 since setjmp/longjmp can cause life info to screw up.
3997 ??? In the case where we don't obey regdecls, this is not sufficient
3998 since we may not fall out the bottom. */
3999 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
4002 /* Return 1 if RTX is a MEM which is known to be aligned to at
4003 least a DESIRED byte boundary. */
4006 mem_min_alignment (rtx mem, int desired)
4008 rtx addr, base, offset;
4010 /* If it's not a MEM we can't accept it. */
4011 if (GET_CODE (mem) != MEM)
4015 if (MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4018 /* ??? The rest of the function predates MEM_ALIGN so
4019 there is probably a bit of redundancy. */
4020 addr = XEXP (mem, 0);
4021 base = offset = NULL_RTX;
4022 if (GET_CODE (addr) == PLUS)
4024 if (GET_CODE (XEXP (addr, 0)) == REG)
4026 base = XEXP (addr, 0);
4028 /* What we are saying here is that if the base
4029 REG is aligned properly, the compiler will make
4030 sure any REG based index upon it will be so
4032 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4033 offset = XEXP (addr, 1);
4035 offset = const0_rtx;
4038 else if (GET_CODE (addr) == REG)
4041 offset = const0_rtx;
4044 if (base != NULL_RTX)
4046 int regno = REGNO (base);
4048 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4050 /* Check if the compiler has recorded some information
4051 about the alignment of the base REG. If reload has
4052 completed, we already matched with proper alignments.
4053 If not running global_alloc, reload might give us
4054 unaligned pointer to local stack though. */
4056 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4057 || (optimize && reload_completed))
4058 && (INTVAL (offset) & (desired - 1)) == 0)
4063 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4067 else if (! TARGET_UNALIGNED_DOUBLES
4068 || CONSTANT_P (addr)
4069 || GET_CODE (addr) == LO_SUM)
4071 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4072 is true, in which case we can only assume that an access is aligned if
4073 it is to a constant address, or the address involves a LO_SUM. */
4077 /* An obviously unaligned address. */
4082 /* Vectors to keep interesting information about registers where it can easily
4083 be got. We used to use the actual mode value as the bit number, but there
4084 are more than 32 modes now. Instead we use two tables: one indexed by
4085 hard register number, and one indexed by mode. */
4087 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4088 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4089 mapped into one sparc_mode_class mode. */
4091 enum sparc_mode_class {
4092 S_MODE, D_MODE, T_MODE, O_MODE,
4093 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4097 /* Modes for single-word and smaller quantities. */
4098 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4100 /* Modes for double-word and smaller quantities. */
4101 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4103 /* Modes for quad-word and smaller quantities. */
4104 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4106 /* Modes for 8-word and smaller quantities. */
4107 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4109 /* Modes for single-float quantities. We must allow any single word or
4110 smaller quantity. This is because the fix/float conversion instructions
4111 take integer inputs/outputs from the float registers. */
4112 #define SF_MODES (S_MODES)
4114 /* Modes for double-float and smaller quantities. */
4115 #define DF_MODES (S_MODES | D_MODES)
4117 /* Modes for double-float only quantities. */
4118 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4120 /* Modes for quad-float only quantities. */
4121 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4123 /* Modes for quad-float and smaller quantities. */
4124 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4126 /* Modes for quad-float and double-float quantities. */
4127 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4129 /* Modes for quad-float pair only quantities. */
4130 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4132 /* Modes for quad-float pairs and smaller quantities. */
4133 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4135 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4137 /* Modes for condition codes. */
4138 #define CC_MODES (1 << (int) CC_MODE)
4139 #define CCFP_MODES (1 << (int) CCFP_MODE)
4141 /* Value is 1 if register/mode pair is acceptable on sparc.
4142 The funny mixture of D and T modes is because integer operations
4143 do not specially operate on tetra quantities, so non-quad-aligned
4144 registers can hold quadword quantities (except %o4 and %i4 because
4145 they cross fixed registers). */
4147 /* This points to either the 32 bit or the 64 bit version. */
4148 const int *hard_regno_mode_classes;
4150 static const int hard_32bit_mode_classes[] = {
4151 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4152 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4153 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4154 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4156 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4157 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4158 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4159 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4161 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4162 and none can hold SFmode/SImode values. */
4163 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4164 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4165 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4166 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4169 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4175 static const int hard_64bit_mode_classes[] = {
4176 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4177 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4178 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4179 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4181 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4182 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4183 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4184 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4186 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4187 and none can hold SFmode/SImode values. */
4188 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4189 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4190 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4191 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4194 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4200 int sparc_mode_class [NUM_MACHINE_MODES];
4202 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4205 sparc_init_modes (void)
4209 for (i = 0; i < NUM_MACHINE_MODES; i++)
4211 switch (GET_MODE_CLASS (i))
4214 case MODE_PARTIAL_INT:
4215 case MODE_COMPLEX_INT:
4216 if (GET_MODE_SIZE (i) <= 4)
4217 sparc_mode_class[i] = 1 << (int) S_MODE;
4218 else if (GET_MODE_SIZE (i) == 8)
4219 sparc_mode_class[i] = 1 << (int) D_MODE;
4220 else if (GET_MODE_SIZE (i) == 16)
4221 sparc_mode_class[i] = 1 << (int) T_MODE;
4222 else if (GET_MODE_SIZE (i) == 32)
4223 sparc_mode_class[i] = 1 << (int) O_MODE;
4225 sparc_mode_class[i] = 0;
4227 case MODE_VECTOR_INT:
4228 if (GET_MODE_SIZE (i) <= 4)
4229 sparc_mode_class[i] = 1 << (int)SF_MODE;
4230 else if (GET_MODE_SIZE (i) == 8)
4231 sparc_mode_class[i] = 1 << (int)DF_MODE;
4234 case MODE_COMPLEX_FLOAT:
4235 if (GET_MODE_SIZE (i) <= 4)
4236 sparc_mode_class[i] = 1 << (int) SF_MODE;
4237 else if (GET_MODE_SIZE (i) == 8)
4238 sparc_mode_class[i] = 1 << (int) DF_MODE;
4239 else if (GET_MODE_SIZE (i) == 16)
4240 sparc_mode_class[i] = 1 << (int) TF_MODE;
4241 else if (GET_MODE_SIZE (i) == 32)
4242 sparc_mode_class[i] = 1 << (int) OF_MODE;
4244 sparc_mode_class[i] = 0;
4247 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4248 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4250 sparc_mode_class[i] = 1 << (int) CC_MODE;
4253 sparc_mode_class[i] = 0;
4259 hard_regno_mode_classes = hard_64bit_mode_classes;
4261 hard_regno_mode_classes = hard_32bit_mode_classes;
4263 /* Initialize the array used by REGNO_REG_CLASS. */
4264 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4266 if (i < 16 && TARGET_V8PLUS)
4267 sparc_regno_reg_class[i] = I64_REGS;
4268 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4269 sparc_regno_reg_class[i] = GENERAL_REGS;
4271 sparc_regno_reg_class[i] = FP_REGS;
4273 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4275 sparc_regno_reg_class[i] = FPCC_REGS;
4277 sparc_regno_reg_class[i] = NO_REGS;
4281 /* Compute the frame size required by the function. This function is called
4282 during the reload pass and also by sparc_expand_prologue. */
4285 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4287 int outgoing_args_size = (current_function_outgoing_args_size
4288 + REG_PARM_STACK_SPACE (current_function_decl));
4289 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4294 for (i = 0; i < 8; i++)
4295 if (regs_ever_live[i] && ! call_used_regs[i])
4300 for (i = 0; i < 8; i += 2)
4301 if ((regs_ever_live[i] && ! call_used_regs[i])
4302 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4306 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4307 if ((regs_ever_live[i] && ! call_used_regs[i])
4308 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4311 /* Set up values for use in prologue and epilogue. */
4312 num_gfregs = n_regs;
4317 && current_function_outgoing_args_size == 0)
4318 actual_fsize = apparent_fsize = 0;
4321 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4322 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4323 apparent_fsize += n_regs * 4;
4324 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4327 /* Make sure nothing can clobber our register windows.
4328 If a SAVE must be done, or there is a stack-local variable,
4329 the register window area must be allocated.
4330 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4331 if (! leaf_function_p || size > 0)
4332 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4334 return SPARC_STACK_ALIGN (actual_fsize);
4337 /* Output any necessary .register pseudo-ops. */
4340 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4342 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4348 /* Check if %g[2367] were used without
4349 .register being printed for them already. */
4350 for (i = 2; i < 8; i++)
4352 if (regs_ever_live [i]
4353 && ! sparc_hard_reg_printed [i])
4355 sparc_hard_reg_printed [i] = 1;
4356 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4363 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4364 as needed. LOW should be double-word aligned for 32-bit registers.
4365 Return the new OFFSET. */
4368 #define SORR_RESTORE 1
4371 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4376 if (TARGET_ARCH64 && high <= 32)
4378 for (i = low; i < high; i++)
4380 if (regs_ever_live[i] && ! call_used_regs[i])
4382 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4383 set_mem_alias_set (mem, sparc_sr_alias_set);
4384 if (action == SORR_SAVE)
4386 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4387 RTX_FRAME_RELATED_P (insn) = 1;
4389 else /* action == SORR_RESTORE */
4390 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4397 for (i = low; i < high; i += 2)
4399 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4400 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4401 enum machine_mode mode;
4406 mode = i < 32 ? DImode : DFmode;
4411 mode = i < 32 ? SImode : SFmode;
4416 mode = i < 32 ? SImode : SFmode;
4423 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4424 set_mem_alias_set (mem, sparc_sr_alias_set);
4425 if (action == SORR_SAVE)
4427 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4428 RTX_FRAME_RELATED_P (insn) = 1;
4430 else /* action == SORR_RESTORE */
4431 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4433 /* Always preserve double-word alignment. */
4434 offset = (offset + 7) & -8;
4441 /* Emit code to save call-saved registers. */
4444 emit_save_regs (void)
4446 HOST_WIDE_INT offset;
4449 offset = frame_base_offset - apparent_fsize;
4451 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4453 /* ??? This might be optimized a little as %g1 might already have a
4454 value close enough that a single add insn will do. */
4455 /* ??? Although, all of this is probably only a temporary fix
4456 because if %g1 can hold a function result, then
4457 sparc_expand_epilogue will lose (the result will be
4459 base = gen_rtx_REG (Pmode, 1);
4460 emit_move_insn (base, GEN_INT (offset));
4461 emit_insn (gen_rtx_SET (VOIDmode,
4463 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4467 base = frame_base_reg;
4469 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4470 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4473 /* Emit code to restore call-saved registers. */
4476 emit_restore_regs (void)
4478 HOST_WIDE_INT offset;
4481 offset = frame_base_offset - apparent_fsize;
4483 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4485 base = gen_rtx_REG (Pmode, 1);
4486 emit_move_insn (base, GEN_INT (offset));
4487 emit_insn (gen_rtx_SET (VOIDmode,
4489 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4493 base = frame_base_reg;
4495 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4496 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4499 /* Generate a save_register_window insn. */
4502 gen_save_register_window (rtx increment)
4505 return gen_save_register_windowdi (increment);
4507 return gen_save_register_windowsi (increment);
4510 /* Generate an increment for the stack pointer. */
4513 gen_stack_pointer_inc (rtx increment)
4516 return gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment);
4518 return gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment);
4521 /* Generate a decrement for the stack pointer. */
4524 gen_stack_pointer_dec (rtx decrement)
4527 return gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement);
4529 return gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement);
4532 /* Expand the function prologue. The prologue is responsible for reserving
4533 storage for the frame, saving the call-saved registers and loading the
4534 PIC register if needed. */
4537 sparc_expand_prologue (void)
4542 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4543 on the final value of the flag means deferring the prologue/epilogue
4544 expansion until just before the second scheduling pass, which is too
4545 late to emit multiple epilogues or return insns.
4547 Of course we are making the assumption that the value of the flag
4548 will not change between now and its final value. Of the three parts
4549 of the formula, only the last one can reasonably vary. Let's take a
4550 closer look, after assuming that the first two ones are set to true
4551 (otherwise the last value is effectively silenced).
4553 If only_leaf_regs_used returns false, the global predicate will also
4554 be false so the actual frame size calculated below will be positive.
4555 As a consequence, the save_register_window insn will be emitted in
4556 the instruction stream; now this insn explicitly references %fp
4557 which is not a leaf register so only_leaf_regs_used will always
4558 return false subsequently.
4560 If only_leaf_regs_used returns true, we hope that the subsequent
4561 optimization passes won't cause non-leaf registers to pop up. For
4562 example, the regrename pass has special provisions to not rename to
4563 non-leaf registers in a leaf function. */
4564 sparc_leaf_function_p
4565 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
4567 /* Need to use actual_fsize, since we are also allocating
4568 space for our callee (and our own register save area). */
4570 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4572 /* Advertise that the data calculated just above are now valid. */
4573 sparc_prologue_data_valid_p = true;
4575 if (sparc_leaf_function_p)
4577 frame_base_reg = stack_pointer_rtx;
4578 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4582 frame_base_reg = hard_frame_pointer_rtx;
4583 frame_base_offset = SPARC_STACK_BIAS;
4586 if (actual_fsize == 0)
4588 else if (sparc_leaf_function_p)
4590 if (actual_fsize <= 4096)
4591 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize)));
4592 else if (actual_fsize <= 8192)
4594 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4595 /* %sp is still the CFA register. */
4596 RTX_FRAME_RELATED_P (insn) = 1;
4598 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
4602 rtx reg = gen_rtx_REG (Pmode, 1);
4603 emit_move_insn (reg, GEN_INT (-actual_fsize));
4604 insn = emit_insn (gen_stack_pointer_inc (reg));
4606 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4607 PATTERN (gen_stack_pointer_inc (GEN_INT (-actual_fsize))),
4611 RTX_FRAME_RELATED_P (insn) = 1;
4615 if (actual_fsize <= 4096)
4616 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4617 else if (actual_fsize <= 8192)
4619 insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
4620 /* %sp is not the CFA register anymore. */
4621 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
4625 rtx reg = gen_rtx_REG (Pmode, 1);
4626 emit_move_insn (reg, GEN_INT (-actual_fsize));
4627 insn = emit_insn (gen_save_register_window (reg));
4630 RTX_FRAME_RELATED_P (insn) = 1;
4631 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++)
4632 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1;
4635 /* Call-saved registers are saved just above the outgoing argument area. */
4639 /* Load the PIC register if needed. */
4640 if (flag_pic && current_function_uses_pic_offset_table)
4641 load_pic_register (false);
4644 /* This function generates the assembly code for function entry, which boils
4645 down to emitting the necessary .register directives.
4647 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4648 an 8-byte block of memory. If any fpu reg is used in the function, we
4649 allocate such a block here, at the bottom of the frame, just in case it's
4650 needed." Could this explain the -8 in emit_restore_regs? */
4653 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4655 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4656 if (sparc_leaf_function_p != current_function_uses_only_leaf_regs)
4659 sparc_output_scratch_registers (file);
4662 /* Expand the function epilogue, either normal or part of a sibcall.
4663 We emit all the instructions except the return or the call. */
4666 sparc_expand_epilogue (void)
4669 emit_restore_regs ();
4671 if (actual_fsize == 0)
4673 else if (sparc_leaf_function_p)
4675 if (actual_fsize <= 4096)
4676 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize)));
4677 else if (actual_fsize <= 8192)
4679 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4680 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize)));
4684 rtx reg = gen_rtx_REG (Pmode, 1);
4685 emit_move_insn (reg, GEN_INT (-actual_fsize));
4686 emit_insn (gen_stack_pointer_dec (reg));
4691 /* Return true if it is appropriate to emit `return' instructions in the
4692 body of a function. */
4695 sparc_can_use_return_insn_p (void)
4697 return sparc_prologue_data_valid_p
4698 && (actual_fsize == 0 || !sparc_leaf_function_p);
4701 /* This function generates the assembly code for function exit. */
4704 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4706 /* If code does not drop into the epilogue, we have to still output
4707 a dummy nop for the sake of sane backtraces. Otherwise, if the
4708 last two instructions of a function were "call foo; dslot;" this
4709 can make the return PC of foo (i.e. address of call instruction
4710 plus 8) point to the first instruction in the next function. */
4712 rtx insn, last_real_insn;
4714 insn = get_last_insn ();
4716 last_real_insn = prev_real_insn (insn);
4718 && GET_CODE (last_real_insn) == INSN
4719 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4720 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4722 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4723 fputs("\tnop\n", file);
4725 sparc_output_deferred_case_vectors ();
4728 /* Output a 'restore' instruction. */
4731 output_restore (rtx pat)
4737 fputs ("\t restore\n", asm_out_file);
4741 if (GET_CODE (pat) != SET)
4744 operands[0] = SET_DEST (pat);
4745 pat = SET_SRC (pat);
4747 switch (GET_CODE (pat))
4750 operands[1] = XEXP (pat, 0);
4751 operands[2] = XEXP (pat, 1);
4752 output_asm_insn (" restore %r1, %2, %Y0", operands);
4755 operands[1] = XEXP (pat, 0);
4756 operands[2] = XEXP (pat, 1);
4757 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4760 operands[1] = XEXP (pat, 0);
4761 if (XEXP (pat, 1) != const1_rtx)
4763 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4767 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4772 /* Output a return. */
4775 output_return (rtx insn)
4777 if (sparc_leaf_function_p)
4779 /* This is a leaf function so we don't have to bother restoring the
4780 register window, which frees us from dealing with the convoluted
4781 semantics of restore/return. We simply output the jump to the
4782 return address and the insn in the delay slot (if any). */
4784 if (current_function_calls_eh_return)
4787 return "jmp\t%%o7+%)%#";
4791 /* This is a regular function so we have to restore the register window.
4792 We may have a pending insn for the delay slot, which will be either
4793 combined with the 'restore' instruction or put in the delay slot of
4794 the 'return' instruction. */
4796 if (current_function_calls_eh_return)
4798 /* If the function uses __builtin_eh_return, the eh_return
4799 machinery occupies the delay slot. */
4803 if (! flag_delayed_branch)
4804 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4807 fputs ("\treturn\t%i7+8\n", asm_out_file);
4809 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4811 if (flag_delayed_branch)
4812 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4814 fputs ("\t nop\n", asm_out_file);
4816 else if (final_sequence)
4820 delay = NEXT_INSN (insn);
4824 pat = PATTERN (delay);
4826 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4828 epilogue_renumber (&pat, 0);
4829 return "return\t%%i7+%)%#";
4833 output_asm_insn ("jmp\t%%i7+%)", NULL);
4834 output_restore (pat);
4835 PATTERN (delay) = gen_blockage ();
4836 INSN_CODE (delay) = -1;
4841 /* The delay slot is empty. */
4843 return "return\t%%i7+%)\n\t nop";
4844 else if (flag_delayed_branch)
4845 return "jmp\t%%i7+%)\n\t restore";
4847 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4854 /* Output a sibling call. */
4857 output_sibcall (rtx insn, rtx call_operand)
4861 if (! flag_delayed_branch)
4864 operands[0] = call_operand;
4866 if (sparc_leaf_function_p)
4868 /* This is a leaf function so we don't have to bother restoring the
4869 register window. We simply output the jump to the function and
4870 the insn in the delay slot (if any). */
4872 if (LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)
4876 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4879 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4880 it into branch if possible. */
4881 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4886 /* This is a regular function so we have to restore the register window.
4887 We may have a pending insn for the delay slot, which will be combined
4888 with the 'restore' instruction. */
4890 output_asm_insn ("call\t%a0, 0", operands);
4894 rtx delay = NEXT_INSN (insn);
4898 output_restore (PATTERN (delay));
4900 PATTERN (delay) = gen_blockage ();
4901 INSN_CODE (delay) = -1;
4904 output_restore (NULL_RTX);
4910 /* Functions for handling argument passing.
4912 For 32-bit, the first 6 args are normally in registers and the rest are
4913 pushed. Any arg that starts within the first 6 words is at least
4914 partially passed in a register unless its data type forbids.
4916 For 64-bit, the argument registers are laid out as an array of 16 elements
4917 and arguments are added sequentially. The first 6 int args and up to the
4918 first 16 fp args (depending on size) are passed in regs.
4920 Slot Stack Integral Float Float in structure Double Long Double
4921 ---- ----- -------- ----- ------------------ ------ -----------
4922 15 [SP+248] %f31 %f30,%f31 %d30
4923 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4924 13 [SP+232] %f27 %f26,%f27 %d26
4925 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4926 11 [SP+216] %f23 %f22,%f23 %d22
4927 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4928 9 [SP+200] %f19 %f18,%f19 %d18
4929 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4930 7 [SP+184] %f15 %f14,%f15 %d14
4931 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4932 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4933 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4934 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4935 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4936 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4937 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4939 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4941 Integral arguments are always passed as 64-bit quantities appropriately
4944 Passing of floating point values is handled as follows.
4945 If a prototype is in scope:
4946 If the value is in a named argument (i.e. not a stdarg function or a
4947 value not part of the `...') then the value is passed in the appropriate
4949 If the value is part of the `...' and is passed in one of the first 6
4950 slots then the value is passed in the appropriate int reg.
4951 If the value is part of the `...' and is not passed in one of the first 6
4952 slots then the value is passed in memory.
4953 If a prototype is not in scope:
4954 If the value is one of the first 6 arguments the value is passed in the
4955 appropriate integer reg and the appropriate fp reg.
4956 If the value is not one of the first 6 arguments the value is passed in
4957 the appropriate fp reg and in memory.
4960 Summary of the calling conventions implemented by GCC on SPARC:
4963 size argument return value
4965 small integer <4 int. reg. int. reg.
4966 word 4 int. reg. int. reg.
4967 double word 8 int. reg. int. reg.
4969 _Complex small integer <8 int. reg. int. reg.
4970 _Complex word 8 int. reg. int. reg.
4971 _Complex double word 16 memory int. reg.
4973 vector integer <=8 int. reg. FP reg.
4974 vector integer >8 memory memory
4976 float 4 int. reg. FP reg.
4977 double 8 int. reg. FP reg.
4978 long double 16 memory memory
4980 _Complex float 8 memory FP reg.
4981 _Complex double 16 memory FP reg.
4982 _Complex long double 32 memory FP reg.
4984 vector float any memory memory
4986 aggregate any memory memory
4991 size argument return value
4993 small integer <8 int. reg. int. reg.
4994 word 8 int. reg. int. reg.
4995 double word 16 int. reg. int. reg.
4997 _Complex small integer <16 int. reg. int. reg.
4998 _Complex word 16 int. reg. int. reg.
4999 _Complex double word 32 memory int. reg.
5001 vector integer <=16 FP reg. FP reg.
5002 vector integer 16<s<=32 memory FP reg.
5003 vector integer >32 memory memory
5005 float 4 FP reg. FP reg.
5006 double 8 FP reg. FP reg.
5007 long double 16 FP reg. FP reg.
5009 _Complex float 8 FP reg. FP reg.
5010 _Complex double 16 FP reg. FP reg.
5011 _Complex long double 32 memory FP reg.
5013 vector float <=16 FP reg. FP reg.
5014 vector float 16<s<=32 memory FP reg.
5015 vector float >32 memory memory
5017 aggregate <=16 reg. reg.
5018 aggregate 16<s<=32 memory reg.
5019 aggregate >32 memory memory
5023 Note #1: complex floating-point types follow the extended SPARC ABIs as
5024 implemented by the Sun compiler.
5026 Note #2: integral vector types follow the scalar floating-point types
5027 conventions to match what is implemented by the Sun VIS SDK.
5029 Note #3: floating-point vector types follow the aggregate types
5033 /* Maximum number of int regs for args. */
5034 #define SPARC_INT_ARG_MAX 6
5035 /* Maximum number of fp regs for args. */
5036 #define SPARC_FP_ARG_MAX 16
5038 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5040 /* Handle the INIT_CUMULATIVE_ARGS macro.
5041 Initialize a variable CUM of type CUMULATIVE_ARGS
5042 for a call to a function whose data type is FNTYPE.
5043 For a library call, FNTYPE is 0. */
5046 init_cumulative_args (struct sparc_args *cum, tree fntype,
5047 rtx libname ATTRIBUTE_UNUSED,
5048 tree fndecl ATTRIBUTE_UNUSED)
5051 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
5052 cum->libcall_p = fntype == 0;
5055 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
5056 When a prototype says `char' or `short', really pass an `int'. */
5059 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
5061 return TARGET_ARCH32 ? true : false;
5064 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5067 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
5069 return TARGET_ARCH64 ? true : false;
5072 /* Scan the record type TYPE and return the following predicates:
5073 - INTREGS_P: the record contains at least one field or sub-field
5074 that is eligible for promotion in integer registers.
5075 - FP_REGS_P: the record contains at least one field or sub-field
5076 that is eligible for promotion in floating-point registers.
5077 - PACKED_P: the record contains at least one field that is packed.
5079 Sub-fields are not taken into account for the PACKED_P predicate. */
5082 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5086 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5088 if (TREE_CODE (field) == FIELD_DECL)
5090 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5091 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5092 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5093 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5099 if (packed_p && DECL_PACKED (field))
5105 /* Compute the slot number to pass an argument in.
5106 Return the slot number or -1 if passing on the stack.
5108 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5109 the preceding args and about the function being called.
5110 MODE is the argument's machine mode.
5111 TYPE is the data type of the argument (as a tree).
5112 This is null for libcalls where that information may
5114 NAMED is nonzero if this argument is a named parameter
5115 (otherwise it is an extra parameter matching an ellipsis).
5116 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5117 *PREGNO records the register number to use if scalar type.
5118 *PPADDING records the amount of padding needed in words. */
5121 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5122 tree type, int named, int incoming_p,
5123 int *pregno, int *ppadding)
5125 int regbase = (incoming_p
5126 ? SPARC_INCOMING_INT_ARG_FIRST
5127 : SPARC_OUTGOING_INT_ARG_FIRST);
5128 int slotno = cum->words;
5129 enum mode_class mclass;
5134 if (type && TREE_ADDRESSABLE (type))
5140 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5143 /* For SPARC64, objects requiring 16-byte alignment get it. */
5145 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5146 && (slotno & 1) != 0)
5147 slotno++, *ppadding = 1;
5149 mclass = GET_MODE_CLASS (mode);
5150 if (type && TREE_CODE (type) == VECTOR_TYPE)
5152 /* Vector types deserve special treatment because they are
5153 polymorphic wrt their mode, depending upon whether VIS
5154 instructions are enabled. */
5155 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5157 /* The SPARC port defines no floating-point vector modes. */
5158 if (mode != BLKmode)
5163 /* Integral vector types should either have a vector
5164 mode or an integral mode, because we are guaranteed
5165 by pass_by_reference that their size is not greater
5166 than 16 bytes and TImode is 16-byte wide. */
5167 if (mode == BLKmode)
5170 /* Vector integers are handled like floats according to
5172 mclass = MODE_FLOAT;
5179 case MODE_COMPLEX_FLOAT:
5180 if (TARGET_ARCH64 && TARGET_FPU && named)
5182 if (slotno >= SPARC_FP_ARG_MAX)
5184 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5185 /* Arguments filling only one single FP register are
5186 right-justified in the outer double FP register. */
5187 if (GET_MODE_SIZE (mode) <= 4)
5194 case MODE_COMPLEX_INT:
5195 if (slotno >= SPARC_INT_ARG_MAX)
5197 regno = regbase + slotno;
5201 if (mode == VOIDmode)
5202 /* MODE is VOIDmode when generating the actual call. */
5205 if (mode != BLKmode)
5208 /* For SPARC64, objects requiring 16-byte alignment get it. */
5211 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5212 && (slotno & 1) != 0)
5213 slotno++, *ppadding = 1;
5215 if (TARGET_ARCH32 || !type || (TREE_CODE (type) == UNION_TYPE))
5217 if (slotno >= SPARC_INT_ARG_MAX)
5219 regno = regbase + slotno;
5221 else /* TARGET_ARCH64 && type */
5223 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5225 /* First see what kinds of registers we would need. */
5226 if (TREE_CODE (type) == VECTOR_TYPE)
5229 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5231 /* The ABI obviously doesn't specify how packed structures
5232 are passed. These are defined to be passed in int regs
5233 if possible, otherwise memory. */
5234 if (packed_p || !named)
5235 fpregs_p = 0, intregs_p = 1;
5237 /* If all arg slots are filled, then must pass on stack. */
5238 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5241 /* If there are only int args and all int arg slots are filled,
5242 then must pass on stack. */
5243 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5246 /* Note that even if all int arg slots are filled, fp members may
5247 still be passed in regs if such regs are available.
5248 *PREGNO isn't set because there may be more than one, it's up
5249 to the caller to compute them. */
5262 /* Handle recursive register counting for structure field layout. */
5264 struct function_arg_record_value_parms
5266 rtx ret; /* return expression being built. */
5267 int slotno; /* slot number of the argument. */
5268 int named; /* whether the argument is named. */
5269 int regbase; /* regno of the base register. */
5270 int stack; /* 1 if part of the argument is on the stack. */
5271 int intoffset; /* offset of the first pending integer field. */
5272 unsigned int nregs; /* number of words passed in registers. */
5275 static void function_arg_record_value_3
5276 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5277 static void function_arg_record_value_2
5278 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5279 static void function_arg_record_value_1
5280 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5281 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5282 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5284 /* A subroutine of function_arg_record_value. Traverse the structure
5285 recursively and determine how many registers will be required. */
5288 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5289 struct function_arg_record_value_parms *parms,
5294 /* We need to compute how many registers are needed so we can
5295 allocate the PARALLEL but before we can do that we need to know
5296 whether there are any packed fields. The ABI obviously doesn't
5297 specify how structures are passed in this case, so they are
5298 defined to be passed in int regs if possible, otherwise memory,
5299 regardless of whether there are fp values present. */
5302 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5304 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5311 /* Compute how many registers we need. */
5312 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5314 if (TREE_CODE (field) == FIELD_DECL)
5316 HOST_WIDE_INT bitpos = startbitpos;
5318 if (DECL_SIZE (field) != 0)
5320 if (integer_zerop (DECL_SIZE (field)))
5323 if (host_integerp (bit_position (field), 1))
5324 bitpos += int_bit_position (field);
5327 /* ??? FIXME: else assume zero offset. */
5329 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5330 function_arg_record_value_1 (TREE_TYPE (field),
5334 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5335 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5340 if (parms->intoffset != -1)
5342 unsigned int startbit, endbit;
5343 int intslots, this_slotno;
5345 startbit = parms->intoffset & -BITS_PER_WORD;
5346 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5348 intslots = (endbit - startbit) / BITS_PER_WORD;
5349 this_slotno = parms->slotno + parms->intoffset
5352 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5354 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5355 /* We need to pass this field on the stack. */
5359 parms->nregs += intslots;
5360 parms->intoffset = -1;
5363 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5364 If it wasn't true we wouldn't be here. */
5365 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5366 && DECL_MODE (field) == BLKmode)
5367 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5368 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5375 if (parms->intoffset == -1)
5376 parms->intoffset = bitpos;
5382 /* A subroutine of function_arg_record_value. Assign the bits of the
5383 structure between parms->intoffset and bitpos to integer registers. */
5386 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5387 struct function_arg_record_value_parms *parms)
5389 enum machine_mode mode;
5391 unsigned int startbit, endbit;
5392 int this_slotno, intslots, intoffset;
5395 if (parms->intoffset == -1)
5398 intoffset = parms->intoffset;
5399 parms->intoffset = -1;
5401 startbit = intoffset & -BITS_PER_WORD;
5402 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5403 intslots = (endbit - startbit) / BITS_PER_WORD;
5404 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5406 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5410 /* If this is the trailing part of a word, only load that much into
5411 the register. Otherwise load the whole register. Note that in
5412 the latter case we may pick up unwanted bits. It's not a problem
5413 at the moment but may wish to revisit. */
5415 if (intoffset % BITS_PER_WORD != 0)
5416 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5421 intoffset /= BITS_PER_UNIT;
5424 regno = parms->regbase + this_slotno;
5425 reg = gen_rtx_REG (mode, regno);
5426 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5427 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5430 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5435 while (intslots > 0);
5438 /* A subroutine of function_arg_record_value. Traverse the structure
5439 recursively and assign bits to floating point registers. Track which
5440 bits in between need integer registers; invoke function_arg_record_value_3
5441 to make that happen. */
5444 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5445 struct function_arg_record_value_parms *parms,
5451 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5453 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5460 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5462 if (TREE_CODE (field) == FIELD_DECL)
5464 HOST_WIDE_INT bitpos = startbitpos;
5466 if (DECL_SIZE (field) != 0)
5468 if (integer_zerop (DECL_SIZE (field)))
5471 if (host_integerp (bit_position (field), 1))
5472 bitpos += int_bit_position (field);
5475 /* ??? FIXME: else assume zero offset. */
5477 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5478 function_arg_record_value_2 (TREE_TYPE (field),
5482 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5483 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5488 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5489 int regno, nregs, pos;
5490 enum machine_mode mode = DECL_MODE (field);
5493 function_arg_record_value_3 (bitpos, parms);
5495 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5498 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5499 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5501 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5503 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5509 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5510 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5512 reg = gen_rtx_REG (mode, regno);
5513 pos = bitpos / BITS_PER_UNIT;
5514 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5515 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5519 regno += GET_MODE_SIZE (mode) / 4;
5520 reg = gen_rtx_REG (mode, regno);
5521 pos += GET_MODE_SIZE (mode);
5522 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5523 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5529 if (parms->intoffset == -1)
5530 parms->intoffset = bitpos;
5536 /* Used by function_arg and function_value to implement the complex
5537 conventions of the 64-bit ABI for passing and returning structures.
5538 Return an expression valid as a return value for the two macros
5539 FUNCTION_ARG and FUNCTION_VALUE.
5541 TYPE is the data type of the argument (as a tree).
5542 This is null for libcalls where that information may
5544 MODE is the argument's machine mode.
5545 SLOTNO is the index number of the argument's slot in the parameter array.
5546 NAMED is nonzero if this argument is a named parameter
5547 (otherwise it is an extra parameter matching an ellipsis).
5548 REGBASE is the regno of the base register for the parameter array. */
5551 function_arg_record_value (tree type, enum machine_mode mode,
5552 int slotno, int named, int regbase)
5554 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5555 struct function_arg_record_value_parms parms;
5558 parms.ret = NULL_RTX;
5559 parms.slotno = slotno;
5560 parms.named = named;
5561 parms.regbase = regbase;
5564 /* Compute how many registers we need. */
5566 parms.intoffset = 0;
5567 function_arg_record_value_1 (type, 0, &parms, false);
5569 /* Take into account pending integer fields. */
5570 if (parms.intoffset != -1)
5572 unsigned int startbit, endbit;
5573 int intslots, this_slotno;
5575 startbit = parms.intoffset & -BITS_PER_WORD;
5576 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5577 intslots = (endbit - startbit) / BITS_PER_WORD;
5578 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5580 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5582 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5583 /* We need to pass this field on the stack. */
5587 parms.nregs += intslots;
5589 nregs = parms.nregs;
5591 /* Allocate the vector and handle some annoying special cases. */
5594 /* ??? Empty structure has no value? Duh? */
5597 /* Though there's nothing really to store, return a word register
5598 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5599 leads to breakage due to the fact that there are zero bytes to
5601 return gen_rtx_REG (mode, regbase);
5605 /* ??? C++ has structures with no fields, and yet a size. Give up
5606 for now and pass everything back in integer registers. */
5607 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5609 if (nregs + slotno > SPARC_INT_ARG_MAX)
5610 nregs = SPARC_INT_ARG_MAX - slotno;
5615 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5617 /* If at least one field must be passed on the stack, generate
5618 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5619 also be passed on the stack. We can't do much better because the
5620 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5621 of structures for which the fields passed exclusively in registers
5622 are not at the beginning of the structure. */
5624 XVECEXP (parms.ret, 0, 0)
5625 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5627 /* Fill in the entries. */
5629 parms.intoffset = 0;
5630 function_arg_record_value_2 (type, 0, &parms, false);
5631 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5633 if (parms.nregs != nregs)
5639 /* Used by function_arg and function_value to implement the conventions
5640 of the 64-bit ABI for passing and returning unions.
5641 Return an expression valid as a return value for the two macros
5642 FUNCTION_ARG and FUNCTION_VALUE.
5644 SIZE is the size in bytes of the union.
5645 MODE is the argument's machine mode.
5646 REGNO is the hard register the union will be passed in. */
5649 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5652 int nwords = ROUND_ADVANCE (size), i;
5655 /* See comment in previous function for empty structures. */
5657 return gen_rtx_REG (mode, regno);
5659 if (slotno == SPARC_INT_ARG_MAX - 1)
5662 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5664 for (i = 0; i < nwords; i++)
5666 /* Unions are passed left-justified. */
5667 XVECEXP (regs, 0, i)
5668 = gen_rtx_EXPR_LIST (VOIDmode,
5669 gen_rtx_REG (word_mode, regno),
5670 GEN_INT (UNITS_PER_WORD * i));
5677 /* Used by function_arg and function_value to implement the conventions
5678 for passing and returning large (BLKmode) vectors.
5679 Return an expression valid as a return value for the two macros
5680 FUNCTION_ARG and FUNCTION_VALUE.
5682 SIZE is the size in bytes of the vector.
5683 BASE_MODE is the argument's base machine mode.
5684 REGNO is the FP hard register the vector will be passed in. */
5687 function_arg_vector_value (int size, enum machine_mode base_mode, int regno)
5689 unsigned short base_mode_size = GET_MODE_SIZE (base_mode);
5690 int nregs = size / base_mode_size, i;
5693 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5695 for (i = 0; i < nregs; i++)
5697 XVECEXP (regs, 0, i)
5698 = gen_rtx_EXPR_LIST (VOIDmode,
5699 gen_rtx_REG (base_mode, regno),
5700 GEN_INT (base_mode_size * i));
5701 regno += base_mode_size / 4;
5707 /* Handle the FUNCTION_ARG macro.
5708 Determine where to put an argument to a function.
5709 Value is zero to push the argument on the stack,
5710 or a hard register in which to store the argument.
5712 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5713 the preceding args and about the function being called.
5714 MODE is the argument's machine mode.
5715 TYPE is the data type of the argument (as a tree).
5716 This is null for libcalls where that information may
5718 NAMED is nonzero if this argument is a named parameter
5719 (otherwise it is an extra parameter matching an ellipsis).
5720 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5723 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5724 tree type, int named, int incoming_p)
5726 int regbase = (incoming_p
5727 ? SPARC_INCOMING_INT_ARG_FIRST
5728 : SPARC_OUTGOING_INT_ARG_FIRST);
5729 int slotno, regno, padding;
5730 enum mode_class mclass = GET_MODE_CLASS (mode);
5733 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5741 reg = gen_rtx_REG (mode, regno);
5745 if (type && TREE_CODE (type) == RECORD_TYPE)
5747 /* Structures up to 16 bytes in size are passed in arg slots on the
5748 stack and are promoted to registers where possible. */
5750 if (int_size_in_bytes (type) > 16)
5751 abort (); /* shouldn't get here */
5753 return function_arg_record_value (type, mode, slotno, named, regbase);
5755 else if (type && TREE_CODE (type) == UNION_TYPE)
5757 HOST_WIDE_INT size = int_size_in_bytes (type);
5760 abort (); /* shouldn't get here */
5762 return function_arg_union_value (size, mode, slotno, regno);
5764 else if (type && TREE_CODE (type) == VECTOR_TYPE)
5766 /* Vector types deserve special treatment because they are
5767 polymorphic wrt their mode, depending upon whether VIS
5768 instructions are enabled. */
5769 HOST_WIDE_INT size = int_size_in_bytes (type);
5772 abort (); /* shouldn't get here */
5774 if (mode == BLKmode)
5775 return function_arg_vector_value (size,
5776 TYPE_MODE (TREE_TYPE (type)),
5777 SPARC_FP_ARG_FIRST + 2*slotno);
5779 mclass = MODE_FLOAT;
5782 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5783 but also have the slot allocated for them.
5784 If no prototype is in scope fp values in register slots get passed
5785 in two places, either fp regs and int regs or fp regs and memory. */
5786 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5787 && SPARC_FP_REG_P (regno))
5789 reg = gen_rtx_REG (mode, regno);
5790 if (cum->prototype_p || cum->libcall_p)
5792 /* "* 2" because fp reg numbers are recorded in 4 byte
5795 /* ??? This will cause the value to be passed in the fp reg and
5796 in the stack. When a prototype exists we want to pass the
5797 value in the reg but reserve space on the stack. That's an
5798 optimization, and is deferred [for a bit]. */
5799 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5800 return gen_rtx_PARALLEL (mode,
5802 gen_rtx_EXPR_LIST (VOIDmode,
5803 NULL_RTX, const0_rtx),
5804 gen_rtx_EXPR_LIST (VOIDmode,
5808 /* ??? It seems that passing back a register even when past
5809 the area declared by REG_PARM_STACK_SPACE will allocate
5810 space appropriately, and will not copy the data onto the
5811 stack, exactly as we desire.
5813 This is due to locate_and_pad_parm being called in
5814 expand_call whenever reg_parm_stack_space > 0, which
5815 while beneficial to our example here, would seem to be
5816 in error from what had been intended. Ho hum... -- r~ */
5824 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5828 /* On incoming, we don't need to know that the value
5829 is passed in %f0 and %i0, and it confuses other parts
5830 causing needless spillage even on the simplest cases. */
5834 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5835 + (regno - SPARC_FP_ARG_FIRST) / 2);
5837 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5838 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5840 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5844 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5845 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5846 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5852 /* Scalar or complex int. */
5853 reg = gen_rtx_REG (mode, regno);
5859 /* For an arg passed partly in registers and partly in memory,
5860 this is the number of bytes of registers used.
5861 For args passed entirely in registers or entirely in memory, zero.
5863 Any arg that starts in the first 6 regs but won't entirely fit in them
5864 needs partial registers on v8. On v9, structures with integer
5865 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5866 values that begin in the last fp reg [where "last fp reg" varies with the
5867 mode] will be split between that reg and memory. */
5870 sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5871 tree type, bool named)
5873 int slotno, regno, padding;
5875 /* We pass 0 for incoming_p here, it doesn't matter. */
5876 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5883 if ((slotno + (mode == BLKmode
5884 ? ROUND_ADVANCE (int_size_in_bytes (type))
5885 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5886 > SPARC_INT_ARG_MAX)
5887 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
5891 /* We are guaranteed by pass_by_reference that the size of the
5892 argument is not greater than 16 bytes, so we only need to return
5893 one word if the argument is partially passed in registers. */
5895 if (type && AGGREGATE_TYPE_P (type))
5897 int size = int_size_in_bytes (type);
5899 if (size > UNITS_PER_WORD
5900 && slotno == SPARC_INT_ARG_MAX - 1)
5901 return UNITS_PER_WORD;
5903 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5904 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5905 && ! (TARGET_FPU && named)))
5907 /* The complex types are passed as packed types. */
5908 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5909 && slotno == SPARC_INT_ARG_MAX - 1)
5910 return UNITS_PER_WORD;
5912 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5914 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5916 return UNITS_PER_WORD;
5923 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5924 Specify whether to pass the argument by reference. */
5927 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5928 enum machine_mode mode, tree type,
5929 bool named ATTRIBUTE_UNUSED)
5933 /* Original SPARC 32-bit ABI says that structures and unions,
5934 and quad-precision floats are passed by reference. For Pascal,
5935 also pass arrays by reference. All other base types are passed
5938 Extended ABI (as implemented by the Sun compiler) says that all
5939 complex floats are passed by reference. Pass complex integers
5940 in registers up to 8 bytes. More generally, enforce the 2-word
5941 cap for passing arguments in registers.
5943 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5944 integers are passed like floats of the same size, that is in
5945 registers up to 8 bytes. Pass all vector floats by reference
5946 like structure and unions. */
5947 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5949 /* Catch CDImode, TFmode, DCmode and TCmode. */
5950 || GET_MODE_SIZE (mode) > 8
5952 && TREE_CODE (type) == VECTOR_TYPE
5953 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
5957 /* Original SPARC 64-bit ABI says that structures and unions
5958 smaller than 16 bytes are passed in registers, as well as
5959 all other base types. For Pascal, pass arrays by reference.
5961 Extended ABI (as implemented by the Sun compiler) says that
5962 complex floats are passed in registers up to 16 bytes. Pass
5963 all complex integers in registers up to 16 bytes. More generally,
5964 enforce the 2-word cap for passing arguments in registers.
5966 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5967 integers are passed like floats of the same size, that is in
5968 registers (up to 16 bytes). Pass all vector floats like structure
5970 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5972 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5973 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5974 /* Catch CTImode and TCmode. */
5975 || GET_MODE_SIZE (mode) > 16);
5979 /* Handle the FUNCTION_ARG_ADVANCE macro.
5980 Update the data in CUM to advance over an argument
5981 of mode MODE and data type TYPE.
5982 TYPE is null for libcalls where that information may not be available. */
5985 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5986 tree type, int named)
5988 int slotno, regno, padding;
5990 /* We pass 0 for incoming_p here, it doesn't matter. */
5991 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5993 /* If register required leading padding, add it. */
5995 cum->words += padding;
5999 cum->words += (mode != BLKmode
6000 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6001 : ROUND_ADVANCE (int_size_in_bytes (type)));
6005 if (type && AGGREGATE_TYPE_P (type))
6007 int size = int_size_in_bytes (type);
6011 else if (size <= 16)
6013 else /* passed by reference */
6018 cum->words += (mode != BLKmode
6019 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6020 : ROUND_ADVANCE (int_size_in_bytes (type)));
6025 /* Handle the FUNCTION_ARG_PADDING macro.
6026 For the 64 bit ABI structs are always stored left shifted in their
6030 function_arg_padding (enum machine_mode mode, tree type)
6032 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6035 /* Fall back to the default. */
6036 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6039 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6040 Specify whether to return the return value in memory. */
6043 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
6046 /* Original SPARC 32-bit ABI says that structures and unions,
6047 and quad-precision floats are returned in memory. All other
6048 base types are returned in registers.
6050 Extended ABI (as implemented by the Sun compiler) says that
6051 all complex floats are returned in registers (8 FP registers
6052 at most for '_Complex long double'). Return all complex integers
6053 in registers (4 at most for '_Complex long long').
6055 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6056 integers are returned like floats of the same size, that is in
6057 registers up to 8 bytes and in memory otherwise. Return all
6058 vector floats in memory like structure and unions; note that
6059 they always have BLKmode like the latter. */
6060 return (TYPE_MODE (type) == BLKmode
6061 || TYPE_MODE (type) == TFmode
6062 || (TREE_CODE (type) == VECTOR_TYPE
6063 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6065 /* Original SPARC 64-bit ABI says that structures and unions
6066 smaller than 32 bytes are returned in registers, as well as
6067 all other base types.
6069 Extended ABI (as implemented by the Sun compiler) says that all
6070 complex floats are returned in registers (8 FP registers at most
6071 for '_Complex long double'). Return all complex integers in
6072 registers (4 at most for '_Complex TItype').
6074 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6075 integers are returned like floats of the same size, that is in
6076 registers. Return all vector floats like structure and unions;
6077 note that they always have BLKmode like the latter. */
6078 return ((TYPE_MODE (type) == BLKmode
6079 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
6082 /* Handle the TARGET_STRUCT_VALUE target hook.
6083 Return where to find the structure return value address. */
6086 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
6095 mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
6096 STRUCT_VALUE_OFFSET));
6098 mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
6099 STRUCT_VALUE_OFFSET));
6101 set_mem_alias_set (mem, struct_value_alias_set);
6106 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
6107 For v9, function return values are subject to the same rules as arguments,
6108 except that up to 32 bytes may be returned in registers. */
6111 function_value (tree type, enum machine_mode mode, int incoming_p)
6113 /* Beware that the two values are swapped here wrt function_arg. */
6114 int regbase = (incoming_p
6115 ? SPARC_OUTGOING_INT_ARG_FIRST
6116 : SPARC_INCOMING_INT_ARG_FIRST);
6117 enum mode_class mclass = GET_MODE_CLASS (mode);
6120 if (type && TREE_CODE (type) == VECTOR_TYPE)
6122 /* Vector types deserve special treatment because they are
6123 polymorphic wrt their mode, depending upon whether VIS
6124 instructions are enabled. */
6125 HOST_WIDE_INT size = int_size_in_bytes (type);
6127 if ((TARGET_ARCH32 && size > 8) || (TARGET_ARCH64 && size > 32))
6128 abort (); /* shouldn't get here */
6130 if (mode == BLKmode)
6131 return function_arg_vector_value (size,
6132 TYPE_MODE (TREE_TYPE (type)),
6133 SPARC_FP_ARG_FIRST);
6135 mclass = MODE_FLOAT;
6137 else if (type && TARGET_ARCH64)
6139 if (TREE_CODE (type) == RECORD_TYPE)
6141 /* Structures up to 32 bytes in size are passed in registers,
6142 promoted to fp registers where possible. */
6144 if (int_size_in_bytes (type) > 32)
6145 abort (); /* shouldn't get here */
6147 return function_arg_record_value (type, mode, 0, 1, regbase);
6149 else if (TREE_CODE (type) == UNION_TYPE)
6151 HOST_WIDE_INT size = int_size_in_bytes (type);
6154 abort (); /* shouldn't get here */
6156 return function_arg_union_value (size, mode, 0, regbase);
6158 else if (AGGREGATE_TYPE_P (type))
6160 /* All other aggregate types are passed in an integer register
6161 in a mode corresponding to the size of the type. */
6162 HOST_WIDE_INT bytes = int_size_in_bytes (type);
6165 abort (); /* shouldn't get here */
6167 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
6169 /* ??? We probably should have made the same ABI change in
6170 3.4.0 as the one we made for unions. The latter was
6171 required by the SCD though, while the former is not
6172 specified, so we favored compatibility and efficiency.
6174 Now we're stuck for aggregates larger than 16 bytes,
6175 because OImode vanished in the meantime. Let's not
6176 try to be unduly clever, and simply follow the ABI
6177 for unions in that case. */
6178 if (mode == BLKmode)
6179 return function_arg_union_value (bytes, mode, 0, regbase);
6183 else if (mclass == MODE_INT
6184 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6188 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6190 regno = SPARC_FP_ARG_FIRST;
6194 return gen_rtx_REG (mode, regno);
6197 /* Do what is necessary for `va_start'. We look at the current function
6198 to determine if stdarg or varargs is used and return the address of
6199 the first unnamed parameter. */
6202 sparc_builtin_saveregs (void)
6204 int first_reg = current_function_args_info.words;
6208 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6209 emit_move_insn (gen_rtx_MEM (word_mode,
6210 gen_rtx_PLUS (Pmode,
6212 GEN_INT (FIRST_PARM_OFFSET (0)
6215 gen_rtx_REG (word_mode,
6216 SPARC_INCOMING_INT_ARG_FIRST + regno));
6218 address = gen_rtx_PLUS (Pmode,
6220 GEN_INT (FIRST_PARM_OFFSET (0)
6221 + UNITS_PER_WORD * first_reg));
6226 /* Implement `va_start' for stdarg. */
6229 sparc_va_start (tree valist, rtx nextarg)
6231 nextarg = expand_builtin_saveregs ();
6232 std_expand_builtin_va_start (valist, nextarg);
6235 /* Implement `va_arg' for stdarg. */
6238 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6240 HOST_WIDE_INT size, rsize, align;
6243 tree ptrtype = build_pointer_type (type);
6245 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6248 size = rsize = UNITS_PER_WORD;
6254 size = int_size_in_bytes (type);
6255 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6260 /* For SPARC64, objects requiring 16-byte alignment get it. */
6261 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6262 align = 2 * UNITS_PER_WORD;
6264 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6265 are left-justified in their slots. */
6266 if (AGGREGATE_TYPE_P (type))
6269 size = rsize = UNITS_PER_WORD;
6279 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6280 ssize_int (align - 1)));
6281 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6282 ssize_int (-align)));
6285 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6288 if (BYTES_BIG_ENDIAN && size < rsize)
6289 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6290 ssize_int (rsize - size)));
6294 addr = fold_convert (build_pointer_type (ptrtype), addr);
6295 addr = build_va_arg_indirect_ref (addr);
6297 /* If the address isn't aligned properly for the type,
6298 we may need to copy to a temporary.
6299 FIXME: This is inefficient. Usually we can do this
6302 && TYPE_ALIGN (type) > BITS_PER_WORD)
6304 tree tmp = create_tmp_var (type, "va_arg_tmp");
6305 tree dest_addr = build_fold_addr_expr (tmp);
6307 tree copy = build_function_call_expr
6308 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6309 tree_cons (NULL_TREE, dest_addr,
6310 tree_cons (NULL_TREE, addr,
6311 tree_cons (NULL_TREE, size_int (rsize),
6314 gimplify_and_add (copy, pre_p);
6318 addr = fold_convert (ptrtype, addr);
6320 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6321 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6322 gimplify_and_add (incr, post_p);
6324 return build_va_arg_indirect_ref (addr);
6327 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6328 Specify whether the vector mode is supported by the hardware. */
6331 sparc_vector_mode_supported_p (enum machine_mode mode)
6333 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6336 /* Return the string to output an unconditional branch to LABEL, which is
6337 the operand number of the label.
6339 DEST is the destination insn (i.e. the label), INSN is the source. */
6342 output_ubranch (rtx dest, int label, rtx insn)
6344 static char string[64];
6345 bool v9_form = false;
6348 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6350 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6351 - INSN_ADDRESSES (INSN_UID (insn)));
6352 /* Leave some instructions for "slop". */
6353 if (delta >= -260000 && delta < 260000)
6358 strcpy (string, "ba%*,pt\t%%xcc, ");
6360 strcpy (string, "b%*\t");
6362 p = strchr (string, '\0');
6373 /* Return the string to output a conditional branch to LABEL, which is
6374 the operand number of the label. OP is the conditional expression.
6375 XEXP (OP, 0) is assumed to be a condition code register (integer or
6376 floating point) and its mode specifies what kind of comparison we made.
6378 DEST is the destination insn (i.e. the label), INSN is the source.
6380 REVERSED is nonzero if we should reverse the sense of the comparison.
6382 ANNUL is nonzero if we should generate an annulling branch. */
6385 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6388 static char string[64];
6389 enum rtx_code code = GET_CODE (op);
6390 rtx cc_reg = XEXP (op, 0);
6391 enum machine_mode mode = GET_MODE (cc_reg);
6392 const char *labelno, *branch;
6393 int spaces = 8, far;
6396 /* v9 branches are limited to +-1MB. If it is too far away,
6409 fbne,a,pn %fcc2, .LC29
6417 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6420 /* Reversal of FP compares takes care -- an ordered compare
6421 becomes an unordered compare and vice versa. */
6422 if (mode == CCFPmode || mode == CCFPEmode)
6423 code = reverse_condition_maybe_unordered (code);
6425 code = reverse_condition (code);
6428 /* Start by writing the branch condition. */
6429 if (mode == CCFPmode || mode == CCFPEmode)
6480 /* ??? !v9: FP branches cannot be preceded by another floating point
6481 insn. Because there is currently no concept of pre-delay slots,
6482 we can fix this only by always emitting a nop before a floating
6487 strcpy (string, "nop\n\t");
6488 strcat (string, branch);
6501 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6513 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6534 strcpy (string, branch);
6536 spaces -= strlen (branch);
6537 p = strchr (string, '\0');
6539 /* Now add the annulling, the label, and a possible noop. */
6552 if (! far && insn && INSN_ADDRESSES_SET_P ())
6554 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6555 - INSN_ADDRESSES (INSN_UID (insn)));
6556 /* Leave some instructions for "slop". */
6557 if (delta < -260000 || delta >= 260000)
6561 if (mode == CCFPmode || mode == CCFPEmode)
6563 static char v9_fcc_labelno[] = "%%fccX, ";
6564 /* Set the char indicating the number of the fcc reg to use. */
6565 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6566 labelno = v9_fcc_labelno;
6569 if (REGNO (cc_reg) == SPARC_FCC_REG)
6575 else if (mode == CCXmode || mode == CCX_NOOVmode)
6577 labelno = "%%xcc, ";
6583 labelno = "%%icc, ";
6588 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6591 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6604 strcpy (p, labelno);
6605 p = strchr (p, '\0');
6608 strcpy (p, ".+12\n\t nop\n\tb\t");
6609 /* Skip the next insn if requested or
6610 if we know that it will be a nop. */
6611 if (annul || ! final_sequence)
6625 /* Emit a library call comparison between floating point X and Y.
6626 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6627 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6628 values as arguments instead of the TFmode registers themselves,
6629 that's why we cannot call emit_float_lib_cmp. */
6631 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6634 rtx slot0, slot1, result, tem, tem2;
6635 enum machine_mode mode;
6640 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6644 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6648 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6652 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6656 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6660 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6671 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6681 if (GET_CODE (x) != MEM)
6683 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6684 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6689 if (GET_CODE (y) != MEM)
6691 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6692 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6697 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6699 XEXP (slot0, 0), Pmode,
6700 XEXP (slot1, 0), Pmode);
6706 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6708 x, TFmode, y, TFmode);
6714 /* Immediately move the result of the libcall into a pseudo
6715 register so reload doesn't clobber the value if it needs
6716 the return register for a spill reg. */
6717 result = gen_reg_rtx (mode);
6718 emit_move_insn (result, hard_libcall_value (mode));
6723 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6727 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6732 emit_cmp_insn (result, const1_rtx,
6733 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6736 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6739 tem = gen_reg_rtx (mode);
6741 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6743 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6744 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6748 tem = gen_reg_rtx (mode);
6750 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6752 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6753 tem2 = gen_reg_rtx (mode);
6755 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6757 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6758 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6764 /* Generate an unsigned DImode to FP conversion. This is the same code
6765 optabs would emit if we didn't have TFmode patterns. */
6768 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6770 rtx neglab, donelab, i0, i1, f0, in, out;
6773 in = force_reg (DImode, operands[1]);
6774 neglab = gen_label_rtx ();
6775 donelab = gen_label_rtx ();
6776 i0 = gen_reg_rtx (DImode);
6777 i1 = gen_reg_rtx (DImode);
6778 f0 = gen_reg_rtx (mode);
6780 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6782 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6783 emit_jump_insn (gen_jump (donelab));
6786 emit_label (neglab);
6788 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6789 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6790 emit_insn (gen_iordi3 (i0, i0, i1));
6791 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6792 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6794 emit_label (donelab);
6797 /* Generate an FP to unsigned DImode conversion. This is the same code
6798 optabs would emit if we didn't have TFmode patterns. */
6801 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6803 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6806 in = force_reg (mode, operands[1]);
6807 neglab = gen_label_rtx ();
6808 donelab = gen_label_rtx ();
6809 i0 = gen_reg_rtx (DImode);
6810 i1 = gen_reg_rtx (DImode);
6811 limit = gen_reg_rtx (mode);
6812 f0 = gen_reg_rtx (mode);
6814 emit_move_insn (limit,
6815 CONST_DOUBLE_FROM_REAL_VALUE (
6816 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6817 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6819 emit_insn (gen_rtx_SET (VOIDmode,
6821 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6822 emit_jump_insn (gen_jump (donelab));
6825 emit_label (neglab);
6827 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6828 emit_insn (gen_rtx_SET (VOIDmode,
6830 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6831 emit_insn (gen_movdi (i1, const1_rtx));
6832 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6833 emit_insn (gen_xordi3 (out, i0, i1));
6835 emit_label (donelab);
6838 /* Return the string to output a conditional branch to LABEL, testing
6839 register REG. LABEL is the operand number of the label; REG is the
6840 operand number of the reg. OP is the conditional expression. The mode
6841 of REG says what kind of comparison we made.
6843 DEST is the destination insn (i.e. the label), INSN is the source.
6845 REVERSED is nonzero if we should reverse the sense of the comparison.
6847 ANNUL is nonzero if we should generate an annulling branch. */
6850 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6851 int annul, rtx insn)
6853 static char string[64];
6854 enum rtx_code code = GET_CODE (op);
6855 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6860 /* branch on register are limited to +-128KB. If it is too far away,
6873 brgez,a,pn %o1, .LC29
6879 ba,pt %xcc, .LC29 */
6881 far = get_attr_length (insn) >= 3;
6883 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6885 code = reverse_condition (code);
6887 /* Only 64 bit versions of these instructions exist. */
6891 /* Start by writing the branch condition. */
6896 strcpy (string, "brnz");
6900 strcpy (string, "brz");
6904 strcpy (string, "brgez");
6908 strcpy (string, "brlz");
6912 strcpy (string, "brlez");
6916 strcpy (string, "brgz");
6923 p = strchr (string, '\0');
6925 /* Now add the annulling, reg, label, and nop. */
6932 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6935 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6940 *p = p < string + 8 ? '\t' : ' ';
6948 int veryfar = 1, delta;
6950 if (INSN_ADDRESSES_SET_P ())
6952 delta = (INSN_ADDRESSES (INSN_UID (dest))
6953 - INSN_ADDRESSES (INSN_UID (insn)));
6954 /* Leave some instructions for "slop". */
6955 if (delta >= -260000 && delta < 260000)
6959 strcpy (p, ".+12\n\t nop\n\t");
6960 /* Skip the next insn if requested or
6961 if we know that it will be a nop. */
6962 if (annul || ! final_sequence)
6972 strcpy (p, "ba,pt\t%%xcc, ");
6986 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6987 Such instructions cannot be used in the delay slot of return insn on v9.
6988 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6992 epilogue_renumber (register rtx *where, int test)
6994 register const char *fmt;
6996 register enum rtx_code code;
7001 code = GET_CODE (*where);
7006 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7008 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7009 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7017 /* Do not replace the frame pointer with the stack pointer because
7018 it can cause the delayed instruction to load below the stack.
7019 This occurs when instructions like:
7021 (set (reg/i:SI 24 %i0)
7022 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7023 (const_int -20 [0xffffffec])) 0))
7025 are in the return delayed slot. */
7027 if (GET_CODE (XEXP (*where, 0)) == REG
7028 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7029 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7030 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7035 if (SPARC_STACK_BIAS
7036 && GET_CODE (XEXP (*where, 0)) == REG
7037 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7045 fmt = GET_RTX_FORMAT (code);
7047 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7052 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7053 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7056 else if (fmt[i] == 'e'
7057 && epilogue_renumber (&(XEXP (*where, i)), test))
7063 /* Leaf functions and non-leaf functions have different needs. */
7066 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7069 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7071 static const int *const reg_alloc_orders[] = {
7072 reg_leaf_alloc_order,
7073 reg_nonleaf_alloc_order};
7076 order_regs_for_local_alloc (void)
7078 static int last_order_nonleaf = 1;
7080 if (regs_ever_live[15] != last_order_nonleaf)
7082 last_order_nonleaf = !last_order_nonleaf;
7083 memcpy ((char *) reg_alloc_order,
7084 (const char *) reg_alloc_orders[last_order_nonleaf],
7085 FIRST_PSEUDO_REGISTER * sizeof (int));
7089 /* Return 1 if REG and MEM are legitimate enough to allow the various
7090 mem<-->reg splits to be run. */
7093 sparc_splitdi_legitimate (rtx reg, rtx mem)
7095 /* Punt if we are here by mistake. */
7096 if (! reload_completed)
7099 /* We must have an offsettable memory reference. */
7100 if (! offsettable_memref_p (mem))
7103 /* If we have legitimate args for ldd/std, we do not want
7104 the split to happen. */
7105 if ((REGNO (reg) % 2) == 0
7106 && mem_min_alignment (mem, 8))
7113 /* Return 1 if x and y are some kind of REG and they refer to
7114 different hard registers. This test is guaranteed to be
7115 run after reload. */
7118 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7120 if (GET_CODE (x) != REG)
7122 if (GET_CODE (y) != REG)
7124 if (REGNO (x) == REGNO (y))
7129 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7130 This makes them candidates for using ldd and std insns.
7132 Note reg1 and reg2 *must* be hard registers. */
7135 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7137 /* We might have been passed a SUBREG. */
7138 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7141 if (REGNO (reg1) % 2 != 0)
7144 /* Integer ldd is deprecated in SPARC V9 */
7145 if (TARGET_V9 && REGNO (reg1) < 32)
7148 return (REGNO (reg1) == REGNO (reg2) - 1);
7151 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7154 This can only happen when addr1 and addr2, the addresses in mem1
7155 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7156 addr1 must also be aligned on a 64-bit boundary.
7158 Also iff dependent_reg_rtx is not null it should not be used to
7159 compute the address for mem1, i.e. we cannot optimize a sequence
7171 But, note that the transformation from:
7176 is perfectly fine. Thus, the peephole2 patterns always pass us
7177 the destination register of the first load, never the second one.
7179 For stores we don't have a similar problem, so dependent_reg_rtx is
7183 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7187 HOST_WIDE_INT offset1;
7189 /* The mems cannot be volatile. */
7190 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7193 /* MEM1 should be aligned on a 64-bit boundary. */
7194 if (MEM_ALIGN (mem1) < 64)
7197 addr1 = XEXP (mem1, 0);
7198 addr2 = XEXP (mem2, 0);
7200 /* Extract a register number and offset (if used) from the first addr. */
7201 if (GET_CODE (addr1) == PLUS)
7203 /* If not a REG, return zero. */
7204 if (GET_CODE (XEXP (addr1, 0)) != REG)
7208 reg1 = REGNO (XEXP (addr1, 0));
7209 /* The offset must be constant! */
7210 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7212 offset1 = INTVAL (XEXP (addr1, 1));
7215 else if (GET_CODE (addr1) != REG)
7219 reg1 = REGNO (addr1);
7220 /* This was a simple (mem (reg)) expression. Offset is 0. */
7224 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7225 if (GET_CODE (addr2) != PLUS)
7228 if (GET_CODE (XEXP (addr2, 0)) != REG
7229 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7232 if (reg1 != REGNO (XEXP (addr2, 0)))
7235 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7238 /* The first offset must be evenly divisible by 8 to ensure the
7239 address is 64 bit aligned. */
7240 if (offset1 % 8 != 0)
7243 /* The offset for the second addr must be 4 more than the first addr. */
7244 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7247 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7252 /* Return 1 if reg is a pseudo, or is the first register in
7253 a hard register pair. This makes it a candidate for use in
7254 ldd and std insns. */
7257 register_ok_for_ldd (rtx reg)
7259 /* We might have been passed a SUBREG. */
7260 if (GET_CODE (reg) != REG)
7263 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7264 return (REGNO (reg) % 2 == 0);
7269 /* Print operand X (an rtx) in assembler syntax to file FILE.
7270 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7271 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7274 print_operand (FILE *file, rtx x, int code)
7279 /* Output an insn in a delay slot. */
7281 sparc_indent_opcode = 1;
7283 fputs ("\n\t nop", file);
7286 /* Output an annul flag if there's nothing for the delay slot and we
7287 are optimizing. This is always used with '(' below.
7288 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7289 this is a dbx bug. So, we only do this when optimizing.
7290 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7291 Always emit a nop in case the next instruction is a branch. */
7292 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7296 /* Output a 'nop' if there's nothing for the delay slot and we are
7297 not optimizing. This is always used with '*' above. */
7298 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7299 fputs ("\n\t nop", file);
7300 else if (final_sequence)
7301 sparc_indent_opcode = 1;
7304 /* Output the right displacement from the saved PC on function return.
7305 The caller may have placed an "unimp" insn immediately after the call
7306 so we have to account for it. This insn is used in the 32-bit ABI
7307 when calling a function that returns a non zero-sized structure. The
7308 64-bit ABI doesn't have it. Be careful to have this test be the same
7309 as that used on the call. */
7311 && current_function_returns_struct
7312 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7314 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
7320 /* Output the Embedded Medium/Anywhere code model base register. */
7321 fputs (EMBMEDANY_BASE_REG, file);
7324 /* Print some local dynamic TLS name. */
7325 assemble_name (file, get_some_local_dynamic_name ());
7329 /* Adjust the operand to take into account a RESTORE operation. */
7330 if (GET_CODE (x) == CONST_INT)
7332 else if (GET_CODE (x) != REG)
7333 output_operand_lossage ("invalid %%Y operand");
7334 else if (REGNO (x) < 8)
7335 fputs (reg_names[REGNO (x)], file);
7336 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7337 fputs (reg_names[REGNO (x)-16], file);
7339 output_operand_lossage ("invalid %%Y operand");
7342 /* Print out the low order register name of a register pair. */
7343 if (WORDS_BIG_ENDIAN)
7344 fputs (reg_names[REGNO (x)+1], file);
7346 fputs (reg_names[REGNO (x)], file);
7349 /* Print out the high order register name of a register pair. */
7350 if (WORDS_BIG_ENDIAN)
7351 fputs (reg_names[REGNO (x)], file);
7353 fputs (reg_names[REGNO (x)+1], file);
7356 /* Print out the second register name of a register pair or quad.
7357 I.e., R (%o0) => %o1. */
7358 fputs (reg_names[REGNO (x)+1], file);
7361 /* Print out the third register name of a register quad.
7362 I.e., S (%o0) => %o2. */
7363 fputs (reg_names[REGNO (x)+2], file);
7366 /* Print out the fourth register name of a register quad.
7367 I.e., T (%o0) => %o3. */
7368 fputs (reg_names[REGNO (x)+3], file);
7371 /* Print a condition code register. */
7372 if (REGNO (x) == SPARC_ICC_REG)
7374 /* We don't handle CC[X]_NOOVmode because they're not supposed
7376 if (GET_MODE (x) == CCmode)
7377 fputs ("%icc", file);
7378 else if (GET_MODE (x) == CCXmode)
7379 fputs ("%xcc", file);
7384 /* %fccN register */
7385 fputs (reg_names[REGNO (x)], file);
7388 /* Print the operand's address only. */
7389 output_address (XEXP (x, 0));
7392 /* In this case we need a register. Use %g0 if the
7393 operand is const0_rtx. */
7395 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7397 fputs ("%g0", file);
7404 switch (GET_CODE (x))
7406 case IOR: fputs ("or", file); break;
7407 case AND: fputs ("and", file); break;
7408 case XOR: fputs ("xor", file); break;
7409 default: output_operand_lossage ("invalid %%A operand");
7414 switch (GET_CODE (x))
7416 case IOR: fputs ("orn", file); break;
7417 case AND: fputs ("andn", file); break;
7418 case XOR: fputs ("xnor", file); break;
7419 default: output_operand_lossage ("invalid %%B operand");
7423 /* These are used by the conditional move instructions. */
7427 enum rtx_code rc = GET_CODE (x);
7431 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7432 if (mode == CCFPmode || mode == CCFPEmode)
7433 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7435 rc = reverse_condition (GET_CODE (x));
7439 case NE: fputs ("ne", file); break;
7440 case EQ: fputs ("e", file); break;
7441 case GE: fputs ("ge", file); break;
7442 case GT: fputs ("g", file); break;
7443 case LE: fputs ("le", file); break;
7444 case LT: fputs ("l", file); break;
7445 case GEU: fputs ("geu", file); break;
7446 case GTU: fputs ("gu", file); break;
7447 case LEU: fputs ("leu", file); break;
7448 case LTU: fputs ("lu", file); break;
7449 case LTGT: fputs ("lg", file); break;
7450 case UNORDERED: fputs ("u", file); break;
7451 case ORDERED: fputs ("o", file); break;
7452 case UNLT: fputs ("ul", file); break;
7453 case UNLE: fputs ("ule", file); break;
7454 case UNGT: fputs ("ug", file); break;
7455 case UNGE: fputs ("uge", file); break;
7456 case UNEQ: fputs ("ue", file); break;
7457 default: output_operand_lossage (code == 'c'
7458 ? "invalid %%c operand"
7459 : "invalid %%C operand");
7464 /* These are used by the movr instruction pattern. */
7468 enum rtx_code rc = (code == 'd'
7469 ? reverse_condition (GET_CODE (x))
7473 case NE: fputs ("ne", file); break;
7474 case EQ: fputs ("e", file); break;
7475 case GE: fputs ("gez", file); break;
7476 case LT: fputs ("lz", file); break;
7477 case LE: fputs ("lez", file); break;
7478 case GT: fputs ("gz", file); break;
7479 default: output_operand_lossage (code == 'd'
7480 ? "invalid %%d operand"
7481 : "invalid %%D operand");
7488 /* Print a sign-extended character. */
7489 int i = trunc_int_for_mode (INTVAL (x), QImode);
7490 fprintf (file, "%d", i);
7495 /* Operand must be a MEM; write its address. */
7496 if (GET_CODE (x) != MEM)
7497 output_operand_lossage ("invalid %%f operand");
7498 output_address (XEXP (x, 0));
7503 /* Print a sign-extended 32-bit value. */
7505 if (GET_CODE(x) == CONST_INT)
7507 else if (GET_CODE(x) == CONST_DOUBLE)
7508 i = CONST_DOUBLE_LOW (x);
7511 output_operand_lossage ("invalid %%s operand");
7514 i = trunc_int_for_mode (i, SImode);
7515 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7520 /* Do nothing special. */
7524 /* Undocumented flag. */
7525 output_operand_lossage ("invalid operand output code");
7528 if (GET_CODE (x) == REG)
7529 fputs (reg_names[REGNO (x)], file);
7530 else if (GET_CODE (x) == MEM)
7533 /* Poor Sun assembler doesn't understand absolute addressing. */
7534 if (CONSTANT_P (XEXP (x, 0)))
7535 fputs ("%g0+", file);
7536 output_address (XEXP (x, 0));
7539 else if (GET_CODE (x) == HIGH)
7541 fputs ("%hi(", file);
7542 output_addr_const (file, XEXP (x, 0));
7545 else if (GET_CODE (x) == LO_SUM)
7547 print_operand (file, XEXP (x, 0), 0);
7548 if (TARGET_CM_MEDMID)
7549 fputs ("+%l44(", file);
7551 fputs ("+%lo(", file);
7552 output_addr_const (file, XEXP (x, 1));
7555 else if (GET_CODE (x) == CONST_DOUBLE
7556 && (GET_MODE (x) == VOIDmode
7557 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7559 if (CONST_DOUBLE_HIGH (x) == 0)
7560 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7561 else if (CONST_DOUBLE_HIGH (x) == -1
7562 && CONST_DOUBLE_LOW (x) < 0)
7563 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7565 output_operand_lossage ("long long constant not a valid immediate operand");
7567 else if (GET_CODE (x) == CONST_DOUBLE)
7568 output_operand_lossage ("floating point constant not a valid immediate operand");
7569 else { output_addr_const (file, x); }
7572 /* Target hook for assembling integer objects. The sparc version has
7573 special handling for aligned DI-mode objects. */
7576 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7578 /* ??? We only output .xword's for symbols and only then in environments
7579 where the assembler can handle them. */
7580 if (aligned_p && size == 8
7581 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7585 assemble_integer_with_op ("\t.xword\t", x);
7590 assemble_aligned_integer (4, const0_rtx);
7591 assemble_aligned_integer (4, x);
7595 return default_assemble_integer (x, size, aligned_p);
7598 /* Return the value of a code used in the .proc pseudo-op that says
7599 what kind of result this function returns. For non-C types, we pick
7600 the closest C type. */
7602 #ifndef SHORT_TYPE_SIZE
7603 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7606 #ifndef INT_TYPE_SIZE
7607 #define INT_TYPE_SIZE BITS_PER_WORD
7610 #ifndef LONG_TYPE_SIZE
7611 #define LONG_TYPE_SIZE BITS_PER_WORD
7614 #ifndef LONG_LONG_TYPE_SIZE
7615 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7618 #ifndef FLOAT_TYPE_SIZE
7619 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7622 #ifndef DOUBLE_TYPE_SIZE
7623 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7626 #ifndef LONG_DOUBLE_TYPE_SIZE
7627 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7631 sparc_type_code (register tree type)
7633 register unsigned long qualifiers = 0;
7634 register unsigned shift;
7636 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7637 setting more, since some assemblers will give an error for this. Also,
7638 we must be careful to avoid shifts of 32 bits or more to avoid getting
7639 unpredictable results. */
7641 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7643 switch (TREE_CODE (type))
7649 qualifiers |= (3 << shift);
7654 qualifiers |= (2 << shift);
7658 case REFERENCE_TYPE:
7660 qualifiers |= (1 << shift);
7664 return (qualifiers | 8);
7667 case QUAL_UNION_TYPE:
7668 return (qualifiers | 9);
7671 return (qualifiers | 10);
7674 return (qualifiers | 16);
7677 /* If this is a range type, consider it to be the underlying
7679 if (TREE_TYPE (type) != 0)
7682 /* Carefully distinguish all the standard types of C,
7683 without messing up if the language is not C. We do this by
7684 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7685 look at both the names and the above fields, but that's redundant.
7686 Any type whose size is between two C types will be considered
7687 to be the wider of the two types. Also, we do not have a
7688 special code to use for "long long", so anything wider than
7689 long is treated the same. Note that we can't distinguish
7690 between "int" and "long" in this code if they are the same
7691 size, but that's fine, since neither can the assembler. */
7693 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7694 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7696 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7697 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7699 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7700 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7703 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7706 /* If this is a range type, consider it to be the underlying
7708 if (TREE_TYPE (type) != 0)
7711 /* Carefully distinguish all the standard types of C,
7712 without messing up if the language is not C. */
7714 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7715 return (qualifiers | 6);
7718 return (qualifiers | 7);
7720 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7721 /* ??? We need to distinguish between double and float complex types,
7722 but I don't know how yet because I can't reach this code from
7723 existing front-ends. */
7724 return (qualifiers | 7); /* Who knows? */
7727 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7728 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7729 case LANG_TYPE: /* ? */
7733 abort (); /* Not a type! */
7740 /* Nested function support. */
7742 /* Emit RTL insns to initialize the variable parts of a trampoline.
7743 FNADDR is an RTX for the address of the function's pure code.
7744 CXT is an RTX for the static chain value for the function.
7746 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7747 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7748 (to store insns). This is a bit excessive. Perhaps a different
7749 mechanism would be better here.
7751 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7754 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7756 /* SPARC 32-bit trampoline:
7759 sethi %hi(static), %g2
7761 or %g2, %lo(static), %g2
7763 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7764 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7768 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7769 expand_binop (SImode, ior_optab,
7770 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7771 size_int (10), 0, 1),
7772 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7773 NULL_RTX, 1, OPTAB_DIRECT));
7776 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7777 expand_binop (SImode, ior_optab,
7778 expand_shift (RSHIFT_EXPR, SImode, cxt,
7779 size_int (10), 0, 1),
7780 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7781 NULL_RTX, 1, OPTAB_DIRECT));
7784 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7785 expand_binop (SImode, ior_optab,
7786 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7787 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7788 NULL_RTX, 1, OPTAB_DIRECT));
7791 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7792 expand_binop (SImode, ior_optab,
7793 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7794 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7795 NULL_RTX, 1, OPTAB_DIRECT));
7797 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7798 aligned on a 16 byte boundary so one flush clears it all. */
7799 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7800 if (sparc_cpu != PROCESSOR_ULTRASPARC
7801 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7802 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7803 plus_constant (tramp, 8)))));
7805 /* Call __enable_execute_stack after writing onto the stack to make sure
7806 the stack address is accessible. */
7807 #ifdef ENABLE_EXECUTE_STACK
7808 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7809 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7814 /* The 64-bit version is simpler because it makes more sense to load the
7815 values as "immediate" data out of the trampoline. It's also easier since
7816 we can read the PC without clobbering a register. */
7819 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7821 /* SPARC 64-bit trampoline:
7830 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7831 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7832 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7833 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7834 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7835 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7836 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7837 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7838 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7839 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7840 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7842 if (sparc_cpu != PROCESSOR_ULTRASPARC
7843 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7844 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7846 /* Call __enable_execute_stack after writing onto the stack to make sure
7847 the stack address is accessible. */
7848 #ifdef ENABLE_EXECUTE_STACK
7849 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7850 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7854 /* Adjust the cost of a scheduling dependency. Return the new cost of
7855 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7858 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7860 enum attr_type insn_type;
7862 if (! recog_memoized (insn))
7865 insn_type = get_attr_type (insn);
7867 if (REG_NOTE_KIND (link) == 0)
7869 /* Data dependency; DEP_INSN writes a register that INSN reads some
7872 /* if a load, then the dependence must be on the memory address;
7873 add an extra "cycle". Note that the cost could be two cycles
7874 if the reg was written late in an instruction group; we ca not tell
7876 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7879 /* Get the delay only if the address of the store is the dependence. */
7880 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7882 rtx pat = PATTERN(insn);
7883 rtx dep_pat = PATTERN (dep_insn);
7885 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7886 return cost; /* This should not happen! */
7888 /* The dependency between the two instructions was on the data that
7889 is being stored. Assume that this implies that the address of the
7890 store is not dependent. */
7891 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7894 return cost + 3; /* An approximation. */
7897 /* A shift instruction cannot receive its data from an instruction
7898 in the same cycle; add a one cycle penalty. */
7899 if (insn_type == TYPE_SHIFT)
7900 return cost + 3; /* Split before cascade into shift. */
7904 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7905 INSN writes some cycles later. */
7907 /* These are only significant for the fpu unit; writing a fp reg before
7908 the fpu has finished with it stalls the processor. */
7910 /* Reusing an integer register causes no problems. */
7911 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7919 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7921 enum attr_type insn_type, dep_type;
7922 rtx pat = PATTERN(insn);
7923 rtx dep_pat = PATTERN (dep_insn);
7925 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7928 insn_type = get_attr_type (insn);
7929 dep_type = get_attr_type (dep_insn);
7931 switch (REG_NOTE_KIND (link))
7934 /* Data dependency; DEP_INSN writes a register that INSN reads some
7941 /* Get the delay iff the address of the store is the dependence. */
7942 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7945 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7952 /* If a load, then the dependence must be on the memory address. If
7953 the addresses aren't equal, then it might be a false dependency */
7954 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7956 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7957 || GET_CODE (SET_DEST (dep_pat)) != MEM
7958 || GET_CODE (SET_SRC (pat)) != MEM
7959 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7960 XEXP (SET_SRC (pat), 0)))
7968 /* Compare to branch latency is 0. There is no benefit from
7969 separating compare and branch. */
7970 if (dep_type == TYPE_COMPARE)
7972 /* Floating point compare to branch latency is less than
7973 compare to conditional move. */
7974 if (dep_type == TYPE_FPCMP)
7983 /* Anti-dependencies only penalize the fpu unit. */
7984 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7996 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8000 case PROCESSOR_SUPERSPARC:
8001 cost = supersparc_adjust_cost (insn, link, dep, cost);
8003 case PROCESSOR_HYPERSPARC:
8004 case PROCESSOR_SPARCLITE86X:
8005 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8014 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8015 int sched_verbose ATTRIBUTE_UNUSED,
8016 int max_ready ATTRIBUTE_UNUSED)
8021 sparc_use_sched_lookahead (void)
8023 if (sparc_cpu == PROCESSOR_ULTRASPARC
8024 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8026 if ((1 << sparc_cpu) &
8027 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8028 (1 << PROCESSOR_SPARCLITE86X)))
8034 sparc_issue_rate (void)
8041 /* Assume V9 processors are capable of at least dual-issue. */
8043 case PROCESSOR_SUPERSPARC:
8045 case PROCESSOR_HYPERSPARC:
8046 case PROCESSOR_SPARCLITE86X:
8048 case PROCESSOR_ULTRASPARC:
8049 case PROCESSOR_ULTRASPARC3:
8055 set_extends (rtx insn)
8057 register rtx pat = PATTERN (insn);
8059 switch (GET_CODE (SET_SRC (pat)))
8061 /* Load and some shift instructions zero extend. */
8064 /* sethi clears the high bits */
8066 /* LO_SUM is used with sethi. sethi cleared the high
8067 bits and the values used with lo_sum are positive */
8069 /* Store flag stores 0 or 1 */
8079 rtx op0 = XEXP (SET_SRC (pat), 0);
8080 rtx op1 = XEXP (SET_SRC (pat), 1);
8081 if (GET_CODE (op1) == CONST_INT)
8082 return INTVAL (op1) >= 0;
8083 if (GET_CODE (op0) != REG)
8085 if (sparc_check_64 (op0, insn) == 1)
8087 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8092 rtx op0 = XEXP (SET_SRC (pat), 0);
8093 rtx op1 = XEXP (SET_SRC (pat), 1);
8094 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8096 if (GET_CODE (op1) == CONST_INT)
8097 return INTVAL (op1) >= 0;
8098 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8101 return GET_MODE (SET_SRC (pat)) == SImode;
8102 /* Positive integers leave the high bits zero. */
8104 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8106 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8109 return - (GET_MODE (SET_SRC (pat)) == SImode);
8111 return sparc_check_64 (SET_SRC (pat), insn);
8117 /* We _ought_ to have only one kind per function, but... */
8118 static GTY(()) rtx sparc_addr_diff_list;
8119 static GTY(()) rtx sparc_addr_list;
8122 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8124 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8126 sparc_addr_diff_list
8127 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8129 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8133 sparc_output_addr_vec (rtx vec)
8135 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8136 int idx, vlen = XVECLEN (body, 0);
8138 #ifdef ASM_OUTPUT_ADDR_VEC_START
8139 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8142 #ifdef ASM_OUTPUT_CASE_LABEL
8143 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8146 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8149 for (idx = 0; idx < vlen; idx++)
8151 ASM_OUTPUT_ADDR_VEC_ELT
8152 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8155 #ifdef ASM_OUTPUT_ADDR_VEC_END
8156 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8161 sparc_output_addr_diff_vec (rtx vec)
8163 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8164 rtx base = XEXP (XEXP (body, 0), 0);
8165 int idx, vlen = XVECLEN (body, 1);
8167 #ifdef ASM_OUTPUT_ADDR_VEC_START
8168 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8171 #ifdef ASM_OUTPUT_CASE_LABEL
8172 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8175 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8178 for (idx = 0; idx < vlen; idx++)
8180 ASM_OUTPUT_ADDR_DIFF_ELT
8183 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8184 CODE_LABEL_NUMBER (base));
8187 #ifdef ASM_OUTPUT_ADDR_VEC_END
8188 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8193 sparc_output_deferred_case_vectors (void)
8198 if (sparc_addr_list == NULL_RTX
8199 && sparc_addr_diff_list == NULL_RTX)
8202 /* Align to cache line in the function's code section. */
8203 current_function_section (current_function_decl);
8205 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8207 ASM_OUTPUT_ALIGN (asm_out_file, align);
8209 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8210 sparc_output_addr_vec (XEXP (t, 0));
8211 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8212 sparc_output_addr_diff_vec (XEXP (t, 0));
8214 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8217 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8218 unknown. Return 1 if the high bits are zero, -1 if the register is
8221 sparc_check_64 (rtx x, rtx insn)
8223 /* If a register is set only once it is safe to ignore insns this
8224 code does not know how to handle. The loop will either recognize
8225 the single set and return the correct value or fail to recognize
8230 if (GET_CODE (x) != REG)
8233 if (GET_MODE (x) == DImode)
8234 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8236 if (flag_expensive_optimizations
8237 && REG_N_SETS (REGNO (y)) == 1)
8243 insn = get_last_insn_anywhere ();
8248 while ((insn = PREV_INSN (insn)))
8250 switch (GET_CODE (insn))
8263 rtx pat = PATTERN (insn);
8264 if (GET_CODE (pat) != SET)
8266 if (rtx_equal_p (x, SET_DEST (pat)))
8267 return set_extends (insn);
8268 if (y && rtx_equal_p (y, SET_DEST (pat)))
8269 return set_extends (insn);
8270 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8278 /* Returns assembly code to perform a DImode shift using
8279 a 64-bit global or out register on SPARC-V8+. */
8281 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8283 static char asm_code[60];
8285 /* The scratch register is only required when the destination
8286 register is not a 64-bit global or out register. */
8287 if (which_alternative != 2)
8288 operands[3] = operands[0];
8290 /* We can only shift by constants <= 63. */
8291 if (GET_CODE (operands[2]) == CONST_INT)
8292 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8294 if (GET_CODE (operands[1]) == CONST_INT)
8296 output_asm_insn ("mov\t%1, %3", operands);
8300 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8301 if (sparc_check_64 (operands[1], insn) <= 0)
8302 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8303 output_asm_insn ("or\t%L1, %3, %3", operands);
8306 strcpy(asm_code, opcode);
8308 if (which_alternative != 2)
8309 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8311 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8314 /* Output rtl to increment the profiler label LABELNO
8315 for profiling a function entry. */
8318 sparc_profile_hook (int labelno)
8323 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8324 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8325 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8327 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8330 #ifdef OBJECT_FORMAT_ELF
8332 sparc_elf_asm_named_section (const char *name, unsigned int flags,
8335 if (flags & SECTION_MERGE)
8337 /* entsize cannot be expressed in this section attributes
8339 default_elf_asm_named_section (name, flags, decl);
8343 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8345 if (!(flags & SECTION_DEBUG))
8346 fputs (",#alloc", asm_out_file);
8347 if (flags & SECTION_WRITE)
8348 fputs (",#write", asm_out_file);
8349 if (flags & SECTION_TLS)
8350 fputs (",#tls", asm_out_file);
8351 if (flags & SECTION_CODE)
8352 fputs (",#execinstr", asm_out_file);
8354 /* ??? Handle SECTION_BSS. */
8356 fputc ('\n', asm_out_file);
8358 #endif /* OBJECT_FORMAT_ELF */
8360 /* We do not allow indirect calls to be optimized into sibling calls.
8362 We cannot use sibling calls when delayed branches are disabled
8363 because they will likely require the call delay slot to be filled.
8365 Also, on SPARC 32-bit we cannot emit a sibling call when the
8366 current function returns a structure. This is because the "unimp
8367 after call" convention would cause the callee to return to the
8368 wrong place. The generic code already disallows cases where the
8369 function being called returns a structure.
8371 It may seem strange how this last case could occur. Usually there
8372 is code after the call which jumps to epilogue code which dumps the
8373 return value into the struct return area. That ought to invalidate
8374 the sibling call right? Well, in the C++ case we can end up passing
8375 the pointer to the struct return area to a constructor (which returns
8376 void) and then nothing else happens. Such a sibling call would look
8377 valid without the added check here. */
8379 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8382 && flag_delayed_branch
8383 && (TARGET_ARCH64 || ! current_function_returns_struct));
8386 /* libfunc renaming. */
8387 #include "config/gofast.h"
8390 sparc_init_libfuncs (void)
8394 /* Use the subroutines that Sun's library provides for integer
8395 multiply and divide. The `*' prevents an underscore from
8396 being prepended by the compiler. .umul is a little faster
8398 set_optab_libfunc (smul_optab, SImode, "*.umul");
8399 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8400 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8401 set_optab_libfunc (smod_optab, SImode, "*.rem");
8402 set_optab_libfunc (umod_optab, SImode, "*.urem");
8404 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8405 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8406 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8407 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8408 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8409 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8411 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8412 is because with soft-float, the SFmode and DFmode sqrt
8413 instructions will be absent, and the compiler will notice and
8414 try to use the TFmode sqrt instruction for calls to the
8415 builtin function sqrt, but this fails. */
8417 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8419 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8420 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8421 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8422 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8423 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8424 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8426 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8427 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8428 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8429 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8431 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8432 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8433 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8435 if (DITF_CONVERSION_LIBFUNCS)
8437 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8438 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8439 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8442 if (SUN_CONVERSION_LIBFUNCS)
8444 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8445 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8446 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8447 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8452 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8453 do not exist in the library. Make sure the compiler does not
8454 emit calls to them by accident. (It should always use the
8455 hardware instructions.) */
8456 set_optab_libfunc (smul_optab, SImode, 0);
8457 set_optab_libfunc (sdiv_optab, SImode, 0);
8458 set_optab_libfunc (udiv_optab, SImode, 0);
8459 set_optab_libfunc (smod_optab, SImode, 0);
8460 set_optab_libfunc (umod_optab, SImode, 0);
8462 if (SUN_INTEGER_MULTIPLY_64)
8464 set_optab_libfunc (smul_optab, DImode, "__mul64");
8465 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8466 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8467 set_optab_libfunc (smod_optab, DImode, "__rem64");
8468 set_optab_libfunc (umod_optab, DImode, "__urem64");
8471 if (SUN_CONVERSION_LIBFUNCS)
8473 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8474 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8475 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8476 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8480 gofast_maybe_init_libfuncs ();
8483 #define def_builtin(NAME, CODE, TYPE) \
8484 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
8487 /* Implement the TARGET_INIT_BUILTINS target hook.
8488 Create builtin functions for special SPARC instructions. */
8491 sparc_init_builtins (void)
8494 sparc_vis_init_builtins ();
8497 /* Create builtin functions for VIS 1.0 instructions. */
8500 sparc_vis_init_builtins (void)
8502 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
8503 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
8504 tree v4hi = build_vector_type (intHI_type_node, 4);
8505 tree v2hi = build_vector_type (intHI_type_node, 2);
8506 tree v2si = build_vector_type (intSI_type_node, 2);
8508 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
8509 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
8510 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
8511 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
8512 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
8513 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
8514 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
8515 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
8516 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
8517 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
8518 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
8519 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
8520 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
8522 intDI_type_node, 0);
8523 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
8525 intDI_type_node, 0);
8526 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
8528 intSI_type_node, 0);
8529 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
8531 intDI_type_node, 0);
8533 /* Packing and expanding vectors. */
8534 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
8535 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
8536 v8qi_ftype_v2si_v8qi);
8537 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
8539 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
8540 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
8541 v8qi_ftype_v4qi_v4qi);
8543 /* Multiplications. */
8544 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
8545 v4hi_ftype_v4qi_v4hi);
8546 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
8547 v4hi_ftype_v4qi_v2hi);
8548 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
8549 v4hi_ftype_v4qi_v2hi);
8550 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
8551 v4hi_ftype_v8qi_v4hi);
8552 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
8553 v4hi_ftype_v8qi_v4hi);
8554 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
8555 v2si_ftype_v4qi_v2hi);
8556 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
8557 v2si_ftype_v4qi_v2hi);
8559 /* Data aligning. */
8560 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
8561 v4hi_ftype_v4hi_v4hi);
8562 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
8563 v8qi_ftype_v8qi_v8qi);
8564 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
8565 v2si_ftype_v2si_v2si);
8566 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
8569 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
8572 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
8575 /* Pixel distance. */
8576 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
8577 di_ftype_v8qi_v8qi_di);
8580 /* Handle TARGET_EXPAND_BUILTIN target hook.
8581 Expand builtin functions for sparc instrinsics. */
8584 sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8585 enum machine_mode tmode, int ignore ATTRIBUTE_UNUSED)
8588 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8589 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
8591 enum machine_mode mode[4];
8594 mode[arg_count] = tmode;
8597 || GET_MODE (target) != tmode
8598 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8599 op[arg_count] = gen_reg_rtx (tmode);
8601 op[arg_count] = target;
8603 for (arglist = TREE_OPERAND (exp, 1); arglist;
8604 arglist = TREE_CHAIN (arglist))
8606 tree arg = TREE_VALUE (arglist);
8609 mode[arg_count] = insn_data[icode].operand[arg_count].mode;
8610 op[arg_count] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
8612 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
8614 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
8620 pat = GEN_FCN (icode) (op[0], op[1]);
8623 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
8626 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
8641 sparc_extra_constraint_check (rtx op, int c, int strict)
8646 && (c == 'T' || c == 'U'))
8652 return fp_sethi_p (op);
8655 return fp_mov_p (op);
8658 return fp_high_losum_p (op);
8662 || (GET_CODE (op) == REG
8663 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8664 || reg_renumber[REGNO (op)] >= 0)))
8665 return register_ok_for_ldd (op);
8674 return fp_zero_operand (op, GET_MODE (op));
8680 /* Our memory extra constraints have to emulate the
8681 behavior of 'm' and 'o' in order for reload to work
8683 if (GET_CODE (op) == MEM)
8686 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8688 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8693 reload_ok_mem = (reload_in_progress
8694 && GET_CODE (op) == REG
8695 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8696 && reg_renumber [REGNO (op)] < 0);
8699 return reload_ok_mem;
8702 /* ??? This duplicates information provided to the compiler by the
8703 ??? scheduler description. Some day, teach genautomata to output
8704 ??? the latencies and then CSE will just use that. */
8707 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8709 enum machine_mode mode = GET_MODE (x);
8710 bool float_mode_p = FLOAT_MODE_P (mode);
8715 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8733 if (GET_MODE (x) == DImode
8734 && ((XINT (x, 3) == 0
8735 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8736 || (XINT (x, 3) == -1
8738 && XINT (x, 2) >= -0x1000)))
8745 /* If outer-code was a sign or zero extension, a cost
8746 of COSTS_N_INSNS (1) was already added in. This is
8747 why we are subtracting it back out. */
8748 if (outer_code == ZERO_EXTEND)
8750 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8752 else if (outer_code == SIGN_EXTEND)
8754 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8756 else if (float_mode_p)
8758 *total = sparc_costs->float_load;
8762 *total = sparc_costs->int_load;
8770 *total = sparc_costs->float_plusminus;
8772 *total = COSTS_N_INSNS (1);
8777 *total = sparc_costs->float_mul;
8778 else if (! TARGET_HARD_MUL)
8779 *total = COSTS_N_INSNS (25);
8785 if (sparc_costs->int_mul_bit_factor)
8789 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8791 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8792 for (nbits = 0; value != 0; value &= value - 1)
8795 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8796 && GET_MODE (XEXP (x, 1)) == DImode)
8798 rtx x1 = XEXP (x, 1);
8799 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8800 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8802 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8804 for (; value2 != 0; value2 &= value2 - 1)
8812 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8813 bit_cost = COSTS_N_INSNS (bit_cost);
8817 *total = sparc_costs->int_mulX + bit_cost;
8819 *total = sparc_costs->int_mul + bit_cost;
8826 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8836 *total = sparc_costs->float_div_df;
8838 *total = sparc_costs->float_div_sf;
8843 *total = sparc_costs->int_divX;
8845 *total = sparc_costs->int_div;
8852 *total = COSTS_N_INSNS (1);
8859 case UNSIGNED_FLOAT:
8863 case FLOAT_TRUNCATE:
8864 *total = sparc_costs->float_move;
8869 *total = sparc_costs->float_sqrt_df;
8871 *total = sparc_costs->float_sqrt_sf;
8876 *total = sparc_costs->float_cmp;
8878 *total = COSTS_N_INSNS (1);
8883 *total = sparc_costs->float_cmove;
8885 *total = sparc_costs->int_cmove;
8889 /* Handle the NAND vector patterns. */
8890 if (sparc_vector_mode_supported_p (GET_MODE (x))
8891 && GET_CODE (XEXP (x, 0)) == NOT
8892 && GET_CODE (XEXP (x, 1)) == NOT)
8894 *total = COSTS_N_INSNS (1);
8905 /* Emit the sequence of insns SEQ while preserving the register REG. */
8908 emit_and_preserve (rtx seq, rtx reg)
8910 rtx slot = gen_rtx_MEM (word_mode,
8911 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8913 emit_insn (gen_stack_pointer_dec (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT)));
8914 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8916 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8917 emit_insn (gen_stack_pointer_inc (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT)));
8920 /* Output the assembler code for a thunk function. THUNK_DECL is the
8921 declaration for the thunk function itself, FUNCTION is the decl for
8922 the target function. DELTA is an immediate constant offset to be
8923 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8924 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8927 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8928 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8931 rtx this, insn, funexp;
8932 unsigned int int_arg_first;
8934 reload_completed = 1;
8935 epilogue_completed = 1;
8937 reset_block_changes ();
8939 emit_note (NOTE_INSN_PROLOGUE_END);
8941 if (flag_delayed_branch)
8943 /* We will emit a regular sibcall below, so we need to instruct
8944 output_sibcall that we are in a leaf function. */
8945 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
8947 /* This will cause final.c to invoke leaf_renumber_regs so we
8948 must behave as if we were in a not-yet-leafified function. */
8949 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8953 /* We will emit the sibcall manually below, so we will need to
8954 manually spill non-leaf registers. */
8955 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
8957 /* We really are in a leaf function. */
8958 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8961 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8962 returns a structure, the structure return pointer is there instead. */
8963 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8964 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8966 this = gen_rtx_REG (Pmode, int_arg_first);
8968 /* Add DELTA. When possible use a plain add, otherwise load it into
8969 a register first. */
8972 rtx delta_rtx = GEN_INT (delta);
8974 if (! SPARC_SIMM13_P (delta))
8976 rtx scratch = gen_rtx_REG (Pmode, 1);
8977 emit_move_insn (scratch, delta_rtx);
8978 delta_rtx = scratch;
8981 /* THIS += DELTA. */
8982 emit_insn (gen_add2_insn (this, delta_rtx));
8985 /* Add the word at address (*THIS + VCALL_OFFSET). */
8988 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8989 rtx scratch = gen_rtx_REG (Pmode, 1);
8991 if (vcall_offset >= 0)
8994 /* SCRATCH = *THIS. */
8995 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
8997 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8998 may not have any available scratch register at this point. */
8999 if (SPARC_SIMM13_P (vcall_offset))
9001 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9002 else if (! fixed_regs[5]
9003 /* The below sequence is made up of at least 2 insns,
9004 while the default method may need only one. */
9005 && vcall_offset < -8192)
9007 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9008 emit_move_insn (scratch2, vcall_offset_rtx);
9009 vcall_offset_rtx = scratch2;
9013 rtx increment = GEN_INT (-4096);
9015 /* VCALL_OFFSET is a negative number whose typical range can be
9016 estimated as -32768..0 in 32-bit mode. In almost all cases
9017 it is therefore cheaper to emit multiple add insns than
9018 spilling and loading the constant into a register (at least
9020 while (! SPARC_SIMM13_P (vcall_offset))
9022 emit_insn (gen_add2_insn (scratch, increment));
9023 vcall_offset += 4096;
9025 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
9028 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
9029 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9030 gen_rtx_PLUS (Pmode,
9032 vcall_offset_rtx)));
9034 /* THIS += *(*THIS + VCALL_OFFSET). */
9035 emit_insn (gen_add2_insn (this, scratch));
9038 /* Generate a tail call to the target function. */
9039 if (! TREE_USED (function))
9041 assemble_external (function);
9042 TREE_USED (function) = 1;
9044 funexp = XEXP (DECL_RTL (function), 0);
9046 if (flag_delayed_branch)
9048 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9049 insn = emit_call_insn (gen_sibcall (funexp));
9050 SIBLING_CALL_P (insn) = 1;
9054 /* The hoops we have to jump through in order to generate a sibcall
9055 without using delay slots... */
9056 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
9060 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
9062 /* Delay emitting the PIC helper function because it needs to
9063 change the section and we are emitting assembly code. */
9064 load_pic_register (true); /* clobbers %o7 */
9065 scratch = legitimize_pic_address (funexp, Pmode, scratch);
9068 emit_and_preserve (seq, spill_reg);
9070 else if (TARGET_ARCH32)
9072 emit_insn (gen_rtx_SET (VOIDmode,
9074 gen_rtx_HIGH (SImode, funexp)));
9075 emit_insn (gen_rtx_SET (VOIDmode,
9077 gen_rtx_LO_SUM (SImode, scratch, funexp)));
9079 else /* TARGET_ARCH64 */
9081 switch (sparc_cmodel)
9085 /* The destination can serve as a temporary. */
9086 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
9091 /* The destination cannot serve as a temporary. */
9092 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
9094 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
9097 emit_and_preserve (seq, spill_reg);
9105 emit_jump_insn (gen_indirect_jump (scratch));
9110 /* Run just enough of rest_of_compilation to get the insns emitted.
9111 There's not really enough bulk here to make other passes such as
9112 instruction scheduling worth while. Note that use_thunk calls
9113 assemble_start_function and assemble_end_function. */
9114 insn = get_insns ();
9115 insn_locators_initialize ();
9116 shorten_branches (insn);
9117 final_start_function (insn, file, 1);
9118 final (insn, file, 1);
9119 final_end_function ();
9121 reload_completed = 0;
9122 epilogue_completed = 0;
9126 /* Return true if sparc_output_mi_thunk would be able to output the
9127 assembler code for the thunk function specified by the arguments
9128 it is passed, and false otherwise. */
9130 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED,
9131 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9132 HOST_WIDE_INT vcall_offset,
9133 tree function ATTRIBUTE_UNUSED)
9135 /* Bound the loop used in the default method above. */
9136 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9139 /* How to allocate a 'struct machine_function'. */
9141 static struct machine_function *
9142 sparc_init_machine_status (void)
9144 return ggc_alloc_cleared (sizeof (struct machine_function));
9147 /* Locate some local-dynamic symbol still in use by this function
9148 so that we can print its name in local-dynamic base patterns. */
9151 get_some_local_dynamic_name (void)
9155 if (cfun->machine->some_ld_name)
9156 return cfun->machine->some_ld_name;
9158 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9160 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9161 return cfun->machine->some_ld_name;
9167 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9172 && GET_CODE (x) == SYMBOL_REF
9173 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9175 cfun->machine->some_ld_name = XSTR (x, 0);
9182 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
9183 This is called from dwarf2out.c to emit call frame instructions
9184 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
9186 sparc_dwarf_handle_frame_unspec (const char *label,
9187 rtx pattern ATTRIBUTE_UNUSED,
9188 int index ATTRIBUTE_UNUSED)
9190 gcc_assert (index == UNSPECV_SAVEW);
9191 dwarf2out_window_save (label);
9194 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9195 We need to emit DTP-relative relocations. */
9198 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9203 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9206 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9211 output_addr_const (file, x);
9216 void sparc_file_end (void)
9218 /* If we haven't emitted the special PIC helper function, do so now. */
9219 if (pic_helper_symbol_name[0] && !pic_helper_emitted_p)
9222 if (NEED_INDICATE_EXEC_STACK)
9223 file_end_indicate_exec_stack ();
9226 #include "gt-sparc.h"