1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs {
67 /* Integer signed load */
70 /* Integer zeroed load */
76 /* fmov, fneg, fabs */
80 const int float_plusminus;
86 const int float_cmove;
92 const int float_div_sf;
95 const int float_div_df;
98 const int float_sqrt_sf;
101 const int float_sqrt_df;
109 /* integer multiply cost for each bit set past the most
110 significant 3, so the formula for multiply cost becomes:
113 highest_bit = highest_clear_bit(rs1);
115 highest_bit = highest_set_bit(rs1);
118 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
120 A value of zero indicates that the multiply costs is fixed,
122 const int int_mul_bit_factor;
133 /* penalty for shifts, due to scheduling rules etc. */
134 const int shift_penalty;
138 struct processor_costs cypress_costs = {
139 COSTS_N_INSNS (2), /* int load */
140 COSTS_N_INSNS (2), /* int signed load */
141 COSTS_N_INSNS (2), /* int zeroed load */
142 COSTS_N_INSNS (2), /* float load */
143 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
144 COSTS_N_INSNS (5), /* fadd, fsub */
145 COSTS_N_INSNS (1), /* fcmp */
146 COSTS_N_INSNS (1), /* fmov, fmovr */
147 COSTS_N_INSNS (7), /* fmul */
148 COSTS_N_INSNS (37), /* fdivs */
149 COSTS_N_INSNS (37), /* fdivd */
150 COSTS_N_INSNS (63), /* fsqrts */
151 COSTS_N_INSNS (63), /* fsqrtd */
152 COSTS_N_INSNS (1), /* imul */
153 COSTS_N_INSNS (1), /* imulX */
154 0, /* imul bit factor */
155 COSTS_N_INSNS (1), /* idiv */
156 COSTS_N_INSNS (1), /* idivX */
157 COSTS_N_INSNS (1), /* movcc/movr */
158 0, /* shift penalty */
162 struct processor_costs supersparc_costs = {
163 COSTS_N_INSNS (1), /* int load */
164 COSTS_N_INSNS (1), /* int signed load */
165 COSTS_N_INSNS (1), /* int zeroed load */
166 COSTS_N_INSNS (0), /* float load */
167 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
168 COSTS_N_INSNS (3), /* fadd, fsub */
169 COSTS_N_INSNS (3), /* fcmp */
170 COSTS_N_INSNS (1), /* fmov, fmovr */
171 COSTS_N_INSNS (3), /* fmul */
172 COSTS_N_INSNS (6), /* fdivs */
173 COSTS_N_INSNS (9), /* fdivd */
174 COSTS_N_INSNS (12), /* fsqrts */
175 COSTS_N_INSNS (12), /* fsqrtd */
176 COSTS_N_INSNS (4), /* imul */
177 COSTS_N_INSNS (4), /* imulX */
178 0, /* imul bit factor */
179 COSTS_N_INSNS (4), /* idiv */
180 COSTS_N_INSNS (4), /* idivX */
181 COSTS_N_INSNS (1), /* movcc/movr */
182 1, /* shift penalty */
186 struct processor_costs hypersparc_costs = {
187 COSTS_N_INSNS (1), /* int load */
188 COSTS_N_INSNS (1), /* int signed load */
189 COSTS_N_INSNS (1), /* int zeroed load */
190 COSTS_N_INSNS (1), /* float load */
191 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
192 COSTS_N_INSNS (1), /* fadd, fsub */
193 COSTS_N_INSNS (1), /* fcmp */
194 COSTS_N_INSNS (1), /* fmov, fmovr */
195 COSTS_N_INSNS (1), /* fmul */
196 COSTS_N_INSNS (8), /* fdivs */
197 COSTS_N_INSNS (12), /* fdivd */
198 COSTS_N_INSNS (17), /* fsqrts */
199 COSTS_N_INSNS (17), /* fsqrtd */
200 COSTS_N_INSNS (17), /* imul */
201 COSTS_N_INSNS (17), /* imulX */
202 0, /* imul bit factor */
203 COSTS_N_INSNS (17), /* idiv */
204 COSTS_N_INSNS (17), /* idivX */
205 COSTS_N_INSNS (1), /* movcc/movr */
206 0, /* shift penalty */
210 struct processor_costs leon_costs = {
211 COSTS_N_INSNS (1), /* int load */
212 COSTS_N_INSNS (1), /* int signed load */
213 COSTS_N_INSNS (1), /* int zeroed load */
214 COSTS_N_INSNS (1), /* float load */
215 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
216 COSTS_N_INSNS (1), /* fadd, fsub */
217 COSTS_N_INSNS (1), /* fcmp */
218 COSTS_N_INSNS (1), /* fmov, fmovr */
219 COSTS_N_INSNS (1), /* fmul */
220 COSTS_N_INSNS (15), /* fdivs */
221 COSTS_N_INSNS (15), /* fdivd */
222 COSTS_N_INSNS (23), /* fsqrts */
223 COSTS_N_INSNS (23), /* fsqrtd */
224 COSTS_N_INSNS (5), /* imul */
225 COSTS_N_INSNS (5), /* imulX */
226 0, /* imul bit factor */
227 COSTS_N_INSNS (5), /* idiv */
228 COSTS_N_INSNS (5), /* idivX */
229 COSTS_N_INSNS (1), /* movcc/movr */
230 0, /* shift penalty */
234 struct processor_costs sparclet_costs = {
235 COSTS_N_INSNS (3), /* int load */
236 COSTS_N_INSNS (3), /* int signed load */
237 COSTS_N_INSNS (1), /* int zeroed load */
238 COSTS_N_INSNS (1), /* float load */
239 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
240 COSTS_N_INSNS (1), /* fadd, fsub */
241 COSTS_N_INSNS (1), /* fcmp */
242 COSTS_N_INSNS (1), /* fmov, fmovr */
243 COSTS_N_INSNS (1), /* fmul */
244 COSTS_N_INSNS (1), /* fdivs */
245 COSTS_N_INSNS (1), /* fdivd */
246 COSTS_N_INSNS (1), /* fsqrts */
247 COSTS_N_INSNS (1), /* fsqrtd */
248 COSTS_N_INSNS (5), /* imul */
249 COSTS_N_INSNS (5), /* imulX */
250 0, /* imul bit factor */
251 COSTS_N_INSNS (5), /* idiv */
252 COSTS_N_INSNS (5), /* idivX */
253 COSTS_N_INSNS (1), /* movcc/movr */
254 0, /* shift penalty */
258 struct processor_costs ultrasparc_costs = {
259 COSTS_N_INSNS (2), /* int load */
260 COSTS_N_INSNS (3), /* int signed load */
261 COSTS_N_INSNS (2), /* int zeroed load */
262 COSTS_N_INSNS (2), /* float load */
263 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
264 COSTS_N_INSNS (4), /* fadd, fsub */
265 COSTS_N_INSNS (1), /* fcmp */
266 COSTS_N_INSNS (2), /* fmov, fmovr */
267 COSTS_N_INSNS (4), /* fmul */
268 COSTS_N_INSNS (13), /* fdivs */
269 COSTS_N_INSNS (23), /* fdivd */
270 COSTS_N_INSNS (13), /* fsqrts */
271 COSTS_N_INSNS (23), /* fsqrtd */
272 COSTS_N_INSNS (4), /* imul */
273 COSTS_N_INSNS (4), /* imulX */
274 2, /* imul bit factor */
275 COSTS_N_INSNS (37), /* idiv */
276 COSTS_N_INSNS (68), /* idivX */
277 COSTS_N_INSNS (2), /* movcc/movr */
278 2, /* shift penalty */
282 struct processor_costs ultrasparc3_costs = {
283 COSTS_N_INSNS (2), /* int load */
284 COSTS_N_INSNS (3), /* int signed load */
285 COSTS_N_INSNS (3), /* int zeroed load */
286 COSTS_N_INSNS (2), /* float load */
287 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
288 COSTS_N_INSNS (4), /* fadd, fsub */
289 COSTS_N_INSNS (5), /* fcmp */
290 COSTS_N_INSNS (3), /* fmov, fmovr */
291 COSTS_N_INSNS (4), /* fmul */
292 COSTS_N_INSNS (17), /* fdivs */
293 COSTS_N_INSNS (20), /* fdivd */
294 COSTS_N_INSNS (20), /* fsqrts */
295 COSTS_N_INSNS (29), /* fsqrtd */
296 COSTS_N_INSNS (6), /* imul */
297 COSTS_N_INSNS (6), /* imulX */
298 0, /* imul bit factor */
299 COSTS_N_INSNS (40), /* idiv */
300 COSTS_N_INSNS (71), /* idivX */
301 COSTS_N_INSNS (2), /* movcc/movr */
302 0, /* shift penalty */
306 struct processor_costs niagara_costs = {
307 COSTS_N_INSNS (3), /* int load */
308 COSTS_N_INSNS (3), /* int signed load */
309 COSTS_N_INSNS (3), /* int zeroed load */
310 COSTS_N_INSNS (9), /* float load */
311 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
312 COSTS_N_INSNS (8), /* fadd, fsub */
313 COSTS_N_INSNS (26), /* fcmp */
314 COSTS_N_INSNS (8), /* fmov, fmovr */
315 COSTS_N_INSNS (29), /* fmul */
316 COSTS_N_INSNS (54), /* fdivs */
317 COSTS_N_INSNS (83), /* fdivd */
318 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
319 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
320 COSTS_N_INSNS (11), /* imul */
321 COSTS_N_INSNS (11), /* imulX */
322 0, /* imul bit factor */
323 COSTS_N_INSNS (72), /* idiv */
324 COSTS_N_INSNS (72), /* idivX */
325 COSTS_N_INSNS (1), /* movcc/movr */
326 0, /* shift penalty */
330 struct processor_costs niagara2_costs = {
331 COSTS_N_INSNS (3), /* int load */
332 COSTS_N_INSNS (3), /* int signed load */
333 COSTS_N_INSNS (3), /* int zeroed load */
334 COSTS_N_INSNS (3), /* float load */
335 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
336 COSTS_N_INSNS (6), /* fadd, fsub */
337 COSTS_N_INSNS (6), /* fcmp */
338 COSTS_N_INSNS (6), /* fmov, fmovr */
339 COSTS_N_INSNS (6), /* fmul */
340 COSTS_N_INSNS (19), /* fdivs */
341 COSTS_N_INSNS (33), /* fdivd */
342 COSTS_N_INSNS (19), /* fsqrts */
343 COSTS_N_INSNS (33), /* fsqrtd */
344 COSTS_N_INSNS (5), /* imul */
345 COSTS_N_INSNS (5), /* imulX */
346 0, /* imul bit factor */
347 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
348 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
349 COSTS_N_INSNS (1), /* movcc/movr */
350 0, /* shift penalty */
354 struct processor_costs niagara3_costs = {
355 COSTS_N_INSNS (3), /* int load */
356 COSTS_N_INSNS (3), /* int signed load */
357 COSTS_N_INSNS (3), /* int zeroed load */
358 COSTS_N_INSNS (3), /* float load */
359 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
360 COSTS_N_INSNS (9), /* fadd, fsub */
361 COSTS_N_INSNS (9), /* fcmp */
362 COSTS_N_INSNS (9), /* fmov, fmovr */
363 COSTS_N_INSNS (9), /* fmul */
364 COSTS_N_INSNS (23), /* fdivs */
365 COSTS_N_INSNS (37), /* fdivd */
366 COSTS_N_INSNS (23), /* fsqrts */
367 COSTS_N_INSNS (37), /* fsqrtd */
368 COSTS_N_INSNS (9), /* imul */
369 COSTS_N_INSNS (9), /* imulX */
370 0, /* imul bit factor */
371 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
372 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
373 COSTS_N_INSNS (1), /* movcc/movr */
374 0, /* shift penalty */
377 static const struct processor_costs *sparc_costs = &cypress_costs;
379 #ifdef HAVE_AS_RELAX_OPTION
380 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
381 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
382 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
383 somebody does not branch between the sethi and jmp. */
384 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
386 #define LEAF_SIBCALL_SLOT_RESERVED_P \
387 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
390 /* Vector to say how input registers are mapped to output registers.
391 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
392 eliminate it. You must use -fomit-frame-pointer to get that. */
393 char leaf_reg_remap[] =
394 { 0, 1, 2, 3, 4, 5, 6, 7,
395 -1, -1, -1, -1, -1, -1, 14, -1,
396 -1, -1, -1, -1, -1, -1, -1, -1,
397 8, 9, 10, 11, 12, 13, -1, 15,
399 32, 33, 34, 35, 36, 37, 38, 39,
400 40, 41, 42, 43, 44, 45, 46, 47,
401 48, 49, 50, 51, 52, 53, 54, 55,
402 56, 57, 58, 59, 60, 61, 62, 63,
403 64, 65, 66, 67, 68, 69, 70, 71,
404 72, 73, 74, 75, 76, 77, 78, 79,
405 80, 81, 82, 83, 84, 85, 86, 87,
406 88, 89, 90, 91, 92, 93, 94, 95,
407 96, 97, 98, 99, 100, 101, 102};
409 /* Vector, indexed by hard register number, which contains 1
410 for a register that is allowable in a candidate for leaf
411 function treatment. */
412 char sparc_leaf_regs[] =
413 { 1, 1, 1, 1, 1, 1, 1, 1,
414 0, 0, 0, 0, 0, 0, 1, 0,
415 0, 0, 0, 0, 0, 0, 0, 0,
416 1, 1, 1, 1, 1, 1, 0, 1,
417 1, 1, 1, 1, 1, 1, 1, 1,
418 1, 1, 1, 1, 1, 1, 1, 1,
419 1, 1, 1, 1, 1, 1, 1, 1,
420 1, 1, 1, 1, 1, 1, 1, 1,
421 1, 1, 1, 1, 1, 1, 1, 1,
422 1, 1, 1, 1, 1, 1, 1, 1,
423 1, 1, 1, 1, 1, 1, 1, 1,
424 1, 1, 1, 1, 1, 1, 1, 1,
425 1, 1, 1, 1, 1, 1, 1};
427 struct GTY(()) machine_function
429 /* Size of the frame of the function. */
430 HOST_WIDE_INT frame_size;
432 /* Size of the frame of the function minus the register window save area
433 and the outgoing argument area. */
434 HOST_WIDE_INT apparent_frame_size;
436 /* Register we pretend the frame pointer is allocated to. Normally, this
437 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
438 record "offset" separately as it may be too big for (reg + disp). */
440 HOST_WIDE_INT frame_base_offset;
442 /* Some local-dynamic TLS symbol name. */
443 const char *some_ld_name;
445 /* Number of global or FP registers to be saved (as 4-byte quantities). */
446 int n_global_fp_regs;
448 /* True if the current function is leaf and uses only leaf regs,
449 so that the SPARC leaf function optimization can be applied.
450 Private version of current_function_uses_only_leaf_regs, see
451 sparc_expand_prologue for the rationale. */
454 /* True if the prologue saves local or in registers. */
455 bool save_local_in_regs_p;
457 /* True if the data calculated by sparc_expand_prologue are valid. */
458 bool prologue_data_valid_p;
461 #define sparc_frame_size cfun->machine->frame_size
462 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
463 #define sparc_frame_base_reg cfun->machine->frame_base_reg
464 #define sparc_frame_base_offset cfun->machine->frame_base_offset
465 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
466 #define sparc_leaf_function_p cfun->machine->leaf_function_p
467 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
468 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
470 /* 1 if the next opcode is to be specially indented. */
471 int sparc_indent_opcode = 0;
473 static void sparc_option_override (void);
474 static void sparc_init_modes (void);
475 static void scan_record_type (const_tree, int *, int *, int *);
476 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
477 const_tree, bool, bool, int *, int *);
479 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
480 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
482 static void sparc_emit_set_const32 (rtx, rtx);
483 static void sparc_emit_set_const64 (rtx, rtx);
484 static void sparc_output_addr_vec (rtx);
485 static void sparc_output_addr_diff_vec (rtx);
486 static void sparc_output_deferred_case_vectors (void);
487 static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool);
488 static bool sparc_legitimate_constant_p (enum machine_mode, rtx);
489 static rtx sparc_builtin_saveregs (void);
490 static int epilogue_renumber (rtx *, int);
491 static bool sparc_assemble_integer (rtx, unsigned int, int);
492 static int set_extends (rtx);
493 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
494 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
495 #ifdef TARGET_SOLARIS
496 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
497 tree) ATTRIBUTE_UNUSED;
499 static int sparc_adjust_cost (rtx, rtx, rtx, int);
500 static int sparc_issue_rate (void);
501 static void sparc_sched_init (FILE *, int, int);
502 static int sparc_use_sched_lookahead (void);
504 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
505 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
506 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
507 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
508 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
510 static bool sparc_function_ok_for_sibcall (tree, tree);
511 static void sparc_init_libfuncs (void);
512 static void sparc_init_builtins (void);
513 static void sparc_vis_init_builtins (void);
514 static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
515 static tree sparc_fold_builtin (tree, int, tree *, bool);
516 static int sparc_vis_mul8x16 (int, int);
517 static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree);
518 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
519 HOST_WIDE_INT, tree);
520 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
521 HOST_WIDE_INT, const_tree);
522 static void sparc_reorg (void);
523 static struct machine_function * sparc_init_machine_status (void);
524 static bool sparc_cannot_force_const_mem (enum machine_mode, rtx);
525 static rtx sparc_tls_get_addr (void);
526 static rtx sparc_tls_got (void);
527 static const char *get_some_local_dynamic_name (void);
528 static int get_some_local_dynamic_name_1 (rtx *, void *);
529 static int sparc_register_move_cost (enum machine_mode,
530 reg_class_t, reg_class_t);
531 static bool sparc_rtx_costs (rtx, int, int, int, int *, bool);
532 static rtx sparc_function_value (const_tree, const_tree, bool);
533 static rtx sparc_libcall_value (enum machine_mode, const_rtx);
534 static bool sparc_function_value_regno_p (const unsigned int);
535 static rtx sparc_struct_value_rtx (tree, int);
536 static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode,
537 int *, const_tree, int);
538 static bool sparc_return_in_memory (const_tree, const_tree);
539 static bool sparc_strict_argument_naming (cumulative_args_t);
540 static void sparc_va_start (tree, rtx);
541 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
542 static bool sparc_vector_mode_supported_p (enum machine_mode);
543 static bool sparc_tls_referenced_p (rtx);
544 static rtx sparc_legitimize_tls_address (rtx);
545 static rtx sparc_legitimize_pic_address (rtx, rtx);
546 static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode);
547 static rtx sparc_delegitimize_address (rtx);
548 static bool sparc_mode_dependent_address_p (const_rtx);
549 static bool sparc_pass_by_reference (cumulative_args_t,
550 enum machine_mode, const_tree, bool);
551 static void sparc_function_arg_advance (cumulative_args_t,
552 enum machine_mode, const_tree, bool);
553 static rtx sparc_function_arg_1 (cumulative_args_t,
554 enum machine_mode, const_tree, bool, bool);
555 static rtx sparc_function_arg (cumulative_args_t,
556 enum machine_mode, const_tree, bool);
557 static rtx sparc_function_incoming_arg (cumulative_args_t,
558 enum machine_mode, const_tree, bool);
559 static unsigned int sparc_function_arg_boundary (enum machine_mode,
561 static int sparc_arg_partial_bytes (cumulative_args_t,
562 enum machine_mode, tree, bool);
563 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
564 static void sparc_file_end (void);
565 static bool sparc_frame_pointer_required (void);
566 static bool sparc_can_eliminate (const int, const int);
567 static rtx sparc_builtin_setjmp_frame_value (void);
568 static void sparc_conditional_register_usage (void);
569 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
570 static const char *sparc_mangle_type (const_tree);
572 static void sparc_trampoline_init (rtx, tree, rtx);
573 static enum machine_mode sparc_preferred_simd_mode (enum machine_mode);
574 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
575 static bool sparc_print_operand_punct_valid_p (unsigned char);
576 static void sparc_print_operand (FILE *, rtx, int);
577 static void sparc_print_operand_address (FILE *, rtx);
578 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
580 secondary_reload_info *);
582 #ifdef SUBTARGET_ATTRIBUTE_TABLE
583 /* Table of valid machine attributes. */
584 static const struct attribute_spec sparc_attribute_table[] =
586 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
588 SUBTARGET_ATTRIBUTE_TABLE,
589 { NULL, 0, 0, false, false, false, NULL, false }
593 /* Option handling. */
596 enum cmodel sparc_cmodel;
598 char sparc_hard_reg_printed[8];
600 /* Initialize the GCC target structure. */
602 /* The default is to use .half rather than .short for aligned HI objects. */
603 #undef TARGET_ASM_ALIGNED_HI_OP
604 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
606 #undef TARGET_ASM_UNALIGNED_HI_OP
607 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
608 #undef TARGET_ASM_UNALIGNED_SI_OP
609 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
610 #undef TARGET_ASM_UNALIGNED_DI_OP
611 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
613 /* The target hook has to handle DI-mode values. */
614 #undef TARGET_ASM_INTEGER
615 #define TARGET_ASM_INTEGER sparc_assemble_integer
617 #undef TARGET_ASM_FUNCTION_PROLOGUE
618 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
619 #undef TARGET_ASM_FUNCTION_EPILOGUE
620 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
622 #undef TARGET_SCHED_ADJUST_COST
623 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
624 #undef TARGET_SCHED_ISSUE_RATE
625 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
626 #undef TARGET_SCHED_INIT
627 #define TARGET_SCHED_INIT sparc_sched_init
628 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
629 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
631 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
632 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
634 #undef TARGET_INIT_LIBFUNCS
635 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
636 #undef TARGET_INIT_BUILTINS
637 #define TARGET_INIT_BUILTINS sparc_init_builtins
639 #undef TARGET_LEGITIMIZE_ADDRESS
640 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
641 #undef TARGET_DELEGITIMIZE_ADDRESS
642 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
643 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
644 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
646 #undef TARGET_EXPAND_BUILTIN
647 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
648 #undef TARGET_FOLD_BUILTIN
649 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
652 #undef TARGET_HAVE_TLS
653 #define TARGET_HAVE_TLS true
656 #undef TARGET_CANNOT_FORCE_CONST_MEM
657 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
659 #undef TARGET_ASM_OUTPUT_MI_THUNK
660 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
661 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
662 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
664 #undef TARGET_MACHINE_DEPENDENT_REORG
665 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
667 #undef TARGET_RTX_COSTS
668 #define TARGET_RTX_COSTS sparc_rtx_costs
669 #undef TARGET_ADDRESS_COST
670 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
671 #undef TARGET_REGISTER_MOVE_COST
672 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
674 #undef TARGET_PROMOTE_FUNCTION_MODE
675 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
677 #undef TARGET_FUNCTION_VALUE
678 #define TARGET_FUNCTION_VALUE sparc_function_value
679 #undef TARGET_LIBCALL_VALUE
680 #define TARGET_LIBCALL_VALUE sparc_libcall_value
681 #undef TARGET_FUNCTION_VALUE_REGNO_P
682 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
684 #undef TARGET_STRUCT_VALUE_RTX
685 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
686 #undef TARGET_RETURN_IN_MEMORY
687 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
688 #undef TARGET_MUST_PASS_IN_STACK
689 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
690 #undef TARGET_PASS_BY_REFERENCE
691 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
692 #undef TARGET_ARG_PARTIAL_BYTES
693 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
694 #undef TARGET_FUNCTION_ARG_ADVANCE
695 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
696 #undef TARGET_FUNCTION_ARG
697 #define TARGET_FUNCTION_ARG sparc_function_arg
698 #undef TARGET_FUNCTION_INCOMING_ARG
699 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
700 #undef TARGET_FUNCTION_ARG_BOUNDARY
701 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
703 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
704 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
705 #undef TARGET_STRICT_ARGUMENT_NAMING
706 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
708 #undef TARGET_EXPAND_BUILTIN_VA_START
709 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
710 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
711 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
713 #undef TARGET_VECTOR_MODE_SUPPORTED_P
714 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
716 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
717 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
719 #ifdef SUBTARGET_INSERT_ATTRIBUTES
720 #undef TARGET_INSERT_ATTRIBUTES
721 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
724 #ifdef SUBTARGET_ATTRIBUTE_TABLE
725 #undef TARGET_ATTRIBUTE_TABLE
726 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
729 #undef TARGET_RELAXED_ORDERING
730 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
732 #undef TARGET_OPTION_OVERRIDE
733 #define TARGET_OPTION_OVERRIDE sparc_option_override
735 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
736 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
737 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
740 #undef TARGET_ASM_FILE_END
741 #define TARGET_ASM_FILE_END sparc_file_end
743 #undef TARGET_FRAME_POINTER_REQUIRED
744 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
746 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
747 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
749 #undef TARGET_CAN_ELIMINATE
750 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
752 #undef TARGET_PREFERRED_RELOAD_CLASS
753 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
755 #undef TARGET_SECONDARY_RELOAD
756 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
758 #undef TARGET_CONDITIONAL_REGISTER_USAGE
759 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
761 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
762 #undef TARGET_MANGLE_TYPE
763 #define TARGET_MANGLE_TYPE sparc_mangle_type
766 #undef TARGET_LEGITIMATE_ADDRESS_P
767 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
769 #undef TARGET_LEGITIMATE_CONSTANT_P
770 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
772 #undef TARGET_TRAMPOLINE_INIT
773 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
775 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
776 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
777 #undef TARGET_PRINT_OPERAND
778 #define TARGET_PRINT_OPERAND sparc_print_operand
779 #undef TARGET_PRINT_OPERAND_ADDRESS
780 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
782 /* The value stored by LDSTUB. */
783 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
784 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
786 struct gcc_target targetm = TARGET_INITIALIZER;
789 dump_target_flag_bits (const int flags)
791 if (flags & MASK_64BIT)
792 fprintf (stderr, "64BIT ");
793 if (flags & MASK_APP_REGS)
794 fprintf (stderr, "APP_REGS ");
795 if (flags & MASK_FASTER_STRUCTS)
796 fprintf (stderr, "FASTER_STRUCTS ");
797 if (flags & MASK_FLAT)
798 fprintf (stderr, "FLAT ");
799 if (flags & MASK_FMAF)
800 fprintf (stderr, "FMAF ");
801 if (flags & MASK_FPU)
802 fprintf (stderr, "FPU ");
803 if (flags & MASK_HARD_QUAD)
804 fprintf (stderr, "HARD_QUAD ");
805 if (flags & MASK_POPC)
806 fprintf (stderr, "POPC ");
807 if (flags & MASK_PTR64)
808 fprintf (stderr, "PTR64 ");
809 if (flags & MASK_STACK_BIAS)
810 fprintf (stderr, "STACK_BIAS ");
811 if (flags & MASK_UNALIGNED_DOUBLES)
812 fprintf (stderr, "UNALIGNED_DOUBLES ");
813 if (flags & MASK_V8PLUS)
814 fprintf (stderr, "V8PLUS ");
815 if (flags & MASK_VIS)
816 fprintf (stderr, "VIS ");
817 if (flags & MASK_VIS2)
818 fprintf (stderr, "VIS2 ");
819 if (flags & MASK_VIS3)
820 fprintf (stderr, "VIS3 ");
821 if (flags & MASK_DEPRECATED_V8_INSNS)
822 fprintf (stderr, "DEPRECATED_V8_INSNS ");
823 if (flags & MASK_SPARCLET)
824 fprintf (stderr, "SPARCLET ");
825 if (flags & MASK_SPARCLITE)
826 fprintf (stderr, "SPARCLITE ");
828 fprintf (stderr, "V8 ");
830 fprintf (stderr, "V9 ");
834 dump_target_flags (const char *prefix, const int flags)
836 fprintf (stderr, "%s: (%08x) [ ", prefix, flags);
837 dump_target_flag_bits (flags);
838 fprintf(stderr, "]\n");
841 /* Validate and override various options, and do some machine dependent
845 sparc_option_override (void)
847 static struct code_model {
848 const char *const name;
849 const enum cmodel value;
850 } const cmodels[] = {
852 { "medlow", CM_MEDLOW },
853 { "medmid", CM_MEDMID },
854 { "medany", CM_MEDANY },
855 { "embmedany", CM_EMBMEDANY },
856 { NULL, (enum cmodel) 0 }
858 const struct code_model *cmodel;
859 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
860 static struct cpu_default {
862 const enum processor_type processor;
863 } const cpu_default[] = {
864 /* There must be one entry here for each TARGET_CPU value. */
865 { TARGET_CPU_sparc, PROCESSOR_CYPRESS },
866 { TARGET_CPU_v8, PROCESSOR_V8 },
867 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC },
868 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
869 { TARGET_CPU_leon, PROCESSOR_LEON },
870 { TARGET_CPU_sparclite, PROCESSOR_F930 },
871 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
872 { TARGET_CPU_sparclet, PROCESSOR_TSC701 },
873 { TARGET_CPU_v9, PROCESSOR_V9 },
874 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC },
875 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 },
876 { TARGET_CPU_niagara, PROCESSOR_NIAGARA },
877 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 },
878 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
879 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
882 const struct cpu_default *def;
883 /* Table of values for -m{cpu,tune}=. This must match the order of
884 the PROCESSOR_* enumeration. */
885 static struct cpu_table {
886 const char *const name;
889 } const cpu_table[] = {
890 { "v7", MASK_ISA, 0 },
891 { "cypress", MASK_ISA, 0 },
892 { "v8", MASK_ISA, MASK_V8 },
893 /* TI TMS390Z55 supersparc */
894 { "supersparc", MASK_ISA, MASK_V8 },
895 { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
897 { "leon", MASK_ISA, MASK_V8|MASK_FPU },
898 { "sparclite", MASK_ISA, MASK_SPARCLITE },
899 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
900 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
901 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
902 { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
903 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
904 { "sparclet", MASK_ISA, MASK_SPARCLET },
906 { "tsc701", MASK_ISA, MASK_SPARCLET },
907 { "v9", MASK_ISA, MASK_V9 },
908 /* UltraSPARC I, II, IIi */
909 { "ultrasparc", MASK_ISA,
910 /* Although insns using %y are deprecated, it is a clear win. */
911 MASK_V9|MASK_DEPRECATED_V8_INSNS },
913 /* ??? Check if %y issue still holds true. */
914 { "ultrasparc3", MASK_ISA,
915 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 },
917 { "niagara", MASK_ISA,
918 MASK_V9|MASK_DEPRECATED_V8_INSNS },
920 { "niagara2", MASK_ISA,
921 MASK_V9|MASK_POPC|MASK_VIS2 },
923 { "niagara3", MASK_ISA,
924 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
926 { "niagara4", MASK_ISA,
927 MASK_V9|MASK_POPC|MASK_VIS2|MASK_VIS3|MASK_FMAF },
929 const struct cpu_table *cpu;
933 if (sparc_debug_string != NULL)
938 p = ASTRDUP (sparc_debug_string);
939 while ((q = strtok (p, ",")) != NULL)
953 if (! strcmp (q, "all"))
954 mask = MASK_DEBUG_ALL;
955 else if (! strcmp (q, "options"))
956 mask = MASK_DEBUG_OPTIONS;
958 error ("unknown -mdebug-%s switch", q);
961 sparc_debug &= ~mask;
967 if (TARGET_DEBUG_OPTIONS)
969 dump_target_flags("Initial target_flags", target_flags);
970 dump_target_flags("target_flags_explicit", target_flags_explicit);
973 #ifdef SUBTARGET_OVERRIDE_OPTIONS
974 SUBTARGET_OVERRIDE_OPTIONS;
977 #ifndef SPARC_BI_ARCH
978 /* Check for unsupported architecture size. */
979 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
980 error ("%s is not supported by this configuration",
981 DEFAULT_ARCH32_P ? "-m64" : "-m32");
984 /* We force all 64bit archs to use 128 bit long double */
985 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
987 error ("-mlong-double-64 not allowed with -m64");
988 target_flags |= MASK_LONG_DOUBLE_128;
991 /* Code model selection. */
992 sparc_cmodel = SPARC_DEFAULT_CMODEL;
996 sparc_cmodel = CM_32;
999 if (sparc_cmodel_string != NULL)
1003 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
1004 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
1006 if (cmodel->name == NULL)
1007 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
1009 sparc_cmodel = cmodel->value;
1012 error ("-mcmodel= is not supported on 32 bit systems");
1015 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1016 for (i = 8; i < 16; i++)
1017 if (!call_used_regs [i])
1019 error ("-fcall-saved-REG is not supported for out registers");
1020 call_used_regs [i] = 1;
1023 fpu = target_flags & MASK_FPU; /* save current -mfpu status */
1025 /* Set the default CPU. */
1026 if (!global_options_set.x_sparc_cpu_and_features)
1028 for (def = &cpu_default[0]; def->cpu != -1; ++def)
1029 if (def->cpu == TARGET_CPU_DEFAULT)
1031 gcc_assert (def->cpu != -1);
1032 sparc_cpu_and_features = def->processor;
1035 if (!global_options_set.x_sparc_cpu)
1036 sparc_cpu = sparc_cpu_and_features;
1038 cpu = &cpu_table[(int) sparc_cpu_and_features];
1040 if (TARGET_DEBUG_OPTIONS)
1042 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
1043 fprintf (stderr, "sparc_cpu: %s\n",
1044 cpu_table[(int) sparc_cpu].name);
1045 dump_target_flags ("cpu->disable", cpu->disable);
1046 dump_target_flags ("cpu->enable", cpu->enable);
1049 target_flags &= ~cpu->disable;
1050 target_flags |= (cpu->enable
1051 #ifndef HAVE_AS_FMAF_HPC_VIS3
1052 & ~(MASK_FMAF | MASK_VIS3)
1056 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1057 the processor default. */
1058 if (target_flags_explicit & MASK_FPU)
1059 target_flags = (target_flags & ~MASK_FPU) | fpu;
1061 /* -mvis2 implies -mvis */
1063 target_flags |= MASK_VIS;
1065 /* -mvis3 implies -mvis2 and -mvis */
1067 target_flags |= MASK_VIS2 | MASK_VIS;
1069 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
1071 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_FMAF);
1073 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1075 -m64 also implies v9. */
1076 if (TARGET_VIS || TARGET_ARCH64)
1078 target_flags |= MASK_V9;
1079 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
1082 /* -mvis also implies -mv8plus on 32-bit */
1083 if (TARGET_VIS && ! TARGET_ARCH64)
1084 target_flags |= MASK_V8PLUS;
1086 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1087 if (TARGET_V9 && TARGET_ARCH32)
1088 target_flags |= MASK_DEPRECATED_V8_INSNS;
1090 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1091 if (! TARGET_V9 || TARGET_ARCH64)
1092 target_flags &= ~MASK_V8PLUS;
1094 /* Don't use stack biasing in 32 bit mode. */
1096 target_flags &= ~MASK_STACK_BIAS;
1098 /* Supply a default value for align_functions. */
1099 if (align_functions == 0
1100 && (sparc_cpu == PROCESSOR_ULTRASPARC
1101 || sparc_cpu == PROCESSOR_ULTRASPARC3
1102 || sparc_cpu == PROCESSOR_NIAGARA
1103 || sparc_cpu == PROCESSOR_NIAGARA2
1104 || sparc_cpu == PROCESSOR_NIAGARA3
1105 || sparc_cpu == PROCESSOR_NIAGARA4))
1106 align_functions = 32;
1108 /* Validate PCC_STRUCT_RETURN. */
1109 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
1110 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
1112 /* Only use .uaxword when compiling for a 64-bit target. */
1114 targetm.asm_out.unaligned_op.di = NULL;
1116 /* Do various machine dependent initializations. */
1117 sparc_init_modes ();
1119 /* Set up function hooks. */
1120 init_machine_status = sparc_init_machine_status;
1125 case PROCESSOR_CYPRESS:
1126 sparc_costs = &cypress_costs;
1129 case PROCESSOR_SPARCLITE:
1130 case PROCESSOR_SUPERSPARC:
1131 sparc_costs = &supersparc_costs;
1133 case PROCESSOR_F930:
1134 case PROCESSOR_F934:
1135 case PROCESSOR_HYPERSPARC:
1136 case PROCESSOR_SPARCLITE86X:
1137 sparc_costs = &hypersparc_costs;
1139 case PROCESSOR_LEON:
1140 sparc_costs = &leon_costs;
1142 case PROCESSOR_SPARCLET:
1143 case PROCESSOR_TSC701:
1144 sparc_costs = &sparclet_costs;
1147 case PROCESSOR_ULTRASPARC:
1148 sparc_costs = &ultrasparc_costs;
1150 case PROCESSOR_ULTRASPARC3:
1151 sparc_costs = &ultrasparc3_costs;
1153 case PROCESSOR_NIAGARA:
1154 sparc_costs = &niagara_costs;
1156 case PROCESSOR_NIAGARA2:
1157 sparc_costs = &niagara2_costs;
1159 case PROCESSOR_NIAGARA3:
1160 case PROCESSOR_NIAGARA4:
1161 sparc_costs = &niagara3_costs;
1163 case PROCESSOR_NATIVE:
1167 if (sparc_memory_model == SMM_DEFAULT)
1169 /* Choose the memory model for the operating system. */
1170 enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL;
1171 if (os_default != SMM_DEFAULT)
1172 sparc_memory_model = os_default;
1173 /* Choose the most relaxed model for the processor. */
1175 sparc_memory_model = SMM_RMO;
1177 sparc_memory_model = SMM_PSO;
1179 sparc_memory_model = SMM_SC;
1182 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1183 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1184 target_flags |= MASK_LONG_DOUBLE_128;
1187 if (TARGET_DEBUG_OPTIONS)
1188 dump_target_flags ("Final target_flags", target_flags);
1190 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
1191 ((sparc_cpu == PROCESSOR_ULTRASPARC
1192 || sparc_cpu == PROCESSOR_NIAGARA
1193 || sparc_cpu == PROCESSOR_NIAGARA2
1194 || sparc_cpu == PROCESSOR_NIAGARA3
1195 || sparc_cpu == PROCESSOR_NIAGARA4)
1197 : (sparc_cpu == PROCESSOR_ULTRASPARC3
1199 global_options.x_param_values,
1200 global_options_set.x_param_values);
1201 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
1202 ((sparc_cpu == PROCESSOR_ULTRASPARC
1203 || sparc_cpu == PROCESSOR_ULTRASPARC3
1204 || sparc_cpu == PROCESSOR_NIAGARA
1205 || sparc_cpu == PROCESSOR_NIAGARA2
1206 || sparc_cpu == PROCESSOR_NIAGARA3
1207 || sparc_cpu == PROCESSOR_NIAGARA4)
1209 global_options.x_param_values,
1210 global_options_set.x_param_values);
1212 /* Disable save slot sharing for call-clobbered registers by default.
1213 The IRA sharing algorithm works on single registers only and this
1214 pessimizes for double floating-point registers. */
1215 if (!global_options_set.x_flag_ira_share_save_slots)
1216 flag_ira_share_save_slots = 0;
1219 /* Miscellaneous utilities. */
1221 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1222 or branch on register contents instructions. */
1225 v9_regcmp_p (enum rtx_code code)
1227 return (code == EQ || code == NE || code == GE || code == LT
1228 || code == LE || code == GT);
1231 /* Nonzero if OP is a floating point constant which can
1232 be loaded into an integer register using a single
1233 sethi instruction. */
1238 if (GET_CODE (op) == CONST_DOUBLE)
1243 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1244 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1245 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i);
1251 /* Nonzero if OP is a floating point constant which can
1252 be loaded into an integer register using a single
1258 if (GET_CODE (op) == CONST_DOUBLE)
1263 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1264 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1265 return SPARC_SIMM13_P (i);
1271 /* Nonzero if OP is a floating point constant which can
1272 be loaded into an integer register using a high/losum
1273 instruction sequence. */
1276 fp_high_losum_p (rtx op)
1278 /* The constraints calling this should only be in
1279 SFmode move insns, so any constant which cannot
1280 be moved using a single insn will do. */
1281 if (GET_CODE (op) == CONST_DOUBLE)
1286 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
1287 REAL_VALUE_TO_TARGET_SINGLE (r, i);
1288 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i);
1294 /* Return true if the address of LABEL can be loaded by means of the
1295 mov{si,di}_pic_label_ref patterns in PIC mode. */
1298 can_use_mov_pic_label_ref (rtx label)
1300 /* VxWorks does not impose a fixed gap between segments; the run-time
1301 gap can be different from the object-file gap. We therefore can't
1302 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1303 are absolutely sure that X is in the same segment as the GOT.
1304 Unfortunately, the flexibility of linker scripts means that we
1305 can't be sure of that in general, so assume that GOT-relative
1306 accesses are never valid on VxWorks. */
1307 if (TARGET_VXWORKS_RTP)
1310 /* Similarly, if the label is non-local, it might end up being placed
1311 in a different section than the current one; now mov_pic_label_ref
1312 requires the label and the code to be in the same section. */
1313 if (LABEL_REF_NONLOCAL_P (label))
1316 /* Finally, if we are reordering basic blocks and partition into hot
1317 and cold sections, this might happen for any label. */
1318 if (flag_reorder_blocks_and_partition)
1324 /* Expand a move instruction. Return true if all work is done. */
1327 sparc_expand_move (enum machine_mode mode, rtx *operands)
1329 /* Handle sets of MEM first. */
1330 if (GET_CODE (operands[0]) == MEM)
1332 /* 0 is a register (or a pair of registers) on SPARC. */
1333 if (register_or_zero_operand (operands[1], mode))
1336 if (!reload_in_progress)
1338 operands[0] = validize_mem (operands[0]);
1339 operands[1] = force_reg (mode, operands[1]);
1343 /* Fixup TLS cases. */
1345 && CONSTANT_P (operands[1])
1346 && sparc_tls_referenced_p (operands [1]))
1348 operands[1] = sparc_legitimize_tls_address (operands[1]);
1352 /* Fixup PIC cases. */
1353 if (flag_pic && CONSTANT_P (operands[1]))
1355 if (pic_address_needs_scratch (operands[1]))
1356 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
1358 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1359 if (GET_CODE (operands[1]) == LABEL_REF
1360 && can_use_mov_pic_label_ref (operands[1]))
1364 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1370 gcc_assert (TARGET_ARCH64);
1371 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
1376 if (symbolic_operand (operands[1], mode))
1379 = sparc_legitimize_pic_address (operands[1],
1381 ? operands[0] : NULL_RTX);
1386 /* If we are trying to toss an integer constant into FP registers,
1387 or loading a FP or vector constant, force it into memory. */
1388 if (CONSTANT_P (operands[1])
1389 && REG_P (operands[0])
1390 && (SPARC_FP_REG_P (REGNO (operands[0]))
1391 || SCALAR_FLOAT_MODE_P (mode)
1392 || VECTOR_MODE_P (mode)))
1394 /* emit_group_store will send such bogosity to us when it is
1395 not storing directly into memory. So fix this up to avoid
1396 crashes in output_constant_pool. */
1397 if (operands [1] == const0_rtx)
1398 operands[1] = CONST0_RTX (mode);
1400 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1401 always other regs. */
1402 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1403 && (const_zero_operand (operands[1], mode)
1404 || const_all_ones_operand (operands[1], mode)))
1407 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1408 /* We are able to build any SF constant in integer registers
1409 with at most 2 instructions. */
1411 /* And any DF constant in integer registers. */
1413 && ! can_create_pseudo_p ())))
1416 operands[1] = force_const_mem (mode, operands[1]);
1417 if (!reload_in_progress)
1418 operands[1] = validize_mem (operands[1]);
1422 /* Accept non-constants and valid constants unmodified. */
1423 if (!CONSTANT_P (operands[1])
1424 || GET_CODE (operands[1]) == HIGH
1425 || input_operand (operands[1], mode))
1431 /* All QImode constants require only one insn, so proceed. */
1436 sparc_emit_set_const32 (operands[0], operands[1]);
1440 /* input_operand should have filtered out 32-bit mode. */
1441 sparc_emit_set_const64 (operands[0], operands[1]);
1451 /* Load OP1, a 32-bit constant, into OP0, a register.
1452 We know it can't be done in one insn when we get
1453 here, the move expander guarantees this. */
1456 sparc_emit_set_const32 (rtx op0, rtx op1)
1458 enum machine_mode mode = GET_MODE (op0);
1461 if (can_create_pseudo_p ())
1462 temp = gen_reg_rtx (mode);
1464 if (GET_CODE (op1) == CONST_INT)
1466 gcc_assert (!small_int_operand (op1, mode)
1467 && !const_high_operand (op1, mode));
1469 /* Emit them as real moves instead of a HIGH/LO_SUM,
1470 this way CSE can see everything and reuse intermediate
1471 values if it wants. */
1472 emit_insn (gen_rtx_SET (VOIDmode, temp,
1473 GEN_INT (INTVAL (op1)
1474 & ~(HOST_WIDE_INT)0x3ff)));
1476 emit_insn (gen_rtx_SET (VOIDmode,
1478 gen_rtx_IOR (mode, temp,
1479 GEN_INT (INTVAL (op1) & 0x3ff))));
1483 /* A symbol, emit in the traditional way. */
1484 emit_insn (gen_rtx_SET (VOIDmode, temp,
1485 gen_rtx_HIGH (mode, op1)));
1486 emit_insn (gen_rtx_SET (VOIDmode,
1487 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1491 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1492 If TEMP is nonzero, we are forbidden to use any other scratch
1493 registers. Otherwise, we are allowed to generate them as needed.
1495 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1496 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1499 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1501 rtx temp1, temp2, temp3, temp4, temp5;
1504 if (temp && GET_MODE (temp) == TImode)
1507 temp = gen_rtx_REG (DImode, REGNO (temp));
1510 /* SPARC-V9 code-model support. */
1511 switch (sparc_cmodel)
1514 /* The range spanned by all instructions in the object is less
1515 than 2^31 bytes (2GB) and the distance from any instruction
1516 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1517 than 2^31 bytes (2GB).
1519 The executable must be in the low 4TB of the virtual address
1522 sethi %hi(symbol), %temp1
1523 or %temp1, %lo(symbol), %reg */
1525 temp1 = temp; /* op0 is allowed. */
1527 temp1 = gen_reg_rtx (DImode);
1529 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1530 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1534 /* The range spanned by all instructions in the object is less
1535 than 2^31 bytes (2GB) and the distance from any instruction
1536 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1537 than 2^31 bytes (2GB).
1539 The executable must be in the low 16TB of the virtual address
1542 sethi %h44(symbol), %temp1
1543 or %temp1, %m44(symbol), %temp2
1544 sllx %temp2, 12, %temp3
1545 or %temp3, %l44(symbol), %reg */
1550 temp3 = temp; /* op0 is allowed. */
1554 temp1 = gen_reg_rtx (DImode);
1555 temp2 = gen_reg_rtx (DImode);
1556 temp3 = gen_reg_rtx (DImode);
1559 emit_insn (gen_seth44 (temp1, op1));
1560 emit_insn (gen_setm44 (temp2, temp1, op1));
1561 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1562 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1563 emit_insn (gen_setl44 (op0, temp3, op1));
1567 /* The range spanned by all instructions in the object is less
1568 than 2^31 bytes (2GB) and the distance from any instruction
1569 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1570 than 2^31 bytes (2GB).
1572 The executable can be placed anywhere in the virtual address
1575 sethi %hh(symbol), %temp1
1576 sethi %lm(symbol), %temp2
1577 or %temp1, %hm(symbol), %temp3
1578 sllx %temp3, 32, %temp4
1579 or %temp4, %temp2, %temp5
1580 or %temp5, %lo(symbol), %reg */
1583 /* It is possible that one of the registers we got for operands[2]
1584 might coincide with that of operands[0] (which is why we made
1585 it TImode). Pick the other one to use as our scratch. */
1586 if (rtx_equal_p (temp, op0))
1588 gcc_assert (ti_temp);
1589 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1592 temp2 = temp; /* op0 is _not_ allowed, see above. */
1599 temp1 = gen_reg_rtx (DImode);
1600 temp2 = gen_reg_rtx (DImode);
1601 temp3 = gen_reg_rtx (DImode);
1602 temp4 = gen_reg_rtx (DImode);
1603 temp5 = gen_reg_rtx (DImode);
1606 emit_insn (gen_sethh (temp1, op1));
1607 emit_insn (gen_setlm (temp2, op1));
1608 emit_insn (gen_sethm (temp3, temp1, op1));
1609 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1610 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1611 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1612 gen_rtx_PLUS (DImode, temp4, temp2)));
1613 emit_insn (gen_setlo (op0, temp5, op1));
1617 /* Old old old backwards compatibility kruft here.
1618 Essentially it is MEDLOW with a fixed 64-bit
1619 virtual base added to all data segment addresses.
1620 Text-segment stuff is computed like MEDANY, we can't
1621 reuse the code above because the relocation knobs
1624 Data segment: sethi %hi(symbol), %temp1
1625 add %temp1, EMBMEDANY_BASE_REG, %temp2
1626 or %temp2, %lo(symbol), %reg */
1627 if (data_segment_operand (op1, GET_MODE (op1)))
1631 temp1 = temp; /* op0 is allowed. */
1636 temp1 = gen_reg_rtx (DImode);
1637 temp2 = gen_reg_rtx (DImode);
1640 emit_insn (gen_embmedany_sethi (temp1, op1));
1641 emit_insn (gen_embmedany_brsum (temp2, temp1));
1642 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1645 /* Text segment: sethi %uhi(symbol), %temp1
1646 sethi %hi(symbol), %temp2
1647 or %temp1, %ulo(symbol), %temp3
1648 sllx %temp3, 32, %temp4
1649 or %temp4, %temp2, %temp5
1650 or %temp5, %lo(symbol), %reg */
1655 /* It is possible that one of the registers we got for operands[2]
1656 might coincide with that of operands[0] (which is why we made
1657 it TImode). Pick the other one to use as our scratch. */
1658 if (rtx_equal_p (temp, op0))
1660 gcc_assert (ti_temp);
1661 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1664 temp2 = temp; /* op0 is _not_ allowed, see above. */
1671 temp1 = gen_reg_rtx (DImode);
1672 temp2 = gen_reg_rtx (DImode);
1673 temp3 = gen_reg_rtx (DImode);
1674 temp4 = gen_reg_rtx (DImode);
1675 temp5 = gen_reg_rtx (DImode);
1678 emit_insn (gen_embmedany_textuhi (temp1, op1));
1679 emit_insn (gen_embmedany_texthi (temp2, op1));
1680 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1681 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1682 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1683 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1684 gen_rtx_PLUS (DImode, temp4, temp2)));
1685 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1694 #if HOST_BITS_PER_WIDE_INT == 32
1696 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED)
1701 /* These avoid problems when cross compiling. If we do not
1702 go through all this hair then the optimizer will see
1703 invalid REG_EQUAL notes or in some cases none at all. */
1704 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT);
1705 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1706 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1707 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1709 /* The optimizer is not to assume anything about exactly
1710 which bits are set for a HIGH, they are unspecified.
1711 Unfortunately this leads to many missed optimizations
1712 during CSE. We mask out the non-HIGH bits, and matches
1713 a plain movdi, to alleviate this problem. */
1715 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1717 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff));
1721 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1723 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val));
1727 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1729 return gen_rtx_IOR (DImode, src, GEN_INT (val));
1733 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1735 return gen_rtx_XOR (DImode, src, GEN_INT (val));
1738 /* Worker routines for 64-bit constant formation on arch64.
1739 One of the key things to be doing in these emissions is
1740 to create as many temp REGs as possible. This makes it
1741 possible for half-built constants to be used later when
1742 such values are similar to something required later on.
1743 Without doing this, the optimizer cannot see such
1746 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1747 unsigned HOST_WIDE_INT, int);
1750 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1751 unsigned HOST_WIDE_INT low_bits, int is_neg)
1753 unsigned HOST_WIDE_INT high_bits;
1756 high_bits = (~low_bits) & 0xffffffff;
1758 high_bits = low_bits;
1760 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1763 emit_insn (gen_rtx_SET (VOIDmode, op0,
1764 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1768 /* If we are XOR'ing with -1, then we should emit a one's complement
1769 instead. This way the combiner will notice logical operations
1770 such as ANDN later on and substitute. */
1771 if ((low_bits & 0x3ff) == 0x3ff)
1773 emit_insn (gen_rtx_SET (VOIDmode, op0,
1774 gen_rtx_NOT (DImode, temp)));
1778 emit_insn (gen_rtx_SET (VOIDmode, op0,
1779 gen_safe_XOR64 (temp,
1780 (-(HOST_WIDE_INT)0x400
1781 | (low_bits & 0x3ff)))));
1786 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1787 unsigned HOST_WIDE_INT, int);
1790 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1791 unsigned HOST_WIDE_INT high_bits,
1792 unsigned HOST_WIDE_INT low_immediate,
1797 if ((high_bits & 0xfffffc00) != 0)
1799 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1800 if ((high_bits & ~0xfffffc00) != 0)
1801 emit_insn (gen_rtx_SET (VOIDmode, op0,
1802 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1808 emit_insn (gen_safe_SET64 (temp, high_bits));
1812 /* Now shift it up into place. */
1813 emit_insn (gen_rtx_SET (VOIDmode, op0,
1814 gen_rtx_ASHIFT (DImode, temp2,
1815 GEN_INT (shift_count))));
1817 /* If there is a low immediate part piece, finish up by
1818 putting that in as well. */
1819 if (low_immediate != 0)
1820 emit_insn (gen_rtx_SET (VOIDmode, op0,
1821 gen_safe_OR64 (op0, low_immediate)));
1824 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1825 unsigned HOST_WIDE_INT);
1827 /* Full 64-bit constant decomposition. Even though this is the
1828 'worst' case, we still optimize a few things away. */
1830 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1831 unsigned HOST_WIDE_INT high_bits,
1832 unsigned HOST_WIDE_INT low_bits)
1836 if (can_create_pseudo_p ())
1837 sub_temp = gen_reg_rtx (DImode);
1839 if ((high_bits & 0xfffffc00) != 0)
1841 emit_insn (gen_safe_HIGH64 (temp, high_bits));
1842 if ((high_bits & ~0xfffffc00) != 0)
1843 emit_insn (gen_rtx_SET (VOIDmode,
1845 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1851 emit_insn (gen_safe_SET64 (temp, high_bits));
1855 if (can_create_pseudo_p ())
1857 rtx temp2 = gen_reg_rtx (DImode);
1858 rtx temp3 = gen_reg_rtx (DImode);
1859 rtx temp4 = gen_reg_rtx (DImode);
1861 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1862 gen_rtx_ASHIFT (DImode, sub_temp,
1865 emit_insn (gen_safe_HIGH64 (temp2, low_bits));
1866 if ((low_bits & ~0xfffffc00) != 0)
1868 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1869 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1870 emit_insn (gen_rtx_SET (VOIDmode, op0,
1871 gen_rtx_PLUS (DImode, temp4, temp3)));
1875 emit_insn (gen_rtx_SET (VOIDmode, op0,
1876 gen_rtx_PLUS (DImode, temp4, temp2)));
1881 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1882 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1883 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1886 /* We are in the middle of reload, so this is really
1887 painful. However we do still make an attempt to
1888 avoid emitting truly stupid code. */
1889 if (low1 != const0_rtx)
1891 emit_insn (gen_rtx_SET (VOIDmode, op0,
1892 gen_rtx_ASHIFT (DImode, sub_temp,
1893 GEN_INT (to_shift))));
1894 emit_insn (gen_rtx_SET (VOIDmode, op0,
1895 gen_rtx_IOR (DImode, op0, low1)));
1903 if (low2 != const0_rtx)
1905 emit_insn (gen_rtx_SET (VOIDmode, op0,
1906 gen_rtx_ASHIFT (DImode, sub_temp,
1907 GEN_INT (to_shift))));
1908 emit_insn (gen_rtx_SET (VOIDmode, op0,
1909 gen_rtx_IOR (DImode, op0, low2)));
1917 emit_insn (gen_rtx_SET (VOIDmode, op0,
1918 gen_rtx_ASHIFT (DImode, sub_temp,
1919 GEN_INT (to_shift))));
1920 if (low3 != const0_rtx)
1921 emit_insn (gen_rtx_SET (VOIDmode, op0,
1922 gen_rtx_IOR (DImode, op0, low3)));
1927 /* Analyze a 64-bit constant for certain properties. */
1928 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1929 unsigned HOST_WIDE_INT,
1930 int *, int *, int *);
1933 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1934 unsigned HOST_WIDE_INT low_bits,
1935 int *hbsp, int *lbsp, int *abbasp)
1937 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1940 lowest_bit_set = highest_bit_set = -1;
1944 if ((lowest_bit_set == -1)
1945 && ((low_bits >> i) & 1))
1947 if ((highest_bit_set == -1)
1948 && ((high_bits >> (32 - i - 1)) & 1))
1949 highest_bit_set = (64 - i - 1);
1952 && ((highest_bit_set == -1)
1953 || (lowest_bit_set == -1)));
1959 if ((lowest_bit_set == -1)
1960 && ((high_bits >> i) & 1))
1961 lowest_bit_set = i + 32;
1962 if ((highest_bit_set == -1)
1963 && ((low_bits >> (32 - i - 1)) & 1))
1964 highest_bit_set = 32 - i - 1;
1967 && ((highest_bit_set == -1)
1968 || (lowest_bit_set == -1)));
1970 /* If there are no bits set this should have gone out
1971 as one instruction! */
1972 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1);
1973 all_bits_between_are_set = 1;
1974 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1978 if ((low_bits & (1 << i)) != 0)
1983 if ((high_bits & (1 << (i - 32))) != 0)
1986 all_bits_between_are_set = 0;
1989 *hbsp = highest_bit_set;
1990 *lbsp = lowest_bit_set;
1991 *abbasp = all_bits_between_are_set;
1994 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1997 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1998 unsigned HOST_WIDE_INT low_bits)
2000 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2003 || high_bits == 0xffffffff)
2006 analyze_64bit_constant (high_bits, low_bits,
2007 &highest_bit_set, &lowest_bit_set,
2008 &all_bits_between_are_set);
2010 if ((highest_bit_set == 63
2011 || lowest_bit_set == 0)
2012 && all_bits_between_are_set != 0)
2015 if ((highest_bit_set - lowest_bit_set) < 21)
2021 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2022 unsigned HOST_WIDE_INT,
2025 static unsigned HOST_WIDE_INT
2026 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2027 unsigned HOST_WIDE_INT low_bits,
2028 int lowest_bit_set, int shift)
2030 HOST_WIDE_INT hi, lo;
2032 if (lowest_bit_set < 32)
2034 lo = (low_bits >> lowest_bit_set) << shift;
2035 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2040 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2042 gcc_assert (! (hi & lo));
2046 /* Here we are sure to be arch64 and this is an integer constant
2047 being loaded into a register. Emit the most efficient
2048 insn sequence possible. Detection of all the 1-insn cases
2049 has been done already. */
2051 sparc_emit_set_const64 (rtx op0, rtx op1)
2053 unsigned HOST_WIDE_INT high_bits, low_bits;
2054 int lowest_bit_set, highest_bit_set;
2055 int all_bits_between_are_set;
2058 /* Sanity check that we know what we are working with. */
2059 gcc_assert (TARGET_ARCH64
2060 && (GET_CODE (op0) == SUBREG
2061 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
2063 if (! can_create_pseudo_p ())
2066 if (GET_CODE (op1) != CONST_INT)
2068 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2073 temp = gen_reg_rtx (DImode);
2075 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2076 low_bits = (INTVAL (op1) & 0xffffffff);
2078 /* low_bits bits 0 --> 31
2079 high_bits bits 32 --> 63 */
2081 analyze_64bit_constant (high_bits, low_bits,
2082 &highest_bit_set, &lowest_bit_set,
2083 &all_bits_between_are_set);
2085 /* First try for a 2-insn sequence. */
2087 /* These situations are preferred because the optimizer can
2088 * do more things with them:
2090 * sllx %reg, shift, %reg
2092 * srlx %reg, shift, %reg
2093 * 3) mov some_small_const, %reg
2094 * sllx %reg, shift, %reg
2096 if (((highest_bit_set == 63
2097 || lowest_bit_set == 0)
2098 && all_bits_between_are_set != 0)
2099 || ((highest_bit_set - lowest_bit_set) < 12))
2101 HOST_WIDE_INT the_const = -1;
2102 int shift = lowest_bit_set;
2104 if ((highest_bit_set != 63
2105 && lowest_bit_set != 0)
2106 || all_bits_between_are_set == 0)
2109 create_simple_focus_bits (high_bits, low_bits,
2112 else if (lowest_bit_set == 0)
2113 shift = -(63 - highest_bit_set);
2115 gcc_assert (SPARC_SIMM13_P (the_const));
2116 gcc_assert (shift != 0);
2118 emit_insn (gen_safe_SET64 (temp, the_const));
2120 emit_insn (gen_rtx_SET (VOIDmode,
2122 gen_rtx_ASHIFT (DImode,
2126 emit_insn (gen_rtx_SET (VOIDmode,
2128 gen_rtx_LSHIFTRT (DImode,
2130 GEN_INT (-shift))));
2134 /* Now a range of 22 or less bits set somewhere.
2135 * 1) sethi %hi(focus_bits), %reg
2136 * sllx %reg, shift, %reg
2137 * 2) sethi %hi(focus_bits), %reg
2138 * srlx %reg, shift, %reg
2140 if ((highest_bit_set - lowest_bit_set) < 21)
2142 unsigned HOST_WIDE_INT focus_bits =
2143 create_simple_focus_bits (high_bits, low_bits,
2144 lowest_bit_set, 10);
2146 gcc_assert (SPARC_SETHI_P (focus_bits));
2147 gcc_assert (lowest_bit_set != 10);
2149 emit_insn (gen_safe_HIGH64 (temp, focus_bits));
2151 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2152 if (lowest_bit_set < 10)
2153 emit_insn (gen_rtx_SET (VOIDmode,
2155 gen_rtx_LSHIFTRT (DImode, temp,
2156 GEN_INT (10 - lowest_bit_set))));
2157 else if (lowest_bit_set > 10)
2158 emit_insn (gen_rtx_SET (VOIDmode,
2160 gen_rtx_ASHIFT (DImode, temp,
2161 GEN_INT (lowest_bit_set - 10))));
2165 /* 1) sethi %hi(low_bits), %reg
2166 * or %reg, %lo(low_bits), %reg
2167 * 2) sethi %hi(~low_bits), %reg
2168 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2171 || high_bits == 0xffffffff)
2173 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2174 (high_bits == 0xffffffff));
2178 /* Now, try 3-insn sequences. */
2180 /* 1) sethi %hi(high_bits), %reg
2181 * or %reg, %lo(high_bits), %reg
2182 * sllx %reg, 32, %reg
2186 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2190 /* We may be able to do something quick
2191 when the constant is negated, so try that. */
2192 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2193 (~low_bits) & 0xfffffc00))
2195 /* NOTE: The trailing bits get XOR'd so we need the
2196 non-negated bits, not the negated ones. */
2197 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2199 if ((((~high_bits) & 0xffffffff) == 0
2200 && ((~low_bits) & 0x80000000) == 0)
2201 || (((~high_bits) & 0xffffffff) == 0xffffffff
2202 && ((~low_bits) & 0x80000000) != 0))
2204 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff);
2206 if ((SPARC_SETHI_P (fast_int)
2207 && (~high_bits & 0xffffffff) == 0)
2208 || SPARC_SIMM13_P (fast_int))
2209 emit_insn (gen_safe_SET64 (temp, fast_int));
2211 sparc_emit_set_const64 (temp, GEN_INT (fast_int));
2216 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2217 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2218 sparc_emit_set_const64 (temp, negated_const);
2221 /* If we are XOR'ing with -1, then we should emit a one's complement
2222 instead. This way the combiner will notice logical operations
2223 such as ANDN later on and substitute. */
2224 if (trailing_bits == 0x3ff)
2226 emit_insn (gen_rtx_SET (VOIDmode, op0,
2227 gen_rtx_NOT (DImode, temp)));
2231 emit_insn (gen_rtx_SET (VOIDmode,
2233 gen_safe_XOR64 (temp,
2234 (-0x400 | trailing_bits))));
2239 /* 1) sethi %hi(xxx), %reg
2240 * or %reg, %lo(xxx), %reg
2241 * sllx %reg, yyy, %reg
2243 * ??? This is just a generalized version of the low_bits==0
2244 * thing above, FIXME...
2246 if ((highest_bit_set - lowest_bit_set) < 32)
2248 unsigned HOST_WIDE_INT focus_bits =
2249 create_simple_focus_bits (high_bits, low_bits,
2252 /* We can't get here in this state. */
2253 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32);
2255 /* So what we know is that the set bits straddle the
2256 middle of the 64-bit word. */
2257 sparc_emit_set_const64_quick2 (op0, temp,
2263 /* 1) sethi %hi(high_bits), %reg
2264 * or %reg, %lo(high_bits), %reg
2265 * sllx %reg, 32, %reg
2266 * or %reg, low_bits, %reg
2268 if (SPARC_SIMM13_P(low_bits)
2269 && ((int)low_bits > 0))
2271 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2275 /* The easiest way when all else fails, is full decomposition. */
2276 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2278 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2280 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2281 return the mode to be used for the comparison. For floating-point,
2282 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2283 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2284 processing is needed. */
2287 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2289 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2315 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2316 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2318 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2319 return CCX_NOOVmode;
2325 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2332 /* Emit the compare insn and return the CC reg for a CODE comparison
2333 with operands X and Y. */
2336 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y)
2338 enum machine_mode mode;
2341 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
2344 mode = SELECT_CC_MODE (code, x, y);
2346 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2347 fcc regs (cse can't tell they're really call clobbered regs and will
2348 remove a duplicate comparison even if there is an intervening function
2349 call - it will then try to reload the cc reg via an int reg which is why
2350 we need the movcc patterns). It is possible to provide the movcc
2351 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2352 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2353 to tell cse that CCFPE mode registers (even pseudos) are call
2356 /* ??? This is an experiment. Rather than making changes to cse which may
2357 or may not be easy/clean, we do our own cse. This is possible because
2358 we will generate hard registers. Cse knows they're call clobbered (it
2359 doesn't know the same thing about pseudos). If we guess wrong, no big
2360 deal, but if we win, great! */
2362 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2363 #if 1 /* experiment */
2366 /* We cycle through the registers to ensure they're all exercised. */
2367 static int next_fcc_reg = 0;
2368 /* Previous x,y for each fcc reg. */
2369 static rtx prev_args[4][2];
2371 /* Scan prev_args for x,y. */
2372 for (reg = 0; reg < 4; reg++)
2373 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2378 prev_args[reg][0] = x;
2379 prev_args[reg][1] = y;
2380 next_fcc_reg = (next_fcc_reg + 1) & 3;
2382 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2385 cc_reg = gen_reg_rtx (mode);
2386 #endif /* ! experiment */
2387 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2388 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2390 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2392 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2393 will only result in an unrecognizable insn so no point in asserting. */
2394 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)));
2400 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2403 gen_compare_reg (rtx cmp)
2405 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
2408 /* This function is used for v9 only.
2409 DEST is the target of the Scc insn.
2410 CODE is the code for an Scc's comparison.
2411 X and Y are the values we compare.
2413 This function is needed to turn
2416 (gt (reg:CCX 100 %icc)
2420 (gt:DI (reg:CCX 100 %icc)
2423 IE: The instruction recognizer needs to see the mode of the comparison to
2424 find the right instruction. We could use "gt:DI" right in the
2425 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2428 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y)
2431 && (GET_MODE (x) == DImode
2432 || GET_MODE (dest) == DImode))
2435 /* Try to use the movrCC insns. */
2437 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT
2439 && v9_regcmp_p (compare_code))
2444 /* Special case for op0 != 0. This can be done with one instruction if
2447 if (compare_code == NE
2448 && GET_MODE (dest) == DImode
2449 && rtx_equal_p (op0, dest))
2451 emit_insn (gen_rtx_SET (VOIDmode, dest,
2452 gen_rtx_IF_THEN_ELSE (DImode,
2453 gen_rtx_fmt_ee (compare_code, DImode,
2460 if (reg_overlap_mentioned_p (dest, op0))
2462 /* Handle the case where dest == x.
2463 We "early clobber" the result. */
2464 op0 = gen_reg_rtx (GET_MODE (x));
2465 emit_move_insn (op0, x);
2468 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2469 if (GET_MODE (op0) != DImode)
2471 temp = gen_reg_rtx (DImode);
2472 convert_move (temp, op0, 0);
2476 emit_insn (gen_rtx_SET (VOIDmode, dest,
2477 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2478 gen_rtx_fmt_ee (compare_code, DImode,
2486 x = gen_compare_reg_1 (compare_code, x, y);
2489 gcc_assert (GET_MODE (x) != CC_NOOVmode
2490 && GET_MODE (x) != CCX_NOOVmode);
2492 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
2493 emit_insn (gen_rtx_SET (VOIDmode, dest,
2494 gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
2495 gen_rtx_fmt_ee (compare_code,
2496 GET_MODE (x), x, y),
2497 const1_rtx, dest)));
2503 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2504 without jumps using the addx/subx instructions. */
2507 emit_scc_insn (rtx operands[])
2514 /* The quad-word fp compare library routines all return nonzero to indicate
2515 true, which is different from the equivalent libgcc routines, so we must
2516 handle them specially here. */
2517 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD)
2519 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3],
2520 GET_CODE (operands[1]));
2521 operands[2] = XEXP (operands[1], 0);
2522 operands[3] = XEXP (operands[1], 1);
2525 code = GET_CODE (operands[1]);
2529 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2530 more applications). The exception to this is "reg != 0" which can
2531 be done in one instruction on v9 (so we do it). */
2534 if (GET_MODE (x) == SImode)
2536 rtx pat = gen_seqsi_special (operands[0], x, y);
2540 else if (GET_MODE (x) == DImode)
2542 rtx pat = gen_seqdi_special (operands[0], x, y);
2550 if (GET_MODE (x) == SImode)
2552 rtx pat = gen_snesi_special (operands[0], x, y);
2556 else if (GET_MODE (x) == DImode)
2560 pat = gen_snedi_special_vis3 (operands[0], x, y);
2562 pat = gen_snedi_special (operands[0], x, y);
2570 && GET_MODE (x) == DImode
2572 && (code == GTU || code == LTU))
2573 && gen_v9_scc (operands[0], code, x, y))
2576 /* We can do LTU and GEU using the addx/subx instructions too. And
2577 for GTU/LEU, if both operands are registers swap them and fall
2578 back to the easy case. */
2579 if (code == GTU || code == LEU)
2581 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2582 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
2587 code = swap_condition (code);
2592 || (!TARGET_VIS3 && code == GEU))
2594 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2595 gen_rtx_fmt_ee (code, SImode,
2596 gen_compare_reg_1 (code, x, y),
2601 /* All the posibilities to use addx/subx based sequences has been
2602 exhausted, try for a 3 instruction sequence using v9 conditional
2604 if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y))
2607 /* Nope, do branches. */
2611 /* Emit a conditional jump insn for the v9 architecture using comparison code
2612 CODE and jump target LABEL.
2613 This function exists to take advantage of the v9 brxx insns. */
2616 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2618 emit_jump_insn (gen_rtx_SET (VOIDmode,
2620 gen_rtx_IF_THEN_ELSE (VOIDmode,
2621 gen_rtx_fmt_ee (code, GET_MODE (op0),
2623 gen_rtx_LABEL_REF (VOIDmode, label),
2628 emit_conditional_branch_insn (rtx operands[])
2630 /* The quad-word fp compare library routines all return nonzero to indicate
2631 true, which is different from the equivalent libgcc routines, so we must
2632 handle them specially here. */
2633 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD)
2635 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2],
2636 GET_CODE (operands[0]));
2637 operands[1] = XEXP (operands[0], 0);
2638 operands[2] = XEXP (operands[0], 1);
2641 if (TARGET_ARCH64 && operands[2] == const0_rtx
2642 && GET_CODE (operands[1]) == REG
2643 && GET_MODE (operands[1]) == DImode)
2645 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
2649 operands[1] = gen_compare_reg (operands[0]);
2650 operands[2] = const0_rtx;
2651 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode,
2652 operands[1], operands[2]);
2653 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2],
2658 /* Generate a DFmode part of a hard TFmode register.
2659 REG is the TFmode hard register, LOW is 1 for the
2660 low 64bit of the register and 0 otherwise.
2663 gen_df_reg (rtx reg, int low)
2665 int regno = REGNO (reg);
2667 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2668 regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2;
2669 return gen_rtx_REG (DFmode, regno);
2672 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2673 Unlike normal calls, TFmode operands are passed by reference. It is
2674 assumed that no more than 3 operands are required. */
2677 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2679 rtx ret_slot = NULL, arg[3], func_sym;
2682 /* We only expect to be called for conversions, unary, and binary ops. */
2683 gcc_assert (nargs == 2 || nargs == 3);
2685 for (i = 0; i < nargs; ++i)
2687 rtx this_arg = operands[i];
2690 /* TFmode arguments and return values are passed by reference. */
2691 if (GET_MODE (this_arg) == TFmode)
2693 int force_stack_temp;
2695 force_stack_temp = 0;
2696 if (TARGET_BUGGY_QP_LIB && i == 0)
2697 force_stack_temp = 1;
2699 if (GET_CODE (this_arg) == MEM
2700 && ! force_stack_temp)
2701 this_arg = XEXP (this_arg, 0);
2702 else if (CONSTANT_P (this_arg)
2703 && ! force_stack_temp)
2705 this_slot = force_const_mem (TFmode, this_arg);
2706 this_arg = XEXP (this_slot, 0);
2710 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2712 /* Operand 0 is the return value. We'll copy it out later. */
2714 emit_move_insn (this_slot, this_arg);
2716 ret_slot = this_slot;
2718 this_arg = XEXP (this_slot, 0);
2725 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2727 if (GET_MODE (operands[0]) == TFmode)
2730 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2731 arg[0], GET_MODE (arg[0]),
2732 arg[1], GET_MODE (arg[1]));
2734 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2735 arg[0], GET_MODE (arg[0]),
2736 arg[1], GET_MODE (arg[1]),
2737 arg[2], GET_MODE (arg[2]));
2740 emit_move_insn (operands[0], ret_slot);
2746 gcc_assert (nargs == 2);
2748 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2749 GET_MODE (operands[0]), 1,
2750 arg[1], GET_MODE (arg[1]));
2752 if (ret != operands[0])
2753 emit_move_insn (operands[0], ret);
2757 /* Expand soft-float TFmode calls to sparc abi routines. */
2760 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2782 emit_soft_tfmode_libcall (func, 3, operands);
2786 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2790 gcc_assert (code == SQRT);
2793 emit_soft_tfmode_libcall (func, 2, operands);
2797 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2804 switch (GET_MODE (operands[1]))
2817 case FLOAT_TRUNCATE:
2818 switch (GET_MODE (operands[0]))
2832 switch (GET_MODE (operands[1]))
2837 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]);
2847 case UNSIGNED_FLOAT:
2848 switch (GET_MODE (operands[1]))
2853 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2864 switch (GET_MODE (operands[0]))
2878 switch (GET_MODE (operands[0]))
2895 emit_soft_tfmode_libcall (func, 2, operands);
2898 /* Expand a hard-float tfmode operation. All arguments must be in
2902 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2906 if (GET_RTX_CLASS (code) == RTX_UNARY)
2908 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2909 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2913 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2914 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2915 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2916 operands[1], operands[2]);
2919 if (register_operand (operands[0], VOIDmode))
2922 dest = gen_reg_rtx (GET_MODE (operands[0]));
2924 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2926 if (dest != operands[0])
2927 emit_move_insn (operands[0], dest);
2931 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2933 if (TARGET_HARD_QUAD)
2934 emit_hard_tfmode_operation (code, operands);
2936 emit_soft_tfmode_binop (code, operands);
2940 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2942 if (TARGET_HARD_QUAD)
2943 emit_hard_tfmode_operation (code, operands);
2945 emit_soft_tfmode_unop (code, operands);
2949 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2951 if (TARGET_HARD_QUAD)
2952 emit_hard_tfmode_operation (code, operands);
2954 emit_soft_tfmode_cvt (code, operands);
2957 /* Return nonzero if a branch/jump/call instruction will be emitting
2958 nop into its delay slot. */
2961 empty_delay_slot (rtx insn)
2965 /* If no previous instruction (should not happen), return true. */
2966 if (PREV_INSN (insn) == NULL)
2969 seq = NEXT_INSN (PREV_INSN (insn));
2970 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2976 /* Return nonzero if TRIAL can go into the call delay slot. */
2979 tls_call_delay (rtx trial)
2984 call __tls_get_addr, %tgd_call (foo)
2985 add %l7, %o0, %o0, %tgd_add (foo)
2986 while Sun as/ld does not. */
2987 if (TARGET_GNU_TLS || !TARGET_TLS)
2990 pat = PATTERN (trial);
2992 /* We must reject tgd_add{32|64}, i.e.
2993 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2994 and tldm_add{32|64}, i.e.
2995 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2997 if (GET_CODE (pat) == SET
2998 && GET_CODE (SET_SRC (pat)) == PLUS)
3000 rtx unspec = XEXP (SET_SRC (pat), 1);
3002 if (GET_CODE (unspec) == UNSPEC
3003 && (XINT (unspec, 1) == UNSPEC_TLSGD
3004 || XINT (unspec, 1) == UNSPEC_TLSLDM))
3011 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3012 instruction. RETURN_P is true if the v9 variant 'return' is to be
3013 considered in the test too.
3015 TRIAL must be a SET whose destination is a REG appropriate for the
3016 'restore' instruction or, if RETURN_P is true, for the 'return'
3020 eligible_for_restore_insn (rtx trial, bool return_p)
3022 rtx pat = PATTERN (trial);
3023 rtx src = SET_SRC (pat);
3024 bool src_is_freg = false;
3027 /* Since we now can do moves between float and integer registers when
3028 VIS3 is enabled, we have to catch this case. We can allow such
3029 moves when doing a 'return' however. */
3031 if (GET_CODE (src_reg) == SUBREG)
3032 src_reg = SUBREG_REG (src_reg);
3033 if (GET_CODE (src_reg) == REG
3034 && SPARC_FP_REG_P (REGNO (src_reg)))
3037 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3038 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3039 && arith_operand (src, GET_MODE (src))
3043 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3045 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3048 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3049 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3050 && arith_double_operand (src, GET_MODE (src))
3052 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3054 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3055 else if (! TARGET_FPU && register_operand (src, SFmode))
3058 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3059 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3062 /* If we have the 'return' instruction, anything that does not use
3063 local or output registers and can go into a delay slot wins. */
3066 && !epilogue_renumber (&pat, 1)
3067 && get_attr_in_uncond_branch_delay (trial)
3068 == IN_UNCOND_BRANCH_DELAY_TRUE)
3071 /* The 'restore src1,src2,dest' pattern for SImode. */
3072 else if (GET_CODE (src) == PLUS
3073 && register_operand (XEXP (src, 0), SImode)
3074 && arith_operand (XEXP (src, 1), SImode))
3077 /* The 'restore src1,src2,dest' pattern for DImode. */
3078 else if (GET_CODE (src) == PLUS
3079 && register_operand (XEXP (src, 0), DImode)
3080 && arith_double_operand (XEXP (src, 1), DImode))
3083 /* The 'restore src1,%lo(src2),dest' pattern. */
3084 else if (GET_CODE (src) == LO_SUM
3085 && ! TARGET_CM_MEDMID
3086 && ((register_operand (XEXP (src, 0), SImode)
3087 && immediate_operand (XEXP (src, 1), SImode))
3089 && register_operand (XEXP (src, 0), DImode)
3090 && immediate_operand (XEXP (src, 1), DImode))))
3093 /* The 'restore src,src,dest' pattern. */
3094 else if (GET_CODE (src) == ASHIFT
3095 && (register_operand (XEXP (src, 0), SImode)
3096 || register_operand (XEXP (src, 0), DImode))
3097 && XEXP (src, 1) == const1_rtx)
3103 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3106 eligible_for_return_delay (rtx trial)
3111 if (GET_CODE (trial) != INSN)
3114 if (get_attr_length (trial) != 1)
3117 /* If the function uses __builtin_eh_return, the eh_return machinery
3118 occupies the delay slot. */
3119 if (crtl->calls_eh_return)
3122 /* In the case of a leaf or flat function, anything can go into the slot. */
3123 if (sparc_leaf_function_p || TARGET_FLAT)
3125 get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE;
3127 pat = PATTERN (trial);
3128 if (GET_CODE (pat) == PARALLEL)
3134 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
3136 rtx expr = XVECEXP (pat, 0, i);
3137 if (GET_CODE (expr) != SET)
3139 if (GET_CODE (SET_DEST (expr)) != REG)
3141 regno = REGNO (SET_DEST (expr));
3142 if (regno >= 8 && regno < 24)
3145 return !epilogue_renumber (&pat, 1)
3146 && (get_attr_in_uncond_branch_delay (trial)
3147 == IN_UNCOND_BRANCH_DELAY_TRUE);
3150 if (GET_CODE (pat) != SET)
3153 if (GET_CODE (SET_DEST (pat)) != REG)
3156 regno = REGNO (SET_DEST (pat));
3158 /* Otherwise, only operations which can be done in tandem with
3159 a `restore' or `return' insn can go into the delay slot. */
3160 if (regno >= 8 && regno < 24)
3163 /* If this instruction sets up floating point register and we have a return
3164 instruction, it can probably go in. But restore will not work
3166 if (! SPARC_INT_REG_P (regno))
3168 && !epilogue_renumber (&pat, 1)
3169 && get_attr_in_uncond_branch_delay (trial)
3170 == IN_UNCOND_BRANCH_DELAY_TRUE);
3172 return eligible_for_restore_insn (trial, true);
3175 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3178 eligible_for_sibcall_delay (rtx trial)
3182 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3185 if (get_attr_length (trial) != 1)
3188 pat = PATTERN (trial);
3190 if (sparc_leaf_function_p || TARGET_FLAT)
3192 /* If the tail call is done using the call instruction,
3193 we have to restore %o7 in the delay slot. */
3194 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3197 /* %g1 is used to build the function address */
3198 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3204 /* Otherwise, only operations which can be done in tandem with
3205 a `restore' insn can go into the delay slot. */
3206 if (GET_CODE (SET_DEST (pat)) != REG
3207 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3208 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
3211 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3213 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3216 return eligible_for_restore_insn (trial, false);
3219 /* Determine if it's legal to put X into the constant pool. This
3220 is not possible if X contains the address of a symbol that is
3221 not constant (TLS) or not known at final link time (PIC). */
3224 sparc_cannot_force_const_mem (enum machine_mode mode, rtx x)
3226 switch (GET_CODE (x))
3231 /* Accept all non-symbolic constants. */
3235 /* Labels are OK iff we are non-PIC. */
3236 return flag_pic != 0;
3239 /* 'Naked' TLS symbol references are never OK,
3240 non-TLS symbols are OK iff we are non-PIC. */
3241 if (SYMBOL_REF_TLS_MODEL (x))
3244 return flag_pic != 0;
3247 return sparc_cannot_force_const_mem (mode, XEXP (x, 0));
3250 return sparc_cannot_force_const_mem (mode, XEXP (x, 0))
3251 || sparc_cannot_force_const_mem (mode, XEXP (x, 1));
3259 /* Global Offset Table support. */
3260 static GTY(()) rtx got_helper_rtx = NULL_RTX;
3261 static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
3263 /* Return the SYMBOL_REF for the Global Offset Table. */
3265 static GTY(()) rtx sparc_got_symbol = NULL_RTX;
3270 if (!sparc_got_symbol)
3271 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3273 return sparc_got_symbol;
3276 /* Ensure that we are not using patterns that are not OK with PIC. */
3286 op = recog_data.operand[i];
3287 gcc_assert (GET_CODE (op) != SYMBOL_REF
3288 && (GET_CODE (op) != CONST
3289 || (GET_CODE (XEXP (op, 0)) == MINUS
3290 && XEXP (XEXP (op, 0), 0) == sparc_got ()
3291 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
3298 /* Return true if X is an address which needs a temporary register when
3299 reloaded while generating PIC code. */
3302 pic_address_needs_scratch (rtx x)
3304 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3305 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3306 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3307 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3308 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3314 /* Determine if a given RTX is a valid constant. We already know this
3315 satisfies CONSTANT_P. */
3318 sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
3320 switch (GET_CODE (x))
3324 if (sparc_tls_referenced_p (x))
3329 if (GET_MODE (x) == VOIDmode)
3332 /* Floating point constants are generally not ok.
3333 The only exception is 0.0 and all-ones in VIS. */
3335 && SCALAR_FLOAT_MODE_P (mode)
3336 && (const_zero_operand (x, mode)
3337 || const_all_ones_operand (x, mode)))
3343 /* Vector constants are generally not ok.
3344 The only exception is 0 or -1 in VIS. */
3346 && (const_zero_operand (x, mode)
3347 || const_all_ones_operand (x, mode)))
3359 /* Determine if a given RTX is a valid constant address. */
3362 constant_address_p (rtx x)
3364 switch (GET_CODE (x))
3372 if (flag_pic && pic_address_needs_scratch (x))
3374 return sparc_legitimate_constant_p (Pmode, x);
3377 return !flag_pic && sparc_legitimate_constant_p (Pmode, x);
3384 /* Nonzero if the constant value X is a legitimate general operand
3385 when generating PIC code. It is given that flag_pic is on and
3386 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3389 legitimate_pic_operand_p (rtx x)
3391 if (pic_address_needs_scratch (x))
3393 if (sparc_tls_referenced_p (x))
3398 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3400 && INTVAL (X) >= -0x1000 \
3401 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3403 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3405 && INTVAL (X) >= -0x1000 \
3406 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3408 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3410 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3411 ordinarily. This changes a bit when generating PIC. */
3414 sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3416 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3418 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3420 else if (GET_CODE (addr) == PLUS)
3422 rs1 = XEXP (addr, 0);
3423 rs2 = XEXP (addr, 1);
3425 /* Canonicalize. REG comes first, if there are no regs,
3426 LO_SUM comes first. */
3428 && GET_CODE (rs1) != SUBREG
3430 || GET_CODE (rs2) == SUBREG
3431 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3433 rs1 = XEXP (addr, 1);
3434 rs2 = XEXP (addr, 0);
3438 && rs1 == pic_offset_table_rtx
3440 && GET_CODE (rs2) != SUBREG
3441 && GET_CODE (rs2) != LO_SUM
3442 && GET_CODE (rs2) != MEM
3443 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
3444 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3445 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3447 || GET_CODE (rs1) == SUBREG)
3448 && RTX_OK_FOR_OFFSET_P (rs2, mode)))
3453 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3454 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3456 /* We prohibit REG + REG for TFmode when there are no quad move insns
3457 and we consequently need to split. We do this because REG+REG
3458 is not an offsettable address. If we get the situation in reload
3459 where source and destination of a movtf pattern are both MEMs with
3460 REG+REG address, then only one of them gets converted to an
3461 offsettable address. */
3463 && ! (TARGET_ARCH64 && TARGET_HARD_QUAD))
3466 /* We prohibit REG + REG on ARCH32 if not optimizing for
3467 DFmode/DImode because then mem_min_alignment is likely to be zero
3468 after reload and the forced split would lack a matching splitter
3470 if (TARGET_ARCH32 && !optimize
3471 && (mode == DFmode || mode == DImode))
3474 else if (USE_AS_OFFSETABLE_LO10
3475 && GET_CODE (rs1) == LO_SUM
3477 && ! TARGET_CM_MEDMID
3478 && RTX_OK_FOR_OLO10_P (rs2, mode))
3481 imm1 = XEXP (rs1, 1);
3482 rs1 = XEXP (rs1, 0);
3483 if (!CONSTANT_P (imm1)
3484 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3488 else if (GET_CODE (addr) == LO_SUM)
3490 rs1 = XEXP (addr, 0);
3491 imm1 = XEXP (addr, 1);
3493 if (!CONSTANT_P (imm1)
3494 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
3497 /* We can't allow TFmode in 32-bit mode, because an offset greater
3498 than the alignment (8) may cause the LO_SUM to overflow. */
3499 if (mode == TFmode && TARGET_ARCH32)
3502 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3507 if (GET_CODE (rs1) == SUBREG)
3508 rs1 = SUBREG_REG (rs1);
3514 if (GET_CODE (rs2) == SUBREG)
3515 rs2 = SUBREG_REG (rs2);
3522 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3523 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3528 if ((! SPARC_INT_REG_P (REGNO (rs1))
3529 && REGNO (rs1) != FRAME_POINTER_REGNUM
3530 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3532 && (! SPARC_INT_REG_P (REGNO (rs2))
3533 && REGNO (rs2) != FRAME_POINTER_REGNUM
3534 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3540 /* Return the SYMBOL_REF for the tls_get_addr function. */
3542 static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
3545 sparc_tls_get_addr (void)
3547 if (!sparc_tls_symbol)
3548 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3550 return sparc_tls_symbol;
3553 /* Return the Global Offset Table to be used in TLS mode. */
3556 sparc_tls_got (void)
3558 /* In PIC mode, this is just the PIC offset table. */
3561 crtl->uses_pic_offset_table = 1;
3562 return pic_offset_table_rtx;
3565 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3566 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3567 if (TARGET_SUN_TLS && TARGET_ARCH32)
3569 load_got_register ();
3570 return global_offset_table_rtx;
3573 /* In all other cases, we load a new pseudo with the GOT symbol. */
3574 return copy_to_reg (sparc_got ());
3577 /* Return true if X contains a thread-local symbol. */
3580 sparc_tls_referenced_p (rtx x)
3582 if (!TARGET_HAVE_TLS)
3585 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
3586 x = XEXP (XEXP (x, 0), 0);
3588 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
3591 /* That's all we handle in sparc_legitimize_tls_address for now. */
3595 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3596 this (thread-local) address. */
3599 sparc_legitimize_tls_address (rtx addr)
3601 rtx temp1, temp2, temp3, ret, o0, got, insn;
3603 gcc_assert (can_create_pseudo_p ());
3605 if (GET_CODE (addr) == SYMBOL_REF)
3606 switch (SYMBOL_REF_TLS_MODEL (addr))
3608 case TLS_MODEL_GLOBAL_DYNAMIC:
3610 temp1 = gen_reg_rtx (SImode);
3611 temp2 = gen_reg_rtx (SImode);
3612 ret = gen_reg_rtx (Pmode);
3613 o0 = gen_rtx_REG (Pmode, 8);
3614 got = sparc_tls_got ();
3615 emit_insn (gen_tgd_hi22 (temp1, addr));
3616 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3619 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3620 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3625 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3626 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3629 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3630 insn = get_insns ();
3632 emit_libcall_block (insn, ret, o0, addr);
3635 case TLS_MODEL_LOCAL_DYNAMIC:
3637 temp1 = gen_reg_rtx (SImode);
3638 temp2 = gen_reg_rtx (SImode);
3639 temp3 = gen_reg_rtx (Pmode);
3640 ret = gen_reg_rtx (Pmode);
3641 o0 = gen_rtx_REG (Pmode, 8);
3642 got = sparc_tls_got ();
3643 emit_insn (gen_tldm_hi22 (temp1));
3644 emit_insn (gen_tldm_lo10 (temp2, temp1));
3647 emit_insn (gen_tldm_add32 (o0, got, temp2));
3648 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3653 emit_insn (gen_tldm_add64 (o0, got, temp2));
3654 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3657 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
3658 insn = get_insns ();
3660 emit_libcall_block (insn, temp3, o0,
3661 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3662 UNSPEC_TLSLD_BASE));
3663 temp1 = gen_reg_rtx (SImode);
3664 temp2 = gen_reg_rtx (SImode);
3665 emit_insn (gen_tldo_hix22 (temp1, addr));
3666 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3668 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3670 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3673 case TLS_MODEL_INITIAL_EXEC:
3674 temp1 = gen_reg_rtx (SImode);
3675 temp2 = gen_reg_rtx (SImode);
3676 temp3 = gen_reg_rtx (Pmode);
3677 got = sparc_tls_got ();
3678 emit_insn (gen_tie_hi22 (temp1, addr));
3679 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3681 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3683 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3686 ret = gen_reg_rtx (Pmode);
3688 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3691 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3695 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3698 case TLS_MODEL_LOCAL_EXEC:
3699 temp1 = gen_reg_rtx (Pmode);
3700 temp2 = gen_reg_rtx (Pmode);
3703 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3704 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3708 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3709 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3711 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3718 else if (GET_CODE (addr) == CONST)
3722 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS);
3724 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0));
3725 offset = XEXP (XEXP (addr, 0), 1);
3727 base = force_operand (base, NULL_RTX);
3728 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
3729 offset = force_reg (Pmode, offset);
3730 ret = gen_rtx_PLUS (Pmode, base, offset);
3734 gcc_unreachable (); /* for now ... */
3739 /* Legitimize PIC addresses. If the address is already position-independent,
3740 we return ORIG. Newly generated position-independent addresses go into a
3741 reg. This is REG if nonzero, otherwise we allocate register(s) as
3745 sparc_legitimize_pic_address (rtx orig, rtx reg)
3747 bool gotdata_op = false;
3749 if (GET_CODE (orig) == SYMBOL_REF
3750 /* See the comment in sparc_expand_move. */
3751 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
3753 rtx pic_ref, address;
3758 gcc_assert (can_create_pseudo_p ());
3759 reg = gen_reg_rtx (Pmode);
3764 /* If not during reload, allocate another temp reg here for loading
3765 in the address, so that these instructions can be optimized
3767 rtx temp_reg = (! can_create_pseudo_p ()
3768 ? reg : gen_reg_rtx (Pmode));
3770 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3771 won't get confused into thinking that these two instructions
3772 are loading in the true address of the symbol. If in the
3773 future a PIC rtx exists, that should be used instead. */
3776 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3777 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3781 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3782 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3790 crtl->uses_pic_offset_table = 1;
3794 insn = emit_insn (gen_movdi_pic_gotdata_op (reg,
3795 pic_offset_table_rtx,
3798 insn = emit_insn (gen_movsi_pic_gotdata_op (reg,
3799 pic_offset_table_rtx,
3805 = gen_const_mem (Pmode,
3806 gen_rtx_PLUS (Pmode,
3807 pic_offset_table_rtx, address));
3808 insn = emit_move_insn (reg, pic_ref);
3811 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3813 set_unique_reg_note (insn, REG_EQUAL, orig);
3816 else if (GET_CODE (orig) == CONST)
3820 if (GET_CODE (XEXP (orig, 0)) == PLUS
3821 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3826 gcc_assert (can_create_pseudo_p ());
3827 reg = gen_reg_rtx (Pmode);
3830 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3831 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
3832 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
3833 base == reg ? NULL_RTX : reg);
3835 if (GET_CODE (offset) == CONST_INT)
3837 if (SMALL_INT (offset))
3838 return plus_constant (base, INTVAL (offset));
3839 else if (can_create_pseudo_p ())
3840 offset = force_reg (Pmode, offset);
3842 /* If we reach here, then something is seriously wrong. */
3845 return gen_rtx_PLUS (Pmode, base, offset);
3847 else if (GET_CODE (orig) == LABEL_REF)
3848 /* ??? We ought to be checking that the register is live instead, in case
3849 it is eliminated. */
3850 crtl->uses_pic_offset_table = 1;
3855 /* Try machine-dependent ways of modifying an illegitimate address X
3856 to be legitimate. If we find one, return the new, valid address.
3858 OLDX is the address as it was before break_out_memory_refs was called.
3859 In some cases it is useful to look at this to decide what needs to be done.
3861 MODE is the mode of the operand pointed to by X.
3863 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3866 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3867 enum machine_mode mode)
3871 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3872 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3873 force_operand (XEXP (x, 0), NULL_RTX));
3874 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3875 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3876 force_operand (XEXP (x, 1), NULL_RTX));
3877 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3878 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3880 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3881 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3882 force_operand (XEXP (x, 1), NULL_RTX));
3884 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE))
3887 if (sparc_tls_referenced_p (x))
3888 x = sparc_legitimize_tls_address (x);
3890 x = sparc_legitimize_pic_address (x, NULL_RTX);
3891 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3892 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3893 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3894 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3895 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3896 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3897 else if (GET_CODE (x) == SYMBOL_REF
3898 || GET_CODE (x) == CONST
3899 || GET_CODE (x) == LABEL_REF)
3900 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3905 /* Delegitimize an address that was legitimized by the above function. */
3908 sparc_delegitimize_address (rtx x)
3910 x = delegitimize_mem_from_attrs (x);
3912 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
3913 switch (XINT (XEXP (x, 1), 1))
3915 case UNSPEC_MOVE_PIC:
3917 x = XVECEXP (XEXP (x, 1), 0, 0);
3918 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3924 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3925 if (GET_CODE (x) == MINUS
3926 && REG_P (XEXP (x, 0))
3927 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
3928 && GET_CODE (XEXP (x, 1)) == LO_SUM
3929 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
3930 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
3932 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
3933 gcc_assert (GET_CODE (x) == LABEL_REF);
3939 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3940 replace the input X, or the original X if no replacement is called for.
3941 The output parameter *WIN is 1 if the calling macro should goto WIN,
3944 For SPARC, we wish to handle addresses by splitting them into
3945 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3946 This cuts the number of extra insns by one.
3948 Do nothing when generating PIC code and the address is a symbolic
3949 operand or requires a scratch register. */
3952 sparc_legitimize_reload_address (rtx x, enum machine_mode mode,
3953 int opnum, int type,
3954 int ind_levels ATTRIBUTE_UNUSED, int *win)
3956 /* Decompose SImode constants into HIGH+LO_SUM. */
3958 && (mode != TFmode || TARGET_ARCH64)
3959 && GET_MODE (x) == SImode
3960 && GET_CODE (x) != LO_SUM
3961 && GET_CODE (x) != HIGH
3962 && sparc_cmodel <= CM_MEDLOW
3964 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
3966 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x);
3967 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3968 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3969 opnum, (enum reload_type)type);
3974 /* We have to recognize what we have already generated above. */
3975 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH)
3977 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3978 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3979 opnum, (enum reload_type)type);
3988 /* Return true if ADDR (a legitimate address expression)
3989 has an effect that depends on the machine mode it is used for.
3995 is not equivalent to
3997 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3999 because [%l7+a+1] is interpreted as the address of (a+1). */
4003 sparc_mode_dependent_address_p (const_rtx addr)
4005 if (flag_pic && GET_CODE (addr) == PLUS)
4007 rtx op0 = XEXP (addr, 0);
4008 rtx op1 = XEXP (addr, 1);
4009 if (op0 == pic_offset_table_rtx
4010 && symbolic_operand (op1, VOIDmode))
4017 #ifdef HAVE_GAS_HIDDEN
4018 # define USE_HIDDEN_LINKONCE 1
4020 # define USE_HIDDEN_LINKONCE 0
4024 get_pc_thunk_name (char name[32], unsigned int regno)
4026 const char *reg_name = reg_names[regno];
4028 /* Skip the leading '%' as that cannot be used in a
4032 if (USE_HIDDEN_LINKONCE)
4033 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
4035 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
4038 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4041 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
4043 int orig_flag_pic = flag_pic;
4046 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4049 insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
4051 insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
4052 flag_pic = orig_flag_pic;
4057 /* Emit code to load the GOT register. */
4060 load_got_register (void)
4062 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4063 if (!global_offset_table_rtx)
4064 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
4066 if (TARGET_VXWORKS_RTP)
4067 emit_insn (gen_vxworks_load_got ());
4070 /* The GOT symbol is subject to a PC-relative relocation so we need a
4071 helper function to add the PC value and thus get the final value. */
4072 if (!got_helper_rtx)
4075 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
4076 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4079 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
4081 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
4084 /* Need to emit this whether or not we obey regdecls,
4085 since setjmp/longjmp can cause life info to screw up.
4086 ??? In the case where we don't obey regdecls, this is not sufficient
4087 since we may not fall out the bottom. */
4088 emit_use (global_offset_table_rtx);
4091 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4092 address of the call target. */
4095 sparc_emit_call_insn (rtx pat, rtx addr)
4099 insn = emit_call_insn (pat);
4101 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4102 if (TARGET_VXWORKS_RTP
4104 && GET_CODE (addr) == SYMBOL_REF
4105 && (SYMBOL_REF_DECL (addr)
4106 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
4107 : !SYMBOL_REF_LOCAL_P (addr)))
4109 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
4110 crtl->uses_pic_offset_table = 1;
4114 /* Return 1 if RTX is a MEM which is known to be aligned to at
4115 least a DESIRED byte boundary. */
4118 mem_min_alignment (rtx mem, int desired)
4120 rtx addr, base, offset;
4122 /* If it's not a MEM we can't accept it. */
4123 if (GET_CODE (mem) != MEM)
4127 if (!TARGET_UNALIGNED_DOUBLES
4128 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
4131 /* ??? The rest of the function predates MEM_ALIGN so
4132 there is probably a bit of redundancy. */
4133 addr = XEXP (mem, 0);
4134 base = offset = NULL_RTX;
4135 if (GET_CODE (addr) == PLUS)
4137 if (GET_CODE (XEXP (addr, 0)) == REG)
4139 base = XEXP (addr, 0);
4141 /* What we are saying here is that if the base
4142 REG is aligned properly, the compiler will make
4143 sure any REG based index upon it will be so
4145 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4146 offset = XEXP (addr, 1);
4148 offset = const0_rtx;
4151 else if (GET_CODE (addr) == REG)
4154 offset = const0_rtx;
4157 if (base != NULL_RTX)
4159 int regno = REGNO (base);
4161 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4163 /* Check if the compiler has recorded some information
4164 about the alignment of the base REG. If reload has
4165 completed, we already matched with proper alignments.
4166 If not running global_alloc, reload might give us
4167 unaligned pointer to local stack though. */
4169 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4170 || (optimize && reload_completed))
4171 && (INTVAL (offset) & (desired - 1)) == 0)
4176 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4180 else if (! TARGET_UNALIGNED_DOUBLES
4181 || CONSTANT_P (addr)
4182 || GET_CODE (addr) == LO_SUM)
4184 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4185 is true, in which case we can only assume that an access is aligned if
4186 it is to a constant address, or the address involves a LO_SUM. */
4190 /* An obviously unaligned address. */
4195 /* Vectors to keep interesting information about registers where it can easily
4196 be got. We used to use the actual mode value as the bit number, but there
4197 are more than 32 modes now. Instead we use two tables: one indexed by
4198 hard register number, and one indexed by mode. */
4200 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4201 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4202 mapped into one sparc_mode_class mode. */
4204 enum sparc_mode_class {
4205 S_MODE, D_MODE, T_MODE, O_MODE,
4206 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4210 /* Modes for single-word and smaller quantities. */
4211 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4213 /* Modes for double-word and smaller quantities. */
4214 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4216 /* Modes for quad-word and smaller quantities. */
4217 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4219 /* Modes for 8-word and smaller quantities. */
4220 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4222 /* Modes for single-float quantities. We must allow any single word or
4223 smaller quantity. This is because the fix/float conversion instructions
4224 take integer inputs/outputs from the float registers. */
4225 #define SF_MODES (S_MODES)
4227 /* Modes for double-float and smaller quantities. */
4228 #define DF_MODES (D_MODES)
4230 /* Modes for quad-float and smaller quantities. */
4231 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4233 /* Modes for quad-float pairs and smaller quantities. */
4234 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4236 /* Modes for double-float only quantities. */
4237 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4239 /* Modes for quad-float and double-float only quantities. */
4240 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4242 /* Modes for quad-float pairs and double-float only quantities. */
4243 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4245 /* Modes for condition codes. */
4246 #define CC_MODES (1 << (int) CC_MODE)
4247 #define CCFP_MODES (1 << (int) CCFP_MODE)
4249 /* Value is 1 if register/mode pair is acceptable on sparc.
4250 The funny mixture of D and T modes is because integer operations
4251 do not specially operate on tetra quantities, so non-quad-aligned
4252 registers can hold quadword quantities (except %o4 and %i4 because
4253 they cross fixed registers). */
4255 /* This points to either the 32 bit or the 64 bit version. */
4256 const int *hard_regno_mode_classes;
4258 static const int hard_32bit_mode_classes[] = {
4259 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4260 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4261 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4262 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4264 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4265 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4266 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4267 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4269 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4270 and none can hold SFmode/SImode values. */
4271 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4272 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4273 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4274 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4277 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4279 /* %icc, %sfp, %gsr */
4280 CC_MODES, 0, D_MODES
4283 static const int hard_64bit_mode_classes[] = {
4284 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4285 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4286 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4287 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4289 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4290 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4291 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4292 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4294 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4295 and none can hold SFmode/SImode values. */
4296 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4297 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4298 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4299 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4302 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4304 /* %icc, %sfp, %gsr */
4305 CC_MODES, 0, D_MODES
4308 int sparc_mode_class [NUM_MACHINE_MODES];
4310 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4313 sparc_init_modes (void)
4317 for (i = 0; i < NUM_MACHINE_MODES; i++)
4319 switch (GET_MODE_CLASS (i))
4322 case MODE_PARTIAL_INT:
4323 case MODE_COMPLEX_INT:
4324 if (GET_MODE_SIZE (i) <= 4)
4325 sparc_mode_class[i] = 1 << (int) S_MODE;
4326 else if (GET_MODE_SIZE (i) == 8)
4327 sparc_mode_class[i] = 1 << (int) D_MODE;
4328 else if (GET_MODE_SIZE (i) == 16)
4329 sparc_mode_class[i] = 1 << (int) T_MODE;
4330 else if (GET_MODE_SIZE (i) == 32)
4331 sparc_mode_class[i] = 1 << (int) O_MODE;
4333 sparc_mode_class[i] = 0;
4335 case MODE_VECTOR_INT:
4336 if (GET_MODE_SIZE (i) <= 4)
4337 sparc_mode_class[i] = 1 << (int)SF_MODE;
4338 else if (GET_MODE_SIZE (i) == 8)
4339 sparc_mode_class[i] = 1 << (int)DF_MODE;
4342 case MODE_COMPLEX_FLOAT:
4343 if (GET_MODE_SIZE (i) <= 4)
4344 sparc_mode_class[i] = 1 << (int) SF_MODE;
4345 else if (GET_MODE_SIZE (i) == 8)
4346 sparc_mode_class[i] = 1 << (int) DF_MODE;
4347 else if (GET_MODE_SIZE (i) == 16)
4348 sparc_mode_class[i] = 1 << (int) TF_MODE;
4349 else if (GET_MODE_SIZE (i) == 32)
4350 sparc_mode_class[i] = 1 << (int) OF_MODE;
4352 sparc_mode_class[i] = 0;
4355 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4356 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4358 sparc_mode_class[i] = 1 << (int) CC_MODE;
4361 sparc_mode_class[i] = 0;
4367 hard_regno_mode_classes = hard_64bit_mode_classes;
4369 hard_regno_mode_classes = hard_32bit_mode_classes;
4371 /* Initialize the array used by REGNO_REG_CLASS. */
4372 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4374 if (i < 16 && TARGET_V8PLUS)
4375 sparc_regno_reg_class[i] = I64_REGS;
4376 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4377 sparc_regno_reg_class[i] = GENERAL_REGS;
4379 sparc_regno_reg_class[i] = FP_REGS;
4381 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4383 sparc_regno_reg_class[i] = FPCC_REGS;
4385 sparc_regno_reg_class[i] = NO_REGS;
4389 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4392 save_global_or_fp_reg_p (unsigned int regno,
4393 int leaf_function ATTRIBUTE_UNUSED)
4395 return !call_used_regs[regno] && df_regs_ever_live_p (regno);
4398 /* Return whether the return address register (%i7) is needed. */
4401 return_addr_reg_needed_p (int leaf_function)
4403 /* If it is live, for example because of __builtin_return_address (0). */
4404 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM))
4407 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4409 /* Loading the GOT register clobbers %o7. */
4410 || crtl->uses_pic_offset_table
4411 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM))
4417 /* Return whether REGNO, a local or in register, must be saved/restored. */
4420 save_local_or_in_reg_p (unsigned int regno, int leaf_function)
4422 /* General case: call-saved registers live at some point. */
4423 if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
4426 /* Frame pointer register (%fp) if needed. */
4427 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
4430 /* Return address register (%i7) if needed. */
4431 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function))
4434 /* GOT register (%l7) if needed. */
4435 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
4438 /* If the function accesses prior frames, the frame pointer and the return
4439 address of the previous frame must be saved on the stack. */
4440 if (crtl->accesses_prior_frames
4441 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM))
4447 /* Compute the frame size required by the function. This function is called
4448 during the reload pass and also by sparc_expand_prologue. */
4451 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4453 HOST_WIDE_INT frame_size, apparent_frame_size;
4454 int args_size, n_global_fp_regs = 0;
4455 bool save_local_in_regs_p = false;
4458 /* If the function allocates dynamic stack space, the dynamic offset is
4459 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4460 if (leaf_function && !cfun->calls_alloca)
4463 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl);
4465 /* Calculate space needed for global registers. */
4467 for (i = 0; i < 8; i++)
4468 if (save_global_or_fp_reg_p (i, 0))
4469 n_global_fp_regs += 2;
4471 for (i = 0; i < 8; i += 2)
4472 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4473 n_global_fp_regs += 2;
4475 /* In the flat window model, find out which local and in registers need to
4476 be saved. We don't reserve space in the current frame for them as they
4477 will be spilled into the register window save area of the caller's frame.
4478 However, as soon as we use this register window save area, we must create
4479 that of the current frame to make it the live one. */
4481 for (i = 16; i < 32; i++)
4482 if (save_local_or_in_reg_p (i, leaf_function))
4484 save_local_in_regs_p = true;
4488 /* Calculate space needed for FP registers. */
4489 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4490 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0))
4491 n_global_fp_regs += 2;
4494 && n_global_fp_regs == 0
4496 && !save_local_in_regs_p)
4497 frame_size = apparent_frame_size = 0;
4500 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4501 apparent_frame_size = (size - STARTING_FRAME_OFFSET + 7) & -8;
4502 apparent_frame_size += n_global_fp_regs * 4;
4504 /* We need to add the size of the outgoing argument area. */
4505 frame_size = apparent_frame_size + ((args_size + 7) & -8);
4507 /* And that of the register window save area. */
4508 frame_size += FIRST_PARM_OFFSET (cfun->decl);
4510 /* Finally, bump to the appropriate alignment. */
4511 frame_size = SPARC_STACK_ALIGN (frame_size);
4514 /* Set up values for use in prologue and epilogue. */
4515 sparc_frame_size = frame_size;
4516 sparc_apparent_frame_size = apparent_frame_size;
4517 sparc_n_global_fp_regs = n_global_fp_regs;
4518 sparc_save_local_in_regs_p = save_local_in_regs_p;
4523 /* Output any necessary .register pseudo-ops. */
4526 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4528 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4534 /* Check if %g[2367] were used without
4535 .register being printed for them already. */
4536 for (i = 2; i < 8; i++)
4538 if (df_regs_ever_live_p (i)
4539 && ! sparc_hard_reg_printed [i])
4541 sparc_hard_reg_printed [i] = 1;
4542 /* %g7 is used as TLS base register, use #ignore
4543 for it instead of #scratch. */
4544 fprintf (file, "\t.register\t%%g%d, #%s\n", i,
4545 i == 7 ? "ignore" : "scratch");
4552 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4554 #if PROBE_INTERVAL > 4096
4555 #error Cannot use indexed addressing mode for stack probing
4558 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4559 inclusive. These are offsets from the current stack pointer.
4561 Note that we don't use the REG+REG addressing mode for the probes because
4562 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4563 so the advantages of having a single code win here. */
4566 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
4568 rtx g1 = gen_rtx_REG (Pmode, 1);
4570 /* See if we have a constant small number of probes to generate. If so,
4571 that's the easy case. */
4572 if (size <= PROBE_INTERVAL)
4574 emit_move_insn (g1, GEN_INT (first));
4575 emit_insn (gen_rtx_SET (VOIDmode, g1,
4576 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4577 emit_stack_probe (plus_constant (g1, -size));
4580 /* The run-time loop is made up of 10 insns in the generic case while the
4581 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4582 else if (size <= 5 * PROBE_INTERVAL)
4586 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL));
4587 emit_insn (gen_rtx_SET (VOIDmode, g1,
4588 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4589 emit_stack_probe (g1);
4591 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4592 it exceeds SIZE. If only two probes are needed, this will not
4593 generate any code. Then probe at FIRST + SIZE. */
4594 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
4596 emit_insn (gen_rtx_SET (VOIDmode, g1,
4597 plus_constant (g1, -PROBE_INTERVAL)));
4598 emit_stack_probe (g1);
4601 emit_stack_probe (plus_constant (g1, (i - PROBE_INTERVAL) - size));
4604 /* Otherwise, do the same as above, but in a loop. Note that we must be
4605 extra careful with variables wrapping around because we might be at
4606 the very top (or the very bottom) of the address space and we have
4607 to be able to handle this case properly; in particular, we use an
4608 equality test for the loop condition. */
4611 HOST_WIDE_INT rounded_size;
4612 rtx g4 = gen_rtx_REG (Pmode, 4);
4614 emit_move_insn (g1, GEN_INT (first));
4617 /* Step 1: round SIZE to the previous multiple of the interval. */
4619 rounded_size = size & -PROBE_INTERVAL;
4620 emit_move_insn (g4, GEN_INT (rounded_size));
4623 /* Step 2: compute initial and final value of the loop counter. */
4625 /* TEST_ADDR = SP + FIRST. */
4626 emit_insn (gen_rtx_SET (VOIDmode, g1,
4627 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1)));
4629 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4630 emit_insn (gen_rtx_SET (VOIDmode, g4, gen_rtx_MINUS (Pmode, g1, g4)));
4635 while (TEST_ADDR != LAST_ADDR)
4637 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4641 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4642 until it is equal to ROUNDED_SIZE. */
4645 emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
4647 emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
4650 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4651 that SIZE is equal to ROUNDED_SIZE. */
4653 if (size != rounded_size)
4654 emit_stack_probe (plus_constant (g4, rounded_size - size));
4657 /* Make sure nothing is scheduled before we are done. */
4658 emit_insn (gen_blockage ());
4661 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4662 absolute addresses. */
4665 output_probe_stack_range (rtx reg1, rtx reg2)
4667 static int labelno = 0;
4668 char loop_lab[32], end_lab[32];
4671 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
4672 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
4674 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
4676 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4679 output_asm_insn ("cmp\t%0, %1", xops);
4681 fputs ("\tbe,pn\t%xcc,", asm_out_file);
4683 fputs ("\tbe\t", asm_out_file);
4684 assemble_name_raw (asm_out_file, end_lab);
4685 fputc ('\n', asm_out_file);
4687 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4688 xops[1] = GEN_INT (-PROBE_INTERVAL);
4689 output_asm_insn (" add\t%0, %1, %0", xops);
4691 /* Probe at TEST_ADDR and branch. */
4693 fputs ("\tba,pt\t%xcc,", asm_out_file);
4695 fputs ("\tba\t", asm_out_file);
4696 assemble_name_raw (asm_out_file, loop_lab);
4697 fputc ('\n', asm_out_file);
4698 xops[1] = GEN_INT (SPARC_STACK_BIAS);
4699 output_asm_insn (" st\t%%g0, [%0+%1]", xops);
4701 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
4706 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4707 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4708 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4709 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4710 the action to be performed if it returns false. Return the new offset. */
4712 typedef bool (*sorr_pred_t) (unsigned int, int);
4713 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t;
4716 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base,
4717 int offset, int leaf_function, sorr_pred_t save_p,
4718 sorr_act_t action_true, sorr_act_t action_false)
4723 if (TARGET_ARCH64 && high <= 32)
4727 for (i = low; i < high; i++)
4729 if (save_p (i, leaf_function))
4731 mem = gen_frame_mem (DImode, plus_constant (base, offset));
4732 if (action_true == SORR_SAVE)
4734 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4735 RTX_FRAME_RELATED_P (insn) = 1;
4737 else /* action_true == SORR_RESTORE */
4739 /* The frame pointer must be restored last since its old
4740 value may be used as base address for the frame. This
4741 is problematic in 64-bit mode only because of the lack
4742 of double-word load instruction. */
4743 if (i == HARD_FRAME_POINTER_REGNUM)
4746 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4750 else if (action_false == SORR_ADVANCE)
4756 mem = gen_frame_mem (DImode, plus_constant (base, fp_offset));
4757 emit_move_insn (hard_frame_pointer_rtx, mem);
4762 for (i = low; i < high; i += 2)
4764 bool reg0 = save_p (i, leaf_function);
4765 bool reg1 = save_p (i + 1, leaf_function);
4766 enum machine_mode mode;
4771 mode = SPARC_INT_REG_P (i) ? DImode : DFmode;
4776 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
4781 mode = SPARC_INT_REG_P (i) ? SImode : SFmode;
4787 if (action_false == SORR_ADVANCE)
4792 mem = gen_frame_mem (mode, plus_constant (base, offset));
4793 if (action_true == SORR_SAVE)
4795 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4796 RTX_FRAME_RELATED_P (insn) = 1;
4800 mem = gen_frame_mem (SImode, plus_constant (base, offset));
4801 set1 = gen_rtx_SET (VOIDmode, mem,
4802 gen_rtx_REG (SImode, regno));
4803 RTX_FRAME_RELATED_P (set1) = 1;
4805 = gen_frame_mem (SImode, plus_constant (base, offset + 4));
4806 set2 = gen_rtx_SET (VOIDmode, mem,
4807 gen_rtx_REG (SImode, regno + 1));
4808 RTX_FRAME_RELATED_P (set2) = 1;
4809 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4810 gen_rtx_PARALLEL (VOIDmode,
4811 gen_rtvec (2, set1, set2)));
4814 else /* action_true == SORR_RESTORE */
4815 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4817 /* Always preserve double-word alignment. */
4818 offset = (offset + 8) & -8;
4825 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4828 emit_adjust_base_to_offset (rtx base, int offset)
4830 /* ??? This might be optimized a little as %g1 might already have a
4831 value close enough that a single add insn will do. */
4832 /* ??? Although, all of this is probably only a temporary fix because
4833 if %g1 can hold a function result, then sparc_expand_epilogue will
4834 lose (the result will be clobbered). */
4835 rtx new_base = gen_rtx_REG (Pmode, 1);
4836 emit_move_insn (new_base, GEN_INT (offset));
4837 emit_insn (gen_rtx_SET (VOIDmode,
4838 new_base, gen_rtx_PLUS (Pmode, base, new_base)));
4842 /* Emit code to save/restore call-saved global and FP registers. */
4845 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action)
4847 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095)
4849 base = emit_adjust_base_to_offset (base, offset);
4854 = emit_save_or_restore_regs (0, 8, base, offset, 0,
4855 save_global_or_fp_reg_p, action, SORR_NONE);
4856 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0,
4857 save_global_or_fp_reg_p, action, SORR_NONE);
4860 /* Emit code to save/restore call-saved local and in registers. */
4863 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action)
4865 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095)
4867 base = emit_adjust_base_to_offset (base, offset);
4871 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p,
4872 save_local_or_in_reg_p, action, SORR_ADVANCE);
4875 /* Emit a window_save insn. */
4878 emit_window_save (rtx increment)
4880 rtx insn = emit_insn (gen_window_save (increment));
4881 RTX_FRAME_RELATED_P (insn) = 1;
4883 /* The incoming return address (%o7) is saved in %i7. */
4884 add_reg_note (insn, REG_CFA_REGISTER,
4885 gen_rtx_SET (VOIDmode,
4886 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM),
4888 INCOMING_RETURN_ADDR_REGNUM)));
4890 /* The window save event. */
4891 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx);
4893 /* The CFA is %fp, the hard frame pointer. */
4894 add_reg_note (insn, REG_CFA_DEF_CFA,
4895 plus_constant (hard_frame_pointer_rtx,
4896 INCOMING_FRAME_SP_OFFSET));
4901 /* Generate an increment for the stack pointer. */
4904 gen_stack_pointer_inc (rtx increment)
4906 return gen_rtx_SET (VOIDmode,
4908 gen_rtx_PLUS (Pmode,
4913 /* Generate a decrement for the stack pointer. */
4916 gen_stack_pointer_dec (rtx decrement)
4918 return gen_rtx_SET (VOIDmode,
4920 gen_rtx_MINUS (Pmode,
4925 /* Expand the function prologue. The prologue is responsible for reserving
4926 storage for the frame, saving the call-saved registers and loading the
4927 GOT register if needed. */
4930 sparc_expand_prologue (void)
4935 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4936 on the final value of the flag means deferring the prologue/epilogue
4937 expansion until just before the second scheduling pass, which is too
4938 late to emit multiple epilogues or return insns.
4940 Of course we are making the assumption that the value of the flag
4941 will not change between now and its final value. Of the three parts
4942 of the formula, only the last one can reasonably vary. Let's take a
4943 closer look, after assuming that the first two ones are set to true
4944 (otherwise the last value is effectively silenced).
4946 If only_leaf_regs_used returns false, the global predicate will also
4947 be false so the actual frame size calculated below will be positive.
4948 As a consequence, the save_register_window insn will be emitted in
4949 the instruction stream; now this insn explicitly references %fp
4950 which is not a leaf register so only_leaf_regs_used will always
4951 return false subsequently.
4953 If only_leaf_regs_used returns true, we hope that the subsequent
4954 optimization passes won't cause non-leaf registers to pop up. For
4955 example, the regrename pass has special provisions to not rename to
4956 non-leaf registers in a leaf function. */
4957 sparc_leaf_function_p
4958 = optimize > 0 && current_function_is_leaf && only_leaf_regs_used ();
4960 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4962 if (flag_stack_usage_info)
4963 current_function_static_stack_size = size;
4965 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
4966 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
4970 else if (sparc_leaf_function_p)
4972 rtx size_int_rtx = GEN_INT (-size);
4975 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
4976 else if (size <= 8192)
4978 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4979 RTX_FRAME_RELATED_P (insn) = 1;
4981 /* %sp is still the CFA register. */
4982 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
4986 rtx size_rtx = gen_rtx_REG (Pmode, 1);
4987 emit_move_insn (size_rtx, size_int_rtx);
4988 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
4989 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4990 gen_stack_pointer_inc (size_int_rtx));
4993 RTX_FRAME_RELATED_P (insn) = 1;
4997 rtx size_int_rtx = GEN_INT (-size);
5000 emit_window_save (size_int_rtx);
5001 else if (size <= 8192)
5003 emit_window_save (GEN_INT (-4096));
5005 /* %sp is not the CFA register anymore. */
5006 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5008 /* Make sure no %fp-based store is issued until after the frame is
5009 established. The offset between the frame pointer and the stack
5010 pointer is calculated relative to the value of the stack pointer
5011 at the end of the function prologue, and moving instructions that
5012 access the stack via the frame pointer between the instructions
5013 that decrement the stack pointer could result in accessing the
5014 register window save area, which is volatile. */
5015 emit_insn (gen_frame_blockage ());
5019 rtx size_rtx = gen_rtx_REG (Pmode, 1);
5020 emit_move_insn (size_rtx, size_int_rtx);
5021 emit_window_save (size_rtx);
5025 if (sparc_leaf_function_p)
5027 sparc_frame_base_reg = stack_pointer_rtx;
5028 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5032 sparc_frame_base_reg = hard_frame_pointer_rtx;
5033 sparc_frame_base_offset = SPARC_STACK_BIAS;
5036 if (sparc_n_global_fp_regs > 0)
5037 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5038 sparc_frame_base_offset
5039 - sparc_apparent_frame_size,
5042 /* Load the GOT register if needed. */
5043 if (crtl->uses_pic_offset_table)
5044 load_got_register ();
5046 /* Advertise that the data calculated just above are now valid. */
5047 sparc_prologue_data_valid_p = true;
5050 /* Expand the function prologue. The prologue is responsible for reserving
5051 storage for the frame, saving the call-saved registers and loading the
5052 GOT register if needed. */
5055 sparc_flat_expand_prologue (void)
5060 sparc_leaf_function_p = optimize > 0 && current_function_is_leaf;
5062 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
5064 if (flag_stack_usage_info)
5065 current_function_static_stack_size = size;
5067 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
5068 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
5070 if (sparc_save_local_in_regs_p)
5071 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS,
5078 rtx size_int_rtx, size_rtx;
5080 size_rtx = size_int_rtx = GEN_INT (-size);
5082 /* We establish the frame (i.e. decrement the stack pointer) first, even
5083 if we use a frame pointer, because we cannot clobber any call-saved
5084 registers, including the frame pointer, if we haven't created a new
5085 register save area, for the sake of compatibility with the ABI. */
5087 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx));
5088 else if (size <= 8192 && !frame_pointer_needed)
5090 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5091 RTX_FRAME_RELATED_P (insn) = 1;
5092 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size)));
5096 size_rtx = gen_rtx_REG (Pmode, 1);
5097 emit_move_insn (size_rtx, size_int_rtx);
5098 insn = emit_insn (gen_stack_pointer_inc (size_rtx));
5099 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5100 gen_stack_pointer_inc (size_int_rtx));
5102 RTX_FRAME_RELATED_P (insn) = 1;
5104 /* Ensure nothing is scheduled until after the frame is established. */
5105 emit_insn (gen_blockage ());
5107 if (frame_pointer_needed)
5109 insn = emit_insn (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5110 gen_rtx_MINUS (Pmode,
5113 RTX_FRAME_RELATED_P (insn) = 1;
5115 add_reg_note (insn, REG_CFA_ADJUST_CFA,
5116 gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
5117 plus_constant (stack_pointer_rtx,
5121 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5123 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM);
5124 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
5126 insn = emit_move_insn (i7, o7);
5127 RTX_FRAME_RELATED_P (insn) = 1;
5129 add_reg_note (insn, REG_CFA_REGISTER,
5130 gen_rtx_SET (VOIDmode, i7, o7));
5132 /* Prevent this instruction from ever being considered dead,
5133 even if this function has no epilogue. */
5134 emit_insn (gen_rtx_USE (VOIDmode, i7));
5138 if (frame_pointer_needed)
5140 sparc_frame_base_reg = hard_frame_pointer_rtx;
5141 sparc_frame_base_offset = SPARC_STACK_BIAS;
5145 sparc_frame_base_reg = stack_pointer_rtx;
5146 sparc_frame_base_offset = size + SPARC_STACK_BIAS;
5149 if (sparc_n_global_fp_regs > 0)
5150 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5151 sparc_frame_base_offset
5152 - sparc_apparent_frame_size,
5155 /* Load the GOT register if needed. */
5156 if (crtl->uses_pic_offset_table)
5157 load_got_register ();
5159 /* Advertise that the data calculated just above are now valid. */
5160 sparc_prologue_data_valid_p = true;
5163 /* This function generates the assembly code for function entry, which boils
5164 down to emitting the necessary .register directives. */
5167 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5169 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5171 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs);
5173 sparc_output_scratch_registers (file);
5176 /* Expand the function epilogue, either normal or part of a sibcall.
5177 We emit all the instructions except the return or the call. */
5180 sparc_expand_epilogue (bool for_eh)
5182 HOST_WIDE_INT size = sparc_frame_size;
5184 if (sparc_n_global_fp_regs > 0)
5185 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5186 sparc_frame_base_offset
5187 - sparc_apparent_frame_size,
5190 if (size == 0 || for_eh)
5192 else if (sparc_leaf_function_p)
5195 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5196 else if (size <= 8192)
5198 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5199 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5203 rtx reg = gen_rtx_REG (Pmode, 1);
5204 emit_move_insn (reg, GEN_INT (-size));
5205 emit_insn (gen_stack_pointer_dec (reg));
5210 /* Expand the function epilogue, either normal or part of a sibcall.
5211 We emit all the instructions except the return or the call. */
5214 sparc_flat_expand_epilogue (bool for_eh)
5216 HOST_WIDE_INT size = sparc_frame_size;
5218 if (sparc_n_global_fp_regs > 0)
5219 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
5220 sparc_frame_base_offset
5221 - sparc_apparent_frame_size,
5224 /* If we have a frame pointer, we'll need both to restore it before the
5225 frame is destroyed and use its current value in destroying the frame.
5226 Since we don't have an atomic way to do that in the flat window model,
5227 we save the current value into a temporary register (%g1). */
5228 if (frame_pointer_needed && !for_eh)
5229 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx);
5231 if (return_addr_reg_needed_p (sparc_leaf_function_p))
5232 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM),
5233 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM));
5235 if (sparc_save_local_in_regs_p)
5236 emit_save_or_restore_local_in_regs (sparc_frame_base_reg,
5237 sparc_frame_base_offset,
5240 if (size == 0 || for_eh)
5242 else if (frame_pointer_needed)
5244 /* Make sure the frame is destroyed after everything else is done. */
5245 emit_insn (gen_blockage ());
5247 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1));
5252 emit_insn (gen_blockage ());
5255 emit_insn (gen_stack_pointer_dec (GEN_INT (-size)));
5256 else if (size <= 8192)
5258 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5259 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size)));
5263 rtx reg = gen_rtx_REG (Pmode, 1);
5264 emit_move_insn (reg, GEN_INT (-size));
5265 emit_insn (gen_stack_pointer_dec (reg));
5270 /* Return true if it is appropriate to emit `return' instructions in the
5271 body of a function. */
5274 sparc_can_use_return_insn_p (void)
5276 return sparc_prologue_data_valid_p
5277 && sparc_n_global_fp_regs == 0
5279 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p)
5280 : (sparc_frame_size == 0 || !sparc_leaf_function_p);
5283 /* This function generates the assembly code for function exit. */
5286 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5288 /* If the last two instructions of a function are "call foo; dslot;"
5289 the return address might point to the first instruction in the next
5290 function and we have to output a dummy nop for the sake of sane
5291 backtraces in such cases. This is pointless for sibling calls since
5292 the return address is explicitly adjusted. */
5294 rtx insn, last_real_insn;
5296 insn = get_last_insn ();
5298 last_real_insn = prev_real_insn (insn);
5300 && GET_CODE (last_real_insn) == INSN
5301 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
5302 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
5305 && CALL_P (last_real_insn)
5306 && !SIBLING_CALL_P (last_real_insn))
5307 fputs("\tnop\n", file);
5309 sparc_output_deferred_case_vectors ();
5312 /* Output a 'restore' instruction. */
5315 output_restore (rtx pat)
5321 fputs ("\t restore\n", asm_out_file);
5325 gcc_assert (GET_CODE (pat) == SET);
5327 operands[0] = SET_DEST (pat);
5328 pat = SET_SRC (pat);
5330 switch (GET_CODE (pat))
5333 operands[1] = XEXP (pat, 0);
5334 operands[2] = XEXP (pat, 1);
5335 output_asm_insn (" restore %r1, %2, %Y0", operands);
5338 operands[1] = XEXP (pat, 0);
5339 operands[2] = XEXP (pat, 1);
5340 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
5343 operands[1] = XEXP (pat, 0);
5344 gcc_assert (XEXP (pat, 1) == const1_rtx);
5345 output_asm_insn (" restore %r1, %r1, %Y0", operands);
5349 output_asm_insn (" restore %%g0, %1, %Y0", operands);
5354 /* Output a return. */
5357 output_return (rtx insn)
5359 if (crtl->calls_eh_return)
5361 /* If the function uses __builtin_eh_return, the eh_return
5362 machinery occupies the delay slot. */
5363 gcc_assert (!final_sequence);
5365 if (flag_delayed_branch)
5367 if (!TARGET_FLAT && TARGET_V9)
5368 fputs ("\treturn\t%i7+8\n", asm_out_file);
5372 fputs ("\trestore\n", asm_out_file);
5374 fputs ("\tjmp\t%o7+8\n", asm_out_file);
5377 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
5382 fputs ("\trestore\n", asm_out_file);
5384 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file);
5385 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file);
5388 else if (sparc_leaf_function_p || TARGET_FLAT)
5390 /* This is a leaf or flat function so we don't have to bother restoring
5391 the register window, which frees us from dealing with the convoluted
5392 semantics of restore/return. We simply output the jump to the
5393 return address and the insn in the delay slot (if any). */
5395 return "jmp\t%%o7+%)%#";
5399 /* This is a regular function so we have to restore the register window.
5400 We may have a pending insn for the delay slot, which will be either
5401 combined with the 'restore' instruction or put in the delay slot of
5402 the 'return' instruction. */
5408 delay = NEXT_INSN (insn);
5411 pat = PATTERN (delay);
5413 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
5415 epilogue_renumber (&pat, 0);
5416 return "return\t%%i7+%)%#";
5420 output_asm_insn ("jmp\t%%i7+%)", NULL);
5421 output_restore (pat);
5422 PATTERN (delay) = gen_blockage ();
5423 INSN_CODE (delay) = -1;
5428 /* The delay slot is empty. */
5430 return "return\t%%i7+%)\n\t nop";
5431 else if (flag_delayed_branch)
5432 return "jmp\t%%i7+%)\n\t restore";
5434 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5441 /* Output a sibling call. */
5444 output_sibcall (rtx insn, rtx call_operand)
5448 gcc_assert (flag_delayed_branch);
5450 operands[0] = call_operand;
5452 if (sparc_leaf_function_p || TARGET_FLAT)
5454 /* This is a leaf or flat function so we don't have to bother restoring
5455 the register window. We simply output the jump to the function and
5456 the insn in the delay slot (if any). */
5458 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence));
5461 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5464 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5465 it into branch if possible. */
5466 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5471 /* This is a regular function so we have to restore the register window.
5472 We may have a pending insn for the delay slot, which will be combined
5473 with the 'restore' instruction. */
5475 output_asm_insn ("call\t%a0, 0", operands);
5479 rtx delay = NEXT_INSN (insn);
5482 output_restore (PATTERN (delay));
5484 PATTERN (delay) = gen_blockage ();
5485 INSN_CODE (delay) = -1;
5488 output_restore (NULL_RTX);
5494 /* Functions for handling argument passing.
5496 For 32-bit, the first 6 args are normally in registers and the rest are
5497 pushed. Any arg that starts within the first 6 words is at least
5498 partially passed in a register unless its data type forbids.
5500 For 64-bit, the argument registers are laid out as an array of 16 elements
5501 and arguments are added sequentially. The first 6 int args and up to the
5502 first 16 fp args (depending on size) are passed in regs.
5504 Slot Stack Integral Float Float in structure Double Long Double
5505 ---- ----- -------- ----- ------------------ ------ -----------
5506 15 [SP+248] %f31 %f30,%f31 %d30
5507 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5508 13 [SP+232] %f27 %f26,%f27 %d26
5509 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5510 11 [SP+216] %f23 %f22,%f23 %d22
5511 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5512 9 [SP+200] %f19 %f18,%f19 %d18
5513 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5514 7 [SP+184] %f15 %f14,%f15 %d14
5515 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5516 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5517 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5518 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5519 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5520 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5521 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5523 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5525 Integral arguments are always passed as 64-bit quantities appropriately
5528 Passing of floating point values is handled as follows.
5529 If a prototype is in scope:
5530 If the value is in a named argument (i.e. not a stdarg function or a
5531 value not part of the `...') then the value is passed in the appropriate
5533 If the value is part of the `...' and is passed in one of the first 6
5534 slots then the value is passed in the appropriate int reg.
5535 If the value is part of the `...' and is not passed in one of the first 6
5536 slots then the value is passed in memory.
5537 If a prototype is not in scope:
5538 If the value is one of the first 6 arguments the value is passed in the
5539 appropriate integer reg and the appropriate fp reg.
5540 If the value is not one of the first 6 arguments the value is passed in
5541 the appropriate fp reg and in memory.
5544 Summary of the calling conventions implemented by GCC on the SPARC:
5547 size argument return value
5549 small integer <4 int. reg. int. reg.
5550 word 4 int. reg. int. reg.
5551 double word 8 int. reg. int. reg.
5553 _Complex small integer <8 int. reg. int. reg.
5554 _Complex word 8 int. reg. int. reg.
5555 _Complex double word 16 memory int. reg.
5557 vector integer <=8 int. reg. FP reg.
5558 vector integer >8 memory memory
5560 float 4 int. reg. FP reg.
5561 double 8 int. reg. FP reg.
5562 long double 16 memory memory
5564 _Complex float 8 memory FP reg.
5565 _Complex double 16 memory FP reg.
5566 _Complex long double 32 memory FP reg.
5568 vector float any memory memory
5570 aggregate any memory memory
5575 size argument return value
5577 small integer <8 int. reg. int. reg.
5578 word 8 int. reg. int. reg.
5579 double word 16 int. reg. int. reg.
5581 _Complex small integer <16 int. reg. int. reg.
5582 _Complex word 16 int. reg. int. reg.
5583 _Complex double word 32 memory int. reg.
5585 vector integer <=16 FP reg. FP reg.
5586 vector integer 16<s<=32 memory FP reg.
5587 vector integer >32 memory memory
5589 float 4 FP reg. FP reg.
5590 double 8 FP reg. FP reg.
5591 long double 16 FP reg. FP reg.
5593 _Complex float 8 FP reg. FP reg.
5594 _Complex double 16 FP reg. FP reg.
5595 _Complex long double 32 memory FP reg.
5597 vector float <=16 FP reg. FP reg.
5598 vector float 16<s<=32 memory FP reg.
5599 vector float >32 memory memory
5601 aggregate <=16 reg. reg.
5602 aggregate 16<s<=32 memory reg.
5603 aggregate >32 memory memory
5607 Note #1: complex floating-point types follow the extended SPARC ABIs as
5608 implemented by the Sun compiler.
5610 Note #2: integral vector types follow the scalar floating-point types
5611 conventions to match what is implemented by the Sun VIS SDK.
5613 Note #3: floating-point vector types follow the aggregate types
5617 /* Maximum number of int regs for args. */
5618 #define SPARC_INT_ARG_MAX 6
5619 /* Maximum number of fp regs for args. */
5620 #define SPARC_FP_ARG_MAX 16
5622 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5624 /* Handle the INIT_CUMULATIVE_ARGS macro.
5625 Initialize a variable CUM of type CUMULATIVE_ARGS
5626 for a call to a function whose data type is FNTYPE.
5627 For a library call, FNTYPE is 0. */
5630 init_cumulative_args (struct sparc_args *cum, tree fntype,
5631 rtx libname ATTRIBUTE_UNUSED,
5632 tree fndecl ATTRIBUTE_UNUSED)
5635 cum->prototype_p = fntype && prototype_p (fntype);
5636 cum->libcall_p = fntype == 0;
5639 /* Handle promotion of pointer and integer arguments. */
5641 static enum machine_mode
5642 sparc_promote_function_mode (const_tree type,
5643 enum machine_mode mode,
5645 const_tree fntype ATTRIBUTE_UNUSED,
5646 int for_return ATTRIBUTE_UNUSED)
5648 if (type != NULL_TREE && POINTER_TYPE_P (type))
5650 *punsignedp = POINTERS_EXTEND_UNSIGNED;
5654 /* Integral arguments are passed as full words, as per the ABI. */
5655 if (GET_MODE_CLASS (mode) == MODE_INT
5656 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5662 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5665 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5667 return TARGET_ARCH64 ? true : false;
5670 /* Scan the record type TYPE and return the following predicates:
5671 - INTREGS_P: the record contains at least one field or sub-field
5672 that is eligible for promotion in integer registers.
5673 - FP_REGS_P: the record contains at least one field or sub-field
5674 that is eligible for promotion in floating-point registers.
5675 - PACKED_P: the record contains at least one field that is packed.
5677 Sub-fields are not taken into account for the PACKED_P predicate. */
5680 scan_record_type (const_tree type, int *intregs_p, int *fpregs_p,
5685 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5687 if (TREE_CODE (field) == FIELD_DECL)
5689 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5690 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5691 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5692 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5698 if (packed_p && DECL_PACKED (field))
5704 /* Compute the slot number to pass an argument in.
5705 Return the slot number or -1 if passing on the stack.
5707 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5708 the preceding args and about the function being called.
5709 MODE is the argument's machine mode.
5710 TYPE is the data type of the argument (as a tree).
5711 This is null for libcalls where that information may
5713 NAMED is nonzero if this argument is a named parameter
5714 (otherwise it is an extra parameter matching an ellipsis).
5715 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5716 *PREGNO records the register number to use if scalar type.
5717 *PPADDING records the amount of padding needed in words. */
5720 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5721 const_tree type, bool named, bool incoming_p,
5722 int *pregno, int *ppadding)
5724 int regbase = (incoming_p
5725 ? SPARC_INCOMING_INT_ARG_FIRST
5726 : SPARC_OUTGOING_INT_ARG_FIRST);
5727 int slotno = cum->words;
5728 enum mode_class mclass;
5733 if (type && TREE_ADDRESSABLE (type))
5739 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5742 /* For SPARC64, objects requiring 16-byte alignment get it. */
5744 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
5745 && (slotno & 1) != 0)
5746 slotno++, *ppadding = 1;
5748 mclass = GET_MODE_CLASS (mode);
5749 if (type && TREE_CODE (type) == VECTOR_TYPE)
5751 /* Vector types deserve special treatment because they are
5752 polymorphic wrt their mode, depending upon whether VIS
5753 instructions are enabled. */
5754 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5756 /* The SPARC port defines no floating-point vector modes. */
5757 gcc_assert (mode == BLKmode);
5761 /* Integral vector types should either have a vector
5762 mode or an integral mode, because we are guaranteed
5763 by pass_by_reference that their size is not greater
5764 than 16 bytes and TImode is 16-byte wide. */
5765 gcc_assert (mode != BLKmode);
5767 /* Vector integers are handled like floats according to
5769 mclass = MODE_FLOAT;
5776 case MODE_COMPLEX_FLOAT:
5777 case MODE_VECTOR_INT:
5778 if (TARGET_ARCH64 && TARGET_FPU && named)
5780 if (slotno >= SPARC_FP_ARG_MAX)
5782 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5783 /* Arguments filling only one single FP register are
5784 right-justified in the outer double FP register. */
5785 if (GET_MODE_SIZE (mode) <= 4)
5792 case MODE_COMPLEX_INT:
5793 if (slotno >= SPARC_INT_ARG_MAX)
5795 regno = regbase + slotno;
5799 if (mode == VOIDmode)
5800 /* MODE is VOIDmode when generating the actual call. */
5803 gcc_assert (mode == BLKmode);
5807 || (TREE_CODE (type) != VECTOR_TYPE
5808 && TREE_CODE (type) != RECORD_TYPE))
5810 if (slotno >= SPARC_INT_ARG_MAX)
5812 regno = regbase + slotno;
5814 else /* TARGET_ARCH64 && type */
5816 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5818 /* First see what kinds of registers we would need. */
5819 if (TREE_CODE (type) == VECTOR_TYPE)
5822 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5824 /* The ABI obviously doesn't specify how packed structures
5825 are passed. These are defined to be passed in int regs
5826 if possible, otherwise memory. */
5827 if (packed_p || !named)
5828 fpregs_p = 0, intregs_p = 1;
5830 /* If all arg slots are filled, then must pass on stack. */
5831 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5834 /* If there are only int args and all int arg slots are filled,
5835 then must pass on stack. */
5836 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5839 /* Note that even if all int arg slots are filled, fp members may
5840 still be passed in regs if such regs are available.
5841 *PREGNO isn't set because there may be more than one, it's up
5842 to the caller to compute them. */
5855 /* Handle recursive register counting for structure field layout. */
5857 struct function_arg_record_value_parms
5859 rtx ret; /* return expression being built. */
5860 int slotno; /* slot number of the argument. */
5861 int named; /* whether the argument is named. */
5862 int regbase; /* regno of the base register. */
5863 int stack; /* 1 if part of the argument is on the stack. */
5864 int intoffset; /* offset of the first pending integer field. */
5865 unsigned int nregs; /* number of words passed in registers. */
5868 static void function_arg_record_value_3
5869 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5870 static void function_arg_record_value_2
5871 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5872 static void function_arg_record_value_1
5873 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5874 static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int);
5875 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5877 /* A subroutine of function_arg_record_value. Traverse the structure
5878 recursively and determine how many registers will be required. */
5881 function_arg_record_value_1 (const_tree type, HOST_WIDE_INT startbitpos,
5882 struct function_arg_record_value_parms *parms,
5887 /* We need to compute how many registers are needed so we can
5888 allocate the PARALLEL but before we can do that we need to know
5889 whether there are any packed fields. The ABI obviously doesn't
5890 specify how structures are passed in this case, so they are
5891 defined to be passed in int regs if possible, otherwise memory,
5892 regardless of whether there are fp values present. */
5895 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5897 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5904 /* Compute how many registers we need. */
5905 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5907 if (TREE_CODE (field) == FIELD_DECL)
5909 HOST_WIDE_INT bitpos = startbitpos;
5911 if (DECL_SIZE (field) != 0)
5913 if (integer_zerop (DECL_SIZE (field)))
5916 if (host_integerp (bit_position (field), 1))
5917 bitpos += int_bit_position (field);
5920 /* ??? FIXME: else assume zero offset. */
5922 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5923 function_arg_record_value_1 (TREE_TYPE (field),
5927 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5928 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5933 if (parms->intoffset != -1)
5935 unsigned int startbit, endbit;
5936 int intslots, this_slotno;
5938 startbit = parms->intoffset & -BITS_PER_WORD;
5939 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5941 intslots = (endbit - startbit) / BITS_PER_WORD;
5942 this_slotno = parms->slotno + parms->intoffset
5945 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5947 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5948 /* We need to pass this field on the stack. */
5952 parms->nregs += intslots;
5953 parms->intoffset = -1;
5956 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5957 If it wasn't true we wouldn't be here. */
5958 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5959 && DECL_MODE (field) == BLKmode)
5960 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5961 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5968 if (parms->intoffset == -1)
5969 parms->intoffset = bitpos;
5975 /* A subroutine of function_arg_record_value. Assign the bits of the
5976 structure between parms->intoffset and bitpos to integer registers. */
5979 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5980 struct function_arg_record_value_parms *parms)
5982 enum machine_mode mode;
5984 unsigned int startbit, endbit;
5985 int this_slotno, intslots, intoffset;
5988 if (parms->intoffset == -1)
5991 intoffset = parms->intoffset;
5992 parms->intoffset = -1;
5994 startbit = intoffset & -BITS_PER_WORD;
5995 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5996 intslots = (endbit - startbit) / BITS_PER_WORD;
5997 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5999 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
6003 /* If this is the trailing part of a word, only load that much into
6004 the register. Otherwise load the whole register. Note that in
6005 the latter case we may pick up unwanted bits. It's not a problem
6006 at the moment but may wish to revisit. */
6008 if (intoffset % BITS_PER_WORD != 0)
6009 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
6014 intoffset /= BITS_PER_UNIT;
6017 regno = parms->regbase + this_slotno;
6018 reg = gen_rtx_REG (mode, regno);
6019 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6020 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
6023 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
6028 while (intslots > 0);
6031 /* A subroutine of function_arg_record_value. Traverse the structure
6032 recursively and assign bits to floating point registers. Track which
6033 bits in between need integer registers; invoke function_arg_record_value_3
6034 to make that happen. */
6037 function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos,
6038 struct function_arg_record_value_parms *parms,
6044 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6046 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
6053 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
6055 if (TREE_CODE (field) == FIELD_DECL)
6057 HOST_WIDE_INT bitpos = startbitpos;
6059 if (DECL_SIZE (field) != 0)
6061 if (integer_zerop (DECL_SIZE (field)))
6064 if (host_integerp (bit_position (field), 1))
6065 bitpos += int_bit_position (field);
6068 /* ??? FIXME: else assume zero offset. */
6070 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
6071 function_arg_record_value_2 (TREE_TYPE (field),
6075 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
6076 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6081 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
6082 int regno, nregs, pos;
6083 enum machine_mode mode = DECL_MODE (field);
6086 function_arg_record_value_3 (bitpos, parms);
6088 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
6091 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6092 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
6094 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
6096 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
6102 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
6103 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
6105 reg = gen_rtx_REG (mode, regno);
6106 pos = bitpos / BITS_PER_UNIT;
6107 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6108 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6112 regno += GET_MODE_SIZE (mode) / 4;
6113 reg = gen_rtx_REG (mode, regno);
6114 pos += GET_MODE_SIZE (mode);
6115 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
6116 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
6122 if (parms->intoffset == -1)
6123 parms->intoffset = bitpos;
6129 /* Used by function_arg and sparc_function_value_1 to implement the complex
6130 conventions of the 64-bit ABI for passing and returning structures.
6131 Return an expression valid as a return value for the FUNCTION_ARG
6132 and TARGET_FUNCTION_VALUE.
6134 TYPE is the data type of the argument (as a tree).
6135 This is null for libcalls where that information may
6137 MODE is the argument's machine mode.
6138 SLOTNO is the index number of the argument's slot in the parameter array.
6139 NAMED is nonzero if this argument is a named parameter
6140 (otherwise it is an extra parameter matching an ellipsis).
6141 REGBASE is the regno of the base register for the parameter array. */
6144 function_arg_record_value (const_tree type, enum machine_mode mode,
6145 int slotno, int named, int regbase)
6147 HOST_WIDE_INT typesize = int_size_in_bytes (type);
6148 struct function_arg_record_value_parms parms;
6151 parms.ret = NULL_RTX;
6152 parms.slotno = slotno;
6153 parms.named = named;
6154 parms.regbase = regbase;
6157 /* Compute how many registers we need. */
6159 parms.intoffset = 0;
6160 function_arg_record_value_1 (type, 0, &parms, false);
6162 /* Take into account pending integer fields. */
6163 if (parms.intoffset != -1)
6165 unsigned int startbit, endbit;
6166 int intslots, this_slotno;
6168 startbit = parms.intoffset & -BITS_PER_WORD;
6169 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
6170 intslots = (endbit - startbit) / BITS_PER_WORD;
6171 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
6173 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
6175 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
6176 /* We need to pass this field on the stack. */
6180 parms.nregs += intslots;
6182 nregs = parms.nregs;
6184 /* Allocate the vector and handle some annoying special cases. */
6187 /* ??? Empty structure has no value? Duh? */
6190 /* Though there's nothing really to store, return a word register
6191 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6192 leads to breakage due to the fact that there are zero bytes to
6194 return gen_rtx_REG (mode, regbase);
6198 /* ??? C++ has structures with no fields, and yet a size. Give up
6199 for now and pass everything back in integer registers. */
6200 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6202 if (nregs + slotno > SPARC_INT_ARG_MAX)
6203 nregs = SPARC_INT_ARG_MAX - slotno;
6205 gcc_assert (nregs != 0);
6207 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
6209 /* If at least one field must be passed on the stack, generate
6210 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6211 also be passed on the stack. We can't do much better because the
6212 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6213 of structures for which the fields passed exclusively in registers
6214 are not at the beginning of the structure. */
6216 XVECEXP (parms.ret, 0, 0)
6217 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6219 /* Fill in the entries. */
6221 parms.intoffset = 0;
6222 function_arg_record_value_2 (type, 0, &parms, false);
6223 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
6225 gcc_assert (parms.nregs == nregs);
6230 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6231 of the 64-bit ABI for passing and returning unions.
6232 Return an expression valid as a return value for the FUNCTION_ARG
6233 and TARGET_FUNCTION_VALUE.
6235 SIZE is the size in bytes of the union.
6236 MODE is the argument's machine mode.
6237 REGNO is the hard register the union will be passed in. */
6240 function_arg_union_value (int size, enum machine_mode mode, int slotno,
6243 int nwords = ROUND_ADVANCE (size), i;
6246 /* See comment in previous function for empty structures. */
6248 return gen_rtx_REG (mode, regno);
6250 if (slotno == SPARC_INT_ARG_MAX - 1)
6253 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
6255 for (i = 0; i < nwords; i++)
6257 /* Unions are passed left-justified. */
6258 XVECEXP (regs, 0, i)
6259 = gen_rtx_EXPR_LIST (VOIDmode,
6260 gen_rtx_REG (word_mode, regno),
6261 GEN_INT (UNITS_PER_WORD * i));
6268 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6269 for passing and returning large (BLKmode) vectors.
6270 Return an expression valid as a return value for the FUNCTION_ARG
6271 and TARGET_FUNCTION_VALUE.
6273 SIZE is the size in bytes of the vector (at least 8 bytes).
6274 REGNO is the FP hard register the vector will be passed in. */
6277 function_arg_vector_value (int size, int regno)
6279 int i, nregs = size / 8;
6282 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
6284 for (i = 0; i < nregs; i++)
6286 XVECEXP (regs, 0, i)
6287 = gen_rtx_EXPR_LIST (VOIDmode,
6288 gen_rtx_REG (DImode, regno + 2*i),
6295 /* Determine where to put an argument to a function.
6296 Value is zero to push the argument on the stack,
6297 or a hard register in which to store the argument.
6299 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6300 the preceding args and about the function being called.
6301 MODE is the argument's machine mode.
6302 TYPE is the data type of the argument (as a tree).
6303 This is null for libcalls where that information may
6305 NAMED is true if this argument is a named parameter
6306 (otherwise it is an extra parameter matching an ellipsis).
6307 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6308 TARGET_FUNCTION_INCOMING_ARG. */
6311 sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
6312 const_tree type, bool named, bool incoming_p)
6314 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6316 int regbase = (incoming_p
6317 ? SPARC_INCOMING_INT_ARG_FIRST
6318 : SPARC_OUTGOING_INT_ARG_FIRST);
6319 int slotno, regno, padding;
6320 enum mode_class mclass = GET_MODE_CLASS (mode);
6322 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
6327 /* Vector types deserve special treatment because they are polymorphic wrt
6328 their mode, depending upon whether VIS instructions are enabled. */
6329 if (type && TREE_CODE (type) == VECTOR_TYPE)
6331 HOST_WIDE_INT size = int_size_in_bytes (type);
6332 gcc_assert ((TARGET_ARCH32 && size <= 8)
6333 || (TARGET_ARCH64 && size <= 16));
6335 if (mode == BLKmode)
6336 return function_arg_vector_value (size,
6337 SPARC_FP_ARG_FIRST + 2*slotno);
6339 mclass = MODE_FLOAT;
6343 return gen_rtx_REG (mode, regno);
6345 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6346 and are promoted to registers if possible. */
6347 if (type && TREE_CODE (type) == RECORD_TYPE)
6349 HOST_WIDE_INT size = int_size_in_bytes (type);
6350 gcc_assert (size <= 16);
6352 return function_arg_record_value (type, mode, slotno, named, regbase);
6355 /* Unions up to 16 bytes in size are passed in integer registers. */
6356 else if (type && TREE_CODE (type) == UNION_TYPE)
6358 HOST_WIDE_INT size = int_size_in_bytes (type);
6359 gcc_assert (size <= 16);
6361 return function_arg_union_value (size, mode, slotno, regno);
6364 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6365 but also have the slot allocated for them.
6366 If no prototype is in scope fp values in register slots get passed
6367 in two places, either fp regs and int regs or fp regs and memory. */
6368 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6369 && SPARC_FP_REG_P (regno))
6371 rtx reg = gen_rtx_REG (mode, regno);
6372 if (cum->prototype_p || cum->libcall_p)
6374 /* "* 2" because fp reg numbers are recorded in 4 byte
6377 /* ??? This will cause the value to be passed in the fp reg and
6378 in the stack. When a prototype exists we want to pass the
6379 value in the reg but reserve space on the stack. That's an
6380 optimization, and is deferred [for a bit]. */
6381 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
6382 return gen_rtx_PARALLEL (mode,
6384 gen_rtx_EXPR_LIST (VOIDmode,
6385 NULL_RTX, const0_rtx),
6386 gen_rtx_EXPR_LIST (VOIDmode,
6390 /* ??? It seems that passing back a register even when past
6391 the area declared by REG_PARM_STACK_SPACE will allocate
6392 space appropriately, and will not copy the data onto the
6393 stack, exactly as we desire.
6395 This is due to locate_and_pad_parm being called in
6396 expand_call whenever reg_parm_stack_space > 0, which
6397 while beneficial to our example here, would seem to be
6398 in error from what had been intended. Ho hum... -- r~ */
6406 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
6410 /* On incoming, we don't need to know that the value
6411 is passed in %f0 and %i0, and it confuses other parts
6412 causing needless spillage even on the simplest cases. */
6416 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
6417 + (regno - SPARC_FP_ARG_FIRST) / 2);
6419 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6420 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
6422 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6426 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
6427 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
6428 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
6433 /* All other aggregate types are passed in an integer register in a mode
6434 corresponding to the size of the type. */
6435 else if (type && AGGREGATE_TYPE_P (type))
6437 HOST_WIDE_INT size = int_size_in_bytes (type);
6438 gcc_assert (size <= 16);
6440 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6443 return gen_rtx_REG (mode, regno);
6446 /* Handle the TARGET_FUNCTION_ARG target hook. */
6449 sparc_function_arg (cumulative_args_t cum, enum machine_mode mode,
6450 const_tree type, bool named)
6452 return sparc_function_arg_1 (cum, mode, type, named, false);
6455 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6458 sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
6459 const_tree type, bool named)
6461 return sparc_function_arg_1 (cum, mode, type, named, true);
6464 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6467 sparc_function_arg_boundary (enum machine_mode mode, const_tree type)
6469 return ((TARGET_ARCH64
6470 && (GET_MODE_ALIGNMENT (mode) == 128
6471 || (type && TYPE_ALIGN (type) == 128)))
6476 /* For an arg passed partly in registers and partly in memory,
6477 this is the number of bytes of registers used.
6478 For args passed entirely in registers or entirely in memory, zero.
6480 Any arg that starts in the first 6 regs but won't entirely fit in them
6481 needs partial registers on v8. On v9, structures with integer
6482 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6483 values that begin in the last fp reg [where "last fp reg" varies with the
6484 mode] will be split between that reg and memory. */
6487 sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode,
6488 tree type, bool named)
6490 int slotno, regno, padding;
6492 /* We pass false for incoming_p here, it doesn't matter. */
6493 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
6494 false, ®no, &padding);
6501 if ((slotno + (mode == BLKmode
6502 ? ROUND_ADVANCE (int_size_in_bytes (type))
6503 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
6504 > SPARC_INT_ARG_MAX)
6505 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
6509 /* We are guaranteed by pass_by_reference that the size of the
6510 argument is not greater than 16 bytes, so we only need to return
6511 one word if the argument is partially passed in registers. */
6513 if (type && AGGREGATE_TYPE_P (type))
6515 int size = int_size_in_bytes (type);
6517 if (size > UNITS_PER_WORD
6518 && slotno == SPARC_INT_ARG_MAX - 1)
6519 return UNITS_PER_WORD;
6521 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
6522 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6523 && ! (TARGET_FPU && named)))
6525 /* The complex types are passed as packed types. */
6526 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6527 && slotno == SPARC_INT_ARG_MAX - 1)
6528 return UNITS_PER_WORD;
6530 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6532 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
6534 return UNITS_PER_WORD;
6541 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6542 Specify whether to pass the argument by reference. */
6545 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
6546 enum machine_mode mode, const_tree type,
6547 bool named ATTRIBUTE_UNUSED)
6550 /* Original SPARC 32-bit ABI says that structures and unions,
6551 and quad-precision floats are passed by reference. For Pascal,
6552 also pass arrays by reference. All other base types are passed
6555 Extended ABI (as implemented by the Sun compiler) says that all
6556 complex floats are passed by reference. Pass complex integers
6557 in registers up to 8 bytes. More generally, enforce the 2-word
6558 cap for passing arguments in registers.
6560 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6561 integers are passed like floats of the same size, that is in
6562 registers up to 8 bytes. Pass all vector floats by reference
6563 like structure and unions. */
6564 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
6566 /* Catch CDImode, TFmode, DCmode and TCmode. */
6567 || GET_MODE_SIZE (mode) > 8
6569 && TREE_CODE (type) == VECTOR_TYPE
6570 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6572 /* Original SPARC 64-bit ABI says that structures and unions
6573 smaller than 16 bytes are passed in registers, as well as
6574 all other base types.
6576 Extended ABI (as implemented by the Sun compiler) says that
6577 complex floats are passed in registers up to 16 bytes. Pass
6578 all complex integers in registers up to 16 bytes. More generally,
6579 enforce the 2-word cap for passing arguments in registers.
6581 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6582 integers are passed like floats of the same size, that is in
6583 registers (up to 16 bytes). Pass all vector floats like structure
6586 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
6587 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
6588 /* Catch CTImode and TCmode. */
6589 || GET_MODE_SIZE (mode) > 16);
6592 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6593 Update the data in CUM to advance over an argument
6594 of mode MODE and data type TYPE.
6595 TYPE is null for libcalls where that information may not be available. */
6598 sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
6599 const_tree type, bool named)
6601 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6604 /* We pass false for incoming_p here, it doesn't matter. */
6605 function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
6607 /* If argument requires leading padding, add it. */
6608 cum->words += padding;
6612 cum->words += (mode != BLKmode
6613 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6614 : ROUND_ADVANCE (int_size_in_bytes (type)));
6618 if (type && AGGREGATE_TYPE_P (type))
6620 int size = int_size_in_bytes (type);
6624 else if (size <= 16)
6626 else /* passed by reference */
6631 cum->words += (mode != BLKmode
6632 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
6633 : ROUND_ADVANCE (int_size_in_bytes (type)));
6638 /* Handle the FUNCTION_ARG_PADDING macro.
6639 For the 64 bit ABI structs are always stored left shifted in their
6643 function_arg_padding (enum machine_mode mode, const_tree type)
6645 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6648 /* Fall back to the default. */
6649 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6652 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6653 Specify whether to return the return value in memory. */
6656 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6659 /* Original SPARC 32-bit ABI says that structures and unions,
6660 and quad-precision floats are returned in memory. All other
6661 base types are returned in registers.
6663 Extended ABI (as implemented by the Sun compiler) says that
6664 all complex floats are returned in registers (8 FP registers
6665 at most for '_Complex long double'). Return all complex integers
6666 in registers (4 at most for '_Complex long long').
6668 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6669 integers are returned like floats of the same size, that is in
6670 registers up to 8 bytes and in memory otherwise. Return all
6671 vector floats in memory like structure and unions; note that
6672 they always have BLKmode like the latter. */
6673 return (TYPE_MODE (type) == BLKmode
6674 || TYPE_MODE (type) == TFmode
6675 || (TREE_CODE (type) == VECTOR_TYPE
6676 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6678 /* Original SPARC 64-bit ABI says that structures and unions
6679 smaller than 32 bytes are returned in registers, as well as
6680 all other base types.
6682 Extended ABI (as implemented by the Sun compiler) says that all
6683 complex floats are returned in registers (8 FP registers at most
6684 for '_Complex long double'). Return all complex integers in
6685 registers (4 at most for '_Complex TItype').
6687 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6688 integers are returned like floats of the same size, that is in
6689 registers. Return all vector floats like structure and unions;
6690 note that they always have BLKmode like the latter. */
6691 return (TYPE_MODE (type) == BLKmode
6692 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32);
6695 /* Handle the TARGET_STRUCT_VALUE target hook.
6696 Return where to find the structure return value address. */
6699 sparc_struct_value_rtx (tree fndecl, int incoming)
6708 mem = gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx,
6709 STRUCT_VALUE_OFFSET));
6711 mem = gen_frame_mem (Pmode, plus_constant (stack_pointer_rtx,
6712 STRUCT_VALUE_OFFSET));
6714 /* Only follow the SPARC ABI for fixed-size structure returns.
6715 Variable size structure returns are handled per the normal
6716 procedures in GCC. This is enabled by -mstd-struct-return */
6718 && sparc_std_struct_return
6719 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl))
6720 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST)
6722 /* We must check and adjust the return address, as it is
6723 optional as to whether the return object is really
6725 rtx ret_reg = gen_rtx_REG (Pmode, 31);
6726 rtx scratch = gen_reg_rtx (SImode);
6727 rtx endlab = gen_label_rtx ();
6729 /* Calculate the return object size */
6730 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl));
6731 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff);
6732 /* Construct a temporary return value */
6734 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0);
6736 /* Implement SPARC 32-bit psABI callee return struct checking:
6738 Fetch the instruction where we will return to and see if
6739 it's an unimp instruction (the most significant 10 bits
6741 emit_move_insn (scratch, gen_rtx_MEM (SImode,
6742 plus_constant (ret_reg, 8)));
6743 /* Assume the size is valid and pre-adjust */
6744 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4)));
6745 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode,
6747 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4)));
6748 /* Write the address of the memory pointed to by temp_val into
6749 the memory pointed to by mem */
6750 emit_move_insn (mem, XEXP (temp_val, 0));
6751 emit_label (endlab);
6758 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6759 For v9, function return values are subject to the same rules as arguments,
6760 except that up to 32 bytes may be returned in registers. */
6763 sparc_function_value_1 (const_tree type, enum machine_mode mode,
6766 /* Beware that the two values are swapped here wrt function_arg. */
6767 int regbase = (outgoing
6768 ? SPARC_INCOMING_INT_ARG_FIRST
6769 : SPARC_OUTGOING_INT_ARG_FIRST);
6770 enum mode_class mclass = GET_MODE_CLASS (mode);
6773 /* Vector types deserve special treatment because they are polymorphic wrt
6774 their mode, depending upon whether VIS instructions are enabled. */
6775 if (type && TREE_CODE (type) == VECTOR_TYPE)
6777 HOST_WIDE_INT size = int_size_in_bytes (type);
6778 gcc_assert ((TARGET_ARCH32 && size <= 8)
6779 || (TARGET_ARCH64 && size <= 32));
6781 if (mode == BLKmode)
6782 return function_arg_vector_value (size,
6783 SPARC_FP_ARG_FIRST);
6785 mclass = MODE_FLOAT;
6788 if (TARGET_ARCH64 && type)
6790 /* Structures up to 32 bytes in size are returned in registers. */
6791 if (TREE_CODE (type) == RECORD_TYPE)
6793 HOST_WIDE_INT size = int_size_in_bytes (type);
6794 gcc_assert (size <= 32);
6796 return function_arg_record_value (type, mode, 0, 1, regbase);
6799 /* Unions up to 32 bytes in size are returned in integer registers. */
6800 else if (TREE_CODE (type) == UNION_TYPE)
6802 HOST_WIDE_INT size = int_size_in_bytes (type);
6803 gcc_assert (size <= 32);
6805 return function_arg_union_value (size, mode, 0, regbase);
6808 /* Objects that require it are returned in FP registers. */
6809 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6812 /* All other aggregate types are returned in an integer register in a
6813 mode corresponding to the size of the type. */
6814 else if (AGGREGATE_TYPE_P (type))
6816 /* All other aggregate types are passed in an integer register
6817 in a mode corresponding to the size of the type. */
6818 HOST_WIDE_INT size = int_size_in_bytes (type);
6819 gcc_assert (size <= 32);
6821 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6823 /* ??? We probably should have made the same ABI change in
6824 3.4.0 as the one we made for unions. The latter was
6825 required by the SCD though, while the former is not
6826 specified, so we favored compatibility and efficiency.
6828 Now we're stuck for aggregates larger than 16 bytes,
6829 because OImode vanished in the meantime. Let's not
6830 try to be unduly clever, and simply follow the ABI
6831 for unions in that case. */
6832 if (mode == BLKmode)
6833 return function_arg_union_value (size, mode, 0, regbase);
6838 /* We should only have pointer and integer types at this point. This
6839 must match sparc_promote_function_mode. */
6840 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6844 /* We should only have pointer and integer types at this point. This must
6845 match sparc_promote_function_mode. */
6846 else if (TARGET_ARCH32
6847 && mclass == MODE_INT
6848 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6851 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU)
6852 regno = SPARC_FP_ARG_FIRST;
6856 return gen_rtx_REG (mode, regno);
6859 /* Handle TARGET_FUNCTION_VALUE.
6860 On the SPARC, the value is found in the first "output" register, but the
6861 called function leaves it in the first "input" register. */
6864 sparc_function_value (const_tree valtype,
6865 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
6868 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing);
6871 /* Handle TARGET_LIBCALL_VALUE. */
6874 sparc_libcall_value (enum machine_mode mode,
6875 const_rtx fun ATTRIBUTE_UNUSED)
6877 return sparc_function_value_1 (NULL_TREE, mode, false);
6880 /* Handle FUNCTION_VALUE_REGNO_P.
6881 On the SPARC, the first "output" reg is used for integer values, and the
6882 first floating point register is used for floating point values. */
6885 sparc_function_value_regno_p (const unsigned int regno)
6887 return (regno == 8 || regno == 32);
6890 /* Do what is necessary for `va_start'. We look at the current function
6891 to determine if stdarg or varargs is used and return the address of
6892 the first unnamed parameter. */
6895 sparc_builtin_saveregs (void)
6897 int first_reg = crtl->args.info.words;
6901 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6902 emit_move_insn (gen_rtx_MEM (word_mode,
6903 gen_rtx_PLUS (Pmode,
6905 GEN_INT (FIRST_PARM_OFFSET (0)
6908 gen_rtx_REG (word_mode,
6909 SPARC_INCOMING_INT_ARG_FIRST + regno));
6911 address = gen_rtx_PLUS (Pmode,
6913 GEN_INT (FIRST_PARM_OFFSET (0)
6914 + UNITS_PER_WORD * first_reg));
6919 /* Implement `va_start' for stdarg. */
6922 sparc_va_start (tree valist, rtx nextarg)
6924 nextarg = expand_builtin_saveregs ();
6925 std_expand_builtin_va_start (valist, nextarg);
6928 /* Implement `va_arg' for stdarg. */
6931 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6934 HOST_WIDE_INT size, rsize, align;
6937 tree ptrtype = build_pointer_type (type);
6939 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6942 size = rsize = UNITS_PER_WORD;
6948 size = int_size_in_bytes (type);
6949 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6954 /* For SPARC64, objects requiring 16-byte alignment get it. */
6955 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6956 align = 2 * UNITS_PER_WORD;
6958 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6959 are left-justified in their slots. */
6960 if (AGGREGATE_TYPE_P (type))
6963 size = rsize = UNITS_PER_WORD;
6973 incr = fold_build_pointer_plus_hwi (incr, align - 1);
6974 incr = fold_convert (sizetype, incr);
6975 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr,
6977 incr = fold_convert (ptr_type_node, incr);
6980 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6983 if (BYTES_BIG_ENDIAN && size < rsize)
6984 addr = fold_build_pointer_plus_hwi (incr, rsize - size);
6988 addr = fold_convert (build_pointer_type (ptrtype), addr);
6989 addr = build_va_arg_indirect_ref (addr);
6992 /* If the address isn't aligned properly for the type, we need a temporary.
6993 FIXME: This is inefficient, usually we can do this in registers. */
6994 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD)
6996 tree tmp = create_tmp_var (type, "va_arg_tmp");
6997 tree dest_addr = build_fold_addr_expr (tmp);
6998 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
6999 3, dest_addr, addr, size_int (rsize));
7000 TREE_ADDRESSABLE (tmp) = 1;
7001 gimplify_and_add (copy, pre_p);
7006 addr = fold_convert (ptrtype, addr);
7008 incr = fold_build_pointer_plus_hwi (incr, rsize);
7009 gimplify_assign (valist, incr, post_p);
7011 return build_va_arg_indirect_ref (addr);
7014 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7015 Specify whether the vector mode is supported by the hardware. */
7018 sparc_vector_mode_supported_p (enum machine_mode mode)
7020 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
7023 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7025 static enum machine_mode
7026 sparc_preferred_simd_mode (enum machine_mode mode)
7044 /* Return the string to output an unconditional branch to LABEL, which is
7045 the operand number of the label.
7047 DEST is the destination insn (i.e. the label), INSN is the source. */
7050 output_ubranch (rtx dest, int label, rtx insn)
7052 static char string[64];
7053 bool v9_form = false;
7056 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
7058 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7059 - INSN_ADDRESSES (INSN_UID (insn)));
7060 /* Leave some instructions for "slop". */
7061 if (delta >= -260000 && delta < 260000)
7066 strcpy (string, "ba%*,pt\t%%xcc, ");
7068 strcpy (string, "b%*\t");
7070 p = strchr (string, '\0');
7081 /* Return the string to output a conditional branch to LABEL, which is
7082 the operand number of the label. OP is the conditional expression.
7083 XEXP (OP, 0) is assumed to be a condition code register (integer or
7084 floating point) and its mode specifies what kind of comparison we made.
7086 DEST is the destination insn (i.e. the label), INSN is the source.
7088 REVERSED is nonzero if we should reverse the sense of the comparison.
7090 ANNUL is nonzero if we should generate an annulling branch. */
7093 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
7096 static char string[64];
7097 enum rtx_code code = GET_CODE (op);
7098 rtx cc_reg = XEXP (op, 0);
7099 enum machine_mode mode = GET_MODE (cc_reg);
7100 const char *labelno, *branch;
7101 int spaces = 8, far;
7104 /* v9 branches are limited to +-1MB. If it is too far away,
7117 fbne,a,pn %fcc2, .LC29
7125 far = TARGET_V9 && (get_attr_length (insn) >= 3);
7128 /* Reversal of FP compares takes care -- an ordered compare
7129 becomes an unordered compare and vice versa. */
7130 if (mode == CCFPmode || mode == CCFPEmode)
7131 code = reverse_condition_maybe_unordered (code);
7133 code = reverse_condition (code);
7136 /* Start by writing the branch condition. */
7137 if (mode == CCFPmode || mode == CCFPEmode)
7188 /* ??? !v9: FP branches cannot be preceded by another floating point
7189 insn. Because there is currently no concept of pre-delay slots,
7190 we can fix this only by always emitting a nop before a floating
7195 strcpy (string, "nop\n\t");
7196 strcat (string, branch);
7209 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7221 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
7242 strcpy (string, branch);
7244 spaces -= strlen (branch);
7245 p = strchr (string, '\0');
7247 /* Now add the annulling, the label, and a possible noop. */
7260 if (! far && insn && INSN_ADDRESSES_SET_P ())
7262 int delta = (INSN_ADDRESSES (INSN_UID (dest))
7263 - INSN_ADDRESSES (INSN_UID (insn)));
7264 /* Leave some instructions for "slop". */
7265 if (delta < -260000 || delta >= 260000)
7269 if (mode == CCFPmode || mode == CCFPEmode)
7271 static char v9_fcc_labelno[] = "%%fccX, ";
7272 /* Set the char indicating the number of the fcc reg to use. */
7273 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
7274 labelno = v9_fcc_labelno;
7277 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
7281 else if (mode == CCXmode || mode == CCX_NOOVmode)
7283 labelno = "%%xcc, ";
7288 labelno = "%%icc, ";
7293 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7296 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7309 strcpy (p, labelno);
7310 p = strchr (p, '\0');
7313 strcpy (p, ".+12\n\t nop\n\tb\t");
7314 /* Skip the next insn if requested or
7315 if we know that it will be a nop. */
7316 if (annul || ! final_sequence)
7330 /* Emit a library call comparison between floating point X and Y.
7331 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7332 Return the new operator to be used in the comparison sequence.
7334 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7335 values as arguments instead of the TFmode registers themselves,
7336 that's why we cannot call emit_float_lib_cmp. */
7339 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
7342 rtx slot0, slot1, result, tem, tem2, libfunc;
7343 enum machine_mode mode;
7344 enum rtx_code new_comparison;
7349 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq");
7353 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne");
7357 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt");
7361 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge");
7365 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt");
7369 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle");
7380 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp");
7393 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7394 emit_move_insn (slot0, x);
7401 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
7402 emit_move_insn (slot1, y);
7405 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7406 emit_library_call (libfunc, LCT_NORMAL,
7408 XEXP (slot0, 0), Pmode,
7409 XEXP (slot1, 0), Pmode);
7414 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
7415 emit_library_call (libfunc, LCT_NORMAL,
7417 x, TFmode, y, TFmode);
7422 /* Immediately move the result of the libcall into a pseudo
7423 register so reload doesn't clobber the value if it needs
7424 the return register for a spill reg. */
7425 result = gen_reg_rtx (mode);
7426 emit_move_insn (result, hard_libcall_value (mode, libfunc));
7431 return gen_rtx_NE (VOIDmode, result, const0_rtx);
7434 new_comparison = (comparison == UNORDERED ? EQ : NE);
7435 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3));
7438 new_comparison = (comparison == UNGT ? GT : NE);
7439 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx);
7441 return gen_rtx_NE (VOIDmode, result, const2_rtx);
7443 tem = gen_reg_rtx (mode);
7445 emit_insn (gen_andsi3 (tem, result, const1_rtx));
7447 emit_insn (gen_anddi3 (tem, result, const1_rtx));
7448 return gen_rtx_NE (VOIDmode, tem, const0_rtx);
7451 tem = gen_reg_rtx (mode);
7453 emit_insn (gen_addsi3 (tem, result, const1_rtx));
7455 emit_insn (gen_adddi3 (tem, result, const1_rtx));
7456 tem2 = gen_reg_rtx (mode);
7458 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
7460 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
7461 new_comparison = (comparison == UNEQ ? EQ : NE);
7462 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx);
7468 /* Generate an unsigned DImode to FP conversion. This is the same code
7469 optabs would emit if we didn't have TFmode patterns. */
7472 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
7474 rtx neglab, donelab, i0, i1, f0, in, out;
7477 in = force_reg (DImode, operands[1]);
7478 neglab = gen_label_rtx ();
7479 donelab = gen_label_rtx ();
7480 i0 = gen_reg_rtx (DImode);
7481 i1 = gen_reg_rtx (DImode);
7482 f0 = gen_reg_rtx (mode);
7484 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
7486 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
7487 emit_jump_insn (gen_jump (donelab));
7490 emit_label (neglab);
7492 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
7493 emit_insn (gen_anddi3 (i1, in, const1_rtx));
7494 emit_insn (gen_iordi3 (i0, i0, i1));
7495 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
7496 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
7498 emit_label (donelab);
7501 /* Generate an FP to unsigned DImode conversion. This is the same code
7502 optabs would emit if we didn't have TFmode patterns. */
7505 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
7507 rtx neglab, donelab, i0, i1, f0, in, out, limit;
7510 in = force_reg (mode, operands[1]);
7511 neglab = gen_label_rtx ();
7512 donelab = gen_label_rtx ();
7513 i0 = gen_reg_rtx (DImode);
7514 i1 = gen_reg_rtx (DImode);
7515 limit = gen_reg_rtx (mode);
7516 f0 = gen_reg_rtx (mode);
7518 emit_move_insn (limit,
7519 CONST_DOUBLE_FROM_REAL_VALUE (
7520 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
7521 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
7523 emit_insn (gen_rtx_SET (VOIDmode,
7525 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
7526 emit_jump_insn (gen_jump (donelab));
7529 emit_label (neglab);
7531 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
7532 emit_insn (gen_rtx_SET (VOIDmode,
7534 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
7535 emit_insn (gen_movdi (i1, const1_rtx));
7536 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
7537 emit_insn (gen_xordi3 (out, i0, i1));
7539 emit_label (donelab);
7542 /* Return the string to output a conditional branch to LABEL, testing
7543 register REG. LABEL is the operand number of the label; REG is the
7544 operand number of the reg. OP is the conditional expression. The mode
7545 of REG says what kind of comparison we made.
7547 DEST is the destination insn (i.e. the label), INSN is the source.
7549 REVERSED is nonzero if we should reverse the sense of the comparison.
7551 ANNUL is nonzero if we should generate an annulling branch. */
7554 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
7555 int annul, rtx insn)
7557 static char string[64];
7558 enum rtx_code code = GET_CODE (op);
7559 enum machine_mode mode = GET_MODE (XEXP (op, 0));
7564 /* branch on register are limited to +-128KB. If it is too far away,
7577 brgez,a,pn %o1, .LC29
7583 ba,pt %xcc, .LC29 */
7585 far = get_attr_length (insn) >= 3;
7587 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7589 code = reverse_condition (code);
7591 /* Only 64 bit versions of these instructions exist. */
7592 gcc_assert (mode == DImode);
7594 /* Start by writing the branch condition. */
7599 strcpy (string, "brnz");
7603 strcpy (string, "brz");
7607 strcpy (string, "brgez");
7611 strcpy (string, "brlz");
7615 strcpy (string, "brlez");
7619 strcpy (string, "brgz");
7626 p = strchr (string, '\0');
7628 /* Now add the annulling, reg, label, and nop. */
7635 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
7638 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
7643 *p = p < string + 8 ? '\t' : ' ';
7651 int veryfar = 1, delta;
7653 if (INSN_ADDRESSES_SET_P ())
7655 delta = (INSN_ADDRESSES (INSN_UID (dest))
7656 - INSN_ADDRESSES (INSN_UID (insn)));
7657 /* Leave some instructions for "slop". */
7658 if (delta >= -260000 && delta < 260000)
7662 strcpy (p, ".+12\n\t nop\n\t");
7663 /* Skip the next insn if requested or
7664 if we know that it will be a nop. */
7665 if (annul || ! final_sequence)
7675 strcpy (p, "ba,pt\t%%xcc, ");
7689 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7690 Such instructions cannot be used in the delay slot of return insn on v9.
7691 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7695 epilogue_renumber (register rtx *where, int test)
7697 register const char *fmt;
7699 register enum rtx_code code;
7704 code = GET_CODE (*where);
7709 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
7711 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
7712 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
7720 /* Do not replace the frame pointer with the stack pointer because
7721 it can cause the delayed instruction to load below the stack.
7722 This occurs when instructions like:
7724 (set (reg/i:SI 24 %i0)
7725 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7726 (const_int -20 [0xffffffec])) 0))
7728 are in the return delayed slot. */
7730 if (GET_CODE (XEXP (*where, 0)) == REG
7731 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
7732 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
7733 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
7738 if (SPARC_STACK_BIAS
7739 && GET_CODE (XEXP (*where, 0)) == REG
7740 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7748 fmt = GET_RTX_FORMAT (code);
7750 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7755 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7756 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7759 else if (fmt[i] == 'e'
7760 && epilogue_renumber (&(XEXP (*where, i)), test))
7766 /* Leaf functions and non-leaf functions have different needs. */
7769 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7772 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7774 static const int *const reg_alloc_orders[] = {
7775 reg_leaf_alloc_order,
7776 reg_nonleaf_alloc_order};
7779 order_regs_for_local_alloc (void)
7781 static int last_order_nonleaf = 1;
7783 if (df_regs_ever_live_p (15) != last_order_nonleaf)
7785 last_order_nonleaf = !last_order_nonleaf;
7786 memcpy ((char *) reg_alloc_order,
7787 (const char *) reg_alloc_orders[last_order_nonleaf],
7788 FIRST_PSEUDO_REGISTER * sizeof (int));
7792 /* Return 1 if REG and MEM are legitimate enough to allow the various
7793 mem<-->reg splits to be run. */
7796 sparc_splitdi_legitimate (rtx reg, rtx mem)
7798 /* Punt if we are here by mistake. */
7799 gcc_assert (reload_completed);
7801 /* We must have an offsettable memory reference. */
7802 if (! offsettable_memref_p (mem))
7805 /* If we have legitimate args for ldd/std, we do not want
7806 the split to happen. */
7807 if ((REGNO (reg) % 2) == 0
7808 && mem_min_alignment (mem, 8))
7815 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
7818 sparc_split_regreg_legitimate (rtx reg1, rtx reg2)
7822 if (GET_CODE (reg1) == SUBREG)
7823 reg1 = SUBREG_REG (reg1);
7824 if (GET_CODE (reg1) != REG)
7826 regno1 = REGNO (reg1);
7828 if (GET_CODE (reg2) == SUBREG)
7829 reg2 = SUBREG_REG (reg2);
7830 if (GET_CODE (reg2) != REG)
7832 regno2 = REGNO (reg2);
7834 if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2))
7839 if ((SPARC_INT_REG_P (regno1) && SPARC_FP_REG_P (regno2))
7840 || (SPARC_FP_REG_P (regno1) && SPARC_INT_REG_P (regno2)))
7847 /* Return 1 if x and y are some kind of REG and they refer to
7848 different hard registers. This test is guaranteed to be
7849 run after reload. */
7852 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7854 if (GET_CODE (x) != REG)
7856 if (GET_CODE (y) != REG)
7858 if (REGNO (x) == REGNO (y))
7863 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7864 This makes them candidates for using ldd and std insns.
7866 Note reg1 and reg2 *must* be hard registers. */
7869 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7871 /* We might have been passed a SUBREG. */
7872 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7875 if (REGNO (reg1) % 2 != 0)
7878 /* Integer ldd is deprecated in SPARC V9 */
7879 if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1)))
7882 return (REGNO (reg1) == REGNO (reg2) - 1);
7885 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7888 This can only happen when addr1 and addr2, the addresses in mem1
7889 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7890 addr1 must also be aligned on a 64-bit boundary.
7892 Also iff dependent_reg_rtx is not null it should not be used to
7893 compute the address for mem1, i.e. we cannot optimize a sequence
7905 But, note that the transformation from:
7910 is perfectly fine. Thus, the peephole2 patterns always pass us
7911 the destination register of the first load, never the second one.
7913 For stores we don't have a similar problem, so dependent_reg_rtx is
7917 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7921 HOST_WIDE_INT offset1;
7923 /* The mems cannot be volatile. */
7924 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7927 /* MEM1 should be aligned on a 64-bit boundary. */
7928 if (MEM_ALIGN (mem1) < 64)
7931 addr1 = XEXP (mem1, 0);
7932 addr2 = XEXP (mem2, 0);
7934 /* Extract a register number and offset (if used) from the first addr. */
7935 if (GET_CODE (addr1) == PLUS)
7937 /* If not a REG, return zero. */
7938 if (GET_CODE (XEXP (addr1, 0)) != REG)
7942 reg1 = REGNO (XEXP (addr1, 0));
7943 /* The offset must be constant! */
7944 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7946 offset1 = INTVAL (XEXP (addr1, 1));
7949 else if (GET_CODE (addr1) != REG)
7953 reg1 = REGNO (addr1);
7954 /* This was a simple (mem (reg)) expression. Offset is 0. */
7958 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7959 if (GET_CODE (addr2) != PLUS)
7962 if (GET_CODE (XEXP (addr2, 0)) != REG
7963 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7966 if (reg1 != REGNO (XEXP (addr2, 0)))
7969 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7972 /* The first offset must be evenly divisible by 8 to ensure the
7973 address is 64 bit aligned. */
7974 if (offset1 % 8 != 0)
7977 /* The offset for the second addr must be 4 more than the first addr. */
7978 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7981 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7986 /* Return 1 if reg is a pseudo, or is the first register in
7987 a hard register pair. This makes it suitable for use in
7988 ldd and std insns. */
7991 register_ok_for_ldd (rtx reg)
7993 /* We might have been passed a SUBREG. */
7997 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7998 return (REGNO (reg) % 2 == 0);
8003 /* Return 1 if OP is a memory whose address is known to be
8004 aligned to 8-byte boundary, or a pseudo during reload.
8005 This makes it suitable for use in ldd and std insns. */
8008 memory_ok_for_ldd (rtx op)
8012 /* In 64-bit mode, we assume that the address is word-aligned. */
8013 if (TARGET_ARCH32 && !mem_min_alignment (op, 8))
8016 if (! can_create_pseudo_p ()
8017 && !strict_memory_address_p (Pmode, XEXP (op, 0)))
8020 else if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
8022 if (!(reload_in_progress && reg_renumber [REGNO (op)] < 0))
8031 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8034 sparc_print_operand_punct_valid_p (unsigned char code)
8047 /* Implement TARGET_PRINT_OPERAND.
8048 Print operand X (an rtx) in assembler syntax to file FILE.
8049 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8050 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8053 sparc_print_operand (FILE *file, rtx x, int code)
8058 /* Output an insn in a delay slot. */
8060 sparc_indent_opcode = 1;
8062 fputs ("\n\t nop", file);
8065 /* Output an annul flag if there's nothing for the delay slot and we
8066 are optimizing. This is always used with '(' below.
8067 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8068 this is a dbx bug. So, we only do this when optimizing.
8069 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8070 Always emit a nop in case the next instruction is a branch. */
8071 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
8075 /* Output a 'nop' if there's nothing for the delay slot and we are
8076 not optimizing. This is always used with '*' above. */
8077 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
8078 fputs ("\n\t nop", file);
8079 else if (final_sequence)
8080 sparc_indent_opcode = 1;
8083 /* Output the right displacement from the saved PC on function return.
8084 The caller may have placed an "unimp" insn immediately after the call
8085 so we have to account for it. This insn is used in the 32-bit ABI
8086 when calling a function that returns a non zero-sized structure. The
8087 64-bit ABI doesn't have it. Be careful to have this test be the same
8088 as that for the call. The exception is when sparc_std_struct_return
8089 is enabled, the psABI is followed exactly and the adjustment is made
8090 by the code in sparc_struct_value_rtx. The call emitted is the same
8091 when sparc_std_struct_return is enabled. */
8093 && cfun->returns_struct
8094 && !sparc_std_struct_return
8095 && DECL_SIZE (DECL_RESULT (current_function_decl))
8096 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
8098 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
8104 /* Output the Embedded Medium/Anywhere code model base register. */
8105 fputs (EMBMEDANY_BASE_REG, file);
8108 /* Print some local dynamic TLS name. */
8109 assemble_name (file, get_some_local_dynamic_name ());
8113 /* Adjust the operand to take into account a RESTORE operation. */
8114 if (GET_CODE (x) == CONST_INT)
8116 else if (GET_CODE (x) != REG)
8117 output_operand_lossage ("invalid %%Y operand");
8118 else if (REGNO (x) < 8)
8119 fputs (reg_names[REGNO (x)], file);
8120 else if (REGNO (x) >= 24 && REGNO (x) < 32)
8121 fputs (reg_names[REGNO (x)-16], file);
8123 output_operand_lossage ("invalid %%Y operand");
8126 /* Print out the low order register name of a register pair. */
8127 if (WORDS_BIG_ENDIAN)
8128 fputs (reg_names[REGNO (x)+1], file);
8130 fputs (reg_names[REGNO (x)], file);
8133 /* Print out the high order register name of a register pair. */
8134 if (WORDS_BIG_ENDIAN)
8135 fputs (reg_names[REGNO (x)], file);
8137 fputs (reg_names[REGNO (x)+1], file);
8140 /* Print out the second register name of a register pair or quad.
8141 I.e., R (%o0) => %o1. */
8142 fputs (reg_names[REGNO (x)+1], file);
8145 /* Print out the third register name of a register quad.
8146 I.e., S (%o0) => %o2. */
8147 fputs (reg_names[REGNO (x)+2], file);
8150 /* Print out the fourth register name of a register quad.
8151 I.e., T (%o0) => %o3. */
8152 fputs (reg_names[REGNO (x)+3], file);
8155 /* Print a condition code register. */
8156 if (REGNO (x) == SPARC_ICC_REG)
8158 /* We don't handle CC[X]_NOOVmode because they're not supposed
8160 if (GET_MODE (x) == CCmode)
8161 fputs ("%icc", file);
8162 else if (GET_MODE (x) == CCXmode)
8163 fputs ("%xcc", file);
8168 /* %fccN register */
8169 fputs (reg_names[REGNO (x)], file);
8172 /* Print the operand's address only. */
8173 output_address (XEXP (x, 0));
8176 /* In this case we need a register. Use %g0 if the
8177 operand is const0_rtx. */
8179 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
8181 fputs ("%g0", file);
8188 switch (GET_CODE (x))
8190 case IOR: fputs ("or", file); break;
8191 case AND: fputs ("and", file); break;
8192 case XOR: fputs ("xor", file); break;
8193 default: output_operand_lossage ("invalid %%A operand");
8198 switch (GET_CODE (x))
8200 case IOR: fputs ("orn", file); break;
8201 case AND: fputs ("andn", file); break;
8202 case XOR: fputs ("xnor", file); break;
8203 default: output_operand_lossage ("invalid %%B operand");
8207 /* This is used by the conditional move instructions. */
8210 enum rtx_code rc = GET_CODE (x);
8214 case NE: fputs ("ne", file); break;
8215 case EQ: fputs ("e", file); break;
8216 case GE: fputs ("ge", file); break;
8217 case GT: fputs ("g", file); break;
8218 case LE: fputs ("le", file); break;
8219 case LT: fputs ("l", file); break;
8220 case GEU: fputs ("geu", file); break;
8221 case GTU: fputs ("gu", file); break;
8222 case LEU: fputs ("leu", file); break;
8223 case LTU: fputs ("lu", file); break;
8224 case LTGT: fputs ("lg", file); break;
8225 case UNORDERED: fputs ("u", file); break;
8226 case ORDERED: fputs ("o", file); break;
8227 case UNLT: fputs ("ul", file); break;
8228 case UNLE: fputs ("ule", file); break;
8229 case UNGT: fputs ("ug", file); break;
8230 case UNGE: fputs ("uge", file); break;
8231 case UNEQ: fputs ("ue", file); break;
8232 default: output_operand_lossage ("invalid %%C operand");
8237 /* This are used by the movr instruction pattern. */
8240 enum rtx_code rc = GET_CODE (x);
8243 case NE: fputs ("ne", file); break;
8244 case EQ: fputs ("e", file); break;
8245 case GE: fputs ("gez", file); break;
8246 case LT: fputs ("lz", file); break;
8247 case LE: fputs ("lez", file); break;
8248 case GT: fputs ("gz", file); break;
8249 default: output_operand_lossage ("invalid %%D operand");
8256 /* Print a sign-extended character. */
8257 int i = trunc_int_for_mode (INTVAL (x), QImode);
8258 fprintf (file, "%d", i);
8263 /* Operand must be a MEM; write its address. */
8264 if (GET_CODE (x) != MEM)
8265 output_operand_lossage ("invalid %%f operand");
8266 output_address (XEXP (x, 0));
8271 /* Print a sign-extended 32-bit value. */
8273 if (GET_CODE(x) == CONST_INT)
8275 else if (GET_CODE(x) == CONST_DOUBLE)
8276 i = CONST_DOUBLE_LOW (x);
8279 output_operand_lossage ("invalid %%s operand");
8282 i = trunc_int_for_mode (i, SImode);
8283 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
8288 /* Do nothing special. */
8292 /* Undocumented flag. */
8293 output_operand_lossage ("invalid operand output code");
8296 if (GET_CODE (x) == REG)
8297 fputs (reg_names[REGNO (x)], file);
8298 else if (GET_CODE (x) == MEM)
8301 /* Poor Sun assembler doesn't understand absolute addressing. */
8302 if (CONSTANT_P (XEXP (x, 0)))
8303 fputs ("%g0+", file);
8304 output_address (XEXP (x, 0));
8307 else if (GET_CODE (x) == HIGH)
8309 fputs ("%hi(", file);
8310 output_addr_const (file, XEXP (x, 0));
8313 else if (GET_CODE (x) == LO_SUM)
8315 sparc_print_operand (file, XEXP (x, 0), 0);
8316 if (TARGET_CM_MEDMID)
8317 fputs ("+%l44(", file);
8319 fputs ("+%lo(", file);
8320 output_addr_const (file, XEXP (x, 1));
8323 else if (GET_CODE (x) == CONST_DOUBLE
8324 && (GET_MODE (x) == VOIDmode
8325 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
8327 if (CONST_DOUBLE_HIGH (x) == 0)
8328 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
8329 else if (CONST_DOUBLE_HIGH (x) == -1
8330 && CONST_DOUBLE_LOW (x) < 0)
8331 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
8333 output_operand_lossage ("long long constant not a valid immediate operand");
8335 else if (GET_CODE (x) == CONST_DOUBLE)
8336 output_operand_lossage ("floating point constant not a valid immediate operand");
8337 else { output_addr_const (file, x); }
8340 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8343 sparc_print_operand_address (FILE *file, rtx x)
8345 register rtx base, index = 0;
8347 register rtx addr = x;
8350 fputs (reg_names[REGNO (addr)], file);
8351 else if (GET_CODE (addr) == PLUS)
8353 if (CONST_INT_P (XEXP (addr, 0)))
8354 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
8355 else if (CONST_INT_P (XEXP (addr, 1)))
8356 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
8358 base = XEXP (addr, 0), index = XEXP (addr, 1);
8359 if (GET_CODE (base) == LO_SUM)
8361 gcc_assert (USE_AS_OFFSETABLE_LO10
8363 && ! TARGET_CM_MEDMID);
8364 output_operand (XEXP (base, 0), 0);
8365 fputs ("+%lo(", file);
8366 output_address (XEXP (base, 1));
8367 fprintf (file, ")+%d", offset);
8371 fputs (reg_names[REGNO (base)], file);
8373 fprintf (file, "%+d", offset);
8374 else if (REG_P (index))
8375 fprintf (file, "+%s", reg_names[REGNO (index)]);
8376 else if (GET_CODE (index) == SYMBOL_REF
8377 || GET_CODE (index) == LABEL_REF
8378 || GET_CODE (index) == CONST)
8379 fputc ('+', file), output_addr_const (file, index);
8380 else gcc_unreachable ();
8383 else if (GET_CODE (addr) == MINUS
8384 && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
8386 output_addr_const (file, XEXP (addr, 0));
8388 output_addr_const (file, XEXP (addr, 1));
8389 fputs ("-.)", file);
8391 else if (GET_CODE (addr) == LO_SUM)
8393 output_operand (XEXP (addr, 0), 0);
8394 if (TARGET_CM_MEDMID)
8395 fputs ("+%l44(", file);
8397 fputs ("+%lo(", file);
8398 output_address (XEXP (addr, 1));
8402 && GET_CODE (addr) == CONST
8403 && GET_CODE (XEXP (addr, 0)) == MINUS
8404 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST
8405 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS
8406 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)
8408 addr = XEXP (addr, 0);
8409 output_addr_const (file, XEXP (addr, 0));
8410 /* Group the args of the second CONST in parenthesis. */
8412 /* Skip past the second CONST--it does nothing for us. */
8413 output_addr_const (file, XEXP (XEXP (addr, 1), 0));
8414 /* Close the parenthesis. */
8419 output_addr_const (file, addr);
8423 /* Target hook for assembling integer objects. The sparc version has
8424 special handling for aligned DI-mode objects. */
8427 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
8429 /* ??? We only output .xword's for symbols and only then in environments
8430 where the assembler can handle them. */
8431 if (aligned_p && size == 8
8432 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
8436 assemble_integer_with_op ("\t.xword\t", x);
8441 assemble_aligned_integer (4, const0_rtx);
8442 assemble_aligned_integer (4, x);
8446 return default_assemble_integer (x, size, aligned_p);
8449 /* Return the value of a code used in the .proc pseudo-op that says
8450 what kind of result this function returns. For non-C types, we pick
8451 the closest C type. */
8453 #ifndef SHORT_TYPE_SIZE
8454 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8457 #ifndef INT_TYPE_SIZE
8458 #define INT_TYPE_SIZE BITS_PER_WORD
8461 #ifndef LONG_TYPE_SIZE
8462 #define LONG_TYPE_SIZE BITS_PER_WORD
8465 #ifndef LONG_LONG_TYPE_SIZE
8466 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8469 #ifndef FLOAT_TYPE_SIZE
8470 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8473 #ifndef DOUBLE_TYPE_SIZE
8474 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8477 #ifndef LONG_DOUBLE_TYPE_SIZE
8478 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8482 sparc_type_code (register tree type)
8484 register unsigned long qualifiers = 0;
8485 register unsigned shift;
8487 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8488 setting more, since some assemblers will give an error for this. Also,
8489 we must be careful to avoid shifts of 32 bits or more to avoid getting
8490 unpredictable results. */
8492 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
8494 switch (TREE_CODE (type))
8500 qualifiers |= (3 << shift);
8505 qualifiers |= (2 << shift);
8509 case REFERENCE_TYPE:
8511 qualifiers |= (1 << shift);
8515 return (qualifiers | 8);
8518 case QUAL_UNION_TYPE:
8519 return (qualifiers | 9);
8522 return (qualifiers | 10);
8525 return (qualifiers | 16);
8528 /* If this is a range type, consider it to be the underlying
8530 if (TREE_TYPE (type) != 0)
8533 /* Carefully distinguish all the standard types of C,
8534 without messing up if the language is not C. We do this by
8535 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8536 look at both the names and the above fields, but that's redundant.
8537 Any type whose size is between two C types will be considered
8538 to be the wider of the two types. Also, we do not have a
8539 special code to use for "long long", so anything wider than
8540 long is treated the same. Note that we can't distinguish
8541 between "int" and "long" in this code if they are the same
8542 size, but that's fine, since neither can the assembler. */
8544 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
8545 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
8547 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
8548 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
8550 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
8551 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
8554 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
8557 /* If this is a range type, consider it to be the underlying
8559 if (TREE_TYPE (type) != 0)
8562 /* Carefully distinguish all the standard types of C,
8563 without messing up if the language is not C. */
8565 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
8566 return (qualifiers | 6);
8569 return (qualifiers | 7);
8571 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
8572 /* ??? We need to distinguish between double and float complex types,
8573 but I don't know how yet because I can't reach this code from
8574 existing front-ends. */
8575 return (qualifiers | 7); /* Who knows? */
8578 case BOOLEAN_TYPE: /* Boolean truth value type. */
8584 gcc_unreachable (); /* Not a type! */
8591 /* Nested function support. */
8593 /* Emit RTL insns to initialize the variable parts of a trampoline.
8594 FNADDR is an RTX for the address of the function's pure code.
8595 CXT is an RTX for the static chain value for the function.
8597 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8598 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8599 (to store insns). This is a bit excessive. Perhaps a different
8600 mechanism would be better here.
8602 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8605 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8607 /* SPARC 32-bit trampoline:
8610 sethi %hi(static), %g2
8612 or %g2, %lo(static), %g2
8614 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8615 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8619 (adjust_address (m_tramp, SImode, 0),
8620 expand_binop (SImode, ior_optab,
8621 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1),
8622 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
8623 NULL_RTX, 1, OPTAB_DIRECT));
8626 (adjust_address (m_tramp, SImode, 4),
8627 expand_binop (SImode, ior_optab,
8628 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1),
8629 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
8630 NULL_RTX, 1, OPTAB_DIRECT));
8633 (adjust_address (m_tramp, SImode, 8),
8634 expand_binop (SImode, ior_optab,
8635 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
8636 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
8637 NULL_RTX, 1, OPTAB_DIRECT));
8640 (adjust_address (m_tramp, SImode, 12),
8641 expand_binop (SImode, ior_optab,
8642 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
8643 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
8644 NULL_RTX, 1, OPTAB_DIRECT));
8646 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8647 aligned on a 16 byte boundary so one flush clears it all. */
8648 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 0))));
8649 if (sparc_cpu != PROCESSOR_ULTRASPARC
8650 && sparc_cpu != PROCESSOR_ULTRASPARC3
8651 && sparc_cpu != PROCESSOR_NIAGARA
8652 && sparc_cpu != PROCESSOR_NIAGARA2
8653 && sparc_cpu != PROCESSOR_NIAGARA3
8654 && sparc_cpu != PROCESSOR_NIAGARA4)
8655 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8))));
8657 /* Call __enable_execute_stack after writing onto the stack to make sure
8658 the stack address is accessible. */
8659 #ifdef HAVE_ENABLE_EXECUTE_STACK
8660 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8661 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8666 /* The 64-bit version is simpler because it makes more sense to load the
8667 values as "immediate" data out of the trampoline. It's also easier since
8668 we can read the PC without clobbering a register. */
8671 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
8673 /* SPARC 64-bit trampoline:
8682 emit_move_insn (adjust_address (m_tramp, SImode, 0),
8683 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
8684 emit_move_insn (adjust_address (m_tramp, SImode, 4),
8685 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
8686 emit_move_insn (adjust_address (m_tramp, SImode, 8),
8687 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
8688 emit_move_insn (adjust_address (m_tramp, SImode, 12),
8689 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
8690 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
8691 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
8692 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
8694 if (sparc_cpu != PROCESSOR_ULTRASPARC
8695 && sparc_cpu != PROCESSOR_ULTRASPARC3
8696 && sparc_cpu != PROCESSOR_NIAGARA
8697 && sparc_cpu != PROCESSOR_NIAGARA2
8698 && sparc_cpu != PROCESSOR_NIAGARA3
8699 && sparc_cpu != PROCESSOR_NIAGARA4)
8700 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
8702 /* Call __enable_execute_stack after writing onto the stack to make sure
8703 the stack address is accessible. */
8704 #ifdef HAVE_ENABLE_EXECUTE_STACK
8705 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
8706 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
8710 /* Worker for TARGET_TRAMPOLINE_INIT. */
8713 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8715 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
8716 cxt = force_reg (Pmode, cxt);
8718 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt);
8720 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt);
8723 /* Adjust the cost of a scheduling dependency. Return the new cost of
8724 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8727 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8729 enum attr_type insn_type;
8731 if (! recog_memoized (insn))
8734 insn_type = get_attr_type (insn);
8736 if (REG_NOTE_KIND (link) == 0)
8738 /* Data dependency; DEP_INSN writes a register that INSN reads some
8741 /* if a load, then the dependence must be on the memory address;
8742 add an extra "cycle". Note that the cost could be two cycles
8743 if the reg was written late in an instruction group; we ca not tell
8745 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8748 /* Get the delay only if the address of the store is the dependence. */
8749 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8751 rtx pat = PATTERN(insn);
8752 rtx dep_pat = PATTERN (dep_insn);
8754 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8755 return cost; /* This should not happen! */
8757 /* The dependency between the two instructions was on the data that
8758 is being stored. Assume that this implies that the address of the
8759 store is not dependent. */
8760 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8763 return cost + 3; /* An approximation. */
8766 /* A shift instruction cannot receive its data from an instruction
8767 in the same cycle; add a one cycle penalty. */
8768 if (insn_type == TYPE_SHIFT)
8769 return cost + 3; /* Split before cascade into shift. */
8773 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8774 INSN writes some cycles later. */
8776 /* These are only significant for the fpu unit; writing a fp reg before
8777 the fpu has finished with it stalls the processor. */
8779 /* Reusing an integer register causes no problems. */
8780 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8788 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8790 enum attr_type insn_type, dep_type;
8791 rtx pat = PATTERN(insn);
8792 rtx dep_pat = PATTERN (dep_insn);
8794 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8797 insn_type = get_attr_type (insn);
8798 dep_type = get_attr_type (dep_insn);
8800 switch (REG_NOTE_KIND (link))
8803 /* Data dependency; DEP_INSN writes a register that INSN reads some
8810 /* Get the delay iff the address of the store is the dependence. */
8811 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8814 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8821 /* If a load, then the dependence must be on the memory address. If
8822 the addresses aren't equal, then it might be a false dependency */
8823 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8825 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8826 || GET_CODE (SET_DEST (dep_pat)) != MEM
8827 || GET_CODE (SET_SRC (pat)) != MEM
8828 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8829 XEXP (SET_SRC (pat), 0)))
8837 /* Compare to branch latency is 0. There is no benefit from
8838 separating compare and branch. */
8839 if (dep_type == TYPE_COMPARE)
8841 /* Floating point compare to branch latency is less than
8842 compare to conditional move. */
8843 if (dep_type == TYPE_FPCMP)
8852 /* Anti-dependencies only penalize the fpu unit. */
8853 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8865 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8869 case PROCESSOR_SUPERSPARC:
8870 cost = supersparc_adjust_cost (insn, link, dep, cost);
8872 case PROCESSOR_HYPERSPARC:
8873 case PROCESSOR_SPARCLITE86X:
8874 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8883 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8884 int sched_verbose ATTRIBUTE_UNUSED,
8885 int max_ready ATTRIBUTE_UNUSED)
8889 sparc_use_sched_lookahead (void)
8891 if (sparc_cpu == PROCESSOR_NIAGARA
8892 || sparc_cpu == PROCESSOR_NIAGARA2
8893 || sparc_cpu == PROCESSOR_NIAGARA3
8894 || sparc_cpu == PROCESSOR_NIAGARA4)
8896 if (sparc_cpu == PROCESSOR_ULTRASPARC
8897 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8899 if ((1 << sparc_cpu) &
8900 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8901 (1 << PROCESSOR_SPARCLITE86X)))
8907 sparc_issue_rate (void)
8911 case PROCESSOR_NIAGARA:
8912 case PROCESSOR_NIAGARA2:
8913 case PROCESSOR_NIAGARA3:
8914 case PROCESSOR_NIAGARA4:
8918 /* Assume V9 processors are capable of at least dual-issue. */
8920 case PROCESSOR_SUPERSPARC:
8922 case PROCESSOR_HYPERSPARC:
8923 case PROCESSOR_SPARCLITE86X:
8925 case PROCESSOR_ULTRASPARC:
8926 case PROCESSOR_ULTRASPARC3:
8932 set_extends (rtx insn)
8934 register rtx pat = PATTERN (insn);
8936 switch (GET_CODE (SET_SRC (pat)))
8938 /* Load and some shift instructions zero extend. */
8941 /* sethi clears the high bits */
8943 /* LO_SUM is used with sethi. sethi cleared the high
8944 bits and the values used with lo_sum are positive */
8946 /* Store flag stores 0 or 1 */
8956 rtx op0 = XEXP (SET_SRC (pat), 0);
8957 rtx op1 = XEXP (SET_SRC (pat), 1);
8958 if (GET_CODE (op1) == CONST_INT)
8959 return INTVAL (op1) >= 0;
8960 if (GET_CODE (op0) != REG)
8962 if (sparc_check_64 (op0, insn) == 1)
8964 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8969 rtx op0 = XEXP (SET_SRC (pat), 0);
8970 rtx op1 = XEXP (SET_SRC (pat), 1);
8971 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8973 if (GET_CODE (op1) == CONST_INT)
8974 return INTVAL (op1) >= 0;
8975 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8978 return GET_MODE (SET_SRC (pat)) == SImode;
8979 /* Positive integers leave the high bits zero. */
8981 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8983 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8986 return - (GET_MODE (SET_SRC (pat)) == SImode);
8988 return sparc_check_64 (SET_SRC (pat), insn);
8994 /* We _ought_ to have only one kind per function, but... */
8995 static GTY(()) rtx sparc_addr_diff_list;
8996 static GTY(()) rtx sparc_addr_list;
8999 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
9001 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9003 sparc_addr_diff_list
9004 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
9006 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
9010 sparc_output_addr_vec (rtx vec)
9012 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9013 int idx, vlen = XVECLEN (body, 0);
9015 #ifdef ASM_OUTPUT_ADDR_VEC_START
9016 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9019 #ifdef ASM_OUTPUT_CASE_LABEL
9020 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9023 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9026 for (idx = 0; idx < vlen; idx++)
9028 ASM_OUTPUT_ADDR_VEC_ELT
9029 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9032 #ifdef ASM_OUTPUT_ADDR_VEC_END
9033 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9038 sparc_output_addr_diff_vec (rtx vec)
9040 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
9041 rtx base = XEXP (XEXP (body, 0), 0);
9042 int idx, vlen = XVECLEN (body, 1);
9044 #ifdef ASM_OUTPUT_ADDR_VEC_START
9045 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
9048 #ifdef ASM_OUTPUT_CASE_LABEL
9049 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
9052 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
9055 for (idx = 0; idx < vlen; idx++)
9057 ASM_OUTPUT_ADDR_DIFF_ELT
9060 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
9061 CODE_LABEL_NUMBER (base));
9064 #ifdef ASM_OUTPUT_ADDR_VEC_END
9065 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
9070 sparc_output_deferred_case_vectors (void)
9075 if (sparc_addr_list == NULL_RTX
9076 && sparc_addr_diff_list == NULL_RTX)
9079 /* Align to cache line in the function's code section. */
9080 switch_to_section (current_function_section ());
9082 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9084 ASM_OUTPUT_ALIGN (asm_out_file, align);
9086 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
9087 sparc_output_addr_vec (XEXP (t, 0));
9088 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
9089 sparc_output_addr_diff_vec (XEXP (t, 0));
9091 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
9094 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9095 unknown. Return 1 if the high bits are zero, -1 if the register is
9098 sparc_check_64 (rtx x, rtx insn)
9100 /* If a register is set only once it is safe to ignore insns this
9101 code does not know how to handle. The loop will either recognize
9102 the single set and return the correct value or fail to recognize
9107 gcc_assert (GET_CODE (x) == REG);
9109 if (GET_MODE (x) == DImode)
9110 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
9112 if (flag_expensive_optimizations
9113 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)
9119 insn = get_last_insn_anywhere ();
9124 while ((insn = PREV_INSN (insn)))
9126 switch (GET_CODE (insn))
9139 rtx pat = PATTERN (insn);
9140 if (GET_CODE (pat) != SET)
9142 if (rtx_equal_p (x, SET_DEST (pat)))
9143 return set_extends (insn);
9144 if (y && rtx_equal_p (y, SET_DEST (pat)))
9145 return set_extends (insn);
9146 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
9154 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9155 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9158 output_v8plus_shift (rtx insn, rtx *operands, const char *opcode)
9160 static char asm_code[60];
9162 /* The scratch register is only required when the destination
9163 register is not a 64-bit global or out register. */
9164 if (which_alternative != 2)
9165 operands[3] = operands[0];
9167 /* We can only shift by constants <= 63. */
9168 if (GET_CODE (operands[2]) == CONST_INT)
9169 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
9171 if (GET_CODE (operands[1]) == CONST_INT)
9173 output_asm_insn ("mov\t%1, %3", operands);
9177 output_asm_insn ("sllx\t%H1, 32, %3", operands);
9178 if (sparc_check_64 (operands[1], insn) <= 0)
9179 output_asm_insn ("srl\t%L1, 0, %L1", operands);
9180 output_asm_insn ("or\t%L1, %3, %3", operands);
9183 strcpy (asm_code, opcode);
9185 if (which_alternative != 2)
9186 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9189 strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9192 /* Output rtl to increment the profiler label LABELNO
9193 for profiling a function entry. */
9196 sparc_profile_hook (int labelno)
9201 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
9202 if (NO_PROFILE_COUNTERS)
9204 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0);
9208 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
9209 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9210 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
9214 #ifdef TARGET_SOLARIS
9215 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9218 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
9219 tree decl ATTRIBUTE_UNUSED)
9221 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
9223 solaris_elf_asm_comdat_section (name, flags, decl);
9227 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
9229 if (!(flags & SECTION_DEBUG))
9230 fputs (",#alloc", asm_out_file);
9231 if (flags & SECTION_WRITE)
9232 fputs (",#write", asm_out_file);
9233 if (flags & SECTION_TLS)
9234 fputs (",#tls", asm_out_file);
9235 if (flags & SECTION_CODE)
9236 fputs (",#execinstr", asm_out_file);
9238 /* ??? Handle SECTION_BSS. */
9240 fputc ('\n', asm_out_file);
9242 #endif /* TARGET_SOLARIS */
9244 /* We do not allow indirect calls to be optimized into sibling calls.
9246 We cannot use sibling calls when delayed branches are disabled
9247 because they will likely require the call delay slot to be filled.
9249 Also, on SPARC 32-bit we cannot emit a sibling call when the
9250 current function returns a structure. This is because the "unimp
9251 after call" convention would cause the callee to return to the
9252 wrong place. The generic code already disallows cases where the
9253 function being called returns a structure.
9255 It may seem strange how this last case could occur. Usually there
9256 is code after the call which jumps to epilogue code which dumps the
9257 return value into the struct return area. That ought to invalidate
9258 the sibling call right? Well, in the C++ case we can end up passing
9259 the pointer to the struct return area to a constructor (which returns
9260 void) and then nothing else happens. Such a sibling call would look
9261 valid without the added check here.
9263 VxWorks PIC PLT entries require the global pointer to be initialized
9264 on entry. We therefore can't emit sibling calls to them. */
9266 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9269 && flag_delayed_branch
9270 && (TARGET_ARCH64 || ! cfun->returns_struct)
9271 && !(TARGET_VXWORKS_RTP
9273 && !targetm.binds_local_p (decl)));
9276 /* libfunc renaming. */
9279 sparc_init_libfuncs (void)
9283 /* Use the subroutines that Sun's library provides for integer
9284 multiply and divide. The `*' prevents an underscore from
9285 being prepended by the compiler. .umul is a little faster
9287 set_optab_libfunc (smul_optab, SImode, "*.umul");
9288 set_optab_libfunc (sdiv_optab, SImode, "*.div");
9289 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
9290 set_optab_libfunc (smod_optab, SImode, "*.rem");
9291 set_optab_libfunc (umod_optab, SImode, "*.urem");
9293 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9294 set_optab_libfunc (add_optab, TFmode, "_Q_add");
9295 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
9296 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
9297 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
9298 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
9300 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9301 is because with soft-float, the SFmode and DFmode sqrt
9302 instructions will be absent, and the compiler will notice and
9303 try to use the TFmode sqrt instruction for calls to the
9304 builtin function sqrt, but this fails. */
9306 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
9308 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
9309 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
9310 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
9311 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
9312 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
9313 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
9315 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
9316 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
9317 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
9318 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
9320 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
9321 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
9322 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
9323 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq");
9325 if (DITF_CONVERSION_LIBFUNCS)
9327 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
9328 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
9329 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
9330 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq");
9333 if (SUN_CONVERSION_LIBFUNCS)
9335 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9336 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9337 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9338 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9343 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9344 do not exist in the library. Make sure the compiler does not
9345 emit calls to them by accident. (It should always use the
9346 hardware instructions.) */
9347 set_optab_libfunc (smul_optab, SImode, 0);
9348 set_optab_libfunc (sdiv_optab, SImode, 0);
9349 set_optab_libfunc (udiv_optab, SImode, 0);
9350 set_optab_libfunc (smod_optab, SImode, 0);
9351 set_optab_libfunc (umod_optab, SImode, 0);
9353 if (SUN_INTEGER_MULTIPLY_64)
9355 set_optab_libfunc (smul_optab, DImode, "__mul64");
9356 set_optab_libfunc (sdiv_optab, DImode, "__div64");
9357 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
9358 set_optab_libfunc (smod_optab, DImode, "__rem64");
9359 set_optab_libfunc (umod_optab, DImode, "__urem64");
9362 if (SUN_CONVERSION_LIBFUNCS)
9364 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
9365 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
9366 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
9367 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
9372 static tree def_builtin(const char *name, int code, tree type)
9374 return add_builtin_function(name, type, code, BUILT_IN_MD, NULL,
9378 static tree def_builtin_const(const char *name, int code, tree type)
9380 tree t = def_builtin(name, code, type);
9383 TREE_READONLY (t) = 1;
9388 /* Implement the TARGET_INIT_BUILTINS target hook.
9389 Create builtin functions for special SPARC instructions. */
9392 sparc_init_builtins (void)
9395 sparc_vis_init_builtins ();
9398 /* Create builtin functions for VIS 1.0 instructions. */
9401 sparc_vis_init_builtins (void)
9403 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
9404 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
9405 tree v4hi = build_vector_type (intHI_type_node, 4);
9406 tree v2hi = build_vector_type (intHI_type_node, 2);
9407 tree v2si = build_vector_type (intSI_type_node, 2);
9408 tree v1si = build_vector_type (intSI_type_node, 1);
9410 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
9411 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
9412 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
9413 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
9414 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
9415 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
9416 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
9417 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
9418 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
9419 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
9420 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
9421 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
9422 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0);
9423 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0);
9424 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
9426 intDI_type_node, 0);
9427 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node,
9429 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
9431 tree di_ftype_di_di = build_function_type_list (intDI_type_node,
9433 intDI_type_node, 0);
9434 tree si_ftype_si_si = build_function_type_list (intSI_type_node,
9436 intSI_type_node, 0);
9437 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
9439 intSI_type_node, 0);
9440 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
9442 intDI_type_node, 0);
9443 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node,
9446 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node,
9449 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node,
9451 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
9453 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node,
9455 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node,
9457 tree void_ftype_di = build_function_type_list (void_type_node,
9458 intDI_type_node, 0);
9459 tree di_ftype_void = build_function_type_list (intDI_type_node,
9461 tree void_ftype_si = build_function_type_list (void_type_node,
9462 intSI_type_node, 0);
9463 tree sf_ftype_sf_sf = build_function_type_list (float_type_node,
9465 float_type_node, 0);
9466 tree df_ftype_df_df = build_function_type_list (double_type_node,
9468 double_type_node, 0);
9470 /* Packing and expanding vectors. */
9471 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
9473 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
9474 v8qi_ftype_v2si_v8qi);
9475 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
9477 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
9479 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
9480 v8qi_ftype_v4qi_v4qi);
9482 /* Multiplications. */
9483 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
9484 v4hi_ftype_v4qi_v4hi);
9485 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
9486 v4hi_ftype_v4qi_v2hi);
9487 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
9488 v4hi_ftype_v4qi_v2hi);
9489 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
9490 v4hi_ftype_v8qi_v4hi);
9491 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
9492 v4hi_ftype_v8qi_v4hi);
9493 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
9494 v2si_ftype_v4qi_v2hi);
9495 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
9496 v2si_ftype_v4qi_v2hi);
9498 /* Data aligning. */
9499 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
9500 v4hi_ftype_v4hi_v4hi);
9501 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
9502 v8qi_ftype_v8qi_v8qi);
9503 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
9504 v2si_ftype_v2si_v2si);
9505 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis,
9508 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
9510 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
9515 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
9517 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
9522 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
9524 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
9528 /* Pixel distance. */
9529 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
9530 di_ftype_v8qi_v8qi_di);
9532 /* Edge handling. */
9535 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis,
9537 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis,
9539 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis,
9541 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis,
9543 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis,
9545 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis,
9549 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis,
9551 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis,
9553 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis,
9555 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis,
9557 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis,
9559 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis,
9565 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis,
9567 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis,
9569 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis,
9571 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis,
9573 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis,
9575 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis,
9579 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis,
9581 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis,
9583 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis,
9585 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis,
9587 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis,
9589 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis,
9594 /* Pixel compare. */
9597 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis,
9598 di_ftype_v4hi_v4hi);
9599 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis,
9600 di_ftype_v2si_v2si);
9601 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis,
9602 di_ftype_v4hi_v4hi);
9603 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis,
9604 di_ftype_v2si_v2si);
9605 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis,
9606 di_ftype_v4hi_v4hi);
9607 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis,
9608 di_ftype_v2si_v2si);
9609 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis,
9610 di_ftype_v4hi_v4hi);
9611 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis,
9612 di_ftype_v2si_v2si);
9616 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis,
9617 si_ftype_v4hi_v4hi);
9618 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis,
9619 si_ftype_v2si_v2si);
9620 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis,
9621 si_ftype_v4hi_v4hi);
9622 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis,
9623 si_ftype_v2si_v2si);
9624 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis,
9625 si_ftype_v4hi_v4hi);
9626 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis,
9627 si_ftype_v2si_v2si);
9628 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis,
9629 si_ftype_v4hi_v4hi);
9630 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis,
9631 si_ftype_v2si_v2si);
9634 /* Addition and subtraction. */
9635 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3,
9636 v4hi_ftype_v4hi_v4hi);
9637 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3,
9638 v2hi_ftype_v2hi_v2hi);
9639 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3,
9640 v2si_ftype_v2si_v2si);
9641 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3,
9642 v1si_ftype_v1si_v1si);
9643 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3,
9644 v4hi_ftype_v4hi_v4hi);
9645 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3,
9646 v2hi_ftype_v2hi_v2hi);
9647 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3,
9648 v2si_ftype_v2si_v2si);
9649 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3,
9650 v1si_ftype_v1si_v1si);
9652 /* Three-dimensional array addressing. */
9655 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis,
9657 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis,
9659 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis,
9664 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis,
9666 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis,
9668 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis,
9674 /* Byte mask and shuffle */
9676 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis,
9679 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis,
9681 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis,
9682 v4hi_ftype_v4hi_v4hi);
9683 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis,
9684 v8qi_ftype_v8qi_v8qi);
9685 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis,
9686 v2si_ftype_v2si_v2si);
9687 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis,
9695 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis,
9697 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis,
9699 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis,
9704 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis,
9706 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis,
9708 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis,
9712 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis,
9713 v4hi_ftype_v4hi_v4hi);
9715 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3,
9716 v4hi_ftype_v4hi_v4hi);
9717 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3,
9718 v4hi_ftype_v4hi_v4hi);
9719 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3,
9720 v4hi_ftype_v4hi_v4hi);
9721 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3,
9722 v4hi_ftype_v4hi_v4hi);
9723 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3,
9724 v2si_ftype_v2si_v2si);
9725 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3,
9726 v2si_ftype_v2si_v2si);
9727 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3,
9728 v2si_ftype_v2si_v2si);
9729 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3,
9730 v2si_ftype_v2si_v2si);
9733 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis,
9734 di_ftype_v8qi_v8qi);
9736 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis,
9737 si_ftype_v8qi_v8qi);
9739 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
9740 v4hi_ftype_v4hi_v4hi);
9741 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
9743 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
9746 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
9747 v4hi_ftype_v4hi_v4hi);
9748 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3,
9749 v2hi_ftype_v2hi_v2hi);
9750 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3,
9751 v4hi_ftype_v4hi_v4hi);
9752 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3,
9753 v2hi_ftype_v2hi_v2hi);
9754 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3,
9755 v2si_ftype_v2si_v2si);
9756 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3,
9757 v1si_ftype_v1si_v1si);
9758 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3,
9759 v2si_ftype_v2si_v2si);
9760 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
9761 v1si_ftype_v1si_v1si);
9765 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis,
9766 di_ftype_v8qi_v8qi);
9767 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis,
9768 di_ftype_v8qi_v8qi);
9769 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis,
9770 di_ftype_v8qi_v8qi);
9771 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis,
9772 di_ftype_v8qi_v8qi);
9776 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis,
9777 si_ftype_v8qi_v8qi);
9778 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis,
9779 si_ftype_v8qi_v8qi);
9780 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis,
9781 si_ftype_v8qi_v8qi);
9782 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis,
9783 si_ftype_v8qi_v8qi);
9786 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
9788 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
9790 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
9792 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
9794 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
9796 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
9799 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
9801 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
9803 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
9808 /* Handle TARGET_EXPAND_BUILTIN target hook.
9809 Expand builtin functions for sparc intrinsics. */
9812 sparc_expand_builtin (tree exp, rtx target,
9813 rtx subtarget ATTRIBUTE_UNUSED,
9814 enum machine_mode tmode ATTRIBUTE_UNUSED,
9815 int ignore ATTRIBUTE_UNUSED)
9818 call_expr_arg_iterator iter;
9819 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9820 unsigned int icode = DECL_FUNCTION_CODE (fndecl);
9825 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9829 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9831 || GET_MODE (target) != tmode
9832 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9833 op[0] = gen_reg_rtx (tmode);
9837 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9839 const struct insn_operand_data *insn_op;
9842 if (arg == error_mark_node)
9846 idx = arg_count - !nonvoid;
9847 insn_op = &insn_data[icode].operand[idx];
9848 op[arg_count] = expand_normal (arg);
9850 if (insn_op->mode == V1DImode
9851 && GET_MODE (op[arg_count]) == DImode)
9852 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]);
9853 else if (insn_op->mode == V1SImode
9854 && GET_MODE (op[arg_count]) == SImode)
9855 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]);
9857 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count],
9859 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
9865 pat = GEN_FCN (icode) (op[0]);
9869 pat = GEN_FCN (icode) (op[0], op[1]);
9871 pat = GEN_FCN (icode) (op[1]);
9874 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
9877 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
9895 sparc_vis_mul8x16 (int e8, int e16)
9897 return (e8 * e16 + 128) / 256;
9900 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9901 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9902 constants. A tree list with the results of the multiplications is returned,
9903 and each element in the list is of INNER_TYPE. */
9906 sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1)
9908 tree n_elts = NULL_TREE;
9913 case CODE_FOR_fmul8x16_vis:
9914 for (; elts0 && elts1;
9915 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
9918 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9919 TREE_INT_CST_LOW (TREE_VALUE (elts1)));
9920 n_elts = tree_cons (NULL_TREE,
9921 build_int_cst (inner_type, val),
9926 case CODE_FOR_fmul8x16au_vis:
9927 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1));
9929 for (; elts0; elts0 = TREE_CHAIN (elts0))
9932 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9934 n_elts = tree_cons (NULL_TREE,
9935 build_int_cst (inner_type, val),
9940 case CODE_FOR_fmul8x16al_vis:
9941 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1)));
9943 for (; elts0; elts0 = TREE_CHAIN (elts0))
9946 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)),
9948 n_elts = tree_cons (NULL_TREE,
9949 build_int_cst (inner_type, val),
9958 return nreverse (n_elts);
9961 /* Handle TARGET_FOLD_BUILTIN target hook.
9962 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9963 result of the function call is ignored. NULL_TREE is returned if the
9964 function could not be folded. */
9967 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
9968 tree *args, bool ignore)
9970 tree arg0, arg1, arg2;
9971 tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
9972 enum insn_code icode = (enum insn_code) DECL_FUNCTION_CODE (fndecl);
9976 /* Note that a switch statement instead of the sequence of tests would
9977 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9978 and that would yield multiple alternatives with identical values. */
9979 if (icode == CODE_FOR_alignaddrsi_vis
9980 || icode == CODE_FOR_alignaddrdi_vis
9981 || icode == CODE_FOR_wrgsr_vis
9982 || icode == CODE_FOR_bmasksi_vis
9983 || icode == CODE_FOR_bmaskdi_vis
9984 || icode == CODE_FOR_cmask8si_vis
9985 || icode == CODE_FOR_cmask8di_vis
9986 || icode == CODE_FOR_cmask16si_vis
9987 || icode == CODE_FOR_cmask16di_vis
9988 || icode == CODE_FOR_cmask32si_vis
9989 || icode == CODE_FOR_cmask32di_vis)
9992 return build_zero_cst (rtype);
9997 case CODE_FOR_fexpand_vis:
10001 if (TREE_CODE (arg0) == VECTOR_CST)
10003 tree inner_type = TREE_TYPE (rtype);
10004 tree elts = TREE_VECTOR_CST_ELTS (arg0);
10005 tree n_elts = NULL_TREE;
10007 for (; elts; elts = TREE_CHAIN (elts))
10009 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4;
10010 n_elts = tree_cons (NULL_TREE,
10011 build_int_cst (inner_type, val),
10014 return build_vector (rtype, nreverse (n_elts));
10018 case CODE_FOR_fmul8x16_vis:
10019 case CODE_FOR_fmul8x16au_vis:
10020 case CODE_FOR_fmul8x16al_vis:
10026 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10028 tree inner_type = TREE_TYPE (rtype);
10029 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
10030 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
10031 tree n_elts = sparc_handle_vis_mul8x16 (icode, inner_type, elts0,
10034 return build_vector (rtype, n_elts);
10038 case CODE_FOR_fpmerge_vis:
10044 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST)
10046 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
10047 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
10048 tree n_elts = NULL_TREE;
10050 for (; elts0 && elts1;
10051 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
10053 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts);
10054 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts);
10057 return build_vector (rtype, nreverse (n_elts));
10061 case CODE_FOR_pdist_vis:
10069 if (TREE_CODE (arg0) == VECTOR_CST
10070 && TREE_CODE (arg1) == VECTOR_CST
10071 && TREE_CODE (arg2) == INTEGER_CST)
10074 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2);
10075 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2);
10076 tree elts0 = TREE_VECTOR_CST_ELTS (arg0);
10077 tree elts1 = TREE_VECTOR_CST_ELTS (arg1);
10079 for (; elts0 && elts1;
10080 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1))
10082 unsigned HOST_WIDE_INT
10083 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)),
10084 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1));
10085 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0));
10086 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1));
10088 unsigned HOST_WIDE_INT l;
10091 overflow |= neg_double (low1, high1, &l, &h);
10092 overflow |= add_double (low0, high0, l, h, &l, &h);
10094 overflow |= neg_double (l, h, &l, &h);
10096 overflow |= add_double (low, high, l, h, &low, &high);
10099 gcc_assert (overflow == 0);
10101 return build_int_cst_wide (rtype, low, high);
10111 /* ??? This duplicates information provided to the compiler by the
10112 ??? scheduler description. Some day, teach genautomata to output
10113 ??? the latencies and then CSE will just use that. */
10116 sparc_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
10117 int *total, bool speed ATTRIBUTE_UNUSED)
10119 enum machine_mode mode = GET_MODE (x);
10120 bool float_mode_p = FLOAT_MODE_P (mode);
10125 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
10143 if (GET_MODE (x) == VOIDmode
10144 && ((CONST_DOUBLE_HIGH (x) == 0
10145 && CONST_DOUBLE_LOW (x) < 0x1000)
10146 || (CONST_DOUBLE_HIGH (x) == -1
10147 && CONST_DOUBLE_LOW (x) < 0
10148 && CONST_DOUBLE_LOW (x) >= -0x1000)))
10155 /* If outer-code was a sign or zero extension, a cost
10156 of COSTS_N_INSNS (1) was already added in. This is
10157 why we are subtracting it back out. */
10158 if (outer_code == ZERO_EXTEND)
10160 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
10162 else if (outer_code == SIGN_EXTEND)
10164 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
10166 else if (float_mode_p)
10168 *total = sparc_costs->float_load;
10172 *total = sparc_costs->int_load;
10180 *total = sparc_costs->float_plusminus;
10182 *total = COSTS_N_INSNS (1);
10189 gcc_assert (float_mode_p);
10190 *total = sparc_costs->float_mul;
10193 if (GET_CODE (sub) == NEG)
10194 sub = XEXP (sub, 0);
10195 *total += rtx_cost (sub, FMA, 0, speed);
10198 if (GET_CODE (sub) == NEG)
10199 sub = XEXP (sub, 0);
10200 *total += rtx_cost (sub, FMA, 2, speed);
10206 *total = sparc_costs->float_mul;
10207 else if (! TARGET_HARD_MUL)
10208 *total = COSTS_N_INSNS (25);
10214 if (sparc_costs->int_mul_bit_factor)
10218 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
10220 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
10221 for (nbits = 0; value != 0; value &= value - 1)
10224 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
10225 && GET_MODE (XEXP (x, 1)) == VOIDmode)
10227 rtx x1 = XEXP (x, 1);
10228 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1);
10229 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1);
10231 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
10233 for (; value2 != 0; value2 &= value2 - 1)
10241 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
10242 bit_cost = COSTS_N_INSNS (bit_cost);
10245 if (mode == DImode)
10246 *total = sparc_costs->int_mulX + bit_cost;
10248 *total = sparc_costs->int_mul + bit_cost;
10255 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
10264 if (mode == DFmode)
10265 *total = sparc_costs->float_div_df;
10267 *total = sparc_costs->float_div_sf;
10271 if (mode == DImode)
10272 *total = sparc_costs->int_divX;
10274 *total = sparc_costs->int_div;
10279 if (! float_mode_p)
10281 *total = COSTS_N_INSNS (1);
10288 case UNSIGNED_FLOAT:
10292 case FLOAT_TRUNCATE:
10293 *total = sparc_costs->float_move;
10297 if (mode == DFmode)
10298 *total = sparc_costs->float_sqrt_df;
10300 *total = sparc_costs->float_sqrt_sf;
10305 *total = sparc_costs->float_cmp;
10307 *total = COSTS_N_INSNS (1);
10312 *total = sparc_costs->float_cmove;
10314 *total = sparc_costs->int_cmove;
10318 /* Handle the NAND vector patterns. */
10319 if (sparc_vector_mode_supported_p (GET_MODE (x))
10320 && GET_CODE (XEXP (x, 0)) == NOT
10321 && GET_CODE (XEXP (x, 1)) == NOT)
10323 *total = COSTS_N_INSNS (1);
10334 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10337 general_or_i64_p (reg_class_t rclass)
10339 return (rclass == GENERAL_REGS || rclass == I64_REGS);
10342 /* Implement TARGET_REGISTER_MOVE_COST. */
10345 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10346 reg_class_t from, reg_class_t to)
10348 bool need_memory = false;
10350 if (from == FPCC_REGS || to == FPCC_REGS)
10351 need_memory = true;
10352 else if ((FP_REG_CLASS_P (from) && general_or_i64_p (to))
10353 || (general_or_i64_p (from) && FP_REG_CLASS_P (to)))
10357 int size = GET_MODE_SIZE (mode);
10358 if (size == 8 || size == 4)
10360 if (! TARGET_ARCH32 || size == 4)
10366 need_memory = true;
10371 if (sparc_cpu == PROCESSOR_ULTRASPARC
10372 || sparc_cpu == PROCESSOR_ULTRASPARC3
10373 || sparc_cpu == PROCESSOR_NIAGARA
10374 || sparc_cpu == PROCESSOR_NIAGARA2
10375 || sparc_cpu == PROCESSOR_NIAGARA3
10376 || sparc_cpu == PROCESSOR_NIAGARA4)
10385 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10386 This is achieved by means of a manual dynamic stack space allocation in
10387 the current frame. We make the assumption that SEQ doesn't contain any
10388 function calls, with the possible exception of calls to the GOT helper. */
10391 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
10393 /* We must preserve the lowest 16 words for the register save area. */
10394 HOST_WIDE_INT offset = 16*UNITS_PER_WORD;
10395 /* We really need only 2 words of fresh stack space. */
10396 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD);
10399 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx,
10400 SPARC_STACK_BIAS + offset));
10402 emit_insn (gen_stack_pointer_dec (GEN_INT (size)));
10403 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
10405 emit_insn (gen_rtx_SET (VOIDmode,
10406 adjust_address (slot, word_mode, UNITS_PER_WORD),
10410 emit_insn (gen_rtx_SET (VOIDmode,
10412 adjust_address (slot, word_mode, UNITS_PER_WORD)));
10413 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
10414 emit_insn (gen_stack_pointer_inc (GEN_INT (size)));
10417 /* Output the assembler code for a thunk function. THUNK_DECL is the
10418 declaration for the thunk function itself, FUNCTION is the decl for
10419 the target function. DELTA is an immediate constant offset to be
10420 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10421 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10424 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10425 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10428 rtx this_rtx, insn, funexp;
10429 unsigned int int_arg_first;
10431 reload_completed = 1;
10432 epilogue_completed = 1;
10434 emit_note (NOTE_INSN_PROLOGUE_END);
10438 sparc_leaf_function_p = 1;
10440 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10442 else if (flag_delayed_branch)
10444 /* We will emit a regular sibcall below, so we need to instruct
10445 output_sibcall that we are in a leaf function. */
10446 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
10448 /* This will cause final.c to invoke leaf_renumber_regs so we
10449 must behave as if we were in a not-yet-leafified function. */
10450 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
10454 /* We will emit the sibcall manually below, so we will need to
10455 manually spill non-leaf registers. */
10456 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
10458 /* We really are in a leaf function. */
10459 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
10462 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10463 returns a structure, the structure return pointer is there instead. */
10465 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10466 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1);
10468 this_rtx = gen_rtx_REG (Pmode, int_arg_first);
10470 /* Add DELTA. When possible use a plain add, otherwise load it into
10471 a register first. */
10474 rtx delta_rtx = GEN_INT (delta);
10476 if (! SPARC_SIMM13_P (delta))
10478 rtx scratch = gen_rtx_REG (Pmode, 1);
10479 emit_move_insn (scratch, delta_rtx);
10480 delta_rtx = scratch;
10483 /* THIS_RTX += DELTA. */
10484 emit_insn (gen_add2_insn (this_rtx, delta_rtx));
10487 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10490 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10491 rtx scratch = gen_rtx_REG (Pmode, 1);
10493 gcc_assert (vcall_offset < 0);
10495 /* SCRATCH = *THIS_RTX. */
10496 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx));
10498 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10499 may not have any available scratch register at this point. */
10500 if (SPARC_SIMM13_P (vcall_offset))
10502 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10503 else if (! fixed_regs[5]
10504 /* The below sequence is made up of at least 2 insns,
10505 while the default method may need only one. */
10506 && vcall_offset < -8192)
10508 rtx scratch2 = gen_rtx_REG (Pmode, 5);
10509 emit_move_insn (scratch2, vcall_offset_rtx);
10510 vcall_offset_rtx = scratch2;
10514 rtx increment = GEN_INT (-4096);
10516 /* VCALL_OFFSET is a negative number whose typical range can be
10517 estimated as -32768..0 in 32-bit mode. In almost all cases
10518 it is therefore cheaper to emit multiple add insns than
10519 spilling and loading the constant into a register (at least
10521 while (! SPARC_SIMM13_P (vcall_offset))
10523 emit_insn (gen_add2_insn (scratch, increment));
10524 vcall_offset += 4096;
10526 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
10529 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10530 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
10531 gen_rtx_PLUS (Pmode,
10533 vcall_offset_rtx)));
10535 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10536 emit_insn (gen_add2_insn (this_rtx, scratch));
10539 /* Generate a tail call to the target function. */
10540 if (! TREE_USED (function))
10542 assemble_external (function);
10543 TREE_USED (function) = 1;
10545 funexp = XEXP (DECL_RTL (function), 0);
10547 if (flag_delayed_branch)
10549 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10550 insn = emit_call_insn (gen_sibcall (funexp));
10551 SIBLING_CALL_P (insn) = 1;
10555 /* The hoops we have to jump through in order to generate a sibcall
10556 without using delay slots... */
10557 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
10561 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
10563 load_got_register (); /* clobbers %o7 */
10564 scratch = sparc_legitimize_pic_address (funexp, scratch);
10565 seq = get_insns ();
10567 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
10569 else if (TARGET_ARCH32)
10571 emit_insn (gen_rtx_SET (VOIDmode,
10573 gen_rtx_HIGH (SImode, funexp)));
10574 emit_insn (gen_rtx_SET (VOIDmode,
10576 gen_rtx_LO_SUM (SImode, scratch, funexp)));
10578 else /* TARGET_ARCH64 */
10580 switch (sparc_cmodel)
10584 /* The destination can serve as a temporary. */
10585 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
10590 /* The destination cannot serve as a temporary. */
10591 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
10593 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
10594 seq = get_insns ();
10596 emit_and_preserve (seq, spill_reg, 0);
10600 gcc_unreachable ();
10604 emit_jump_insn (gen_indirect_jump (scratch));
10609 /* Run just enough of rest_of_compilation to get the insns emitted.
10610 There's not really enough bulk here to make other passes such as
10611 instruction scheduling worth while. Note that use_thunk calls
10612 assemble_start_function and assemble_end_function. */
10613 insn = get_insns ();
10614 insn_locators_alloc ();
10615 shorten_branches (insn);
10616 final_start_function (insn, file, 1);
10617 final (insn, file, 1);
10618 final_end_function ();
10620 reload_completed = 0;
10621 epilogue_completed = 0;
10624 /* Return true if sparc_output_mi_thunk would be able to output the
10625 assembler code for the thunk function specified by the arguments
10626 it is passed, and false otherwise. */
10628 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
10629 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
10630 HOST_WIDE_INT vcall_offset,
10631 const_tree function ATTRIBUTE_UNUSED)
10633 /* Bound the loop used in the default method above. */
10634 return (vcall_offset >= -32768 || ! fixed_regs[5]);
10637 /* We use the machine specific reorg pass to enable workarounds for errata. */
10644 /* The only erratum we handle for now is that of the AT697F processor. */
10645 if (!sparc_fix_at697f)
10648 /* We need to have the (essentially) final form of the insn stream in order
10649 to properly detect the various hazards. Run delay slot scheduling. */
10650 if (optimize > 0 && flag_delayed_branch)
10651 dbr_schedule (get_insns ());
10653 /* Now look for specific patterns in the insn stream. */
10654 for (insn = get_insns (); insn; insn = next)
10656 bool insert_nop = false;
10659 /* Look for a single-word load into an odd-numbered FP register. */
10660 if (NONJUMP_INSN_P (insn)
10661 && (set = single_set (insn)) != NULL_RTX
10662 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
10663 && MEM_P (SET_SRC (set))
10664 && REG_P (SET_DEST (set))
10665 && REGNO (SET_DEST (set)) > 31
10666 && REGNO (SET_DEST (set)) % 2 != 0)
10668 /* The wrong dependency is on the enclosing double register. */
10669 unsigned int x = REGNO (SET_DEST (set)) - 1;
10670 unsigned int src1, src2, dest;
10673 /* If the insn has a delay slot, then it cannot be problematic. */
10674 next = next_active_insn (insn);
10675 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
10679 extract_insn (next);
10680 code = INSN_CODE (next);
10685 case CODE_FOR_adddf3:
10686 case CODE_FOR_subdf3:
10687 case CODE_FOR_muldf3:
10688 case CODE_FOR_divdf3:
10689 dest = REGNO (recog_data.operand[0]);
10690 src1 = REGNO (recog_data.operand[1]);
10691 src2 = REGNO (recog_data.operand[2]);
10695 ld [address], %fx+1
10696 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10697 if ((src1 == x || src2 == x)
10698 && (dest == src1 || dest == src2))
10704 ld [address], %fx+1
10705 FPOPd %fx, %fx, %fx */
10708 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
10713 case CODE_FOR_sqrtdf2:
10714 dest = REGNO (recog_data.operand[0]);
10715 src1 = REGNO (recog_data.operand[1]);
10717 ld [address], %fx+1
10719 if (src1 == x && dest == src1)
10728 next = NEXT_INSN (insn);
10731 emit_insn_after (gen_nop (), insn);
10735 /* How to allocate a 'struct machine_function'. */
10737 static struct machine_function *
10738 sparc_init_machine_status (void)
10740 return ggc_alloc_cleared_machine_function ();
10743 /* Locate some local-dynamic symbol still in use by this function
10744 so that we can print its name in local-dynamic base patterns. */
10746 static const char *
10747 get_some_local_dynamic_name (void)
10751 if (cfun->machine->some_ld_name)
10752 return cfun->machine->some_ld_name;
10754 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10756 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10757 return cfun->machine->some_ld_name;
10759 gcc_unreachable ();
10763 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10768 && GET_CODE (x) == SYMBOL_REF
10769 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10771 cfun->machine->some_ld_name = XSTR (x, 0);
10778 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10779 We need to emit DTP-relative relocations. */
10782 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
10787 fputs ("\t.word\t%r_tls_dtpoff32(", file);
10790 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
10793 gcc_unreachable ();
10795 output_addr_const (file, x);
10799 /* Do whatever processing is required at the end of a file. */
10802 sparc_file_end (void)
10804 /* If we need to emit the special GOT helper function, do so now. */
10805 if (got_helper_rtx)
10807 const char *name = XSTR (got_helper_rtx, 0);
10808 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
10809 #ifdef DWARF2_UNWIND_INFO
10813 if (USE_HIDDEN_LINKONCE)
10815 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
10816 get_identifier (name),
10817 build_function_type_list (void_type_node,
10819 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
10820 NULL_TREE, void_type_node);
10821 TREE_STATIC (decl) = 1;
10822 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
10823 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
10824 DECL_VISIBILITY_SPECIFIED (decl) = 1;
10825 resolve_unique_section (decl, 0, flag_function_sections);
10826 allocate_struct_function (decl, true);
10827 cfun->is_thunk = 1;
10828 current_function_decl = decl;
10829 init_varasm_status ();
10830 assemble_start_function (decl, name);
10834 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10835 switch_to_section (text_section);
10837 ASM_OUTPUT_ALIGN (asm_out_file, align);
10838 ASM_OUTPUT_LABEL (asm_out_file, name);
10841 #ifdef DWARF2_UNWIND_INFO
10842 do_cfi = dwarf2out_do_cfi_asm ();
10844 fprintf (asm_out_file, "\t.cfi_startproc\n");
10846 if (flag_delayed_branch)
10847 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10848 reg_name, reg_name);
10850 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10851 reg_name, reg_name);
10852 #ifdef DWARF2_UNWIND_INFO
10854 fprintf (asm_out_file, "\t.cfi_endproc\n");
10858 if (NEED_INDICATE_EXEC_STACK)
10859 file_end_indicate_exec_stack ();
10861 #ifdef TARGET_SOLARIS
10862 solaris_file_end ();
10866 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10867 /* Implement TARGET_MANGLE_TYPE. */
10869 static const char *
10870 sparc_mangle_type (const_tree type)
10873 && TYPE_MAIN_VARIANT (type) == long_double_type_node
10874 && TARGET_LONG_DOUBLE_128)
10877 /* For all other types, use normal C++ mangling. */
10882 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
10883 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
10884 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
10887 sparc_emit_membar_for_model (enum memmodel model,
10888 int load_store, int before_after)
10890 /* Bits for the MEMBAR mmask field. */
10891 const int LoadLoad = 1;
10892 const int StoreLoad = 2;
10893 const int LoadStore = 4;
10894 const int StoreStore = 8;
10896 int mm = 0, implied = 0;
10898 switch (sparc_memory_model)
10901 /* Sequential Consistency. All memory transactions are immediately
10902 visible in sequential execution order. No barriers needed. */
10903 implied = LoadLoad | StoreLoad | LoadStore | StoreStore;
10907 /* Total Store Ordering: all memory transactions with store semantics
10908 are followed by an implied StoreStore. */
10909 implied |= StoreStore;
10913 /* Partial Store Ordering: all memory transactions with load semantics
10914 are followed by an implied LoadLoad | LoadStore. */
10915 implied |= LoadLoad | LoadStore;
10917 /* If we're not looking for a raw barrer (before+after), then atomic
10918 operations get the benefit of being both load and store. */
10919 if (load_store == 3 && before_after == 2)
10920 implied |= StoreLoad | StoreStore;
10924 /* Relaxed Memory Ordering: no implicit bits. */
10928 gcc_unreachable ();
10931 if (before_after & 1)
10933 if (model == MEMMODEL_ACQUIRE
10934 || model == MEMMODEL_ACQ_REL
10935 || model == MEMMODEL_SEQ_CST)
10937 if (load_store & 1)
10938 mm |= LoadLoad | LoadStore;
10939 if (load_store & 2)
10940 mm |= StoreLoad | StoreStore;
10943 if (before_after & 2)
10945 if (model == MEMMODEL_RELEASE
10946 || model == MEMMODEL_ACQ_REL
10947 || model == MEMMODEL_SEQ_CST)
10949 if (load_store & 1)
10950 mm |= LoadLoad | StoreLoad;
10951 if (load_store & 2)
10952 mm |= LoadStore | StoreStore;
10956 /* Remove the bits implied by the system memory model. */
10959 /* For raw barriers (before+after), always emit a barrier.
10960 This will become a compile-time barrier if needed. */
10961 if (mm || before_after == 3)
10962 emit_insn (gen_membar (GEN_INT (mm)));
10965 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10966 compare and swap on the word containing the byte or half-word. */
10969 sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem,
10970 rtx oldval, rtx newval)
10972 rtx addr1 = force_reg (Pmode, XEXP (mem, 0));
10973 rtx addr = gen_reg_rtx (Pmode);
10974 rtx off = gen_reg_rtx (SImode);
10975 rtx oldv = gen_reg_rtx (SImode);
10976 rtx newv = gen_reg_rtx (SImode);
10977 rtx oldvalue = gen_reg_rtx (SImode);
10978 rtx newvalue = gen_reg_rtx (SImode);
10979 rtx res = gen_reg_rtx (SImode);
10980 rtx resv = gen_reg_rtx (SImode);
10981 rtx memsi, val, mask, end_label, loop_label, cc;
10983 emit_insn (gen_rtx_SET (VOIDmode, addr,
10984 gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
10986 if (Pmode != SImode)
10987 addr1 = gen_lowpart (SImode, addr1);
10988 emit_insn (gen_rtx_SET (VOIDmode, off,
10989 gen_rtx_AND (SImode, addr1, GEN_INT (3))));
10991 memsi = gen_rtx_MEM (SImode, addr);
10992 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
10993 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
10995 val = copy_to_reg (memsi);
10997 emit_insn (gen_rtx_SET (VOIDmode, off,
10998 gen_rtx_XOR (SImode, off,
10999 GEN_INT (GET_MODE (mem) == QImode
11002 emit_insn (gen_rtx_SET (VOIDmode, off,
11003 gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
11005 if (GET_MODE (mem) == QImode)
11006 mask = force_reg (SImode, GEN_INT (0xff));
11008 mask = force_reg (SImode, GEN_INT (0xffff));
11010 emit_insn (gen_rtx_SET (VOIDmode, mask,
11011 gen_rtx_ASHIFT (SImode, mask, off)));
11013 emit_insn (gen_rtx_SET (VOIDmode, val,
11014 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11017 oldval = gen_lowpart (SImode, oldval);
11018 emit_insn (gen_rtx_SET (VOIDmode, oldv,
11019 gen_rtx_ASHIFT (SImode, oldval, off)));
11021 newval = gen_lowpart_common (SImode, newval);
11022 emit_insn (gen_rtx_SET (VOIDmode, newv,
11023 gen_rtx_ASHIFT (SImode, newval, off)));
11025 emit_insn (gen_rtx_SET (VOIDmode, oldv,
11026 gen_rtx_AND (SImode, oldv, mask)));
11028 emit_insn (gen_rtx_SET (VOIDmode, newv,
11029 gen_rtx_AND (SImode, newv, mask)));
11031 end_label = gen_label_rtx ();
11032 loop_label = gen_label_rtx ();
11033 emit_label (loop_label);
11035 emit_insn (gen_rtx_SET (VOIDmode, oldvalue,
11036 gen_rtx_IOR (SImode, oldv, val)));
11038 emit_insn (gen_rtx_SET (VOIDmode, newvalue,
11039 gen_rtx_IOR (SImode, newv, val)));
11041 emit_move_insn (bool_result, const1_rtx);
11043 emit_insn (gen_atomic_compare_and_swapsi_1 (res, memsi, oldvalue, newvalue));
11045 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label);
11047 emit_insn (gen_rtx_SET (VOIDmode, resv,
11048 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask),
11051 emit_move_insn (bool_result, const0_rtx);
11053 cc = gen_compare_reg_1 (NE, resv, val);
11054 emit_insn (gen_rtx_SET (VOIDmode, val, resv));
11056 /* Use cbranchcc4 to separate the compare and branch! */
11057 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx),
11058 cc, const0_rtx, loop_label));
11060 emit_label (end_label);
11062 emit_insn (gen_rtx_SET (VOIDmode, res,
11063 gen_rtx_AND (SImode, res, mask)));
11065 emit_insn (gen_rtx_SET (VOIDmode, res,
11066 gen_rtx_LSHIFTRT (SImode, res, off)));
11068 emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
11071 /* Expand code to perform a compare-and-swap. */
11074 sparc_expand_compare_and_swap (rtx operands[])
11076 rtx bval, retval, mem, oldval, newval;
11077 enum machine_mode mode;
11078 enum memmodel model;
11080 bval = operands[0];
11081 retval = operands[1];
11083 oldval = operands[3];
11084 newval = operands[4];
11085 model = (enum memmodel) INTVAL (operands[6]);
11086 mode = GET_MODE (mem);
11088 sparc_emit_membar_for_model (model, 3, 1);
11090 if (reg_overlap_mentioned_p (retval, oldval))
11091 oldval = copy_to_reg (oldval);
11093 if (mode == QImode || mode == HImode)
11094 sparc_expand_compare_and_swap_12 (bval, retval, mem, oldval, newval);
11097 rtx (*gen) (rtx, rtx, rtx, rtx);
11100 if (mode == SImode)
11101 gen = gen_atomic_compare_and_swapsi_1;
11103 gen = gen_atomic_compare_and_swapdi_1;
11104 emit_insn (gen (retval, mem, oldval, newval));
11106 x = emit_store_flag (bval, EQ, retval, oldval, mode, 1, 1);
11108 convert_move (bval, x, 1);
11111 sparc_emit_membar_for_model (model, 3, 2);
11115 sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
11119 sel = gen_lowpart (DImode, sel);
11123 /* inp = xxxxxxxAxxxxxxxB */
11124 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11125 NULL_RTX, 1, OPTAB_DIRECT);
11126 /* t_1 = ....xxxxxxxAxxx. */
11127 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11128 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
11129 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11130 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
11131 /* sel = .......B */
11132 /* t_1 = ...A.... */
11133 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11134 /* sel = ...A...B */
11135 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
11136 /* sel = AAAABBBB * 4 */
11137 t_1 = force_reg (SImode, GEN_INT (0x01230123));
11138 /* sel = { A*4, A*4+1, A*4+2, ... } */
11142 /* inp = xxxAxxxBxxxCxxxD */
11143 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11144 NULL_RTX, 1, OPTAB_DIRECT);
11145 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11146 NULL_RTX, 1, OPTAB_DIRECT);
11147 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
11148 NULL_RTX, 1, OPTAB_DIRECT);
11149 /* t_1 = ..xxxAxxxBxxxCxx */
11150 /* t_2 = ....xxxAxxxBxxxC */
11151 /* t_3 = ......xxxAxxxBxx */
11152 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
11154 NULL_RTX, 1, OPTAB_DIRECT);
11155 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
11157 NULL_RTX, 1, OPTAB_DIRECT);
11158 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
11159 GEN_INT (0x070000),
11160 NULL_RTX, 1, OPTAB_DIRECT);
11161 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
11162 GEN_INT (0x07000000),
11163 NULL_RTX, 1, OPTAB_DIRECT);
11164 /* sel = .......D */
11165 /* t_1 = .....C.. */
11166 /* t_2 = ...B.... */
11167 /* t_3 = .A...... */
11168 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
11169 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
11170 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
11171 /* sel = .A.B.C.D */
11172 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
11173 /* sel = AABBCCDD * 2 */
11174 t_1 = force_reg (SImode, GEN_INT (0x01010101));
11175 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11179 /* input = xAxBxCxDxExFxGxH */
11180 sel = expand_simple_binop (DImode, AND, sel,
11181 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
11183 NULL_RTX, 1, OPTAB_DIRECT);
11184 /* sel = .A.B.C.D.E.F.G.H */
11185 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
11186 NULL_RTX, 1, OPTAB_DIRECT);
11187 /* t_1 = ..A.B.C.D.E.F.G. */
11188 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11189 NULL_RTX, 1, OPTAB_DIRECT);
11190 /* sel = .AABBCCDDEEFFGGH */
11191 sel = expand_simple_binop (DImode, AND, sel,
11192 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
11194 NULL_RTX, 1, OPTAB_DIRECT);
11195 /* sel = ..AB..CD..EF..GH */
11196 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
11197 NULL_RTX, 1, OPTAB_DIRECT);
11198 /* t_1 = ....AB..CD..EF.. */
11199 sel = expand_simple_binop (DImode, IOR, sel, t_1,
11200 NULL_RTX, 1, OPTAB_DIRECT);
11201 /* sel = ..ABABCDCDEFEFGH */
11202 sel = expand_simple_binop (DImode, AND, sel,
11203 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
11204 NULL_RTX, 1, OPTAB_DIRECT);
11205 /* sel = ....ABCD....EFGH */
11206 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
11207 NULL_RTX, 1, OPTAB_DIRECT);
11208 /* t_1 = ........ABCD.... */
11209 sel = gen_lowpart (SImode, sel);
11210 t_1 = gen_lowpart (SImode, t_1);
11214 gcc_unreachable ();
11217 /* Always perform the final addition/merge within the bmask insn. */
11218 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
11221 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11224 sparc_frame_pointer_required (void)
11226 /* If the stack pointer is dynamically modified in the function, it cannot
11227 serve as the frame pointer. */
11228 if (cfun->calls_alloca)
11231 /* If the function receives nonlocal gotos, it needs to save the frame
11232 pointer in the nonlocal_goto_save_area object. */
11233 if (cfun->has_nonlocal_label)
11236 /* In flat mode, that's it. */
11240 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11241 return !(current_function_is_leaf && only_leaf_regs_used ());
11244 /* The way this is structured, we can't eliminate SFP in favor of SP
11245 if the frame pointer is required: we want to use the SFP->HFP elimination
11246 in that case. But the test in update_eliminables doesn't know we are
11247 assuming below that we only do the former elimination. */
11250 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
11252 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
11255 /* Return the hard frame pointer directly to bypass the stack bias. */
11258 sparc_builtin_setjmp_frame_value (void)
11260 return hard_frame_pointer_rtx;
11263 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11264 they won't be allocated. */
11267 sparc_conditional_register_usage (void)
11269 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
11271 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11272 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11274 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11275 /* then honor it. */
11276 if (TARGET_ARCH32 && fixed_regs[5])
11278 else if (TARGET_ARCH64 && fixed_regs[5] == 2)
11283 for (regno = SPARC_FIRST_V9_FP_REG;
11284 regno <= SPARC_LAST_V9_FP_REG;
11286 fixed_regs[regno] = 1;
11287 /* %fcc0 is used by v8 and v9. */
11288 for (regno = SPARC_FIRST_V9_FCC_REG + 1;
11289 regno <= SPARC_LAST_V9_FCC_REG;
11291 fixed_regs[regno] = 1;
11296 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++)
11297 fixed_regs[regno] = 1;
11299 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
11300 /* then honor it. Likewise with g3 and g4. */
11301 if (fixed_regs[2] == 2)
11302 fixed_regs[2] = ! TARGET_APP_REGS;
11303 if (fixed_regs[3] == 2)
11304 fixed_regs[3] = ! TARGET_APP_REGS;
11305 if (TARGET_ARCH32 && fixed_regs[4] == 2)
11306 fixed_regs[4] = ! TARGET_APP_REGS;
11307 else if (TARGET_CM_EMBMEDANY)
11309 else if (fixed_regs[4] == 2)
11314 /* Disable leaf functions. */
11315 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
11316 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
11317 leaf_reg_remap [regno] = regno;
11320 global_regs[SPARC_GSR_REG] = 1;
11323 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
11325 - We can't load constants into FP registers.
11326 - We can't load FP constants into integer registers when soft-float,
11327 because there is no soft-float pattern with a r/F constraint.
11328 - We can't load FP constants into integer registers for TFmode unless
11329 it is 0.0L, because there is no movtf pattern with a r/F constraint.
11330 - Try and reload integer constants (symbolic or otherwise) back into
11331 registers directly, rather than having them dumped to memory. */
11334 sparc_preferred_reload_class (rtx x, reg_class_t rclass)
11336 enum machine_mode mode = GET_MODE (x);
11337 if (CONSTANT_P (x))
11339 if (FP_REG_CLASS_P (rclass)
11340 || rclass == GENERAL_OR_FP_REGS
11341 || rclass == GENERAL_OR_EXTRA_FP_REGS
11342 || (GET_MODE_CLASS (mode) == MODE_FLOAT && ! TARGET_FPU)
11343 || (mode == TFmode && ! const_zero_operand (x, mode)))
11346 if (GET_MODE_CLASS (mode) == MODE_INT)
11347 return GENERAL_REGS;
11349 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
11351 if (! FP_REG_CLASS_P (rclass)
11352 || !(const_zero_operand (x, mode)
11353 || const_all_ones_operand (x, mode)))
11360 && (rclass == EXTRA_FP_REGS
11361 || rclass == GENERAL_OR_EXTRA_FP_REGS))
11363 int regno = true_regnum (x);
11365 if (SPARC_INT_REG_P (regno))
11366 return (rclass == EXTRA_FP_REGS
11367 ? FP_REGS : GENERAL_OR_FP_REGS);
11373 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
11374 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
11377 output_v8plus_mult (rtx insn, rtx *operands, const char *opcode)
11381 gcc_assert (! TARGET_ARCH64);
11383 if (sparc_check_64 (operands[1], insn) <= 0)
11384 output_asm_insn ("srl\t%L1, 0, %L1", operands);
11385 if (which_alternative == 1)
11386 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
11387 if (GET_CODE (operands[2]) == CONST_INT)
11389 if (which_alternative == 1)
11391 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11392 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", opcode);
11393 output_asm_insn (mulstr, operands);
11394 return "srlx\t%L0, 32, %H0";
11398 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11399 output_asm_insn ("or\t%L1, %3, %3", operands);
11400 sprintf (mulstr, "%s\t%%3, %%2, %%3", opcode);
11401 output_asm_insn (mulstr, operands);
11402 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11403 return "mov\t%3, %L0";
11406 else if (rtx_equal_p (operands[1], operands[2]))
11408 if (which_alternative == 1)
11410 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11411 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", opcode);
11412 output_asm_insn (mulstr, operands);
11413 return "srlx\t%L0, 32, %H0";
11417 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11418 output_asm_insn ("or\t%L1, %3, %3", operands);
11419 sprintf (mulstr, "%s\t%%3, %%3, %%3", opcode);
11420 output_asm_insn (mulstr, operands);
11421 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11422 return "mov\t%3, %L0";
11425 if (sparc_check_64 (operands[2], insn) <= 0)
11426 output_asm_insn ("srl\t%L2, 0, %L2", operands);
11427 if (which_alternative == 1)
11429 output_asm_insn ("or\t%L1, %H1, %H1", operands);
11430 output_asm_insn ("sllx\t%H2, 32, %L1", operands);
11431 output_asm_insn ("or\t%L2, %L1, %L1", operands);
11432 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", opcode);
11433 output_asm_insn (mulstr, operands);
11434 return "srlx\t%L0, 32, %H0";
11438 output_asm_insn ("sllx\t%H1, 32, %3", operands);
11439 output_asm_insn ("sllx\t%H2, 32, %4", operands);
11440 output_asm_insn ("or\t%L1, %3, %3", operands);
11441 output_asm_insn ("or\t%L2, %4, %4", operands);
11442 sprintf (mulstr, "%s\t%%3, %%4, %%3", opcode);
11443 output_asm_insn (mulstr, operands);
11444 output_asm_insn ("srlx\t%3, 32, %H0", operands);
11445 return "mov\t%3, %L0";
11449 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
11450 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
11451 and INNER_MODE are the modes describing TARGET. */
11454 vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
11455 enum machine_mode inner_mode)
11457 rtx t1, final_insn;
11460 t1 = gen_reg_rtx (mode);
11462 elt = convert_modes (SImode, inner_mode, elt, true);
11463 emit_move_insn (gen_lowpart(SImode, t1), elt);
11468 final_insn = gen_bshufflev2si_vis (target, t1, t1);
11469 bmask = 0x45674567;
11472 final_insn = gen_bshufflev4hi_vis (target, t1, t1);
11473 bmask = 0x67676767;
11476 final_insn = gen_bshufflev8qi_vis (target, t1, t1);
11477 bmask = 0x77777777;
11480 gcc_unreachable ();
11483 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), CONST0_RTX (SImode),
11484 force_reg (SImode, GEN_INT (bmask))));
11485 emit_insn (final_insn);
11489 vector_init_fpmerge (rtx target, rtx elt, enum machine_mode inner_mode)
11491 rtx t1, t2, t3, t3_low;
11493 t1 = gen_reg_rtx (V4QImode);
11494 elt = convert_modes (SImode, inner_mode, elt, true);
11495 emit_move_insn (gen_lowpart (SImode, t1), elt);
11497 t2 = gen_reg_rtx (V4QImode);
11498 emit_move_insn (t2, t1);
11500 t3 = gen_reg_rtx (V8QImode);
11501 t3_low = gen_lowpart (V4QImode, t3);
11503 emit_insn (gen_fpmerge_vis (t3, t1, t2));
11504 emit_move_insn (t1, t3_low);
11505 emit_move_insn (t2, t3_low);
11507 emit_insn (gen_fpmerge_vis (t3, t1, t2));
11508 emit_move_insn (t1, t3_low);
11509 emit_move_insn (t2, t3_low);
11511 emit_insn (gen_fpmerge_vis (gen_lowpart (V8QImode, target), t1, t2));
11515 vector_init_faligndata (rtx target, rtx elt, enum machine_mode inner_mode)
11517 rtx t1 = gen_reg_rtx (V4HImode);
11519 elt = convert_modes (SImode, inner_mode, elt, true);
11521 emit_move_insn (gen_lowpart (SImode, t1), elt);
11523 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode),
11524 force_reg (SImode, GEN_INT (6)),
11525 CONST0_RTX (SImode)));
11527 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
11528 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
11529 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
11530 emit_insn (gen_faligndatav4hi_vis (target, t1, target));
11533 /* Emit code to initialize TARGET to values for individual fields VALS. */
11536 sparc_expand_vector_init (rtx target, rtx vals)
11538 enum machine_mode mode = GET_MODE (target);
11539 enum machine_mode inner_mode = GET_MODE_INNER (mode);
11540 int n_elts = GET_MODE_NUNITS (mode);
11546 for (i = 0; i < n_elts; i++)
11548 rtx x = XVECEXP (vals, 0, i);
11549 if (!CONSTANT_P (x))
11552 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
11558 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
11562 if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (mode))
11564 if (GET_MODE_SIZE (inner_mode) == 4)
11566 emit_move_insn (gen_lowpart (SImode, target),
11567 gen_lowpart (SImode, XVECEXP (vals, 0, 0)));
11570 else if (GET_MODE_SIZE (inner_mode) == 8)
11572 emit_move_insn (gen_lowpart (DImode, target),
11573 gen_lowpart (DImode, XVECEXP (vals, 0, 0)));
11577 else if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (word_mode)
11578 && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode))
11580 emit_move_insn (gen_highpart (word_mode, target),
11581 gen_lowpart (word_mode, XVECEXP (vals, 0, 0)));
11582 emit_move_insn (gen_lowpart (word_mode, target),
11583 gen_lowpart (word_mode, XVECEXP (vals, 0, 1)));
11587 if (all_same && GET_MODE_SIZE (mode) == 8)
11591 vector_init_bshuffle (target, XVECEXP (vals, 0, 0), mode, inner_mode);
11594 if (mode == V8QImode)
11596 vector_init_fpmerge (target, XVECEXP (vals, 0, 0), inner_mode);
11599 if (mode == V4HImode)
11601 vector_init_faligndata (target, XVECEXP (vals, 0, 0), inner_mode);
11606 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
11607 for (i = 0; i < n_elts; i++)
11608 emit_move_insn (adjust_address_nv (mem, inner_mode,
11609 i * GET_MODE_SIZE (inner_mode)),
11610 XVECEXP (vals, 0, i));
11611 emit_move_insn (target, mem);
11614 /* Implement TARGET_SECONDARY_RELOAD. */
11617 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
11618 enum machine_mode mode, secondary_reload_info *sri)
11620 enum reg_class rclass = (enum reg_class) rclass_i;
11622 sri->icode = CODE_FOR_nothing;
11623 sri->extra_cost = 0;
11625 /* We need a temporary when loading/storing a HImode/QImode value
11626 between memory and the FPU registers. This can happen when combine puts
11627 a paradoxical subreg in a float/fix conversion insn. */
11628 if (FP_REG_CLASS_P (rclass)
11629 && (mode == HImode || mode == QImode)
11630 && (GET_CODE (x) == MEM
11631 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
11632 && true_regnum (x) == -1)))
11633 return GENERAL_REGS;
11635 /* On 32-bit we need a temporary when loading/storing a DFmode value
11636 between unaligned memory and the upper FPU registers. */
11638 && rclass == EXTRA_FP_REGS
11640 && GET_CODE (x) == MEM
11641 && ! mem_min_alignment (x, 8))
11644 if (((TARGET_CM_MEDANY
11645 && symbolic_operand (x, mode))
11646 || (TARGET_CM_EMBMEDANY
11647 && text_segment_operand (x, mode)))
11651 sri->icode = direct_optab_handler (reload_in_optab, mode);
11653 sri->icode = direct_optab_handler (reload_out_optab, mode);
11657 if (TARGET_VIS3 && TARGET_ARCH32)
11659 int regno = true_regnum (x);
11661 /* When using VIS3 fp<-->int register moves, on 32-bit we have
11662 to move 8-byte values in 4-byte pieces. This only works via
11663 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
11664 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
11665 an FP_REGS intermediate move. */
11666 if ((rclass == EXTRA_FP_REGS && SPARC_INT_REG_P (regno))
11667 || ((general_or_i64_p (rclass)
11668 || rclass == GENERAL_OR_FP_REGS)
11669 && SPARC_FP_REG_P (regno)))
11671 sri->extra_cost = 2;
11679 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
11680 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
11683 sparc_expand_conditional_move (enum machine_mode mode, rtx *operands)
11685 enum rtx_code rc = GET_CODE (operands[1]);
11686 enum machine_mode cmp_mode;
11687 rtx cc_reg, dst, cmp;
11690 if (GET_MODE (XEXP (cmp, 0)) == DImode && !TARGET_ARCH64)
11693 if (GET_MODE (XEXP (cmp, 0)) == TFmode && !TARGET_HARD_QUAD)
11694 cmp = sparc_emit_float_lib_cmp (XEXP (cmp, 0), XEXP (cmp, 1), rc);
11696 cmp_mode = GET_MODE (XEXP (cmp, 0));
11697 rc = GET_CODE (cmp);
11700 if (! rtx_equal_p (operands[2], dst)
11701 && ! rtx_equal_p (operands[3], dst))
11703 if (reg_overlap_mentioned_p (dst, cmp))
11704 dst = gen_reg_rtx (mode);
11706 emit_move_insn (dst, operands[3]);
11708 else if (operands[2] == dst)
11710 operands[2] = operands[3];
11712 if (GET_MODE_CLASS (cmp_mode) == MODE_FLOAT)
11713 rc = reverse_condition_maybe_unordered (rc);
11715 rc = reverse_condition (rc);
11718 if (XEXP (cmp, 1) == const0_rtx
11719 && GET_CODE (XEXP (cmp, 0)) == REG
11720 && cmp_mode == DImode
11721 && v9_regcmp_p (rc))
11722 cc_reg = XEXP (cmp, 0);
11724 cc_reg = gen_compare_reg_1 (rc, XEXP (cmp, 0), XEXP (cmp, 1));
11726 cmp = gen_rtx_fmt_ee (rc, GET_MODE (cc_reg), cc_reg, const0_rtx);
11728 emit_insn (gen_rtx_SET (VOIDmode, dst,
11729 gen_rtx_IF_THEN_ELSE (mode, cmp, operands[2], dst)));
11731 if (dst != operands[0])
11732 emit_move_insn (operands[0], dst);
11737 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
11738 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
11739 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
11740 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
11741 code to be used for the condition mask. */
11744 sparc_expand_vcond (enum machine_mode mode, rtx *operands, int ccode, int fcode)
11746 rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr;
11747 enum rtx_code code = GET_CODE (operands[3]);
11749 mask = gen_reg_rtx (Pmode);
11750 cop0 = operands[4];
11751 cop1 = operands[5];
11752 if (code == LT || code == GE)
11756 code = swap_condition (code);
11757 t = cop0; cop0 = cop1; cop1 = t;
11760 gsr = gen_rtx_REG (DImode, SPARC_GSR_REG);
11762 fcmp = gen_rtx_UNSPEC (Pmode,
11763 gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)),
11766 cmask = gen_rtx_UNSPEC (DImode,
11767 gen_rtvec (2, mask, gsr),
11770 bshuf = gen_rtx_UNSPEC (mode,
11771 gen_rtvec (3, operands[1], operands[2], gsr),
11774 emit_insn (gen_rtx_SET (VOIDmode, mask, fcmp));
11775 emit_insn (gen_rtx_SET (VOIDmode, gsr, cmask));
11777 emit_insn (gen_rtx_SET (VOIDmode, operands[0], bshuf));
11780 /* On sparc, any mode which naturally allocates into the float
11781 registers should return 4 here. */
11784 sparc_regmode_natural_size (enum machine_mode mode)
11786 int size = UNITS_PER_WORD;
11790 enum mode_class mclass = GET_MODE_CLASS (mode);
11792 if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT)
11799 /* Return TRUE if it is a good idea to tie two pseudo registers
11800 when one has mode MODE1 and one has mode MODE2.
11801 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
11802 for any hard reg, then this must be FALSE for correct output.
11804 For V9 we have to deal with the fact that only the lower 32 floating
11805 point registers are 32-bit addressable. */
11808 sparc_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11810 enum mode_class mclass1, mclass2;
11811 unsigned short size1, size2;
11813 if (mode1 == mode2)
11816 mclass1 = GET_MODE_CLASS (mode1);
11817 mclass2 = GET_MODE_CLASS (mode2);
11818 if (mclass1 != mclass2)
11824 /* Classes are the same and we are V9 so we have to deal with upper
11825 vs. lower floating point registers. If one of the modes is a
11826 4-byte mode, and the other is not, we have to mark them as not
11827 tieable because only the lower 32 floating point register are
11828 addressable 32-bits at a time.
11830 We can't just test explicitly for SFmode, otherwise we won't
11831 cover the vector mode cases properly. */
11833 if (mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT)
11836 size1 = GET_MODE_SIZE (mode1);
11837 size2 = GET_MODE_SIZE (mode2);
11838 if ((size1 > 4 && size2 == 4)
11839 || (size2 > 4 && size1 == 4))
11845 #include "gt-sparc.h"