* sh.c (dump_table): New argument start. Changed caller.

[pf3gnuchains/gcc-fork.git] / gcc / config / sh / sh.md

;;- Machine description for Renesas / SuperH SH.
;;  Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
;;  2003, 2004 Free Software Foundation, Inc.
;;  Contributed by Steve Chamberlain (sac@cygnus.com).
;;  Improved by Jim Wilson (wilson@cygnus.com).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.


;; ??? Should prepend a * to all pattern names which are not used.
;; This will make the compiler smaller, and rebuilds after changes faster.

;; ??? Should be enhanced to include support for many more GNU superoptimizer
;; sequences.  Especially the sequences for arithmetic right shifts.

;; ??? Should check all DImode patterns for consistency and usefulness.

;; ??? The MAC.W and MAC.L instructions are not supported.  There is no
;; way to generate them.

;; ??? The cmp/str instruction is not supported.  Perhaps it can be used
;; for a str* inline function.

;; BSR is not generated by the compiler proper, but when relaxing, it
;; generates .uses pseudo-ops that allow linker relaxation to create
;; BSR.  This is actually implemented in bfd/{coff,elf32}-sh.c

;; Special constraints for SH machine description:
;;
;;    t -- T
;;    x -- mac
;;    l -- pr
;;    z -- r0
;;
;; Special formats used for outputting SH instructions:
;;
;;   %.  --  print a .s if insn needs delay slot
;;   %@  --  print rte/rts if is/isn't an interrupt function
;;   %#  --  output a nop if there is nothing to put in the delay slot
;;   %O  --  print a constant without the #
;;   %R  --  print the lsw reg of a double
;;   %S  --  print the msw reg of a double
;;   %T  --  print next word of a double REG or MEM
;;
;; Special predicates:
;;
;;  arith_operand          -- operand is valid source for arithmetic op
;;  arith_reg_operand      -- operand is valid register for arithmetic op
;;  general_movdst_operand -- operand is valid move destination
;;  general_movsrc_operand -- operand is valid move source
;;  logical_operand        -- operand is valid source for logical op

;; -------------------------------------------------------------------------
;; Constants
;; -------------------------------------------------------------------------

(define_constants [
  (AP_REG       145)
  (PR_REG       146)
  (T_REG        147)
  (GBR_REG      144)
  (MACH_REG     148)
  (MACL_REG     149)
  (FPUL_REG     150)
  (RAP_REG      152)

  (FPSCR_REG    151)

  (PIC_REG      12)
  (FP_REG       14)
  (SP_REG       15)

  (PR_MEDIA_REG 18)
  (T_MEDIA_REG  19)

  (R0_REG       0)
  (R1_REG       1)
  (R2_REG       2)
  (R3_REG       3)
  (R4_REG       4)
  (R5_REG       5)
  (R6_REG       6)
  (R7_REG       7)
  (R8_REG       8)
  (R9_REG       9)
  (R10_REG      10)
  (R20_REG      20)
  (R21_REG      21)
  (R22_REG      22)
  (R23_REG      23)

  (DR0_REG      64)
  (DR2_REG      66)
  (DR4_REG      68)
  (FR23_REG     87)

  (TR0_REG      128)
  (TR1_REG      129)
  (TR2_REG      130)

  (XD0_REG      136)

  ;; These are used with unspec.
  (UNSPEC_COMPACT_ARGS  0)
  (UNSPEC_MOVA          1)
  (UNSPEC_CASESI        2)
  (UNSPEC_DATALABEL     3)
  (UNSPEC_BBR           4)
  (UNSPEC_SFUNC         5)
  (UNSPEC_PIC           6)
  (UNSPEC_GOT           7)
  (UNSPEC_GOTOFF        8)
  (UNSPEC_PLT           9)
  (UNSPEC_CALLER        10)
  (UNSPEC_GOTPLT        11)
  (UNSPEC_ICACHE        12)
  (UNSPEC_INIT_TRAMP    13)
  (UNSPEC_FCOSA         14)
  (UNSPEC_FSRRA         15)
  (UNSPEC_FSINA         16)
  (UNSPEC_NSB           17)
  (UNSPEC_ALLOCO        18)
  (UNSPEC_EH_RETURN     19)
  (UNSPEC_TLSGD         20)
  (UNSPEC_TLSLDM        21)
  (UNSPEC_TLSIE         22)
  (UNSPEC_DTPOFF        23)
  (UNSPEC_GOTTPOFF      24)
  (UNSPEC_TPOFF         25)
  (UNSPEC_RA            26)

  ;; These are used with unspec_volatile.
  (UNSPECV_BLOCKAGE     0)
  (UNSPECV_ALIGN        1)
  (UNSPECV_CONST2       2)
  (UNSPECV_CONST4       4)
  (UNSPECV_CONST8       6)
  (UNSPECV_WINDOW_END   10)
  (UNSPECV_CONST_END    11)
])

;; -------------------------------------------------------------------------
;; Attributes
;; -------------------------------------------------------------------------

;; Target CPU.

(define_attr "cpu"
 "sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
  (const (symbol_ref "sh_cpu_attr")))

(define_attr "endian" "big,little"
 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
                      (const_string "little") (const_string "big"))))

;; Indicate if the default fpu mode is single precision.
(define_attr "fpu_single" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
                         (const_string "yes") (const_string "no"))))

(define_attr "fmovd" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FMOVD")
                       (const_string "yes") (const_string "no"))))
;; pipeline model
(define_attr "pipe_model" "sh1,sh4,sh5media"
  (const
   (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
          (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
         (const_string "sh1"))))

;; cbranch      conditional branch instructions
;; jump         unconditional jumps
;; arith        ordinary arithmetic
;; arith3       a compound insn that behaves similarly to a sequence of
;;              three insns of type arith
;; arith3b      like above, but might end with a redirected branch
;; load         from memory
;; load_si      Likewise, SImode variant for general register.
;; fload        Likewise, but load to fp register.
;; store        to memory
;; move         general purpose register to register
;; mt_group     other sh4 mt instructions
;; fmove        register to register, floating point
;; smpy         word precision integer multiply
;; dmpy         longword or doublelongword precision integer multiply
;; return       rts
;; pload        load of pr reg, which can't be put into delay slot of rts
;; prset        copy register to pr reg, ditto
;; pstore       store of pr reg, which can't be put into delay slot of jsr
;; prget        copy pr to register, ditto
;; pcload       pc relative load of constant value
;; pcfload      Likewise, but load to fp register.
;; pcload_si    Likewise, SImode variant for general register.
;; rte          return from exception
;; sfunc        special function call with known used registers
;; call         function call
;; fp           floating point
;; fdiv         floating point divide (or square root)
;; gp_fpul      move from general purpose register to fpul
;; fpul_gp      move from fpul to general purpose register
;; mac_gp       move from mac[lh] to general purpose register
;; dfp_arith, dfp_cmp,dfp_conv
;; ftrc_s       fix_truncsfsi2_i4
;; dfdiv        double precision floating point divide (or square root)
;; cwb          ic_invalidate_line_i
;; tls_load     load TLS related address
;; arith_media  SHmedia arithmetic, logical, and shift instructions
;; cbranch_media SHmedia conditional branch instructions
;; cmp_media    SHmedia compare instructions
;; dfdiv_media  SHmedia double precision divide and square root
;; dfmul_media  SHmedia double precision multiply instruction
;; dfparith_media SHmedia double precision floating point arithmetic
;; dfpconv_media SHmedia double precision floating point conversions
;; dmpy_media   SHmedia longword multiply
;; fcmp_media   SHmedia floating point compare instructions
;; fdiv_media   SHmedia single precision divide and square root
;; fload_media  SHmedia floating point register load instructions
;; fmove_media  SHmedia floating point register moves (inc. fabs and fneg)
;; fparith_media SHmedia single precision floating point arithmetic
;; fpconv_media SHmedia single precision floating point conversions
;; fstore_media SHmedia floating point register store instructions
;; gettr_media  SHmedia gettr instruction
;; invalidate_line_media SHmedia invalidate_line sequence
;; jump_media   SHmedia unconditional branch instructions
;; load_media   SHmedia general register load instructions
;; pt_media     SHmedia pt instruction (expanded by assembler)
;; ptabs_media  SHmedia ptabs instruction
;; store_media  SHmedia general register store instructions
;; mcmp_media   SHmedia multimedia compare, absolute, saturating ops
;; mac_media    SHmedia mac-style fixed point operations
;; d2mpy_media  SHmedia: two 32 bit integer multiplies
;; atrans       SHmedia approximate transcendental functions
;; ustore_media SHmedia unaligned stores
;; nil          no-op move, will be deleted.

(define_attr "type"
 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
  (const_string "other"))

;; We define a new attribute namely "insn_class".We use
;; this for the DFA based pipeline description.
;;
;; mt_group      SH4 "mt" group instructions.
;;
;; ex_group      SH4 "ex" group instructions.
;;
;; ls_group      SH4 "ls" group instructions.
;;

(define_attr "insn_class"
  "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
  (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
         (eq_attr "type" "arith,dyn_shift") (const_string "ex_group")
         (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,gp_fpul,fpul_gp") (const_string "ls_group")
         (eq_attr "type" "cbranch,jump") (const_string "br_group")
         (eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
           (const_string "fe_group")
         (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb") (const_string "co_group")]
        (const_string "none")))
;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
;; so these do not belong in an insn group, although they are modeled
;; with their own define_insn_reservations.

;; Indicate what precision must be selected in fpscr for this insn, if any.

(define_attr "fp_mode" "single,double,none" (const_string "none"))

;; Indicate if the fpu mode is set by this instruction
;; "unknown" must have the value as "none" in fp_mode, and means
;; that the instruction/abi has left the processor in an unknown
;; state.
;; "none" means that nothing has changed and no mode is set.
;; This attribute is only used for the Renesas ABI.
(define_attr "fp_set" "single,double,unknown,none" (const_string "none"))

; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long.  Something in the
; range -4090..4100 bytes can be 6 bytes long.  All other conditional
; branches are initially assumed to be 16 bytes long.
; In machine_dependent_reorg, we split all branches that are longer than
; 2 bytes.

;; The maximum range used for SImode constant pool entries is 1018.  A final
;; instruction can add 8 bytes while only being 4 bytes in size, thus we
;; can have a total of 1022 bytes in the pool.  Add 4 bytes for a branch
;; instruction around the pool table, 2 bytes of alignment before the table,
;; and 30 bytes of alignment after the table.  That gives a maximum total
;; pool size of 1058 bytes.
;; Worst case code/pool content size ratio is 1:2 (using asms).
;; Thus, in the worst case, there is one instruction in front of a maximum
;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
;; code.  For the last n bytes of code, there are 2n + 36 bytes of pool.
;; If we have a forward branch, the initial table will be put after the
;; unconditional branch.
;;
;; ??? We could do much better by keeping track of the actual pcloads within
;; the branch range and in the pcload range in front of the branch range.

;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
;; inside an le.
(define_attr "short_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
         (const_string "yes")
         (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "med_branch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
              (const_int 1988))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
              (const_int 8186))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "med_cbranch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
              (const_int 1986))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
               (const_int 8184))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "braf_branch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
              (const_int 20660))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
              (const_int 65530))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "braf_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
              (const_int 20658))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
              (const_int 65528))
         (const_string "yes")
         ] (const_string "no")))

; An unconditional jump in the range -4092..4098 can be 2 bytes long.
; For wider ranges, we need a combination of a code and a data part.
; If we can get a scratch register for a long range jump, the code
; part can be 4 bytes long; otherwise, it must be 8 bytes long.
; If the jump is in the range -32764..32770, the data part can be 2 bytes
; long; otherwise, it must be 6 bytes long.

; All other instructions are two bytes long by default.

;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
;; but getattrtab doesn't understand this.
(define_attr "length" ""
  (cond [(eq_attr "type" "cbranch")
         (cond [(eq_attr "short_cbranch_p" "yes")
                (const_int 2)
                (eq_attr "med_cbranch_p" "yes")
                (const_int 6)
                (eq_attr "braf_cbranch_p" "yes")
                (const_int 12)
;; ??? using pc is not computed transitively.
                (ne (match_dup 0) (match_dup 0))
                (const_int 14)
                (ne (symbol_ref ("flag_pic")) (const_int 0))
                (const_int 24)
                ] (const_int 16))
         (eq_attr "type" "jump")
         (cond [(eq_attr "med_branch_p" "yes")
                (const_int 2)
                (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
                         (symbol_ref "INSN"))
                     (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
                         (symbol_ref "code_for_indirect_jump_scratch")))
                (if_then_else (eq_attr "braf_branch_p" "yes")
                              (const_int 6)
                              (const_int 10))
                (eq_attr "braf_branch_p" "yes")
                (const_int 10)
;; ??? using pc is not computed transitively.
                (ne (match_dup 0) (match_dup 0))
                (const_int 12)
                (ne (symbol_ref ("flag_pic")) (const_int 0))
                (const_int 22)
                ] (const_int 14))
         (eq_attr "type" "pt_media")
         (if_then_else (ne (symbol_ref "TARGET_SHMEDIA64") (const_int 0))
                       (const_int 20) (const_int 12))
         ] (if_then_else (ne (symbol_ref "TARGET_SHMEDIA") (const_int 0))
                         (const_int 4)
                         (const_int 2))))

;; (define_function_unit {name} {num-units} {n-users} {test}
;;                       {ready-delay} {issue-delay} [{conflict-list}])

;; Load and store instructions save a cycle if they are aligned on a
;; four byte boundary.  Using a function unit for stores encourages
;; gcc to separate load and store instructions by one instruction,
;; which makes it more likely that the linker will be able to word
;; align them when relaxing.

;; Loads have a latency of two.
;; However, call insns can have a delay slot, so that we want one more
;; insn to be scheduled between the load of the function address and the call.
;; This is equivalent to a latency of three.
;; We cannot use a conflict list for this, because we need to distinguish
;; between the actual call address and the function arguments.
;; ADJUST_COST can only properly handle reductions of the cost, so we
;; use a latency of three here.
;; We only do this for SImode loads of general registers, to make the work
;; for ADJUST_COST easier.
(define_function_unit "memory" 1 0
  (and (eq_attr "pipe_model" "sh1")
       (eq_attr "type" "load_si,pcload_si"))
  3 2)
(define_function_unit "memory" 1 0
  (and (eq_attr "pipe_model" "sh1")
       (eq_attr "type" "load,pcload,pload,store,pstore"))
  2 2)

(define_function_unit "int"    1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "arith3,arith3b")) 3 3)

(define_function_unit "int"    1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dyn_shift")) 2 2)

(define_function_unit "int"    1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)

;; ??? These are approximations.
(define_function_unit "mpy"    1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "smpy")) 2 2)
(define_function_unit "mpy"    1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "dmpy")) 3 3)

(define_function_unit "fp"     1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fp,fmove")) 2 1)
(define_function_unit "fp"     1 0
  (and (eq_attr "pipe_model" "sh1") (eq_attr "type" "fdiv")) 13 12)


;; SH-5 SHmedia scheduling
;; When executing SHmedia code, the SH-5 is a fairly straightforward
;; single-issue machine.  It has four pipelines, the branch unit (br),
;; the integer and multimedia unit (imu), the load/store unit (lsu), and
;; the floating point unit (fpu).
;; Here model the instructions with a latency greater than one cycle.

;; Every instruction on SH-5 occupies the issue resource for at least one
;; cycle.
(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) 1 1)

;; Specify the various types of instruction which have latency > 1
(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "mcmp_media")) 2 1)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) 3 1)
;; but see sh_adjust_cost for mac_media exception.

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "fload_media,fmove_media")) 4 1)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "d2mpy_media")) 4 2)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "pt_media,ptabs_media")) 5 1)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) 6 1)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media")
       (eq_attr "type" "invalidate_line_media")) 7 7)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) 9 4)

(define_function_unit "sh5issue" 1 0
  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) 10 5)

;; Floating-point divide and square-root occupy an additional resource,
;; which is not internally pipelined.  However, other instructions
;; can continue to issue.
(define_function_unit "sh5fds" 1 0
  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media"))  19 19)

(define_function_unit "sh5fds" 1 0
  (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) 35 35)

; Definitions for filling branch delay slots.

(define_attr "needs_delay_slot" "yes,no" (const_string "no"))

;; ??? This should be (nil) instead of (const_int 0)
(define_attr "hit_stack" "yes,no"
        (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
                   (const_int 0))
               (const_string "no")]
              (const_string "yes")))

(define_attr "interrupt_function" "no,yes"
  (const (symbol_ref "current_function_interrupt")))

(define_attr "in_delay_slot" "yes,no"
  (cond [(eq_attr "type" "cbranch") (const_string "no")
         (eq_attr "type" "pcload,pcload_si") (const_string "no")
         (eq_attr "needs_delay_slot" "yes") (const_string "no")
         (eq_attr "length" "2") (const_string "yes")
         ] (const_string "no")))

(define_attr "cond_delay_slot" "yes,no"
  (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
         ] (const_string "no")))

(define_attr "is_sfunc" ""
  (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))

(define_attr "is_mac_media" ""
  (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))

(define_attr "branch_zero" "yes,no"
  (cond [(eq_attr "type" "!cbranch") (const_string "no")
         (ne (symbol_ref "(next_active_insn (insn)\
                           == (prev_active_insn\
                               (XEXP (SET_SRC (PATTERN (insn)), 1))))\
                          && get_attr_length (next_active_insn (insn)) == 2")
             (const_int 0))
         (const_string "yes")]
        (const_string "no")))

;; SH4 Double-precision computation with double-precision result -
;; the two halves are ready at different times.
(define_attr "dfp_comp" "yes,no"
  (cond [(eq_attr "type" "dfp_arith,dfp_conv,dfdiv") (const_string "yes")]
        (const_string "no")))

;; Insns for which the latency of a preceding fp insn is decreased by one.
(define_attr "late_fp_use" "yes,no" (const_string "no"))
;; And feeding insns for which this relevant.
(define_attr "any_fp_comp" "yes,no"
  (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_conv,dfdiv")
         (const_string "yes")]
        (const_string "no")))

(define_attr "any_int_load" "yes,no"
  (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
         (const_string "yes")]
        (const_string "no")))

(define_delay
  (eq_attr "needs_delay_slot" "yes")
  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])

;; On the SH and SH2, the rte instruction reads the return pc from the stack,
;; and thus we can't put a pop instruction in its delay slot.
;; ??? On the SH3, the rte instruction does not use the stack, so a pop
;; instruction can go in the delay slot.

;; Since a normal return (rts) implicitly uses the PR register,
;; we can't allow PR register loads in an rts delay slot.

(define_delay
  (eq_attr "type" "return")
  [(and (eq_attr "in_delay_slot" "yes")
        (ior (and (eq_attr "interrupt_function" "no")
                  (eq_attr "type" "!pload,prset"))
             (and (eq_attr "interrupt_function" "yes")
                  (ior
                   (ne (symbol_ref "TARGET_SH3") (const_int 0))
                   (eq_attr "hit_stack" "no"))))) (nil) (nil)])

;; Since a call implicitly uses the PR register, we can't allow
;; a PR register store in a jsr delay slot.

(define_delay
  (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
  [(and (eq_attr "in_delay_slot" "yes")
        (eq_attr "type" "!pstore,prget")) (nil) (nil)])

;; Say that we have annulled true branches, since this gives smaller and
;; faster code when branches are predicted as not taken.

(define_delay
  (and (eq_attr "type" "cbranch")
       (ne (symbol_ref "TARGET_SH2") (const_int 0)))
  ;; SH2e has a hardware bug that pretty much prohibits the use of
  ;; annuled delay slots.
  [(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
                                        (not (eq_attr "cpu" "sh2e"))) (nil)])
\f
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
;; -------------------------------------------------------------------------

(define_insn ""
  [(set (reg:SI T_REG)
        (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
                       (match_operand:SI 1 "arith_operand" "K08,r"))
               (const_int 0)))]
  "TARGET_SH1"
  "tst  %1,%0"
  [(set_attr "type" "mt_group")])

;; ??? Perhaps should only accept reg/constant if the register is reg 0.
;; That would still allow reload to create cmpi instructions, but would
;; perhaps allow forcing the constant into a register when that is better.
;; Probably should use r0 for mem/imm compares, but force constant into a
;; register for pseudo/imm compares.

(define_insn "cmpeqsi_t"
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
               (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
  "TARGET_SH1"
  "@
        tst     %0,%0
        cmp/eq  %1,%0
        cmp/eq  %1,%0"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgtsi_t"
  [(set (reg:SI T_REG)
        (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
               (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH1"
  "@
        cmp/gt  %1,%0
        cmp/pl  %0"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgesi_t"
  [(set (reg:SI T_REG)
        (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
               (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH1"
  "@
        cmp/ge  %1,%0
        cmp/pz  %0"
   [(set_attr "type" "mt_group")])

;; -------------------------------------------------------------------------
;; SImode unsigned integer comparisons
;; -------------------------------------------------------------------------

(define_insn "cmpgeusi_t"
  [(set (reg:SI T_REG)
        (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
                (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "cmp/hs       %1,%0"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgtusi_t"
  [(set (reg:SI T_REG)
        (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
                (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "cmp/hi       %1,%0"
   [(set_attr "type" "mt_group")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpsi"
  [(set (reg:SI T_REG)
        (compare (match_operand:SI 0 "cmpsi_operand" "")
                 (match_operand:SI 1 "arith_operand" "")))]
  "TARGET_SH1"
  "
{
  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == T_REG
      && GET_CODE (operands[1]) != CONST_INT)
    operands[0] = copy_to_mode_reg (SImode, operands[0]);
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
\f
;; -------------------------------------------------------------------------
;; DImode signed integer comparisons
;; -------------------------------------------------------------------------

;; ??? Could get better scheduling by splitting the initial test from the
;; rest of the insn after reload.  However, the gain would hardly justify
;; the sh.md size increase necessary to do that.

(define_insn ""
  [(set (reg:SI T_REG)
        (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
                       (match_operand:DI 1 "arith_operand" "r"))
               (const_int 0)))]
  "TARGET_SH1"
  "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
                                 insn, operands);"
  [(set_attr "length" "6")
   (set_attr "type" "arith3b")])

(define_insn "cmpeqdi_t"
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
  "TARGET_SH1"
  "@
        tst     %S0,%S0\;bf     %,Ldi%=\;tst    %R0,%R0\\n%,Ldi%=:
        cmp/eq  %S1,%S0\;bf     %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "6")
   (set_attr "type" "arith3b")])

(define_split
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
               (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
;; If we applied this split when not optimizing, it would only be
;; applied during the machine-dependent reorg, when no new basic blocks
;; may be created.
  "TARGET_SH1 && reload_completed && optimize"
  [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
   (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
                           (label_ref (match_dup 6))
                           (pc)))
   (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
   (match_dup 6)]
  "
{
  operands[2]
    = gen_rtx_REG (SImode,
                   true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  operands[3]
    = (operands[1] == const0_rtx
       ? const0_rtx
       : gen_rtx_REG (SImode,
                      true_regnum (operands[1])
                      + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
  operands[4] = gen_lowpart (SImode, operands[0]);
  operands[5] = gen_lowpart (SImode, operands[1]);
  operands[6] = gen_label_rtx ();
}")

(define_insn "cmpgtdi_t"
  [(set (reg:SI T_REG)
        (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH2"
  "@
        cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
        tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpgedi_t"
  [(set (reg:SI T_REG)
        (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH2"
  "@
        cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
        cmp/pz\\t%S0"
  [(set_attr "length" "8,2")
   (set_attr "type" "arith3,mt_group")])
\f
;; -------------------------------------------------------------------------
;; DImode unsigned integer comparisons
;; -------------------------------------------------------------------------

(define_insn "cmpgeudi_t"
  [(set (reg:SI T_REG)
        (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
                (match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpgtudi_t"
  [(set (reg:SI T_REG)
        (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
                (match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpeqdi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (eq:DI (match_operand:DI 1 "register_operand" "%r")
               (match_operand:DI 2 "arith_reg_or_0_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq        %1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtdi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (gt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
               (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt        %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtudi_media"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (gtu:DI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
                (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu       %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpdi"
  [(set (reg:SI T_REG)
        (compare (match_operand:DI 0 "arith_operand" "")
                 (match_operand:DI 1 "arith_operand" "")))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
;; -------------------------------------------------------------------------
;; Conditional move instructions
;; -------------------------------------------------------------------------

;; The insn names may seem reversed, but note that cmveq performs the move
;; if op1 == 0, and cmvne does it if op1 != 0.

(define_insn "movdicc_false"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
                             (const_int 0))
         (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movdicc_true"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
                             (const_int 0))
         (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "movdicc"
  [(set (match_operand:DI 0 "register_operand" "")
        (if_then_else:DI (match_operand 1 "comparison_operator" "")
                         (match_operand:DI 2 "register_operand" "")
                         (match_operand:DI 3 "register_operand" "")))]
  "TARGET_SHMEDIA"
  "
{
  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
      && GET_MODE (sh_compare_op0) == DImode
      && sh_compare_op1 == const0_rtx)
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
                                  sh_compare_op0, sh_compare_op1);
  else
    {
      rtx tmp;

      if (no_new_pseudos)
        FAIL;

      tmp = gen_reg_rtx (DImode);

      switch (GET_CODE (operands[1]))
        {
        case EQ:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case NE:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GT:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LT:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GE:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LE:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GTU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LTU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GEU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LEU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case ORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNEQ:
        case UNGE:
        case UNGT:
        case UNLE:
        case UNLT:
        case LTGT:
          FAIL;

        default:
          abort ();
        }
    }
}")
\f
;; -------------------------------------------------------------------------
;; Addition instructions
;; -------------------------------------------------------------------------

(define_expand "adddi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
                 (match_operand:DI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      if (no_new_pseudos && ! arith_reg_operand (operands[2], DImode))
        FAIL;
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*adddi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                 (match_operand:DI 2 "arith_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        add     %1, %2, %0
        addi    %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "adddi3z_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (zero_extend:DI
         (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
                  (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
  "TARGET_SHMEDIA"
  "addz.l       %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "adddi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
                 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
                 (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
                       true_regnum (operands[0])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
                       true_regnum (operands[2])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_addc1 (high0, high0, high2));
  DONE;
}")

(define_insn "addc"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                          (match_operand:SI 2 "arith_reg_operand" "r"))
                 (reg:SI T_REG)))
   (set (reg:SI T_REG)
        (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
  "TARGET_SH1"
  "addc %2,%0"
  [(set_attr "type" "arith")])

(define_insn "addc1"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                          (match_operand:SI 2 "arith_reg_operand" "r"))
                 (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "addc %2,%0"
  [(set_attr "type" "arith")])

(define_expand "addsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (plus:SI (match_operand:SI 1 "arith_operand" "")
                 (match_operand:SI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SHMEDIA)
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_insn "addsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
                 (match_operand:SI 2 "arith_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, %2, %0
        addi.l  %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "*addsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (plus:SI (match_operand:SI 1 "arith_operand" "%0")
                 (match_operand:SI 2 "arith_operand" "rI08")))]
  "TARGET_SH1"
  "add  %2,%0"
  [(set_attr "type" "arith")])

;; -------------------------------------------------------------------------
;; Subtraction instructions
;; -------------------------------------------------------------------------

(define_expand "subdi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
                  (match_operand:DI 2 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      operands[1] = force_reg (DImode, operands[1]);
      emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*subdi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
                  (match_operand:DI 2 "arith_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub  %N1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "subdi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=&r")
        (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
                 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
                  (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
                       true_regnum (operands[0])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
                       true_regnum (operands[2])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_subc1 (high0, high0, high2));
  DONE;
}")

(define_insn "subc"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                            (match_operand:SI 2 "arith_reg_operand" "r"))
                  (reg:SI T_REG)))
   (set (reg:SI T_REG)
        (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
                          (reg:SI T_REG))
                (match_dup 1)))]
  "TARGET_SH1"
  "subc %2,%0"
  [(set_attr "type" "arith")])

(define_insn "subc1"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                            (match_operand:SI 2 "arith_reg_operand" "r"))
                  (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "subc %2,%0"
  [(set_attr "type" "arith")])

(define_insn "*subsi3_internal"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                  (match_operand:SI 2 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "sub  %2,%0"
  [(set_attr "type" "arith")])

(define_insn "*subsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (minus:SI (match_operand:SI 1 "extend_reg_or_0_operand" "rN")
                  (match_operand:SI 2 "extend_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub.l        %N1, %2, %0"
  [(set_attr "type" "arith_media")])

;; Convert `constant - reg' to `neg rX; add rX, #const' since this
;; will sometimes save one instruction.  Otherwise we might get
;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
;; are the same.

(define_expand "subsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (minus:SI (match_operand:SI 1 "arith_operand" "")
                  (match_operand:SI 2 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1 && GET_CODE (operands[1]) == CONST_INT)
    {
      emit_insn (gen_negsi2 (operands[0], operands[2]));
      emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
      DONE;
    }
  if (TARGET_SHMEDIA)
    {
      if (no_new_pseudos && ! arith_reg_or_0_operand (operands[1], SImode))
        FAIL;
      if (operands[1] != const0_rtx)
        operands[1] = force_reg (SImode, operands[1]);
    }
}")
\f
;; -------------------------------------------------------------------------
;; Division instructions
;; -------------------------------------------------------------------------

;; We take advantage of the library routines which don't clobber as many
;; registers as a normal function call would.

;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
;; also has an effect on the register that holds the address of the sfunc.
;; To make this work, we have an extra dummy insn that shows the use
;; of this register for reorg.

(define_insn "use_sfunc_addr"
  [(set (reg:SI PR_REG)
        (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
  "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
  ""
  [(set_attr "length" "0")])

;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
;; hard register 0.  If we used hard register 0, then the next instruction
;; would be a move from hard register 0 to a pseudo-reg.  If the pseudo-reg
;; gets allocated to a stack slot that needs its address reloaded, then
;; there is nothing to prevent reload from using r0 to reload the address.
;; This reload would clobber the value in r0 we are trying to store.
;; If we let reload allocate r0, then this problem can never happen.

(define_insn "udivsi3_i1"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R4_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1 && ! TARGET_SH4"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

; Since shmedia-nofpu code could be linked against shcompact code, and
; the udivsi3 libcall has the same name, we must consider all registers
; clobbered that are in the union of the registers clobbered by the
; shmedia and the shcompact implementation.  Note, if the shcompact
; implementation actually used shcompact code, we'd need to clobber
; also r23 and fr23.
(define_insn "udivsi3_i1_media"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R20_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI R22_REG))
   (clobber (reg:DI TR0_REG))
   (clobber (reg:DI TR1_REG))
   (clobber (reg:DI TR2_REG))
   (use (match_operand:DI 1 "target_operand" "b"))]
  "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
  "blink        %1, r18"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "udivsi3_i4_media"
  [(set (match_dup 3)
        (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
   (set (match_dup 4)
        (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
   (set (match_dup 5) (float:DF (match_dup 3)))
   (set (match_dup 6) (float:DF (match_dup 4)))
   (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
   (set (match_dup 8) (fix:DI (match_dup 7)))
   (set (match_operand:SI 0 "register_operand" "")
        (truncate:SI (match_dup 8)))]
  "TARGET_SHMEDIA_FPU"
  "
{
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DFmode);
  operands[6] = gen_reg_rtx (DFmode);
  operands[7] = gen_reg_rtx (DFmode);
  operands[8] = gen_reg_rtx (DImode);
}")

(define_insn "udivsi3_i4"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:DF DR4_REG))
   (clobber (reg:SI R0_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (use (reg:PSI FPSCR_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "fp_mode" "double")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "udivsi3_i4_single"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:DF DR4_REG))
   (clobber (reg:SI R0_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "udivsi3"
  [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (udiv:SI (reg:SI R4_REG)
                            (reg:SI R5_REG)))
              (clobber (reg:SI T_REG))
              (clobber (reg:SI PR_REG))
              (clobber (reg:SI R4_REG))
              (use (match_dup 3))])]
  ""
  "
{
  rtx first, last;

  operands[3] = gen_reg_rtx (Pmode);
  /* Emit the move of the address to a pseudo outside of the libcall.  */
  if (TARGET_HARD_SH4 && TARGET_SH2E)
    {
      emit_move_insn (operands[3], function_symbol (\"__udivsi3_i4\"));
      if (TARGET_FPU_SINGLE)
        last = gen_udivsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_udivsi3_i4 (operands[0], operands[3]);
    }
  else if (TARGET_SHMEDIA_FPU)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_SH5)
    {
      emit_move_insn (operands[3],
                      function_symbol (TARGET_FPU_ANY
                                       ? \"__udivsi3_i4\"
                                       : \"__udivsi3\"));

      if (TARGET_SHMEDIA)
        last = gen_udivsi3_i1_media (operands[0],
                                     Pmode == DImode
                                     ? operands[3]
                                     : gen_rtx_SUBREG (DImode, operands[3],
                                                       0));
      else if (TARGET_FPU_ANY)
        last = gen_udivsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_udivsi3_i1 (operands[0], operands[3]);
    }
  else
    {
      emit_move_insn (operands[3], function_symbol (\"__udivsi3\"));
      last = gen_udivsi3_i1 (operands[0], operands[3]);
    }
  first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
  last = emit_insn (last);
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  DONE;
}")

(define_insn "divsi3_i1"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R2_REG))
   (clobber (reg:SI R3_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1 && ! TARGET_SH4"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

; Since shmedia-nofpu code could be linked against shcompact code, and
; the sdivsi3 libcall has the same name, we must consider all registers
; clobbered that are in the union of the registers clobbered by the
; shmedia and the shcompact implementation.  Note, if the shcompact
; implementation actually used shcompact code, we'd need to clobber
; also r22, r23 and fr23.
(define_insn "divsi3_i1_media"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R2_REG))
   (clobber (reg:SI R3_REG))
   (clobber (reg:SI R20_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:DI TR0_REG))
   (clobber (reg:DI TR1_REG))
   (clobber (reg:DI TR2_REG))
   (use (match_operand:DI 1 "target_operand" "b"))]
  "TARGET_SHMEDIA && ! TARGET_SHMEDIA_FPU"
  "blink        %1, r18"
  [(set_attr "type" "sfunc")])

(define_expand "divsi3_i4_media"
  [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
   (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
   (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
   (set (match_operand:SI 0 "register_operand" "=r")
        (fix:SI (match_dup 5)))]
  "TARGET_SHMEDIA_FPU"
  "
{
  operands[3] = gen_reg_rtx (DFmode);
  operands[4] = gen_reg_rtx (DFmode);
  operands[5] = gen_reg_rtx (DFmode);
}")

(define_insn "divsi3_i4"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (use (reg:PSI FPSCR_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "fp_mode" "double")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "divsi3_i4_single"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:SI R2_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "divsi3"
  [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (div:SI (reg:SI R4_REG)
                           (reg:SI R5_REG)))
              (clobber (reg:SI T_REG))
              (clobber (reg:SI PR_REG))
              (clobber (reg:SI R1_REG))
              (clobber (reg:SI R2_REG))
              (clobber (reg:SI R3_REG))
              (use (match_dup 3))])]
  ""
  "
{
  rtx first, last;

  operands[3] = gen_reg_rtx (Pmode);
  /* Emit the move of the address to a pseudo outside of the libcall.  */
  if (TARGET_HARD_SH4 && TARGET_SH2E)
    {
      emit_move_insn (operands[3], function_symbol (\"__sdivsi3_i4\"));
      if (TARGET_FPU_SINGLE)
        last = gen_divsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_divsi3_i4 (operands[0], operands[3]);
    }
  else if (TARGET_SHMEDIA_FPU)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_SH5)
    {
      emit_move_insn (operands[3],
                      function_symbol (TARGET_FPU_ANY
                                       ? \"__sdivsi3_i4\"
                                       : \"__sdivsi3\"));

      if (TARGET_SHMEDIA)
        last = gen_divsi3_i1_media (operands[0],
                                    Pmode == DImode
                                    ? operands[3]
                                    : gen_rtx_SUBREG (DImode, operands[3],
                                                      0));
      else if (TARGET_FPU_ANY)
        last = gen_divsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_divsi3_i1 (operands[0], operands[3]);
    }
  else
    {
      emit_move_insn (operands[3], function_symbol (\"__sdivsi3\"));
      last = gen_divsi3_i1 (operands[0], operands[3]);
    }
  first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
  last = emit_insn (last);
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  DONE;
}")
\f
;; -------------------------------------------------------------------------
;; Multiplication instructions
;; -------------------------------------------------------------------------

(define_insn "umulhisi3_i"
  [(set (reg:SI MACL_REG)
        (mult:SI (zero_extend:SI
                  (match_operand:HI 0 "arith_reg_operand" "r"))
                 (zero_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" "r"))))]
  "TARGET_SH1"
  "mulu.w       %1,%0"
  [(set_attr "type" "smpy")])

(define_insn "mulhisi3_i"
  [(set (reg:SI MACL_REG)
        (mult:SI (sign_extend:SI
                  (match_operand:HI 0 "arith_reg_operand" "r"))
                 (sign_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" "r"))))]
  "TARGET_SH1"
  "muls.w       %1,%0"
  [(set_attr "type" "smpy")])

(define_expand "mulhisi3"
  [(set (reg:SI MACL_REG)
        (mult:SI (sign_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" ""))
                 (sign_extend:SI
                  (match_operand:HI 2 "arith_reg_operand" ""))))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  rtx first, last;

  first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  /* expand_binop can't find a suitable code in umul_widen_optab to
     make a REG_EQUAL note from, so make one here.
     See also smulsi3_highpart.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_expr.  */
  REG_NOTES (last)
    = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
                         REG_NOTES (last));
  DONE;
}")

(define_expand "umulhisi3"
  [(set (reg:SI MACL_REG)
        (mult:SI (zero_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" ""))
                 (zero_extend:SI
                  (match_operand:HI 2 "arith_reg_operand" ""))))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  rtx first, last;

  first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  /* expand_binop can't find a suitable code in umul_widen_optab to
     make a REG_EQUAL note from, so make one here.
     See also smulsi3_highpart.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_expr.  */
  REG_NOTES (last)
    = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
                         REG_NOTES (last));
  DONE;
}")

;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
;; a call to a routine which clobbers known registers.

(define_insn ""
  [(set (match_operand:SI 1 "register_operand" "=z")
        (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI MACL_REG))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R3_REG))
   (clobber (reg:SI R2_REG))
   (clobber (reg:SI R1_REG))
   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
  "TARGET_SH1"
  "jsr  @%0%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "mulsi3_call"
  [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel[(set (match_operand:SI 0 "register_operand" "")
                  (mult:SI (reg:SI R4_REG)
                           (reg:SI R5_REG)))
             (clobber (reg:SI MACL_REG))
             (clobber (reg:SI T_REG))
             (clobber (reg:SI PR_REG))
             (clobber (reg:SI R3_REG))
             (clobber (reg:SI R2_REG))
             (clobber (reg:SI R1_REG))
             (use (match_operand:SI 3 "register_operand" ""))])]
  "TARGET_SH1"
  "")

(define_insn "mul_l"
  [(set (reg:SI MACL_REG)
        (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
                 (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "mul.l        %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "mulsi3"
  [(set (reg:SI MACL_REG)
        (mult:SI  (match_operand:SI 1 "arith_reg_operand" "")
                  (match_operand:SI 2 "arith_reg_operand" "")))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  rtx first, last;

  if (!TARGET_SH2)
    {
      /* The address must be set outside the libcall,
         since it goes into a pseudo.  */
      rtx sym = function_symbol (\"__mulsi3\");
      rtx addr = force_reg (SImode, sym);
      rtx insns = gen_mulsi3_call (operands[0], operands[1],
                                   operands[2], addr);
      first = insns;
      last = emit_insn (insns);
    }
  else
    {
      rtx macl = gen_rtx_REG (SImode, MACL_REG);

      first = emit_insn (gen_mul_l (operands[1], operands[2]));
      /* consec_sets_giv can only recognize the first insn that sets a
         giv as the giv insn.  So we must tag this also with a REG_EQUAL
         note.  */
      last = emit_insn (gen_movsi_i ((operands[0]), macl));
    }
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  DONE;
}")

(define_insn "mulsidi3_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (set (reg:SI MACL_REG)
        (mult:SI (match_dup 0)
                 (match_dup 1)))]
  "TARGET_SH2"
  "dmuls.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "mulsidi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
                 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  if (TARGET_SH2)
    {
       emit_insn (gen_mulsidi3_compact (operands[0], operands[1],
                                        operands[2]));
       DONE;
    }
}")

(define_insn "mulsidi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
                 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "muls.l       %1, %2, %0"
  [(set_attr "type" "dmpy_media")])

(define_insn "mulsidi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI
         (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
         (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "#")

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (mult:DI
         (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
         (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  [(const_int 0)]
  "
{
  rtx low_dst = gen_lowpart (SImode, operands[0]);
  rtx high_dst = gen_highpart (SImode, operands[0]);

  emit_insn (gen_mulsidi3_i (operands[1], operands[2]));

  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
  /* We need something to tag the possible REG_EQUAL notes on to.  */
  emit_move_insn (operands[0], operands[0]);
  DONE;
}")

(define_insn "umulsidi3_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (set (reg:SI MACL_REG)
        (mult:SI (match_dup 0)
                 (match_dup 1)))]
  "TARGET_SH2"
  "dmulu.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "umulsidi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
                 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  if (TARGET_SH2)
    {
       emit_insn (gen_umulsidi3_compact (operands[0], operands[1],
                                         operands[2]));
       DONE;
    }
}")

(define_insn "umulsidi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
                 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "mulu.l       %1, %2, %0"
  [(set_attr "type" "dmpy_media")])

(define_insn "umulsidi3_compact"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI
         (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
         (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "#")

(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
                 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  [(const_int 0)]
  "
{
  rtx low_dst = gen_lowpart (SImode, operands[0]);
  rtx high_dst = gen_highpart (SImode, operands[0]);

  emit_insn (gen_umulsidi3_i (operands[1], operands[2]));

  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
  /* We need something to tag the possible REG_EQUAL notes on to.  */
  emit_move_insn (operands[0], operands[0]);
  DONE;
}")

(define_insn "smulsi3_highpart_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "dmuls.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "smulsi3_highpart"
  [(parallel
    [(set (reg:SI MACH_REG)
          (truncate:SI
           (lshiftrt:DI
            (mult:DI
             (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
             (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
            (const_int 32))))
    (clobber (reg:SI MACL_REG))])
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACH_REG))]
  "TARGET_SH2"
  "
{
  rtx first, last;

  first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  /* expand_binop can't find a suitable code in mul_highpart_optab to
     make a REG_EQUAL note from, so make one here.
     See also {,u}mulhisi.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_mult_highpart.  */
  REG_NOTES (last)
    = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
                         REG_NOTES (last));
  DONE;
}")

(define_insn "umulsi3_highpart_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "dmulu.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "umulsi3_highpart"
  [(parallel
    [(set (reg:SI MACH_REG)
          (truncate:SI
           (lshiftrt:DI
            (mult:DI
             (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
             (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
            (const_int 32))))
    (clobber (reg:SI MACL_REG))])
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACH_REG))]
  "TARGET_SH2"
  "
{
  rtx first, last;

  first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
     invariant code motion can move it.  */
  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
  DONE;
}")
\f
;; -------------------------------------------------------------------------
;; Logical operations
;; -------------------------------------------------------------------------

(define_insn "*andsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
        (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "r,K08")))]
  "TARGET_SH1"
  "and  %2,%0"
  [(set_attr "type" "arith")])

;; If the constant is 255, then emit an extu.b instruction instead of an
;; and, since that will give better code.

(define_expand "andsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (and:SI (match_operand:SI 1 "arith_reg_operand" "")
                (match_operand:SI 2 "logical_operand" "")))]
  "TARGET_SH1"
  "
{
  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
    {
      emit_insn (gen_zero_extendqisi2 (operands[0],
                                       gen_lowpart (QImode, operands[1])));
      DONE;
    }
}")

(define_insn_and_split "anddi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
        (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
                (match_operand:DI 2 "and_operand" "r,I10,J16")))]
  "TARGET_SHMEDIA"
  "@
        and     %1, %2, %0
        andi    %1, %2, %0
        #"
  "reload_completed
   && ! logical_operand (operands[2], DImode)"
  [(const_int 0)]
  "
{
  if (INTVAL (operands[2]) == (unsigned) 0xffffffff)
    emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
  else
    emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
  DONE;
}"
  [(set_attr "type" "arith_media")])

(define_insn "andcdi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
                (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "andc %1,%2,%0"
  [(set_attr "type" "arith_media")])

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
        (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "r,K08")))]
  "TARGET_SH1"
  "or   %2,%0"
  [(set_attr "type" "arith")])

(define_insn "iordi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                (match_operand:DI 2 "logical_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        or      %1, %2, %0
        ori     %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
        (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "K08,r")))]
  "TARGET_SH1"
  "xor  %2,%0"
  [(set_attr "type" "arith")])

(define_insn "xordi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                (match_operand:DI 2 "shmedia_6bit_operand" "r,I06")))]
  "TARGET_SHMEDIA"
  "@
        xor     %1, %2, %0
        xori    %1, %2, %0"
  [(set_attr "type" "arith_media")])

;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
;; converts 2 * sign extend -> logical op into logical op -> sign extend
(define_split
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (sign_extend:DI (match_operator 4 "binary_logical_operator"
                          [(match_operand 1 "any_register_operand" "")
                           (match_operand 2 "any_register_operand" "")])))]
  "TARGET_SHMEDIA"
  [(set (match_dup 5) (match_dup 4))
   (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
"
{
  enum machine_mode inmode = GET_MODE (operands[1]);
  int offset = 0;

  if (GET_CODE (operands[0]) == SUBREG)
    {
      offset = SUBREG_BYTE (operands[0]);
      operands[0] = SUBREG_REG (operands[0]);
    }
  if (GET_CODE (operands[0]) != REG)
    abort ();
  if (! TARGET_LITTLE_ENDIAN)
    offset += 8 - GET_MODE_SIZE (inmode);
  operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
}")
\f
;; -------------------------------------------------------------------------
;; Shifts and rotates
;; -------------------------------------------------------------------------

(define_expand "rotldi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
                   (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")

(define_insn "rotldi3_mextr"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
                   (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "*
{
  static char templ[16];

  sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
           8 - (int) (INTVAL (operands[2]) >> 3));
  return templ;
}"
  [(set_attr "type" "arith_media")])

(define_expand "rotrdi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
                     (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")

(define_insn "rotrdi3_mextr"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
                     (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "*
{
  static char templ[16];

  sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\", (int) INTVAL (operands[2]) >> 3);
  return templ;
}"
  [(set_attr "type" "arith_media")])

(define_insn "rotlsi3_1"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
                   (const_int 1)))
   (set (reg:SI T_REG)
        (lshiftrt:SI (match_dup 1) (const_int 31)))]
  "TARGET_SH1"
  "rotl %0"
  [(set_attr "type" "arith")])

(define_insn "rotlsi3_31"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
                   (const_int 31)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "rotr %0"
  [(set_attr "type" "arith")])

(define_insn "rotlsi3_16"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
                   (const_int 16)))]
  "TARGET_SH1"
  "swap.w       %1,%0"
  [(set_attr "type" "arith")])

(define_expand "rotlsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
                   (match_operand:SI 2 "immediate_operand" "")))]
  "TARGET_SH1"
  "
{
  static const char rot_tab[] = {
    000, 000, 000, 000, 000, 000, 010, 001,
    001, 001, 011, 013, 003, 003, 003, 003,
    003, 003, 003, 003, 003, 013, 012, 002,
    002, 002, 010, 000, 000, 000, 000, 000,
  };

  int count, choice;

  if (GET_CODE (operands[2]) != CONST_INT)
    FAIL;
  count = INTVAL (operands[2]);
  choice = rot_tab[count];
  if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
    FAIL;
  choice &= 7;
  switch (choice)
    {
    case 0:
      emit_move_insn (operands[0], operands[1]);
      count -= (count & 16) * 2;
      break;
    case 3:
     emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
     count -= 16;
     break;
    case 1:
    case 2:
      {
        rtx parts[2];
        parts[0] = gen_reg_rtx (SImode);
        parts[1] = gen_reg_rtx (SImode);
        emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
        emit_move_insn (parts[choice-1], operands[1]);
        emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
        emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
        emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
        count = (count & ~16) - 8;
      }
    }

  for (; count > 0; count--)
    emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
  for (; count < 0; count++)
    emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));

  DONE;
}")

(define_insn "*rotlhi3_8"
  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
        (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
                   (const_int 8)))]
  "TARGET_SH1"
  "swap.b       %1,%0"
  [(set_attr "type" "arith")])

(define_expand "rotlhi3"
  [(set (match_operand:HI 0 "arith_reg_operand" "")
        (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
                   (match_operand:HI 2 "immediate_operand" "")))]
  "TARGET_SH1"
  "
{
  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
    FAIL;
}")

;;
;; shift left

;; This pattern is used by init_expmed for computing the costs of shift
;; insns.

(define_insn_and_split "ashlsi3_std"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
        (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
                   (match_operand:SI 2 "nonmemory_operand" "r,M,P27,?ri")))
   (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
  "TARGET_SH3
   || (TARGET_SH1 && GET_CODE (operands[2]) == CONST_INT
       && CONST_OK_FOR_P27 (INTVAL (operands[2])))"
  "@
   shld %2,%0
   add  %0,%0
   shll%O2      %0
   #"
  "TARGET_SH3
   && reload_completed
   && GET_CODE (operands[2]) == CONST_INT
   && ! CONST_OK_FOR_P27 (INTVAL (operands[2]))"
  [(set (match_dup 3) (match_dup 2))
   (parallel
    [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
     (clobber (match_dup 4))])]
  "operands[4] = gen_rtx_SCRATCH (SImode);"
  [(set_attr "length" "*,*,*,4")
   (set_attr "type" "dyn_shift,arith,arith,arith")])

(define_insn "ashlhi3_k"
  [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
        (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
                   (match_operand:HI 2 "const_int_operand" "M,P27")))]
  "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))"
  "@
        add     %0,%0
        shll%O2 %0"
  [(set_attr "type" "arith")])

(define_insn "ashlsi3_n"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
                   (match_operand:SI 2 "const_int_operand" "n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
               (const_string "2")
               (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
               (const_string "6")]
              (const_string "8")))
   (set_attr "type" "arith")])

(define_split
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
                   (match_operand:SI 2 "const_int_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(use (reg:SI R0_REG))]
  "
{
  gen_shifty_op (ASHIFT, operands);
  DONE;
}")

(define_insn "ashlsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
                   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shlld.l %1, %2, %0
        shlli.l %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "ashlsi3"
  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
                   (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
                              (match_operand:SI 2 "nonmemory_operand" "")))
              (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (GET_CODE (operands[2]) == CONST_INT
      && sh_dynamicalize_shift_p (operands[2]))
    operands[2] = force_reg (SImode, operands[2]);
  if (TARGET_SH3)
    {
      emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
    FAIL;
}")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
        (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
                   (match_operand:HI 2 "const_int_operand" "n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
               (const_string "2")
               (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
               (const_string "4")]
              (const_string "6")))
   (set_attr "type" "arith")])

(define_split
  [(set (match_operand:HI 0 "arith_reg_operand" "")
        (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
                   (match_operand:HI 2 "const_int_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(use (reg:SI R0_REG))]
  "
{
  gen_shifty_hi_op (ASHIFT, operands);
  DONE;
}")

;
; arithmetic shift right
;

(define_insn "ashrsi3_k"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (match_operand:SI 2 "const_int_operand" "M")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && INTVAL (operands[2]) == 1"
  "shar %0"
  [(set_attr "type" "arith")])

;; We can't do HImode right shifts correctly unless we start out with an
;; explicit zero / sign extension; doing that would result in worse overall
;; code, so just let the machine independent code widen the mode.
;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .


;; ??? This should be a define expand.

(define_insn "ashrsi2_16"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
                     (const_int 16)))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "4")])

(define_split
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
                     (const_int 16)))]
  "TARGET_SH1"
  [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
   (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
  "operands[2] = gen_lowpart (HImode, operands[0]);")

;; ??? This should be a define expand.

(define_insn "ashrsi2_31"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (const_int 31)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "4")])

(define_split
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
                     (const_int 31)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  [(const_int 0)]
  "
{
  emit_insn (gen_ashlsi_c (operands[0], operands[1]));
  emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
  DONE;
}")

(define_insn "ashlsi_c"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
   (set (reg:SI T_REG)
        (lt:SI (match_dup 1) (const_int 0)))]
  "TARGET_SH1"
  "shll %0"
  [(set_attr "type" "arith")])

(define_insn "ashrsi3_d"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH3"
  "shad %2,%0"
  [(set_attr "type" "dyn_shift")])

(define_insn "ashrsi3_n"
  [(set (reg:SI R4_REG)
        (ashiftrt:SI (reg:SI R4_REG)
                     (match_operand:SI 0 "const_int_operand" "i")))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "ashrsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
                     (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shard.l %1, %2, %0
        shari.l %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "ashrsi3"
  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
                   (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
                                (match_operand:SI 2 "nonmemory_operand" "")))
              (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (expand_ashiftrt (operands))
    DONE;
  else
    FAIL;
}")

;; logical shift right

(define_insn "lshrsi3_d"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH3"
  "shld %2,%0"
  [(set_attr "type" "dyn_shift")])

;;  Only the single bit shift clobbers the T bit.

(define_insn "lshrsi3_m"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (match_operand:SI 2 "const_int_operand" "M")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && CONST_OK_FOR_M (INTVAL (operands[2]))"
  "shlr %0"
  [(set_attr "type" "arith")])

(define_insn "lshrsi3_k"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (match_operand:SI 2 "const_int_operand" "P27")))]
  "TARGET_SH1 && CONST_OK_FOR_P27 (INTVAL (operands[2]))
   && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
  "shlr%O2      %0"
  [(set_attr "type" "arith")])

(define_insn "lshrsi3_n"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                     (match_operand:SI 2 "const_int_operand" "n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
               (const_string "2")
               (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
               (const_string "6")]
              (const_string "8")))
   (set_attr "type" "arith")])

(define_split
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
                     (match_operand:SI 2 "const_int_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(use (reg:SI R0_REG))]
  "
{
  gen_shifty_op (LSHIFTRT, operands);
  DONE;
}")

(define_insn "lshrsi3_media"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
                     (match_operand:SI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shlrd.l %1, %2, %0
        shlri.l %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "lshrsi3"
  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
                   (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
                                (match_operand:SI 2 "nonmemory_operand" "")))
              (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (GET_CODE (operands[2]) == CONST_INT
      && sh_dynamicalize_shift_p (operands[2]))
    operands[2] = force_reg (SImode, operands[2]);
  if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
    {
      rtx count = copy_to_mode_reg (SImode, operands[2]);
      emit_insn (gen_negsi2 (count, count));
      emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
      DONE;
    }
  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
    FAIL;
}")

;; ??? This should be a define expand.

(define_insn "ashldi3_k"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
                   (const_int 1)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "shll %R0\;rotcl      %S0"
  [(set_attr "length" "4")
   (set_attr "type" "arith")])

(define_insn "ashldi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
                   (match_operand:DI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shlld   %1, %2, %0
        shlli   %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "ashldi3"
  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
                   (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
                              (match_operand:DI 2 "immediate_operand" "")))
              (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (GET_CODE (operands[2]) != CONST_INT
      || INTVAL (operands[2]) != 1)
    FAIL;
}")

;; ??? This should be a define expand.

(define_insn "lshrdi3_k"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
                     (const_int 1)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "shlr %S0\;rotcr      %R0"
  [(set_attr "length" "4")
   (set_attr "type" "arith")])

(define_insn "lshrdi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
                     (match_operand:DI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shlrd   %1, %2, %0
        shlri   %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "lshrdi3"
  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
                   (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
                               (match_operand:DI 2 "immediate_operand" "")))
             (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (GET_CODE (operands[2]) != CONST_INT
      || INTVAL (operands[2]) != 1)
    FAIL;
}")

;; ??? This should be a define expand.

(define_insn "ashrdi3_k"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
                     (const_int 1)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "shar %S0\;rotcr      %R0"
  [(set_attr "length" "4")
   (set_attr "type" "arith")])

(define_insn "ashrdi3_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r,r")
        (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
                     (match_operand:DI 2 "nonmemory_operand" "r,n")))]
  "TARGET_SHMEDIA"
  "@
        shard   %1, %2, %0
        shari   %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_expand "ashrdi3"
  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
                   (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
                                (match_operand:DI 2 "immediate_operand" "")))
              (clobber (reg:SI T_REG))])]
  ""
  "
{
  if (TARGET_SHMEDIA)
    {
      emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  if (GET_CODE (operands[2]) != CONST_INT
      || INTVAL (operands[2]) != 1)
    FAIL;
}")

;; combined left/right shift

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
                           (match_operand:SI 2 "const_int_operand" ""))
                (match_operand:SI 3 "const_int_operand" "")))]
  "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
  [(use (reg:SI R0_REG))]
  "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
   DONE;")

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
                           (match_operand:SI 2 "const_int_operand" ""))
                (match_operand:SI 3 "const_int_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
  [(use (reg:SI R0_REG))]
  "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
   DONE;")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
                           (match_operand:SI 2 "const_int_operand" "n"))
                (match_operand:SI 3 "const_int_operand" "n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
 "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
               (const_string "6")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
               (const_string "8")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
               (const_string "10")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
               (const_string "12")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
               (const_string "14")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
               (const_string "16")]
              (const_string "18")))
   (set_attr "type" "arith")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=z")
        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
                           (match_operand:SI 2 "const_int_operand" "n"))
                (match_operand:SI 3 "const_int_operand" "n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
 "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
               (const_string "6")
               (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
               (const_string "8")]
              (const_string "10")))
   (set_attr "type" "arith")])

;; shift left / and combination with a scratch register: The combine pass
;; does not accept the individual instructions, even though they are
;; cheap.  But it needs a precise description so that it is usable after
;; reload.
(define_insn "and_shl_scratch"
  [(set (match_operand:SI 0 "register_operand" "=r,&r")
        (lshiftrt:SI
         (ashift:SI
          (and:SI
           (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
                        (match_operand:SI 2 "const_int_operand" "N,n"))
           (match_operand:SI 3 "" "0,r"))
          (match_operand:SI 4 "const_int_operand" "n,n"))
         (match_operand:SI 5 "const_int_operand" "n,n")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
               (const_string "6")
               (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
               (const_string "8")
               (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
               (const_string "10")]
              (const_string "12")))
   (set_attr "type" "arith")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (lshiftrt:SI
         (ashift:SI
          (and:SI
           (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
                        (match_operand:SI 2 "const_int_operand" ""))
           (match_operand:SI 3 "register_operand" ""))
          (match_operand:SI 4 "const_int_operand" ""))
         (match_operand:SI 5 "const_int_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  [(use (reg:SI R0_REG))]
  "
{
  rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];

  if (INTVAL (operands[2]))
    {
      gen_shifty_op (LSHIFTRT, operands);
    }
  emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
  operands[2] = operands[4];
  gen_shifty_op (ASHIFT, operands);
  if (INTVAL (operands[5]))
    {
      operands[2] = operands[5];
      gen_shifty_op (LSHIFTRT, operands);
    }
  DONE;
}")

;; signed left/right shift combination.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (sign_extract:SI
         (ashift:SI (match_operand:SI 1 "register_operand" "")
                    (match_operand:SI 2 "const_int_operand" ""))
         (match_operand:SI 3 "const_int_operand" "")
         (const_int 0)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  [(use (reg:SI R0_REG))]
  "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
   DONE;")

(define_insn "shl_sext_ext"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (sign_extract:SI
         (ashift:SI (match_operand:SI 1 "register_operand" "0")
                    (match_operand:SI 2 "const_int_operand" "n"))
         (match_operand:SI 3 "const_int_operand" "n")
         (const_int 0)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
               (const_string "2")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
               (const_string "4")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
               (const_string "6")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
               (const_string "8")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
               (const_string "10")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
               (const_string "12")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
               (const_string "14")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
               (const_string "16")]
              (const_string "18")))
    (set_attr "type" "arith")])

(define_insn "shl_sext_sub"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (sign_extract:SI
         (ashift:SI (match_operand:SI 1 "register_operand" "0")
                    (match_operand:SI 2 "const_int_operand" "n"))
         (match_operand:SI 3 "const_int_operand" "n")
         (const_int 0)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
  "#"
  [(set (attr "length")
        (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
               (const_string "6")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
               (const_string "8")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
               (const_string "10")
               (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
               (const_string "12")]
              (const_string "14")))
    (set_attr "type" "arith")])

;; These patterns are found in expansions of DImode shifts by 16, and
;; allow the xtrct instruction to be generated from C source.

(define_insn "xtrct_left"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
                           (const_int 16))
                (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
                             (const_int 16))))]
  "TARGET_SH1"
  "xtrct        %1,%0"
  [(set_attr "type" "arith")])

(define_insn "xtrct_right"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
                             (const_int 16))
                (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
                           (const_int 16))))]
  "TARGET_SH1"
  "xtrct        %2,%0"
  [(set_attr "type" "arith")])

;; -------------------------------------------------------------------------
;; Unary arithmetic
;; -------------------------------------------------------------------------

(define_insn "negc"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (neg:SI (plus:SI (reg:SI T_REG)
                         (match_operand:SI 1 "arith_reg_operand" "r"))))
   (set (reg:SI T_REG)
        (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
               (const_int 0)))]
  "TARGET_SH1"
  "negc %1,%0"
  [(set_attr "type" "arith")])

(define_insn "*negdi_media"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub  r63, %1, %0"
  [(set_attr "type" "arith_media")])

(define_expand "negdi2"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
      int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);

      rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
      rtx high_src = operand_subword (operands[1], high_word, 0, DImode);

      rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
      rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);

      emit_insn (gen_clrt ());
      emit_insn (gen_negc (low_dst, low_src));
      emit_insn (gen_negc (high_dst, high_src));
      DONE;
    }
}")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "neg  %1,%0"
  [(set_attr "type" "arith")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "not  %1,%0"
  [(set_attr "type" "arith")])

(define_expand "one_cmpldi2"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
                (const_int -1)))]
  "TARGET_SHMEDIA" "")
\f
;; -------------------------------------------------------------------------
;; Zero extension instructions
;; -------------------------------------------------------------------------

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "addz.l       %1, r63, %0"
  [(set_attr "type" "arith_media")])

(define_insn "zero_extendhidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.uw        %m1, %0"
  [(set_attr "type" "*,load_media")])

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
   (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
  "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

;; ??? when a truncated input to a zero_extend is reloaded, reload will
;; reload the entire truncate expression.
(define_insn_and_split "*loaddi_trunc"
  [(set (match_operand 0 "int_gpr_dest" "=r")
        (truncate (match_operand:DI 1 "memory_operand" "m")))]
  "TARGET_SHMEDIA && reload_completed"
  "#"
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (match_dup 1))]
  "operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));")

(define_insn "zero_extendqidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        andi    %1, 255, %0
        ld%M1.ub        %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "")))]
  ""
  "
{
  if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], HImode))
    operands[1] = copy_to_mode_reg (HImode, operands[1]);
}")

(define_insn "*zero_extendhisi2_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "extu.w       %1,%0"
  [(set_attr "type" "arith")])

(define_insn "*zero_extendhisi2_media"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.uw        %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
  "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

(define_expand "zero_extendqisi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "")))]
  ""
  "
{
  if (! TARGET_SHMEDIA && ! arith_reg_operand (operands[1], QImode))
    operands[1] = copy_to_mode_reg (QImode, operands[1]);
}")

(define_insn "*zero_extendqisi2_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
        (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "extu.b       %1,%0"
  [(set_attr "type" "arith")])

(define_insn "*zero_extendqisi2_media"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        andi    %1, 255, %0
        ld%M1.ub        %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
        (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "extu.b       %1,%0"
  [(set_attr "type" "arith")])

;; -------------------------------------------------------------------------
;; Sign extension instructions
;; -------------------------------------------------------------------------

;; ??? This should be a define expand.
;; ??? Or perhaps it should be dropped?

;; convert_move generates good code for SH[1-4].
(define_insn "extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, r63, %0
        ld%M1.l %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_insn "extendhidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.w %m1, %0"
  [(set_attr "type" "*,load_media")])

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
   (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
  "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

(define_insn "extendqidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
        (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.b %m1, %0"
  [(set_attr "type" "*,load_media")])

(define_split
  [(set (match_operand:DI 0 "register_operand" "")
        (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
   (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
  "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

(define_expand "extendhisi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
  ""
  "")

(define_insn "*extendhisi2_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
  "TARGET_SH1"
  "@
        exts.w  %1,%0
        mov.w   %1,%0"
  [(set_attr "type" "arith,load")])

(define_insn "*extendhisi2_media"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.w %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
  "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

(define_expand "extendqisi2"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
  ""
  "")

(define_insn "*extendqisi2_compact"
  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
        (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
  "TARGET_SH1"
  "@
        exts.b  %1,%0
        mov.b   %1,%0"
  [(set_attr "type" "arith,load")])

(define_insn "*extendqisi2_media"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
        (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
  "TARGET_SHMEDIA"
  "@
        #
        ld%M1.b %m1, %0"
  [(set_attr "type" "arith_media,load_media")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
        (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
  "TARGET_SHMEDIA && reload_completed"
  [(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
   "
{
  if (GET_CODE (operands[1]) == TRUNCATE)
    operands[1] = XEXP (operands[1], 0);
}")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
        (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
  "TARGET_SH1"
  "@
        exts.b  %1,%0
        mov.b   %1,%0"
  [(set_attr "type" "arith,load")])

/* It would seem useful to combine the truncXi patterns into the movXi
   patterns, but unary operators are ignored when matching constraints,
   so we need separate patterns.  */
(define_insn "truncdisi2"
  [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
        (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, r63, %0
        st%M0.l %m0, %1
        fst%M0.s        %m0, %T1
        fmov.ls %1, %0
        fmov.sl %T1, %0
        fmov.s  %T1, %0"
  [(set_attr "type"   "arith_media,store_media,fstore_media,fload_media,fpconv_media,fmove_media")])


(define_insn "truncdihi2"
  [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
        (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
  "TARGET_SHMEDIA"
  "@
        shlli\\t%1,48,%0\;shlri\\t%0,48,%0
        st%M0.w %m0, %1"
  [(set_attr "type"   "arith_media,store_media")
   (set_attr "length" "8,4")])

; N.B. This should agree with LOAD_EXTEND_OP and movqi.
; Because we use zero extension, we can't provide signed QImode compares
; using a simple compare or conditional banch insn.
(define_insn "truncdiqi2"
  [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
        (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
  "TARGET_SHMEDIA"
  "@
        andi    %1, 255, %0
        st%M0.b %m0, %1"
  [(set_attr "type"   "arith_media,store")])

;; -------------------------------------------------------------------------
;; Move instructions
;; -------------------------------------------------------------------------

;; define push and pop so it is easy for sh.c
;; We can't use push and pop on SHcompact because the stack must always
;; be 8-byte aligned.

(define_expand "push"
  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
        (match_operand:SI 0 "register_operand" "r,l,x"))]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_expand "pop"
  [(set (match_operand:SI 0 "register_operand" "=r,l,x")
        (mem:SI (post_inc:SI (reg:SI SP_REG))))]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_expand "push_e"
  [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
                   (match_operand:SF 0 "" ""))
              (use (reg:PSI FPSCR_REG))
              (clobber (scratch:SI))])]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_insn "push_fpul"
  [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
  "TARGET_SH2E && ! TARGET_SH5"
  "sts.l        fpul,@-r15"
  [(set_attr "type" "store")
   (set_attr "late_fp_use" "yes")
   (set_attr "hit_stack" "yes")])

;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
;; so use that.
(define_expand "push_4"
  [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
                   (match_operand:DF 0 "" ""))
              (use (reg:PSI FPSCR_REG))
              (clobber (scratch:SI))])]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_expand "pop_e"
  [(parallel [(set (match_operand:SF 0 "" "")
              (mem:SF (post_inc:SI (reg:SI SP_REG))))
              (use (reg:PSI FPSCR_REG))
              (clobber (scratch:SI))])]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_insn "pop_fpul"
  [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
  "TARGET_SH2E && ! TARGET_SH5"
  "lds.l        @r15+,fpul"
  [(set_attr "type" "load")
   (set_attr "hit_stack" "yes")])

(define_expand "pop_4"
  [(parallel [(set (match_operand:DF 0 "" "")
                   (mem:DF (post_inc:SI (reg:SI SP_REG))))
              (use (reg:PSI FPSCR_REG))
              (clobber (scratch:SI))])]
  "TARGET_SH1 && ! TARGET_SH5"
  "")

(define_expand "push_fpscr"
  [(const_int 0)]
  "TARGET_SH2E"
  "
{
  rtx insn = emit_insn (gen_fpu_switch (gen_rtx_MEM (PSImode,
                                                 gen_rtx_PRE_DEC (Pmode,
                                                          stack_pointer_rtx)),
                                        get_fpscr_rtx ()));
  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
  DONE;
}")

(define_expand "pop_fpscr"
  [(const_int 0)]
  "TARGET_SH2E"
  "
{
  rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
                                        gen_rtx_MEM (PSImode,
                                                 gen_rtx_POST_INC (Pmode,
                                                          stack_pointer_rtx))));
  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, NULL_RTX);
  DONE;
}")

;; These two patterns can happen as the result of optimization, when
;; comparisons get simplified to a move of zero or 1 into the T reg.
;; They don't disappear completely, because the T reg is a fixed hard reg.

(define_insn "clrt"
  [(set (reg:SI T_REG) (const_int 0))]
  "TARGET_SH1"
  "clrt")

(define_insn "sett"
  [(set (reg:SI T_REG) (const_int 1))]
  "TARGET_SH1"
  "sett")

;; t/r must come after r/r, lest reload will try to reload stuff like
;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
(define_insn "movsi_i"
  [(set (match_operand:SI 0 "general_movdst_operand"
            "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
        (match_operand:SI 1 "general_movsrc_operand"
         "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
  "TARGET_SH1
   && ! TARGET_SH2E
   && (register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "@
        mov.l   %1,%0
        mov     %1,%0
        cmp/pl  %1
        mov.l   %1,%0
        sts     %1,%0
        sts     %1,%0
        movt    %0
        mov.l   %1,%0
        sts.l   %1,%0
        sts.l   %1,%0
        lds     %1,%0
        lds     %1,%0
        lds.l   %1,%0
        lds.l   %1,%0
        fake    %1,%0"
  [(set_attr "type" "pcload_si,move,mt_group,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
   (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])

;; t/r must come after r/r, lest reload will try to reload stuff like
;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
;; ??? This allows moves from macl to fpul to be recognized, but these moves
;; will require a reload.
;; ??? We can't include f/f because we need the proper FPSCR setting when
;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie"
  [(set (match_operand:SI 0 "general_movdst_operand"
            "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
        (match_operand:SI 1 "general_movsrc_operand"
         "Q,rI08,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
  "TARGET_SH2E
   && (register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "@
        mov.l   %1,%0
        mov     %1,%0
        cmp/pl  %1
        mov.l