* doc/invoke.texi: Document -mbitops for SH.

[pf3gnuchains/gcc-fork.git] / gcc / config / sh / sh.md

;;- Machine description for Renesas / SuperH SH.
;;  Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
;;  2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
;;  Contributed by Steve Chamberlain (sac@cygnus.com).
;;  Improved by Jim Wilson (wilson@cygnus.com).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.


;; ??? Should prepend a * to all pattern names which are not used.
;; This will make the compiler smaller, and rebuilds after changes faster.

;; ??? Should be enhanced to include support for many more GNU superoptimizer
;; sequences.  Especially the sequences for arithmetic right shifts.

;; ??? Should check all DImode patterns for consistency and usefulness.

;; ??? The MAC.W and MAC.L instructions are not supported.  There is no
;; way to generate them.

;; ??? The cmp/str instruction is not supported.  Perhaps it can be used
;; for a str* inline function.

;; BSR is not generated by the compiler proper, but when relaxing, it
;; generates .uses pseudo-ops that allow linker relaxation to create
;; BSR.  This is actually implemented in bfd/{coff,elf32}-sh.c

;; Special constraints for SH machine description:
;;
;;    t -- T
;;    x -- mac
;;    l -- pr
;;    z -- r0
;;
;; Special formats used for outputting SH instructions:
;;
;;   %.  --  print a .s if insn needs delay slot
;;   %@  --  print rte/rts if is/isn't an interrupt function
;;   %#  --  output a nop if there is nothing to put in the delay slot
;;   %O  --  print a constant without the #
;;   %R  --  print the lsw reg of a double
;;   %S  --  print the msw reg of a double
;;   %T  --  print next word of a double REG or MEM
;;
;; Special predicates:
;;
;;  arith_operand          -- operand is valid source for arithmetic op
;;  arith_reg_operand      -- operand is valid register for arithmetic op
;;  general_movdst_operand -- operand is valid move destination
;;  general_movsrc_operand -- operand is valid move source
;;  logical_operand        -- operand is valid source for logical op

;; -------------------------------------------------------------------------
;; Constants
;; -------------------------------------------------------------------------

(define_constants [
  (AP_REG       145)
  (PR_REG       146)
  (T_REG        147)
  (GBR_REG      144)
  (MACH_REG     148)
  (MACL_REG     149)
  (FPUL_REG     150)
  (RAP_REG      152)

  (FPSCR_REG    151)

  (PIC_REG      12)
  (FP_REG       14)
  (SP_REG       15)

  (PR_MEDIA_REG 18)
  (T_MEDIA_REG  19)

  (R0_REG       0)
  (R1_REG       1)
  (R2_REG       2)
  (R3_REG       3)
  (R4_REG       4)
  (R5_REG       5)
  (R6_REG       6)
  (R7_REG       7)
  (R8_REG       8)
  (R9_REG       9)
  (R10_REG      10)
  (R20_REG      20)
  (R21_REG      21)
  (R22_REG      22)
  (R23_REG      23)

  (DR0_REG      64)
  (DR2_REG      66)
  (DR4_REG      68)
  (FR23_REG     87)

  (TR0_REG      128)
  (TR1_REG      129)
  (TR2_REG      130)

  (XD0_REG      136)

  ;; These are used with unspec.
  (UNSPEC_COMPACT_ARGS  0)
  (UNSPEC_MOVA          1)
  (UNSPEC_CASESI        2)
  (UNSPEC_DATALABEL     3)
  (UNSPEC_BBR           4)
  (UNSPEC_SFUNC         5)
  (UNSPEC_PIC           6)
  (UNSPEC_GOT           7)
  (UNSPEC_GOTOFF        8)
  (UNSPEC_PLT           9)
  (UNSPEC_CALLER        10)
  (UNSPEC_GOTPLT        11)
  (UNSPEC_ICACHE        12)
  (UNSPEC_INIT_TRAMP    13)
  (UNSPEC_FCOSA         14)
  (UNSPEC_FSRRA         15)
  (UNSPEC_FSINA         16)
  (UNSPEC_NSB           17)
  (UNSPEC_ALLOCO        18)
  (UNSPEC_TLSGD         20)
  (UNSPEC_TLSLDM        21)
  (UNSPEC_TLSIE         22)
  (UNSPEC_DTPOFF        23)
  (UNSPEC_GOTTPOFF      24)
  (UNSPEC_TPOFF         25)
  (UNSPEC_RA            26)
  (UNSPEC_DIV_INV_M0    30)
  (UNSPEC_DIV_INV_M1    31)
  (UNSPEC_DIV_INV_M2    32)
  (UNSPEC_DIV_INV_M3    33)
  (UNSPEC_DIV_INV20     34)
  (UNSPEC_DIV_INV_TABLE 37)
  (UNSPEC_ASHIFTRT      35)
  (UNSPEC_THUNK         36)
  (UNSPEC_SP_SET        40)
  (UNSPEC_SP_TEST       41)
  (UNSPEC_MOVUA         42)

  ;; These are used with unspec_volatile.
  (UNSPECV_BLOCKAGE     0)
  (UNSPECV_ALIGN        1)
  (UNSPECV_CONST2       2)
  (UNSPECV_CONST4       4)
  (UNSPECV_CONST8       6)
  (UNSPECV_WINDOW_END   10)
  (UNSPECV_CONST_END    11)
  (UNSPECV_EH_RETURN    12)
])

;; -------------------------------------------------------------------------
;; Attributes
;; -------------------------------------------------------------------------

;; Target CPU.

(define_attr "cpu"
 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
  (const (symbol_ref "sh_cpu_attr")))

(define_attr "endian" "big,little"
 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
                      (const_string "little") (const_string "big"))))

;; Indicate if the default fpu mode is single precision.
(define_attr "fpu_single" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
                         (const_string "yes") (const_string "no"))))

(define_attr "fmovd" "yes,no"
  (const (if_then_else (symbol_ref "TARGET_FMOVD")
                       (const_string "yes") (const_string "no"))))
;; pipeline model
(define_attr "pipe_model" "sh1,sh4,sh5media"
  (const
   (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
          (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
         (const_string "sh1"))))

;; cbranch      conditional branch instructions
;; jump         unconditional jumps
;; arith        ordinary arithmetic
;; arith3       a compound insn that behaves similarly to a sequence of
;;              three insns of type arith
;; arith3b      like above, but might end with a redirected branch
;; load         from memory
;; load_si      Likewise, SImode variant for general register.
;; fload        Likewise, but load to fp register.
;; store        to memory
;; fstore       floating point register to memory
;; move         general purpose register to register
;; movi8        8-bit immediate to general purpose register
;; mt_group     other sh4 mt instructions
;; fmove        register to register, floating point
;; smpy         word precision integer multiply
;; dmpy         longword or doublelongword precision integer multiply
;; return       rts
;; pload        load of pr reg, which can't be put into delay slot of rts
;; prset        copy register to pr reg, ditto
;; pstore       store of pr reg, which can't be put into delay slot of jsr
;; prget        copy pr to register, ditto
;; pcload       pc relative load of constant value
;; pcfload      Likewise, but load to fp register.
;; pcload_si    Likewise, SImode variant for general register.
;; rte          return from exception
;; sfunc        special function call with known used registers
;; call         function call
;; fp           floating point
;; fpscr_toggle toggle a bit in the fpscr
;; fdiv         floating point divide (or square root)
;; gp_fpul      move from general purpose register to fpul
;; fpul_gp      move from fpul to general purpose register
;; mac_gp       move from mac[lh] to general purpose register
;; gp_mac       move from general purpose register to mac[lh]
;; mac_mem      move from mac[lh] to memory
;; mem_mac      move from memory to mac[lh]
;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
;; ftrc_s       fix_truncsfsi2_i4
;; dfdiv        double precision floating point divide (or square root)
;; cwb          ic_invalidate_line_i
;; movua        SH4a unaligned load
;; fsrra        square root reciprocal approximate
;; fsca         sine and cosine approximate
;; tls_load     load TLS related address
;; arith_media  SHmedia arithmetic, logical, and shift instructions
;; cbranch_media SHmedia conditional branch instructions
;; cmp_media    SHmedia compare instructions
;; dfdiv_media  SHmedia double precision divide and square root
;; dfmul_media  SHmedia double precision multiply instruction
;; dfparith_media SHmedia double precision floating point arithmetic
;; dfpconv_media SHmedia double precision floating point conversions
;; dmpy_media   SHmedia longword multiply
;; fcmp_media   SHmedia floating point compare instructions
;; fdiv_media   SHmedia single precision divide and square root
;; fload_media  SHmedia floating point register load instructions
;; fmove_media  SHmedia floating point register moves (inc. fabs and fneg)
;; fparith_media SHmedia single precision floating point arithmetic
;; fpconv_media SHmedia single precision floating point conversions
;; fstore_media SHmedia floating point register store instructions
;; gettr_media  SHmedia gettr instruction
;; invalidate_line_media SHmedia invalidate_line sequence
;; jump_media   SHmedia unconditional branch instructions
;; load_media   SHmedia general register load instructions
;; pt_media     SHmedia pt instruction (expanded by assembler)
;; ptabs_media  SHmedia ptabs instruction
;; store_media  SHmedia general register store instructions
;; mcmp_media   SHmedia multimedia compare, absolute, saturating ops
;; mac_media    SHmedia mac-style fixed point operations
;; d2mpy_media  SHmedia: two 32-bit integer multiplies
;; atrans_media SHmedia approximate transcendental functions
;; ustore_media SHmedia unaligned stores
;; nil          no-op move, will be deleted.

(define_attr "type"
 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
  (const_string "other"))

;; We define a new attribute namely "insn_class".We use
;; this for the DFA based pipeline description.
;;
;; mt_group      SH4 "mt" group instructions.
;;
;; ex_group      SH4 "ex" group instructions.
;;
;; ls_group      SH4 "ls" group instructions.
;;

(define_attr "insn_class"
  "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
  (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
         (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
         (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
         (eq_attr "type" "cbranch,jump") (const_string "br_group")
         (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
           (const_string "fe_group")
         (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,gp_mac,mac_mem,mem_mac") (const_string "co_group")]
        (const_string "none")))
;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
;; so these do not belong in an insn group, although they are modeled
;; with their own define_insn_reservations.

;; Indicate what precision must be selected in fpscr for this insn, if any.

(define_attr "fp_mode" "single,double,none" (const_string "none"))

;; Indicate if the fpu mode is set by this instruction
;; "unknown" must have the value as "none" in fp_mode, and means
;; that the instruction/abi has left the processor in an unknown
;; state.
;; "none" means that nothing has changed and no mode is set.
;; This attribute is only used for the Renesas ABI.
(define_attr "fp_set" "single,double,unknown,none" (const_string "none"))

; If a conditional branch destination is within -252..258 bytes away
; from the instruction it can be 2 bytes long.  Something in the
; range -4090..4100 bytes can be 6 bytes long.  All other conditional
; branches are initially assumed to be 16 bytes long.
; In machine_dependent_reorg, we split all branches that are longer than
; 2 bytes.

;; The maximum range used for SImode constant pool entries is 1018.  A final
;; instruction can add 8 bytes while only being 4 bytes in size, thus we
;; can have a total of 1022 bytes in the pool.  Add 4 bytes for a branch
;; instruction around the pool table, 2 bytes of alignment before the table,
;; and 30 bytes of alignment after the table.  That gives a maximum total
;; pool size of 1058 bytes.
;; Worst case code/pool content size ratio is 1:2 (using asms).
;; Thus, in the worst case, there is one instruction in front of a maximum
;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
;; code.  For the last n bytes of code, there are 2n + 36 bytes of pool.
;; If we have a forward branch, the initial table will be put after the
;; unconditional branch.
;;
;; ??? We could do much better by keeping track of the actual pcloads within
;; the branch range and in the pcload range in front of the branch range.

;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
;; inside an le.
(define_attr "short_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
         (const_string "yes")
         (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "med_branch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
              (const_int 1988))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
              (const_int 8186))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "med_cbranch_p" "no,yes"
  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
              (const_int 1986))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
               (const_int 8184))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "braf_branch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
              (const_int 20660))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
              (const_int 65530))
         (const_string "yes")
         ] (const_string "no")))

(define_attr "braf_cbranch_p" "no,yes"
  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
              (const_int 20658))
         (const_string "yes")
         (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
         (const_string "no")
         (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
              (const_int 65528))
         (const_string "yes")
         ] (const_string "no")))

; An unconditional jump in the range -4092..4098 can be 2 bytes long.
; For wider ranges, we need a combination of a code and a data part.
; If we can get a scratch register for a long range jump, the code
; part can be 4 bytes long; otherwise, it must be 8 bytes long.
; If the jump is in the range -32764..32770, the data part can be 2 bytes
; long; otherwise, it must be 6 bytes long.

; All other instructions are two bytes long by default.

;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
;; but getattrtab doesn't understand this.
(define_attr "length" ""
  (cond [(eq_attr "type" "cbranch")
         (cond [(eq_attr "short_cbranch_p" "yes")
                (const_int 2)
                (eq_attr "med_cbranch_p" "yes")
                (const_int 6)
                (eq_attr "braf_cbranch_p" "yes")
                (const_int 12)
;; ??? using pc is not computed transitively.
                (ne (match_dup 0) (match_dup 0))
                (const_int 14)
                (ne (symbol_ref ("flag_pic")) (const_int 0))
                (const_int 24)
                ] (const_int 16))
         (eq_attr "type" "jump")
         (cond [(eq_attr "med_branch_p" "yes")
                (const_int 2)
                (and (ne (symbol_ref "prev_nonnote_insn (insn)")
                         (const_int 0))
                     (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
                              (symbol_ref "INSN"))
                          (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
                              (symbol_ref "code_for_indirect_jump_scratch"))))
                (cond [(eq_attr "braf_branch_p" "yes")
                       (const_int 6)
                       (eq (symbol_ref "flag_pic") (const_int 0))
                       (const_int 10)
                       (ne (symbol_ref "TARGET_SH2") (const_int 0))
                       (const_int 10)] (const_int 18))
                (eq_attr "braf_branch_p" "yes")
                (const_int 10)
;; ??? using pc is not computed transitively.
                (ne (match_dup 0) (match_dup 0))
                (const_int 12)
                (ne (symbol_ref ("flag_pic")) (const_int 0))
                (const_int 22)
                ] (const_int 14))
         (eq_attr "type" "pt_media")
         (if_then_else (ne (symbol_ref "TARGET_SHMEDIA64") (const_int 0))
                       (const_int 20) (const_int 12))
         (and (eq_attr "type" "jump_media")
              (ne (symbol_ref "TARGET_SH5_CUT2_WORKAROUND") (const_int 0)))
         (const_int 8)
         ] (if_then_else (ne (symbol_ref "TARGET_SHMEDIA") (const_int 0))
                         (const_int 4)
                         (const_int 2))))

;; DFA descriptions for the pipelines

(include "sh1.md")
(include "shmedia.md")
(include "sh4.md")

(include "predicates.md")
(include "constraints.md")

;; Definitions for filling delay slots

(define_attr "needs_delay_slot" "yes,no" (const_string "no"))

(define_attr "banked" "yes,no" 
        (cond [(eq (symbol_ref "sh_loads_bankedreg_p (insn)")
                   (const_int 1))
               (const_string "yes")]
              (const_string "no")))

;; ??? This should be (nil) instead of (const_int 0)
(define_attr "hit_stack" "yes,no"
        (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
                   (const_int 0))
               (const_string "no")]
              (const_string "yes")))

(define_attr "interrupt_function" "no,yes"
  (const (symbol_ref "current_function_interrupt")))

(define_attr "in_delay_slot" "yes,no"
  (cond [(eq_attr "type" "cbranch") (const_string "no")
         (eq_attr "type" "pcload,pcload_si") (const_string "no")
         (eq_attr "needs_delay_slot" "yes") (const_string "no")
         (eq_attr "length" "2") (const_string "yes")
         ] (const_string "no")))

(define_attr "cond_delay_slot" "yes,no"
  (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
         ] (const_string "no")))

(define_attr "is_sfunc" ""
  (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))

(define_attr "is_mac_media" ""
  (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))

(define_attr "branch_zero" "yes,no"
  (cond [(eq_attr "type" "!cbranch") (const_string "no")
         (ne (symbol_ref "(next_active_insn (insn)\
                           == (prev_active_insn\
                               (XEXP (SET_SRC (PATTERN (insn)), 1))))\
                          && get_attr_length (next_active_insn (insn)) == 2")
             (const_int 0))
         (const_string "yes")]
        (const_string "no")))

;; SH4 Double-precision computation with double-precision result -
;; the two halves are ready at different times.
(define_attr "dfp_comp" "yes,no"
  (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
        (const_string "no")))

;; Insns for which the latency of a preceding fp insn is decreased by one.
(define_attr "late_fp_use" "yes,no" (const_string "no"))
;; And feeding insns for which this relevant.
(define_attr "any_fp_comp" "yes,no"
  (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
         (const_string "yes")]
        (const_string "no")))

(define_attr "any_int_load" "yes,no"
  (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
         (const_string "yes")]
        (const_string "no")))

(define_attr "highpart" "user, ignore, extend, depend, must_split"
  (const_string "user"))

(define_delay
  (eq_attr "needs_delay_slot" "yes")
  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])

;; On the SH and SH2, the rte instruction reads the return pc from the stack,
;; and thus we can't put a pop instruction in its delay slot.
;; ??? On the SH3, the rte instruction does not use the stack, so a pop
;; instruction can go in the delay slot.

;; Since a normal return (rts) implicitly uses the PR register,
;; we can't allow PR register loads in an rts delay slot.

(define_delay
  (eq_attr "type" "return")
  [(and (eq_attr "in_delay_slot" "yes")
        (ior (and (eq_attr "interrupt_function" "no")
                  (eq_attr "type" "!pload,prset"))
             (and (eq_attr "interrupt_function" "yes")
                  (ior
                   (eq (symbol_ref "TARGET_SH3") (const_int 0))
                   (eq_attr "hit_stack" "no")
                   (eq_attr "banked" "no"))))) (nil) (nil)])

;; Since a call implicitly uses the PR register, we can't allow
;; a PR register store in a jsr delay slot.

(define_delay
  (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
  [(and (eq_attr "in_delay_slot" "yes")
        (eq_attr "type" "!pstore,prget")) (nil) (nil)])

;; Say that we have annulled true branches, since this gives smaller and
;; faster code when branches are predicted as not taken.

;; ??? The non-annulled condition should really be "in_delay_slot",
;; but insns that can be filled in non-annulled get priority over insns
;; that can only be filled in anulled.

(define_delay
  (and (eq_attr "type" "cbranch")
       (ne (symbol_ref "TARGET_SH2") (const_int 0)))
  ;; SH2e has a hardware bug that pretty much prohibits the use of
  ;; annuled delay slots.
  [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
                                          (not (eq_attr "cpu" "sh2e"))) (nil)])
\f
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
;; -------------------------------------------------------------------------

(define_insn ""
  [(set (reg:SI T_REG)
        (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
                       (match_operand:SI 1 "arith_operand" "K08,r"))
               (const_int 0)))]
  "TARGET_SH1"
  "tst  %1,%0"
  [(set_attr "type" "mt_group")])

;; ??? Perhaps should only accept reg/constant if the register is reg 0.
;; That would still allow reload to create cmpi instructions, but would
;; perhaps allow forcing the constant into a register when that is better.
;; Probably should use r0 for mem/imm compares, but force constant into a
;; register for pseudo/imm compares.

(define_insn "cmpeqsi_t"
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
               (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
  "TARGET_SH1"
  "@
        tst     %0,%0
        cmp/eq  %1,%0
        cmp/eq  %1,%0"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgtsi_t"
  [(set (reg:SI T_REG)
        (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
               (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH1"
  "@
        cmp/gt  %1,%0
        cmp/pl  %0"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgesi_t"
  [(set (reg:SI T_REG)
        (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
               (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH1"
  "@
        cmp/ge  %1,%0
        cmp/pz  %0"
   [(set_attr "type" "mt_group")])

;; -------------------------------------------------------------------------
;; SImode compare and branch
;; -------------------------------------------------------------------------

(define_expand "cbranchsi4"
  [(set (pc)
        (if_then_else (match_operator 0 "comparison_operator"
                        [(match_operand:SI 1 "arith_operand" "")
                         (match_operand:SI 2 "arith_operand" "")])
                      (label_ref (match_operand 3 "" ""))
                      (pc)))
   (clobber (reg:SI T_REG))]
  "TARGET_CBRANCHDI4"
  "expand_cbranchsi4 (operands, CODE_FOR_nothing, -1); DONE;")

;; -------------------------------------------------------------------------
;; SImode unsigned integer comparisons
;; -------------------------------------------------------------------------

(define_insn_and_split "cmpgeusi_t"
  [(set (reg:SI T_REG)
        (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
                (match_operand:SI 1 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SH1"
  "cmp/hs       %1,%0"
  "&& operands[1] == CONST0_RTX (SImode)"
  [(pc)]
  "
{
  emit_insn (gen_sett ());
  DONE;
}"
   [(set_attr "type" "mt_group")])

(define_insn "cmpgtusi_t"
  [(set (reg:SI T_REG)
        (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
                (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "cmp/hi       %1,%0"
   [(set_attr "type" "mt_group")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpsi"
  [(set (reg:SI T_REG)
        (compare (match_operand:SI 0 "cmpsi_operand" "")
                 (match_operand:SI 1 "arith_operand" "")))]
  "TARGET_SH1 || TARGET_SHMEDIA"
  "
{
  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == T_REG
      && GET_CODE (operands[1]) != CONST_INT)
    operands[0] = copy_to_mode_reg (SImode, operands[0]);
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
\f
;; -------------------------------------------------------------------------
;; DImode compare and branch
;; -------------------------------------------------------------------------


;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
;; Therefore, we aim to have a set of three branches that go straight to the
;; destination, i.e. only one of them is taken at any one time.
;; This mechanism should also be slightly better for the sh4-200.

(define_expand "cbranchdi4"
  [(set (pc)
        (if_then_else (match_operator 0 "comparison_operator"
                        [(match_operand:DI 1 "arith_operand" "")
                         (match_operand:DI 2 "arith_operand" "")])
                      (label_ref (match_operand 3 "" ""))
                      (pc)))
   (clobber (match_dup 4))
   (clobber (reg:SI T_REG))]
  "TARGET_CBRANCHDI4"
  "
{
  enum rtx_code comparison;

  if (TARGET_EXPAND_CBRANCHDI4)
    {
      if (expand_cbranchdi4 (operands, CODE_FOR_nothing))
        DONE;
    }
  comparison = prepare_cbranch_operands (operands, DImode, CODE_FOR_nothing);
  if (comparison != GET_CODE (operands[0]))
    operands[0]
      = gen_rtx_fmt_ee (VOIDmode, comparison, operands[1], operands[2]);
   operands[4] = gen_rtx_SCRATCH (SImode);
}")

(define_insn_and_split "cbranchdi4_i"
  [(set (pc)
        (if_then_else (match_operator 0 "comparison_operator"
                        [(match_operand:DI 1 "arith_operand" "r,r")
                         (match_operand:DI 2 "arith_operand" "rN,i")])
                      (label_ref (match_operand 3 "" ""))
                      (pc)))
   (clobber (match_scratch:SI 4 "=X,&r"))
   (clobber (reg:SI T_REG))]
  "TARGET_CBRANCHDI4"
  "#"
  "&& reload_completed"
  [(pc)]
  "
{
  if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
    FAIL;
  DONE;
}")

;; -------------------------------------------------------------------------
;; DImode signed integer comparisons
;; -------------------------------------------------------------------------

(define_insn ""
  [(set (reg:SI T_REG)
        (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
                       (match_operand:DI 1 "arith_operand" "r"))
               (const_int 0)))]
  "TARGET_SH1"
  "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
                                 insn, operands);"
  [(set_attr "length" "6")
   (set_attr "type" "arith3b")])

(define_insn "cmpeqdi_t"
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
  "TARGET_SH1"
  "@
        tst     %S0,%S0\;bf     %,Ldi%=\;tst    %R0,%R0\\n%,Ldi%=:
        cmp/eq  %S1,%S0\;bf     %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "6")
   (set_attr "type" "arith3b")])

(define_split
  [(set (reg:SI T_REG)
        (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
               (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
;; If we applied this split when not optimizing, it would only be
;; applied during the machine-dependent reorg, when no new basic blocks
;; may be created.
  "TARGET_SH1 && reload_completed && optimize"
  [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
   (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
                           (label_ref (match_dup 6))
                           (pc)))
   (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
   (match_dup 6)]
  "
{
  operands[2]
    = gen_rtx_REG (SImode,
                   true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  operands[3]
    = (operands[1] == const0_rtx
       ? const0_rtx
       : gen_rtx_REG (SImode,
                      true_regnum (operands[1])
                      + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
  operands[4] = gen_lowpart (SImode, operands[0]);
  operands[5] = gen_lowpart (SImode, operands[1]);
  operands[6] = gen_label_rtx ();
}")

(define_insn "cmpgtdi_t"
  [(set (reg:SI T_REG)
        (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH2"
  "@
        cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
        tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpgedi_t"
  [(set (reg:SI T_REG)
        (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
               (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
  "TARGET_SH2"
  "@
        cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
        cmp/pz\\t%S0"
  [(set_attr "length" "8,2")
   (set_attr "type" "arith3,mt_group")])
\f
;; -------------------------------------------------------------------------
;; DImode unsigned integer comparisons
;; -------------------------------------------------------------------------

(define_insn "cmpgeudi_t"
  [(set (reg:SI T_REG)
        (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
                (match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpgtudi_t"
  [(set (reg:SI T_REG)
        (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
                (match_operand:DI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
  [(set_attr "length" "8")
   (set_attr "type" "arith3")])

(define_insn "cmpeqsi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (eq:SI (match_operand:SI 1 "logical_operand" "%r")
               (match_operand:SI 2 "cmp_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq        %1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpeqdi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (eq:SI (match_operand:DI 1 "register_operand" "%r")
               (match_operand:DI 2 "cmp_operand" "Nr")))]
  "TARGET_SHMEDIA"
  "cmpeq        %1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtsi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
               (match_operand:SI 2 "cmp_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt        %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtdi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
               (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgt        %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtusi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
                (match_operand:SI 2 "cmp_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu       %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

(define_insn "cmpgtudi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
                (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
  "TARGET_SHMEDIA"
  "cmpgtu       %N1, %N2, %0"
  [(set_attr "type" "cmp_media")])

; These two patterns are for combine.
(define_insn "*cmpne0sisi_media"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
  "TARGET_SHMEDIA"
  "cmpgtu       %1,r63,%0"
  [(set_attr "type" "cmp_media")])

;; We save the compare operands in the cmpxx patterns and use them when
;; we generate the branch.

(define_expand "cmpdi"
  [(set (reg:SI T_REG)
        (compare (match_operand:DI 0 "arith_operand" "")
                 (match_operand:DI 1 "arith_operand" "")))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  sh_compare_op0 = operands[0];
  sh_compare_op1 = operands[1];
  DONE;
}")
;; -------------------------------------------------------------------------
;; Conditional move instructions
;; -------------------------------------------------------------------------

;; The insn names may seem reversed, but note that cmveq performs the move
;; if op1 == 0, and cmvne does it if op1 != 0.

(define_insn "movdicc_false"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
                             (const_int 0))
         (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movdicc_true"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
                             (const_int 0))
         (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:DI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_peephole2
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (if_then_else:DI (match_operator 3 "equality_comparison_operator"
                           [(match_operand:DI 1 "arith_reg_operand" "")
                            (const_int 0)])
         (match_operand:DI 2 "arith_reg_dest" "")
         (match_dup 0)))
   (set (match_dup 2) (match_dup 0))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
        (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
  "
{
  operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
                                VOIDmode, operands[1], CONST0_RTX (DImode));
}")

(define_peephole2
  [(set (match_operand:DI 0 "general_movdst_operand" "")
        (match_operand:DI 1 "arith_reg_or_0_operand" ""))
   (set (match_operand:DI 2 "arith_reg_dest" "")
        (if_then_else:DI (match_operator 4 "equality_comparison_operator"
                           [(match_operand:DI 3 "arith_reg_operand" "")
                            (const_int 0)])
         (match_dup 0)
         (match_dup 2)))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
        (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
  "")

(define_expand "movdicc"
  [(set (match_operand:DI 0 "register_operand" "")
        (if_then_else:DI (match_operand 1 "comparison_operator" "")
                         (match_operand:DI 2 "register_operand" "")
                         (match_operand:DI 3 "register_operand" "")))]
  "TARGET_SHMEDIA"
  "
{
  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
      && GET_MODE (sh_compare_op0) == DImode
      && sh_compare_op1 == const0_rtx)
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
                                  sh_compare_op0, sh_compare_op1);
  else
    {
      rtx tmp;

      if (!can_create_pseudo_p ())
        FAIL;

      tmp = gen_reg_rtx (DImode);

      switch (GET_CODE (operands[1]))
        {
        case EQ:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case NE:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GT:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LT:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GE:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LE:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GTU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LTU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GEU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LEU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case ORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNEQ:
        case UNGE:
        case UNGT:
        case UNLE:
        case UNLT:
        case LTGT:
          FAIL;

        default:
          gcc_unreachable ();
        }
    }
}")

;; Add SImode variants for cmveq / cmvne to compensate for not promoting
;; SImode to DImode.
(define_insn "movsicc_false"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
                          (const_int 0))
         (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:SI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmveq        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "movsicc_true"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
                          (const_int 0))
         (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
         (match_operand:SI 3 "arith_reg_operand" "0")))]
  "TARGET_SHMEDIA"
  "cmvne        %1, %N2, %0"
  [(set_attr "type" "arith_media")])

(define_peephole2
  [(set (match_operand:SI 0 "arith_reg_dest" "")
        (if_then_else:SI (match_operator 3 "equality_comparison_operator"
                           [(match_operand:SI 1 "arith_reg_operand" "")
                            (const_int 0)])
         (match_operand:SI 2 "arith_reg_dest" "")
         (match_dup 0)))
   (set (match_dup 2) (match_dup 0))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
  [(set (match_dup 2)
        (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
  "
{
  operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
                                VOIDmode, operands[1], CONST0_RTX (SImode));
}")

(define_peephole2
  [(set (match_operand:SI 0 "general_movdst_operand" "")
        (match_operand:SI 1 "arith_reg_or_0_operand" ""))
   (set (match_operand:SI 2 "arith_reg_dest" "")
        (if_then_else:SI (match_operator 4 "equality_comparison_operator"
                           [(match_operand:SI 3 "arith_reg_operand" "")
                            (const_int 0)])
         (match_dup 0)
         (match_dup 2)))]
  "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
   && (GET_CODE (operands[1]) != REG || GENERAL_REGISTER_P (REGNO (operands[1])))"
  [(set (match_dup 2)
        (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
  "
{
  replace_rtx (operands[4], operands[0], operands[1]);
}")

(define_peephole2
  [(set (match_operand 0 "any_register_operand" "")
        (match_operand 1 "any_register_operand" ""))
   (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
   (set (match_operand 4 "" "") (match_operand 5 "" ""))]
  "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
    <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
   && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
   && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
   && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
   && ! reg_overlap_mentioned_p (operands[0], operands[3])
   && ! reg_overlap_mentioned_p (operands[2], operands[0])
   && ! reg_overlap_mentioned_p (operands[0], operands[1])
   && (REGNO_REG_CLASS (REGNO (operands[0]))
       == REGNO_REG_CLASS (REGNO (operands[2])))
   && (REGNO_REG_CLASS (REGNO (operands[1]))
       == REGNO_REG_CLASS (REGNO (operands[0])))"
  [(set (match_dup 0) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "
{
  rtx set1, set2;
  rtx replacements[4];

  /* We want to replace occurrences of operands[0] with operands[1] and
     operands[2] with operands[0] in operands[4]/operands[5].
     Doing just two replace_rtx calls naively would result in the second
     replacement undoing all that the first did if operands[1] and operands[2]
     are identical, so we must do this simultaneously.  */
  replacements[0] = operands[0];
  replacements[1] = operands[1];
  replacements[2] = operands[2];
  replacements[3] = operands[0];
  if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
      || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
      || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
    FAIL;

  operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
  replace_n_hard_rtx (operands[4], replacements, 2, 1);
  operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
  /* The operands array is aliased to recog_data.operand, which gets
     clobbered by extract_insn, so finish with it now.  */
  set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
  set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
  /* ??? The last insn might be a jump insn, but the generic peephole2 code
     always uses emit_insn.  */
  /* Check that we don't violate matching constraints or earlyclobbers.  */
  extract_insn (emit_insn (set1));
  if (! constrain_operands (1))
    goto failure;
  extract_insn (emit (set2));
  if (! constrain_operands (1))
    {
      rtx tmp;
    failure:
      tmp = replacements[0];
      replacements[0] = replacements[1];
      replacements[1] = tmp;
      tmp = replacements[2];
      replacements[2] = replacements[3];
      replacements[3] = tmp;
      replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
      replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
      replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
      FAIL;
    }
  DONE;
}")

;; The register allocator is rather clumsy in handling multi-way conditional
;; moves, so allow the combiner to make them, and we split them up after
;; reload.  */
(define_insn_and_split "*movsicc_umin"
  [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
        (umin:SI (if_then_else:SI
                   (eq (match_operand:SI 1 "arith_reg_operand" "r")
                       (const_int 0))
                   (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
                   (match_operand:SI 3 "register_operand" "0"))
                 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
   (clobber (match_scratch:SI 5 "=&r"))]
  "TARGET_SHMEDIA && !can_create_pseudo_p ()"
  "#"
  "TARGET_SHMEDIA && reload_completed"
  [(pc)]
  "
{
  emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
                                operands[3]));
  emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
  emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
                                operands[0]));
  DONE;
}")

(define_insn "*movsicc_t_false"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (if_then_else (eq (reg:SI T_REG) (const_int 0))
                      (match_operand:SI 1 "general_movsrc_operand" "r,I08")
                      (match_operand:SI 2 "arith_reg_operand" "0,0")))]
  "TARGET_PRETEND_CMOVE
   && (arith_reg_operand (operands[1], SImode)
       || (immediate_operand (operands[1], SImode)
           && satisfies_constraint_I08 (operands[1])))"
  "bt 0f\;mov %1,%0\\n0:"
  [(set_attr "type" "mt_group,arith") ;; poor approximation
   (set_attr "length" "4")])

(define_insn "*movsicc_t_true"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (if_then_else (ne (reg:SI T_REG) (const_int 0))
                      (match_operand:SI 1 "general_movsrc_operand" "r,I08")
                      (match_operand:SI 2 "arith_reg_operand" "0,0")))]
  "TARGET_PRETEND_CMOVE
   && (arith_reg_operand (operands[1], SImode)
       || (immediate_operand (operands[1], SImode)
           && satisfies_constraint_I08 (operands[1])))"
  "bf 0f\;mov %1,%0\\n0:"
  [(set_attr "type" "mt_group,arith") ;; poor approximation
   (set_attr "length" "4")])

(define_expand "movsicc"
  [(set (match_operand:SI 0 "arith_reg_dest" "")
        (if_then_else:SI (match_operand 1 "comparison_operator" "")
                         (match_operand:SI 2 "arith_reg_or_0_operand" "")
                         (match_operand:SI 3 "arith_reg_operand" "")))]
  "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
  "
{
  if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
      && GET_MODE (sh_compare_op0) == SImode
      && (TARGET_SHMEDIA
          || (REG_P (sh_compare_op0) && REGNO (sh_compare_op0) == T_REG))
      && sh_compare_op1 == const0_rtx)
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
                                  sh_compare_op0, sh_compare_op1);
  else if (TARGET_PRETEND_CMOVE)
    {
      enum rtx_code code = GET_CODE (operands[1]);
      enum rtx_code new_code = code;
      rtx tmp;

      if (! currently_expanding_to_rtl)
        FAIL;
      switch (code)
        {
        case LT: case LE: case LEU: case LTU:
          if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) != MODE_INT)
            break;
        case NE:
          new_code = reverse_condition (code);
          break;
        case EQ: case GT: case GE: case GEU: case GTU:
          break;
        default:
          FAIL;
        }
      tmp = prepare_scc_operands (new_code);
      operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
                                    tmp, const0_rtx);
    }
  else
    {
      rtx tmp;

      if (!can_create_pseudo_p ())
        FAIL;

      tmp = gen_reg_rtx (SImode);

      switch (GET_CODE (operands[1]))
        {
        case EQ:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case NE:
          emit_insn (gen_seq (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GT:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LT:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GE:
          emit_insn (gen_slt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LE:
          emit_insn (gen_sgt (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case GTU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case LTU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case GEU:
          emit_insn (gen_sltu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case LEU:
          emit_insn (gen_sgtu (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
          break;

        case ORDERED:
          emit_insn (gen_sunordered (tmp));
          operands[1] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
          break;

        case UNEQ:
        case UNGE:
        case UNGT:
        case UNLE:
        case UNLT:
        case LTGT:
          FAIL;

        default:
          abort ();
        }
    }
}")

(define_expand "movqicc"
  [(set (match_operand:QI 0 "register_operand" "")
        (if_then_else:QI (match_operand 1 "comparison_operator" "")
                         (match_operand:QI 2 "register_operand" "")
                         (match_operand:QI 3 "register_operand" "")))]
  "TARGET_SHMEDIA"
  "
{
  operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
  operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
  operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
  emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}")
\f
;; -------------------------------------------------------------------------
;; Addition instructions
;; -------------------------------------------------------------------------

(define_expand "adddi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
                 (match_operand:DI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode))
        FAIL;
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*adddi3_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                 (match_operand:DI 2 "arith_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        add     %1, %2, %0
        addi    %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "*adddisi3_media"
  [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                 (match_operand:DI 2 "arith_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, %2, %0
        addi.l  %1, %2, %0"
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_insn "adddi3z_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (zero_extend:DI
         (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
                  (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
  "TARGET_SHMEDIA"
  "addz.l       %1, %N2, %0"
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_insn "adddi3_compact"
  [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
                 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
                 (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
                       true_regnum (operands[0])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
                       true_regnum (operands[2])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_addc1 (high0, high0, high2));
  DONE;
}")

(define_insn "addc"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                          (match_operand:SI 2 "arith_reg_operand" "r"))
                 (reg:SI T_REG)))
   (set (reg:SI T_REG)
        (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
  "TARGET_SH1"
  "addc %2,%0"
  [(set_attr "type" "arith")])

(define_insn "addc1"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                          (match_operand:SI 2 "arith_reg_operand" "r"))
                 (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "addc %2,%0"
  [(set_attr "type" "arith")])

(define_expand "addsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (plus:SI (match_operand:SI 1 "arith_operand" "")
                 (match_operand:SI 2 "arith_operand" "")))]
  ""
  "
{
  if (TARGET_SHMEDIA)
    operands[1] = force_reg (SImode, operands[1]);
}")

(define_insn "addsi3_media"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
                 (match_operand:SI 2 "arith_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, %2, %0
        addi.l  %1, %2, %0"
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_insn "addsidi3_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
                                  "%r,r")
                                 (match_operand:SI 2 "arith_operand"
                                  "r,I10"))))]
  "TARGET_SHMEDIA"
  "@
        add.l   %1, %2, %0
        addi.l  %1, %2, %0"
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_insn "*addsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (plus:SI (match_operand:SI 1 "arith_operand" "%0")
                 (match_operand:SI 2 "arith_operand" "rI08")))]
  "TARGET_SH1"
  "add  %2,%0"
  [(set_attr "type" "arith")])

;; -------------------------------------------------------------------------
;; Subtraction instructions
;; -------------------------------------------------------------------------

(define_expand "subdi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "")
        (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
                  (match_operand:DI 2 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1)
    {
      operands[1] = force_reg (DImode, operands[1]);
      emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
      DONE;
    }
}")

(define_insn "*subdi3_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
                  (match_operand:DI 2 "arith_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub  %N1, %2, %0"
  [(set_attr "type" "arith_media")])
  
(define_insn "subdisi3_media"
  [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
        (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
                  (match_operand:DI 2 "arith_reg_operand" "r")))]
  "TARGET_SHMEDIA"
  "sub.l        %N1, %2, %0"
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_insn "subdi3_compact"
  [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
        (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
                 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "#"
  [(set_attr "length" "6")])

(define_split
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
                  (match_operand:DI 2 "arith_reg_operand" "")))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1 && reload_completed"
  [(const_int 0)]
  "
{
  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
  high0 = gen_rtx_REG (SImode,
                       true_regnum (operands[0])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  high2 = gen_rtx_REG (SImode,
                       true_regnum (operands[2])
                       + (TARGET_LITTLE_ENDIAN ? 1 : 0));
  emit_insn (gen_clrt ());
  emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
  emit_insn (gen_subc1 (high0, high0, high2));
  DONE;
}")

(define_insn "subc"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                            (match_operand:SI 2 "arith_reg_operand" "r"))
                  (reg:SI T_REG)))
   (set (reg:SI T_REG)
        (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
                          (reg:SI T_REG))
                (match_dup 1)))]
  "TARGET_SH1"
  "subc %2,%0"
  [(set_attr "type" "arith")])

(define_insn "subc1"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                            (match_operand:SI 2 "arith_reg_operand" "r"))
                  (reg:SI T_REG)))
   (clobber (reg:SI T_REG))]
  "TARGET_SH1"
  "subc %2,%0"
  [(set_attr "type" "arith")])

;; life_analysis thinks rn is live before subc rn,rn, so make a special
;; pattern for this case.  This helps multimedia applications that compute
;; the sum of absolute differences.
(define_insn "mov_neg_si_t"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r") (neg:SI (reg:SI T_REG)))]
  "TARGET_SH1"
  "subc %0,%0"
  [(set_attr "type" "arith")])

(define_insn "*subsi3_internal"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
                  (match_operand:SI 2 "arith_reg_operand" "r")))]
  "TARGET_SH1"
  "sub  %2,%0"
  [(set_attr "type" "arith")])

(define_insn_and_split "*subsi3_media"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
                  (match_operand:SI 2 "extend_reg_operand" "r")))]
  "TARGET_SHMEDIA
   && (operands[1] != constm1_rtx
       || (GET_CODE (operands[2]) != TRUNCATE
           && GET_CODE (operands[2]) != SUBREG))"
  "sub.l        %N1, %2, %0"
  "operands[1] == constm1_rtx"
  [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
  ""
  [(set_attr "type" "arith_media")
   (set_attr "highpart" "ignore")])

(define_split
  [(set (match_operand:SI 0 "arith_reg_dest" "")
        (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
                                                       "general_extend_operand"
                                                       "") 0)) 0)))]
  "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
  [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
   (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
  "")

(define_split
  [(set (match_operand:SI 0 "arith_reg_dest" "")
        (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
                                                       "general_extend_operand"
                                                       "") 0)) 3)))]
  "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
  [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
   (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
  "")
;; Convert `constant - reg' to `neg rX; add rX, #const' since this
;; will sometimes save one instruction.  Otherwise we might get
;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
;; are the same.

(define_expand "subsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (minus:SI (match_operand:SI 1 "arith_operand" "")
                  (match_operand:SI 2 "arith_reg_operand" "")))]
  ""
  "
{
  if (TARGET_SH1 && GET_CODE (operands[1]) == CONST_INT)
    {
      emit_insn (gen_negsi2 (operands[0], operands[2]));
      emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
      DONE;
    }
  if (TARGET_SHMEDIA)
    {
      if (!can_create_pseudo_p ()
          && ! arith_reg_or_0_operand (operands[1], SImode))
        FAIL;
      if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
        operands[1] = force_reg (SImode, operands[1]);
    }
}")
\f
;; -------------------------------------------------------------------------
;; Division instructions
;; -------------------------------------------------------------------------

;; We take advantage of the library routines which don't clobber as many
;; registers as a normal function call would.

;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
;; also has an effect on the register that holds the address of the sfunc.
;; To make this work, we have an extra dummy insn that shows the use
;; of this register for reorg.

(define_insn "use_sfunc_addr"
  [(set (reg:SI PR_REG)
        (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
  "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
  ""
  [(set_attr "length" "0")])

(define_insn "udivsi3_sh2a"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
                (match_operand:SI 2 "arith_reg_operand" "z")))]
  "TARGET_SH2A"
  "divu %2,%1"
  [(set_attr "type" "arith")
   (set_attr "in_delay_slot" "no")])

;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
;; hard register 0.  If we used hard register 0, then the next instruction
;; would be a move from hard register 0 to a pseudo-reg.  If the pseudo-reg
;; gets allocated to a stack slot that needs its address reloaded, then
;; there is nothing to prevent reload from using r0 to reload the address.
;; This reload would clobber the value in r0 we are trying to store.
;; If we let reload allocate r0, then this problem can never happen.

(define_insn "udivsi3_i1"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R4_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1 && ! TARGET_SH4"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

; Since shmedia-nofpu code could be linked against shcompact code, and
; the udivsi3 libcall has the same name, we must consider all registers
; clobbered that are in the union of the registers clobbered by the
; shmedia and the shcompact implementation.  Note, if the shcompact
; implementation actually used shcompact code, we'd need to clobber
; also r23 and fr23.
(define_insn "udivsi3_i1_media"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R20_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI R22_REG))
   (clobber (reg:DI TR0_REG))
   (clobber (reg:DI TR1_REG))
   (clobber (reg:DI TR2_REG))
   (use (match_operand 1 "target_reg_operand" "b"))]
  "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
  "blink        %1, r18"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "udivsi3_i4_media"
  [(set (match_dup 3)
        (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
   (set (match_dup 4)
        (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
   (set (match_dup 5) (float:DF (match_dup 3)))
   (set (match_dup 6) (float:DF (match_dup 4)))
   (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
   (set (match_dup 8) (fix:DI (match_dup 7)))
   (set (match_operand:SI 0 "register_operand" "")
        (truncate:SI (match_dup 8)))]
  "TARGET_SHMEDIA_FPU"
  "
{
  operands[3] = gen_reg_rtx (DImode);
  operands[4] = gen_reg_rtx (DImode);
  operands[5] = gen_reg_rtx (DFmode);
  operands[6] = gen_reg_rtx (DFmode);
  operands[7] = gen_reg_rtx (DFmode);
  operands[8] = gen_reg_rtx (DImode);
}")

(define_insn "udivsi3_i4"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:DF DR4_REG))
   (clobber (reg:SI R0_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (use (reg:PSI FPSCR_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "fp_mode" "double")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "udivsi3_i4_single"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:DF DR4_REG))
   (clobber (reg:SI R0_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "udivsi3_i4_int"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])


(define_expand "udivsi3"
  [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (udiv:SI (reg:SI R4_REG)
                            (reg:SI R5_REG)))
              (clobber (reg:SI T_REG))
              (clobber (reg:SI PR_REG))
              (clobber (reg:SI R4_REG))
              (use (match_dup 3))])]
  ""
  "
{
  rtx last;

  operands[3] = gen_reg_rtx (Pmode);
  /* Emit the move of the address to a pseudo outside of the libcall.  */
  if (TARGET_DIVIDE_CALL_TABLE)
    {
      /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
         that causes problems when the divide code is supposed to come from a
         separate library.  Division by zero is undefined, so dividing 1 can be
         implemented by comparing with the divisor.  */
      if (operands[1] == const1_rtx && currently_expanding_to_rtl)
        {
          emit_insn (gen_cmpsi (operands[1], operands[2]));
          emit_insn (gen_sgeu (operands[0]));
          DONE;
        }
      else if (operands[2] == const0_rtx)
        {
          emit_move_insn (operands[0], operands[2]);
          DONE;
        }
      function_symbol (operands[3], \"__udivsi3_i4i\", SFUNC_GOT);
      last = gen_udivsi3_i4_int (operands[0], operands[3]);
    }
  else if (TARGET_DIVIDE_CALL_FP)
    {
      function_symbol (operands[3], \"__udivsi3_i4\", SFUNC_STATIC);
      if (TARGET_FPU_SINGLE)
        last = gen_udivsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_udivsi3_i4 (operands[0], operands[3]);
    }
  else if (TARGET_SHMEDIA_FPU)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_SH2A)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_SH5)
    {
      function_symbol (operands[3],
                       TARGET_FPU_ANY ? \"__udivsi3_i4\" : \"__udivsi3\",
                       SFUNC_STATIC);

      if (TARGET_SHMEDIA)
        last = gen_udivsi3_i1_media (operands[0], operands[3]);
      else if (TARGET_FPU_ANY)
        last = gen_udivsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_udivsi3_i1 (operands[0], operands[3]);
    }
  else
    {
      function_symbol (operands[3], \"__udivsi3\", SFUNC_STATIC);
      last = gen_udivsi3_i1 (operands[0], operands[3]);
    }
  emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
  emit_insn (last);
  DONE;
}")

(define_insn "divsi3_sh2a"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
                (match_operand:SI 2 "arith_reg_operand" "z")))]
  "TARGET_SH2A"
  "divs %2,%1"
  [(set_attr "type" "arith")
   (set_attr "in_delay_slot" "no")])

(define_insn "divsi3_i1"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R2_REG))
   (clobber (reg:SI R3_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1 && ! TARGET_SH4"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "divsi3_i1_media"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R20_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI TR0_REG))
   (use (match_operand 1 "target_reg_operand" "b"))]
  "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
  "blink        %1, r18"
  [(set_attr "type" "sfunc")])

(define_insn "divsi3_media_2"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI TR0_REG))
   (use (reg:SI R20_REG))
   (use (match_operand 1 "target_reg_operand" "b"))]
  "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
  "blink        %1, r18"
  [(set_attr "type" "sfunc")])

;; This pattern acts as a placeholder for -mdiv=inv:call to carry
;; hard reg clobbers and data dependencies that we need when we want
;; to rematerialize the division into a call.
(define_insn_and_split "divsi_inv_call"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (div:SI (match_operand:SI 1 "register_operand" "r")
                (match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI TR0_REG))
   (clobber (reg:SI R20_REG))
   (use (match_operand:SI 3 "register_operand" "r"))]
  "TARGET_SHMEDIA"
  "#"
  "&& (high_life_started || reload_completed)"
  [(set (match_dup 0) (match_dup 3))]
  ""
  [(set_attr "highpart" "must_split")])

;; This is the combiner pattern for -mdiv=inv:call .
(define_insn_and_split "*divsi_inv_call_combine"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (match_operand:SI 1 "register_operand" "r")
                (match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:SI R4_REG))
   (clobber (reg:SI R5_REG))
   (clobber (reg:SI T_MEDIA_REG))
   (clobber (reg:SI PR_MEDIA_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI R21_REG))
   (clobber (reg:SI TR0_REG))
   (clobber (reg:SI R20_REG))
   (use (unspec:SI [(match_dup 1)
                    (match_operand:SI 3 "" "")
                    (unspec:SI [(match_operand:SI 4 "" "")
                                (match_dup 3)
                                (match_operand:DI 5 "" "")]
                     UNSPEC_DIV_INV_M2)
                    (match_operand:DI 6 "" "")
                    (const_int 0)
                    (const_int 0)]
         UNSPEC_DIV_INV_M3))]
  "TARGET_SHMEDIA"
  "#"
  "&& (high_life_started || reload_completed)"
  [(pc)]
  "
{
  const char *name = sh_divsi3_libfunc;
  enum sh_function_kind kind = SFUNC_GOT;
  rtx sym;

  emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
  emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
  while (TARGET_DIVIDE_INV_CALL2)
    {
      rtx x = operands[3];

      if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
        break;
      x = XVECEXP (x, 0, 0);
      name = \"__sdivsi3_2\";
      kind = SFUNC_STATIC;
      emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
      break;
    }
  sym = function_symbol (NULL, name, kind);
  emit_insn (gen_divsi3_media_2 (operands[0], sym));
  DONE;
}"
  [(set_attr "highpart" "must_split")])

(define_expand "divsi3_i4_media"
  [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
   (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
   (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
   (set (match_operand:SI 0 "register_operand" "=r")
        (fix:SI (match_dup 5)))]
  "TARGET_SHMEDIA_FPU"
  "
{
  operands[3] = gen_reg_rtx (DFmode);
  operands[4] = gen_reg_rtx (DFmode);
  operands[5] = gen_reg_rtx (DFmode);
}")

(define_insn "divsi3_i4"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (use (reg:PSI FPSCR_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "fp_mode" "double")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "divsi3_i4_single"
  [(set (match_operand:SI 0 "register_operand" "=y")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI PR_REG))
   (clobber (reg:DF DR0_REG))
   (clobber (reg:DF DR2_REG))
   (clobber (reg:SI R2_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "(TARGET_HARD_SH4 || TARGET_SHCOMPACT) && TARGET_FPU_SINGLE"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_insn "divsi3_i4_int"
  [(set (match_operand:SI 0 "register_operand" "=z")
        (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R1_REG))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))
   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
  "TARGET_SH1"
  "jsr  @%1%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "divsi3"
  [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (div:SI (reg:SI R4_REG)
                           (reg:SI R5_REG)))
              (clobber (reg:SI T_REG))
              (clobber (reg:SI PR_REG))
              (clobber (reg:SI R1_REG))
              (clobber (reg:SI R2_REG))
              (clobber (reg:SI R3_REG))
              (use (match_dup 3))])]
  ""
  "
{
  rtx last;

  operands[3] = gen_reg_rtx (Pmode);
  /* Emit the move of the address to a pseudo outside of the libcall.  */
  if (TARGET_DIVIDE_CALL_TABLE)
    {
      function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
      last = gen_divsi3_i4_int (operands[0], operands[3]);
    }
  else if (TARGET_DIVIDE_CALL_FP)
    {
      function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
      if (TARGET_FPU_SINGLE)
        last = gen_divsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_divsi3_i4 (operands[0], operands[3]);
    }
  else if (TARGET_SH2A)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_DIVIDE_INV)
    {
      rtx dividend = operands[1];
      rtx divisor = operands[2];
      rtx tab_base;
      rtx nsb_res = gen_reg_rtx (DImode);
      rtx norm64 = gen_reg_rtx (DImode);
      rtx tab_ix = gen_reg_rtx (DImode);
      rtx norm32 = gen_reg_rtx (SImode);
      rtx i92 = force_reg (DImode, GEN_INT (92));
      rtx scratch0a = gen_reg_rtx (DImode);
      rtx scratch0b = gen_reg_rtx (DImode);
      rtx inv0 = gen_reg_rtx (SImode);
      rtx scratch1a = gen_reg_rtx (DImode);
      rtx scratch1b = gen_reg_rtx (DImode);
      rtx shift = gen_reg_rtx (DImode);
      rtx i2p27, i43;
      rtx inv1 = gen_reg_rtx (SImode);
      rtx scratch2a = gen_reg_rtx (DImode);
      rtx scratch2b = gen_reg_rtx (SImode);
      rtx inv2 = gen_reg_rtx (SImode);
      rtx scratch3a = gen_reg_rtx (DImode);
      rtx scratch3b = gen_reg_rtx (DImode);
      rtx scratch3c = gen_reg_rtx (DImode);
      rtx scratch3d = gen_reg_rtx (SImode);
      rtx scratch3e = gen_reg_rtx (DImode);
      rtx result = gen_reg_rtx (SImode);

      if (! arith_reg_or_0_operand (dividend, SImode))
        dividend = force_reg (SImode, dividend);
      if (! arith_reg_operand (divisor, SImode))
        divisor = force_reg (SImode, divisor);
      if (flag_pic && Pmode != DImode)
        {
          tab_base = gen_rtx_SYMBOL_REF (Pmode, \"__div_table\");
          tab_base = gen_datalabel_ref (tab_base);
          tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
        }
      else
        {
          tab_base = gen_rtx_SYMBOL_REF (DImode, \"__div_table\");
          tab_base = gen_datalabel_ref (tab_base);
          tab_base = force_reg (DImode, tab_base);
        }
      if (TARGET_DIVIDE_INV20U)
        i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
      else
        i2p27 = GEN_INT (0);
      if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
        i43 = force_reg (DImode, GEN_INT (43));
      else
        i43 = GEN_INT (0);
      emit_insn (gen_nsbdi (nsb_res,
                            simplify_gen_subreg (DImode, divisor, SImode, 0)));
      emit_insn (gen_ashldi3_media (norm64,
                                    gen_rtx_SUBREG (DImode, divisor, 0),
                                    nsb_res));
      emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
      emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
      emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
                                   inv0, scratch0a, scratch0b,
                                   scratch1a, scratch1b));
      emit_insn (gen_subdi3 (shift, i92, nsb_res));
      emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
                                   scratch2a));
      emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
                                   i2p27, i43,
                                   scratch3a, scratch3b, scratch3c,
                                   scratch2a, scratch2b, scratch3d, scratch3e));
      if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
        emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
      else if (TARGET_DIVIDE_INV_FP)
        emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
                                     gen_reg_rtx (SImode), gen_reg_rtx (SImode),
                                     gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
                                     gen_reg_rtx (DFmode)));
      else
        emit_move_insn (operands[0], result);
      DONE;
    }
  else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
    {
      operands[1] = force_reg (SImode, operands[1]);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
      DONE;
    }
  else if (TARGET_SH5)
    {
      if (TARGET_DIVIDE_CALL2)
        {
          rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, \"__div_table\");
          tab_base = gen_datalabel_ref (tab_base);
          emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
        }
      if (TARGET_FPU_ANY && TARGET_SH1)
        function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
      else if (TARGET_DIVIDE_CALL2)
        function_symbol (operands[3], \"__sdivsi3_2\", SFUNC_STATIC);
      else
        function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);

      if (TARGET_SHMEDIA)
        last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
                (operands[0], operands[3]));
      else if (TARGET_FPU_ANY)
        last = gen_divsi3_i4_single (operands[0], operands[3]);
      else
        last = gen_divsi3_i1 (operands[0], operands[3]);
    }
  else
    {
      function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
      last = gen_divsi3_i1 (operands[0], operands[3]);
    }
  emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
  emit_insn (last);
  DONE;
}")

;; operands: scratch, tab_base, tab_ix
;; These are unspecs because we could generate an indexed addressing mode
;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
;; confuse reload.  See PR27117.

(define_insn "divsi_inv_qitable"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
                                    (match_operand:DI 2 "register_operand" "r")]
                         UNSPEC_DIV_INV_TABLE)))]
  "TARGET_SHMEDIA"
  "@
        ldx.ub  %1, %2, %0"
  [(set_attr "type" "load_media")
   (set_attr "highpart" "user")])

;; operands: scratch, tab_base, tab_ix
(define_insn "divsi_inv_hitable"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
                                    (match_operand:DI 2 "register_operand" "r")]
                         UNSPEC_DIV_INV_TABLE)))]
  "TARGET_SHMEDIA"
  "@
        ldx.w   %1, %2, %0"
  [(set_attr "type" "load_media")
   (set_attr "highpart" "user")])

;; operands: inv0, tab_base, tab_ix, norm32
;; scratch equiv in sdivsi3_2: r19, r21
(define_expand "divsi_inv_m0"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "register_operand" "r")
                    (match_operand:SI 3 "register_operand" "r")]
         UNSPEC_DIV_INV_M0))
   (clobber (match_operand:DI 4 "register_operand" "=r"))
   (clobber (match_operand:DI 5 "register_operand" "=r"))]
  "TARGET_SHMEDIA"
  "
{
/*
tab_base: r20
tab_ix: r21
norm32: r25
 ldx.ub r20, r21, r19 // u0.8
 shlli r21, 1, r21
 muls.l r25, r19, r19 // s2.38
 ldx.w r20, r21, r21  // s2.14
 shari r19, 24, r19   // truncate to s2.14
 sub r21, r19, r19    // some 11 bit inverse in s1.14
*/

  rtx inv0 = operands[0];
  rtx tab_base = operands[1];
  rtx tab_ix = operands[2];
  rtx norm32 = operands[3];
  rtx scratch0 = operands[4];
  rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);
  rtx scratch1 = operands[5];

  emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
  emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
  emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
  emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
  emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
  emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
  DONE;
}")

;; operands: inv1, tab_base, tab_ix, norm32
(define_insn_and_split "divsi_inv_m1"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "register_operand" "r")
                    (match_operand:SI 3 "register_operand" "r")]
         UNSPEC_DIV_INV_M1))
   (clobber (match_operand:SI 4 "register_operand" "=r"))
   (clobber (match_operand:DI 5 "register_operand" "=r"))
   (clobber (match_operand:DI 6 "register_operand" "=r"))
   (clobber (match_operand:DI 7 "register_operand" "=r"))
   (clobber (match_operand:DI 8 "register_operand" "=r"))]
  "TARGET_SHMEDIA"
  "#"
  "&& !can_create_pseudo_p ()"
  [(pc)]
  "
{
/* inv0: r19
 muls.l r19, r19, r18 // u0.28
 muls.l r25, r18, r18 // s2.58
 shlli r19, 45, r0    // multiply by two and convert to s2.58
 sub r0, r18, r18
 shari r18, 28, r18   // some 18 bit inverse in s1.30
*/

  rtx inv1 = operands[0];
  rtx tab_base = operands[1];
  rtx tab_ix = operands[2];
  rtx norm32 = operands[3];
  rtx inv0 = operands[4];
  rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
  rtx scratch0a = operands[5];
  rtx scratch0b = operands[6];
  rtx scratch0 = operands[7];
  rtx scratch1 = operands[8];
  rtx scratch1_si = simplify_gen_subreg (SImode, scratch1, DImode, SIDI_OFF);

  emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
                               scratch0a, scratch0b));
  emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
  emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
  emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
  emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
  emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
  DONE;
}")

;; operands: inv2, norm32, inv1, i92
(define_insn_and_split "divsi_inv_m2"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "register_operand" "r")
                    (match_operand:DI 3 "register_operand" "r")]
         UNSPEC_DIV_INV_M2))
   (clobber (match_operand:DI 4 "register_operand" "=r"))]
  "TARGET_SHMEDIA"
  "#"
  "&& !can_create_pseudo_p ()"
  [(pc)]
  "
{
/*
 muls.l r18, r25, r0  // s2.60
 shari r0, 16, r0     // s-16.44
  sub
 muls.l r0, r18, r19  // s-16.74
 shari r19, 30, r19   // s-16.44
*/
  rtx inv2 = operands[0];
  rtx norm32 = operands[1];
  rtx inv1 = operands[2];
  rtx i92 = operands[3];
  rtx scratch0 = operands[4];
  rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);

  emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
  emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
  emit_insn (gen_subdi3 (scratch0, i92, scratch0));
  emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
  emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
  DONE;
}")

(define_insn_and_split "divsi_inv_m3"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
                    (match_operand:SI 2 "register_operand" "r")
                    (match_operand:SI 3 "register_operand" "r")
                    (match_operand:DI 4 "register_operand" "r")
                    (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
                    (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
         UNSPEC_DIV_INV_M3))
   (clobber (match_operand:DI 7 "register_operand" "=r"))
   (clobber (match_operand:DI 8 "register_operand" "=r"))
   (clobber (match_operand:DI 9 "register_operand" "=r"))
   (clobber (match_operand:DI 10 "register_operand" "=r"))
   (clobber (match_operand:SI 11 "register_operand" "=r"))
   (clobber (match_operand:SI 12 "register_operand" "=r"))
   (clobber (match_operand:DI 13 "register_operand" "=r"))]
  "TARGET_SHMEDIA"
  "#"
  "&& !can_create_pseudo_p ()"
  [(pc)]
  "
{
/*
  r0: result  r1: shift  r4: dividend  r18: inv1  r19: inv2
  r0: scratch0  r19: scratch1 r21: scratch2

  muls.l r18, r4, r25 // s32.30
 muls.l r19, r4, r19  // s15.30
 shari r25, 63, r21
  shari r19, 14, r19  // s18.-14
 sub r25, r19, r0
 shard r0, r1, r0
 sub r0, r21, r0
*/

  rtx result = operands[0];
  rtx dividend = operands[1];
  rtx inv1 = operands[2];
  rtx inv2 = operands[3];
  rtx shift = operands[4];
  rtx scratch0 = operands[7];
  rtx scratch1 = operands[8];
  rtx scratch2 = operands[9];

  if (satisfies_constraint_N (dividend))
    {
      emit_move_insn (result, dividend);
      DONE;
    }

  emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
  emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
  emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
  emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
  emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
  emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
  emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
  DONE;
}")

;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
;; inv1: tab_base, tab_ix, norm32
;; inv2: norm32, inv1, i92
(define_insn_and_split "divsi_inv_m1_3"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
                    (unspec:SI [(match_operand:DI 2 "register_operand" "r")
                                (match_operand:DI 3 "register_operand" "r")
                                (match_operand:SI 4 "register_operand" "r")]
                     UNSPEC_DIV_INV_M1)
                    (unspec:SI [(match_dup 4)
                                (unspec:SI [(match_dup 2)
                                            (match_dup 3)
                                            (match_dup 4)] UNSPEC_DIV_INV_M1)
                                (match_operand:SI 5 "" "")]
                     UNSPEC_DIV_INV_M2)
                    (match_operand:DI 6 "register_operand" "r")
                    (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
                    (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
         UNSPEC_DIV_INV_M3))
   (clobber (match_operand:DI 9 "register_operand" "=r"))
   (clobber (match_operand:DI 10 "register_operand" "=r"))
   (clobber (match_operand:DI 11 "register_operand" "=r"))
   (clobber (match_operand:DI 12 "register_operand" "=r"))
   (clobber (match_operand:SI 13 "register_operand" "=r"))
   (clobber (match_operand:SI 14 "register_operand" "=r"))
   (clobber (match_operand:DI 15 "register_operand" "=r"))]
  "TARGET_SHMEDIA
   && (TARGET_DIVIDE_INV_MINLAT
       || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
  "#"
  "&& !can_create_pseudo_p ()"
  [(pc)]
  "
{
  rtx result = operands[0];
  rtx dividend = operands[1];
  rtx tab_base = operands[2];
  rtx tab_ix = operands[3];
  rtx norm32 = operands[4];
  /* rtx i92 = operands[5]; */
  rtx shift = operands[6];
  rtx i2p27 = operands[7];
  rtx i43 = operands[8];
  rtx scratch0 = operands[9];
  rtx scratch0_si = simplify_gen_subreg (SImode, scratch0, DImode, SIDI_OFF);
  rtx scratch1 = operands[10];
  rtx scratch1_si = simplify_gen_subreg (SImode, scratch1, DImode, SIDI_OFF);
  rtx scratch2 = operands[11];
  rtx scratch3 = operands[12];
  rtx scratch4 = operands[13];
  rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
  rtx scratch5 = operands[14];
  rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
  rtx scratch6 = operands[15];

  emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
                               scratch0, scratch1));
  /* inv0 == scratch4 */
  if (! TARGET_DIVIDE_INV20U)
    {
      emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
      i2p27 = scratch0;
      emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
    }
  else
    {
      emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
      emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
    }
  emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
  emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
  emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
  /* inv1 == scratch4 */

  if (TARGET_DIVIDE_INV_MINLAT)
    {
      emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
      emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
      emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
      emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
      emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
      emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
      emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
      emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
      emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
      emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
      emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
    }
  else
    {
      rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
      /* Use separate scratch regs for nsb and sign to allow scheduling.  */
      emit_insn (gen_nsbdi (scratch6,
                            simplify_gen_subreg (DImode, dividend, SImode, 0)));
      emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
      emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
      emit_insn (gen_divsi_inv20 (scratch2,
                                  norm32, scratch4, dividend,
                                  scratch6, scratch3, i43,
                                  /* scratch0 may be shared with i2p27.  */
                                  scratch0, scratch1, scratch5,
                                  label, label, i2p27));
    }
  emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
  emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
  DONE;
}")

(define_insn "divsi_inv20"
  [(set (match_operand:DI 0 "register_operand" "=&r")
        (unspec:DI [(match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "register_operand" "r")
                    (match_operand:SI 3 "register_operand" "r")
                    (match_operand:DI 4 "register_operand" "r")
                    (match_operand:DI 5 "register_operand" "r")
                    (match_operand:DI 6 "register_operand" "r")
                    (match_operand:DI 12 "register_operand" "r")
                    (match_operand 10 "target_operand" "b")
                    (match_operand 11 "immediate_operand" "i")]
         UNSPEC_DIV_INV20))
   (clobber (match_operand:DI 7 "register_operand" "=&r"))
   (clobber (match_operand:DI 8 "register_operand" "=&r"))
   (clobber (match_operand:SI 9 "register_operand" "=r"))]
  "TARGET_SHMEDIA
   && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
  "*
{
/* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
             %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
             %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
             %10 label (tr), %11 label (imm)

 muls.l inv1, norm32, scratch0  // s2.60
  muls.l inv1, dividend, result // s32.30
  xor i2p27, result_sign, round_scratch
 bge/u dividend_nsb, i43, tr.. (label)
 shari scratch0, 16, scratch0   // s-16.44
 muls.l sratch0_si, inv1, scratch0 // s-16.74
  sub result, round_scratch, result
  shari dividend, 14, scratch1   // s19.-14
 shari scratch0, 30, scratch0   // s-16.44
 muls.l scratch0, scratch1, round_scratch // s15.30
label:
 sub result, round_scratch, result */

  int likely = TARGET_DIVIDE_INV20L;

  if (! likely) output_asm_insn (\"muls.l\t%2, %1 , %8\", operands);
  output_asm_insn (\"muls.l\t%2, %3, %0\;xor\t%12, %5, %7\", operands);
  output_asm_insn (likely
                   ? \"bge/l\t%4, %6, %10\;muls.l\t%2, %1 , %8\"
                   : \"bge/u\t%4, %6, %10\", operands);
  output_asm_insn (\"shari\t%8, 16, %8\;muls.l\t%8, %2, %8\", operands);
  if (! likely) output_asm_insn (\"sub\t%0, %7, %0\", operands);
  output_asm_insn (\"shari\t%3, 14, %9\;shari\t%8, 30, %8\", operands);
  return (likely
          ? \"muls.l\t%8, %9, %8\;sub\t%0, %8, %0\n%11:\tadd\t%0, %7, %0\"
          : \"muls.l\t%8, %9, %7\n%11:\tsub\t%0, %7, %0\");
}")

(define_insn_and_split "divsi_inv_fp"
  [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
        (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
                (match_operand:SI 2 "register_operand" "rf")))
   (use (match_operand:SI 3 "general_movsrc_operand" "r"))
   (clobber (match_operand:SI 4 "register_operand" "=r"))
   (clobber (match_operand:SI 5 "register_operand" "=r"))
   (clobber (match_operand:DF 6 "register_operand" "=r"))
   (clobber (match_operand:DF 7 "register_operand" "=r"))
   (clobber (match_operand:DF 8 "register_operand" "=r"))]
  "TARGET_SHMEDIA_FPU"
  "#"
  "&& (high_life_started || reload_completed)"
  [(set (match_dup 0) (match_dup 3))]
  ""
  [(set_attr "highpart" "must_split")])

;; If a matching group of divide-by-inverse instructions is in the same
;; basic block after gcse & loop optimizations, we want to transform them
;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
(define_insn_and_split "*divsi_inv_fp_combine"
  [(set (match_operand:SI 0 "register_operand" "=f")
        (div:SI (match_operand:SI 1 "register_operand" "f")
                (match_operand:SI 2 "register_operand" "f")))
   (use (unspec:SI [(match_dup 1)
                    (match_operand:SI 3 "" "")
                    (unspec:SI [(match_operand:SI 4 "" "")
                                (match_dup 3)
                                (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
                    (match_operand:DI 6 "" "")
                    (const_int 0)
                    (const_int 0)] UNSPEC_DIV_INV_M3))
   (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
   (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
   (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
   (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
   (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
  "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(set (match_dup 9) (float:DF (match_dup 1)))
   (set (match_dup 10) (float:DF (match_dup 2)))
   (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
   (set (match_dup 8)
        (fix:SI (match_dup 11)))
   (set (match_dup 0) (match_dup 8))]
  "
{
  if (! fp_arith_reg_operand (operands[1], SImode))
    {
      emit_move_insn (operands[7], operands[1]);
      operands[1] = operands[7];
    }
  if (! fp_arith_reg_operand (operands[2], SImode))
    {
      emit_move_insn (operands[8], operands[2]);
      operands[2] = operands[8];
    }
}"
  [(set_attr "highpart" "must_split")])
\f
;; -------------------------------------------------------------------------
;; Multiplication instructions
;; -------------------------------------------------------------------------

(define_insn "umulhisi3_i"
  [(set (reg:SI MACL_REG)
        (mult:SI (zero_extend:SI
                  (match_operand:HI 0 "arith_reg_operand" "r"))
                 (zero_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" "r"))))]
  "TARGET_SH1"
  "mulu.w       %1,%0"
  [(set_attr "type" "smpy")])

(define_insn "mulhisi3_i"
  [(set (reg:SI MACL_REG)
        (mult:SI (sign_extend:SI
                  (match_operand:HI 0 "arith_reg_operand" "r"))
                 (sign_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" "r"))))]
  "TARGET_SH1"
  "muls.w       %1,%0"
  [(set_attr "type" "smpy")])

(define_expand "mulhisi3"
  [(set (reg:SI MACL_REG)
        (mult:SI (sign_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" ""))
                 (sign_extend:SI
                  (match_operand:HI 2 "arith_reg_operand" ""))))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  rtx insn, macl;

  macl = gen_rtx_REG (SImode, MACL_REG);
  start_sequence ();
  emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
  insn = get_insns ();  
  end_sequence ();
  /* expand_binop can't find a suitable code in umul_widen_optab to
     make a REG_EQUAL note from, so make one here.
     See also smulsi3_highpart.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_expr.  */
  /* Use emit_libcall_block for loop invariant code motion and to make
     a REG_EQUAL note.  */
  emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));

  DONE;
}")

(define_expand "umulhisi3"
  [(set (reg:SI MACL_REG)
        (mult:SI (zero_extend:SI
                  (match_operand:HI 1 "arith_reg_operand" ""))
                 (zero_extend:SI
                  (match_operand:HI 2 "arith_reg_operand" ""))))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  rtx insn, macl;

  macl = gen_rtx_REG (SImode, MACL_REG);
  start_sequence ();
  emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
  insn = get_insns ();  
  end_sequence ();
  /* expand_binop can't find a suitable code in umul_widen_optab to
     make a REG_EQUAL note from, so make one here.
     See also smulsi3_highpart.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_expr.  */
  /* Use emit_libcall_block for loop invariant code motion and to make
     a REG_EQUAL note.  */
  emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));

  DONE;
}")

;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
;; a call to a routine which clobbers known registers.

(define_insn ""
  [(set (match_operand:SI 1 "register_operand" "=z")
        (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
   (clobber (reg:SI MACL_REG))
   (clobber (reg:SI T_REG))
   (clobber (reg:SI PR_REG))
   (clobber (reg:SI R3_REG))
   (clobber (reg:SI R2_REG))
   (clobber (reg:SI R1_REG))
   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
  "TARGET_SH1"
  "jsr  @%0%#"
  [(set_attr "type" "sfunc")
   (set_attr "needs_delay_slot" "yes")])

(define_expand "mulsi3_call"
  [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel[(set (match_operand:SI 0 "register_operand" "")
                  (mult:SI (reg:SI R4_REG)
                           (reg:SI R5_REG)))
             (clobber (reg:SI MACL_REG))
             (clobber (reg:SI T_REG))
             (clobber (reg:SI PR_REG))
             (clobber (reg:SI R3_REG))
             (clobber (reg:SI R2_REG))
             (clobber (reg:SI R1_REG))
             (use (match_operand:SI 3 "register_operand" ""))])]
  "TARGET_SH1"
  "")

(define_insn "mul_r"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
                 (match_operand:SI 2 "arith_reg_operand" "z")))]
  "TARGET_SH2A"
  "mulr %2,%0"
  [(set_attr "type" "dmpy")])

(define_insn "mul_l"
  [(set (reg:SI MACL_REG)
        (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
                 (match_operand:SI 1 "arith_reg_operand" "r")))]
  "TARGET_SH2"
  "mul.l        %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "mulsi3"
  [(set (reg:SI MACL_REG)
        (mult:SI  (match_operand:SI 1 "arith_reg_operand" "")
                  (match_operand:SI 2 "arith_reg_operand" "")))
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACL_REG))]
  "TARGET_SH1"
  "
{
  if (!TARGET_SH2)
    {
      /* The address must be set outside the libcall,
         since it goes into a pseudo.  */
      rtx sym = function_symbol (NULL, \"__mulsi3\", SFUNC_STATIC);
      rtx addr = force_reg (SImode, sym);
      rtx insns = gen_mulsi3_call (operands[0], operands[1],
                                   operands[2], addr);
      emit_insn (insns);
    }
  else
    {
      rtx macl = gen_rtx_REG (SImode, MACL_REG);

      emit_insn (gen_mul_l (operands[1], operands[2]));
      /* consec_sets_giv can only recognize the first insn that sets a
         giv as the giv insn.  So we must tag this also with a REG_EQUAL
         note.  */
      emit_insn (gen_movsi_i ((operands[0]), macl));
    }
  DONE;
}")

(define_insn "mulsidi3_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (set (reg:SI MACL_REG)
        (mult:SI (match_dup 0)
                 (match_dup 1)))]
  "TARGET_SH2"
  "dmuls.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "mulsidi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
                 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  if (TARGET_SH2)
    {
       emit_insn (gen_mulsidi3_compact (operands[0], operands[1],
                                        operands[2]));
       DONE;
    }
}")

(define_insn "mulsidi3_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
                 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "muls.l       %1, %2, %0"
  [(set_attr "type" "dmpy_media")
   (set_attr "highpart" "ignore")])

(define_insn "mulsidi3_compact"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (mult:DI
         (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
         (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "#")

(define_split
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (mult:DI
         (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
         (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  [(const_int 0)]
  "
{
  rtx low_dst = gen_lowpart (SImode, operands[0]);
  rtx high_dst = gen_highpart (SImode, operands[0]);

  emit_insn (gen_mulsidi3_i (operands[1], operands[2]));

  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
  /* We need something to tag the possible REG_EQUAL notes on to.  */
  emit_move_insn (operands[0], operands[0]);
  DONE;
}")

(define_insn "umulsidi3_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (set (reg:SI MACL_REG)
        (mult:SI (match_dup 0)
                 (match_dup 1)))]
  "TARGET_SH2"
  "dmulu.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "umulsidi3"
  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
                 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SH2 || TARGET_SHMEDIA"
  "
{
  if (TARGET_SH2)
    {
       emit_insn (gen_umulsidi3_compact (operands[0], operands[1],
                                         operands[2]));
       DONE;
    }
}")

(define_insn "umulsidi3_media"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
                 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "mulu.l       %1, %2, %0"
  [(set_attr "type" "dmpy_media")
   (set_attr "highpart" "ignore")])

(define_insn "umulsidi3_compact"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (mult:DI
         (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
         (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "#")

(define_split
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
                 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
   (clobber (reg:SI MACH_REG))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  [(const_int 0)]
  "
{
  rtx low_dst = gen_lowpart (SImode, operands[0]);
  rtx high_dst = gen_highpart (SImode, operands[0]);

  emit_insn (gen_umulsidi3_i (operands[1], operands[2]));

  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
  /* We need something to tag the possible REG_EQUAL notes on to.  */
  emit_move_insn (operands[0], operands[0]);
  DONE;
}")

(define_insn "smulsi3_highpart_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "dmuls.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "smulsi3_highpart"
  [(parallel
    [(set (reg:SI MACH_REG)
          (truncate:SI
           (lshiftrt:DI
            (mult:DI
             (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
             (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
            (const_int 32))))
    (clobber (reg:SI MACL_REG))])
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACH_REG))]
  "TARGET_SH2"
  "
{
  rtx insn, mach;

  mach = gen_rtx_REG (SImode, MACH_REG);
  start_sequence ();
  emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
  insn = get_insns ();  
  end_sequence ();
  /* expand_binop can't find a suitable code in mul_highpart_optab to
     make a REG_EQUAL note from, so make one here.
     See also {,u}mulhisi.
     ??? Alternatively, we could put this at the calling site of expand_binop,
     i.e. expand_mult_highpart.  */
  /* Use emit_libcall_block for loop invariant code motion and to make
     a REG_EQUAL note.  */
  emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));

  DONE;
}")

(define_insn "umulsi3_highpart_i"
  [(set (reg:SI MACH_REG)
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
           (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
           (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
          (const_int 32))))
   (clobber (reg:SI MACL_REG))]
  "TARGET_SH2"
  "dmulu.l      %1,%0"
  [(set_attr "type" "dmpy")])

(define_expand "umulsi3_highpart"
  [(parallel
    [(set (reg:SI MACH_REG)
          (truncate:SI
           (lshiftrt:DI
            (mult:DI
             (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
             (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
            (const_int 32))))
    (clobber (reg:SI MACL_REG))])
   (set (match_operand:SI 0 "arith_reg_operand" "")
        (reg:SI MACH_REG))]
  "TARGET_SH2"
  "
{
  rtx insn, mach;

  mach = gen_rtx_REG (SImode, MACH_REG);
  start_sequence ();
  emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
  insn = get_insns ();  
  end_sequence ();
  /* Use emit_libcall_block for loop invariant code motion and to make
     a REG_EQUAL note.  */
  emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));

  DONE;
}")

(define_insn_and_split "muldi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
                 (match_operand:DI 2 "arith_reg_operand" "r")))
   (clobber (match_scratch:DI 3 "=&r"))
   (clobber (match_scratch:DI 4 "=r"))]
  "TARGET_SHMEDIA"
  "#"
  "reload_completed"
  [(const_int 0)]
  "
{
  rtx op3_v2si, op2_v2si;

  op3_v2si = operands[3];
  if (GET_CODE (op3_v2si) == SIGN_EXTEND)
    {
      op3_v2si = XEXP (op3_v2si, 0);
      op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
    }
  op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
  op2_v2si = operands[2];
  if (GET_CODE (op2_v2si) == SIGN_EXTEND)
    {
      op2_v2si = XEXP (op2_v2si, 0);
      op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
    }
  op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
  emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
  emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
  emit_insn (gen_umulsidi3_media (operands[4],
                                 sh_gen_truncate (SImode, operands[1], 0),
                                 sh_gen_truncate (SImode, operands[2], 0)));
  emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
  emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
  emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
  emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
  DONE;
}")

\f
;; -------------------------------------------------------------------------
;; Logical operations
;; -------------------------------------------------------------------------

(define_insn "*andsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
        (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "r,K08")))]
  "TARGET_SH1"
  "and  %2,%0"
  [(set_attr "type" "arith")])

(define_insn "*andsi3_media"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
                (match_operand:SI 2 "logical_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        and     %1, %2, %0
        andi    %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "*andsi3_bclr"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
                (match_operand:SI 2 "const_int_operand" "Psz")))]
  "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
  "bclr\\t%W2,%0"
  [(set_attr "type" "arith")])

;; If the constant is 255, then emit an extu.b instruction instead of an
;; and, since that will give better code.

(define_expand "andsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (and:SI (match_operand:SI 1 "logical_reg_operand" "")
                (match_operand:SI 2 "logical_operand" "")))]
  ""
  "
{
  if (TARGET_SH1
      && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
    {
      emit_insn (gen_zero_extendqisi2 (operands[0],
                                       gen_lowpart (QImode, operands[1])));
      DONE;
    }
}")

(define_insn_and_split "anddi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
        (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
                (match_operand:DI 2 "and_operand" "r,I10,J16")))]
  "TARGET_SHMEDIA"
  "@
        and     %1, %2, %0
        andi    %1, %2, %0
        #"
  "reload_completed
   && ! logical_operand (operands[2], DImode)"
  [(const_int 0)]
  "
{
  if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
    emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
  else
    emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
  DONE;
}"
  [(set_attr "type" "arith_media")])

(define_insn "andcsi3"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
                (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "andc %1,%2,%0"
  [(set_attr "type" "arith_media")])

(define_insn "andcdi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
                (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
  "TARGET_SHMEDIA"
  "andc %1,%2,%0"
  [(set_attr "type" "arith_media")])

(define_expand "iorsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
                (match_operand:SI 2 "logical_operand" "")))]
  ""
  "")

(define_insn "*iorsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
        (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "r,K08")))]
  "TARGET_SH1
   && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
  "or   %2,%0"
  [(set_attr "type" "arith")])

(define_insn "*iorsi3_media"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
                (match_operand:SI 2 "logical_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        or      %1, %2, %0
        ori     %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn "*iorsi3_bset"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
        (match_operand:SI 2 "const_int_operand" "Pso")))]
  "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
  "bset\\t%V2,%0"
  [(set_attr "type" "arith")])

(define_insn "iordi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                (match_operand:DI 2 "logical_operand" "r,I10")))]
  "TARGET_SHMEDIA"
  "@
        or      %1, %2, %0
        ori     %1, %2, %0"
  [(set_attr "type" "arith_media")])

(define_insn_and_split "*logical_sidi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (sign_extend:DI (match_operator:SI 3 "logical_operator"
                          [(match_operand:SI 1 "arith_reg_operand" "%r,r")
                           (match_operand:SI 2 "logical_operand" "r,I10")])))]
  "TARGET_SHMEDIA"
  "#"
  "&& reload_completed"
  [(set (match_dup 0) (match_dup 3))]
  "
{
  operands[3]
    = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
                      simplify_gen_subreg (DImode, operands[1], SImode, 0),
                      simplify_gen_subreg (DImode, operands[2], SImode, 0));
}")

(define_insn_and_split "*logical_sidisi3"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (truncate:SI (sign_extend:DI
                        (match_operator:SI 3 "logical_operator"
                          [(match_operand:SI 1 "arith_reg_operand" "%r,r")
                           (match_operand:SI 2 "logical_operand" "r,I10")]))))]
  "TARGET_SHMEDIA"
  "#"
  "&& 1"
  [(set (match_dup 0) (match_dup 3))])

(define_insn_and_split "*logical_sidi3_2"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (sign_extend:DI (truncate:SI (sign_extend:DI
                        (match_operator:SI 3 "logical_operator"
                          [(match_operand:SI 1 "arith_reg_operand" "%r,r")
                           (match_operand:SI 2 "logical_operand" "r,I10")])))))]
  "TARGET_SHMEDIA"
  "#"
  "&& 1"
  [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])

(define_expand "xorsi3"
  [(set (match_operand:SI 0 "arith_reg_operand" "")
        (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
                (match_operand:SI 2 "xor_operand" "")))]
  ""
  "")

(define_insn "*xorsi3_compact"
  [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
        (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
                (match_operand:SI 2 "logical_operand" "K08,r")))]
  "TARGET_SH1"
  "xor  %2,%0"
  [(set_attr "type" "arith")])

(define_insn "*xorsi3_media"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
        (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
                (match_operand:SI 2 "xor_operand" "r,I06")))]
  "TARGET_SHMEDIA"
  "@
        xor     %1, %2, %0
        xori    %1, %2, %0"
  [(set_attr "type" "arith_media")])

;; Store the complements of the T bit in a register.
(define_insn "xorsi3_movrt"
  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
        (xor:SI (reg:SI T_REG)
                (const_int 1)))]
  "TARGET_SH2A"
  "movrt\\t%0"
  [(set_attr "type" "arith")])

(define_insn "xordi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
        (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
                (match_operand:DI 2 "xor_operand" "r,I06")))]
  "TARGET_SHMEDIA"
  "@
        xor     %1, %2, %0
        xori    %1, %2, %0"
  [(set_attr "type" "arith_media")])

;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
;; converts 2 * sign extend -> logical op into logical op -> sign extend
(define_split
  [(set (match_operand:DI 0 "arith_reg_dest" "")
        (sign_extend:DI (match_operator 4 "binary_logical_operator"
                          [(match_operand 1 "any_register_operand" "")
                           (match_operand 2 "any_register_operand" "")])))]
  "TARGET_SHMEDIA"
  [(set (match_dup 5) (match_dup 4))
   (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
"
{
  enum machine_mode inmode = GET_MODE (operands[1]);
  int offset = 0;

  if (GET_CODE (operands[0]) == SUBREG)
    {
      offset = SUBREG_BYTE (operands[0]);
      operands[0] = SUBREG_REG (operands[0]);
    }
  gcc_assert (GET_CODE (operands[0]) == REG);
  if (! TARGET_LITTLE_ENDIAN)
    offset += 8 - GET_MODE_SIZE (inmode);
  operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
}")
\f
;; -------------------------------------------------------------------------
;; Shifts and rotates
;; -------------------------------------------------------------------------

(define_expand "rotldi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
                   (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")

(define_insn "rotldi3_mextr"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
                   (match_operand:HI 2 "mextr_bit_offset" "i")))]
  "TARGET_SHMEDIA"
  "*
{
  static char templ[16];

  sprintf (templ, \"mextr%d\\t%%1,%%1,%%0\",
           8 - (int) (INTVAL (operands[2]) >> 3));
  return templ;
}"
  [(set_attr "type" "arith_media")])

(define_expand "rotrdi3"
  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
        (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")