1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
5 ;; Improved by Jim Wilson (wilson@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Should prepend a * to all pattern names which are not used.
26 ;; This will make the compiler smaller, and rebuilds after changes faster.
28 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
29 ;; sequences. Especially the sequences for arithmetic right shifts.
31 ;; ??? Should check all DImode patterns for consistency and usefulness.
33 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
34 ;; way to generate them.
36 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
37 ;; for a str* inline function.
39 ;; BSR is not generated by the compiler proper, but when relaxing, it
40 ;; generates .uses pseudo-ops that allow linker relaxation to create
41 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
43 ;; Special constraints for SH machine description:
50 ;; Special formats used for outputting SH instructions:
52 ;; %. -- print a .s if insn needs delay slot
53 ;; %@ -- print rte/rts if is/isn't an interrupt function
54 ;; %# -- output a nop if there is nothing to put in the delay slot
55 ;; %O -- print a constant without the #
56 ;; %R -- print the lsw reg of a double
57 ;; %S -- print the msw reg of a double
58 ;; %T -- print next word of a double REG or MEM
60 ;; Special predicates:
62 ;; arith_operand -- operand is valid source for arithmetic op
63 ;; arith_reg_operand -- operand is valid register for arithmetic op
64 ;; general_movdst_operand -- operand is valid move destination
65 ;; general_movsrc_operand -- operand is valid move source
66 ;; logical_operand -- operand is valid source for logical op
68 ;; -------------------------------------------------------------------------
70 ;; -------------------------------------------------------------------------
102 ;; These are used with unspec.
114 ;; These are used with unspec_volatile.
120 (UNSPECV_WINDOW_END 10)
121 (UNSPECV_CONST_END 11)
124 ;; -------------------------------------------------------------------------
126 ;; -------------------------------------------------------------------------
131 "sh1,sh2,sh3,sh3e,sh4"
132 (const (symbol_ref "sh_cpu_attr")))
134 (define_attr "endian" "big,little"
135 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
136 (const_string "little") (const_string "big"))))
138 ;; Indicate if the default fpu mode is single precision.
139 (define_attr "fpu_single" "yes,no"
140 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
141 (const_string "yes") (const_string "no"))))
143 (define_attr "fmovd" "yes,no"
144 (const (if_then_else (symbol_ref "TARGET_FMOVD")
145 (const_string "yes") (const_string "no"))))
147 (define_attr "issues" "1,2"
148 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
150 ;; cbranch conditional branch instructions
151 ;; jump unconditional jumps
152 ;; arith ordinary arithmetic
153 ;; arith3 a compound insn that behaves similarly to a sequence of
154 ;; three insns of type arith
155 ;; arith3b like above, but might end with a redirected branch
157 ;; load_si Likewise, SImode variant for general register.
159 ;; move register to register
160 ;; fmove register to register, floating point
161 ;; smpy word precision integer multiply
162 ;; dmpy longword or doublelongword precision integer multiply
164 ;; pload load of pr reg, which can't be put into delay slot of rts
165 ;; prset copy register to pr reg, ditto
166 ;; pstore store of pr reg, which can't be put into delay slot of jsr
167 ;; prget copy pr to register, ditto
168 ;; pcload pc relative load of constant value
169 ;; pcload_si Likewise, SImode variant for general register.
170 ;; rte return from exception
171 ;; sfunc special function call with known used registers
172 ;; call function call
174 ;; fdiv floating point divide (or square root)
175 ;; gp_fpul move between general purpose register and fpul
176 ;; dfp_arith, dfp_cmp,dfp_conv
177 ;; dfdiv double precision floating point divide (or square root)
178 ;; nil no-op move, will be deleted.
181 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
182 (const_string "other"))
184 ;; Indicate what precision must be selected in fpscr for this insn, if any.
186 (define_attr "fp_mode" "single,double,none" (const_string "none"))
188 ; If a conditional branch destination is within -252..258 bytes away
189 ; from the instruction it can be 2 bytes long. Something in the
190 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
191 ; branches are initially assumed to be 16 bytes long.
192 ; In machine_dependent_reorg, we split all branches that are longer than
195 ;; The maximum range used for SImode constant pool entries is 1018. A final
196 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
197 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
198 ;; instruction around the pool table, 2 bytes of alignment before the table,
199 ;; and 30 bytes of alignment after the table. That gives a maximum total
200 ;; pool size of 1058 bytes.
201 ;; Worst case code/pool content size ratio is 1:2 (using asms).
202 ;; Thus, in the worst case, there is one instruction in front of a maximum
203 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
204 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
205 ;; If we have a forward branch, the initial table will be put after the
206 ;; unconditional branch.
208 ;; ??? We could do much better by keeping track of the actual pcloads within
209 ;; the branch range and in the pcload range in front of the branch range.
211 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
213 (define_attr "short_cbranch_p" "no,yes"
214 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
216 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
218 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
220 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
222 ] (const_string "no")))
224 (define_attr "med_branch_p" "no,yes"
225 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
228 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
230 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
233 ] (const_string "no")))
235 (define_attr "med_cbranch_p" "no,yes"
236 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
239 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
241 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
244 ] (const_string "no")))
246 (define_attr "braf_branch_p" "no,yes"
247 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
249 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
252 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
254 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
257 ] (const_string "no")))
259 (define_attr "braf_cbranch_p" "no,yes"
260 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
262 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
265 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
267 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
270 ] (const_string "no")))
272 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
273 ; For wider ranges, we need a combination of a code and a data part.
274 ; If we can get a scratch register for a long range jump, the code
275 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
276 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
277 ; long; otherwise, it must be 6 bytes long.
279 ; All other instructions are two bytes long by default.
281 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
282 ;; but getattrtab doesn't understand this.
283 (define_attr "length" ""
284 (cond [(eq_attr "type" "cbranch")
285 (cond [(eq_attr "short_cbranch_p" "yes")
287 (eq_attr "med_cbranch_p" "yes")
289 (eq_attr "braf_cbranch_p" "yes")
291 ;; ??? using pc is not computed transitively.
292 (ne (match_dup 0) (match_dup 0))
294 (ne (symbol_ref ("flag_pic")) (const_int 0))
297 (eq_attr "type" "jump")
298 (cond [(eq_attr "med_branch_p" "yes")
300 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
302 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
303 (symbol_ref "code_for_indirect_jump_scratch")))
304 (if_then_else (eq_attr "braf_branch_p" "yes")
307 (eq_attr "braf_branch_p" "yes")
309 ;; ??? using pc is not computed transitively.
310 (ne (match_dup 0) (match_dup 0))
312 (ne (symbol_ref ("flag_pic")) (const_int 0))
317 ;; (define_function_unit {name} {num-units} {n-users} {test}
318 ;; {ready-delay} {issue-delay} [{conflict-list}])
320 ;; Load and store instructions save a cycle if they are aligned on a
321 ;; four byte boundary. Using a function unit for stores encourages
322 ;; gcc to separate load and store instructions by one instruction,
323 ;; which makes it more likely that the linker will be able to word
324 ;; align them when relaxing.
326 ;; Loads have a latency of two.
327 ;; However, call insns can have a delay slot, so that we want one more
328 ;; insn to be scheduled between the load of the function address and the call.
329 ;; This is equivalent to a latency of three.
330 ;; We cannot use a conflict list for this, because we need to distinguish
331 ;; between the actual call address and the function arguments.
332 ;; ADJUST_COST can only properly handle reductions of the cost, so we
333 ;; use a latency of three here.
334 ;; We only do this for SImode loads of general registers, to make the work
335 ;; for ADJUST_COST easier.
336 (define_function_unit "memory" 1 0
337 (and (eq_attr "issues" "1")
338 (eq_attr "type" "load_si,pcload_si"))
340 (define_function_unit "memory" 1 0
341 (and (eq_attr "issues" "1")
342 (eq_attr "type" "load,pcload,pload,store,pstore"))
345 (define_function_unit "int" 1 0
346 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
348 (define_function_unit "int" 1 0
349 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
351 (define_function_unit "int" 1 0
352 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
354 ;; ??? These are approximations.
355 (define_function_unit "mpy" 1 0
356 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
357 (define_function_unit "mpy" 1 0
358 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
360 (define_function_unit "fp" 1 0
361 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
362 (define_function_unit "fp" 1 0
363 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
367 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
368 ;; costs by at least two.
369 ;; There will be single increments of the modeled that don't correspond
370 ;; to the actual target ;; whenever two insns to be issued depend one a
371 ;; single resource, and the scheduler picks to be the first one.
372 ;; If we multiplied the costs just by two, just two of these single
373 ;; increments would amount to an actual cycle. By picking a larger
374 ;; factor, we can ameliorate the effect; However, we then have to make sure
375 ;; that only two insns are modeled as issued per actual cycle.
376 ;; Moreover, we need a way to specify the latency of insns that don't
377 ;; use an actual function unit.
378 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
380 (define_function_unit "issue" 2 0
381 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
384 (define_function_unit "issue" 2 0
385 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
388 ;; There is no point in providing exact scheduling information about branches,
389 ;; because they are at the starts / ends of basic blocks anyways.
391 ;; Some insns cannot be issued before/after another insn in the same cycle,
392 ;; irrespective of the type of the other insn.
394 ;; default is dual-issue, but can't be paired with an insn that
395 ;; uses multiple function units.
396 (define_function_unit "single_issue" 1 0
397 (and (eq_attr "issues" "2")
398 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
400 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
402 (define_function_unit "single_issue" 1 0
403 (and (eq_attr "issues" "2")
404 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
408 ;; arith3 insns are always pairable at the start, but not inecessarily at
409 ;; the end; however, there doesn;t seem to be a way to express that.
410 (define_function_unit "single_issue" 1 0
411 (and (eq_attr "issues" "2")
412 (eq_attr "type" "arith3"))
416 ;; arith3b insn are pairable at the end and have latency that prevents pairing
417 ;; with the following branch, but we don't want this latency be respected;
418 ;; When the following branch is immediately adjacent, we can redirect the
419 ;; internal branch, which is likly to be a larger win.
420 (define_function_unit "single_issue" 1 0
421 (and (eq_attr "issues" "2")
422 (eq_attr "type" "arith3b"))
426 ;; calls introduce a longisch delay that is likely to flush the pipelines.
427 (define_function_unit "single_issue" 1 0
428 (and (eq_attr "issues" "2")
429 (eq_attr "type" "call,sfunc"))
431 [(eq_attr "type" "!call") (eq_attr "type" "call")])
433 ;; Load and store instructions have no alignment peculiarities for the SH4,
434 ;; but they use the load-store unit, which they share with the fmove type
435 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
436 ;; Loads have a latency of two.
437 ;; However, call insns can only paired with a preceding insn, and have
438 ;; a delay slot, so that we want two more insns to be scheduled between the
439 ;; load of the function address and the call. This is equivalent to a
441 ;; We cannot use a conflict list for this, because we need to distinguish
442 ;; between the actual call address and the function arguments.
443 ;; ADJUST_COST can only properly handle reductions of the cost, so we
444 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
445 ;; We only do this for SImode loads of general registers, to make the work
446 ;; for ADJUST_COST easier.
448 ;; When specifying different latencies for different insns using the
449 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
450 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
451 ;; for an executing insn E and a candidate insn C.
452 ;; Therefore, we define three different function units for load_store:
453 ;; load_store, load and load_si.
455 (define_function_unit "load_si" 1 0
456 (and (eq_attr "issues" "2")
457 (eq_attr "type" "load_si,pcload_si")) 30 10)
458 (define_function_unit "load" 1 0
459 (and (eq_attr "issues" "2")
460 (eq_attr "type" "load,pcload,pload")) 20 10)
461 (define_function_unit "load_store" 1 0
462 (and (eq_attr "issues" "2")
463 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
466 (define_function_unit "int" 1 0
467 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
469 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
470 ;; spurious FIFO constraint; the multiply instructions use the "int"
471 ;; unit actually only for two cycles.
472 (define_function_unit "int" 1 0
473 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
475 ;; We use a fictous "mpy" unit to express the actual latency.
476 (define_function_unit "mpy" 1 0
477 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
479 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
480 ;; spurious FIFO constraint.
481 (define_function_unit "int" 1 0
482 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
484 ;; We use a fictous "gp_fpul" unit to express the actual latency.
485 (define_function_unit "gp_fpul" 1 0
486 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
488 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
489 ;; Thus, a simple single-precision fp operation could finish if issued in
490 ;; the very next cycle, but stalls when issued two or three cycles later.
491 ;; Similarily, a divide / sqrt can work without stalls if issued in
492 ;; the very next cycle, while it would have to block if issued two or
493 ;; three cycles later.
494 ;; There is no way to model this with gcc's function units. This problem is
495 ;; actually mentioned in md.texi. Tackling this problem requires first that
496 ;; it is possible to speak about the target in an open discussion.
498 ;; However, simple double-precision operations always conflict.
500 (define_function_unit "fp" 1 0
501 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
502 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
504 ;; The "fp" unit is for pipeline stages F1 and F2.
506 (define_function_unit "fp" 1 0
507 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
509 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
510 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
512 (define_function_unit "fp" 1 0
513 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
515 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
516 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
517 ;; We also use it to give the actual latency here.
518 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
519 ;; but that will hardly matter in practice for scheduling.
520 (define_function_unit "fdiv" 1 0
521 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
523 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
524 ;; that we can't express.
526 (define_function_unit "fp" 1 0
527 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
529 (define_function_unit "fp" 1 0
530 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
532 (define_function_unit "fp" 1 0
533 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
535 (define_function_unit "fdiv" 1 0
536 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
538 ; Definitions for filling branch delay slots.
540 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
542 ;; ??? This should be (nil) instead of (const_int 0)
543 (define_attr "hit_stack" "yes,no"
544 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
547 (const_string "yes")))
549 (define_attr "interrupt_function" "no,yes"
550 (const (symbol_ref "current_function_interrupt")))
552 (define_attr "in_delay_slot" "yes,no"
553 (cond [(eq_attr "type" "cbranch") (const_string "no")
554 (eq_attr "type" "pcload,pcload_si") (const_string "no")
555 (eq_attr "needs_delay_slot" "yes") (const_string "no")
556 (eq_attr "length" "2") (const_string "yes")
557 ] (const_string "no")))
559 (define_attr "is_sfunc" ""
560 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
563 (eq_attr "needs_delay_slot" "yes")
564 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
566 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
567 ;; and thus we can't put a pop instruction in its delay slot.
568 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
569 ;; instruction can go in the delay slot.
571 ;; Since a normal return (rts) implicitly uses the PR register,
572 ;; we can't allow PR register loads in an rts delay slot.
575 (eq_attr "type" "return")
576 [(and (eq_attr "in_delay_slot" "yes")
577 (ior (and (eq_attr "interrupt_function" "no")
578 (eq_attr "type" "!pload,prset"))
579 (and (eq_attr "interrupt_function" "yes")
581 (ne (symbol_ref "TARGET_SH3") (const_int 0))
582 (eq_attr "hit_stack" "no"))))) (nil) (nil)])
584 ;; Since a call implicitly uses the PR register, we can't allow
585 ;; a PR register store in a jsr delay slot.
588 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
589 [(and (eq_attr "in_delay_slot" "yes")
590 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
592 ;; Say that we have annulled true branches, since this gives smaller and
593 ;; faster code when branches are predicted as not taken.
596 (and (eq_attr "type" "cbranch")
597 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
598 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
600 ;; -------------------------------------------------------------------------
601 ;; SImode signed integer comparisons
602 ;; -------------------------------------------------------------------------
606 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
607 (match_operand:SI 1 "arith_operand" "L,r"))
612 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
613 ;; That would still allow reload to create cmpi instructions, but would
614 ;; perhaps allow forcing the constant into a register when that is better.
615 ;; Probably should use r0 for mem/imm compares, but force constant into a
616 ;; register for pseudo/imm compares.
618 (define_insn "cmpeqsi_t"
620 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
621 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
628 (define_insn "cmpgtsi_t"
630 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
631 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
637 (define_insn "cmpgesi_t"
639 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
640 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
646 ;; -------------------------------------------------------------------------
647 ;; SImode unsigned integer comparisons
648 ;; -------------------------------------------------------------------------
650 (define_insn "cmpgeusi_t"
652 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
653 (match_operand:SI 1 "arith_reg_operand" "r")))]
657 (define_insn "cmpgtusi_t"
659 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
660 (match_operand:SI 1 "arith_reg_operand" "r")))]
664 ;; We save the compare operands in the cmpxx patterns and use them when
665 ;; we generate the branch.
667 (define_expand "cmpsi"
669 (compare (match_operand:SI 0 "arith_operand" "")
670 (match_operand:SI 1 "arith_operand" "")))]
674 sh_compare_op0 = operands[0];
675 sh_compare_op1 = operands[1];
679 ;; -------------------------------------------------------------------------
680 ;; DImode signed integer comparisons
681 ;; -------------------------------------------------------------------------
683 ;; ??? Could get better scheduling by splitting the initial test from the
684 ;; rest of the insn after reload. However, the gain would hardly justify
685 ;; the sh.md size increase necessary to do that.
689 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
690 (match_operand:DI 1 "arith_operand" "r"))
693 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
695 [(set_attr "length" "6")
696 (set_attr "type" "arith3b")])
698 (define_insn "cmpeqdi_t"
700 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
701 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
704 tst %S0,%S0\;bf %,Ldi%=\;tst %R0,%R0\\n%,Ldi%=:
705 cmp/eq %S1,%S0\;bf %,Ldi%=\;cmp/eq %R1,%R0\\n%,Ldi%=:"
706 [(set_attr "length" "6")
707 (set_attr "type" "arith3b")])
711 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
712 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
713 ;; If we applied this split when not optimizing, it would only be
714 ;; applied during the machine-dependent reorg, when no new basic blocks
716 "reload_completed && optimize"
717 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
718 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
719 (label_ref (match_dup 6))
721 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
726 = gen_rtx_REG (SImode,
727 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
729 = (operands[1] == const0_rtx
731 : gen_rtx_REG (SImode,
732 true_regnum (operands[1])
733 + (TARGET_LITTLE_ENDIAN ? 1 : 0)));
734 operands[4] = gen_lowpart (SImode, operands[0]);
735 operands[5] = gen_lowpart (SImode, operands[1]);
736 operands[6] = gen_label_rtx ();
739 (define_insn "cmpgtdi_t"
741 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
742 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
745 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
746 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
747 [(set_attr "length" "8")
748 (set_attr "type" "arith3")])
750 (define_insn "cmpgedi_t"
752 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
753 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
756 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
758 [(set_attr "length" "8,2")
759 (set_attr "type" "arith3,arith")])
761 ;; -------------------------------------------------------------------------
762 ;; DImode unsigned integer comparisons
763 ;; -------------------------------------------------------------------------
765 (define_insn "cmpgeudi_t"
767 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
768 (match_operand:DI 1 "arith_reg_operand" "r")))]
770 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
771 [(set_attr "length" "8")
772 (set_attr "type" "arith3")])
774 (define_insn "cmpgtudi_t"
776 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
777 (match_operand:DI 1 "arith_reg_operand" "r")))]
779 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
780 [(set_attr "length" "8")
781 (set_attr "type" "arith3")])
783 ;; We save the compare operands in the cmpxx patterns and use them when
784 ;; we generate the branch.
786 (define_expand "cmpdi"
788 (compare (match_operand:DI 0 "arith_operand" "")
789 (match_operand:DI 1 "arith_operand" "")))]
793 sh_compare_op0 = operands[0];
794 sh_compare_op1 = operands[1];
798 ;; -------------------------------------------------------------------------
799 ;; Addition instructions
800 ;; -------------------------------------------------------------------------
802 ;; ??? This should be a define expand.
804 (define_insn "adddi3"
805 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
806 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
807 (match_operand:DI 2 "arith_reg_operand" "r")))
808 (clobber (reg:SI T_REG))]
811 [(set_attr "length" "6")])
814 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
815 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
816 (match_operand:DI 2 "arith_reg_operand" "r")))
817 (clobber (reg:SI T_REG))]
822 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
823 high0 = gen_rtx_REG (SImode,
824 true_regnum (operands[0])
825 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
826 high2 = gen_rtx_REG (SImode,
827 true_regnum (operands[2])
828 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
829 emit_insn (gen_clrt ());
830 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
831 emit_insn (gen_addc1 (high0, high0, high2));
836 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
837 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
838 (match_operand:SI 2 "arith_reg_operand" "r"))
841 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
844 [(set_attr "type" "arith")])
847 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
848 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
849 (match_operand:SI 2 "arith_reg_operand" "r"))
851 (clobber (reg:SI T_REG))]
854 [(set_attr "type" "arith")])
856 (define_insn "addsi3"
857 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
858 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
859 (match_operand:SI 2 "arith_operand" "rI")))]
862 [(set_attr "type" "arith")])
864 ;; -------------------------------------------------------------------------
865 ;; Subtraction instructions
866 ;; -------------------------------------------------------------------------
868 ;; ??? This should be a define expand.
870 (define_insn "subdi3"
871 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
872 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
873 (match_operand:DI 2 "arith_reg_operand" "r")))
874 (clobber (reg:SI T_REG))]
877 [(set_attr "length" "6")])
880 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
881 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
882 (match_operand:DI 2 "arith_reg_operand" "r")))
883 (clobber (reg:SI T_REG))]
888 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
889 high0 = gen_rtx_REG (SImode,
890 true_regnum (operands[0])
891 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
892 high2 = gen_rtx_REG (SImode,
893 true_regnum (operands[2])
894 + (TARGET_LITTLE_ENDIAN ? 1 : 0));
895 emit_insn (gen_clrt ());
896 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
897 emit_insn (gen_subc1 (high0, high0, high2));
902 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
903 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
904 (match_operand:SI 2 "arith_reg_operand" "r"))
907 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
910 [(set_attr "type" "arith")])
913 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
914 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
915 (match_operand:SI 2 "arith_reg_operand" "r"))
917 (clobber (reg:SI T_REG))]
920 [(set_attr "type" "arith")])
922 (define_insn "*subsi3_internal"
923 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
924 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
925 (match_operand:SI 2 "arith_reg_operand" "r")))]
928 [(set_attr "type" "arith")])
930 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
931 ;; will sometimes save one instruction. Otherwise we might get
932 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
935 (define_expand "subsi3"
936 [(set (match_operand:SI 0 "arith_reg_operand" "")
937 (minus:SI (match_operand:SI 1 "arith_operand" "")
938 (match_operand:SI 2 "arith_reg_operand" "")))]
942 if (GET_CODE (operands[1]) == CONST_INT)
944 emit_insn (gen_negsi2 (operands[0], operands[2]));
945 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
950 ;; -------------------------------------------------------------------------
951 ;; Division instructions
952 ;; -------------------------------------------------------------------------
954 ;; We take advantage of the library routines which don't clobber as many
955 ;; registers as a normal function call would.
957 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
958 ;; also has an effect on the register that holds the address of the sfunc.
959 ;; To make this work, we have an extra dummy insns that shows the use
960 ;; of this register for reorg.
962 (define_insn "use_sfunc_addr"
963 [(set (reg:SI PR_REG)
964 (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
967 [(set_attr "length" "0")])
969 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
970 ;; hard register 0. If we used hard register 0, then the next instruction
971 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
972 ;; gets allocated to a stack slot that needs its address reloaded, then
973 ;; there is nothing to prevent reload from using r0 to reload the address.
974 ;; This reload would clobber the value in r0 we are trying to store.
975 ;; If we let reload allocate r0, then this problem can never happen.
977 (define_insn "udivsi3_i1"
978 [(set (match_operand:SI 0 "register_operand" "=z")
979 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
980 (clobber (reg:SI T_REG))
981 (clobber (reg:SI PR_REG))
982 (clobber (reg:SI R4_REG))
983 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
986 [(set_attr "type" "sfunc")
987 (set_attr "needs_delay_slot" "yes")])
989 (define_insn "udivsi3_i4"
990 [(set (match_operand:SI 0 "register_operand" "=y")
991 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
992 (clobber (reg:SI T_REG))
993 (clobber (reg:SI PR_REG))
994 (clobber (reg:DF DR0_REG))
995 (clobber (reg:DF DR2_REG))
996 (clobber (reg:DF DR4_REG))
997 (clobber (reg:SI R0_REG))
998 (clobber (reg:SI R1_REG))
999 (clobber (reg:SI R4_REG))
1000 (clobber (reg:SI R5_REG))
1001 (use (reg:PSI FPSCR_REG))
1002 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1003 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1005 [(set_attr "type" "sfunc")
1006 (set_attr "fp_mode" "double")
1007 (set_attr "needs_delay_slot" "yes")])
1009 (define_insn "udivsi3_i4_single"
1010 [(set (match_operand:SI 0 "register_operand" "=y")
1011 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1012 (clobber (reg:SI T_REG))
1013 (clobber (reg:SI PR_REG))
1014 (clobber (reg:DF DR0_REG))
1015 (clobber (reg:DF DR2_REG))
1016 (clobber (reg:DF DR4_REG))
1017 (clobber (reg:SI R0_REG))
1018 (clobber (reg:SI R1_REG))
1019 (clobber (reg:SI R4_REG))
1020 (clobber (reg:SI R5_REG))
1021 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1022 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1024 [(set_attr "type" "sfunc")
1025 (set_attr "needs_delay_slot" "yes")])
1027 (define_expand "udivsi3"
1028 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
1029 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1030 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1031 (parallel [(set (match_operand:SI 0 "register_operand" "")
1032 (udiv:SI (reg:SI R4_REG)
1034 (clobber (reg:SI T_REG))
1035 (clobber (reg:SI PR_REG))
1036 (clobber (reg:SI R4_REG))
1037 (use (match_dup 3))])]
1043 operands[3] = gen_reg_rtx(SImode);
1044 /* Emit the move of the address to a pseudo outside of the libcall. */
1045 if (TARGET_HARD_SH4 && TARGET_SH3E)
1047 emit_move_insn (operands[3],
1048 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
1049 if (TARGET_FPU_SINGLE)
1050 last = gen_udivsi3_i4_single (operands[0], operands[3]);
1052 last = gen_udivsi3_i4 (operands[0], operands[3]);
1056 emit_move_insn (operands[3],
1057 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
1058 last = gen_udivsi3_i1 (operands[0], operands[3]);
1060 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1061 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1062 last = emit_insn (last);
1063 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1064 invariant code motion can move it. */
1065 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1066 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1070 (define_insn "divsi3_i1"
1071 [(set (match_operand:SI 0 "register_operand" "=z")
1072 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1073 (clobber (reg:SI T_REG))
1074 (clobber (reg:SI PR_REG))
1075 (clobber (reg:SI R1_REG))
1076 (clobber (reg:SI R2_REG))
1077 (clobber (reg:SI R3_REG))
1078 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1081 [(set_attr "type" "sfunc")
1082 (set_attr "needs_delay_slot" "yes")])
1084 (define_insn "divsi3_i4"
1085 [(set (match_operand:SI 0 "register_operand" "=y")
1086 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1087 (clobber (reg:SI PR_REG))
1088 (clobber (reg:DF DR0_REG))
1089 (clobber (reg:DF DR2_REG))
1090 (use (reg:PSI FPSCR_REG))
1091 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1092 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
1094 [(set_attr "type" "sfunc")
1095 (set_attr "fp_mode" "double")
1096 (set_attr "needs_delay_slot" "yes")])
1098 (define_insn "divsi3_i4_single"
1099 [(set (match_operand:SI 0 "register_operand" "=y")
1100 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1101 (clobber (reg:SI PR_REG))
1102 (clobber (reg:DF DR0_REG))
1103 (clobber (reg:DF DR2_REG))
1104 (clobber (reg:SI R2_REG))
1105 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1106 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
1108 [(set_attr "type" "sfunc")
1109 (set_attr "needs_delay_slot" "yes")])
1111 (define_expand "divsi3"
1112 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
1113 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1114 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1115 (parallel [(set (match_operand:SI 0 "register_operand" "")
1116 (div:SI (reg:SI R4_REG)
1118 (clobber (reg:SI T_REG))
1119 (clobber (reg:SI PR_REG))
1120 (clobber (reg:SI R1_REG))
1121 (clobber (reg:SI R2_REG))
1122 (clobber (reg:SI R3_REG))
1123 (use (match_dup 3))])]
1129 operands[3] = gen_reg_rtx(SImode);
1130 /* Emit the move of the address to a pseudo outside of the libcall. */
1131 if (TARGET_HARD_SH4 && TARGET_SH3E)
1133 emit_move_insn (operands[3],
1134 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
1135 if (TARGET_FPU_SINGLE)
1136 last = gen_divsi3_i4_single (operands[0], operands[3]);
1138 last = gen_divsi3_i4 (operands[0], operands[3]);
1142 emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
1143 last = gen_divsi3_i1 (operands[0], operands[3]);
1145 first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1146 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
1147 last = emit_insn (last);
1148 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1149 invariant code motion can move it. */
1150 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1151 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1155 ;; -------------------------------------------------------------------------
1156 ;; Multiplication instructions
1157 ;; -------------------------------------------------------------------------
1159 (define_insn "umulhisi3_i"
1160 [(set (reg:SI MACL_REG)
1161 (mult:SI (zero_extend:SI
1162 (match_operand:HI 0 "arith_reg_operand" "r"))
1164 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1167 [(set_attr "type" "smpy")])
1169 (define_insn "mulhisi3_i"
1170 [(set (reg:SI MACL_REG)
1171 (mult:SI (sign_extend:SI
1172 (match_operand:HI 0 "arith_reg_operand" "r"))
1174 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1177 [(set_attr "type" "smpy")])
1179 (define_expand "mulhisi3"
1180 [(set (reg:SI MACL_REG)
1181 (mult:SI (sign_extend:SI
1182 (match_operand:HI 1 "arith_reg_operand" ""))
1184 (match_operand:HI 2 "arith_reg_operand" ""))))
1185 (set (match_operand:SI 0 "arith_reg_operand" "")
1192 first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
1193 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1194 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1195 invariant code motion can move it. */
1196 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1197 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1201 (define_expand "umulhisi3"
1202 [(set (reg:SI MACL_REG)
1203 (mult:SI (zero_extend:SI
1204 (match_operand:HI 1 "arith_reg_operand" ""))
1206 (match_operand:HI 2 "arith_reg_operand" ""))))
1207 (set (match_operand:SI 0 "arith_reg_operand" "")
1214 first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
1215 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
1216 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1217 invariant code motion can move it. */
1218 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1219 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1223 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1224 ;; a call to a routine which clobbers known registers.
1227 [(set (match_operand:SI 1 "register_operand" "=z")
1228 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
1229 (clobber (reg:SI MACL_REG))
1230 (clobber (reg:SI T_REG))
1231 (clobber (reg:SI PR_REG))
1232 (clobber (reg:SI R3_REG))
1233 (clobber (reg:SI R2_REG))
1234 (clobber (reg:SI R1_REG))
1235 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1238 [(set_attr "type" "sfunc")
1239 (set_attr "needs_delay_slot" "yes")])
1241 (define_expand "mulsi3_call"
1242 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
1243 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
1244 (parallel[(set (match_operand:SI 0 "register_operand" "")
1245 (mult:SI (reg:SI R4_REG)
1247 (clobber (reg:SI MACL_REG))
1248 (clobber (reg:SI T_REG))
1249 (clobber (reg:SI PR_REG))
1250 (clobber (reg:SI R3_REG))
1251 (clobber (reg:SI R2_REG))
1252 (clobber (reg:SI R1_REG))
1253 (use (match_operand:SI 3 "register_operand" ""))])]
1257 (define_insn "mul_l"
1258 [(set (reg:SI MACL_REG)
1259 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1260 (match_operand:SI 1 "arith_reg_operand" "r")))]
1263 [(set_attr "type" "dmpy")])
1265 (define_expand "mulsi3"
1266 [(set (reg:SI MACL_REG)
1267 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1268 (match_operand:SI 2 "arith_reg_operand" "")))
1269 (set (match_operand:SI 0 "arith_reg_operand" "")
1278 /* The address must be set outside the libcall,
1279 since it goes into a pseudo. */
1280 rtx sym = gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\");
1281 rtx addr = force_reg (SImode, sym);
1282 rtx insns = gen_mulsi3_call (operands[0], operands[1],
1284 first = XVECEXP (insns, 0, 0);
1285 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1290 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1292 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1293 /* consec_sets_giv can only recognize the first insn that sets a
1294 giv as the giv insn. So we must tag this also with a REG_EQUAL
1296 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1298 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1299 invariant code motion can move it. */
1300 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1301 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1305 (define_insn "mulsidi3_i"
1306 [(set (reg:SI MACH_REG)
1310 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1311 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1313 (set (reg:SI MACL_REG)
1314 (mult:SI (match_dup 0)
1318 [(set_attr "type" "dmpy")])
1320 (define_insn "mulsidi3"
1321 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1323 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1324 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1325 (clobber (reg:SI MACH_REG))
1326 (clobber (reg:SI MACL_REG))]
1331 [(set (match_operand:DI 0 "arith_reg_operand" "")
1333 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1334 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1335 (clobber (reg:SI MACH_REG))
1336 (clobber (reg:SI MACL_REG))]
1341 rtx low_dst = gen_lowpart (SImode, operands[0]);
1342 rtx high_dst = gen_highpart (SImode, operands[0]);
1344 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1346 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1347 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1348 /* We need something to tag the possible REG_EQUAL notes on to. */
1349 emit_move_insn (operands[0], operands[0]);
1353 (define_insn "umulsidi3_i"
1354 [(set (reg:SI MACH_REG)
1358 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1359 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1361 (set (reg:SI MACL_REG)
1362 (mult:SI (match_dup 0)
1366 [(set_attr "type" "dmpy")])
1368 (define_insn "umulsidi3"
1369 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1371 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
1372 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
1373 (clobber (reg:SI MACH_REG))
1374 (clobber (reg:SI MACL_REG))]
1379 [(set (match_operand:DI 0 "arith_reg_operand" "")
1380 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1381 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1382 (clobber (reg:SI MACH_REG))
1383 (clobber (reg:SI MACL_REG))]
1388 rtx low_dst = gen_lowpart (SImode, operands[0]);
1389 rtx high_dst = gen_highpart (SImode, operands[0]);
1391 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1393 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
1394 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
1395 /* We need something to tag the possible REG_EQUAL notes on to. */
1396 emit_move_insn (operands[0], operands[0]);
1400 (define_insn "smulsi3_highpart_i"
1401 [(set (reg:SI MACH_REG)
1405 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1406 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1408 (clobber (reg:SI MACL_REG))]
1411 [(set_attr "type" "dmpy")])
1413 (define_expand "smulsi3_highpart"
1415 [(set (reg:SI MACH_REG)
1419 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1420 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1422 (clobber (reg:SI MACL_REG))])
1423 (set (match_operand:SI 0 "arith_reg_operand" "")
1430 first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
1431 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1432 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1433 invariant code motion can move it. */
1434 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1435 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1436 /* expand_binop can't find a suitable code in mul_highpart_optab to
1437 make a REG_EQUAL note from, so make one here.
1438 ??? Alternatively, we could put this at the calling site of expand_binop,
1439 i.e. expand_mult_highpart. */
1441 = gen_rtx_EXPR_LIST (REG_EQUAL, copy_rtx (SET_SRC (single_set (first))),
1446 (define_insn "umulsi3_highpart_i"
1447 [(set (reg:SI MACH_REG)
1451 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1452 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1454 (clobber (reg:SI MACL_REG))]
1457 [(set_attr "type" "dmpy")])
1459 (define_expand "umulsi3_highpart"
1461 [(set (reg:SI MACH_REG)
1465 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1466 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1468 (clobber (reg:SI MACL_REG))])
1469 (set (match_operand:SI 0 "arith_reg_operand" "")
1476 first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
1477 last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
1478 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1479 invariant code motion can move it. */
1480 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1481 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1485 ;; -------------------------------------------------------------------------
1486 ;; Logical operations
1487 ;; -------------------------------------------------------------------------
1490 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1491 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1492 (match_operand:SI 2 "logical_operand" "r,L")))]
1495 [(set_attr "type" "arith")])
1497 ;; If the constant is 255, then emit a extu.b instruction instead of an
1498 ;; and, since that will give better code.
1500 (define_expand "andsi3"
1501 [(set (match_operand:SI 0 "arith_reg_operand" "")
1502 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1503 (match_operand:SI 2 "logical_operand" "")))]
1507 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1509 emit_insn (gen_zero_extendqisi2 (operands[0],
1510 gen_lowpart (QImode, operands[1])));
1515 (define_insn "iorsi3"
1516 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1517 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1518 (match_operand:SI 2 "logical_operand" "r,L")))]
1521 [(set_attr "type" "arith")])
1523 (define_insn "xorsi3"
1524 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1525 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1526 (match_operand:SI 2 "logical_operand" "L,r")))]
1529 [(set_attr "type" "arith")])
1531 ;; -------------------------------------------------------------------------
1532 ;; Shifts and rotates
1533 ;; -------------------------------------------------------------------------
1535 (define_insn "rotlsi3_1"
1536 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1537 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1540 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1543 [(set_attr "type" "arith")])
1545 (define_insn "rotlsi3_31"
1546 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1547 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1549 (clobber (reg:SI T_REG))]
1552 [(set_attr "type" "arith")])
1554 (define_insn "rotlsi3_16"
1555 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1556 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1560 [(set_attr "type" "arith")])
1562 (define_expand "rotlsi3"
1563 [(set (match_operand:SI 0 "arith_reg_operand" "")
1564 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1565 (match_operand:SI 2 "immediate_operand" "")))]
1569 static char rot_tab[] = {
1570 000, 000, 000, 000, 000, 000, 010, 001,
1571 001, 001, 011, 013, 003, 003, 003, 003,
1572 003, 003, 003, 003, 003, 013, 012, 002,
1573 002, 002, 010, 000, 000, 000, 000, 000,
1578 if (GET_CODE (operands[2]) != CONST_INT)
1580 count = INTVAL (operands[2]);
1581 choice = rot_tab[count];
1582 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1588 emit_move_insn (operands[0], operands[1]);
1589 count -= (count & 16) * 2;
1592 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1599 parts[0] = gen_reg_rtx (SImode);
1600 parts[1] = gen_reg_rtx (SImode);
1601 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1602 parts[choice-1] = operands[1];
1603 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1604 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1605 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1606 count = (count & ~16) - 8;
1610 for (; count > 0; count--)
1611 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1612 for (; count < 0; count++)
1613 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1618 (define_insn "*rotlhi3_8"
1619 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1620 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1624 [(set_attr "type" "arith")])
1626 (define_expand "rotlhi3"
1627 [(set (match_operand:HI 0 "arith_reg_operand" "")
1628 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1629 (match_operand:HI 2 "immediate_operand" "")))]
1633 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1640 ;; This pattern is used by init_expmed for computing the costs of shift
1643 (define_insn_and_split "ashlsi3_std"
1644 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r,r,r")
1645 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0,0,0")
1646 (match_operand:SI 2 "nonmemory_operand" "r,M,K,?ri")))
1647 (clobber (match_scratch:SI 3 "=X,X,X,&r"))]
1649 || (GET_CODE (operands[2]) == CONST_INT
1650 && CONST_OK_FOR_K (INTVAL (operands[2])))"
1658 && GET_CODE (operands[2]) == CONST_INT
1659 && ! CONST_OK_FOR_K (INTVAL (operands[2]))"
1660 [(set (match_dup 3) (match_dup 2))
1662 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 3)))
1663 (clobber (match_dup 4))])]
1664 "operands[4] = gen_rtx_SCRATCH (SImode);"
1665 [(set_attr "length" "*,*,*,4")
1666 (set_attr "type" "dyn_shift,arith,arith,arith")])
1668 (define_insn "ashlhi3_k"
1669 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1670 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1671 (match_operand:HI 2 "const_int_operand" "M,K")))]
1672 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1676 [(set_attr "type" "arith")])
1678 (define_insn "ashlsi3_n"
1679 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1680 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1681 (match_operand:SI 2 "const_int_operand" "n")))
1682 (clobber (reg:SI T_REG))]
1683 "! sh_dynamicalize_shift_p (operands[2])"
1685 [(set (attr "length")
1686 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1688 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1690 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1692 (const_string "8")))
1693 (set_attr "type" "arith")])
1696 [(set (match_operand:SI 0 "arith_reg_operand" "")
1697 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1698 (match_operand:SI 2 "const_int_operand" "n")))
1699 (clobber (reg:SI T_REG))]
1701 [(use (reg:SI R0_REG))]
1704 gen_shifty_op (ASHIFT, operands);
1708 (define_expand "ashlsi3"
1709 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1710 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1711 (match_operand:SI 2 "nonmemory_operand" "")))
1712 (clobber (reg:SI T_REG))])]
1716 if (GET_CODE (operands[2]) == CONST_INT
1717 && sh_dynamicalize_shift_p (operands[2]))
1718 operands[2] = force_reg (SImode, operands[2]);
1721 emit_insn (gen_ashlsi3_std (operands[0], operands[1], operands[2]));
1724 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1728 (define_insn "ashlhi3"
1729 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1730 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1731 (match_operand:HI 2 "const_int_operand" "n")))
1732 (clobber (reg:SI T_REG))]
1735 [(set (attr "length")
1736 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1738 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1740 (const_string "6")))
1741 (set_attr "type" "arith")])
1744 [(set (match_operand:HI 0 "arith_reg_operand" "")
1745 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1746 (match_operand:HI 2 "const_int_operand" "n")))
1747 (clobber (reg:SI T_REG))]
1749 [(use (reg:SI R0_REG))]
1752 gen_shifty_hi_op (ASHIFT, operands);
1757 ; arithmetic shift right
1760 (define_insn "ashrsi3_k"
1761 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1762 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1763 (match_operand:SI 2 "const_int_operand" "M")))
1764 (clobber (reg:SI T_REG))]
1765 "INTVAL (operands[2]) == 1"
1767 [(set_attr "type" "arith")])
1769 ;; We can't do HImode right shifts correctly unless we start out with an
1770 ;; explicit zero / sign extension; doing that would result in worse overall
1771 ;; code, so just let the machine independent code widen the mode.
1772 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1775 ;; ??? This should be a define expand.
1777 (define_insn "ashrsi2_16"
1778 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1779 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1783 [(set_attr "length" "4")])
1786 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1787 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1790 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1791 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1792 "operands[2] = gen_lowpart (HImode, operands[0]);")
1794 ;; ??? This should be a define expand.
1796 (define_insn "ashrsi2_31"
1797 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1798 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1800 (clobber (reg:SI T_REG))]
1803 [(set_attr "length" "4")])
1806 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1807 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1809 (clobber (reg:SI T_REG))]
1814 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1815 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1819 (define_insn "ashlsi_c"
1820 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1821 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1823 (lt:SI (match_dup 1) (const_int 0)))]
1826 [(set_attr "type" "arith")])
1828 (define_insn "ashrsi3_d"
1829 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1830 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1831 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1834 [(set_attr "type" "dyn_shift")])
1836 (define_insn "ashrsi3_n"
1837 [(set (reg:SI R4_REG)
1838 (ashiftrt:SI (reg:SI R4_REG)
1839 (match_operand:SI 0 "const_int_operand" "i")))
1840 (clobber (reg:SI T_REG))
1841 (clobber (reg:SI PR_REG))
1842 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1845 [(set_attr "type" "sfunc")
1846 (set_attr "needs_delay_slot" "yes")])
1848 (define_expand "ashrsi3"
1849 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1850 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1851 (match_operand:SI 2 "nonmemory_operand" "")))
1852 (clobber (reg:SI T_REG))])]
1854 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1856 ;; logical shift right
1858 (define_insn "lshrsi3_d"
1859 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1860 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1861 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1864 [(set_attr "type" "dyn_shift")])
1866 ;; Only the single bit shift clobbers the T bit.
1868 (define_insn "lshrsi3_m"
1869 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1870 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1871 (match_operand:SI 2 "const_int_operand" "M")))
1872 (clobber (reg:SI T_REG))]
1873 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1875 [(set_attr "type" "arith")])
1877 (define_insn "lshrsi3_k"
1878 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1879 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1880 (match_operand:SI 2 "const_int_operand" "K")))]
1881 "CONST_OK_FOR_K (INTVAL (operands[2]))
1882 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1884 [(set_attr "type" "arith")])
1886 (define_insn "lshrsi3_n"
1887 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1888 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1889 (match_operand:SI 2 "const_int_operand" "n")))
1890 (clobber (reg:SI T_REG))]
1891 "! sh_dynamicalize_shift_p (operands[2])"
1893 [(set (attr "length")
1894 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1896 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1898 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1900 (const_string "8")))
1901 (set_attr "type" "arith")])
1904 [(set (match_operand:SI 0 "arith_reg_operand" "")
1905 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1906 (match_operand:SI 2 "const_int_operand" "n")))
1907 (clobber (reg:SI T_REG))]
1909 [(use (reg:SI R0_REG))]
1912 gen_shifty_op (LSHIFTRT, operands);
1916 (define_expand "lshrsi3"
1917 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1918 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1919 (match_operand:SI 2 "nonmemory_operand" "")))
1920 (clobber (reg:SI T_REG))])]
1924 if (GET_CODE (operands[2]) == CONST_INT
1925 && sh_dynamicalize_shift_p (operands[2]))
1926 operands[2] = force_reg (SImode, operands[2]);
1927 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1929 rtx count = copy_to_mode_reg (SImode, operands[2]);
1930 emit_insn (gen_negsi2 (count, count));
1931 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1934 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1938 ;; ??? This should be a define expand.
1940 (define_insn "ashldi3_k"
1941 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1942 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1944 (clobber (reg:SI T_REG))]
1946 "shll %R0\;rotcl %S0"
1947 [(set_attr "length" "4")
1948 (set_attr "type" "arith")])
1950 (define_expand "ashldi3"
1951 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1952 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1953 (match_operand:DI 2 "immediate_operand" "")))
1954 (clobber (reg:SI T_REG))])]
1956 "{ if (GET_CODE (operands[2]) != CONST_INT
1957 || INTVAL (operands[2]) != 1) FAIL;} ")
1959 ;; ??? This should be a define expand.
1961 (define_insn "lshrdi3_k"
1962 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1963 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1965 (clobber (reg:SI T_REG))]
1967 "shlr %S0\;rotcr %R0"
1968 [(set_attr "length" "4")
1969 (set_attr "type" "arith")])
1971 (define_expand "lshrdi3"
1972 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1973 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1974 (match_operand:DI 2 "immediate_operand" "")))
1975 (clobber (reg:SI T_REG))])]
1977 "{ if (GET_CODE (operands[2]) != CONST_INT
1978 || INTVAL (operands[2]) != 1) FAIL;} ")
1980 ;; ??? This should be a define expand.
1982 (define_insn "ashrdi3_k"
1983 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1984 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1986 (clobber (reg:SI T_REG))]
1988 "shar %S0\;rotcr %R0"
1989 [(set_attr "length" "4")
1990 (set_attr "type" "arith")])
1992 (define_expand "ashrdi3"
1993 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1994 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1995 (match_operand:DI 2 "immediate_operand" "")))
1996 (clobber (reg:SI T_REG))])]
1998 "{ if (GET_CODE (operands[2]) != CONST_INT
1999 || INTVAL (operands[2]) != 1) FAIL; } ")
2001 ;; combined left/right shift
2004 [(set (match_operand:SI 0 "register_operand" "")
2005 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2006 (match_operand:SI 2 "const_int_operand" "n"))
2007 (match_operand:SI 3 "const_int_operand" "n")))]
2008 "(unsigned)INTVAL (operands[2]) < 32"
2009 [(use (reg:SI R0_REG))]
2010 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2014 [(set (match_operand:SI 0 "register_operand" "")
2015 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2016 (match_operand:SI 2 "const_int_operand" "n"))
2017 (match_operand:SI 3 "const_int_operand" "n")))
2018 (clobber (reg:SI T_REG))]
2019 "(unsigned)INTVAL (operands[2]) < 32"
2020 [(use (reg:SI R0_REG))]
2021 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
2025 [(set (match_operand:SI 0 "register_operand" "=r")
2026 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2027 (match_operand:SI 2 "const_int_operand" "n"))
2028 (match_operand:SI 3 "const_int_operand" "n")))
2029 (clobber (reg:SI T_REG))]
2030 "shl_and_kind (operands[2], operands[3], 0) == 1"
2032 [(set (attr "length")
2033 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2035 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2037 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2039 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
2041 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
2043 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
2045 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
2046 (const_string "16")]
2047 (const_string "18")))
2048 (set_attr "type" "arith")])
2051 [(set (match_operand:SI 0 "register_operand" "=z")
2052 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2053 (match_operand:SI 2 "const_int_operand" "n"))
2054 (match_operand:SI 3 "const_int_operand" "n")))
2055 (clobber (reg:SI T_REG))]
2056 "shl_and_kind (operands[2], operands[3], 0) == 2"
2058 [(set (attr "length")
2059 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
2061 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
2063 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
2065 (const_string "10")))
2066 (set_attr "type" "arith")])
2068 ;; shift left / and combination with a scratch register: The combine pass
2069 ;; does not accept the individual instructions, even though they are
2070 ;; cheap. But it needs a precise description so that it is usable after
2072 (define_insn "and_shl_scratch"
2073 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2077 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2078 (match_operand:SI 2 "const_int_operand" "N,n"))
2079 (match_operand:SI 3 "" "0,r"))
2080 (match_operand:SI 4 "const_int_operand" "n,n"))
2081 (match_operand:SI 5 "const_int_operand" "n,n")))
2082 (clobber (reg:SI T_REG))]
2085 [(set (attr "length")
2086 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
2088 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
2090 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
2092 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
2093 (const_string "10")]
2094 (const_string "12")))
2095 (set_attr "type" "arith")])
2098 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2102 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
2103 (match_operand:SI 2 "const_int_operand" "N,n"))
2104 (match_operand:SI 3 "register_operand" "0,r"))
2105 (match_operand:SI 4 "const_int_operand" "n,n"))
2106 (match_operand:SI 5 "const_int_operand" "n,n")))
2107 (clobber (reg:SI T_REG))]
2109 [(use (reg:SI R0_REG))]
2112 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
2114 if (INTVAL (operands[2]))
2116 gen_shifty_op (LSHIFTRT, operands);
2118 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
2119 operands[2] = operands[4];
2120 gen_shifty_op (ASHIFT, operands);
2121 if (INTVAL (operands[5]))
2123 operands[2] = operands[5];
2124 gen_shifty_op (LSHIFTRT, operands);
2129 ;; signed left/right shift combination.
2131 [(set (match_operand:SI 0 "register_operand" "=r")
2133 (ashift:SI (match_operand:SI 1 "register_operand" "r")
2134 (match_operand:SI 2 "const_int_operand" "n"))
2135 (match_operand:SI 3 "const_int_operand" "n")
2137 (clobber (reg:SI T_REG))]
2139 [(use (reg:SI R0_REG))]
2140 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
2143 (define_insn "shl_sext_ext"
2144 [(set (match_operand:SI 0 "register_operand" "=r")
2146 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2147 (match_operand:SI 2 "const_int_operand" "n"))
2148 (match_operand:SI 3 "const_int_operand" "n")
2150 (clobber (reg:SI T_REG))]
2151 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
2153 [(set (attr "length")
2154 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
2156 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
2158 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2160 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2162 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2164 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2166 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
2168 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
2169 (const_string "16")]
2170 (const_string "18")))
2171 (set_attr "type" "arith")])
2173 (define_insn "shl_sext_sub"
2174 [(set (match_operand:SI 0 "register_operand" "=z")
2176 (ashift:SI (match_operand:SI 1 "register_operand" "0")
2177 (match_operand:SI 2 "const_int_operand" "n"))
2178 (match_operand:SI 3 "const_int_operand" "n")
2180 (clobber (reg:SI T_REG))]
2181 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
2183 [(set (attr "length")
2184 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
2186 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
2188 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
2190 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
2191 (const_string "12")]
2192 (const_string "14")))
2193 (set_attr "type" "arith")])
2195 ;; These patterns are found in expansions of DImode shifts by 16, and
2196 ;; allow the xtrct instruction to be generated from C source.
2198 (define_insn "xtrct_left"
2199 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2200 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
2202 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
2206 [(set_attr "type" "arith")])
2208 (define_insn "xtrct_right"
2209 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2210 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
2212 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
2216 [(set_attr "type" "arith")])
2218 ;; -------------------------------------------------------------------------
2220 ;; -------------------------------------------------------------------------
2223 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2224 (neg:SI (plus:SI (reg:SI T_REG)
2225 (match_operand:SI 1 "arith_reg_operand" "r"))))
2227 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
2231 [(set_attr "type" "arith")])
2233 (define_expand "negdi2"
2234 [(set (match_operand:DI 0 "arith_reg_operand" "")
2235 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
2236 (clobber (reg:SI T_REG))]
2240 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
2241 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
2243 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
2244 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
2246 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
2247 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
2249 emit_insn (gen_clrt ());
2250 emit_insn (gen_negc (low_dst, low_src));
2251 emit_insn (gen_negc (high_dst, high_src));
2255 (define_insn "negsi2"
2256 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2257 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2260 [(set_attr "type" "arith")])
2262 (define_insn "one_cmplsi2"
2263 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2264 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2267 [(set_attr "type" "arith")])
2269 ;; -------------------------------------------------------------------------
2270 ;; Zero extension instructions
2271 ;; -------------------------------------------------------------------------
2273 (define_insn "zero_extendhisi2"
2274 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2275 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2278 [(set_attr "type" "arith")])
2280 (define_insn "zero_extendqisi2"
2281 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2282 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2285 [(set_attr "type" "arith")])
2287 (define_insn "zero_extendqihi2"
2288 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2289 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2292 [(set_attr "type" "arith")])
2294 ;; -------------------------------------------------------------------------
2295 ;; Sign extension instructions
2296 ;; -------------------------------------------------------------------------
2298 ;; ??? This should be a define expand.
2299 ;; ??? Or perhaps it should be dropped?
2301 /* There is no point in defining extendsidi2; convert_move generates good
2304 (define_insn "extendhisi2"
2305 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2306 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2311 [(set_attr "type" "arith,load")])
2313 (define_insn "extendqisi2"
2314 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2315 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2320 [(set_attr "type" "arith,load")])
2322 (define_insn "extendqihi2"
2323 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2324 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2329 [(set_attr "type" "arith,load")])
2331 ;; -------------------------------------------------------------------------
2332 ;; Move instructions
2333 ;; -------------------------------------------------------------------------
2335 ;; define push and pop so it is easy for sh.c
2337 (define_expand "push"
2338 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2339 (match_operand:SI 0 "register_operand" "r,l,x"))]
2343 (define_expand "pop"
2344 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2345 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2349 (define_expand "push_e"
2350 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
2351 (match_operand:SF 0 "" ""))
2352 (use (reg:PSI FPSCR_REG))
2353 (clobber (scratch:SI))])]
2357 (define_insn "push_fpul"
2358 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
2361 [(set_attr "type" "store")
2362 (set_attr "hit_stack" "yes")])
2364 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2366 (define_expand "push_4"
2367 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
2368 (match_operand:DF 0 "" ""))
2369 (use (reg:PSI FPSCR_REG))
2370 (clobber (scratch:SI))])]
2374 (define_expand "pop_e"
2375 [(parallel [(set (match_operand:SF 0 "" "")
2376 (mem:SF (post_inc:SI (reg:SI SP_REG))))
2377 (use (reg:PSI FPSCR_REG))
2378 (clobber (scratch:SI))])]
2382 (define_insn "pop_fpul"
2383 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
2386 [(set_attr "type" "load")
2387 (set_attr "hit_stack" "yes")])
2389 (define_expand "pop_4"
2390 [(parallel [(set (match_operand:DF 0 "" "")
2391 (mem:DF (post_inc:SI (reg:SI SP_REG))))
2392 (use (reg:PSI FPSCR_REG))
2393 (clobber (scratch:SI))])]
2397 ;; These two patterns can happen as the result of optimization, when
2398 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2399 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2402 [(set (reg:SI T_REG) (const_int 0))]
2407 [(set (reg:SI T_REG) (const_int 1))]
2411 ;; t/r must come after r/r, lest reload will try to reload stuff like
2412 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
2413 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
2414 (define_insn "movsi_i"
2415 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
2416 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
2419 && (register_operand (operands[0], SImode)
2420 || register_operand (operands[1], SImode))"
2437 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,pcload_si")
2438 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
2440 ;; t/r must come after r/r, lest reload will try to reload stuff like
2441 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2442 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2443 ;; will require a reload.
2444 (define_insn "movsi_ie"
2445 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,y")
2446 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y"))]
2448 && (register_operand (operands[0], SImode)
2449 || register_operand (operands[1], SImode))"
2470 ! move optimized away"
2471 [(set_attr "type" "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,gp_fpul,nil")
2472 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2474 (define_insn "movsi_i_lowpart"
2475 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
2476 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,x,l,t,r,i"))]
2477 "register_operand (operands[0], SImode)
2478 || register_operand (operands[1], SImode)"
2488 [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
2490 (define_expand "movsi"
2491 [(set (match_operand:SI 0 "general_movdst_operand" "")
2492 (match_operand:SI 1 "general_movsrc_operand" ""))]
2494 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2496 (define_expand "ic_invalidate_line"
2497 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2498 (match_dup 1)] UNSPEC_ICACHE)
2499 (clobber (scratch:SI))])]
2503 operands[0] = force_reg (Pmode, operands[0]);
2504 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2507 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2508 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2509 ;; the requirement *1*00 for associative address writes. The alignment of
2510 ;; %0 implies that its least significant bit is cleared,
2511 ;; thus we clear the V bit of a matching entry if there is one.
2512 (define_insn "ic_invalidate_line_i"
2513 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2514 (match_operand:SI 1 "register_operand" "r")]
2516 (clobber (match_scratch:SI 2 "=&r"))]
2518 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2519 [(set_attr "length" "8")])
2521 (define_insn "movqi_i"
2522 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2523 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2524 "arith_reg_operand (operands[0], QImode)
2525 || arith_reg_operand (operands[1], QImode)"
2533 [(set_attr "type" "move,load,store,move,move,move")])
2535 (define_expand "movqi"
2536 [(set (match_operand:QI 0 "general_operand" "")
2537 (match_operand:QI 1 "general_operand" ""))]
2539 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2541 (define_insn "movhi_i"
2542 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2543 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2544 "arith_reg_operand (operands[0], HImode)
2545 || arith_reg_operand (operands[1], HImode)"
2555 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2557 (define_expand "movhi"
2558 [(set (match_operand:HI 0 "general_movdst_operand" "")
2559 (match_operand:HI 1 "general_movsrc_operand" ""))]
2561 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2563 ;; ??? This should be a define expand.
2565 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2566 ;; compiled with -m2 -ml -O3 -funroll-loops
2568 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2569 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2570 "arith_reg_operand (operands[0], DImode)
2571 || arith_reg_operand (operands[1], DImode)"
2572 "* return output_movedouble (insn, operands, DImode);"
2573 [(set_attr "length" "4")
2574 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2576 ;; If the output is a register and the input is memory or a register, we have
2577 ;; to be careful and see which word needs to be loaded first.
2580 [(set (match_operand:DI 0 "general_movdst_operand" "")
2581 (match_operand:DI 1 "general_movsrc_operand" ""))]
2583 [(set (match_dup 2) (match_dup 3))
2584 (set (match_dup 4) (match_dup 5))]
2589 if ((GET_CODE (operands[0]) == MEM
2590 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2591 || (GET_CODE (operands[1]) == MEM
2592 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2595 if (GET_CODE (operands[0]) == REG)
2596 regno = REGNO (operands[0]);
2597 else if (GET_CODE (operands[0]) == SUBREG)
2598 regno = subreg_regno (operands[0]);
2599 else if (GET_CODE (operands[0]) == MEM)
2603 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2605 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2606 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2607 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2608 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2612 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2613 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2614 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2615 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2618 if (operands[2] == 0 || operands[3] == 0
2619 || operands[4] == 0 || operands[5] == 0)
2623 (define_expand "movdi"
2624 [(set (match_operand:DI 0 "general_movdst_operand" "")
2625 (match_operand:DI 1 "general_movsrc_operand" ""))]
2627 "{ if (prepare_move_operands (operands, DImode)) DONE; }")
2629 ;; ??? This should be a define expand.
2631 (define_insn "movdf_k"
2632 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2633 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2634 "(! TARGET_SH4 || reload_completed
2635 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2636 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
2637 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
2638 && (arith_reg_operand (operands[0], DFmode)
2639 || arith_reg_operand (operands[1], DFmode))"
2640 "* return output_movedouble (insn, operands, DFmode);"
2641 [(set_attr "length" "4")
2642 (set_attr "type" "move,pcload,load,store")])
2644 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2645 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2646 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2647 ;; the d/m/c/X alternative, which is split later into single-precision
2648 ;; instructions. And when not optimizing, no splits are done before fixing
2649 ;; up pcloads, so we need usable length information for that.
2650 (define_insn "movdf_i4"
2651 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2652 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2653 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2654 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2656 && (arith_reg_operand (operands[0], DFmode)
2657 || arith_reg_operand (operands[1], DFmode))"
2669 [(set_attr_alternative "length"
2670 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2672 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2673 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2674 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2676 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2677 (const_int 8) (const_int 8)])
2678 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")
2679 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
2680 (const_string "double")
2681 (const_string "none")))])
2683 ;; Moving DFmode between fp/general registers through memory
2684 ;; (the top of the stack) is faster than moving through fpul even for
2685 ;; little endian. Because the type of an instruction is important for its
2686 ;; scheduling, it is beneficial to split these operations, rather than
2687 ;; emitting them in one single chunk, even if this will expose a stack
2688 ;; use that will prevent scheduling of other stack accesses beyond this
2691 [(set (match_operand:DF 0 "register_operand" "")
2692 (match_operand:DF 1 "register_operand" ""))
2693 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2694 (clobber (match_scratch:SI 3 "=X"))]
2695 "TARGET_SH4 && reload_completed
2696 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2702 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2703 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2704 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2705 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2706 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2707 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2711 ;; local-alloc sometimes allocates scratch registers even when not required,
2712 ;; so we must be prepared to handle these.
2714 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2716 [(set (match_operand:DF 0 "general_movdst_operand" "")
2717 (match_operand:DF 1 "general_movsrc_operand" ""))
2718 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2719 (clobber (match_scratch:SI 3 "X"))]
2722 && true_regnum (operands[0]) < 16
2723 && true_regnum (operands[1]) < 16"
2724 [(set (match_dup 0) (match_dup 1))]
2727 /* If this was a reg <-> mem operation with base + index reg addressing,
2728 we have to handle this in a special way. */
2729 rtx mem = operands[0];
2731 if (! memory_operand (mem, DFmode))
2736 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
2737 mem = SUBREG_REG (mem);
2738 if (GET_CODE (mem) == MEM)
2740 rtx addr = XEXP (mem, 0);
2741 if (GET_CODE (addr) == PLUS
2742 && GET_CODE (XEXP (addr, 0)) == REG
2743 && GET_CODE (XEXP (addr, 1)) == REG)
2746 rtx reg0 = gen_rtx (REG, Pmode, 0);
2747 rtx regop = operands[store_p], word0 ,word1;
2749 if (GET_CODE (regop) == SUBREG)
2750 regop = alter_subreg (regop);
2751 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2755 mem = copy_rtx (mem);
2756 PUT_MODE (mem, SImode);
2757 word0 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 0));
2758 word1 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 4));
2759 if (store_p || ! refers_to_regno_p (REGNO (word0),
2760 REGNO (word0) + 1, addr, 0))
2763 ? gen_movsi_ie (mem, word0)
2764 : gen_movsi_ie (word0, mem));
2765 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2766 mem = copy_rtx (mem);
2768 ? gen_movsi_ie (mem, word1)
2769 : gen_movsi_ie (word1, mem));
2770 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2774 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2775 emit_insn (gen_movsi_ie (word1, mem));
2776 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2777 mem = copy_rtx (mem);
2778 emit_insn (gen_movsi_ie (word0, mem));
2785 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2787 [(set (match_operand:DF 0 "register_operand" "")
2788 (match_operand:DF 1 "memory_operand" ""))
2789 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2790 (clobber (reg:SI R0_REG))]
2791 "TARGET_SH4 && reload_completed"
2792 [(parallel [(set (match_dup 0) (match_dup 1))
2794 (clobber (scratch:SI))])]
2797 (define_expand "reload_indf"
2798 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2799 (match_operand:DF 1 "immediate_operand" "FQ"))
2800 (use (reg:PSI FPSCR_REG))
2801 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2805 (define_expand "reload_outdf"
2806 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2807 (match_operand:DF 1 "register_operand" "af,r"))
2808 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2812 ;; Simplify no-op moves.
2814 [(set (match_operand:SF 0 "register_operand" "")
2815 (match_operand:SF 1 "register_operand" ""))
2816 (use (match_operand:PSI 2 "fpscr_operand" ""))
2817 (clobber (match_scratch:SI 3 "X"))]
2818 "TARGET_SH3E && reload_completed
2819 && true_regnum (operands[0]) == true_regnum (operands[1])"
2820 [(set (match_dup 0) (match_dup 0))]
2823 ;; fmovd substitute post-reload splits
2825 [(set (match_operand:DF 0 "register_operand" "")
2826 (match_operand:DF 1 "register_operand" ""))
2827 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2828 (clobber (match_scratch:SI 3 "X"))]
2829 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2830 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2831 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2835 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2836 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2837 gen_rtx (REG, SFmode, src), operands[2]));
2838 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2839 gen_rtx (REG, SFmode, src + 1), operands[2]));
2844 [(set (match_operand:DF 0 "register_operand" "")
2845 (mem:DF (match_operand:SI 1 "register_operand" "")))
2846 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2847 (clobber (match_scratch:SI 3 "X"))]
2848 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2849 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
2850 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2854 int regno = true_regnum (operands[0]);
2856 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2858 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2859 regno + !! TARGET_LITTLE_ENDIAN),
2860 mem2, operands[2]));
2861 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2862 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2863 regno + ! TARGET_LITTLE_ENDIAN),
2864 gen_rtx (MEM, SFmode, operands[1]),
2870 [(set (match_operand:DF 0 "register_operand" "")
2871 (match_operand:DF 1 "memory_operand" ""))
2872 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2873 (clobber (match_scratch:SI 3 "X"))]
2874 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2875 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
2879 int regno = true_regnum (operands[0]);
2880 rtx addr, insn, adjust = NULL_RTX;
2881 rtx mem2 = copy_rtx (operands[1]);
2882 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2883 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2885 PUT_MODE (mem2, SFmode);
2886 operands[1] = copy_rtx (mem2);
2887 addr = XEXP (mem2, 0);
2888 if (GET_CODE (addr) != POST_INC)
2890 /* If we have to modify the stack pointer, the value that we have
2891 read with post-increment might be modified by an interrupt,
2892 so write it back. */
2893 if (REGNO (addr) == STACK_POINTER_REGNUM)
2894 adjust = gen_push_e (reg0);
2896 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2897 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2899 addr = XEXP (addr, 0);
2900 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2901 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2902 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2906 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2911 [(set (match_operand:DF 0 "memory_operand" "")
2912 (match_operand:DF 1 "register_operand" ""))
2913 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2914 (clobber (match_scratch:SI 3 "X"))]
2915 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2916 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
2920 int regno = true_regnum (operands[1]);
2921 rtx insn, addr, adjust = NULL_RTX;
2923 operands[0] = copy_rtx (operands[0]);
2924 PUT_MODE (operands[0], SFmode);
2925 insn = emit_insn (gen_movsf_ie (operands[0],
2926 gen_rtx (REG, SFmode,
2927 regno + ! TARGET_LITTLE_ENDIAN),
2929 operands[0] = copy_rtx (operands[0]);
2930 addr = XEXP (operands[0], 0);
2931 if (GET_CODE (addr) != PRE_DEC)
2933 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2934 emit_insn_before (adjust, insn);
2935 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2937 addr = XEXP (addr, 0);
2939 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2940 insn = emit_insn (gen_movsf_ie (operands[0],
2941 gen_rtx (REG, SFmode,
2942 regno + !! TARGET_LITTLE_ENDIAN),
2944 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2948 ;; If the output is a register and the input is memory or a register, we have
2949 ;; to be careful and see which word needs to be loaded first.
2952 [(set (match_operand:DF 0 "general_movdst_operand" "")
2953 (match_operand:DF 1 "general_movsrc_operand" ""))]
2955 [(set (match_dup 2) (match_dup 3))
2956 (set (match_dup 4) (match_dup 5))]
2961 if ((GET_CODE (operands[0]) == MEM
2962 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2963 || (GET_CODE (operands[1]) == MEM
2964 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2967 if (GET_CODE (operands[0]) == REG)
2968 regno = REGNO (operands[0]);
2969 else if (GET_CODE (operands[0]) == SUBREG)
2970 regno = subreg_regno (operands[0]);
2971 else if (GET_CODE (operands[0]) == MEM)
2975 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2977 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2978 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2979 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2980 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2984 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2985 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2986 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2987 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2990 if (operands[2] == 0 || operands[3] == 0
2991 || operands[4] == 0 || operands[5] == 0)
2995 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2996 ;; used only once, let combine add in the index again.
2999 [(set (match_operand:SI 0 "register_operand" "")
3000 (match_operand:SI 1 "" ""))
3001 (clobber (match_operand 2 "register_operand" ""))]
3002 "! reload_in_progress && ! reload_completed"
3003 [(use (reg:SI R0_REG))]
3006 rtx addr, reg, const_int;
3008 if (GET_CODE (operands[1]) != MEM)
3010 addr = XEXP (operands[1], 0);
3011 if (GET_CODE (addr) != PLUS)
3013 reg = XEXP (addr, 0);
3014 const_int = XEXP (addr, 1);
3015 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3016 && GET_CODE (const_int) == CONST_INT))
3018 emit_move_insn (operands[2], const_int);
3019 emit_move_insn (operands[0],
3020 change_address (operands[1], VOIDmode,
3021 gen_rtx_PLUS (SImode, reg, operands[2])));
3026 [(set (match_operand:SI 1 "" "")
3027 (match_operand:SI 0 "register_operand" ""))
3028 (clobber (match_operand 2 "register_operand" ""))]
3029 "! reload_in_progress && ! reload_completed"
3030 [(use (reg:SI R0_REG))]
3033 rtx addr, reg, const_int;
3035 if (GET_CODE (operands[1]) != MEM)
3037 addr = XEXP (operands[1], 0);
3038 if (GET_CODE (addr) != PLUS)
3040 reg = XEXP (addr, 0);
3041 const_int = XEXP (addr, 1);
3042 if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
3043 && GET_CODE (const_int) == CONST_INT))
3045 emit_move_insn (operands[2], const_int);
3046 emit_move_insn (change_address (operands[1], VOIDmode,
3047 gen_rtx_PLUS (SImode, reg, operands[2])),
3052 (define_expand "movdf"
3053 [(set (match_operand:DF 0 "general_movdst_operand" "")
3054 (match_operand:DF 1 "general_movsrc_operand" ""))]
3058 if (prepare_move_operands (operands, DFmode)) DONE;
3061 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
3067 (define_insn "movsf_i"
3068 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
3069 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
3072 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
3073 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
3074 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
3075 && (arith_reg_operand (operands[0], SFmode)
3076 || arith_reg_operand (operands[1], SFmode))"
3085 [(set_attr "type" "move,move,pcload,load,store,move,move")])
3087 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
3088 ;; update_flow_info would not know where to put REG_EQUAL notes
3089 ;; when the destination changes mode.
3090 (define_insn "movsf_ie"
3091 [(set (match_operand:SF 0 "general_movdst_operand"
3092 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
3093 (match_operand:SF 1 "general_movsrc_operand"
3094 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
3095 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
3096 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
3099 && (arith_reg_operand (operands[0], SFmode)
3100 || arith_reg_operand (operands[1], SFmode)
3101 || arith_reg_operand (operands[3], SImode)
3102 || (fpul_operand (operands[0], SFmode)
3103 && memory_operand (operands[1], SFmode)
3104 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3105 || (fpul_operand (operands[1], SFmode)
3106 && memory_operand (operands[0], SFmode)
3107 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))"
3127 ! move optimized away"
3128 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,store,load,nil")
3129 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,2,2,0")
3130 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
3131 (const_string "single")
3132 (const_string "none")))])
3135 [(set (match_operand:SF 0 "register_operand" "")
3136 (match_operand:SF 1 "register_operand" ""))
3137 (use (match_operand:PSI 2 "fpscr_operand" "c"))
3138 (clobber (reg:SI FPUL_REG))]
3140 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
3142 (clobber (scratch:SI))])
3143 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
3145 (clobber (scratch:SI))])]
3148 (define_expand "movsf"
3149 [(set (match_operand:SF 0 "general_movdst_operand" "")
3150 (match_operand:SF 1 "general_movsrc_operand" ""))]
3154 if (prepare_move_operands (operands, SFmode))
3158 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
3163 (define_insn "mov_nop"
3164 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
3167 [(set_attr "length" "0")
3168 (set_attr "type" "nil")])
3170 (define_expand "reload_insf"
3171 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
3172 (match_operand:SF 1 "immediate_operand" "FQ"))
3173 (use (reg:PSI FPSCR_REG))
3174 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3178 (define_expand "reload_insi"
3179 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
3180 (match_operand:SF 1 "immediate_operand" "FQ"))
3181 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
3185 (define_insn "*movsi_y"
3186 [(set (match_operand:SI 0 "register_operand" "=y,y")
3187 (match_operand:SI 1 "immediate_operand" "Qi,I"))
3188 (clobber (match_scratch:SI 2 "=&z,r"))]
3190 && (reload_in_progress || reload_completed)"
3192 [(set_attr "length" "4")
3193 (set_attr "type" "pcload,move")])
3196 [(set (match_operand:SI 0 "register_operand" "")
3197 (match_operand:SI 1 "immediate_operand" ""))
3198 (clobber (match_operand:SI 2 "register_operand" ""))]
3200 [(set (match_dup 2) (match_dup 1))
3201 (set (match_dup 0) (match_dup 2))]
3205 [(set (match_operand:SI 0 "register_operand" "")
3206 (match_operand:SI 1 "memory_operand" ""))
3207 (clobber (reg:SI R0_REG))]
3209 [(set (match_dup 0) (match_dup 1))]
3212 ;; ------------------------------------------------------------------------
3213 ;; Define the real conditional branch instructions.
3214 ;; ------------------------------------------------------------------------
3216 (define_insn "branch_true"
3217 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
3218 (label_ref (match_operand 0 "" ""))
3221 "* return output_branch (1, insn, operands);"
3222 [(set_attr "type" "cbranch")])
3224 (define_insn "branch_false"
3225 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
3226 (label_ref (match_operand 0 "" ""))
3229 "* return output_branch (0, insn, operands);"
3230 [(set_attr "type" "cbranch")])
3232 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
3233 ;; which destination is too far away.
3234 ;; The const_int_operand is distinct for each branch target; it avoids
3235 ;; unwanted matches with redundant_insn.
3236 (define_insn "block_branch_redirect"
3237 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
3240 [(set_attr "length" "0")])
3242 ;; This one has the additional purpose to record a possible scratch register
3243 ;; for the following branch.
3244 (define_insn "indirect_jump_scratch"
3245 [(set (match_operand 0 "register_operand" "=r")
3246 (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
3249 [(set_attr "length" "0")])
3251 ;; Conditional branch insns
3253 (define_expand "beq"
3255 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3256 (label_ref (match_operand 0 "" ""))
3259 "from_compare (operands, EQ);")
3261 (define_expand "bne"
3263 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3264 (label_ref (match_operand 0 "" ""))
3267 "from_compare (operands, EQ);")
3269 (define_expand "bgt"
3271 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3272 (label_ref (match_operand 0 "" ""))
3275 "from_compare (operands, GT);")
3277 (define_expand "blt"
3279 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3280 (label_ref (match_operand 0 "" ""))
3285 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3287 rtx tmp = sh_compare_op0;
3288 sh_compare_op0 = sh_compare_op1;
3289 sh_compare_op1 = tmp;
3290 emit_insn (gen_bgt (operands[0]));
3293 from_compare (operands, GE);
3296 (define_expand "ble"
3298 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3299 (label_ref (match_operand 0 "" ""))
3306 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3308 rtx tmp = sh_compare_op0;
3309 sh_compare_op0 = sh_compare_op1;
3310 sh_compare_op1 = tmp;
3311 emit_insn (gen_bge (operands[0]));
3314 from_compare (operands, GT);
3317 (define_expand "bge"
3319 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3320 (label_ref (match_operand 0 "" ""))
3327 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3329 rtx tmp = sh_compare_op0;
3330 sh_compare_op0 = sh_compare_op1;
3331 sh_compare_op1 = tmp;
3332 emit_insn (gen_ble (operands[0]));
3335 from_compare (operands, GE);
3338 (define_expand "bgtu"
3340 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3341 (label_ref (match_operand 0 "" ""))
3344 "from_compare (operands, GTU); ")
3346 (define_expand "bltu"
3348 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3349 (label_ref (match_operand 0 "" ""))
3352 "from_compare (operands, GEU);")
3354 (define_expand "bgeu"
3356 (if_then_else (ne (reg:SI T_REG) (const_int 0))
3357 (label_ref (match_operand 0 "" ""))
3360 "from_compare (operands, GEU);")
3362 (define_expand "bleu"
3364 (if_then_else (eq (reg:SI T_REG) (const_int 0))
3365 (label_ref (match_operand 0 "" ""))
3368 "from_compare (operands, GTU);")
3370 ;; ------------------------------------------------------------------------
3371 ;; Jump and linkage insns
3372 ;; ------------------------------------------------------------------------
3376 (label_ref (match_operand 0 "" "")))]
3380 /* The length is 16 if the delay slot is unfilled. */
3381 if (get_attr_length(insn) > 4)
3382 return output_far_jump(insn, operands[0]);
3384 return \"bra %l0%#\";
3386 [(set_attr "type" "jump")
3387 (set_attr "needs_delay_slot" "yes")])
3389 (define_insn "calli"
3390 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3391 (match_operand 1 "" ""))
3392 (use (reg:PSI FPSCR_REG))
3393 (clobber (reg:SI PR_REG))]
3396 [(set_attr "type" "call")
3397 (set (attr "fp_mode")
3398 (if_then_else (eq_attr "fpu_single" "yes")
3399 (const_string "single") (const_string "double")))
3400 (set_attr "needs_delay_slot" "yes")])
3402 ;; This is a pc-rel call, using bsrf, for use with PIC.
3404 (define_insn "calli_pcrel"
3405 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3406 (match_operand 1 "" ""))
3407 (use (reg:PSI FPSCR_REG))
3408 (use (reg:SI PIC_REG))
3409 (use (match_operand 2 "" ""))
3410 (clobber (reg:SI PR_REG))]
3413 [(set_attr "type" "call")
3414 (set (attr "fp_mode")
3415 (if_then_else (eq_attr "fpu_single" "yes")
3416 (const_string "single") (const_string "double")))
3417 (set_attr "needs_delay_slot" "yes")])
3419 (define_insn_and_split "call_pcrel"
3420 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3421 (match_operand 1 "" ""))
3422 (use (reg:PSI FPSCR_REG))
3423 (use (reg:SI PIC_REG))
3424 (clobber (reg:SI PR_REG))
3425 (clobber (match_scratch:SI 2 "=r"))]
3432 rtx lab = gen_call_site ();
3434 if (SYMBOL_REF_FLAG (operands[0]))
3435 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3437 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
3438 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], lab));
3441 [(set_attr "type" "call")
3442 (set (attr "fp_mode")
3443 (if_then_else (eq_attr "fpu_single" "yes")
3444 (const_string "single") (const_string "double")))
3445 (set_attr "needs_delay_slot" "yes")])
3447 (define_insn "call_valuei"
3448 [(set (match_operand 0 "" "=rf")
3449 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3450 (match_operand 2 "" "")))
3451 (use (reg:PSI FPSCR_REG))
3452 (clobber (reg:SI PR_REG))]
3455 [(set_attr "type" "call")
3456 (set (attr "fp_mode")
3457 (if_then_else (eq_attr "fpu_single" "yes")
3458 (const_string "single") (const_string "double")))
3459 (set_attr "needs_delay_slot" "yes")])
3461 (define_insn "call_valuei_pcrel"
3462 [(set (match_operand 0 "" "=rf")
3463 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3464 (match_operand 2 "" "")))
3465 (use (reg:PSI FPSCR_REG))
3466 (use (reg:SI PIC_REG))
3467 (use (match_operand 3 "" ""))
3468 (clobber (reg:SI PR_REG))]
3471 [(set_attr "type" "call")
3472 (set (attr "fp_mode")
3473 (if_then_else (eq_attr "fpu_single" "yes")
3474 (const_string "single") (const_string "double")))
3475 (set_attr "needs_delay_slot" "yes")])
3477 (define_insn_and_split "call_value_pcrel"
3478 [(set (match_operand 0 "" "=rf")
3479 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
3480 (match_operand 2 "" "")))
3481 (use (reg:PSI FPSCR_REG))
3482 (use (reg:SI PIC_REG))
3483 (clobber (reg:SI PR_REG))
3484 (clobber (match_scratch:SI 3 "=r"))]
3491 rtx lab = gen_call_site ();
3493 if (SYMBOL_REF_FLAG (operands[1]))
3494 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
3496 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
3497 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
3501 [(set_attr "type" "call")
3502 (set (attr "fp_mode")
3503 (if_then_else (eq_attr "fpu_single" "yes")
3504 (const_string "single") (const_string "double")))
3505 (set_attr "needs_delay_slot" "yes")])
3507 (define_expand "call"
3508 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3509 (match_operand 1 "" ""))
3510 (use (reg:PSI FPSCR_REG))
3511 (clobber (reg:SI PR_REG))])]
3515 if (flag_pic && TARGET_SH2
3516 && GET_CODE (operands[0]) == MEM
3517 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3519 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
3523 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3526 (define_expand "call_value"
3527 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3528 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3529 (match_operand 2 "" "")))
3530 (use (reg:PSI FPSCR_REG))
3531 (clobber (reg:SI PR_REG))])]
3535 if (flag_pic && TARGET_SH2
3536 && GET_CODE (operands[1]) == MEM
3537 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3539 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
3544 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
3547 (define_insn "sibcalli"
3548 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
3549 (match_operand 1 "" ""))
3550 (use (reg:PSI FPSCR_REG))
3554 [(set_attr "needs_delay_slot" "yes")
3555 (set (attr "fp_mode")
3556 (if_then_else (eq_attr "fpu_single" "yes")
3557 (const_string "single") (const_string "double")))
3558 (set_attr "type" "jump_ind")])
3560 (define_insn "sibcalli_pcrel"
3561 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
3562 (match_operand 1 "" ""))
3563 (use (match_operand 2 "" ""))
3564 (use (reg:PSI FPSCR_REG))
3568 [(set_attr "needs_delay_slot" "yes")
3569 (set (attr "fp_mode")
3570 (if_then_else (eq_attr "fpu_single" "yes")
3571 (const_string "single") (const_string "double")))
3572 (set_attr "type" "jump_ind")])
3574 (define_insn_and_split "sibcall_pcrel"
3575 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
3576 (match_operand 1 "" ""))
3577 (use (reg:PSI FPSCR_REG))
3578 (clobber (match_scratch:SI 2 "=k"))
3586 rtx lab = gen_call_site ();
3589 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
3590 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
3592 SIBLING_CALL_P (call_insn) = 1;
3595 [(set_attr "needs_delay_slot" "yes")
3596 (set (attr "fp_mode")
3597 (if_then_else (eq_attr "fpu_single" "yes")
3598 (const_string "single") (const_string "double")))
3599 (set_attr "type" "jump_ind")])
3601 (define_expand "sibcall"
3603 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3604 (match_operand 1 "" ""))
3605 (use (reg:PSI FPSCR_REG))
3610 if (flag_pic && TARGET_SH2
3611 && GET_CODE (operands[0]) == MEM
3612 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3613 /* The PLT needs the PIC register, but the epilogue would have
3614 to restore it, so we can only use PC-relative PIC calls for
3615 static functions. */
3616 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
3618 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
3622 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
3625 (define_expand "sibcall_value"
3626 [(set (match_operand 0 "" "")
3627 (call (match_operand 1 "" "")
3628 (match_operand 2 "" "")))]
3632 emit_call_insn (gen_sibcall (operands[1], operands[2]));
3636 (define_expand "sibcall_epilogue"
3641 sh_expand_epilogue ();
3645 (define_insn "indirect_jump"
3647 (match_operand:SI 0 "arith_reg_operand" "r"))]
3650 [(set_attr "needs_delay_slot" "yes")
3651 (set_attr "type" "jump_ind")])
3653 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3654 ;; which can be present in structured code from indirect jumps which can not
3655 ;; be present in structured code. This allows -fprofile-arcs to work.
3657 ;; For SH1 processors.
3658 (define_insn "casesi_jump_1"
3660 (match_operand:SI 0 "register_operand" "r"))
3661 (use (label_ref (match_operand 1 "" "")))]
3664 [(set_attr "needs_delay_slot" "yes")
3665 (set_attr "type" "jump_ind")])
3667 ;; For all later processors.
3668 (define_insn "casesi_jump_2"
3669 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3670 (label_ref (match_operand 1 "" ""))))
3671 (use (label_ref (match_operand 2 "" "")))]
3673 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
3675 [(set_attr "needs_delay_slot" "yes")
3676 (set_attr "type" "jump_ind")])
3678 ;; Call subroutine returning any type.
3679 ;; ??? This probably doesn't work.
3681 (define_expand "untyped_call"
3682 [(parallel [(call (match_operand 0 "" "")
3684 (match_operand 1 "" "")
3685 (match_operand 2 "" "")])]
3691 emit_call_insn (gen_call (operands[0], const0_rtx));
3693 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3695 rtx set = XVECEXP (operands[2], 0, i);
3696 emit_move_insn (SET_DEST (set), SET_SRC (set));
3699 /* The optimizer does not know that the call sets the function value
3700 registers we stored in the result block. We avoid problems by
3701 claiming that all hard registers are used and clobbered at this
3703 emit_insn (gen_blockage ());
3708 ;; ------------------------------------------------------------------------
3710 ;; ------------------------------------------------------------------------
3713 [(set (reg:SI T_REG)
3714 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3715 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3718 [(set_attr "type" "arith")])
3725 ;; Load address of a label. This is only generated by the casesi expand,
3726 ;; and by machine_dependent_reorg (fixing up fp moves).
3727 ;; This must use unspec, because this only works for labels that are
3731 [(set (reg:SI R0_REG)
3732 (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
3735 [(set_attr "in_delay_slot" "no")
3736 (set_attr "type" "arith")])
3738 ;; machine_dependent_reorg() will make this a `mova'.
3739 (define_insn "mova_const"
3740 [(set (reg:SI R0_REG)
3741 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
3744 [(set_attr "in_delay_slot" "no")
3745 (set_attr "type" "arith")])
3747 (define_expand "GOTaddr2picreg"
3748 [(set (reg:SI R0_REG)
3749 (unspec [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
3751 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
3752 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3755 operands[0] = pic_offset_table_rtx;
3756 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
3760 (define_expand "builtin_setjmp_receiver"
3761 [(match_operand 0 "" "")]
3765 emit_insn (gen_GOTaddr2picreg ());
3769 (define_expand "call_site"
3770 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
3774 static HOST_WIDE_INT i = 0;
3775 operands[0] = GEN_INT (i);
3779 (define_expand "sym_label2reg"
3780 [(set (match_operand:SI 0 "" "")
3782 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC))
3784 (match_operand:SI 2 "" "")
3788 (define_expand "symGOT2reg"
3789 [(set (match_operand:SI 0 "" "")
3790 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_GOT)))
3791 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
3792 (set (match_dup 0) (mem:SI (match_dup 0)))]
3796 operands[2] = pic_offset_table_rtx;
3799 (define_expand "symGOTOFF2reg"
3800 [(set (match_operand:SI 0 "" "")
3801 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
3802 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3806 operands[2] = pic_offset_table_rtx;
3809 (define_expand "symPLT_label2reg"
3810 [(set (match_operand:SI 0 "" "")
3813 (unspec [(match_operand:SI 1 "" "")] UNSPEC_PLT)
3816 (match_operand:SI 2 "" "")
3818 ;; Even though the PIC register is not really used by the call
3819 ;; sequence in which this is expanded, the PLT code assumes the PIC
3820 ;; register is set, so we must not skip its initialization. Since
3821 ;; we only use this expand as part of calling sequences, and never
3822 ;; to take the address of a function, this is the best point to
3823 ;; insert the (use). Using the PLT to take the address of a
3824 ;; function would be wrong, not only because the PLT entry could
3825 ;; then be called from a function that doesn't initialize the PIC
3826 ;; register to the proper GOT, but also because pointers to the
3827 ;; same function might not compare equal, should they be set by
3828 ;; different shared libraries.
3829 (use (reg:SI PIC_REG))]
3833 ;; case instruction for switch statements.
3835 ;; Operand 0 is index
3836 ;; operand 1 is the minimum bound
3837 ;; operand 2 is the maximum bound - minimum bound + 1
3838 ;; operand 3 is CODE_LABEL for the table;
3839 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3841 (define_expand "casesi"
3842 [(match_operand:SI 0 "arith_reg_operand" "")
3843 (match_operand:SI 1 "arith_reg_operand" "")
3844 (match_operand:SI 2 "arith_reg_operand" "")
3845 (match_operand 3 "" "") (match_operand 4 "" "")]
3849 rtx reg = gen_reg_rtx (SImode);
3850 rtx reg2 = gen_reg_rtx (SImode);
3851 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3852 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3853 /* If optimizing, casesi_worker depends on the mode of the instruction
3854 before label it 'uses' - operands[3]. */
3855 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3857 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3859 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3861 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3862 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3863 operands[3], but to lab. We will fix this up in
3864 machine_dependent_reorg. */
3869 (define_expand "casesi_0"
3870 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3871 (set (match_dup 4) (minus:SI (match_dup 4)
3872 (match_operand:SI 1 "arith_operand" "")))
3874 (gtu:SI (match_dup 4)
3875 (match_operand:SI 2 "arith_reg_operand" "")))
3877 (if_then_else (ne (reg:SI T_REG)
3879 (label_ref (match_operand 3 "" ""))
3884 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3885 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3886 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3888 (define_insn "casesi_worker_0"
3889 [(set (match_operand:SI 0 "register_operand" "=r,r")
3890 (unspec:SI [(match_operand 1 "register_operand" "0,r")
3891 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3892 (clobber (match_scratch:SI 3 "=X,1"))
3893 (clobber (match_scratch:SI 4 "=&z,z"))]
3898 [(set (match_operand:SI 0 "register_operand" "")
3899 (unspec [(match_operand 1 "register_operand" "")
3900 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3901 (clobber (match_scratch:SI 3 ""))
3902 (clobber (match_scratch:SI 4 ""))]
3903 "! TARGET_SH2 && reload_completed"
3904 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3905 (parallel [(set (match_dup 0)
3906 (unspec [(reg:SI R0_REG) (match_dup 1)
3907 (label_ref (match_dup 2))] UNSPEC_CASESI))
3908 (clobber (match_dup 3))])
3909 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
3910 "LABEL_NUSES (operands[2])++;")
3913 [(set (match_operand:SI 0 "register_operand" "")
3914 (unspec:SI [(match_operand 1 "register_operand" "")
3915 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3916 (clobber (match_scratch:SI 3 ""))
3917 (clobber (match_scratch:SI 4 ""))]
3918 "TARGET_SH2 && reload_completed"
3919 [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
3920 (parallel [(set (match_dup 0)
3921 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
3922 (label_ref (match_dup 2))] UNSPEC_CASESI))
3923 (clobber (match_dup 3))])]
3924 "LABEL_NUSES (operands[2])++;")
3926 (define_insn "*casesi_worker"
3927 [(set (match_operand:SI 0 "register_operand" "=r,r")
3928 (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
3929 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
3930 (clobber (match_scratch:SI 3 "=X,1"))]
3934 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3936 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3939 switch (GET_MODE (diff_vec))
3942 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3944 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3946 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3947 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3948 return \"mov.b @(r0,%1),%0\";
3953 [(set_attr "length" "4")])
3955 (define_expand "return"
3957 "reload_completed && ! sh_need_epilogue ()"
3960 (define_insn "*return_i"
3964 [(set_attr "type" "return")
3965 (set_attr "needs_delay_slot" "yes")])
3967 (define_expand "prologue"
3970 "sh_expand_prologue (); DONE;")
3972 (define_expand "epilogue"
3975 "sh_expand_epilogue ();")
3977 (define_insn "blockage"
3978 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
3981 [(set_attr "length" "0")])
3983 ;; ------------------------------------------------------------------------
3985 ;; ------------------------------------------------------------------------
3988 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3989 (eq:SI (reg:SI T_REG) (const_int 1)))]
3992 [(set_attr "type" "arith")])
3994 (define_expand "seq"
3995 [(set (match_operand:SI 0 "arith_reg_operand" "")
3998 "operands[1] = prepare_scc_operands (EQ);")
4000 (define_expand "slt"
4001 [(set (match_operand:SI 0 "arith_reg_operand" "")
4004 "operands[1] = prepare_scc_operands (LT);")
4006 (define_expand "sle"
4007 [(match_operand:SI 0 "arith_reg_operand" "")]
4011 rtx tmp = sh_compare_op0;
4012 sh_compare_op0 = sh_compare_op1;
4013 sh_compare_op1 = tmp;
4014 emit_insn (gen_sge (operands[0]));
4018 (define_expand "sgt"
4019 [(set (match_operand:SI 0 "arith_reg_operand" "")
4022 "operands[1] = prepare_scc_operands (GT);")
4024 (define_expand "sge"
4025 [(set (match_operand:SI 0 "arith_reg_operand" "")
4030 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
4034 rtx lab = gen_label_rtx ();
4035 prepare_scc_operands (EQ);
4036 emit_jump_insn (gen_branch_true (lab));
4037 prepare_scc_operands (GT);
4039 emit_insn (gen_movt (operands[0]));
4042 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
4045 operands[1] = prepare_scc_operands (GE);
4048 (define_expand "sgtu"
4049 [(set (match_operand:SI 0 "arith_reg_operand" "")
4052 "operands[1] = prepare_scc_operands (GTU);")
4054 (define_expand "sltu"
4055 [(set (match_operand:SI 0 "arith_reg_operand" "")
4058 "operands[1] = prepare_scc_operands (LTU);")
4060 (define_expand "sleu"
4061 [(set (match_operand:SI 0 "arith_reg_operand" "")
4064 "operands[1] = prepare_scc_operands (LEU);")
4066 (define_expand "sgeu"
4067 [(set (match_operand:SI 0 "arith_reg_operand" "")
4070 "operands[1] = prepare_scc_operands (GEU);")
4072 ;; sne moves the complement of the T reg to DEST like this:
4076 ;; This is better than xoring compare result with 1 because it does
4077 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
4080 (define_expand "sne"
4081 [(set (match_dup 2) (const_int -1))
4082 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
4083 (neg:SI (plus:SI (match_dup 1)
4086 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
4091 operands[1] = prepare_scc_operands (EQ);
4092 operands[2] = gen_reg_rtx (SImode);
4095 ;; Use the same trick for FP sle / sge
4096 (define_expand "movnegt"
4097 [(set (match_dup 2) (const_int -1))
4098 (parallel [(set (match_operand 0 "" "")
4099 (neg:SI (plus:SI (match_dup 1)
4102 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
4105 "operands[2] = gen_reg_rtx (SImode);")
4107 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
4108 ;; This prevents a regression that occurred when we switched from xor to
4112 [(set (match_operand:SI 0 "arith_reg_operand" "")
4113 (plus:SI (reg:SI T_REG)
4116 [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
4117 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
4120 ;; -------------------------------------------------------------------------
4121 ;; Instructions to cope with inline literal tables
4122 ;; -------------------------------------------------------------------------
4124 ; 2 byte integer in line
4126 (define_insn "consttable_2"
4127 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
4128 (match_operand 1 "" "")]
4133 if (operands[1] != const0_rtx)
4134 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
4137 [(set_attr "length" "2")
4138 (set_attr "in_delay_slot" "no")])
4140 ; 4 byte integer in line
4142 (define_insn "consttable_4"
4143 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
4144 (match_operand 1 "" "")]
4149 if (operands[1] != const0_rtx)
4150 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
4153 [(set_attr "length" "4")
4154 (set_attr "in_delay_slot" "no")])
4156 ; 8 byte integer in line
4158 (define_insn "consttable_8"
4159 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
4160 (match_operand 1 "" "")]
4165 if (operands[1] != const0_rtx)
4166 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
4169 [(set_attr "length" "8")
4170 (set_attr "in_delay_slot" "no")])
4172 ; 4 byte floating point
4174 (define_insn "consttable_sf"
4175 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
4176 (match_operand 1 "" "")]
4181 if (operands[1] != const0_rtx)
4183 union real_extract u;
4184 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4185 assemble_real (u.d, SFmode, GET_MODE_ALIGNMENT (SFmode));
4189 [(set_attr "length" "4")
4190 (set_attr "in_delay_slot" "no")])
4192 ; 8 byte floating point
4194 (define_insn "consttable_df"
4195 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
4196 (match_operand 1 "" "")]
4201 if (operands[1] != const0_rtx)
4203 union real_extract u;
4204 memcpy (&u, &CONST_DOUBLE_LOW (operands[0]), sizeof u);
4205 assemble_real (u.d, DFmode, GET_MODE_ALIGNMENT (DFmode));
4209 [(set_attr "length" "8")
4210 (set_attr "in_delay_slot" "no")])
4212 ;; Alignment is needed for some constant tables; it may also be added for
4213 ;; Instructions at the start of loops, or after unconditional branches.
4214 ;; ??? We would get more accurate lengths if we did instruction
4215 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
4216 ;; here is too conservative.
4218 ; align to a two byte boundary
4220 (define_expand "align_2"
4221 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
4225 ; align to a four byte boundary
4226 ;; align_4 and align_log are instructions for the starts of loops, or
4227 ;; after unconditional branches, which may take up extra room.
4229 (define_expand "align_4"
4230 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
4234 ; align to a cache line boundary
4236 (define_insn "align_log"
4237 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
4240 [(set_attr "length" "0")
4241 (set_attr "in_delay_slot" "no")])
4243 ; emitted at the end of the literal table, used to emit the
4244 ; 32bit branch labels if needed.
4246 (define_insn "consttable_end"
4247 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
4249 "* return output_jump_label_table ();"
4250 [(set_attr "in_delay_slot" "no")])
4252 ; emitted at the end of the window in the literal table.
4254 (define_insn "consttable_window_end"
4255 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
4258 [(set_attr "length" "0")
4259 (set_attr "in_delay_slot" "no")])
4261 ;; -------------------------------------------------------------------------
4263 ;; -------------------------------------------------------------------------
4265 ;; String/block move insn.
4267 (define_expand "movstrsi"
4268 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
4269 (mem:BLK (match_operand:BLK 1 "" "")))
4270 (use (match_operand:SI 2 "nonmemory_operand" ""))
4271 (use (match_operand:SI 3 "immediate_operand" ""))
4272 (clobber (reg:SI PR_REG))
4273 (clobber (reg:SI R4_REG))
4274 (clobber (reg:SI R5_REG))
4275 (clobber (reg:SI R0_REG))])]
4279 if(expand_block_move (operands))
4284 (define_insn "block_move_real"
4285 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4286 (mem:BLK (reg:SI R5_REG)))
4287 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4288 (clobber (reg:SI PR_REG))
4289 (clobber (reg:SI R0_REG))])]
4292 [(set_attr "type" "sfunc")
4293 (set_attr "needs_delay_slot" "yes")])
4295 (define_insn "block_lump_real"
4296 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4297 (mem:BLK (reg:SI R5_REG)))
4298 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4299 (use (reg:SI R6_REG))
4300 (clobber (reg:SI PR_REG))
4301 (clobber (reg:SI T_REG))
4302 (clobber (reg:SI R4_REG))
4303 (clobber (reg:SI R5_REG))
4304 (clobber (reg:SI R6_REG))
4305 (clobber (reg:SI R0_REG))])]
4308 [(set_attr "type" "sfunc")
4309 (set_attr "needs_delay_slot" "yes")])
4311 (define_insn "block_move_real_i4"
4312 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4313 (mem:BLK (reg:SI R5_REG)))
4314 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4315 (clobber (reg:SI PR_REG))
4316 (clobber (reg:SI R0_REG))
4317 (clobber (reg:SI R1_REG))
4318 (clobber (reg:SI R2_REG))])]
4321 [(set_attr "type" "sfunc")
4322 (set_attr "needs_delay_slot" "yes")])
4324 (define_insn "block_lump_real_i4"
4325 [(parallel [(set (mem:BLK (reg:SI R4_REG))
4326 (mem:BLK (reg:SI R5_REG)))
4327 (use (match_operand:SI 0 "arith_reg_operand" "r"))
4328 (use (reg:SI R6_REG))
4329 (clobber (reg:SI PR_REG))
4330 (clobber (reg:SI T_REG))
4331 (clobber (reg:SI R4_REG))
4332 (clobber (reg:SI R5_REG))
4333 (clobber (reg:SI R6_REG))
4334 (clobber (reg:SI R0_REG))
4335 (clobber (reg:SI R1_REG))
4336 (clobber (reg:SI R2_REG))
4337 (clobber (reg:SI R3_REG))])]
4340 [(set_attr "type" "sfunc")
4341 (set_attr "needs_delay_slot" "yes")])
4343 ;; -------------------------------------------------------------------------
4344 ;; Floating point instructions.
4345 ;; -------------------------------------------------------------------------
4347 ;; ??? All patterns should have a type attribute.
4349 (define_expand "fpu_switch0"
4350 [(set (match_operand:SI 0 "" "") (match_dup 2))
4351 (set (match_dup 1) (mem:PSI (match_dup 0)))]
4355 operands[1] = get_fpscr_rtx ();
4356 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4358 operands[2] = legitimize_pic_address (operands[2], SImode,
4359 no_new_pseudos ? operands[0] : 0);
4362 (define_expand "fpu_switch1"
4363 [(set (match_operand:SI 0 "" "") (match_dup 2))
4364 (set (match_dup 3) (plus:SI (match_dup 0) (const_int 4)))
4365 (set (match_dup 1) (mem:PSI (match_dup 3)))]
4369 operands[1] = get_fpscr_rtx ();
4370 operands[2] = gen_rtx_SYMBOL_REF (SImode, \"__fpscr_values\");
4372 operands[2] = legitimize_pic_address (operands[2], SImode,
4373 no_new_pseudos ? operands[0] : 0);
4374 operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
4377 (define_expand "movpsi"
4378 [(set (match_operand:PSI 0 "register_operand" "")
4379 (match_operand:PSI 1 "general_movsrc_operand" ""))]
4383 ;; The c / m alternative is a fake to guide reload to load directly into
4384 ;; fpscr, since reload doesn't know how to use post-increment.
4385 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
4386 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
4387 ;; predicate after reload.
4388 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
4389 ;; like a gpr <-> fpul move.
4390 (define_insn "fpu_switch"
4391 [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
4392 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
4394 && (! reload_completed
4395 || true_regnum (operands[0]) != FPSCR_REG
4396 || GET_CODE (operands[1]) != MEM
4397 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
4399 ! precision stays the same
4407 [(set_attr "length" "0,2,2,4,2,2,2,2")
4408 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
4411 [(set (reg:PSI FPSCR_REG)
4412 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4413 "TARGET_SH4 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
4414 [(set (match_dup 0) (match_dup 0))]
4417 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4418 gen_rtx (MEM, PSImode,
4419 gen_rtx (POST_INC, Pmode,
4421 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4425 [(set (reg:PSI FPSCR_REG)
4426 (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
4428 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
4431 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
4432 gen_rtx (MEM, PSImode,
4433 gen_rtx (POST_INC, Pmode,
4435 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
4438 ;; ??? This uses the fp unit, but has no type indicating that.
4439 ;; If we did that, this would either give a bogus latency or introduce
4440 ;; a bogus FIFO constraint.
4441 ;; Since this insn is currently only used for prologues/epilogues,
4442 ;; it is probably best to claim no function unit, which matches the
4444 (define_insn "toggle_sz"
4445 [(set (reg:PSI FPSCR_REG)
4446 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
4450 (define_expand "addsf3"
4451 [(match_operand:SF 0 "arith_reg_operand" "")
4452 (match_operand:SF 1 "arith_reg_operand" "")
4453 (match_operand:SF 2 "arith_reg_operand" "")]
4455 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
4457 (define_insn "addsf3_i"
4458 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4459 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
4460 (match_operand:SF 2 "arith_reg_operand" "f")))
4461 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4464 [(set_attr "type" "fp")
4465 (set_attr "fp_mode" "single")])
4467 (define_expand "subsf3"
4468 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4469 (match_operand:SF 1 "fp_arith_reg_operand" "")
4470 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4472 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
4474 (define_insn "subsf3_i"
4475 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4476 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
4477 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4478 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4481 [(set_attr "type" "fp")
4482 (set_attr "fp_mode" "single")])
4484 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
4485 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
4486 ;; mixed-precision SH4 targets. To allow it to be still generated for the
4487 ;; SH3E, we use a separate insn for SH3E mulsf3.
4489 (define_expand "mulsf3"
4490 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4491 (match_operand:SF 1 "fp_arith_reg_operand" "")
4492 (match_operand:SF 2 "fp_arith_reg_operand" "")]
4497 expand_sf_binop (&gen_mulsf3_i4, operands);
4499 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
4503 (define_insn "mulsf3_i4"
4504 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4505 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4506 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
4507 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4510 [(set_attr "type" "fp")
4511 (set_attr "fp_mode" "single")])
4513 (define_insn "mulsf3_ie"
4514 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4515 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
4516 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
4517 "TARGET_SH3E && ! TARGET_SH4"
4519 [(set_attr "type" "fp")])
4521 (define_insn "*macsf3"
4522 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4523 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
4524 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
4525 (match_operand:SF 3 "arith_reg_operand" "0")))
4526 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
4527 "TARGET_SH3E && ! TARGET_SH4"
4529 [(set_attr "type" "fp")
4530 (set_attr "fp_mode" "single")])
4532 (define_expand "divsf3"
4533 [(match_operand:SF 0 "arith_reg_operand" "")
4534 (match_operand:SF 1 "arith_reg_operand" "")
4535 (match_operand:SF 2 "arith_reg_operand" "")]
4537 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
4539 (define_insn "divsf3_i"
4540 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4541 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
4542 (match_operand:SF 2 "arith_reg_operand" "f")))
4543 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4546 [(set_attr "type" "fdiv")
4547 (set_attr "fp_mode" "single")])
4549 (define_expand "floatsisf2"
4550 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
4551 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
4557 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4562 (define_insn "floatsisf2_i4"
4563 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4564 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
4565 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4568 [(set_attr "type" "fp")
4569 (set_attr "fp_mode" "single")])
4571 (define_insn "*floatsisf2_ie"
4572 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4573 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
4574 "TARGET_SH3E && ! TARGET_SH4"
4576 [(set_attr "type" "fp")])
4578 (define_expand "fix_truncsfsi2"
4579 [(set (match_operand:SI 0 "fpul_operand" "=y")
4580 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4586 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4591 (define_insn "fix_truncsfsi2_i4"
4592 [(set (match_operand:SI 0 "fpul_operand" "=y")
4593 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4594 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4597 [(set_attr "type" "fp")
4598 (set_attr "fp_mode" "single")])
4600 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
4601 ;; fix_truncsfsi2_i4.
4602 ;; (define_insn "fix_truncsfsi2_i4_2"
4603 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4604 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4605 ;; (use (reg:PSI FPSCR_REG))
4606 ;; (clobber (reg:SI FPUL_REG))]
4609 ;; [(set_attr "length" "4")
4610 ;; (set_attr "fp_mode" "single")])
4613 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4614 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4615 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4616 ;; (clobber (reg:SI FPUL_REG))]
4618 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4619 ;; (use (match_dup 2))])
4620 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4622 (define_insn "*fixsfsi"
4623 [(set (match_operand:SI 0 "fpul_operand" "=y")
4624 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4625 "TARGET_SH3E && ! TARGET_SH4"
4627 [(set_attr "type" "fp")])
4629 (define_insn "cmpgtsf_t"
4630 [(set (reg:SI T_REG)
4631 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4632 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4633 "TARGET_SH3E && ! TARGET_SH4"
4635 [(set_attr "type" "fp")
4636 (set_attr "fp_mode" "single")])
4638 (define_insn "cmpeqsf_t"
4639 [(set (reg:SI T_REG)
4640 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4641 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
4642 "TARGET_SH3E && ! TARGET_SH4"
4644 [(set_attr "type" "fp")
4645 (set_attr "fp_mode" "single")])
4647 (define_insn "ieee_ccmpeqsf_t"
4648 [(set (reg:SI T_REG)
4649 (ior:SI (reg:SI T_REG)
4650 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4651 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
4652 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4653 "* return output_ieee_ccmpeq (insn, operands);"
4654 [(set_attr "length" "4")])
4657 (define_insn "cmpgtsf_t_i4"
4658 [(set (reg:SI T_REG)
4659 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4660 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4661 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4664 [(set_attr "type" "fp")
4665 (set_attr "fp_mode" "single")])
4667 (define_insn "cmpeqsf_t_i4"
4668 [(set (reg:SI T_REG)
4669 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4670 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
4671 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4674 [(set_attr "type" "fp")
4675 (set_attr "fp_mode" "single")])
4677 (define_insn "*ieee_ccmpeqsf_t_4"
4678 [(set (reg:SI T_REG)
4679 (ior:SI (reg:SI T_REG)
4680 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
4681 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
4682 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4683 "TARGET_IEEE && TARGET_SH4"
4684 "* return output_ieee_ccmpeq (insn, operands);"
4685 [(set_attr "length" "4")
4686 (set_attr "fp_mode" "single")])
4688 (define_expand "cmpsf"
4689 [(set (reg:SI T_REG)
4690 (compare (match_operand:SF 0 "arith_operand" "")
4691 (match_operand:SF 1 "arith_operand" "")))]
4695 sh_compare_op0 = operands[0];
4696 sh_compare_op1 = operands[1];
4700 (define_expand "negsf2"
4701 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4702 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4704 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4706 (define_insn "negsf2_i"
4707 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4708 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4709 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4712 [(set_attr "type" "fmove")
4713 (set_attr "fp_mode" "single")])
4715 (define_expand "sqrtsf2"
4716 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4717 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4719 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4721 (define_insn "sqrtsf2_i"
4722 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4723 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4724 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4727 [(set_attr "type" "fdiv")
4728 (set_attr "fp_mode" "single")])
4730 (define_expand "abssf2"
4731 [(match_operand:SF 0 "fp_arith_reg_operand" "")
4732 (match_operand:SF 1 "fp_arith_reg_operand" "")]
4734 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4736 (define_insn "abssf2_i"
4737 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
4738 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
4739 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4742 [(set_attr "type" "fmove")
4743 (set_attr "fp_mode" "single")])
4745 (define_expand "adddf3"
4746 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4747 (match_operand:DF 1 "fp_arith_reg_operand" "")
4748 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4750 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4752 (define_insn "adddf3_i"
4753 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4754 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4755 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4756 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4759 [(set_attr "type" "dfp_arith")
4760 (set_attr "fp_mode" "double")])
4762 (define_expand "subdf3"
4763 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4764 (match_operand:DF 1 "fp_arith_reg_operand" "")
4765 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4767 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4769 (define_insn "subdf3_i"
4770 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4771 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4772 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4773 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4776 [(set_attr "type" "dfp_arith")
4777 (set_attr "fp_mode" "double")])
4779 (define_expand "muldf3"
4780 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4781 (match_operand:DF 1 "fp_arith_reg_operand" "")
4782 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4784 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4786 (define_insn "muldf3_i"
4787 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4788 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
4789 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4790 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4793 [(set_attr "type" "dfp_arith")
4794 (set_attr "fp_mode" "double")])
4796 (define_expand "divdf3"
4797 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4798 (match_operand:DF 1 "fp_arith_reg_operand" "")
4799 (match_operand:DF 2 "fp_arith_reg_operand" "")]
4801 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4803 (define_insn "divdf3_i"
4804 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4805 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
4806 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
4807 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4810 [(set_attr "type" "dfdiv")
4811 (set_attr "fp_mode" "double")])
4813 (define_expand "floatsidf2"
4814 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4815 (match_operand:SI 1 "fpul_operand" "")]
4819 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1], get_fpscr_rtx ()));
4823 (define_insn "floatsidf2_i"
4824 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4825 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
4826 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4829 [(set_attr "type" "dfp_conv")
4830 (set_attr "fp_mode" "double")])
4832 (define_expand "fix_truncdfsi2"
4833 [(match_operand:SI 0 "fpul_operand" "")
4834 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4838 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1], get_fpscr_rtx ()));
4842 (define_insn "fix_truncdfsi2_i"
4843 [(set (match_operand:SI 0 "fpul_operand" "=y")
4844 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4845 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4848 [(set_attr "type" "dfp_conv")
4849 (set_attr "fp_mode" "double")])
4851 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
4852 ;; fix_truncdfsi2_i.
4853 ;; (define_insn "fix_truncdfsi2_i4"
4854 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4855 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4856 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4857 ;; (clobber (reg:SI FPUL_REG))]
4860 ;; [(set_attr "length" "4")
4861 ;; (set_attr "fp_mode" "double")])
4864 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4865 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4866 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
4867 ;; (clobber (reg:SI FPUL_REG))]
4869 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
4870 ;; (use (match_dup 2))])
4871 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
4873 (define_insn "cmpgtdf_t"
4874 [(set (reg:SI T_REG)
4875 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4876 (match_operand:DF 1 "arith_reg_operand" "f")))
4877 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4880 [(set_attr "type" "dfp_cmp")
4881 (set_attr "fp_mode" "double")])
4883 (define_insn "cmpeqdf_t"
4884 [(set (reg:SI T_REG)
4885 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4886 (match_operand:DF 1 "arith_reg_operand" "f")))
4887 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4890 [(set_attr "type" "dfp_cmp")
4891 (set_attr "fp_mode" "double")])
4893 (define_insn "*ieee_ccmpeqdf_t"
4894 [(set (reg:SI T_REG)
4895 (ior:SI (reg:SI T_REG)
4896 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4897 (match_operand:DF 1 "arith_reg_operand" "f"))))
4898 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4899 "TARGET_IEEE && TARGET_SH4"
4900 "* return output_ieee_ccmpeq (insn, operands);"
4901 [(set_attr "length" "4")
4902 (set_attr "fp_mode" "double")])
4904 (define_expand "cmpdf"
4905 [(set (reg:SI T_REG)
4906 (compare (match_operand:DF 0 "arith_operand" "")
4907 (match_operand:DF 1 "arith_operand" "")))]
4911 sh_compare_op0 = operands[0];
4912 sh_compare_op1 = operands[1];
4916 (define_expand "negdf2"
4917 [(match_operand:DF 0 "arith_reg_operand" "")
4918 (match_operand:DF 1 "arith_reg_operand" "")]
4920 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4922 (define_insn "negdf2_i"
4923 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4924 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4925 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4928 [(set_attr "type" "fmove")
4929 (set_attr "fp_mode" "double")])
4931 (define_expand "sqrtdf2"
4932 [(match_operand:DF 0 "arith_reg_operand" "")
4933 (match_operand:DF 1 "arith_reg_operand" "")]
4935 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4937 (define_insn "sqrtdf2_i"
4938 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4939 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4940 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4943 [(set_attr "type" "dfdiv")
4944 (set_attr "fp_mode" "double")])
4946 (define_expand "absdf2"
4947 [(match_operand:DF 0 "arith_reg_operand" "")
4948 (match_operand:DF 1 "arith_reg_operand" "")]
4950 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4952 (define_insn "absdf2_i"
4953 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4954 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4955 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4958 [(set_attr "type" "fmove")
4959 (set_attr "fp_mode" "double")])
4961 (define_expand "extendsfdf2"
4962 [(match_operand:DF 0 "fp_arith_reg_operand" "")
4963 (match_operand:SF 1 "fpul_operand" "")]
4967 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4971 (define_insn "extendsfdf2_i4"
4972 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
4973 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
4974 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4977 [(set_attr "type" "fp")
4978 (set_attr "fp_mode" "double")])
4980 (define_expand "truncdfsf2"
4981 [(match_operand:SF 0 "fpul_operand" "")
4982 (match_operand:DF 1 "fp_arith_reg_operand" "")]
4986 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1], get_fpscr_rtx ()));
4990 (define_insn "truncdfsf2_i4"
4991 [(set (match_operand:SF 0 "fpul_operand" "=y")
4992 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
4993 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4996 [(set_attr "type" "fp")
4997 (set_attr "fp_mode" "double")])
4999 ;; Bit field extract patterns. These give better code for packed bitfields,
5000 ;; because they allow auto-increment addresses to be generated.
5002 (define_expand "insv"
5003 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
5004 (match_operand:SI 1 "immediate_operand" "")
5005 (match_operand:SI 2 "immediate_operand" ""))
5006 (match_operand:SI 3 "general_operand" ""))]
5007 "! TARGET_LITTLE_ENDIAN"
5010 rtx addr_target, orig_address, shift_reg;
5013 /* ??? expmed doesn't care for non-register predicates. */
5014 if (! memory_operand (operands[0], VOIDmode)
5015 || ! immediate_operand (operands[1], VOIDmode)
5016 || ! immediate_operand (operands[2], VOIDmode)
5017 || ! general_operand (operands[3], VOIDmode))
5019 /* If this isn't a 16 / 24 / 32 bit field, or if
5020 it doesn't start on a byte boundary, then fail. */
5021 size = INTVAL (operands[1]);
5022 if (size < 16 || size > 32 || size % 8 != 0
5023 || (INTVAL (operands[2]) % 8) != 0)
5027 orig_address = XEXP (operands[0], 0);
5028 shift_reg = gen_reg_rtx (SImode);
5029 emit_insn (gen_movsi (shift_reg, operands[3]));
5030 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
5032 operands[0] = replace_equiv_address (operands[0], addr_target);
5033 emit_insn (gen_movqi (operands[0], gen_rtx_SUBREG (QImode, shift_reg, 0)));
5037 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
5038 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
5039 emit_insn (gen_movqi (operands[0],
5040 gen_rtx_SUBREG (QImode, shift_reg, 0)));
5046 ;; -------------------------------------------------------------------------
5048 ;; -------------------------------------------------------------------------
5050 ;; This matches cases where a stack pointer increment at the start of the
5051 ;; epilogue combines with a stack slot read loading the return value.
5054 [(set (match_operand:SI 0 "arith_reg_operand" "")
5055 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
5056 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
5057 "REGNO (operands[1]) != REGNO (operands[0])"
5060 ;; See the comment on the dt combiner pattern above.
5063 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
5064 (plus:SI (match_dup 0)
5067 (eq:SI (match_dup 0)
5072 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
5073 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
5074 ;; reload when the constant is too large for a reg+offset address.
5076 ;; ??? We would get much better code if this was done in reload. This would
5077 ;; require modifying find_reloads_address to recognize that if the constant
5078 ;; is out-of-range for an immediate add, then we get better code by reloading
5079 ;; the constant into a register than by reloading the sum into a register,
5080 ;; since the former is one instruction shorter if the address does not need
5081 ;; to be offsettable. Unfortunately this does not work, because there is
5082 ;; only one register, r0, that can be used as an index register. This register
5083 ;; is also the function return value register. So, if we try to force reload
5084 ;; to use double-reg addresses, then we end up with some instructions that
5085 ;; need to use r0 twice. The only way to fix this is to change the calling
5086 ;; convention so that r0 is not used to return values.
5089 [(set (match_operand:SI 0 "register_operand" "=r")
5090 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5091 (set (mem:SI (match_dup 0))
5092 (match_operand:SI 2 "general_movsrc_operand" ""))]
5093 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5094 "mov.l %2,@(%0,%1)")
5097 [(set (match_operand:SI 0 "register_operand" "=r")
5098 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5099 (set (match_operand:SI 2 "general_movdst_operand" "")
5100 (mem:SI (match_dup 0)))]
5101 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5102 "mov.l @(%0,%1),%2")
5105 [(set (match_operand:SI 0 "register_operand" "=r")
5106 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5107 (set (mem:HI (match_dup 0))
5108 (match_operand:HI 2 "general_movsrc_operand" ""))]
5109 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5110 "mov.w %2,@(%0,%1)")
5113 [(set (match_operand:SI 0 "register_operand" "=r")
5114 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5115 (set (match_operand:HI 2 "general_movdst_operand" "")
5116 (mem:HI (match_dup 0)))]
5117 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5118 "mov.w @(%0,%1),%2")
5121 [(set (match_operand:SI 0 "register_operand" "=r")
5122 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5123 (set (mem:QI (match_dup 0))
5124 (match_operand:QI 2 "general_movsrc_operand" ""))]
5125 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5126 "mov.b %2,@(%0,%1)")
5129 [(set (match_operand:SI 0 "register_operand" "=r")
5130 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5131 (set (match_operand:QI 2 "general_movdst_operand" "")
5132 (mem:QI (match_dup 0)))]
5133 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
5134 "mov.b @(%0,%1),%2")
5137 [(set (match_operand:SI 0 "register_operand" "=r")
5138 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5139 (set (mem:SF (match_dup 0))
5140 (match_operand:SF 2 "general_movsrc_operand" ""))]
5141 "REGNO (operands[0]) == 0
5142 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5143 || (GET_CODE (operands[2]) == SUBREG
5144 && REGNO (SUBREG_REG (operands[2])) < 16))
5145 && reg_unused_after (operands[0], insn)"
5146 "mov.l %2,@(%0,%1)")
5149 [(set (match_operand:SI 0 "register_operand" "=r")
5150 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5151 (set (match_operand:SF 2 "general_movdst_operand" "")
5153 (mem:SF (match_dup 0)))]
5154 "REGNO (operands[0]) == 0
5155 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
5156 || (GET_CODE (operands[2]) == SUBREG
5157 && REGNO (SUBREG_REG (operands[2])) < 16))
5158 && reg_unused_after (operands[0], insn)"
5159 "mov.l @(%0,%1),%2")
5162 [(set (match_operand:SI 0 "register_operand" "=r")
5163 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5164 (set (mem:SF (match_dup 0))
5165 (match_operand:SF 2 "general_movsrc_operand" ""))]
5166 "REGNO (operands[0]) == 0
5167 && ((GET_CODE (operands[2]) == REG
5168 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5169 || (GET_CODE (operands[2]) == SUBREG
5170 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5171 && reg_unused_after (operands[0], insn)"
5172 "fmov{.s|} %2,@(%0,%1)")
5175 [(set (match_operand:SI 0 "register_operand" "=r")
5176 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
5177 (set (match_operand:SF 2 "general_movdst_operand" "")
5179 (mem:SF (match_dup 0)))]
5180 "REGNO (operands[0]) == 0
5181 && ((GET_CODE (operands[2]) == REG
5182 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
5183 || (GET_CODE (operands[2]) == SUBREG
5184 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
5185 && reg_unused_after (operands[0], insn)"
5186 "fmov{.s|} @(%0,%1),%2")
5188 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
5189 (define_insn "sp_switch_1"
5196 xoperands[0] = sp_switch;
5197 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
5198 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
5199 return \"mov r0,r15\";
5201 [(set_attr "length" "10")])
5203 ;; Switch back to the original stack for interrupt functions with the
5204 ;; sp_switch attribute. */
5205 (define_insn "sp_switch_2"
5208 "mov.l @r15+,r15\;mov.l @r15+,r0"
5209 [(set_attr "length" "4")])