1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
84 /* We can not debug without a frame pointer. */
85 /* #define CAN_DEBUG_WITHOUT_FP */
87 #define CONDITIONAL_REGISTER_USAGE do \
90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
105 /* Renesas saves and restores mac registers on call. */ \
106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
114 if (TARGET_SHMEDIA) \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
126 /* ??? Need to write documentation for all SH options and add it to the
129 /* Run-time compilation parameters selecting different hardware subsets. */
131 extern int target_flags;
132 #define ISIZE_BIT (1<<1)
133 #define DALIGN_BIT (1<<6)
134 #define SH1_BIT (1<<8)
135 #define SH2_BIT (1<<9)
136 #define SH3_BIT (1<<10)
137 #define SH_E_BIT (1<<11)
138 #define HARD_SH4_BIT (1<<5)
139 #define FPU_SINGLE_BIT (1<<7)
140 #define SH4_BIT (1<<12)
141 #define FMOVD_BIT (1<<4)
142 #define SH5_BIT (1<<0)
143 #define SPACE_BIT (1<<13)
144 #define BIGTABLE_BIT (1<<14)
145 #define RELAX_BIT (1<<15)
146 #define USERMODE_BIT (1<<16)
147 #define HITACHI_BIT (1<<22)
148 #define NOMACSAVE_BIT (1<<23)
149 #define PREFERGOT_BIT (1<<24)
150 #define PADSTRUCT_BIT (1<<28)
151 #define LITTLE_ENDIAN_BIT (1<<29)
152 #define IEEE_BIT (1<<30)
154 /* Nonzero if we should dump out instruction size info. */
155 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
157 /* Nonzero to align doubles on 64 bit boundaries. */
158 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
160 /* Nonzero if we should generate code using type 1 insns. */
161 #define TARGET_SH1 (target_flags & SH1_BIT)
163 /* Nonzero if we should generate code using type 2 insns. */
164 #define TARGET_SH2 (target_flags & SH2_BIT)
166 /* Nonzero if we should generate code using type 2E insns. */
167 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
169 /* Nonzero if we should generate code using type 3 insns. */
170 #define TARGET_SH3 (target_flags & SH3_BIT)
172 /* Nonzero if we should generate code using type 3E insns. */
173 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
175 /* Nonzero if the cache line size is 32. */
176 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
178 /* Nonzero if we schedule for a superscalar implementation. */
179 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
181 /* Nonzero if the target has separate instruction and data caches. */
182 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
184 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
185 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
187 /* Nonzero if the default precision of th FPU is single */
188 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
190 /* Nonzero if a double-precision FPU is available. */
191 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
193 /* Nonzero if an FPU is available. */
194 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
196 /* Nonzero if we should generate code using type 4 insns. */
197 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
199 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
200 #define TARGET_SH5 (target_flags & SH5_BIT)
202 /* Nonzero if we should generate code using the SHcompact instruction
203 set and 32-bit ABI. */
204 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
206 /* Nonzero if we should generate code using the SHmedia instruction
208 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
210 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
212 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
213 && (target_flags & SH_E_BIT))
215 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
217 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
218 && ! (target_flags & SH_E_BIT))
220 /* Nonzero if we should generate code using SHmedia FPU instructions. */
221 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
222 /* Nonzero if we should generate fmovd. */
223 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
225 /* Nonzero if we respect NANs. */
226 #define TARGET_IEEE (target_flags & IEEE_BIT)
228 /* Nonzero if we should generate smaller code rather than faster code. */
229 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
231 /* Nonzero to use long jump tables. */
232 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
234 /* Nonzero to generate pseudo-ops needed by the assembler and linker
235 to do function call relaxing. */
236 #define TARGET_RELAX (target_flags & RELAX_BIT)
238 /* Nonzero if using Renesas's calling convention. */
239 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
241 /* Nonzero if not saving macl/mach when using -mhitachi */
242 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
244 /* Nonzero if padding structures to a multiple of 4 bytes. This is
245 incompatible with Renesas's compiler, and gives unusual structure layouts
246 which confuse programmers.
247 ??? This option is not useful, but is retained in case there are people
248 who are still relying on it. It may be deleted in the future. */
249 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
251 /* Nonzero if generating code for a little endian SH. */
252 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
254 /* Nonzero if we should do everything in userland. */
255 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
257 /* Nonzero if we should prefer @GOT calls when generating PIC. */
258 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
260 #define SELECT_SH1 (SH1_BIT)
261 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
262 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
263 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
264 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
265 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
266 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
267 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
268 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
269 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
270 #define SELECT_SH5_64_NOFPU (SH5_BIT)
271 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
272 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
273 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
274 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
276 /* Reset all target-selection flags. */
277 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
278 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
280 #define TARGET_SWITCHES \
281 { {"1", TARGET_NONE, "" }, \
282 {"1", SELECT_SH1, "Generate SH1 code" }, \
283 {"2", TARGET_NONE, "" }, \
284 {"2", SELECT_SH2, "Generate SH2 code" }, \
285 {"2e", TARGET_NONE, "" }, \
286 {"2e", SELECT_SH2E, "Generate SH2e code" }, \
287 {"3", TARGET_NONE, "" }, \
288 {"3", SELECT_SH3, "Generate SH3 code" }, \
289 {"3e", TARGET_NONE, "" }, \
290 {"3e", SELECT_SH3E, "Generate SH3e code" }, \
291 {"4-single-only", TARGET_NONE, "" }, \
292 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" }, \
293 {"4-single", TARGET_NONE, "" }, \
294 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" }, \
295 {"4-nofpu", TARGET_NONE, "" }, \
296 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" }, \
297 {"4", TARGET_NONE, "" }, \
298 {"4", SELECT_SH4, "Generate SH4 code" }, \
299 {"5-64media", TARGET_NONE, "" }, \
300 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
301 {"5-64media-nofpu", TARGET_NONE, "" }, \
302 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
303 {"5-32media", TARGET_NONE, "" }, \
304 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
305 {"5-32media-nofpu", TARGET_NONE, "" }, \
306 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
307 {"5-compact", TARGET_NONE, "" }, \
308 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
309 {"5-compact-nofpu", TARGET_NONE, "" }, \
310 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
311 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
312 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
313 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
314 {"fmovd", FMOVD_BIT, "" }, \
315 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
316 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
317 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
318 {"isize", ISIZE_BIT, "" }, \
319 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
320 {"no-ieee", -IEEE_BIT, "" }, \
321 {"padstruct", PADSTRUCT_BIT, "" }, \
322 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
323 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
324 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
325 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
327 {"", TARGET_DEFAULT, "" } \
330 /* This are meant to be redefined in the host dependent files */
331 #define SUBTARGET_SWITCHES
333 /* This defaults us to big-endian. */
334 #ifndef TARGET_ENDIAN_DEFAULT
335 #define TARGET_ENDIAN_DEFAULT 0
338 #ifndef TARGET_CPU_DEFAULT
339 #define TARGET_CPU_DEFAULT SELECT_SH1
342 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
344 #define CPP_SPEC " %(subtarget_cpp_spec) "
346 #ifndef SUBTARGET_CPP_SPEC
347 #define SUBTARGET_CPP_SPEC ""
350 #ifndef SUBTARGET_EXTRA_SPECS
351 #define SUBTARGET_EXTRA_SPECS
354 #define EXTRA_SPECS \
355 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
356 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
357 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
358 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
359 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
360 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
361 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
362 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
363 SUBTARGET_EXTRA_SPECS
365 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
366 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
368 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
371 #define SH_ASM_SPEC \
372 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
373 %(subtarget_asm_isa_spec)"
375 #define ASM_SPEC SH_ASM_SPEC
377 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
378 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
379 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
381 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
385 #define SUBTARGET_ASM_ISA_SPEC ""
387 #define LINK_EMUL_PREFIX "sh%{ml:l}"
389 #if TARGET_CPU_DEFAULT & SH5_BIT
390 #if TARGET_CPU_DEFAULT & SH_E_BIT
391 #define LINK_DEFAULT_CPU_EMUL "32"
393 #define LINK_DEFAULT_CPU_EMUL "64"
394 #endif /* SH_E_BIT */
396 #define LINK_DEFAULT_CPU_EMUL ""
399 #define SUBTARGET_LINK_EMUL_SUFFIX ""
400 #define SUBTARGET_LINK_SPEC ""
402 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
403 so that we can undo the damage without code replication. */
404 #define LINK_SPEC SH_LINK_SPEC
406 #define SH_LINK_SPEC "\
407 -m %(link_emul_prefix)\
408 %{m5-compact*|m5-32media*:32}\
410 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
411 %(subtarget_link_emul_suffix) \
412 %{mrelax:-relax} %(subtarget_link_spec)"
414 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
417 flag_omit_frame_pointer = -1; \
419 target_flags |= SPACE_BIT; \
422 #define ASSEMBLER_DIALECT assembler_dialect
424 extern int assembler_dialect;
426 #define OVERRIDE_OPTIONS \
431 assembler_dialect = 0; \
442 assembler_dialect = 1; \
448 target_flags |= DALIGN_BIT; \
450 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
451 target_flags |= FMOVD_BIT; \
452 if (TARGET_SHMEDIA) \
454 /* There are no delay slots on SHmedia. */ \
455 flag_delayed_branch = 0; \
456 /* Relaxation isn't yet supported for SHmedia */ \
457 target_flags &= ~RELAX_BIT; \
459 /* -fprofile-arcs needs a working libgcov . In unified tree \
460 configurations with newlib, this requires to configure with \
461 --with-newlib --with-headers. But there is no way to check \
462 here we have a working libgcov, so just assume that we have. */\
465 warning ("Profiling is not supported on this target."); \
466 profile_flag = profile_arc_flag = 0; \
471 /* Only the sh64-elf assembler fully supports .quad properly. */\
472 targetm.asm_out.aligned_op.di = NULL; \
473 targetm.asm_out.unaligned_op.di = NULL; \
476 reg_class_from_letter['e' - 'a'] = NO_REGS; \
478 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
479 if (! VALID_REGISTER_P (regno)) \
480 sh_register_names[regno][0] = '\0'; \
482 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
483 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
484 sh_additional_register_names[regno][0] = '\0'; \
486 if (flag_omit_frame_pointer < 0) \
488 /* The debugging information is sufficient, \
489 but gdb doesn't implement this yet */ \
491 flag_omit_frame_pointer \
492 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
493 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
495 flag_omit_frame_pointer = 0; \
498 if (flag_pic && ! TARGET_PREFERGOT) \
499 flag_no_function_cse = 1; \
501 if (SMALL_REGISTER_CLASSES) \
503 /* Never run scheduling before reload, since that can \
504 break global alloc, and generates slower code anyway due \
505 to the pressure on R0. */ \
506 flag_schedule_insns = 0; \
509 if (align_loops == 0) \
510 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
511 if (align_jumps == 0) \
512 align_jumps = 1 << CACHE_LOG; \
513 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
514 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
516 /* Allocation boundary (in *bytes*) for the code of a function. \
517 SH1: 32 bit alignment is faster, because instructions are always \
518 fetched as a pair from a longword boundary. \
519 SH2 .. SH5 : align to cache line start. */ \
520 if (align_functions == 0) \
522 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
523 /* The linker relaxation code breaks when a function contains \
524 alignments that are larger than that at the start of a \
525 compilation unit. */ \
529 = align_loops > align_jumps ? align_loops : align_jumps; \
531 /* Also take possible .long constants / mova tables int account. */\
534 if (align_functions < min_align) \
535 align_functions = min_align; \
539 /* Target machine storage layout. */
541 /* Define this if most significant bit is lowest numbered
542 in instructions that operate on numbered bit-fields. */
544 #define BITS_BIG_ENDIAN 0
546 /* Define this if most significant byte of a word is the lowest numbered. */
547 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
549 /* Define this if most significant word of a multiword number is the lowest
551 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
553 /* Define this to set the endianness to use in libgcc2.c, which can
554 not depend on target_flags. */
555 #if defined(__LITTLE_ENDIAN__)
556 #define LIBGCC2_WORDS_BIG_ENDIAN 0
558 #define LIBGCC2_WORDS_BIG_ENDIAN 1
561 #define MAX_BITS_PER_WORD 64
563 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
565 /* Width in bits of an `int'. We want just 32-bits, even if words are
567 #define INT_TYPE_SIZE 32
569 /* Width in bits of a `long'. */
570 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
572 /* Width in bits of a `long long'. */
573 #define LONG_LONG_TYPE_SIZE 64
575 /* Width in bits of a `long double'. */
576 #define LONG_DOUBLE_TYPE_SIZE 64
578 /* Width of a word, in units (bytes). */
579 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
580 #define MIN_UNITS_PER_WORD 4
582 /* Width in bits of a pointer.
583 See also the macro `Pmode' defined below. */
584 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
586 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
587 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
589 /* Boundary (in *bits*) on which stack pointer should be aligned. */
590 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
592 /* The log (base 2) of the cache line size, in bytes. Processors prior to
593 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
594 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
595 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
597 /* ABI given & required minimum allocation boundary (in *bits*) for the
598 code of a function. */
599 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
601 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
602 the vbit must go into the delta field of
603 pointers-to-member-functions. */
604 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
605 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
607 /* Alignment of field after `int : 0' in a structure. */
608 #define EMPTY_FIELD_BOUNDARY 32
610 /* No data type wants to be aligned rounder than this. */
611 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
613 /* The best alignment to use in cases where we have a choice. */
614 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
616 /* Make strings word-aligned so strcpy from constants will be faster. */
617 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
618 ((TREE_CODE (EXP) == STRING_CST \
619 && (ALIGN) < FASTEST_ALIGNMENT) \
620 ? FASTEST_ALIGNMENT : (ALIGN))
622 /* get_mode_alignment assumes complex values are always held in multiple
623 registers, but that is not the case on the SH; CQImode and CHImode are
624 held in a single integer register. SH5 also holds CSImode and SCmode
625 values in integer regsters. Thus the alignment needs to be bumped up
626 to match the size of the mode. */
627 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
628 (MAX ((GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_INT \
629 || GET_MODE_CLASS (TYPE_MODE (STRUCT)) == MODE_COMPLEX_FLOAT) \
630 ? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (STRUCT))) \
633 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
634 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
635 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
636 ? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
639 /* Make arrays of chars word-aligned for the same reasons. */
640 #define DATA_ALIGNMENT(TYPE, ALIGN) \
641 (TREE_CODE (TYPE) == ARRAY_TYPE \
642 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
643 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
645 /* Number of bits which any structure or union's size must be a
646 multiple of. Each structure or union's size is rounded up to a
648 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
650 /* Set this nonzero if move instructions will actually fail to work
651 when given unaligned data. */
652 #define STRICT_ALIGNMENT 1
654 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
655 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
656 barrier_align (LABEL_AFTER_BARRIER)
658 #define LOOP_ALIGN(A_LABEL) \
659 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
660 ? 0 : sh_loop_align (A_LABEL))
662 #define LABEL_ALIGN(A_LABEL) \
664 (PREV_INSN (A_LABEL) \
665 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
666 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
667 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
668 /* explicit alignment insn in constant tables. */ \
669 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
672 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
673 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
675 /* The base two logarithm of the known minimum alignment of an insn length. */
676 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
677 (GET_CODE (A_INSN) == INSN \
678 ? 1 << TARGET_SHMEDIA \
679 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
680 ? 1 << TARGET_SHMEDIA \
683 /* Standard register usage. */
685 /* Register allocation for the Renesas calling convention:
691 r14 frame pointer/call saved
693 ap arg pointer (doesn't really exist, always eliminated)
694 pr subroutine return address
696 mach multiply/accumulate result, high part
697 macl multiply/accumulate result, low part.
698 fpul fp/int communication register
699 rap return address pointer register
701 fr1..fr3 scratch floating point registers
703 fr12..fr15 call saved floating point registers */
705 #define MAX_REGISTER_NAME_LENGTH 5
706 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
708 #define SH_REGISTER_NAMES_INITIALIZER \
710 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
711 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
712 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
713 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
714 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
715 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
716 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
717 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
718 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
719 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
720 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
721 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
722 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
723 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
724 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
725 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
726 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
727 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
728 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
732 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
734 #define REGNAMES_ARR_INDEX_1(index) \
735 (sh_register_names[index])
736 #define REGNAMES_ARR_INDEX_2(index) \
737 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
738 #define REGNAMES_ARR_INDEX_4(index) \
739 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
740 #define REGNAMES_ARR_INDEX_8(index) \
741 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
742 #define REGNAMES_ARR_INDEX_16(index) \
743 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
744 #define REGNAMES_ARR_INDEX_32(index) \
745 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
746 #define REGNAMES_ARR_INDEX_64(index) \
747 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
749 #define REGISTER_NAMES \
751 REGNAMES_ARR_INDEX_64 (0), \
752 REGNAMES_ARR_INDEX_64 (64), \
753 REGNAMES_ARR_INDEX_8 (128), \
754 REGNAMES_ARR_INDEX_8 (136), \
755 REGNAMES_ARR_INDEX_8 (144), \
756 REGNAMES_ARR_INDEX_1 (152) \
759 #define ADDREGNAMES_SIZE 32
760 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
761 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
762 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
764 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
766 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
767 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
768 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
769 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
772 #define ADDREGNAMES_REGNO(index) \
773 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
776 #define ADDREGNAMES_ARR_INDEX_1(index) \
777 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
778 #define ADDREGNAMES_ARR_INDEX_2(index) \
779 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
780 #define ADDREGNAMES_ARR_INDEX_4(index) \
781 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
782 #define ADDREGNAMES_ARR_INDEX_8(index) \
783 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
784 #define ADDREGNAMES_ARR_INDEX_16(index) \
785 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
786 #define ADDREGNAMES_ARR_INDEX_32(index) \
787 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
789 #define ADDITIONAL_REGISTER_NAMES \
791 ADDREGNAMES_ARR_INDEX_32 (0) \
794 /* Number of actual hardware registers.
795 The hardware registers are assigned numbers for the compiler
796 from 0 to just below FIRST_PSEUDO_REGISTER.
797 All registers that the compiler knows about must be given numbers,
798 even those that are not normally considered general registers. */
800 /* There are many other relevant definitions in sh.md's md_constants. */
802 #define FIRST_GENERAL_REG R0_REG
803 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
804 #define FIRST_FP_REG DR0_REG
805 #define LAST_FP_REG (FIRST_FP_REG + \
806 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
807 #define FIRST_XD_REG XD0_REG
808 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
809 #define FIRST_TARGET_REG TR0_REG
810 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
812 #define GENERAL_REGISTER_P(REGNO) \
813 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
815 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
816 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
818 #define FP_REGISTER_P(REGNO) \
819 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
821 #define XD_REGISTER_P(REGNO) \
822 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
824 #define FP_OR_XD_REGISTER_P(REGNO) \
825 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
827 #define FP_ANY_REGISTER_P(REGNO) \
828 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
830 #define SPECIAL_REGISTER_P(REGNO) \
831 ((REGNO) == GBR_REG || (REGNO) == T_REG \
832 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
834 #define TARGET_REGISTER_P(REGNO) \
835 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
837 #define SHMEDIA_REGISTER_P(REGNO) \
838 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
839 || TARGET_REGISTER_P (REGNO))
841 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
842 that should be fixed. */
843 #define VALID_REGISTER_P(REGNO) \
844 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
845 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
846 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
847 || (TARGET_SH2E && (REGNO) == FPUL_REG))
849 /* The mode that should be generally used to store a register by
850 itself in the stack, or to load it back. */
851 #define REGISTER_NATURAL_MODE(REGNO) \
852 (FP_REGISTER_P (REGNO) ? SFmode \
853 : XD_REGISTER_P (REGNO) ? DFmode \
854 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
858 #define FIRST_PSEUDO_REGISTER 153
860 /* 1 for registers that have pervasive standard uses
861 and are not available for the register allocator.
863 Mach register is fixed 'cause it's only 10 bits wide for SH1.
864 It is 32 bits wide for SH2. */
866 #define FIXED_REGISTERS \
868 /* Regular registers. */ \
869 0, 0, 0, 0, 0, 0, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 1, \
871 /* r16 is reserved, r18 is the former pr. */ \
872 1, 0, 0, 0, 0, 0, 0, 0, \
873 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
874 /* r26 is a global variable data pointer; r27 is for constants. */ \
875 1, 1, 1, 1, 0, 0, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, \
877 0, 0, 0, 0, 0, 0, 0, 0, \
878 0, 0, 0, 0, 0, 0, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 1, \
880 /* FP registers. */ \
881 0, 0, 0, 0, 0, 0, 0, 0, \
882 0, 0, 0, 0, 0, 0, 0, 0, \
883 0, 0, 0, 0, 0, 0, 0, 0, \
884 0, 0, 0, 0, 0, 0, 0, 0, \
885 0, 0, 0, 0, 0, 0, 0, 0, \
886 0, 0, 0, 0, 0, 0, 0, 0, \
887 0, 0, 0, 0, 0, 0, 0, 0, \
888 0, 0, 0, 0, 0, 0, 0, 0, \
889 /* Branch target registers. */ \
890 0, 0, 0, 0, 0, 0, 0, 0, \
891 /* XD registers. */ \
892 0, 0, 0, 0, 0, 0, 0, 0, \
893 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
894 1, 1, 1, 1, 1, 1, 0, 1, \
899 /* 1 for registers not available across function calls.
900 These must include the FIXED_REGISTERS and also any
901 registers that can be used without being saved.
902 The latter must include the registers where values are returned
903 and the register where structure-value addresses are passed.
904 Aside from that, you can include as many other registers as you like. */
906 #define CALL_USED_REGISTERS \
908 /* Regular registers. */ \
909 1, 1, 1, 1, 1, 1, 1, 1, \
910 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
911 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
912 across SH5 function calls. */ \
913 0, 0, 0, 0, 0, 0, 0, 1, \
914 1, 1, 0, 1, 1, 1, 1, 1, \
915 1, 1, 1, 1, 0, 0, 0, 0, \
916 0, 0, 0, 0, 1, 1, 1, 1, \
917 1, 1, 1, 1, 0, 0, 0, 0, \
918 0, 0, 0, 0, 0, 0, 0, 0, \
919 0, 0, 0, 0, 1, 1, 1, 1, \
920 /* FP registers. */ \
921 1, 1, 1, 1, 1, 1, 1, 1, \
922 1, 1, 1, 1, 0, 0, 0, 0, \
923 1, 1, 1, 1, 1, 1, 1, 1, \
924 1, 1, 1, 1, 1, 1, 1, 1, \
925 1, 1, 1, 1, 0, 0, 0, 0, \
926 0, 0, 0, 0, 0, 0, 0, 0, \
927 0, 0, 0, 0, 0, 0, 0, 0, \
928 0, 0, 0, 0, 0, 0, 0, 0, \
929 /* Branch target registers. */ \
930 1, 1, 1, 1, 1, 0, 0, 0, \
931 /* XD registers. */ \
932 1, 1, 1, 1, 1, 1, 0, 0, \
933 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
934 1, 1, 0, 1, 1, 1, 1, 1, \
939 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
940 across SHcompact function calls. We can't tell whether a called
941 function is SHmedia or SHcompact, so we assume it may be when
942 compiling SHmedia code with the 32-bit ABI, since that's the only
943 ABI that can be linked with SHcompact code. */
944 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
946 && GET_MODE_SIZE (MODE) > 4 \
947 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
948 && (REGNO) <= FIRST_GENERAL_REG + 14) \
949 || (REGNO) == PR_MEDIA_REG))
951 /* Return number of consecutive hard regs needed starting at reg REGNO
952 to hold something of mode MODE.
953 This is ordinarily the length in words of a value of mode MODE
954 but can be less for certain modes in special long registers.
956 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
958 #define HARD_REGNO_NREGS(REGNO, MODE) \
959 (XD_REGISTER_P (REGNO) \
960 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
961 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
962 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
963 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
965 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
966 We can allow any mode in any general register. The special registers
967 only allow SImode. Don't allow any mode in the PR. */
969 /* We cannot hold DCmode values in the XD registers because alter_reg
970 handles subregs of them incorrectly. We could work around this by
971 spacing the XD registers like the DR registers, but this would require
972 additional memory in every compilation to hold larger register vectors.
973 We could hold SFmode / SCmode values in XD registers, but that
974 would require a tertiary reload when reloading from / to memory,
975 and a secondary reload to reload from / to general regs; that
976 seems to be a loosing proposition. */
977 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
978 it won't be ferried through GP registers first. */
979 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
980 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
981 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
982 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
984 : (MODE) == V2SFmode \
985 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
986 || GENERAL_REGISTER_P (REGNO)) \
987 : (MODE) == V4SFmode \
988 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
989 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
990 : (MODE) == V16SFmode \
992 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
993 : (REGNO) == FIRST_XD_REG) \
994 : FP_REGISTER_P (REGNO) \
995 ? ((MODE) == SFmode || (MODE) == SImode \
996 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
997 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
998 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
999 || (MODE) == V2SFmode || (MODE) == TImode))) \
1000 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1001 : XD_REGISTER_P (REGNO) \
1002 ? (MODE) == DFmode \
1003 : TARGET_REGISTER_P (REGNO) \
1004 ? ((MODE) == DImode || (MODE) == SImode) \
1005 : (REGNO) == PR_REG ? 0 \
1006 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1009 /* Value is 1 if MODE is a supported vector mode. */
1010 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1012 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1013 || (TARGET_SHMEDIA \
1014 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1015 || (MODE) == V2SImode)))
1017 /* Value is 1 if it is a good idea to tie two pseudo registers
1018 when one has mode MODE1 and one has mode MODE2.
1019 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1020 for any hard reg, then this must be 0 for correct output.
1021 That's the case for xd registers: we don't hold SFmode values in
1022 them, so we can't tie an SFmode pseudos with one in another
1023 floating-point mode. */
1025 #define MODES_TIEABLE_P(MODE1, MODE2) \
1026 ((MODE1) == (MODE2) \
1027 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1028 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1029 && (GET_MODE_SIZE (MODE2) <= 4)) \
1030 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1032 /* A C expression that is nonzero if hard register NEW_REG can be
1033 considered for use as a rename register for OLD_REG register */
1035 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1036 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1038 /* Specify the registers used for certain standard purposes.
1039 The values of these macros are register numbers. */
1041 /* Define this if the program counter is overloaded on a register. */
1042 /* #define PC_REGNUM 15*/
1044 /* Register to use for pushing function arguments. */
1045 #define STACK_POINTER_REGNUM SP_REG
1047 /* Base register for access to local variables of the function. */
1048 #define FRAME_POINTER_REGNUM FP_REG
1050 /* Fake register that holds the address on the stack of the
1051 current function's return address. */
1052 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1054 /* Register to hold the addressing base for position independent
1055 code access to data items. */
1056 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1058 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1060 /* Value should be nonzero if functions must have frame pointers.
1061 Zero means the frame pointer need not be set up (and parms may be accessed
1062 via the stack pointer) in functions that seem suitable. */
1064 #define FRAME_POINTER_REQUIRED 0
1066 /* Definitions for register eliminations.
1068 We have three registers that can be eliminated on the SH. First, the
1069 frame pointer register can often be eliminated in favor of the stack
1070 pointer register. Secondly, the argument pointer register can always be
1071 eliminated; it is replaced with either the stack or frame pointer.
1072 Third, there is the return address pointer, which can also be replaced
1073 with either the stack or the frame pointer. */
1075 /* This is an array of structures. Each structure initializes one pair
1076 of eliminable registers. The "from" register number is given first,
1077 followed by "to". Eliminations of the same "from" register are listed
1078 in order of preference. */
1080 /* If you add any registers here that are not actually hard registers,
1081 and that have any alternative of elimination that doesn't always
1082 apply, you need to amend calc_live_regs to exclude it, because
1083 reload spills all eliminable registers where it sees an
1084 can_eliminate == 0 entry, thus making them 'live' .
1085 If you add any hard registers that can be eliminated in different
1086 ways, you have to patch reload to spill them only when all alternatives
1087 of elimination fail. */
1089 #define ELIMINABLE_REGS \
1090 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1091 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1092 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1093 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1094 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1096 /* Given FROM and TO register numbers, say whether this elimination
1098 #define CAN_ELIMINATE(FROM, TO) \
1099 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1101 /* Define the offset between two registers, one to be eliminated, and the other
1102 its replacement, at the start of a routine. */
1104 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1105 OFFSET = initial_elimination_offset ((FROM), (TO))
1107 /* Base register for access to arguments of the function. */
1108 #define ARG_POINTER_REGNUM AP_REG
1110 /* Register in which the static-chain is passed to a function. */
1111 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1113 /* The register in which a struct value address is passed. */
1115 #define STRUCT_VALUE_REGNUM 2
1117 /* If the structure value address is not passed in a register, define
1118 `STRUCT_VALUE' as an expression returning an RTX for the place
1119 where the address is passed. If it returns 0, the address is
1120 passed as an "invisible" first argument. */
1122 /* The Renesas calling convention doesn't quite fit into this scheme since
1123 the address is passed like an invisible argument, but one that is always
1124 passed in memory. */
1125 #define STRUCT_VALUE \
1126 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1128 #define RETURN_IN_MEMORY(TYPE) \
1130 ? ((TYPE_MODE (TYPE) == BLKmode \
1131 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1132 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1133 : (TYPE_MODE (TYPE) == BLKmode \
1134 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1136 /* Don't default to pcc-struct-return, because we have already specified
1137 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1139 #define DEFAULT_PCC_STRUCT_RETURN 0
1141 #define SHMEDIA_REGS_STACK_ADJUST() \
1142 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1143 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1144 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1148 /* Define the classes of registers for register constraints in the
1149 machine description. Also define ranges of constants.
1151 One of the classes must always be named ALL_REGS and include all hard regs.
1152 If there is more than one class, another class must be named NO_REGS
1153 and contain no registers.
1155 The name GENERAL_REGS must be the name of a class (or an alias for
1156 another name such as ALL_REGS). This is the class of registers
1157 that is allowed by "g" or "r" in a register constraint.
1158 Also, registers outside this class are allocated only when
1159 instructions express preferences for them.
1161 The classes must be numbered in nondecreasing order; that is,
1162 a larger-numbered class must never be contained completely
1163 in a smaller-numbered class.
1165 For any two classes, it is very desirable that there be another
1166 class that represents their union. */
1168 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1169 be used as the destination of some of the arithmetic ops. There are
1170 also some special purpose registers; the T bit register, the
1171 Procedure Return Register and the Multiply Accumulate Registers. */
1172 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1173 reg_class_subunion. We don't want to have an actual union class
1174 of these, because it would only be used when both classes are calculated
1175 to give the same cost, but there is only one FPUL register.
1176 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1177 applying to the actual instruction alternative considered. E.g., the
1178 y/r alternative of movsi_ie is considered to have no more cost that
1179 the r/r alternative, which is patently untrue. */
1202 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1204 /* Give names of register classes as strings for dump file. */
1205 #define REG_CLASS_NAMES \
1220 "GENERAL_FP_REGS", \
1225 /* Define which registers fit in which classes.
1226 This is an initializer for a vector of HARD_REG_SET
1227 of length N_REG_CLASSES. */
1229 #define REG_CLASS_CONTENTS \
1232 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1234 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1236 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1238 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1240 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1242 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1243 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1244 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1245 /* GENERAL_REGS: */ \
1246 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1248 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1250 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1251 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1252 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1254 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1256 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1257 /* GENERAL_FP_REGS: */ \
1258 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1259 /* TARGET_REGS: */ \
1260 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1262 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1265 /* The same information, inverted:
1266 Return the class number of the smallest class containing
1267 reg number REGNO. This could be a conditional expression
1268 or could index an array. */
1270 extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
1271 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1273 /* When defined, the compiler allows registers explicitly used in the
1274 rtl to be used as spill registers but prevents the compiler from
1275 extending the lifetime of these registers. */
1277 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1279 /* The order in which register should be allocated. */
1280 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1281 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1282 spilled or used otherwise, we better have the FP_REGS allocated first. */
1283 #define REG_ALLOC_ORDER \
1284 {/* Caller-saved FPRs */ \
1285 65, 66, 67, 68, 69, 70, 71, 64, \
1286 72, 73, 74, 75, 80, 81, 82, 83, \
1287 84, 85, 86, 87, 88, 89, 90, 91, \
1288 92, 93, 94, 95, 96, 97, 98, 99, \
1289 /* Callee-saved FPRs */ \
1290 76, 77, 78, 79,100,101,102,103, \
1291 104,105,106,107,108,109,110,111, \
1292 112,113,114,115,116,117,118,119, \
1293 120,121,122,123,124,125,126,127, \
1294 136,137,138,139,140,141,142,143, \
1296 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1297 1, 2, 3, 7, 6, 5, 4, 0, \
1298 8, 9, 17, 19, 20, 21, 22, 23, \
1299 36, 37, 38, 39, 40, 41, 42, 43, \
1301 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1302 10, 11, 12, 13, 14, 18, \
1303 /* SH5 callee-saved GPRs */ \
1304 28, 29, 30, 31, 32, 33, 34, 35, \
1305 44, 45, 46, 47, 48, 49, 50, 51, \
1306 52, 53, 54, 55, 56, 57, 58, 59, \
1308 /* SH5 branch target registers */ \
1309 128,129,130,131,132,133,134,135, \
1310 /* Fixed registers */ \
1311 15, 16, 24, 25, 26, 27, 63,144, \
1312 145,146,147,148,149,152 }
1314 /* The class value for index registers, and the one for base regs. */
1315 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1316 #define BASE_REG_CLASS GENERAL_REGS
1318 /* Get reg_class from a letter such as appears in the machine
1320 extern enum reg_class reg_class_from_letter[];
1322 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1323 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1324 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1326 /* Overview of uppercase letter constraints:
1327 A: Addresses (constraint len == 3)
1328 Ac4: sh4 cache operations
1329 Ac5: sh5 cache operations
1330 Bxx: miscellaneous constraints
1331 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1333 C: Constants other than only CONST_INT (constraint len == 3)
1334 C16: 16 bit constant, literal or symbolic
1335 Csy: label or symbol
1336 Cpg: non-explicit constants that can be directly loaded into a general
1337 purpose register in PIC code. like 's' except we don't allow
1339 IJKLMNOP: CONT_INT constants
1341 J16: 0xffffffff00000000 | 0x00000000ffffffff
1342 Kxx: unsigned xx bit
1346 Q: pc relative load operand
1347 Rxx: reserved for exotic register classes.
1348 S: extra memory (storage) constraints (constraint len == 3)
1349 Sua: unaligned memory operations
1353 unused CONST_INT constraint letters: LO
1354 unused EXTRA_CONSTRAINT letters: D T U Y */
1356 #if 1 /* check that the transistion went well. */
1357 #define CONSTRAINT_LEN(C,STR) \
1358 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1360 || ((C) == 'I' && (((STR)[1] != '0' && (STR)[1] != '1') || ! isdigit ((STR)[2]))) \
1361 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1362 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1363 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1364 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1366 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1367 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1368 || (C) == 'R' || (C) == 'S') \
1370 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1372 #define CONSTRAINT_LEN(C,STR) \
1373 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1374 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1375 || (C) == 'R' || (C) == 'S') \
1376 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1379 /* The letters I, J, K, L and M in a register constraint string
1380 can be used to stand for particular ranges of immediate operands.
1381 This macro defines what the ranges are.
1382 C is the letter, and VALUE is a constant value.
1383 Return 1 if VALUE is in the range specified by C.
1384 I08: arithmetic operand -127..128, as used in add, sub, etc
1385 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1386 P27: shift operand 1,2,8 or 16
1387 K08: logical operand 0..255, as used in and, or, etc.
1390 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1391 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1394 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1395 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1396 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1397 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1398 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1399 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1400 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1401 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1402 #define CONST_OK_FOR_I(VALUE, STR) \
1403 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1404 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1405 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1406 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1409 #define CONST_OK_FOR_J16(VALUE) \
1410 (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff \
1411 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1412 #define CONST_OK_FOR_J(VALUE, STR) \
1413 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1416 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1417 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1418 #define CONST_OK_FOR_K(VALUE, STR) \
1419 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1421 #define CONST_OK_FOR_P27(VALUE) \
1422 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1423 #define CONST_OK_FOR_P(VALUE, STR) \
1424 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1426 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1427 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1428 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1429 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1430 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1431 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1432 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1433 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1434 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1437 /* Similar, but for floating constants, and defining letters G and H.
1438 Here VALUE is the CONST_DOUBLE rtx itself. */
1440 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1441 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1442 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1445 /* Given an rtx X being reloaded into a reg required to be
1446 in class CLASS, return the class of reg to actually use.
1447 In general this is just CLASS; but on some machines
1448 in some cases it is preferable to use a more restrictive class. */
1450 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1451 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1452 && (GET_CODE (X) == CONST_DOUBLE \
1453 || GET_CODE (X) == SYMBOL_REF) \
1457 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1458 ((((REGCLASS_HAS_FP_REG (CLASS) \
1459 && (GET_CODE (X) == REG \
1460 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1461 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1462 && TARGET_FMOVD)))) \
1463 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1464 && GET_CODE (X) == REG \
1465 && FP_REGISTER_P (REGNO (X)))) \
1466 && ! TARGET_SHMEDIA \
1467 && ((MODE) == SFmode || (MODE) == SImode)) \
1469 : (((CLASS) == FPUL_REGS \
1470 || (REGCLASS_HAS_FP_REG (CLASS) \
1471 && ! TARGET_SHMEDIA && MODE == SImode)) \
1472 && (GET_CODE (X) == MEM \
1473 || (GET_CODE (X) == REG \
1474 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1475 || REGNO (X) == T_REG \
1476 || system_reg_operand (X, VOIDmode))))) \
1478 : ((CLASS) == TARGET_REGS \
1479 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1480 ? ((target_operand ((X), (MODE)) \
1481 && ! target_reg_operand ((X), (MODE))) \
1482 ? NO_REGS : GENERAL_REGS) \
1483 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1484 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1485 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1487 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1488 && TARGET_REGISTER_P (REGNO (X))) \
1489 ? GENERAL_REGS : NO_REGS)
1491 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1492 ((REGCLASS_HAS_FP_REG (CLASS) \
1493 && ! TARGET_SHMEDIA \
1494 && immediate_operand ((X), (MODE)) \
1495 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1496 && (MODE) == SFmode && fldi_ok ())) \
1498 : (CLASS == FPUL_REGS \
1499 && ((GET_CODE (X) == REG \
1500 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1501 || REGNO (X) == T_REG)) \
1502 || GET_CODE (X) == PLUS)) \
1504 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1505 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1508 : (CLASS == FPSCR_REGS \
1509 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1510 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1512 : (REGCLASS_HAS_FP_REG (CLASS) \
1514 && immediate_operand ((X), (MODE)) \
1515 && (X) != CONST0_RTX (GET_MODE (X)) \
1516 && GET_MODE (X) != V4SFmode) \
1518 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1520 /* Return the maximum number of consecutive registers
1521 needed to represent mode MODE in a register of class CLASS.
1523 If TARGET_SHMEDIA, we need two FP registers per word.
1524 Otherwise we will need at most one register per word. */
1525 #define CLASS_MAX_NREGS(CLASS, MODE) \
1527 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1528 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1529 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1531 /* If defined, gives a class of registers that cannot be used as the
1532 operand of a SUBREG that changes the mode of the object illegally. */
1533 /* ??? We need to renumber the internal numbers for the frnn registers
1534 when in little endian in order to allow mode size changes. */
1536 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1537 sh_cannot_change_mode_class (FROM, TO, CLASS)
1539 /* Stack layout; function entry, exit and calling. */
1541 /* Define the number of registers that can hold parameters.
1542 These macros are used only in other macro definitions below. */
1544 #define NPARM_REGS(MODE) \
1545 (TARGET_FPU_ANY && (MODE) == SFmode \
1546 ? (TARGET_SH5 ? 12 : 8) \
1547 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1548 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1549 ? (TARGET_SH5 ? 12 : 8) \
1550 : (TARGET_SH5 ? 8 : 4))
1552 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1553 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1555 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1556 #define FIRST_FP_RET_REG FIRST_FP_REG
1558 /* Define this if pushing a word on the stack
1559 makes the stack pointer a smaller address. */
1560 #define STACK_GROWS_DOWNWARD
1562 /* Define this macro if the addresses of local variable slots are at
1563 negative offsets from the frame pointer.
1565 The SH only has positive indexes, so grow the frame up. */
1566 /* #define FRAME_GROWS_DOWNWARD */
1568 /* Offset from the frame pointer to the first local variable slot to
1570 #define STARTING_FRAME_OFFSET 0
1572 /* If we generate an insn to push BYTES bytes,
1573 this says how many the stack pointer really advances by. */
1574 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1575 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1576 do correct alignment. */
1578 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1581 /* Offset of first parameter from the argument pointer register value. */
1582 #define FIRST_PARM_OFFSET(FNDECL) 0
1584 /* Value is the number of byte of arguments automatically
1585 popped when returning from a subroutine call.
1586 FUNDECL is the declaration node of the function (as a tree),
1587 FUNTYPE is the data type of the function (as a tree),
1588 or for a library call it is an identifier node for the subroutine name.
1589 SIZE is the number of bytes of arguments passed on the stack.
1591 On the SH, the caller does not pop any of its arguments that were passed
1593 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1595 /* Value is the number of bytes of arguments automatically popped when
1596 calling a subroutine.
1597 CUM is the accumulated argument list.
1599 On SHcompact, the call trampoline pops arguments off the stack. */
1600 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1602 /* Nonzero if we do not know how to pass TYPE solely in registers.
1603 Values that come in registers with inconvenient padding are stored
1604 to memory at the function start. */
1606 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1608 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1609 || TREE_ADDRESSABLE (TYPE)))
1610 /* Some subroutine macros specific to this machine. */
1612 #define BASE_RETURN_VALUE_REG(MODE) \
1613 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1614 ? FIRST_FP_RET_REG \
1615 : TARGET_FPU_ANY && (MODE) == SCmode \
1616 ? FIRST_FP_RET_REG \
1617 : (TARGET_FPU_DOUBLE \
1618 && ((MODE) == DFmode || (MODE) == SFmode \
1619 || (MODE) == DCmode || (MODE) == SCmode )) \
1620 ? FIRST_FP_RET_REG \
1623 #define BASE_ARG_REG(MODE) \
1624 ((TARGET_SH2E && ((MODE) == SFmode)) \
1625 ? FIRST_FP_PARM_REG \
1626 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1627 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1628 ? FIRST_FP_PARM_REG \
1631 /* Define how to find the value returned by a function.
1632 VALTYPE is the data type of the value (as a tree).
1633 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1634 otherwise, FUNC is 0.
1635 For the SH, this is like LIBCALL_VALUE, except that we must change the
1636 mode like PROMOTE_MODE does.
1637 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1638 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1640 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1642 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1643 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1644 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1645 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1646 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1647 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1648 || TREE_CODE (VALTYPE) == REAL_TYPE \
1649 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1650 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1651 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1653 /* Define how to find the value returned by a library function
1654 assuming the value has mode MODE. */
1655 #define LIBCALL_VALUE(MODE) \
1656 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1658 /* 1 if N is a possible register number for a function value. */
1659 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1660 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1661 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1663 /* 1 if N is a possible register number for function argument passing. */
1664 #define FUNCTION_ARG_REGNO_P(REGNO) \
1665 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1666 + NPARM_REGS (SImode))) \
1667 || (TARGET_FPU_ANY \
1668 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1669 + NPARM_REGS (SFmode))))
1671 /* Define a data type for recording info about an argument list
1672 during the scan of that argument list. This data type should
1673 hold all necessary information about the function itself
1674 and about the args processed so far, enough to enable macros
1675 such as FUNCTION_ARG to determine where the next arg should go.
1677 On SH, this is a single integer, which is a number of words
1678 of arguments scanned so far (including the invisible argument,
1679 if any, which holds the structure-value-address).
1680 Thus NARGREGS or more means all following args should go on the stack. */
1682 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1686 /* Nonzero if a prototype is available for the function. */
1688 /* The number of an odd floating-point register, that should be used
1689 for the next argument of type float. */
1690 int free_single_fp_reg;
1691 /* Whether we're processing an outgoing function call. */
1693 /* The number of general-purpose registers that should have been
1694 used to pass partial arguments, that are passed totally on the
1695 stack. On SHcompact, a call trampoline will pop them off the
1696 stack before calling the actual function, and, if the called
1697 function is implemented in SHcompact mode, the incoming arguments
1698 decoder will push such arguments back onto the stack. For
1699 incoming arguments, STACK_REGS also takes into account other
1700 arguments passed by reference, that the decoder will also push
1703 /* The number of general-purpose registers that should have been
1704 used to pass arguments, if the arguments didn't have to be passed
1707 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1711 /* call_cookie is a bitmask used by call expanders, as well as
1712 function prologue and epilogues, to allow SHcompact to comply
1713 with the SH5 32-bit ABI, that requires 64-bit registers to be
1714 used even though only the lower 32-bit half is visible in
1715 SHcompact mode. The strategy is to call SHmedia trampolines.
1717 The alternatives for each of the argument-passing registers are
1718 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1719 contents from the address in it; (d) add 8 to it, storing the
1720 result in the next register, then (c); (e) copy it from some
1721 floating-point register,
1723 Regarding copies from floating-point registers, r2 may only be
1724 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1725 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1726 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1727 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1730 The bit mask is structured as follows:
1732 - 1 bit to tell whether to set up a return trampoline.
1734 - 3 bits to count the number consecutive registers to pop off the
1737 - 4 bits for each of r9, r8, r7 and r6.
1739 - 3 bits for each of r5, r4, r3 and r2.
1741 - 3 bits set to 0 (the most significant ones)
1744 1098 7654 3210 9876 5432 1098 7654 3210
1745 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1746 2223 3344 4555 6666 7777 8888 9999 SSS-
1748 - If F is set, the register must be copied from an FP register,
1749 whose number is encoded in the remaining bits.
1751 - Else, if L is set, the register must be loaded from the address
1752 contained in it. If the P bit is *not* set, the address of the
1753 following dword should be computed first, and stored in the
1756 - Else, if P is set, the register alone should be popped off the
1759 - After all this processing, the number of registers represented
1760 in SSS will be popped off the stack. This is an optimization
1761 for pushing/popping consecutive registers, typically used for
1762 varargs and large arguments partially passed in registers.
1764 - If T is set, a return trampoline will be set up for 64-bit
1765 return values to be split into 2 32-bit registers. */
1766 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1767 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1768 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1769 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1770 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1771 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1772 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1773 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1774 #define CALL_COOKIE_INT_REG(REG, VAL) \
1775 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1776 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1777 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1781 #define CUMULATIVE_ARGS struct sh_args
1783 #define GET_SH_ARG_CLASS(MODE) \
1784 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1786 /* There's no mention of complex float types in the SH5 ABI, so we
1787 should presumably handle them as aggregate types. */ \
1788 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1790 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1791 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1792 ? SH_ARG_FLOAT : SH_ARG_INT)
1794 #define ROUND_ADVANCE(SIZE) \
1795 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1797 /* Round a register number up to a proper boundary for an arg of mode
1800 The SH doesn't care about double alignment, so we only
1801 round doubles to even regs when asked to explicitly. */
1803 #define ROUND_REG(CUM, MODE) \
1804 (((TARGET_ALIGN_DOUBLE \
1805 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1806 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1807 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1808 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1809 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1810 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1812 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1813 for a call to a function whose data type is FNTYPE.
1814 For a library call, FNTYPE is 0.
1816 On SH, the offset always starts at 0: the first parm reg is always
1817 the same reg for a given argument class.
1819 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1821 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1823 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1824 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1826 = (TARGET_HITACHI && FNTYPE \
1827 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1828 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1829 (CUM).arg_count[(int) SH_ARG_INT] \
1830 = (TARGET_SH5 && (FNTYPE) \
1831 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1832 (CUM).free_single_fp_reg = 0; \
1833 (CUM).outgoing = 1; \
1834 (CUM).stack_regs = 0; \
1835 (CUM).byref_regs = 0; \
1838 = (CALL_COOKIE_RET_TRAMP \
1839 (TARGET_SHCOMPACT && (FNTYPE) \
1840 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1841 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1842 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1843 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1844 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1846 == FIRST_RET_REG))); \
1849 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1851 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1853 = (CALL_COOKIE_RET_TRAMP \
1854 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1855 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1858 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1860 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1861 (CUM).outgoing = 0; \
1864 #define OLD_ARG_MODE(MODE, TYPE) \
1866 && (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE) \
1867 && (MODE) != BLKmode && GET_MODE_CLASS (MODE) != MODE_INT) \
1868 ? int_mode_for_mode (MODE) : (MODE))
1870 /* Update the data in CUM to advance over an argument
1871 of mode MODE and data type TYPE.
1872 (TYPE is null for libcalls where that information may not be
1875 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1877 enum machine_mode MODE_ = OLD_ARG_MODE ((MODE), (TYPE));\
1878 if ((CUM).force_mem) \
1879 (CUM).force_mem = 0; \
1880 else if (TARGET_SH5) \
1882 tree TYPE_ = ((CUM).byref && (TYPE) \
1883 ? TREE_TYPE (TYPE) \
1885 int dwords, numregs; \
1887 MODE_ = ((CUM).byref && (TYPE) \
1888 ? TYPE_MODE (TYPE_) : (MODE_)); \
1889 dwords = (((CUM).byref \
1891 : (MODE_) == BLKmode \
1892 ? int_size_in_bytes (TYPE_) \
1893 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1894 numregs = MIN (dwords, NPARM_REGS (SImode) \
1895 - (CUM).arg_count[(int) SH_ARG_INT]); \
1898 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1899 if (TARGET_SHCOMPACT \
1900 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1903 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1905 /* N.B. We want this also for outgoing. */\
1906 (CUM).stack_regs += numregs; \
1908 else if ((CUM).byref) \
1910 if (! (CUM).outgoing) \
1911 (CUM).stack_regs += numregs; \
1912 (CUM).byref_regs += numregs; \
1916 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1918 while (--numregs); \
1920 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1923 else if (dwords > numregs) \
1925 int pushregs = numregs; \
1927 if (TARGET_SHCOMPACT) \
1928 (CUM).stack_regs += numregs; \
1929 while (pushregs < NPARM_REGS (SImode) - 1 \
1930 && (CALL_COOKIE_INT_REG_GET \
1931 ((CUM).call_cookie, \
1932 NPARM_REGS (SImode) - pushregs) \
1936 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1940 if (numregs == NPARM_REGS (SImode)) \
1942 |= CALL_COOKIE_INT_REG (0, 1) \
1943 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1946 |= CALL_COOKIE_STACKSEQ (numregs); \
1949 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1950 && ((NAMED) || ! (CUM).prototype_p)) \
1952 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1953 (CUM).free_single_fp_reg = 0; \
1954 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1955 < NPARM_REGS (SFmode)) \
1958 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1959 NPARM_REGS (SFmode) \
1960 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1962 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1964 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1966 if ((CUM).outgoing && numregs > 0) \
1970 |= (CALL_COOKIE_INT_REG \
1971 ((CUM).arg_count[(int) SH_ARG_INT] \
1972 - numregs + ((numfpregs - 2) / 2), \
1973 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1974 - numfpregs) / 2)); \
1976 while (numfpregs -= 2); \
1978 else if ((MODE_) == SFmode && (NAMED) \
1979 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1980 < NPARM_REGS (SFmode))) \
1981 (CUM).free_single_fp_reg \
1982 = FIRST_FP_PARM_REG - numfpregs \
1983 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1987 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE_), (TYPE))) \
1988 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE_)] \
1989 = (ROUND_REG ((CUM), (MODE_)) \
1990 + ((MODE_) == BLKmode \
1991 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1992 : ROUND_ADVANCE (GET_MODE_SIZE (MODE_))))); \
1995 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1996 This macro is only used in this file. */
1998 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2000 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2001 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
2002 && ! (CUM).force_mem \
2004 ? ((MODE) == BLKmode \
2005 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2006 + int_size_in_bytes (TYPE)) \
2007 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2008 : ((ROUND_REG((CUM), (MODE)) \
2009 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2010 <= NPARM_REGS (MODE))) \
2011 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2013 /* Define where to put the arguments to a function.
2014 Value is zero to push the argument on the stack,
2015 or a hard register in which to store the argument.
2017 MODE is the argument's machine mode.
2018 TYPE is the data type of the argument (as a tree).
2019 This is null for libcalls where that information may
2021 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2022 the preceding args and about the function being called.
2023 NAMED is nonzero if this argument is a named parameter
2024 (otherwise it is an extra parameter matching an ellipsis).
2026 On SH the first args are normally in registers
2027 and the rest are pushed. Any arg that starts within the first
2028 NPARM_REGS words is at least partially passed in a register unless
2029 its data type forbids. */
2031 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2032 FUNCTION_ARG_1 ((CUM), OLD_ARG_MODE ((MODE), (TYPE)), (MODE), (TYPE), (NAMED))
2034 #define FUNCTION_ARG_1(CUM, MODE, NEW_MODE, TYPE, NAMED) \
2036 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2037 && ((NAMED) || !TARGET_HITACHI)) \
2038 ? gen_rtx_REG ((NEW_MODE), \
2039 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
2040 ^ ((MODE) == SFmode && TARGET_SH4 \
2041 && TARGET_LITTLE_ENDIAN != 0))) \
2043 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
2044 ? GEN_INT ((CUM).call_cookie) \
2045 /* The following test assumes unnamed arguments are promoted to \
2047 : (MODE) == SFmode && (CUM).free_single_fp_reg \
2048 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (NEW_MODE), (CUM).free_single_fp_reg) \
2049 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2050 && ((NAMED) || ! (CUM).prototype_p) \
2051 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
2052 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
2053 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (NEW_MODE)) \
2054 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (NEW_MODE), \
2056 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
2057 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2058 && (! TARGET_SHCOMPACT \
2059 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2060 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2061 (TYPE), (NAMED))))) \
2062 ? gen_rtx_REG ((NEW_MODE), (FIRST_PARM_REG \
2063 + (CUM).arg_count[(int) SH_ARG_INT])) \
2067 /* Whether an argument must be passed by reference. On SHcompact, we
2068 pretend arguments wider than 32-bits that would have been passed in
2069 registers are passed by reference, so that an SHmedia trampoline
2070 loads them into the full 64-bits registers. */
2071 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
2072 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
2073 || SHCOMPACT_BYREF ((CUM), OLD_ARG_MODE ((MODE), (TYPE)), (TYPE), (NAMED)))
2075 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
2077 = (TARGET_SHCOMPACT \
2078 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2079 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
2080 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2081 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
2082 >= NPARM_REGS (SFmode)))) \
2083 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2084 : GET_MODE_SIZE (MODE)) > 4 \
2085 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2086 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2088 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2089 : GET_MODE_SIZE (MODE)) \
2092 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2093 register in SHcompact mode, it must be padded in the most
2094 significant end. This means that passing it by reference wouldn't
2095 pad properly on a big-endian machine. In this particular case, we
2096 pass this argument on the stack, in a way that the call trampoline
2097 will load its value into the appropriate register. */
2098 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2099 ((MODE) == BLKmode \
2100 && TARGET_SHCOMPACT \
2101 && ! TARGET_LITTLE_ENDIAN \
2102 && int_size_in_bytes (TYPE) > 4 \
2103 && int_size_in_bytes (TYPE) < 8)
2105 /* Minimum alignment for an argument to be passed by callee-copy
2106 reference. We need such arguments to be aligned to 8 byte
2107 boundaries, because they'll be loaded using quad loads. */
2108 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2110 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2112 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2113 : GET_MODE_ALIGNMENT (MODE)) \
2114 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2116 /* The SH5 ABI requires floating-point arguments to be passed to
2117 functions without a prototype in both an FP register and a regular
2118 register or the stack. When passing the argument in both FP and
2119 general-purpose registers, list the FP register first. */
2120 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2126 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2127 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2128 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2133 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2134 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2135 + (CUM).arg_count[(int) SH_ARG_INT]) \
2136 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2137 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2140 /* The SH5 ABI requires regular registers or stack slots to be
2141 reserved for floating-point arguments. Registers are taken care of
2142 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2143 Unfortunately, there's no way to just reserve a stack slot, so
2144 we'll end up needlessly storing a copy of the argument in the
2145 stack. For incoming arguments, however, the PARALLEL will be
2146 optimized to the register-only form, and the value in the stack
2147 slot won't be used at all. */
2148 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2149 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2150 ? gen_rtx_REG ((MODE), (REG)) \
2151 : gen_rtx_PARALLEL ((MODE), \
2154 (VOIDmode, NULL_RTX, \
2157 (VOIDmode, gen_rtx_REG ((MODE), \
2161 #define STRICT_ARGUMENT_NAMING TARGET_SH5
2163 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
2165 /* For an arg passed partly in registers and partly in memory,
2166 this is the number of registers used.
2167 For args passed entirely in registers or entirely in memory, zero.
2169 We sometimes split args. */
2171 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2173 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2175 && (ROUND_REG ((CUM), (MODE)) \
2176 + ((MODE) != BLKmode \
2177 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2178 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2179 > NPARM_REGS (MODE))) \
2180 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2181 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2182 && ! TARGET_SHCOMPACT) \
2183 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2186 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2188 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2189 || (MODE) == DCmode) \
2190 && ((CUM).arg_count[(int) SH_ARG_INT] \
2191 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2193 /* Perform any needed actions needed for a function that is receiving a
2194 variable number of arguments. */
2196 /* We actually emit the code in sh_expand_prologue. We used to use
2197 a static variable to flag that we need to emit this code, but that
2198 doesn't when inlining, when functions are deferred and then emitted
2199 later. Fortunately, we already have two flags that are part of struct
2200 function that tell if a function uses varargs or stdarg. */
2201 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2202 if (! current_function_stdarg) \
2206 /* Define the `__builtin_va_list' type for the ABI. */
2207 #define BUILD_VA_LIST_TYPE(VALIST) \
2208 (VALIST) = sh_build_va_list ()
2210 /* Implement `va_start' for varargs and stdarg. */
2211 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2212 sh_va_start (valist, nextarg)
2214 /* Implement `va_arg'. */
2215 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2216 sh_va_arg (valist, type)
2218 /* Call the function profiler with a given profile label.
2219 We use two .aligns, so as to make sure that both the .long is aligned
2220 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2221 from the trapa instruction. */
2223 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2225 fprintf((STREAM), "\t.align\t2\n"); \
2226 fprintf((STREAM), "\ttrapa\t#33\n"); \
2227 fprintf((STREAM), "\t.align\t2\n"); \
2228 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2231 /* Define this macro if the code for function profiling should come
2232 before the function prologue. Normally, the profiling code comes
2235 #define PROFILE_BEFORE_PROLOGUE
2237 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2238 the stack pointer does not matter. The value is tested only in
2239 functions that have frame pointers.
2240 No definition is equivalent to always zero. */
2242 #define EXIT_IGNORE_STACK 1
2245 On the SH, the trampoline looks like
2246 2 0002 D202 mov.l l2,r2
2247 1 0000 D301 mov.l l1,r3
2250 5 0008 00000000 l1: .long area
2251 6 000c 00000000 l2: .long function */
2253 /* Length in units of the trampoline for entering a nested function. */
2254 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2256 /* Alignment required for a trampoline in bits . */
2257 #define TRAMPOLINE_ALIGNMENT \
2258 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2259 : TARGET_SHMEDIA ? 256 : 64)
2261 /* Emit RTL insns to initialize the variable parts of a trampoline.
2262 FNADDR is an RTX for the address of the function's pure code.
2263 CXT is an RTX for the static chain value for the function. */
2265 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2266 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2268 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2270 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2272 if (TARGET_SHMEDIA) \
2273 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2274 gen_reg_rtx (Pmode), 0, \
2278 /* A C expression whose value is RTL representing the value of the return
2279 address for the frame COUNT steps up from the current frame.
2280 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2281 can ignore COUNT. */
2283 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2285 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2288 /* A C expression whose value is RTL representing the location of the
2289 incoming return address at the beginning of any function, before the
2290 prologue. This RTL is either a REG, indicating that the return
2291 value is saved in REG, or a MEM representing a location in
2293 #define INCOMING_RETURN_ADDR_RTX \
2294 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2296 /* Generate necessary RTL for __builtin_saveregs(). */
2297 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2299 /* Addressing modes, and classification of registers for them. */
2300 #define HAVE_POST_INCREMENT TARGET_SH1
2301 #define HAVE_PRE_DECREMENT TARGET_SH1
2303 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2305 #define USE_LOAD_PRE_DECREMENT(mode) 0
2306 #define USE_STORE_POST_INCREMENT(mode) 0
2307 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2310 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2311 < (TARGET_SMALLCODE ? 2 : \
2312 ((ALIGN >= 32) ? 16 : 2)))
2314 /* Macros to check register numbers against specific register classes. */
2316 /* These assume that REGNO is a hard or pseudo reg number.
2317 They give nonzero only if REGNO is a hard reg of the suitable class
2318 or a pseudo reg currently allocated to a suitable hard reg.
2319 Since they use reg_renumber, they are safe only once reg_renumber
2320 has been allocated, which happens in local-alloc.c. */
2322 #define REGNO_OK_FOR_BASE_P(REGNO) \
2323 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2324 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2325 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2327 ? (GENERAL_REGISTER_P (REGNO) \
2328 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2329 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2331 /* Maximum number of registers that can appear in a valid memory
2334 #define MAX_REGS_PER_ADDRESS 2
2336 /* Recognize any constant value that is a valid address. */
2338 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2340 /* Nonzero if the constant value X is a legitimate general operand. */
2342 #define LEGITIMATE_CONSTANT_P(X) \
2344 ? ((GET_MODE (X) != DFmode \
2345 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2346 || (X) == CONST0_RTX (GET_MODE (X)) \
2347 || ! TARGET_SHMEDIA_FPU \
2348 || TARGET_SHMEDIA64) \
2349 : (GET_CODE (X) != CONST_DOUBLE \
2350 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2351 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2353 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2354 and check its validity for a certain class.
2355 We have two alternate definitions for each of them.
2356 The usual definition accepts all pseudo regs; the other rejects
2357 them unless they have been allocated suitable hard regs.
2358 The symbol REG_OK_STRICT causes the latter definition to be used. */
2360 #ifndef REG_OK_STRICT
2362 /* Nonzero if X is a hard reg that can be used as a base reg
2363 or if it is a pseudo reg. */
2364 #define REG_OK_FOR_BASE_P(X) \
2365 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2367 /* Nonzero if X is a hard reg that can be used as an index
2368 or if it is a pseudo reg. */
2369 #define REG_OK_FOR_INDEX_P(X) \
2370 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2371 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2373 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2374 or if X is a pseudo reg. */
2375 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2376 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2377 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2381 /* Nonzero if X is a hard reg that can be used as a base reg. */
2382 #define REG_OK_FOR_BASE_P(X) \
2383 REGNO_OK_FOR_BASE_P (REGNO (X))
2385 /* Nonzero if X is a hard reg that can be used as an index. */
2386 #define REG_OK_FOR_INDEX_P(X) \
2387 REGNO_OK_FOR_INDEX_P (REGNO (X))
2389 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2390 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2391 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2395 /* The 'Q' constraint is a pc relative load operand. */
2396 #define EXTRA_CONSTRAINT_Q(OP) \
2397 (GET_CODE (OP) == MEM \
2398 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2399 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2400 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2401 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2402 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2404 /* Extra address constraints. */
2405 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2407 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2408 operand is not SCRATCH (i.e. REG) then R0 is probably being
2409 used, hence mova is being used, hence do not select this pattern */
2410 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2411 #define EXTRA_CONSTRAINT_B(OP, STR) \
2412 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2415 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2416 #define EXTRA_CONSTRAINT_C16(OP) \
2417 (GET_CODE (OP) == CONST \
2418 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2419 && GET_MODE (XEXP ((OP), 0)) == DImode \
2420 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2421 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2422 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2423 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2424 && (MOVI_SHORI_BASE_OPERAND_P \
2425 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2426 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2429 /* Check whether OP is a datalabel unspec. */
2430 #define DATALABEL_REF_NO_CONST_P(OP) \
2431 (GET_CODE (OP) == UNSPEC \
2432 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2433 && XVECLEN ((OP), 0) == 1 \
2434 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2435 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2437 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2439 #define DATALABEL_REF_P(OP) \
2440 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2441 || DATALABEL_REF_NO_CONST_P (OP))
2443 #define GOT_ENTRY_P(OP) \
2444 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2445 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2447 #define GOTPLT_ENTRY_P(OP) \
2448 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2449 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2451 #define UNSPEC_GOTOFF_P(OP) \
2452 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2454 #define GOTOFF_P(OP) \
2455 (GET_CODE (OP) == CONST \
2456 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2457 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2458 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2459 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2461 #define PIC_ADDR_P(OP) \
2462 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2463 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2465 #define PIC_OFFSET_P(OP) \
2467 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2468 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2470 #define PIC_DIRECT_ADDR_P(OP) \
2471 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2473 #define NON_PIC_REFERENCE_P(OP) \
2474 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2475 || DATALABEL_REF_P (OP) \
2476 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2477 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2478 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2479 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2481 #define PIC_REFERENCE_P(OP) \
2482 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2483 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2485 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2487 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2488 || PIC_OFFSET_P (OP)) \
2489 : NON_PIC_REFERENCE_P (OP))
2491 /* The `Csy' constraint is a label or a symbol. */
2492 #define EXTRA_CONSTRAINT_Csy(OP) \
2493 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2495 /* A zero in any shape or form. */
2496 #define EXTRA_CONSTRAINT_Z(OP) \
2497 ((OP) == CONST0_RTX (GET_MODE (OP)))
2499 /* Any vector constant we can handle. */
2500 #define EXTRA_CONSTRAINT_W(OP) \
2501 (GET_CODE (OP) == CONST_VECTOR \
2502 && (sh_rep_vec ((OP), VOIDmode) \
2503 || (HOST_BITS_PER_WIDE_INT >= 64 \
2504 ? sh_const_vec ((OP), VOIDmode) \
2505 : sh_1el_vec ((OP), VOIDmode))))
2507 /* A non-explicit constant that can be loaded directly into a general purpose
2508 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2509 #define EXTRA_CONSTRAINT_Cpg(OP) \
2511 && GET_CODE (OP) != CONST_INT \
2512 && GET_CODE (OP) != CONST_DOUBLE \
2514 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2515 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2516 && GET_CODE (OP) != LABEL_REF)))
2517 #define EXTRA_CONSTRAINT_C(OP, STR) \
2518 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2519 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2520 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2523 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2524 #define EXTRA_CONSTRAINT_Sr0(OP) \
2525 (memory_operand((OP), GET_MODE (OP)) \
2526 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2527 #define EXTRA_CONSTRAINT_S(OP, STR) \
2528 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2531 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2532 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2533 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2534 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2535 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2536 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2537 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2538 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2541 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2542 that is a valid memory address for an instruction.
2543 The MODE argument is the machine mode for the MEM expression
2544 that wants to use this address. */
2546 #define MODE_DISP_OK_4(X,MODE) \
2547 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2548 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2550 #define MODE_DISP_OK_8(X,MODE) \
2551 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2552 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2554 #define BASE_REGISTER_RTX_P(X) \
2555 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2556 || (GET_CODE (X) == SUBREG \
2557 && GET_CODE (SUBREG_REG (X)) == REG \
2558 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2560 /* Since this must be r0, which is a single register class, we must check
2561 SUBREGs more carefully, to be sure that we don't accept one that extends
2562 outside the class. */
2563 #define INDEX_REGISTER_RTX_P(X) \
2564 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2565 || (GET_CODE (X) == SUBREG \
2566 && GET_CODE (SUBREG_REG (X)) == REG \
2567 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2569 /* Jump to LABEL if X is a valid address RTX. This must also take
2570 REG_OK_STRICT into account when deciding about valid registers, but it uses
2571 the above macros so we are in luck.
2579 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2580 into the FRx registers. We implement this by setting the maximum offset
2581 to zero when the value is SFmode. This also restricts loading of SFmode
2582 values into the integer registers, but that can't be helped. */
2584 /* The SH allows a displacement in a QI or HI amode, but only when the
2585 other operand is R0. GCC doesn't handle this very well, so we forgo
2588 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2589 DI can be any number 0..60. */
2591 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2593 if (GET_CODE (OP) == CONST_INT) \
2595 if (TARGET_SHMEDIA) \
2597 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2598 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2599 && INTVAL (OP) >= -512 * MODE_SIZE \
2600 && INTVAL (OP) < 512 * MODE_SIZE) \
2605 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2606 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2610 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2612 if (BASE_REGISTER_RTX_P (X)) \
2614 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2615 && ! TARGET_SHMEDIA \
2616 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2618 else if (GET_CODE (X) == PLUS \
2619 && ((MODE) != PSImode || reload_completed)) \
2621 rtx xop0 = XEXP ((X), 0); \
2622 rtx xop1 = XEXP ((X), 1); \
2623 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2624 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2625 if (GET_MODE_SIZE (MODE) <= 4 \
2626 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2627 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2629 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2631 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2637 /* Try machine-dependent ways of modifying an illegitimate address
2638 to be legitimate. If we find one, return the new, valid address.
2639 This macro is used in only one place: `memory_address' in explow.c.
2641 OLDX is the address as it was before break_out_memory_refs was called.
2642 In some cases it is useful to look at this to decide what needs to be done.
2644 MODE and WIN are passed so that this macro can use
2645 GO_IF_LEGITIMATE_ADDRESS.
2647 It is always safe for this macro to do nothing. It exists to recognize
2648 opportunities to optimize the output.
2650 For the SH, if X is almost suitable for indexing, but the offset is
2651 out of range, convert it into a normal form so that cse has a chance
2652 of reducing the number of address registers used. */
2654 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2657 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2658 if (GET_CODE (X) == PLUS \
2659 && (GET_MODE_SIZE (MODE) == 4 \
2660 || GET_MODE_SIZE (MODE) == 8) \
2661 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2662 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2663 && ! TARGET_SHMEDIA \
2664 && ! (TARGET_SH4 && (MODE) == DFmode) \
2665 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2667 rtx index_rtx = XEXP ((X), 1); \
2668 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2671 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2672 /* On rare occasions, we might get an unaligned pointer \
2673 that is indexed in a way to give an aligned address. \
2674 Therefore, keep the lower two bits in offset_base. */ \
2675 /* Instead of offset_base 128..131 use 124..127, so that \
2676 simple add suffices. */ \
2679 offset_base = ((offset + 4) & ~60) - 4; \
2682 offset_base = offset & ~60; \
2683 /* Sometimes the normal form does not suit DImode. We \
2684 could avoid that by using smaller ranges, but that \
2685 would give less optimized code when SImode is \
2687 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2689 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2690 GEN_INT (offset_base), NULL_RTX, 0, \
2693 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2699 /* A C compound statement that attempts to replace X, which is an address
2700 that needs reloading, with a valid memory address for an operand of
2701 mode MODE. WIN is a C statement label elsewhere in the code.
2703 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2704 of the address. That will allow inheritance of the address reloads. */
2706 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2708 if (GET_CODE (X) == PLUS \
2709 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2710 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2711 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2712 && ! TARGET_SHMEDIA \
2713 && ! (TARGET_SH4 && (MODE) == DFmode) \
2714 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2716 rtx index_rtx = XEXP (X, 1); \
2717 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2720 if (TARGET_SH2E && MODE == SFmode) \
2723 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2724 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2728 /* Instead of offset_base 128..131 use 124..127, so that \
2729 simple add suffices. */ \
2732 offset_base = ((offset + 4) & ~60) - 4; \
2735 offset_base = offset & ~60; \
2736 /* Sometimes the normal form does not suit DImode. We \
2737 could avoid that by using smaller ranges, but that \
2738 would give less optimized code when SImode is \
2740 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2742 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2743 GEN_INT (offset_base)); \
2744 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2745 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2746 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2751 /* We must re-recognize what we created before. */ \
2752 else if (GET_CODE (X) == PLUS \
2753 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2754 && GET_CODE (XEXP (X, 0)) == PLUS \
2755 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2756 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2757 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2758 && ! TARGET_SHMEDIA \
2759 && ! (TARGET_SH2E && MODE == SFmode)) \
2761 /* Because this address is so complex, we know it must have \
2762 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2763 it is already unshared, and needs no further unsharing. */ \
2764 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2765 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2770 /* Go to LABEL if ADDR (a legitimate address expression)
2771 has an effect that depends on the machine mode it is used for.
2773 ??? Strictly speaking, we should also include all indexed addressing,
2774 because the index scale factor is the length of the operand.
2775 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2776 high if we did that. So we rely on reload to fix things up. */
2778 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2780 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2784 /* Specify the machine mode that this machine uses
2785 for the index in the tablejump instruction. */
2786 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2788 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2789 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2790 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2791 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2792 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2793 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2796 /* Define as C expression which evaluates to nonzero if the tablejump
2797 instruction expects the table to contain offsets from the address of the
2799 Do not define this if the table should contain absolute addresses. */
2800 #define CASE_VECTOR_PC_RELATIVE 1
2802 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2803 #define FLOAT_TYPE_SIZE 32
2805 /* Since the SH2e has only `float' support, it is desirable to make all
2806 floating point types equivalent to `float'. */
2807 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2809 /* 'char' is signed by default. */
2810 #define DEFAULT_SIGNED_CHAR 1
2812 /* The type of size_t unsigned int. */
2813 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2816 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2818 #define WCHAR_TYPE "short unsigned int"
2819 #define WCHAR_TYPE_SIZE 16
2821 #define SH_ELF_WCHAR_TYPE "long int"
2823 /* Don't cse the address of the function being compiled. */
2824 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2826 /* Max number of bytes we can move from memory to memory
2827 in one reasonably fast instruction. */
2828 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2830 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2831 MOVE_MAX is not a compile-time constant. */
2832 #define MAX_MOVE_MAX 8
2834 /* Max number of bytes we want move_by_pieces to be able to copy
2836 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2838 /* Define if operations between registers always perform the operation
2839 on the full register even if a narrower mode is specified. */
2840 #define WORD_REGISTER_OPERATIONS
2842 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2843 will either zero-extend or sign-extend. The value of this macro should
2844 be the code that says which one of the two operations is implicitly
2845 done, NIL if none. */
2846 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2847 /* FP registers can load SImode values, but don't implicitly sign-extend
2849 #define LOAD_EXTEND_OP(MODE) \
2850 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2851 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2853 /* Define if loading short immediate values into registers sign extends. */
2854 #define SHORT_IMMEDIATES_SIGN_EXTEND
2856 /* Nonzero if access to memory by bytes is no faster than for words. */
2857 #define SLOW_BYTE_ACCESS 1
2859 /* Immediate shift counts are truncated by the output routines (or was it
2860 the assembler?). Shift counts in a register are truncated by SH. Note
2861 that the native compiler puts too large (> 32) immediate shift counts
2862 into a register and shifts by the register, letting the SH decide what
2863 to do instead of doing that itself. */
2864 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2865 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2866 expects - the sign bit is significant - so it appears that we need to
2867 leave this zero for correct SH3 code. */
2868 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2870 /* All integers have the same format so truncation is easy. */
2871 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2873 /* Define this if addresses of constant functions
2874 shouldn't be put through pseudo regs where they can be cse'd.
2875 Desirable on machines where ordinary constants are expensive
2876 but a CALL with constant address is cheap. */
2877 /*#define NO_FUNCTION_CSE 1*/
2879 /* Chars and shorts should be passed as ints. */
2880 #define PROMOTE_PROTOTYPES 1
2882 /* The machine modes of pointers and functions. */
2883 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2884 #define FUNCTION_MODE Pmode
2886 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2887 are actually function calls with some special constraints on arguments
2890 These macros tell reorg that the references to arguments and
2891 register clobbers for insns of type sfunc do not appear to happen
2892 until after the millicode call. This allows reorg to put insns
2893 which set the argument registers into the delay slot of the millicode
2894 call -- thus they act more like traditional CALL_INSNs.
2896 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2897 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2900 #define INSN_SETS_ARE_DELAYED(X) \
2901 ((GET_CODE (X) == INSN \
2902 && GET_CODE (PATTERN (X)) != SEQUENCE \
2903 && GET_CODE (PATTERN (X)) != USE \
2904 && GET_CODE (PATTERN (X)) != CLOBBER \
2905 && get_attr_is_sfunc (X)))
2907 #define INSN_REFERENCES_ARE_DELAYED(X) \
2908 ((GET_CODE (X) == INSN \
2909 && GET_CODE (PATTERN (X)) != SEQUENCE \
2910 && GET_CODE (PATTERN (X)) != USE \
2911 && GET_CODE (PATTERN (X)) != CLOBBER \
2912 && get_attr_is_sfunc (X)))
2915 /* Position Independent Code. */
2917 /* We can't directly access anything that contains a symbol,
2918 nor can we indirect via the constant pool. */
2919 #define LEGITIMATE_PIC_OPERAND_P(X) \
2920 ((! nonpic_symbol_mentioned_p (X) \
2921 && (GET_CODE (X) != SYMBOL_REF \
2922 || ! CONSTANT_POOL_ADDRESS_P (X) \
2923 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2924 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2926 #define SYMBOLIC_CONST_P(X) \
2927 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2928 && nonpic_symbol_mentioned_p (X))
2930 /* Compute extra cost of moving data between one register class
2933 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2934 uses this information. Hence, the general register <-> floating point
2935 register information here is not used for SFmode. */
2937 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2938 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2939 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2941 #define REGCLASS_HAS_FP_REG(CLASS) \
2942 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2943 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2945 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2946 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2948 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2949 would be so that people with slow memory systems could generate
2950 different code that does fewer memory accesses. */
2952 /* A C expression for the cost of a branch instruction. A value of 1
2953 is the default; other values are interpreted relative to that.
2954 The SH1 does not have delay slots, hence we get a pipeline stall
2955 at every branch. The SH4 is superscalar, so the single delay slot
2956 is not sufficient to keep both pipelines filled. */
2957 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2959 /* Assembler output control. */
2961 /* A C string constant describing how to begin a comment in the target
2962 assembler language. The compiler assumes that the comment will end at
2963 the end of the line. */
2964 #define ASM_COMMENT_START "!"
2966 /* The text to go at the start of the assembler file. */
2967 #define ASM_FILE_START(STREAM) \
2968 output_file_start (STREAM)
2970 #define ASM_APP_ON ""
2971 #define ASM_APP_OFF ""
2972 #define FILE_ASM_OP "\t.file\n"
2973 #define SET_ASM_OP "\t.set\t"
2975 /* How to change between sections. */
2977 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2978 #define DATA_SECTION_ASM_OP "\t.data"
2980 #if defined CRT_BEGIN || defined CRT_END
2981 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2982 # undef TEXT_SECTION_ASM_OP
2983 # if __SHMEDIA__ == 1 && __SH5__ == 32
2984 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2986 # define TEXT_SECTION_ASM_OP "\t.text"
2991 /* If defined, a C expression whose value is a string containing the
2992 assembler operation to identify the following data as
2993 uninitialized global data. If not defined, and neither
2994 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2995 uninitialized global data will be output in the data section if
2996 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2998 #ifndef BSS_SECTION_ASM_OP
2999 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3002 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3003 separate, explicit argument. If you define this macro, it is used
3004 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3005 handling the required alignment of the variable. The alignment is
3006 specified as the number of bits.
3008 Try to use function `asm_output_aligned_bss' defined in file
3009 `varasm.c' when defining this macro. */
3010 #ifndef ASM_OUTPUT_ALIGNED_BSS
3011 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3012 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3015 /* Define this so that jump tables go in same section as the current function,
3016 which could be text or it could be a user defined section. */
3017 #define JUMP_TABLES_IN_TEXT_SECTION 1
3019 #undef DO_GLOBAL_CTORS_BODY
3020 #define DO_GLOBAL_CTORS_BODY \
3022 typedef (*pfunc)(); \
3023 extern pfunc __ctors[]; \
3024 extern pfunc __ctors_end[]; \
3026 for (p = __ctors_end; p > __ctors; ) \
3032 #undef DO_GLOBAL_DTORS_BODY
3033 #define DO_GLOBAL_DTORS_BODY \
3035 typedef (*pfunc)(); \
3036 extern pfunc __dtors[]; \
3037 extern pfunc __dtors_end[]; \
3039 for (p = __dtors; p < __dtors_end; p++) \
3045 #define ASM_OUTPUT_REG_PUSH(file, v) \
3046 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3048 #define ASM_OUTPUT_REG_POP(file, v) \
3049 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3051 /* DBX register number for a given compiler register number. */
3052 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3054 /* svr4.h undefines this macro, yet we really want to use the same numbers
3055 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3056 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3057 register exists, so we should return -1 for invalid register numbers. */
3058 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3060 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3061 (GENERAL_REGISTER_P (REGNO) \
3062 ? ((REGNO) - FIRST_GENERAL_REG) \
3063 : FP_REGISTER_P (REGNO) \
3064 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
3066 : XD_REGISTER_P (REGNO) \
3067 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3068 : TARGET_REGISTER_P (REGNO) \
3069 ? ((REGNO) - FIRST_TARGET_REG + 68) \
3070 : (REGNO) == PR_REG \
3071 ? (TARGET_SH5 ? 241 : 17) \
3072 : (REGNO) == PR_MEDIA_REG \
3073 ? (TARGET_SH5 ? 18 : -1) \
3074 : (REGNO) == T_REG \
3075 ? (TARGET_SH5 ? 242 : 18) \
3076 : (REGNO) == GBR_REG \
3077 ? (TARGET_SH5 ? 238 : 19) \
3078 : (REGNO) == MACH_REG \
3079 ? (TARGET_SH5 ? 239 : 20) \
3080 : (REGNO) == MACL_REG \
3081 ? (TARGET_SH5 ? 240 : 21) \
3082 : (REGNO) == FPUL_REG \
3083 ? (TARGET_SH5 ? 244 : 23) \
3086 /* This is how to output a reference to a symbol_ref. On SH5,
3087 references to non-code symbols must be preceded by `datalabel'. */
3088 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3091 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3092 fputs ("datalabel ", (FILE)); \
3093 assemble_name ((FILE), XSTR ((SYM), 0)); \
3097 /* This is how to output an assembler line
3098 that says to advance the location counter
3099 to a multiple of 2**LOG bytes. */
3101 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3103 fprintf ((FILE), "\t.align %d\n", (LOG))
3105 /* Globalizing directive for a label. */
3106 #define GLOBAL_ASM_OP "\t.global\t"
3108 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3110 /* Output a relative address table. */
3112 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3113 switch (GET_MODE (BODY)) \
3118 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3122 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3127 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3131 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3136 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3140 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3146 /* Output an absolute table element. */
3148 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3149 if (! optimize || TARGET_BIGTABLE) \
3150 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3152 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3155 /* A C statement to be executed just prior to the output of
3156 assembler code for INSN, to modify the extracted operands so
3157 they will be output differently.
3159 Here the argument OPVEC is the vector containing the operands
3160 extracted from INSN, and NOPERANDS is the number of elements of
3161 the vector which contain meaningful data for this insn.
3162 The contents of this vector are what will be used to convert the insn
3163 template into assembler code, so you can change the assembler output
3164 by changing the contents of the vector. */
3166 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3167 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3169 /* Print operand X (an rtx) in assembler syntax to file FILE.
3170 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3171 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3173 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3175 /* Print a memory address as an operand to reference that memory location. */
3177 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3179 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3180 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3181 || (CHAR) == '$'|| (CHAR) == '\'')
3183 /* Recognize machine-specific patterns that may appear within
3184 constants. Used for PIC-specific UNSPECs. */
3185 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3187 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3189 switch (XINT ((X), 1)) \
3191 case UNSPEC_DATALABEL: \
3192 fputs ("datalabel ", (STREAM)); \
3193 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3196 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3197 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3200 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3201 fputs ("@GOT", (STREAM)); \
3203 case UNSPEC_GOTOFF: \
3204 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3205 fputs ("@GOTOFF", (STREAM)); \
3208 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3209 fputs ("@PLT", (STREAM)); \
3211 case UNSPEC_GOTPLT: \
3212 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3213 fputs ("@GOTPLT", (STREAM)); \
3215 case UNSPEC_DTPOFF: \
3216 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3217 fputs ("@DTPOFF", (STREAM)); \
3219 case UNSPEC_GOTTPOFF: \
3220 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3221 fputs ("@GOTTPOFF", (STREAM)); \
3223 case UNSPEC_TPOFF: \
3224 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3225 fputs ("@TPOFF", (STREAM)); \
3227 case UNSPEC_CALLER: \
3230 /* LPCS stands for Label for PIC Call Site. */ \
3231 ASM_GENERATE_INTERNAL_LABEL \
3232 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3233 assemble_name ((STREAM), name); \
3246 extern struct rtx_def *sh_compare_op0;
3247 extern struct rtx_def *sh_compare_op1;
3249 /* Which processor to schedule for. The elements of the enumeration must
3250 match exactly the cpu attribute in the sh.md file. */
3252 enum processor_type {
3262 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3263 extern enum processor_type sh_cpu;
3265 extern int optimize; /* needed for gen_casesi. */
3267 enum mdep_reorg_phase_e
3269 SH_BEFORE_MDEP_REORG,
3270 SH_INSERT_USES_LABELS,
3271 SH_SHORTEN_BRANCHES0,
3273 SH_SHORTEN_BRANCHES1,
3277 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3279 /* Generate calls to memcpy, memcmp and memset. */
3281 #define TARGET_MEM_FUNCTIONS
3283 /* Handle Renesas compiler's pragmas. */
3284 #define REGISTER_TARGET_PRAGMAS() do { \
3285 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3286 c_register_pragma (0, "trapa", sh_pr_trapa); \
3287 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3290 /* Set when processing a function with pragma interrupt turned on. */
3292 extern int pragma_interrupt;
3294 /* Set when processing a function with interrupt attribute. */
3296 extern int current_function_interrupt;
3298 /* Set to an RTX containing the address of the stack to switch to
3299 for interrupt functions. */
3300 extern struct rtx_def *sp_switch;
3302 extern int rtx_equal_function_value_matters;
3305 /* Instructions with unfilled delay slots take up an
3306 extra two bytes for the nop in the delay slot.
3307 sh-dsp parallel processing insns are four bytes long. */
3309 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3310 (LENGTH) += sh_insn_length_adjustment (X);
3312 /* Define the codes that are matched by predicates in sh.c. */
3313 #define PREDICATE_CODES \
3314 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3315 {"any_register_operand", {SUBREG, REG}}, \
3316 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3317 {"arith_reg_dest", {SUBREG, REG}}, \
3318 {"arith_reg_operand", {SUBREG, REG}}, \
3319 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3320 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3321 {"binary_logical_operator", {AND, IOR, XOR}}, \
3322 {"commutative_float_operator", {PLUS, MULT}}, \
3323 {"equality_comparison_operator", {EQ,NE}}, \
3324 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3325 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3326 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3327 {"fpscr_operand", {REG}}, \
3328 {"fpul_operand", {REG}}, \
3329 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3330 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3331 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3332 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3333 {"int_gpr_dest", {SUBREG, REG}}, \
3334 {"inqhi_operand", {TRUNCATE}}, \
3335 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3336 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3337 {"mextr_bit_offset", {CONST_INT}}, \
3338 {"noncommutative_float_operator", {MINUS, DIV}}, \
3339 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3340 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3341 {"target_reg_operand", {SUBREG, REG}}, \
3342 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3343 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3344 {"register_operand", {SUBREG, REG}}, \
3345 {"sh_const_vec", {CONST_VECTOR}}, \
3346 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3347 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3348 {"symbol_ref_operand", {SYMBOL_REF}}, \
3349 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3351 #define SPECIAL_MODE_PREDICATES \
3352 "any_register_operand", \
3354 "trunc_hi_operand", \
3355 /* This line intentionally left blank. */
3357 #define any_register_operand register_operand
3359 /* Define this macro if it is advisable to hold scalars in registers
3360 in a wider mode than that declared by the program. In such cases,
3361 the value is constrained to be within the bounds of the declared
3362 type, but kept valid in the wider mode. The signedness of the
3363 extension may differ from that of the type.
3365 Leaving the unsignedp unchanged gives better code than always setting it
3366 to 0. This is despite the fact that we have only signed char and short
3367 load instructions. */
3368 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3369 if (GET_MODE_CLASS (MODE) == MODE_INT \
3370 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3371 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3372 (MODE) = (TARGET_SH1 ? SImode : DImode);
3374 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3375 extensions applied to char/short functions arguments. Defining
3376 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3378 #define PROMOTE_FUNCTION_ARGS
3379 #define PROMOTE_FUNCTION_RETURN
3381 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3383 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3384 and poping arguments. However, we do have push/pop instructions, and
3385 rather limited offsets (4 bits) in load/store instructions, so it isn't
3386 clear if this would give better code. If implemented, should check for
3387 compatibility problems. */
3389 #define SH_DYNAMIC_SHIFT_COST \
3390 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3393 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3395 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3397 #define ACTUAL_NORMAL_MODE(ENTITY) \
3398 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3400 #define NORMAL_MODE(ENTITY) \
3401 (sh_cfun_interrupt_handler_p () \
3402 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3403 : ACTUAL_NORMAL_MODE (ENTITY))
3405 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3406 && (REGNO) == FPSCR_REG)
3408 #define MODE_NEEDED(ENTITY, INSN) \
3409 (recog_memoized (INSN) >= 0 \
3410 ? get_attr_fp_mode (INSN) \
3413 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3414 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3416 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3417 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3419 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3420 sh_can_redirect_branch ((INSN), (SEQ))
3422 #define DWARF_FRAME_RETURN_COLUMN \
3423 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3425 #define EH_RETURN_DATA_REGNO(N) \
3426 ((N) < 4 ? (N) + (TARGET_SH5 ? 2 : 4) : INVALID_REGNUM)
3428 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)
3430 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3431 /* SH constant pool breaks the devices in crtstuff.c to control section
3432 in where code resides. We have to write it as asm code. */
3433 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3434 asm (SECTION_OP "\n\
3440 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3441 2:\n" TEXT_SECTION_ASM_OP);
3442 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3444 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3445 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3446 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3448 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3449 ? (plus_constant (arg_pointer_rtx, \
3450 TARGET_SHMEDIA64 ? -8 : -4)) \
3451 : frame_pointer_rtx)) \
3454 #endif /* ! GCC_SH_H */
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