1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
49 builtin_define ("__sh3__"); \
50 builtin_define ("__SH3__"); \
51 if (TARGET_HARD_SH4) \
52 builtin_define ("__SH4_NOFPU__"); \
54 case PROCESSOR_SH3E: \
55 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
58 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
62 builtin_define_with_value ("__SH5__", \
63 TARGET_SHMEDIA64 ? "64" : "32", 0); \
64 builtin_define_with_value ("__SHMEDIA__", \
65 TARGET_SHMEDIA ? "1" : "0", 0); \
66 if (! TARGET_FPU_DOUBLE) \
67 builtin_define ("__SH4_NOFPU__"); \
71 builtin_define ("__HITACHI__"); \
72 builtin_define (TARGET_LITTLE_ENDIAN \
73 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
76 builtin_define ("__pic__"); \
77 builtin_define ("__PIC__"); \
79 TARGET_OBJFMT_CPP_BUILTINS (); \
82 /* We can not debug without a frame pointer. */
83 /* #define CAN_DEBUG_WITHOUT_FP */
85 #define CONDITIONAL_REGISTER_USAGE do \
88 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
89 if (! VALID_REGISTER_P (regno)) \
90 fixed_regs[regno] = call_used_regs[regno] = 1; \
91 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
93 call_used_regs[FIRST_GENERAL_REG + 8] \
94 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
97 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
98 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
99 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
103 /* Hitachi saves and restores mac registers on call. */ \
104 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
106 call_used_regs[MACH_REG] = 0; \
107 call_used_regs[MACL_REG] = 0; \
109 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
110 regno <= LAST_FP_REG; regno += 2) \
111 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
112 if (TARGET_SHMEDIA) \
114 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
115 if (! fixed_regs[regno] && call_used_regs[regno]) \
116 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
119 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
120 if (! fixed_regs[regno] && call_used_regs[regno]) \
121 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
124 /* ??? Need to write documentation for all SH options and add it to the
127 /* Run-time compilation parameters selecting different hardware subsets. */
129 extern int target_flags;
130 #define ISIZE_BIT (1<<1)
131 #define DALIGN_BIT (1<<6)
132 #define SH1_BIT (1<<8)
133 #define SH2_BIT (1<<9)
134 #define SH3_BIT (1<<10)
135 #define SH3E_BIT (1<<11)
136 #define HARD_SH4_BIT (1<<5)
137 #define FPU_SINGLE_BIT (1<<7)
138 #define SH4_BIT (1<<12)
139 #define FMOVD_BIT (1<<4)
140 #define SH5_BIT (1<<0)
141 #define SPACE_BIT (1<<13)
142 #define BIGTABLE_BIT (1<<14)
143 #define RELAX_BIT (1<<15)
144 #define USERMODE_BIT (1<<16)
145 #define HITACHI_BIT (1<<22)
146 #define NOMACSAVE_BIT (1<<23)
147 #define PREFERGOT_BIT (1<<24)
148 #define PADSTRUCT_BIT (1<<28)
149 #define LITTLE_ENDIAN_BIT (1<<29)
150 #define IEEE_BIT (1<<30)
152 /* Nonzero if we should dump out instruction size info. */
153 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
155 /* Nonzero to align doubles on 64 bit boundaries. */
156 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
158 /* Nonzero if we should generate code using type 1 insns. */
159 #define TARGET_SH1 (target_flags & SH1_BIT)
161 /* Nonzero if we should generate code using type 2 insns. */
162 #define TARGET_SH2 (target_flags & SH2_BIT)
164 /* Nonzero if we should generate code using type 3 insns. */
165 #define TARGET_SH3 (target_flags & SH3_BIT)
167 /* Nonzero if we should generate code using type 3E insns. */
168 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
170 /* Nonzero if the cache line size is 32. */
171 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
173 /* Nonzero if we schedule for a superscalar implementation. */
174 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
176 /* Nonzero if the target has separate instruction and data caches. */
177 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
179 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
180 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
182 /* Nonzero if the default precision of th FPU is single */
183 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
185 /* Nonzero if a double-precision FPU is available. */
186 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
188 /* Nonzero if an FPU is available. */
189 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
191 /* Nonzero if we should generate code using type 4 insns. */
192 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
194 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
195 #define TARGET_SH5 (target_flags & SH5_BIT)
197 /* Nonzero if we should generate code using the SHcompact instruction
198 set and 32-bit ABI. */
199 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
201 /* Nonzero if we should generate code using the SHmedia instruction
203 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
205 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
207 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
208 && (target_flags & SH3E_BIT))
210 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
212 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
213 && ! (target_flags & SH3E_BIT))
215 /* Nonzero if we should generate code using SHmedia FPU instructions. */
216 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
217 /* Nonzero if we should generate fmovd. */
218 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
220 /* Nonzero if we respect NANs. */
221 #define TARGET_IEEE (target_flags & IEEE_BIT)
223 /* Nonzero if we should generate smaller code rather than faster code. */
224 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
226 /* Nonzero to use long jump tables. */
227 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
229 /* Nonzero to generate pseudo-ops needed by the assembler and linker
230 to do function call relaxing. */
231 #define TARGET_RELAX (target_flags & RELAX_BIT)
233 /* Nonzero if using Hitachi's calling convention. */
234 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
236 /* Nonzero if not saving macl/mach when using -mhitachi */
237 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
239 /* Nonzero if padding structures to a multiple of 4 bytes. This is
240 incompatible with Hitachi's compiler, and gives unusual structure layouts
241 which confuse programmers.
242 ??? This option is not useful, but is retained in case there are people
243 who are still relying on it. It may be deleted in the future. */
244 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
246 /* Nonzero if generating code for a little endian SH. */
247 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
249 /* Nonzero if we should do everything in userland. */
250 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
252 /* Nonzero if we should prefer @GOT calls when generating PIC. */
253 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
255 #define SELECT_SH1 (SH1_BIT)
256 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
257 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
258 #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
259 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
260 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
261 #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
262 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
263 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
264 #define SELECT_SH5_64_NOFPU (SH5_BIT)
265 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
266 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
267 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
268 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
270 /* Reset all target-selection flags. */
271 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
272 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
274 #define TARGET_SWITCHES \
275 { {"1", TARGET_NONE, "" }, \
276 {"1", SELECT_SH1, "" }, \
277 {"2", TARGET_NONE, "" }, \
278 {"2", SELECT_SH2, "" }, \
279 {"3", TARGET_NONE, "" }, \
280 {"3", SELECT_SH3, "" }, \
281 {"3e", TARGET_NONE, "" }, \
282 {"3e", SELECT_SH3E, "" }, \
283 {"4-single-only", TARGET_NONE, "" }, \
284 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
285 {"4-single", TARGET_NONE, "" }, \
286 {"4-single", SELECT_SH4_SINGLE, "" },\
287 {"4-nofpu", TARGET_NONE, "" }, \
288 {"4-nofpu", SELECT_SH4_NOFPU, "" },\
289 {"4", TARGET_NONE, "" }, \
290 {"4", SELECT_SH4, "" }, \
291 {"5-64media", TARGET_NONE, "" }, \
292 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
293 {"5-64media-nofpu", TARGET_NONE, "" }, \
294 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
295 {"5-32media", TARGET_NONE, "" }, \
296 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
297 {"5-32media-nofpu", TARGET_NONE, "" }, \
298 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
299 {"5-compact", TARGET_NONE, "" }, \
300 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
301 {"5-compact-nofpu", TARGET_NONE, "" }, \
302 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
303 {"b", -LITTLE_ENDIAN_BIT, "" }, \
304 {"bigtable", BIGTABLE_BIT, "" }, \
305 {"dalign", DALIGN_BIT, "" }, \
306 {"fmovd", FMOVD_BIT, "" }, \
307 {"hitachi", HITACHI_BIT, "" }, \
308 {"nomacsave", NOMACSAVE_BIT, "" }, \
309 {"ieee", IEEE_BIT, "" }, \
310 {"isize", ISIZE_BIT, "" }, \
311 {"l", LITTLE_ENDIAN_BIT, "" }, \
312 {"no-ieee", -IEEE_BIT, "" }, \
313 {"padstruct", PADSTRUCT_BIT, "" }, \
314 {"prefergot", PREFERGOT_BIT, "" }, \
315 {"relax", RELAX_BIT, "" }, \
316 {"space", SPACE_BIT, "" }, \
317 {"usermode", USERMODE_BIT, "" }, \
319 {"", TARGET_DEFAULT, "" } \
322 /* This are meant to be redefined in the host dependent files */
323 #define SUBTARGET_SWITCHES
325 /* This defaults us to big-endian. */
326 #ifndef TARGET_ENDIAN_DEFAULT
327 #define TARGET_ENDIAN_DEFAULT 0
330 #ifndef TARGET_CPU_DEFAULT
331 #define TARGET_CPU_DEFAULT SELECT_SH1
334 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
336 #define CPP_SPEC " %(subtarget_cpp_spec) "
338 #ifndef SUBTARGET_CPP_SPEC
339 #define SUBTARGET_CPP_SPEC ""
342 #ifndef SUBTARGET_EXTRA_SPECS
343 #define SUBTARGET_EXTRA_SPECS
346 #define EXTRA_SPECS \
347 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
348 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
349 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
350 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
351 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
352 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
353 SUBTARGET_EXTRA_SPECS
355 #define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
357 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
358 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
359 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
361 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
365 #define LINK_EMUL_PREFIX "sh%{ml:l}"
367 #if TARGET_CPU_DEFAULT & SH5_BIT
368 #if TARGET_CPU_DEFAULT & SH3E_BIT
369 #define LINK_DEFAULT_CPU_EMUL "32"
371 #define LINK_DEFAULT_CPU_EMUL "64"
372 #endif /* SH3E_BIT */
374 #define LINK_DEFAULT_CPU_EMUL ""
377 #define SUBTARGET_LINK_EMUL_SUFFIX ""
378 #define SUBTARGET_LINK_SPEC ""
380 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
381 so that we can undo the damage without code replication. */
382 #define LINK_SPEC SH_LINK_SPEC
384 #define SH_LINK_SPEC "\
385 -m %(link_emul_prefix)\
386 %{m5-compact*|m5-32media*:32}\
388 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
389 %(subtarget_link_emul_suffix) \
390 %{mrelax:-relax} %(subtarget_link_spec)"
392 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
395 flag_omit_frame_pointer = -1; \
397 target_flags |= SPACE_BIT; \
400 #define ASSEMBLER_DIALECT assembler_dialect
402 extern int assembler_dialect;
404 #define OVERRIDE_OPTIONS \
409 assembler_dialect = 0; \
418 assembler_dialect = 1; \
424 target_flags |= DALIGN_BIT; \
426 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
427 target_flags |= FMOVD_BIT; \
428 if (TARGET_SHMEDIA) \
430 /* There are no delay slots on SHmedia. */ \
431 flag_delayed_branch = 0; \
432 /* Relaxation isn't yet supported for SHmedia */ \
433 target_flags &= ~RELAX_BIT; \
435 if (profile_flag || profile_arc_flag) \
437 warning ("Profiling is not supported on this target."); \
438 profile_flag = profile_arc_flag = 0; \
443 /* Only the sh64-elf assembler fully supports .quad properly. */\
444 targetm.asm_out.aligned_op.di = NULL; \
445 targetm.asm_out.unaligned_op.di = NULL; \
448 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
449 if (! VALID_REGISTER_P (regno)) \
450 sh_register_names[regno][0] = '\0'; \
452 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
453 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
454 sh_additional_register_names[regno][0] = '\0'; \
456 if (flag_omit_frame_pointer < 0) \
458 /* The debugging information is sufficient, \
459 but gdb doesn't implement this yet */ \
461 flag_omit_frame_pointer \
462 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
463 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
465 flag_omit_frame_pointer = 0; \
468 if (flag_pic && ! TARGET_PREFERGOT) \
469 flag_no_function_cse = 1; \
471 /* Never run scheduling before reload, since that can \
472 break global alloc, and generates slower code anyway due \
473 to the pressure on R0. */ \
474 flag_schedule_insns = 0; \
476 /* Allocation boundary (in *bytes*) for the code of a function. \
477 SH1: 32 bit alignment is faster, because instructions are always \
478 fetched as a pair from a longword boundary. \
479 SH2 .. SH5 : align to cache line start. */ \
480 if (align_functions == 0) \
482 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
485 /* Target machine storage layout. */
487 /* Define this if most significant bit is lowest numbered
488 in instructions that operate on numbered bit-fields. */
490 #define BITS_BIG_ENDIAN 0
492 /* Define this if most significant byte of a word is the lowest numbered. */
493 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
495 /* Define this if most significant word of a multiword number is the lowest
497 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
499 /* Define this to set the endianness to use in libgcc2.c, which can
500 not depend on target_flags. */
501 #if defined(__LITTLE_ENDIAN__)
502 #define LIBGCC2_WORDS_BIG_ENDIAN 0
504 #define LIBGCC2_WORDS_BIG_ENDIAN 1
507 #define MAX_BITS_PER_WORD 64
509 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
511 /* Width in bits of an `int'. We want just 32-bits, even if words are
513 #define INT_TYPE_SIZE 32
515 /* Width in bits of a `long'. */
516 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
518 /* Width in bits of a `long long'. */
519 #define LONG_LONG_TYPE_SIZE 64
521 /* Width in bits of a `long double'. */
522 #define LONG_DOUBLE_TYPE_SIZE 64
524 /* Width of a word, in units (bytes). */
525 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
526 #define MIN_UNITS_PER_WORD 4
528 /* Width in bits of a pointer.
529 See also the macro `Pmode' defined below. */
530 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
532 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
533 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
535 /* Boundary (in *bits*) on which stack pointer should be aligned. */
536 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
538 /* The log (base 2) of the cache line size, in bytes. Processors prior to
539 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
540 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
541 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
543 /* ABI given & required minimum allocation boundary (in *bits*) for the
544 code of a function. */
545 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
547 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
548 the vbit must go into the delta field of
549 pointers-to-member-functions. */
550 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
551 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
553 /* Alignment of field after `int : 0' in a structure. */
554 #define EMPTY_FIELD_BOUNDARY 32
556 /* No data type wants to be aligned rounder than this. */
557 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
559 /* The best alignment to use in cases where we have a choice. */
560 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
562 /* Make strings word-aligned so strcpy from constants will be faster. */
563 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
564 ((TREE_CODE (EXP) == STRING_CST \
565 && (ALIGN) < FASTEST_ALIGNMENT) \
566 ? FASTEST_ALIGNMENT : (ALIGN))
568 /* Make arrays of chars word-aligned for the same reasons. */
569 #define DATA_ALIGNMENT(TYPE, ALIGN) \
570 (TREE_CODE (TYPE) == ARRAY_TYPE \
571 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
572 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
574 /* Number of bits which any structure or union's size must be a
575 multiple of. Each structure or union's size is rounded up to a
577 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
579 /* Set this nonzero if move instructions will actually fail to work
580 when given unaligned data. */
581 #define STRICT_ALIGNMENT 1
583 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
584 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
585 barrier_align (LABEL_AFTER_BARRIER)
587 #define LOOP_ALIGN(A_LABEL) \
588 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
589 ? 0 : sh_loop_align (A_LABEL))
591 #define LABEL_ALIGN(A_LABEL) \
593 (PREV_INSN (A_LABEL) \
594 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
595 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
596 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
597 /* explicit alignment insn in constant tables. */ \
598 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
601 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
602 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
604 /* The base two logarithm of the known minimum alignment of an insn length. */
605 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
606 (GET_CODE (A_INSN) == INSN \
607 ? 1 << TARGET_SHMEDIA \
608 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
609 ? 1 << TARGET_SHMEDIA \
612 /* Standard register usage. */
614 /* Register allocation for the Hitachi calling convention:
620 r14 frame pointer/call saved
622 ap arg pointer (doesn't really exist, always eliminated)
623 pr subroutine return address
625 mach multiply/accumulate result, high part
626 macl multiply/accumulate result, low part.
627 fpul fp/int communication register
628 rap return address pointer register
630 fr1..fr3 scratch floating point registers
632 fr12..fr15 call saved floating point registers */
634 #define MAX_REGISTER_NAME_LENGTH 5
635 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
637 #define SH_REGISTER_NAMES_INITIALIZER \
639 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
640 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
641 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
642 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
643 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
644 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
645 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
646 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
647 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
648 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
649 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
650 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
651 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
652 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
653 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
654 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
655 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
656 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
657 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
661 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
663 #define REGNAMES_ARR_INDEX_1(index) \
664 (sh_register_names[index])
665 #define REGNAMES_ARR_INDEX_2(index) \
666 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
667 #define REGNAMES_ARR_INDEX_4(index) \
668 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
669 #define REGNAMES_ARR_INDEX_8(index) \
670 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
671 #define REGNAMES_ARR_INDEX_16(index) \
672 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
673 #define REGNAMES_ARR_INDEX_32(index) \
674 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
675 #define REGNAMES_ARR_INDEX_64(index) \
676 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
678 #define REGISTER_NAMES \
680 REGNAMES_ARR_INDEX_64 (0), \
681 REGNAMES_ARR_INDEX_64 (64), \
682 REGNAMES_ARR_INDEX_8 (128), \
683 REGNAMES_ARR_INDEX_8 (136), \
684 REGNAMES_ARR_INDEX_8 (144), \
685 REGNAMES_ARR_INDEX_1 (152) \
688 #define ADDREGNAMES_SIZE 32
689 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
690 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
691 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
693 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
695 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
696 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
697 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
698 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
701 #define ADDREGNAMES_REGNO(index) \
702 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
705 #define ADDREGNAMES_ARR_INDEX_1(index) \
706 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
707 #define ADDREGNAMES_ARR_INDEX_2(index) \
708 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
709 #define ADDREGNAMES_ARR_INDEX_4(index) \
710 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
711 #define ADDREGNAMES_ARR_INDEX_8(index) \
712 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
713 #define ADDREGNAMES_ARR_INDEX_16(index) \
714 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
715 #define ADDREGNAMES_ARR_INDEX_32(index) \
716 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
718 #define ADDITIONAL_REGISTER_NAMES \
720 ADDREGNAMES_ARR_INDEX_32 (0) \
723 /* Number of actual hardware registers.
724 The hardware registers are assigned numbers for the compiler
725 from 0 to just below FIRST_PSEUDO_REGISTER.
726 All registers that the compiler knows about must be given numbers,
727 even those that are not normally considered general registers. */
729 /* There are many other relevant definitions in sh.md's md_constants. */
731 #define FIRST_GENERAL_REG R0_REG
732 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
733 #define FIRST_FP_REG DR0_REG
734 #define LAST_FP_REG (FIRST_FP_REG + \
735 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
736 #define FIRST_XD_REG XD0_REG
737 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
738 #define FIRST_TARGET_REG TR0_REG
739 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
741 #define GENERAL_REGISTER_P(REGNO) \
742 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
744 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
745 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
747 #define FP_REGISTER_P(REGNO) \
748 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
750 #define XD_REGISTER_P(REGNO) \
751 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
753 #define FP_OR_XD_REGISTER_P(REGNO) \
754 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
756 #define FP_ANY_REGISTER_P(REGNO) \
757 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
759 #define SPECIAL_REGISTER_P(REGNO) \
760 ((REGNO) == GBR_REG || (REGNO) == T_REG \
761 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
763 #define TARGET_REGISTER_P(REGNO) \
764 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
766 #define SHMEDIA_REGISTER_P(REGNO) \
767 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
768 || TARGET_REGISTER_P (REGNO))
770 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
771 that should be fixed. */
772 #define VALID_REGISTER_P(REGNO) \
773 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
774 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
775 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
776 || (TARGET_SH3E && (REGNO) == FPUL_REG))
778 /* The mode that should be generally used to store a register by
779 itself in the stack, or to load it back. */
780 #define REGISTER_NATURAL_MODE(REGNO) \
781 (FP_REGISTER_P (REGNO) ? SFmode \
782 : XD_REGISTER_P (REGNO) ? DFmode \
783 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
787 #define FIRST_PSEUDO_REGISTER 153
789 /* 1 for registers that have pervasive standard uses
790 and are not available for the register allocator.
792 Mach register is fixed 'cause it's only 10 bits wide for SH1.
793 It is 32 bits wide for SH2. */
795 #define FIXED_REGISTERS \
797 /* Regular registers. */ \
798 0, 0, 0, 0, 0, 0, 0, 0, \
799 0, 0, 0, 0, 0, 0, 0, 1, \
800 /* r16 is reserved, r18 is the former pr. */ \
801 1, 0, 0, 0, 0, 0, 0, 0, \
802 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
803 /* r26 is a global variable data pointer; r27 is for constants. */ \
804 1, 1, 1, 1, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 0, \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 0, 0, 0, 0, 0, 0, 0, 1, \
809 /* FP registers. */ \
810 0, 0, 0, 0, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 0, \
817 0, 0, 0, 0, 0, 0, 0, 0, \
818 /* Branch target registers. */ \
819 0, 0, 0, 0, 0, 0, 0, 0, \
820 /* XD registers. */ \
821 0, 0, 0, 0, 0, 0, 0, 0, \
822 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
823 1, 1, 1, 1, 1, 1, 0, 1, \
828 /* 1 for registers not available across function calls.
829 These must include the FIXED_REGISTERS and also any
830 registers that can be used without being saved.
831 The latter must include the registers where values are returned
832 and the register where structure-value addresses are passed.
833 Aside from that, you can include as many other registers as you like. */
835 #define CALL_USED_REGISTERS \
837 /* Regular registers. */ \
838 1, 1, 1, 1, 1, 1, 1, 1, \
839 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
840 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
841 across SH5 function calls. */ \
842 0, 0, 0, 0, 0, 0, 0, 1, \
843 1, 1, 0, 1, 1, 1, 1, 1, \
844 1, 1, 1, 1, 0, 0, 0, 0, \
845 0, 0, 0, 0, 1, 1, 1, 1, \
846 1, 1, 1, 1, 0, 0, 0, 0, \
847 0, 0, 0, 0, 0, 0, 0, 0, \
848 0, 0, 0, 0, 1, 1, 1, 1, \
849 /* FP registers. */ \
850 1, 1, 1, 1, 1, 1, 1, 1, \
851 1, 1, 1, 1, 0, 0, 0, 0, \
852 1, 1, 1, 1, 1, 1, 1, 1, \
853 1, 1, 1, 1, 1, 1, 1, 1, \
854 1, 1, 1, 1, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, \
856 0, 0, 0, 0, 0, 0, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 /* Branch target registers. */ \
859 1, 1, 1, 1, 1, 0, 0, 0, \
860 /* XD registers. */ \
861 1, 1, 1, 1, 1, 1, 0, 0, \
862 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
863 1, 1, 0, 1, 1, 1, 1, 1, \
868 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
869 across SHcompact function calls. We can't tell whether a called
870 function is SHmedia or SHcompact, so we assume it may be when
871 compiling SHmedia code with the 32-bit ABI, since that's the only
872 ABI that can be linked with SHcompact code. */
873 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
875 && GET_MODE_SIZE (MODE) > 4 \
876 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
877 && (REGNO) <= FIRST_GENERAL_REG + 14) \
878 || (REGNO) == PR_MEDIA_REG))
880 /* Return number of consecutive hard regs needed starting at reg REGNO
881 to hold something of mode MODE.
882 This is ordinarily the length in words of a value of mode MODE
883 but can be less for certain modes in special long registers.
885 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
887 #define HARD_REGNO_NREGS(REGNO, MODE) \
888 (XD_REGISTER_P (REGNO) \
889 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
890 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
891 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
892 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
894 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
895 We can allow any mode in any general register. The special registers
896 only allow SImode. Don't allow any mode in the PR. */
898 /* We cannot hold DCmode values in the XD registers because alter_reg
899 handles subregs of them incorrectly. We could work around this by
900 spacing the XD registers like the DR registers, but this would require
901 additional memory in every compilation to hold larger register vectors.
902 We could hold SFmode / SCmode values in XD registers, but that
903 would require a tertiary reload when reloading from / to memory,
904 and a secondary reload to reload from / to general regs; that
905 seems to be a loosing proposition. */
906 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
907 it won't be ferried through GP registers first. */
908 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
909 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
910 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
911 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
913 : (MODE) == V2SFmode \
914 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
915 || (TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
916 : (MODE) == V4SFmode \
917 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
918 : (MODE) == V16SFmode \
920 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
921 : (REGNO) == FIRST_XD_REG) \
922 : FP_REGISTER_P (REGNO) \
923 ? ((MODE) == SFmode \
924 || (TARGET_SHMEDIA && (MODE) == SImode) \
925 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
926 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
927 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
928 || (MODE) == V2SFmode || (MODE) == TImode))) \
929 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
930 : XD_REGISTER_P (REGNO) \
932 : TARGET_REGISTER_P (REGNO) \
933 ? ((MODE) == DImode || (MODE) == SImode) \
934 : (REGNO) == PR_REG ? 0 \
935 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
938 /* Value is 1 if MODE is a supported vector mode. */
939 #define VECTOR_MODE_SUPPORTED_P(MODE) \
941 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
943 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
944 || (MODE) == V2SImode)))
946 /* Value is 1 if it is a good idea to tie two pseudo registers
947 when one has mode MODE1 and one has mode MODE2.
948 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
949 for any hard reg, then this must be 0 for correct output.
950 That's the case for xd registers: we don't hold SFmode values in
951 them, so we can't tie an SFmode pseudos with one in another
952 floating-point mode. */
954 #define MODES_TIEABLE_P(MODE1, MODE2) \
955 ((MODE1) == (MODE2) \
956 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
957 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
958 && (GET_MODE_SIZE (MODE2) <= 4)) \
959 : ((MODE1) != SFmode && (MODE2) != SFmode))))
961 /* A C expression that is nonzero if hard register NEW_REG can be
962 considered for use as a rename register for OLD_REG register */
964 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
965 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
967 /* Specify the registers used for certain standard purposes.
968 The values of these macros are register numbers. */
970 /* Define this if the program counter is overloaded on a register. */
971 /* #define PC_REGNUM 15*/
973 /* Register to use for pushing function arguments. */
974 #define STACK_POINTER_REGNUM SP_REG
976 /* Base register for access to local variables of the function. */
977 #define FRAME_POINTER_REGNUM FP_REG
979 /* Fake register that holds the address on the stack of the
980 current function's return address. */
981 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
983 /* Register to hold the addressing base for position independent
984 code access to data items. */
985 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
987 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
989 /* Value should be nonzero if functions must have frame pointers.
990 Zero means the frame pointer need not be set up (and parms may be accessed
991 via the stack pointer) in functions that seem suitable. */
993 #define FRAME_POINTER_REQUIRED 0
995 /* Definitions for register eliminations.
997 We have three registers that can be eliminated on the SH. First, the
998 frame pointer register can often be eliminated in favor of the stack
999 pointer register. Secondly, the argument pointer register can always be
1000 eliminated; it is replaced with either the stack or frame pointer.
1001 Third, there is the return address pointer, which can also be replaced
1002 with either the stack or the frame pointer. */
1004 /* This is an array of structures. Each structure initializes one pair
1005 of eliminable registers. The "from" register number is given first,
1006 followed by "to". Eliminations of the same "from" register are listed
1007 in order of preference. */
1009 /* If you add any registers here that are not actually hard registers,
1010 and that have any alternative of elimination that doesn't always
1011 apply, you need to amend calc_live_regs to exclude it, because
1012 reload spills all eliminable registers where it sees an
1013 can_eliminate == 0 entry, thus making them 'live' .
1014 If you add any hard registers that can be eliminated in different
1015 ways, you have to patch reload to spill them only when all alternatives
1016 of elimination fail. */
1018 #define ELIMINABLE_REGS \
1019 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1020 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1021 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1022 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1023 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1025 /* Given FROM and TO register numbers, say whether this elimination
1027 #define CAN_ELIMINATE(FROM, TO) \
1028 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1030 /* Define the offset between two registers, one to be eliminated, and the other
1031 its replacement, at the start of a routine. */
1033 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1034 OFFSET = initial_elimination_offset ((FROM), (TO))
1036 /* Base register for access to arguments of the function. */
1037 #define ARG_POINTER_REGNUM AP_REG
1039 /* Register in which the static-chain is passed to a function. */
1040 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1042 /* The register in which a struct value address is passed. */
1044 #define STRUCT_VALUE_REGNUM 2
1046 /* If the structure value address is not passed in a register, define
1047 `STRUCT_VALUE' as an expression returning an RTX for the place
1048 where the address is passed. If it returns 0, the address is
1049 passed as an "invisible" first argument. */
1051 /* The Hitachi calling convention doesn't quite fit into this scheme since
1052 the address is passed like an invisible argument, but one that is always
1053 passed in memory. */
1054 #define STRUCT_VALUE \
1055 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1057 #define RETURN_IN_MEMORY(TYPE) \
1059 ? ((TYPE_MODE (TYPE) == BLKmode \
1060 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1061 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1062 : (TYPE_MODE (TYPE) == BLKmode \
1063 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1065 /* Don't default to pcc-struct-return, because we have already specified
1066 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1068 #define DEFAULT_PCC_STRUCT_RETURN 0
1070 #define SHMEDIA_REGS_STACK_ADJUST() \
1071 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1072 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1073 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1077 /* Define the classes of registers for register constraints in the
1078 machine description. Also define ranges of constants.
1080 One of the classes must always be named ALL_REGS and include all hard regs.
1081 If there is more than one class, another class must be named NO_REGS
1082 and contain no registers.
1084 The name GENERAL_REGS must be the name of a class (or an alias for
1085 another name such as ALL_REGS). This is the class of registers
1086 that is allowed by "g" or "r" in a register constraint.
1087 Also, registers outside this class are allocated only when
1088 instructions express preferences for them.
1090 The classes must be numbered in nondecreasing order; that is,
1091 a larger-numbered class must never be contained completely
1092 in a smaller-numbered class.
1094 For any two classes, it is very desirable that there be another
1095 class that represents their union. */
1097 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1098 be used as the destination of some of the arithmetic ops. There are
1099 also some special purpose registers; the T bit register, the
1100 Procedure Return Register and the Multiply Accumulate Registers. */
1101 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1102 reg_class_subunion. We don't want to have an actual union class
1103 of these, because it would only be used when both classes are calculated
1104 to give the same cost, but there is only one FPUL register.
1105 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1106 applying to the actual instruction alternative considered. E.g., the
1107 y/r alternative of movsi_ie is considered to have no more cost that
1108 the r/r alternative, which is patently untrue. */
1131 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1133 /* Give names of register classes as strings for dump file. */
1134 #define REG_CLASS_NAMES \
1149 "GENERAL_FP_REGS", \
1154 /* Define which registers fit in which classes.
1155 This is an initializer for a vector of HARD_REG_SET
1156 of length N_REG_CLASSES. */
1158 #define REG_CLASS_CONTENTS \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1163 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1167 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1169 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1171 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1172 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1173 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1174 /* GENERAL_REGS: */ \
1175 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1177 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1179 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1180 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1181 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1183 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1185 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1186 /* GENERAL_FP_REGS: */ \
1187 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1188 /* TARGET_REGS: */ \
1189 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1191 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1194 /* The same information, inverted:
1195 Return the class number of the smallest class containing
1196 reg number REGNO. This could be a conditional expression
1197 or could index an array. */
1199 extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
1200 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1202 /* When defined, the compiler allows registers explicitly used in the
1203 rtl to be used as spill registers but prevents the compiler from
1204 extending the lifetime of these registers. */
1206 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1208 /* The order in which register should be allocated. */
1209 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1210 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1211 spilled or used otherwise, we better have the FP_REGS allocated first. */
1212 #define REG_ALLOC_ORDER \
1213 { 65, 66, 67, 68, 69, 70, 71, 64, \
1214 72, 73, 74, 75, 76, 77, 78, 79, \
1215 136,137,138,139,140,141,142,143, \
1216 80, 81, 82, 83, 84, 85, 86, 87, \
1217 88, 89, 90, 91, 92, 93, 94, 95, \
1218 96, 97, 98, 99,100,101,102,103, \
1219 104,105,106,107,108,109,110,111, \
1220 112,113,114,115,116,117,118,119, \
1221 120,121,122,123,124,125,126,127, \
1222 151, 1, 2, 3, 7, 6, 5, 4, \
1223 0, 8, 9, 10, 11, 12, 13, 14, \
1224 16, 17, 18, 19, 20, 21, 22, 23, \
1225 24, 25, 26, 27, 28, 29, 30, 31, \
1226 32, 33, 34, 35, 36, 37, 38, 39, \
1227 40, 41, 42, 43, 44, 45, 46, 47, \
1228 48, 49, 50, 51, 52, 53, 54, 55, \
1229 56, 57, 58, 59, 60, 61, 62, 63, \
1230 150, 15,145,146,147,144,148,149, \
1231 128,129,130,131,132,133,134,135, \
1234 /* The class value for index registers, and the one for base regs. */
1235 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1236 #define BASE_REG_CLASS GENERAL_REGS
1238 /* Get reg_class from a letter such as appears in the machine
1240 extern const enum reg_class reg_class_from_letter[];
1242 #define REG_CLASS_FROM_LETTER(C) \
1243 ( ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1245 /* The letters I, J, K, L and M in a register constraint string
1246 can be used to stand for particular ranges of immediate operands.
1247 This macro defines what the ranges are.
1248 C is the letter, and VALUE is a constant value.
1249 Return 1 if VALUE is in the range specified by C.
1250 I: arithmetic operand -127..128, as used in add, sub, etc
1251 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1252 K: shift operand 1,2,8 or 16
1253 L: logical operand 0..255, as used in and, or, etc.
1256 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1257 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1260 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1261 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1262 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1263 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1264 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1265 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1266 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1267 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1268 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1269 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1270 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1271 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1272 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1273 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1274 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1275 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1276 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1277 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1278 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1279 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1280 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1281 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1284 /* Similar, but for floating constants, and defining letters G and H.
1285 Here VALUE is the CONST_DOUBLE rtx itself. */
1287 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1288 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1289 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1292 /* Given an rtx X being reloaded into a reg required to be
1293 in class CLASS, return the class of reg to actually use.
1294 In general this is just CLASS; but on some machines
1295 in some cases it is preferable to use a more restrictive class. */
1297 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1298 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1299 && (GET_CODE (X) == CONST_DOUBLE \
1300 || GET_CODE (X) == SYMBOL_REF) \
1304 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1305 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
1306 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) \
1307 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
1308 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
1309 && GET_CODE (X) == REG \
1310 && FP_REGISTER_P (REGNO (X)))) \
1311 && ! TARGET_SHMEDIA \
1312 && MODE == SFmode) \
1314 : ((CLASS) == FPUL_REGS \
1315 && (GET_CODE (X) == MEM \
1316 || (GET_CODE (X) == REG \
1317 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1318 || REGNO (X) == T_REG \
1319 || system_reg_operand (X, VOIDmode))))) \
1321 : ((CLASS) == TARGET_REGS \
1322 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1323 ? ((target_operand ((X), (MODE)) \
1324 && ! target_reg_operand ((X), (MODE))) \
1325 ? NO_REGS : GENERAL_REGS) \
1326 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1327 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1328 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1330 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1331 && TARGET_REGISTER_P (REGNO (X))) \
1332 ? GENERAL_REGS : NO_REGS)
1334 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1335 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS \
1336 || (CLASS) == DF_HI_REGS) \
1337 && ! TARGET_SHMEDIA \
1338 && immediate_operand ((X), (MODE)) \
1339 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1340 && (MODE) == SFmode && fldi_ok ())) \
1342 : (CLASS == FPUL_REGS \
1343 && ((GET_CODE (X) == REG \
1344 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1345 || REGNO (X) == T_REG)))) \
1347 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1348 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1351 : (CLASS == FPSCR_REGS \
1352 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1353 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1355 : (((CLASS) == FP_REGS || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)\
1357 && immediate_operand ((X), (MODE)) \
1358 && (X) != CONST0_RTX (GET_MODE (X)) \
1359 && GET_MODE (X) != V4SFmode) \
1361 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1363 /* Return the maximum number of consecutive registers
1364 needed to represent mode MODE in a register of class CLASS.
1366 On SH this is the size of MODE in words. */
1367 #define CLASS_MAX_NREGS(CLASS, MODE) \
1368 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1370 /* If defined, gives a class of registers that cannot be used as the
1371 operand of a SUBREG that changes the mode of the object illegally. */
1372 /* ??? We need to renumber the internal numbers for the frnn registers
1373 when in little endian in order to allow mode size changes. */
1375 #define CLASS_CANNOT_CHANGE_MODE (TARGET_LITTLE_ENDIAN ? DF_REGS : DF_HI_REGS)
1377 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1379 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1380 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1381 && ((TARGET_LITTLE_ENDIAN && GET_MODE_SIZE (TO) < 8) \
1382 || GET_MODE_SIZE (FROM) < 8))
1384 /* Stack layout; function entry, exit and calling. */
1386 /* Define the number of registers that can hold parameters.
1387 These macros are used only in other macro definitions below. */
1389 #define NPARM_REGS(MODE) \
1390 (TARGET_FPU_ANY && (MODE) == SFmode \
1391 ? (TARGET_SH5 ? 12 : 8) \
1392 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1393 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1394 ? (TARGET_SH5 ? 12 : 8) \
1395 : (TARGET_SH5 ? 8 : 4))
1397 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1398 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1400 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1401 #define FIRST_FP_RET_REG FIRST_FP_REG
1403 /* Define this if pushing a word on the stack
1404 makes the stack pointer a smaller address. */
1405 #define STACK_GROWS_DOWNWARD
1407 /* Define this macro if the addresses of local variable slots are at
1408 negative offsets from the frame pointer.
1410 The SH only has positive indexes, so grow the frame up. */
1411 /* #define FRAME_GROWS_DOWNWARD */
1413 /* Offset from the frame pointer to the first local variable slot to
1415 #define STARTING_FRAME_OFFSET 0
1417 /* If we generate an insn to push BYTES bytes,
1418 this says how many the stack pointer really advances by. */
1419 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1420 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1421 do correct alignment. */
1423 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1426 /* Offset of first parameter from the argument pointer register value. */
1427 #define FIRST_PARM_OFFSET(FNDECL) 0
1429 /* Value is the number of byte of arguments automatically
1430 popped when returning from a subroutine call.
1431 FUNDECL is the declaration node of the function (as a tree),
1432 FUNTYPE is the data type of the function (as a tree),
1433 or for a library call it is an identifier node for the subroutine name.
1434 SIZE is the number of bytes of arguments passed on the stack.
1436 On the SH, the caller does not pop any of its arguments that were passed
1438 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1440 /* Value is the number of bytes of arguments automatically popped when
1441 calling a subroutine.
1442 CUM is the accumulated argument list.
1444 On SHcompact, the call trampoline pops arguments off the stack. */
1445 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1447 /* Nonzero if we do not know how to pass TYPE solely in registers.
1448 Values that come in registers with inconvenient padding are stored
1449 to memory at the function start. */
1451 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1453 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1454 || TREE_ADDRESSABLE (TYPE)))
1455 /* Some subroutine macros specific to this machine. */
1457 #define BASE_RETURN_VALUE_REG(MODE) \
1458 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1459 ? FIRST_FP_RET_REG \
1460 : TARGET_FPU_ANY && (MODE) == SCmode \
1461 ? FIRST_FP_RET_REG \
1462 : (TARGET_FPU_DOUBLE \
1463 && ((MODE) == DFmode || (MODE) == SFmode \
1464 || (MODE) == DCmode || (MODE) == SCmode )) \
1465 ? FIRST_FP_RET_REG \
1468 #define BASE_ARG_REG(MODE) \
1469 ((TARGET_SH3E && ((MODE) == SFmode)) \
1470 ? FIRST_FP_PARM_REG \
1471 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1472 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1473 ? FIRST_FP_PARM_REG \
1476 /* Define how to find the value returned by a function.
1477 VALTYPE is the data type of the value (as a tree).
1478 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1479 otherwise, FUNC is 0.
1480 For the SH, this is like LIBCALL_VALUE, except that we must change the
1481 mode like PROMOTE_MODE does.
1482 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1483 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1485 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1487 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1488 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1489 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1490 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1491 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1492 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1493 || TREE_CODE (VALTYPE) == REAL_TYPE \
1494 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1495 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1496 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1498 /* Define how to find the value returned by a library function
1499 assuming the value has mode MODE. */
1500 #define LIBCALL_VALUE(MODE) \
1501 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1503 /* 1 if N is a possible register number for a function value. */
1504 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1505 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
1506 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1508 /* 1 if N is a possible register number for function argument passing. */
1509 #define FUNCTION_ARG_REGNO_P(REGNO) \
1510 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1511 + NPARM_REGS (SImode))) \
1512 || (TARGET_FPU_ANY \
1513 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1514 + NPARM_REGS (SFmode))))
1516 /* Define a data type for recording info about an argument list
1517 during the scan of that argument list. This data type should
1518 hold all necessary information about the function itself
1519 and about the args processed so far, enough to enable macros
1520 such as FUNCTION_ARG to determine where the next arg should go.
1522 On SH, this is a single integer, which is a number of words
1523 of arguments scanned so far (including the invisible argument,
1524 if any, which holds the structure-value-address).
1525 Thus NARGREGS or more means all following args should go on the stack. */
1527 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1531 /* Non-zero if a prototype is available for the function. */
1533 /* The number of an odd floating-point register, that should be used
1534 for the next argument of type float. */
1535 int free_single_fp_reg;
1536 /* Whether we're processing an outgoing function call. */
1538 /* The number of general-purpose registers that should have been
1539 used to pass partial arguments, that are passed totally on the
1540 stack. On SHcompact, a call trampoline will pop them off the
1541 stack before calling the actual function, and, if the called
1542 function is implemented in SHcompact mode, the incoming arguments
1543 decoder will push such arguments back onto the stack. For
1544 incoming arguments, STACK_REGS also takes into account other
1545 arguments passed by reference, that the decoder will also push
1548 /* The number of general-purpose registers that should have been
1549 used to pass arguments, if the arguments didn't have to be passed
1552 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1556 /* call_cookie is a bitmask used by call expanders, as well as
1557 function prologue and epilogues, to allow SHcompact to comply
1558 with the SH5 32-bit ABI, that requires 64-bit registers to be
1559 used even though only the lower 32-bit half is visible in
1560 SHcompact mode. The strategy is to call SHmedia trampolines.
1562 The alternatives for each of the argument-passing registers are
1563 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1564 contents from the address in it; (d) add 8 to it, storing the
1565 result in the next register, then (c); (e) copy it from some
1566 floating-point register,
1568 Regarding copies from floating-point registers, r2 may only be
1569 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1570 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1571 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1572 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1575 The bit mask is structured as follows:
1577 - 1 bit to tell whether to set up a return trampoline.
1579 - 3 bits to count the number consecutive registers to pop off the
1582 - 4 bits for each of r9, r8, r7 and r6.
1584 - 3 bits for each of r5, r4, r3 and r2.
1586 - 3 bits set to 0 (the most significant ones)
1589 1098 7654 3210 9876 5432 1098 7654 3210
1590 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1591 2223 3344 4555 6666 7777 8888 9999 SSS-
1593 - If F is set, the register must be copied from an FP register,
1594 whose number is encoded in the remaining bits.
1596 - Else, if L is set, the register must be loaded from the address
1597 contained in it. If the P bit is *not* set, the address of the
1598 following dword should be computed first, and stored in the
1601 - Else, if P is set, the register alone should be popped off the
1604 - After all this processing, the number of registers represented
1605 in SSS will be popped off the stack. This is an optimization
1606 for pushing/popping consecutive registers, typically used for
1607 varargs and large arguments partially passed in registers.
1609 - If T is set, a return trampoline will be set up for 64-bit
1610 return values to be split into 2 32-bit registers. */
1611 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1612 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1613 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1614 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1615 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1616 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1617 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1618 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1619 #define CALL_COOKIE_INT_REG(REG, VAL) \
1620 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1621 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1622 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1626 #define CUMULATIVE_ARGS struct sh_args
1628 #define GET_SH_ARG_CLASS(MODE) \
1629 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1631 /* There's no mention of complex float types in the SH5 ABI, so we
1632 should presumably handle them as aggregate types. */ \
1633 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1635 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1636 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1637 ? SH_ARG_FLOAT : SH_ARG_INT)
1639 #define ROUND_ADVANCE(SIZE) \
1640 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1642 /* Round a register number up to a proper boundary for an arg of mode
1645 The SH doesn't care about double alignment, so we only
1646 round doubles to even regs when asked to explicitly. */
1648 #define ROUND_REG(CUM, MODE) \
1649 (((TARGET_ALIGN_DOUBLE \
1650 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1651 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1652 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1653 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1654 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1655 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1657 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1658 for a call to a function whose data type is FNTYPE.
1659 For a library call, FNTYPE is 0.
1661 On SH, the offset always starts at 0: the first parm reg is always
1662 the same reg for a given argument class.
1664 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1666 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1668 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1669 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1671 = (TARGET_HITACHI && FNTYPE \
1672 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1673 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1674 (CUM).arg_count[(int) SH_ARG_INT] \
1675 = (TARGET_SH5 && (FNTYPE) \
1676 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1677 (CUM).free_single_fp_reg = 0; \
1678 (CUM).outgoing = 1; \
1679 (CUM).stack_regs = 0; \
1680 (CUM).byref_regs = 0; \
1683 = (CALL_COOKIE_RET_TRAMP \
1684 (TARGET_SHCOMPACT && (FNTYPE) \
1685 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1686 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1687 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1688 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1689 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1691 == FIRST_RET_REG))); \
1694 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1696 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1698 = (CALL_COOKIE_RET_TRAMP \
1699 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1700 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1703 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1705 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1706 (CUM).outgoing = 0; \
1709 /* FIXME: This is overly conservative. A SHcompact function that
1710 receives arguments ``by reference'' will have them stored in its
1711 own stack frame, so it must not pass pointers or references to
1712 these arguments to other functions by means of sibling calls. */
1713 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1714 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0)
1716 /* Update the data in CUM to advance over an argument
1717 of mode MODE and data type TYPE.
1718 (TYPE is null for libcalls where that information may not be
1721 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1722 if ((CUM).force_mem) \
1723 (CUM).force_mem = 0; \
1724 else if (TARGET_SH5) \
1726 tree TYPE_ = ((CUM).byref && (TYPE) \
1727 ? TREE_TYPE (TYPE) \
1729 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1730 ? TYPE_MODE (TYPE_) \
1732 int dwords = (((CUM).byref \
1734 : (MODE_) == BLKmode \
1735 ? int_size_in_bytes (TYPE_) \
1736 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1737 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1738 - (CUM).arg_count[(int) SH_ARG_INT]); \
1742 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1743 if (TARGET_SHCOMPACT \
1744 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1747 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1749 /* N.B. We want this also for outgoing. */\
1750 (CUM).stack_regs += numregs; \
1752 else if ((CUM).byref) \
1754 if (! (CUM).outgoing) \
1755 (CUM).stack_regs += numregs; \
1756 (CUM).byref_regs += numregs; \
1760 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1762 while (--numregs); \
1764 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1767 else if (dwords > numregs) \
1769 int pushregs = numregs; \
1771 if (TARGET_SHCOMPACT) \
1772 (CUM).stack_regs += numregs; \
1773 while (pushregs < NPARM_REGS (SImode) - 1 \
1774 && (CALL_COOKIE_INT_REG_GET \
1775 ((CUM).call_cookie, \
1776 NPARM_REGS (SImode) - pushregs) \
1780 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1784 if (numregs == NPARM_REGS (SImode)) \
1786 |= CALL_COOKIE_INT_REG (0, 1) \
1787 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1790 |= CALL_COOKIE_STACKSEQ (numregs); \
1793 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1794 && ((NAMED) || ! (CUM).prototype_p)) \
1796 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1797 (CUM).free_single_fp_reg = 0; \
1798 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1799 < NPARM_REGS (SFmode)) \
1802 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1803 NPARM_REGS (SFmode) \
1804 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1806 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1808 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1810 if ((CUM).outgoing && numregs > 0) \
1814 |= (CALL_COOKIE_INT_REG \
1815 ((CUM).arg_count[(int) SH_ARG_INT] \
1816 - numregs + ((numfpregs - 2) / 2), \
1817 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1818 - numfpregs) / 2)); \
1820 while (numfpregs -= 2); \
1822 else if ((MODE_) == SFmode && (NAMED) \
1823 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1824 < NPARM_REGS (SFmode))) \
1825 (CUM).free_single_fp_reg \
1826 = FIRST_FP_PARM_REG - numfpregs \
1827 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1831 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1832 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1833 = (ROUND_REG ((CUM), (MODE)) \
1834 + ((MODE) == BLKmode \
1835 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1836 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1838 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1839 This macro is only used in this file. */
1841 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1843 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1844 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1845 && ! (CUM).force_mem \
1847 ? ((MODE) == BLKmode \
1848 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1849 + int_size_in_bytes (TYPE)) \
1850 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1851 : ((ROUND_REG((CUM), (MODE)) \
1852 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1853 <= NPARM_REGS (MODE))) \
1854 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1856 /* Define where to put the arguments to a function.
1857 Value is zero to push the argument on the stack,
1858 or a hard register in which to store the argument.
1860 MODE is the argument's machine mode.
1861 TYPE is the data type of the argument (as a tree).
1862 This is null for libcalls where that information may
1864 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1865 the preceding args and about the function being called.
1866 NAMED is nonzero if this argument is a named parameter
1867 (otherwise it is an extra parameter matching an ellipsis).
1869 On SH the first args are normally in registers
1870 and the rest are pushed. Any arg that starts within the first
1871 NPARM_REGS words is at least partially passed in a register unless
1872 its data type forbids. */
1874 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1876 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1877 && ((NAMED) || !TARGET_HITACHI)) \
1878 ? gen_rtx_REG ((MODE), \
1879 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1880 ^ ((MODE) == SFmode && TARGET_SH4 \
1881 && TARGET_LITTLE_ENDIAN != 0))) \
1883 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1884 ? GEN_INT ((CUM).call_cookie) \
1885 /* The following test assumes unnamed arguments are promoted to \
1887 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1888 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1889 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1890 && ((NAMED) || ! (CUM).prototype_p) \
1891 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1892 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1893 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1894 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1896 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1897 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1898 && (! TARGET_SHCOMPACT \
1899 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1900 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1901 (TYPE), (NAMED))))) \
1902 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1903 + (CUM).arg_count[(int) SH_ARG_INT])) \
1907 /* Whether an argument must be passed by reference. On SHcompact, we
1908 pretend arguments wider than 32-bits that would have been passed in
1909 registers are passed by reference, so that an SHmedia trampoline
1910 loads them into the full 64-bits registers. */
1911 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1912 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1913 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1915 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1917 = (TARGET_SHCOMPACT \
1918 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1919 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1920 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1921 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1922 >= NPARM_REGS (SFmode)))) \
1923 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1924 : GET_MODE_SIZE (MODE)) > 4 \
1925 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1926 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1928 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1929 : GET_MODE_SIZE (MODE)) \
1932 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1933 register in SHcompact mode, it must be padded in the most
1934 significant end. This means that passing it by reference wouldn't
1935 pad properly on a big-endian machine. In this particular case, we
1936 pass this argument on the stack, in a way that the call trampoline
1937 will load its value into the appropriate register. */
1938 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1939 ((MODE) == BLKmode \
1940 && TARGET_SHCOMPACT \
1941 && ! TARGET_LITTLE_ENDIAN \
1942 && int_size_in_bytes (TYPE) > 4 \
1943 && int_size_in_bytes (TYPE) < 8)
1945 /* Minimum alignment for an argument to be passed by callee-copy
1946 reference. We need such arguments to be aligned to 8 byte
1947 boundaries, because they'll be loaded using quad loads. */
1948 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1950 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1952 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1953 : GET_MODE_ALIGNMENT (MODE)) \
1954 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1956 /* The SH5 ABI requires floating-point arguments to be passed to
1957 functions without a prototype in both an FP register and a regular
1958 register or the stack. When passing the argument in both FP and
1959 general-purpose registers, list the FP register first. */
1960 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1966 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1967 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1968 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1973 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1974 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1975 + (CUM).arg_count[(int) SH_ARG_INT]) \
1976 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1977 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1980 /* The SH5 ABI requires regular registers or stack slots to be
1981 reserved for floating-point arguments. Registers are taken care of
1982 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1983 Unfortunately, there's no way to just reserve a stack slot, so
1984 we'll end up needlessly storing a copy of the argument in the
1985 stack. For incoming arguments, however, the PARALLEL will be
1986 optimized to the register-only form, and the value in the stack
1987 slot won't be used at all. */
1988 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1989 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1990 ? gen_rtx_REG ((MODE), (REG)) \
1991 : gen_rtx_PARALLEL ((MODE), \
1994 (VOIDmode, NULL_RTX, \
1997 (VOIDmode, gen_rtx_REG ((MODE), \
2001 #define STRICT_ARGUMENT_NAMING TARGET_SH5
2003 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
2005 /* For an arg passed partly in registers and partly in memory,
2006 this is the number of registers used.
2007 For args passed entirely in registers or entirely in memory, zero.
2009 We sometimes split args. */
2011 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2013 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2015 && (ROUND_REG ((CUM), (MODE)) \
2016 + ((MODE) != BLKmode \
2017 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2018 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2019 > NPARM_REGS (MODE))) \
2020 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2021 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2022 && ! TARGET_SHCOMPACT) \
2023 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2026 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2027 (TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \
2028 && ((CUM).arg_count[(int) SH_ARG_INT] \
2029 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2031 /* Perform any needed actions needed for a function that is receiving a
2032 variable number of arguments. */
2034 /* We actually emit the code in sh_expand_prologue. We used to use
2035 a static variable to flag that we need to emit this code, but that
2036 doesn't when inlining, when functions are deferred and then emitted
2037 later. Fortunately, we already have two flags that are part of struct
2038 function that tell if a function uses varargs or stdarg. */
2039 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2040 if (! current_function_stdarg) \
2044 /* Define the `__builtin_va_list' type for the ABI. */
2045 #define BUILD_VA_LIST_TYPE(VALIST) \
2046 (VALIST) = sh_build_va_list ()
2048 /* Implement `va_start' for varargs and stdarg. */
2049 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2050 sh_va_start (valist, nextarg)
2052 /* Implement `va_arg'. */
2053 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2054 sh_va_arg (valist, type)
2056 /* Call the function profiler with a given profile label.
2057 We use two .aligns, so as to make sure that both the .long is aligned
2058 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2059 from the trapa instruction. */
2061 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2063 fprintf((STREAM), "\t.align\t2\n"); \
2064 fprintf((STREAM), "\ttrapa\t#33\n"); \
2065 fprintf((STREAM), "\t.align\t2\n"); \
2066 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2069 /* Define this macro if the code for function profiling should come
2070 before the function prologue. Normally, the profiling code comes
2073 #define PROFILE_BEFORE_PROLOGUE
2075 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2076 the stack pointer does not matter. The value is tested only in
2077 functions that have frame pointers.
2078 No definition is equivalent to always zero. */
2080 #define EXIT_IGNORE_STACK 1
2083 On the SH, the trampoline looks like
2084 2 0002 D202 mov.l l2,r2
2085 1 0000 D301 mov.l l1,r3
2088 5 0008 00000000 l1: .long area
2089 6 000c 00000000 l2: .long function */
2091 /* Length in units of the trampoline for entering a nested function. */
2092 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2094 /* Alignment required for a trampoline in bits . */
2095 #define TRAMPOLINE_ALIGNMENT \
2096 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2097 : TARGET_SHMEDIA ? 256 : 64)
2099 /* Emit RTL insns to initialize the variable parts of a trampoline.
2100 FNADDR is an RTX for the address of the function's pure code.
2101 CXT is an RTX for the static chain value for the function. */
2103 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2104 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2106 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2108 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2110 if (TARGET_SHMEDIA) \
2111 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2112 gen_reg_rtx (Pmode), 0, \
2116 /* A C expression whose value is RTL representing the value of the return
2117 address for the frame COUNT steps up from the current frame.
2118 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2119 can ignore COUNT. */
2121 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2123 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2126 /* A C expression whose value is RTL representing the location of the
2127 incoming return address at the beginning of any function, before the
2128 prologue. This RTL is either a REG, indicating that the return
2129 value is saved in REG, or a MEM representing a location in
2131 #define INCOMING_RETURN_ADDR_RTX \
2132 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2134 /* Generate necessary RTL for __builtin_saveregs(). */
2135 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2137 /* Addressing modes, and classification of registers for them. */
2138 #define HAVE_POST_INCREMENT TARGET_SH1
2139 /*#define HAVE_PRE_INCREMENT 1*/
2140 /*#define HAVE_POST_DECREMENT 1*/
2141 #define HAVE_PRE_DECREMENT TARGET_SH1
2143 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2145 #define USE_LOAD_PRE_DECREMENT(mode) 0
2146 #define USE_STORE_POST_INCREMENT(mode) 0
2147 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2150 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2151 < (TARGET_SMALLCODE ? 2 : \
2152 ((ALIGN >= 32) ? 16 : 2)))
2154 /* Macros to check register numbers against specific register classes. */
2156 /* These assume that REGNO is a hard or pseudo reg number.
2157 They give nonzero only if REGNO is a hard reg of the suitable class
2158 or a pseudo reg currently allocated to a suitable hard reg.
2159 Since they use reg_renumber, they are safe only once reg_renumber
2160 has been allocated, which happens in local-alloc.c. */
2162 #define REGNO_OK_FOR_BASE_P(REGNO) \
2163 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2164 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2165 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2167 ? (GENERAL_REGISTER_P (REGNO) \
2168 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2169 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2171 /* Maximum number of registers that can appear in a valid memory
2174 #define MAX_REGS_PER_ADDRESS 2
2176 /* Recognize any constant value that is a valid address. */
2178 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2180 /* Nonzero if the constant value X is a legitimate general operand. */
2182 #define LEGITIMATE_CONSTANT_P(X) \
2184 ? ((GET_MODE (X) != DFmode \
2185 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2186 || (X) == CONST0_RTX (GET_MODE (X)) \
2187 || ! TARGET_SHMEDIA_FPU \
2188 || TARGET_SHMEDIA64) \
2189 : (GET_CODE (X) != CONST_DOUBLE \
2190 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2191 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
2193 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2194 and check its validity for a certain class.
2195 We have two alternate definitions for each of them.
2196 The usual definition accepts all pseudo regs; the other rejects
2197 them unless they have been allocated suitable hard regs.
2198 The symbol REG_OK_STRICT causes the latter definition to be used. */
2200 #ifndef REG_OK_STRICT
2202 /* Nonzero if X is a hard reg that can be used as a base reg
2203 or if it is a pseudo reg. */
2204 #define REG_OK_FOR_BASE_P(X) \
2205 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2207 /* Nonzero if X is a hard reg that can be used as an index
2208 or if it is a pseudo reg. */
2209 #define REG_OK_FOR_INDEX_P(X) \
2210 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2211 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2213 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2214 or if X is a pseudo reg. */
2215 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2216 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2217 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2221 /* Nonzero if X is a hard reg that can be used as a base reg. */
2222 #define REG_OK_FOR_BASE_P(X) \
2223 REGNO_OK_FOR_BASE_P (REGNO (X))
2225 /* Nonzero if X is a hard reg that can be used as an index. */
2226 #define REG_OK_FOR_INDEX_P(X) \
2227 REGNO_OK_FOR_INDEX_P (REGNO (X))
2229 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2230 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2231 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2235 /* The 'Q' constraint is a pc relative load operand. */
2236 #define EXTRA_CONSTRAINT_Q(OP) \
2237 (GET_CODE (OP) == MEM \
2238 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2239 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2240 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2241 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2242 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2244 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2245 #define EXTRA_CONSTRAINT_S(OP) \
2246 (GET_CODE (OP) == CONST \
2247 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2248 && GET_MODE (XEXP ((OP), 0)) == DImode \
2249 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2250 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2251 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2252 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2253 && (MOVI_SHORI_BASE_OPERAND_P \
2254 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2255 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2258 /* Check whether OP is a datalabel unspec. */
2259 #define DATALABEL_REF_NO_CONST_P(OP) \
2260 (GET_CODE (OP) == UNSPEC \
2261 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2262 && XVECLEN ((OP), 0) == 1 \
2263 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2264 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2266 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2268 #define DATALABEL_REF_P(OP) \
2269 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2270 || DATALABEL_REF_NO_CONST_P (OP))
2272 #define GOT_ENTRY_P(OP) \
2273 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2274 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2276 #define GOTPLT_ENTRY_P(OP) \
2277 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2278 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2280 #define GOTOFF_P(OP) \
2281 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2282 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTOFF)
2284 #define PIC_ADDR_P(OP) \
2285 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2286 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2288 #define NON_PIC_REFERENCE_P(OP) \
2289 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2290 || DATALABEL_REF_P (OP) \
2291 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2292 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2293 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2294 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2296 #define PIC_REFERENCE_P(OP) \
2297 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2298 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2300 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2301 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2303 /* The `T' constraint is a label or a symbol. */
2304 #define EXTRA_CONSTRAINT_T(OP) \
2305 (NON_PIC_REFERENCE_P (OP))
2307 /* A zero in any shape or form. */
2308 #define EXTRA_CONSTRAINT_U(OP) \
2309 ((OP) == CONST0_RTX (GET_MODE (OP)))
2311 /* Any vector constant we can handle. */
2312 #define EXTRA_CONSTRAINT_W(OP) \
2313 (GET_CODE (OP) == CONST_VECTOR \
2314 && (sh_rep_vec ((OP), VOIDmode) \
2315 || (HOST_BITS_PER_WIDE_INT >= 64 \
2316 ? sh_const_vec ((OP), VOIDmode) \
2317 : sh_1el_vec ((OP), VOIDmode))))
2319 #define EXTRA_CONSTRAINT(OP, C) \
2320 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2321 : (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \
2322 : (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \
2323 : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \
2324 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2327 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2328 that is a valid memory address for an instruction.
2329 The MODE argument is the machine mode for the MEM expression
2330 that wants to use this address. */
2332 #define MODE_DISP_OK_4(X,MODE) \
2333 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2334 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
2336 #define MODE_DISP_OK_8(X,MODE) \
2337 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2338 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2340 #define BASE_REGISTER_RTX_P(X) \
2341 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2342 || (GET_CODE (X) == SUBREG \
2343 && GET_CODE (SUBREG_REG (X)) == REG \
2344 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2346 /* Since this must be r0, which is a single register class, we must check
2347 SUBREGs more carefully, to be sure that we don't accept one that extends
2348 outside the class. */
2349 #define INDEX_REGISTER_RTX_P(X) \
2350 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2351 || (GET_CODE (X) == SUBREG \
2352 && GET_CODE (SUBREG_REG (X)) == REG \
2353 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2355 /* Jump to LABEL if X is a valid address RTX. This must also take
2356 REG_OK_STRICT into account when deciding about valid registers, but it uses
2357 the above macros so we are in luck.
2365 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
2366 into the FRx registers. We implement this by setting the maximum offset
2367 to zero when the value is SFmode. This also restricts loading of SFmode
2368 values into the integer registers, but that can't be helped. */
2370 /* The SH allows a displacement in a QI or HI amode, but only when the
2371 other operand is R0. GCC doesn't handle this very well, so we forgo
2374 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2375 DI can be any number 0..60. */
2377 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2379 if (GET_CODE (OP) == CONST_INT) \
2381 if (TARGET_SHMEDIA) \
2383 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2384 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2385 && INTVAL (OP) >= -512 * MODE_SIZE \
2386 && INTVAL (OP) < 512 * MODE_SIZE) \
2391 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2392 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2396 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2398 if (BASE_REGISTER_RTX_P (X)) \
2400 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2401 && ! TARGET_SHMEDIA \
2402 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2404 else if (GET_CODE (X) == PLUS \
2405 && ((MODE) != PSImode || reload_completed)) \
2407 rtx xop0 = XEXP ((X), 0); \
2408 rtx xop1 = XEXP ((X), 1); \
2409 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2410 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2411 if (GET_MODE_SIZE (MODE) <= 4 \
2412 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2413 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2415 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2417 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2423 /* Try machine-dependent ways of modifying an illegitimate address
2424 to be legitimate. If we find one, return the new, valid address.
2425 This macro is used in only one place: `memory_address' in explow.c.
2427 OLDX is the address as it was before break_out_memory_refs was called.
2428 In some cases it is useful to look at this to decide what needs to be done.
2430 MODE and WIN are passed so that this macro can use
2431 GO_IF_LEGITIMATE_ADDRESS.
2433 It is always safe for this macro to do nothing. It exists to recognize
2434 opportunities to optimize the output.
2436 For the SH, if X is almost suitable for indexing, but the offset is
2437 out of range, convert it into a normal form so that cse has a chance
2438 of reducing the number of address registers used. */
2440 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2443 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2444 if (GET_CODE (X) == PLUS \
2445 && (GET_MODE_SIZE (MODE) == 4 \
2446 || GET_MODE_SIZE (MODE) == 8) \
2447 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2448 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2449 && ! TARGET_SHMEDIA \
2450 && ! (TARGET_SH4 && (MODE) == DFmode) \
2451 && ! (TARGET_SH3E && (MODE) == SFmode)) \
2453 rtx index_rtx = XEXP ((X), 1); \
2454 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2457 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2458 /* On rare occasions, we might get an unaligned pointer \
2459 that is indexed in a way to give an aligned address. \
2460 Therefore, keep the lower two bits in offset_base. */ \
2461 /* Instead of offset_base 128..131 use 124..127, so that \
2462 simple add suffices. */ \
2465 offset_base = ((offset + 4) & ~60) - 4; \
2468 offset_base = offset & ~60; \
2469 /* Sometimes the normal form does not suit DImode. We \
2470 could avoid that by using smaller ranges, but that \
2471 would give less optimized code when SImode is \
2473 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2475 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2476 GEN_INT (offset_base), NULL_RTX, 0, \
2479 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2485 /* A C compound statement that attempts to replace X, which is an address
2486 that needs reloading, with a valid memory address for an operand of
2487 mode MODE. WIN is a C statement label elsewhere in the code.
2489 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2490 of the address. That will allow inheritance of the address reloads. */
2492 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2494 if (GET_CODE (X) == PLUS \
2495 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2496 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2497 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2498 && ! TARGET_SHMEDIA \
2499 && ! (TARGET_SH4 && (MODE) == DFmode) \
2500 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2502 rtx index_rtx = XEXP (X, 1); \
2503 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2506 if (TARGET_SH3E && MODE == SFmode) \
2509 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2510 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2514 /* Instead of offset_base 128..131 use 124..127, so that \
2515 simple add suffices. */ \
2518 offset_base = ((offset + 4) & ~60) - 4; \
2521 offset_base = offset & ~60; \
2522 /* Sometimes the normal form does not suit DImode. We \
2523 could avoid that by using smaller ranges, but that \
2524 would give less optimized code when SImode is \
2526 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2528 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2529 GEN_INT (offset_base)); \
2530 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2531 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2532 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2537 /* We must re-recognize what we created before. */ \
2538 else if (GET_CODE (X) == PLUS \
2539 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2540 && GET_CODE (XEXP (X, 0)) == PLUS \
2541 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2542 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2543 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2544 && ! TARGET_SHMEDIA \
2545 && ! (TARGET_SH3E && MODE == SFmode)) \
2547 /* Because this address is so complex, we know it must have \
2548 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2549 it is already unshared, and needs no further unsharing. */ \
2550 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2551 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2556 /* Go to LABEL if ADDR (a legitimate address expression)
2557 has an effect that depends on the machine mode it is used for.
2559 ??? Strictly speaking, we should also include all indexed addressing,
2560 because the index scale factor is the length of the operand.
2561 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2562 high if we did that. So we rely on reload to fix things up. */
2564 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2566 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2570 /* Specify the machine mode that this machine uses
2571 for the index in the tablejump instruction. */
2572 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
2574 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2575 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2576 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2577 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2578 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2579 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2582 /* Define as C expression which evaluates to nonzero if the tablejump
2583 instruction expects the table to contain offsets from the address of the
2585 Do not define this if the table should contain absolute addresses. */
2586 #define CASE_VECTOR_PC_RELATIVE 1
2588 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2589 #define FLOAT_TYPE_SIZE 32
2591 /* Since the SH3e has only `float' support, it is desirable to make all
2592 floating point types equivalent to `float'. */
2593 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
2595 /* 'char' is signed by default. */
2596 #define DEFAULT_SIGNED_CHAR 1
2598 /* The type of size_t unsigned int. */
2599 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2602 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2604 #define WCHAR_TYPE "short unsigned int"
2605 #define WCHAR_TYPE_SIZE 16
2607 #define SH_ELF_WCHAR_TYPE "long int"
2609 /* Don't cse the address of the function being compiled. */
2610 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2612 /* Max number of bytes we can move from memory to memory
2613 in one reasonably fast instruction. */
2614 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2616 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2617 MOVE_MAX is not a compile-time constant. */
2618 #define MAX_MOVE_MAX 8
2620 /* Max number of bytes we want move_by_pieces to be able to copy
2622 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2624 /* Define if operations between registers always perform the operation
2625 on the full register even if a narrower mode is specified. */
2626 #define WORD_REGISTER_OPERATIONS
2628 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2629 will either zero-extend or sign-extend. The value of this macro should
2630 be the code that says which one of the two operations is implicitly
2631 done, NIL if none. */
2632 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2633 /* FP registers can load SImode values, but don't implicitly sign-extend
2635 #define LOAD_EXTEND_OP(MODE) \
2636 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2637 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2639 /* Define if loading short immediate values into registers sign extends. */
2640 #define SHORT_IMMEDIATES_SIGN_EXTEND
2642 /* Nonzero if access to memory by bytes is no faster than for words. */
2643 #define SLOW_BYTE_ACCESS 1
2645 /* We assume that the store-condition-codes instructions store 0 for false
2646 and some other value for true. This is the value stored for true. */
2648 #define STORE_FLAG_VALUE 1
2650 /* Immediate shift counts are truncated by the output routines (or was it
2651 the assembler?). Shift counts in a register are truncated by SH. Note
2652 that the native compiler puts too large (> 32) immediate shift counts
2653 into a register and shifts by the register, letting the SH decide what
2654 to do instead of doing that itself. */
2655 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2656 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2657 expects - the sign bit is significant - so it appears that we need to
2658 leave this zero for correct SH3 code. */
2659 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2661 /* All integers have the same format so truncation is easy. */
2662 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2664 /* Define this if addresses of constant functions
2665 shouldn't be put through pseudo regs where they can be cse'd.
2666 Desirable on machines where ordinary constants are expensive
2667 but a CALL with constant address is cheap. */
2668 /*#define NO_FUNCTION_CSE 1*/
2670 /* Chars and shorts should be passed as ints. */
2671 #define PROMOTE_PROTOTYPES 1
2673 /* The machine modes of pointers and functions. */
2674 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2675 #define FUNCTION_MODE Pmode
2677 /* The relative costs of various types of constants. */
2679 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2681 if (TARGET_SHMEDIA) \
2683 if (INTVAL (RTX) == 0) \
2685 if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \
2687 if (((OUTER_CODE) == IOR || (OUTER_CODE) == XOR \
2688 || (OUTER_CODE) == PLUS) \
2689 && CONST_OK_FOR_P (INTVAL (RTX))) \
2691 if (CONST_OK_FOR_J (INTVAL (RTX))) \
2692 return COSTS_N_INSNS ((OUTER_CODE) != SET); \
2693 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
2694 return COSTS_N_INSNS (2); \
2695 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
2696 return COSTS_N_INSNS (3); \
2698 return COSTS_N_INSNS (4); \
2700 if (CONST_OK_FOR_I (INTVAL (RTX))) \
2702 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
2703 && CONST_OK_FOR_L (INTVAL (RTX))) \
2710 if (TARGET_SHMEDIA64) \
2711 return COSTS_N_INSNS (4); \
2712 if (TARGET_SHMEDIA32) \
2713 return COSTS_N_INSNS (2); \
2715 case CONST_DOUBLE: \
2716 if (TARGET_SHMEDIA) \
2717 return COSTS_N_INSNS (4); \
2721 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2723 return COSTS_N_INSNS (addsubcosts (X)); \
2725 return COSTS_N_INSNS (andcosts (X)); \
2727 return COSTS_N_INSNS (multcosts (X)); \
2731 return COSTS_N_INSNS (shiftcosts (X)); \
2736 return COSTS_N_INSNS (20); \
2741 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2742 are actually function calls with some special constraints on arguments
2745 These macros tell reorg that the references to arguments and
2746 register clobbers for insns of type sfunc do not appear to happen
2747 until after the millicode call. This allows reorg to put insns
2748 which set the argument registers into the delay slot of the millicode
2749 call -- thus they act more like traditional CALL_INSNs.
2751 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2752 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2755 #define INSN_SETS_ARE_DELAYED(X) \
2756 ((GET_CODE (X) == INSN \
2757 && GET_CODE (PATTERN (X)) != SEQUENCE \
2758 && GET_CODE (PATTERN (X)) != USE \
2759 && GET_CODE (PATTERN (X)) != CLOBBER \
2760 && get_attr_is_sfunc (X)))
2762 #define INSN_REFERENCES_ARE_DELAYED(X) \
2763 ((GET_CODE (X) == INSN \
2764 && GET_CODE (PATTERN (X)) != SEQUENCE \
2765 && GET_CODE (PATTERN (X)) != USE \
2766 && GET_CODE (PATTERN (X)) != CLOBBER \
2767 && get_attr_is_sfunc (X)))
2770 /* Position Independent Code. */
2772 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2773 #define SH_DATALABEL_ENCODING "#"
2775 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2776 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2777 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2778 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2780 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2781 SYM_NAME. Then, remove a leading *, like the default definition in
2783 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2784 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2785 ? strlen (SH_DATALABEL_ENCODING) : 0)
2787 /* We can't directly access anything that contains a symbol,
2788 nor can we indirect via the constant pool. */
2789 #define LEGITIMATE_PIC_OPERAND_P(X) \
2790 (! nonpic_symbol_mentioned_p (X) \
2791 && (GET_CODE (X) != SYMBOL_REF \
2792 || ! CONSTANT_POOL_ADDRESS_P (X) \
2793 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2795 #define SYMBOLIC_CONST_P(X) \
2796 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2797 && nonpic_symbol_mentioned_p (X))
2799 /* Compute the cost of an address. For the SH, all valid addresses are
2800 the same cost. Use a slightly higher cost for reg + reg addressing,
2801 since it increases pressure on r0. */
2803 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
2804 && ! TARGET_SHMEDIA \
2807 /* Compute extra cost of moving data between one register class
2810 /* Regclass always uses 2 for moves in the same register class;
2811 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
2812 it uses this information. Hence, the general register <-> floating point
2813 register information here is not used for SFmode. */
2814 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2815 (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
2816 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
2817 || (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
2818 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2819 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
2820 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
2821 || (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
2822 ? (TARGET_SHMEDIA ? 4 \
2823 : TARGET_FMOVD ? 8 : 12) \
2824 : (((DSTCLASS) == FPUL_REGS \
2825 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2826 || (SRCCLASS == FPUL_REGS \
2827 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
2829 : (((DSTCLASS) == FPUL_REGS \
2830 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
2831 || (SRCCLASS) == T_REGS)) \
2832 || ((SRCCLASS) == FPUL_REGS \
2833 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
2835 : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
2836 || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
2838 : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
2839 || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
2841 : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
2843 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2844 would be so that people with slow memory systems could generate
2845 different code that does fewer memory accesses. */
2847 /* A C expression for the cost of a branch instruction. A value of 1
2848 is the default; other values are interpreted relative to that.
2849 The SH1 does not have delay slots, hence we get a pipeline stall
2850 at every branch. The SH4 is superscalar, so the single delay slot
2851 is not sufficient to keep both pipelines filled. */
2852 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2854 /* Assembler output control. */
2856 /* A C string constant describing how to begin a comment in the target
2857 assembler language. The compiler assumes that the comment will end at
2858 the end of the line. */
2859 #define ASM_COMMENT_START "!"
2861 /* The text to go at the start of the assembler file. */
2862 #define ASM_FILE_START(STREAM) \
2863 output_file_start (STREAM)
2865 #define ASM_APP_ON ""
2866 #define ASM_APP_OFF ""
2867 #define FILE_ASM_OP "\t.file\n"
2868 #define SET_ASM_OP "\t.set\t"
2870 /* How to change between sections. */
2872 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2873 #define DATA_SECTION_ASM_OP "\t.data"
2875 #if defined CRT_BEGIN || defined CRT_END
2876 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2877 # undef TEXT_SECTION_ASM_OP
2878 # if __SHMEDIA__ == 1 && __SH5__ == 32
2879 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2881 # define TEXT_SECTION_ASM_OP "\t.text"
2886 /* If defined, a C expression whose value is a string containing the
2887 assembler operation to identify the following data as
2888 uninitialized global data. If not defined, and neither
2889 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2890 uninitialized global data will be output in the data section if
2891 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2893 #ifndef BSS_SECTION_ASM_OP
2894 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2897 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2898 separate, explicit argument. If you define this macro, it is used
2899 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2900 handling the required alignment of the variable. The alignment is
2901 specified as the number of bits.
2903 Try to use function `asm_output_aligned_bss' defined in file
2904 `varasm.c' when defining this macro. */
2905 #ifndef ASM_OUTPUT_ALIGNED_BSS
2906 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2907 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2910 /* Define this so that jump tables go in same section as the current function,
2911 which could be text or it could be a user defined section. */
2912 #define JUMP_TABLES_IN_TEXT_SECTION 1
2914 #undef DO_GLOBAL_CTORS_BODY
2915 #define DO_GLOBAL_CTORS_BODY \
2917 typedef (*pfunc)(); \
2918 extern pfunc __ctors[]; \
2919 extern pfunc __ctors_end[]; \
2921 for (p = __ctors_end; p > __ctors; ) \
2927 #undef DO_GLOBAL_DTORS_BODY
2928 #define DO_GLOBAL_DTORS_BODY \
2930 typedef (*pfunc)(); \
2931 extern pfunc __dtors[]; \
2932 extern pfunc __dtors_end[]; \
2934 for (p = __dtors; p < __dtors_end; p++) \
2940 #define ASM_OUTPUT_REG_PUSH(file, v) \
2941 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2943 #define ASM_OUTPUT_REG_POP(file, v) \
2944 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2946 /* DBX register number for a given compiler register number. */
2947 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2949 /* svr4.h undefines this macro, yet we really want to use the same numbers
2950 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2951 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2953 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2954 (GENERAL_REGISTER_P (REGNO) \
2955 ? ((REGNO) - FIRST_GENERAL_REG) \
2956 : FP_REGISTER_P (REGNO) \
2957 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2959 : XD_REGISTER_P (REGNO) \
2960 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2961 : TARGET_REGISTER_P (REGNO) \
2962 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2963 : (REGNO) == PR_REG \
2964 ? (TARGET_SH5 ? 241 : 17) \
2965 : (REGNO) == T_REG \
2966 ? (TARGET_SH5 ? 242 : 18) \
2967 : (REGNO) == GBR_REG \
2968 ? (TARGET_SH5 ? 238 : 19) \
2969 : (REGNO) == MACH_REG \
2970 ? (TARGET_SH5 ? 239 : 20) \
2971 : (REGNO) == MACL_REG \
2972 ? (TARGET_SH5 ? 240 : 21) \
2973 : (REGNO) == FPUL_REG \
2974 ? (TARGET_SH5 ? 244 : 23) \
2977 /* This is how to output a reference to a user-level label named NAME. */
2978 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2983 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
2984 if (lname[0] == '*') \
2985 fputs (lname + 1, (FILE)); \
2987 asm_fprintf ((FILE), "%U%s", lname); \
2991 /* This is how to output a reference to a symbol_ref. On SH5,
2992 references to non-code symbols must be preceded by `datalabel'. */
2993 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2997 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
2998 || CONSTANT_POOL_ADDRESS_P (SYM))) \
2999 fputs ("datalabel ", (FILE)); \
3000 assemble_name ((FILE), XSTR ((SYM), 0)); \
3004 /* This is how to output an assembler line
3005 that says to advance the location counter
3006 to a multiple of 2**LOG bytes. */
3008 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3010 fprintf ((FILE), "\t.align %d\n", (LOG))
3012 /* Globalizing directive for a label. */
3013 #define GLOBAL_ASM_OP "\t.global\t"
3015 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3017 /* Construct a private name. */
3018 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
3019 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
3020 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
3022 /* Output a relative address table. */
3024 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3025 switch (GET_MODE (BODY)) \
3030 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3034 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3039 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3043 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3048 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3052 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3058 /* Output an absolute table element. */
3060 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3061 if (TARGET_BIGTABLE) \
3062 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3064 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3067 /* A C statement to be executed just prior to the output of
3068 assembler code for INSN, to modify the extracted operands so
3069 they will be output differently.
3071 Here the argument OPVEC is the vector containing the operands
3072 extracted from INSN, and NOPERANDS is the number of elements of
3073 the vector which contain meaningful data for this insn.
3074 The contents of this vector are what will be used to convert the insn
3075 template into assembler code, so you can change the assembler output
3076 by changing the contents of the vector. */
3078 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3079 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3081 /* Print operand X (an rtx) in assembler syntax to file FILE.
3082 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3083 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3085 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3087 /* Print a memory address as an operand to reference that memory location. */
3089 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3091 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3092 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3093 || (CHAR) == '$'|| (CHAR) == '\'')
3095 /* Recognize machine-specific patterns that may appear within
3096 constants. Used for PIC-specific UNSPECs. */
3097 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3099 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3101 switch (XINT ((X), 1)) \
3103 case UNSPEC_DATALABEL: \
3104 fputs ("datalabel ", (STREAM)); \
3105 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3108 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3109 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3112 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3113 fputs ("@GOT", (STREAM)); \
3115 case UNSPEC_GOTOFF: \
3116 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3117 fputs ("@GOTOFF", (STREAM)); \
3120 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3121 fputs ("@PLT", (STREAM)); \
3123 case UNSPEC_GOTPLT: \
3124 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3125 fputs ("@GOTPLT", (STREAM)); \
3127 case UNSPEC_CALLER: \
3130 /* LPCS stands for Label for PIC Call Site. */ \
3131 ASM_GENERATE_INTERNAL_LABEL \
3132 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3133 assemble_name ((STREAM), name); \
3146 extern struct rtx_def *sh_compare_op0;
3147 extern struct rtx_def *sh_compare_op1;
3149 /* Which processor to schedule for. The elements of the enumeration must
3150 match exactly the cpu attribute in the sh.md file. */
3152 enum processor_type {
3161 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3162 extern enum processor_type sh_cpu;
3164 extern int optimize; /* needed for gen_casesi. */
3166 enum mdep_reorg_phase_e
3168 SH_BEFORE_MDEP_REORG,
3169 SH_INSERT_USES_LABELS,
3170 SH_SHORTEN_BRANCHES0,
3172 SH_SHORTEN_BRANCHES1,
3176 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3178 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3180 /* Generate calls to memcpy, memcmp and memset. */
3182 #define TARGET_MEM_FUNCTIONS
3184 /* Handle Hitachi compiler's pragmas. */
3185 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
3186 cpp_register_pragma (PFILE, 0, "interrupt", sh_pr_interrupt); \
3187 cpp_register_pragma (PFILE, 0, "trapa", sh_pr_trapa); \
3188 cpp_register_pragma (PFILE, 0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3191 /* Set when processing a function with pragma interrupt turned on. */
3193 extern int pragma_interrupt;
3195 /* Set when processing a function with interrupt attribute. */
3197 extern int current_function_interrupt;
3199 /* Set to an RTX containing the address of the stack to switch to
3200 for interrupt functions. */
3201 extern struct rtx_def *sp_switch;
3203 extern int rtx_equal_function_value_matters;
3206 /* Instructions with unfilled delay slots take up an
3207 extra two bytes for the nop in the delay slot.
3208 sh-dsp parallel processing insns are four bytes long. */
3210 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3211 (LENGTH) += sh_insn_length_adjustment (X);
3213 /* Define the codes that are matched by predicates in sh.c. */
3214 #define PREDICATE_CODES \
3215 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3216 {"any_register_operand", {SUBREG, REG}}, \
3217 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3218 {"arith_reg_dest", {SUBREG, REG}}, \
3219 {"arith_reg_operand", {SUBREG, REG}}, \
3220 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3221 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3222 {"commutative_float_operator", {PLUS, MULT}}, \
3223 {"equality_comparison_operator", {EQ,NE}}, \
3224 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3225 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3226 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3227 {"fpscr_operand", {REG}}, \
3228 {"fpul_operand", {REG}}, \
3229 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3230 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3231 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3232 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3233 {"int_gpr_dest", {SUBREG, REG}}, \
3234 {"inqhi_operand", {TRUNCATE}}, \
3235 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3236 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3237 {"mextr_bit_offset", {CONST_INT}}, \
3238 {"noncommutative_float_operator", {MINUS, DIV}}, \
3239 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3240 {"target_reg_operand", {SUBREG, REG}}, \
3241 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3242 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3243 {"register_operand", {SUBREG, REG}}, \
3244 {"sh_const_vec", {CONST_VECTOR}}, \
3245 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3246 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3247 {"symbol_ref_operand", {SYMBOL_REF}}, \
3248 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3250 #define SPECIAL_MODE_PREDICATES \
3251 "any_register_operand", \
3253 "trunc_hi_operand", \
3254 /* This line intentionally left blank. */
3256 #define any_register_operand register_operand
3258 /* Define this macro if it is advisable to hold scalars in registers
3259 in a wider mode than that declared by the program. In such cases,
3260 the value is constrained to be within the bounds of the declared
3261 type, but kept valid in the wider mode. The signedness of the
3262 extension may differ from that of the type.
3264 Leaving the unsignedp unchanged gives better code than always setting it
3265 to 0. This is despite the fact that we have only signed char and short
3266 load instructions. */
3267 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3268 if (GET_MODE_CLASS (MODE) == MODE_INT \
3269 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3270 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3271 (MODE) = (TARGET_SH1 ? SImode : DImode);
3273 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3274 extensions applied to char/short functions arguments. Defining
3275 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3277 #define PROMOTE_FUNCTION_ARGS
3278 #define PROMOTE_FUNCTION_RETURN
3280 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3282 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3283 and poping arguments. However, we do have push/pop instructions, and
3284 rather limited offsets (4 bits) in load/store instructions, so it isn't
3285 clear if this would give better code. If implemented, should check for
3286 compatibility problems. */
3288 #define SH_DYNAMIC_SHIFT_COST \
3289 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3292 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3294 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3296 #define NORMAL_MODE(ENTITY) \
3297 (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \
3298 : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
3301 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
3302 && (REGNO) == FPSCR_REG)
3304 #define MODE_NEEDED(ENTITY, INSN) \
3305 (recog_memoized (INSN) >= 0 \
3306 ? get_attr_fp_mode (INSN) \
3309 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3310 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3312 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3313 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3315 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3316 sh_can_redirect_branch ((INSN), (SEQ))
3318 #define DWARF_FRAME_RETURN_COLUMN (TARGET_SH5 ? PR_MEDIA_REG : PR_REG)
3320 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3321 /* SH constant pool breaks the devices in crtstuff.c to control section
3322 in where code resides. We have to write it as asm code. */
3323 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3324 asm (SECTION_OP "\n\
3330 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3331 2:\n" TEXT_SECTION_ASM_OP);
3332 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3334 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3335 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3336 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3338 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3339 ? (plus_constant (arg_pointer_rtx, \
3340 TARGET_SHMEDIA64 ? -8 : -4)) \
3341 : frame_pointer_rtx)) \
3344 #endif /* ! GCC_SH_H */
OSDN Git Service
