1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
43 builtin_define ("__sh1__"); \
46 builtin_define ("__sh2__"); \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
88 builtin_define ("__SH_FPU_ANY__"); \
89 if (TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH_FPU_DOUBLE__"); \
92 builtin_define ("__HITACHI__"); \
93 builtin_define (TARGET_LITTLE_ENDIAN \
94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
97 builtin_define ("__pic__"); \
98 builtin_define ("__PIC__"); \
102 /* We can not debug without a frame pointer. */
103 /* #define CAN_DEBUG_WITHOUT_FP */
105 #define CONDITIONAL_REGISTER_USAGE do \
108 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
109 if (! VALID_REGISTER_P (regno)) \
110 fixed_regs[regno] = call_used_regs[regno] = 1; \
111 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
114 call_used_regs[FIRST_GENERAL_REG + 8] \
115 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
116 call_really_used_regs[FIRST_GENERAL_REG + 8] \
117 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
119 if (TARGET_SHMEDIA) \
121 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
122 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
123 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
127 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
128 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
130 /* Renesas saves and restores mac registers on call. */ \
131 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
133 call_really_used_regs[MACH_REG] = 0; \
134 call_really_used_regs[MACL_REG] = 0; \
136 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
137 regno <= LAST_FP_REG; regno += 2) \
138 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
139 if (TARGET_SHMEDIA) \
141 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
146 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
147 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
148 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
151 /* Nonzero if this is an ELF target - compile time only */
154 /* Nonzero if we should generate code using type 2E insns. */
155 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
157 /* Nonzero if we should generate code using type 2A insns. */
158 #define TARGET_SH2A TARGET_HARD_SH2A
159 /* Nonzero if we should generate code using type 2A SF insns. */
160 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
161 /* Nonzero if we should generate code using type 2A DF insns. */
162 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
164 /* Nonzero if we should generate code using type 3E insns. */
165 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
167 /* Nonzero if the cache line size is 32. */
168 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
170 /* Nonzero if we schedule for a superscalar implementation. */
171 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
173 /* Nonzero if the target has separate instruction and data caches. */
174 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
176 /* Nonzero if a double-precision FPU is available. */
177 #define TARGET_FPU_DOUBLE \
178 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
180 /* Nonzero if an FPU is available. */
181 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
183 /* Nonzero if we should generate code using type 4 insns. */
185 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
187 /* Nonzero if we're generating code for the common subset of
188 instructions present on both SH4a and SH4al-dsp. */
189 #define TARGET_SH4A_ARCH TARGET_SH4A
191 /* Nonzero if we're generating code for SH4a, unless the use of the
192 FPU is disabled (which makes it compatible with SH4al-dsp). */
193 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
195 /* Nonzero if we should generate code using the SHcompact instruction
196 set and 32-bit ABI. */
197 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
199 /* Nonzero if we should generate code using the SHmedia instruction
201 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
203 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
205 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
207 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
209 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
211 /* Nonzero if we should generate code using SHmedia FPU instructions. */
212 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
214 /* This is not used by the SH2E calling convention */
215 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
216 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
217 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
219 #ifndef TARGET_CPU_DEFAULT
220 #define TARGET_CPU_DEFAULT SELECT_SH1
221 #define SUPPORT_SH1 1
222 #define SUPPORT_SH2E 1
223 #define SUPPORT_SH4 1
224 #define SUPPORT_SH4_SINGLE 1
225 #define SUPPORT_SH2A 1
226 #define SUPPORT_SH2A_SINGLE 1
229 #define TARGET_DIVIDE_INV \
230 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
231 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
232 || sh_div_strategy == SH_DIV_INV_CALL \
233 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
234 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
235 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
236 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
237 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
238 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
239 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
240 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
241 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
243 #define SELECT_SH1 (MASK_SH1)
244 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
245 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
247 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
248 | MASK_HARD_SH2A_DOUBLE \
249 | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
251 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
252 | MASK_SH1 | MASK_FPU_SINGLE)
253 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
254 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
255 | MASK_SH2 | MASK_SH1)
256 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
257 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
258 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
259 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
260 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
262 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
263 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
264 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
265 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
266 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
267 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
268 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
269 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
270 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
271 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
272 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
275 #define SUPPORT_SH2 1
278 #define SUPPORT_SH3 1
281 #define SUPPORT_SH4_NOFPU 1
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
286 #define SUPPORT_SH2A_NOFPU 1
290 #define SUPPORT_SH3E 1
293 #define SUPPORT_SH4_SINGLE_ONLY 1
294 #define SUPPORT_SH4A_SINGLE_ONLY 1
295 #define SUPPORT_SH2A_SINGLE_ONLY 1
299 #define SUPPORT_SH4A 1
302 #if SUPPORT_SH4_SINGLE
303 #define SUPPORT_SH4A_SINGLE 1
306 #if SUPPORT_SH5_COMPAT
307 #define SUPPORT_SH5_32MEDIA 1
310 #if SUPPORT_SH5_COMPACT_NOFPU
311 #define SUPPORT_SH5_32MEDIA_NOFPU 1
314 #define SUPPORT_ANY_SH5_32MEDIA \
315 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
316 #define SUPPORT_ANY_SH5_64MEDIA \
317 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
318 #define SUPPORT_ANY_SH5 \
319 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
321 /* Reset all target-selection flags. */
322 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
323 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
324 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
326 /* This defaults us to big-endian. */
327 #ifndef TARGET_ENDIAN_DEFAULT
328 #define TARGET_ENDIAN_DEFAULT 0
331 #ifndef TARGET_OPT_DEFAULT
332 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
335 #define TARGET_DEFAULT \
336 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
338 #ifndef SH_MULTILIB_CPU_DEFAULT
339 #define SH_MULTILIB_CPU_DEFAULT "m1"
342 #if TARGET_ENDIAN_DEFAULT
343 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
345 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
348 #define CPP_SPEC " %(subtarget_cpp_spec) "
350 #ifndef SUBTARGET_CPP_SPEC
351 #define SUBTARGET_CPP_SPEC ""
354 #ifndef SUBTARGET_EXTRA_SPECS
355 #define SUBTARGET_EXTRA_SPECS
358 #define EXTRA_SPECS \
359 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
360 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
361 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
362 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
363 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
364 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
365 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
366 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
367 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
368 SUBTARGET_EXTRA_SPECS
370 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
371 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
373 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
376 #define SH_ASM_SPEC \
377 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
378 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
380 %{m2a-single:--isa=sh2a} \
381 %{m2a-single-only:--isa=sh2a} \
382 %{m2a-nofpu:--isa=sh2a-nofpu} \
383 %{m5-compact*:--isa=SHcompact} \
384 %{m5-32media*:--isa=SHmedia --abi=32} \
385 %{m5-64media*:--isa=SHmedia --abi=64} \
386 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
388 #define ASM_SPEC SH_ASM_SPEC
390 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
391 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
392 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
394 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
398 #if STRICT_NOFPU == 1
399 /* Strict nofpu means that the compiler should tell the assembler
400 to reject FPU instructions. E.g. from ASM inserts. */
401 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
402 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
404 /* If there were an -isa option for sh5-nofpu then it would also go here. */
405 #define SUBTARGET_ASM_ISA_SPEC \
406 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
408 #else /* ! STRICT_NOFPU */
409 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
412 #ifndef SUBTARGET_ASM_SPEC
413 #define SUBTARGET_ASM_SPEC ""
416 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
417 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
419 #define LINK_EMUL_PREFIX "sh%{ml:l}"
422 #if TARGET_CPU_DEFAULT & MASK_SH5
423 #if TARGET_CPU_DEFAULT & MASK_SH_E
424 #define LINK_DEFAULT_CPU_EMUL "32"
425 #if TARGET_CPU_DEFAULT & MASK_SH1
426 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
428 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
429 #endif /* MASK_SH1 */
430 #else /* !MASK_SH_E */
431 #define LINK_DEFAULT_CPU_EMUL "64"
432 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
433 #endif /* MASK_SH_E */
434 #define ASM_ISA_DEFAULT_SPEC \
435 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
436 #else /* !MASK_SH5 */
437 #define LINK_DEFAULT_CPU_EMUL ""
438 #define ASM_ISA_DEFAULT_SPEC ""
439 #endif /* MASK_SH5 */
441 #define SUBTARGET_LINK_EMUL_SUFFIX ""
442 #define SUBTARGET_LINK_SPEC ""
444 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
445 so that we can undo the damage without code replication. */
446 #define LINK_SPEC SH_LINK_SPEC
448 #define SH_LINK_SPEC "\
449 -m %(link_emul_prefix)\
450 %{m5-compact*|m5-32media*:32}\
452 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
453 %(subtarget_link_emul_suffix) \
454 %{mrelax:-relax} %(subtarget_link_spec)"
456 #ifndef SH_DIV_STR_FOR_SIZE
457 #define SH_DIV_STR_FOR_SIZE "call"
460 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
461 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
465 flag_omit_frame_pointer = -1; \
467 sh_div_str = "inv:minlat"; \
471 target_flags |= MASK_SMALLCODE; \
472 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
475 haven't been parsed yet, hence we';d read only the default. \
476 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
477 it's OK to always set flag_branch_target_load_optimize. */ \
480 flag_branch_target_load_optimize = 1; \
482 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
484 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
485 here, so leave it to OVERRIDE_OPTIONS to set \
486 flag_finite_math_only. We set it to 2 here so we know if the user \
487 explicitly requested this to be on or off. */ \
488 flag_finite_math_only = 2; \
491 #define ASSEMBLER_DIALECT assembler_dialect
493 extern int assembler_dialect;
495 enum sh_divide_strategy_e {
508 extern enum sh_divide_strategy_e sh_div_strategy;
510 #ifndef SH_DIV_STRATEGY_DEFAULT
511 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
514 #define OVERRIDE_OPTIONS \
518 if (flag_finite_math_only == 2) \
519 flag_finite_math_only \
520 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
521 if (TARGET_SH2E && !flag_finite_math_only) \
522 target_flags |= MASK_IEEE; \
524 assembler_dialect = 0; \
532 if (TARGET_SH2A_DOUBLE) \
533 target_flags |= MASK_FMOVD; \
541 assembler_dialect = 1; \
544 if (TARGET_SH4A_ARCH) \
546 assembler_dialect = 1; \
552 target_flags |= MASK_ALIGN_DOUBLE; \
553 if (TARGET_SHMEDIA_FPU) \
554 target_flags |= MASK_FMOVD; \
555 if (TARGET_SHMEDIA) \
557 /* There are no delay slots on SHmedia. */ \
558 flag_delayed_branch = 0; \
559 /* Relaxation isn't yet supported for SHmedia */ \
560 target_flags &= ~MASK_RELAX; \
561 /* After reload, if conversion does little good but can cause \
563 - find_if_block doesn't do anything for SH because we don't\
564 have conditional execution patterns. (We use conditional\
565 move patterns, which are handled differently, and only \
567 - find_cond_trap doesn't do anything for the SH because we \
568 don't have conditional traps. \
569 - find_if_case_1 uses redirect_edge_and_branch_force in \
570 the only path that does an optimization, and this causes \
571 an ICE when branch targets are in registers. \
572 - find_if_case_2 doesn't do anything for the SHmedia after \
573 reload except when it can redirect a tablejump - and \
574 that's rather rare. */ \
575 flag_if_conversion2 = 0; \
576 if (! strcmp (sh_div_str, "call")) \
577 sh_div_strategy = SH_DIV_CALL; \
578 else if (! strcmp (sh_div_str, "call2")) \
579 sh_div_strategy = SH_DIV_CALL2; \
580 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
581 sh_div_strategy = SH_DIV_FP; \
582 else if (! strcmp (sh_div_str, "inv")) \
583 sh_div_strategy = SH_DIV_INV; \
584 else if (! strcmp (sh_div_str, "inv:minlat")) \
585 sh_div_strategy = SH_DIV_INV_MINLAT; \
586 else if (! strcmp (sh_div_str, "inv20u")) \
587 sh_div_strategy = SH_DIV_INV20U; \
588 else if (! strcmp (sh_div_str, "inv20l")) \
589 sh_div_strategy = SH_DIV_INV20L; \
590 else if (! strcmp (sh_div_str, "inv:call2")) \
591 sh_div_strategy = SH_DIV_INV_CALL2; \
592 else if (! strcmp (sh_div_str, "inv:call")) \
593 sh_div_strategy = SH_DIV_INV_CALL; \
594 else if (! strcmp (sh_div_str, "inv:fp")) \
596 if (TARGET_FPU_ANY) \
597 sh_div_strategy = SH_DIV_INV_FP; \
599 sh_div_strategy = SH_DIV_INV; \
602 /* -fprofile-arcs needs a working libgcov . In unified tree \
603 configurations with newlib, this requires to configure with \
604 --with-newlib --with-headers. But there is no way to check \
605 here we have a working libgcov, so just assume that we have. */\
607 warning (0, "profiling is still experimental for this target");\
611 /* Only the sh64-elf assembler fully supports .quad properly. */\
612 targetm.asm_out.aligned_op.di = NULL; \
613 targetm.asm_out.unaligned_op.di = NULL; \
615 if (sh_divsi3_libfunc[0]) \
616 ; /* User supplied - leave it alone. */ \
617 else if (TARGET_HARD_SH4 && TARGET_SH2E) \
618 sh_divsi3_libfunc = "__sdivsi3_i4"; \
619 else if (TARGET_SH5) \
621 if (TARGET_FPU_ANY && TARGET_SH1) \
622 sh_divsi3_libfunc = "__sdivsi3_i4"; \
624 sh_divsi3_libfunc = "__sdivsi3_1"; \
627 sh_divsi3_libfunc = "__sdivsi3"; \
629 reg_class_from_letter['e' - 'a'] = NO_REGS; \
631 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
632 if (! VALID_REGISTER_P (regno)) \
633 sh_register_names[regno][0] = '\0'; \
635 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
636 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
637 sh_additional_register_names[regno][0] = '\0'; \
639 if (flag_omit_frame_pointer < 0) \
641 /* The debugging information is sufficient, \
642 but gdb doesn't implement this yet */ \
644 flag_omit_frame_pointer \
645 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
647 flag_omit_frame_pointer = 0; \
650 if ((flag_pic && ! TARGET_PREFERGOT) \
651 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
652 flag_no_function_cse = 1; \
654 if (SMALL_REGISTER_CLASSES) \
656 /* Never run scheduling before reload, since that can \
657 break global alloc, and generates slower code anyway due \
658 to the pressure on R0. */ \
659 /* Enable sched1 for SH4; ready queue will be reordered by \
660 the target hooks when pressure is high. We can not do this for \
661 SH3 and lower as they give spill failures for R0. */ \
662 if (!TARGET_HARD_SH4) \
663 flag_schedule_insns = 0; \
666 if (align_loops == 0) \
667 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
668 if (align_jumps == 0) \
669 align_jumps = 1 << CACHE_LOG; \
670 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
671 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
673 /* Allocation boundary (in *bytes*) for the code of a function. \
674 SH1: 32 bit alignment is faster, because instructions are always \
675 fetched as a pair from a longword boundary. \
676 SH2 .. SH5 : align to cache line start. */ \
677 if (align_functions == 0) \
679 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
680 /* The linker relaxation code breaks when a function contains \
681 alignments that are larger than that at the start of a \
682 compilation unit. */ \
686 = align_loops > align_jumps ? align_loops : align_jumps; \
688 /* Also take possible .long constants / mova tables int account. */\
691 if (align_functions < min_align) \
692 align_functions = min_align; \
696 /* Target machine storage layout. */
698 /* Define this if most significant bit is lowest numbered
699 in instructions that operate on numbered bit-fields. */
701 #define BITS_BIG_ENDIAN 0
703 /* Define this if most significant byte of a word is the lowest numbered. */
704 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
706 /* Define this if most significant word of a multiword number is the lowest
708 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
710 /* Define this to set the endianness to use in libgcc2.c, which can
711 not depend on target_flags. */
712 #if defined(__LITTLE_ENDIAN__)
713 #define LIBGCC2_WORDS_BIG_ENDIAN 0
715 #define LIBGCC2_WORDS_BIG_ENDIAN 1
718 #define MAX_BITS_PER_WORD 64
720 /* Width in bits of an `int'. We want just 32-bits, even if words are
722 #define INT_TYPE_SIZE 32
724 /* Width in bits of a `long'. */
725 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
727 /* Width in bits of a `long long'. */
728 #define LONG_LONG_TYPE_SIZE 64
730 /* Width in bits of a `long double'. */
731 #define LONG_DOUBLE_TYPE_SIZE 64
733 /* Width of a word, in units (bytes). */
734 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
735 #define MIN_UNITS_PER_WORD 4
737 /* Scaling factor for Dwarf data offsets for CFI information.
738 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
739 SHmedia; however, since we do partial register saves for the registers
740 visible to SHcompact, and for target registers for SHMEDIA32, we have
741 to allow saves that are only 4-byte aligned. */
742 #define DWARF_CIE_DATA_ALIGNMENT -4
744 /* Width in bits of a pointer.
745 See also the macro `Pmode' defined below. */
746 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
748 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
749 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
751 /* Boundary (in *bits*) on which stack pointer should be aligned. */
752 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
754 /* The log (base 2) of the cache line size, in bytes. Processors prior to
755 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
756 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
757 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
759 /* ABI given & required minimum allocation boundary (in *bits*) for the
760 code of a function. */
761 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
763 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
764 the vbit must go into the delta field of
765 pointers-to-member-functions. */
766 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
767 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
769 /* Alignment of field after `int : 0' in a structure. */
770 #define EMPTY_FIELD_BOUNDARY 32
772 /* No data type wants to be aligned rounder than this. */
773 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
775 /* The best alignment to use in cases where we have a choice. */
776 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
778 /* Make strings word-aligned so strcpy from constants will be faster. */
779 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
780 ((TREE_CODE (EXP) == STRING_CST \
781 && (ALIGN) < FASTEST_ALIGNMENT) \
782 ? FASTEST_ALIGNMENT : (ALIGN))
784 /* get_mode_alignment assumes complex values are always held in multiple
785 registers, but that is not the case on the SH; CQImode and CHImode are
786 held in a single integer register. SH5 also holds CSImode and SCmode
787 values in integer registers. This is relevant for argument passing on
788 SHcompact as we use a stack temp in order to pass CSImode by reference. */
789 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
790 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
791 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
792 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
795 /* Make arrays of chars word-aligned for the same reasons. */
796 #define DATA_ALIGNMENT(TYPE, ALIGN) \
797 (TREE_CODE (TYPE) == ARRAY_TYPE \
798 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
799 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
801 /* Number of bits which any structure or union's size must be a
802 multiple of. Each structure or union's size is rounded up to a
804 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
806 /* Set this nonzero if move instructions will actually fail to work
807 when given unaligned data. */
808 #define STRICT_ALIGNMENT 1
810 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
811 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
812 barrier_align (LABEL_AFTER_BARRIER)
814 #define LOOP_ALIGN(A_LABEL) \
815 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
816 ? 0 : sh_loop_align (A_LABEL))
818 #define LABEL_ALIGN(A_LABEL) \
820 (PREV_INSN (A_LABEL) \
821 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
822 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
823 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
824 /* explicit alignment insn in constant tables. */ \
825 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
828 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
829 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
831 /* The base two logarithm of the known minimum alignment of an insn length. */
832 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
833 (GET_CODE (A_INSN) == INSN \
834 ? 1 << TARGET_SHMEDIA \
835 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
836 ? 1 << TARGET_SHMEDIA \
839 /* Standard register usage. */
841 /* Register allocation for the Renesas calling convention:
847 r14 frame pointer/call saved
849 ap arg pointer (doesn't really exist, always eliminated)
850 pr subroutine return address
852 mach multiply/accumulate result, high part
853 macl multiply/accumulate result, low part.
854 fpul fp/int communication register
855 rap return address pointer register
857 fr1..fr3 scratch floating point registers
859 fr12..fr15 call saved floating point registers */
861 #define MAX_REGISTER_NAME_LENGTH 5
862 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
864 #define SH_REGISTER_NAMES_INITIALIZER \
866 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
867 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
868 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
869 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
870 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
871 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
872 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
873 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
874 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
875 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
876 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
877 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
878 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
879 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
880 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
881 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
882 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
883 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
884 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
888 #define REGNAMES_ARR_INDEX_1(index) \
889 (sh_register_names[index])
890 #define REGNAMES_ARR_INDEX_2(index) \
891 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
892 #define REGNAMES_ARR_INDEX_4(index) \
893 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
894 #define REGNAMES_ARR_INDEX_8(index) \
895 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
896 #define REGNAMES_ARR_INDEX_16(index) \
897 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
898 #define REGNAMES_ARR_INDEX_32(index) \
899 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
900 #define REGNAMES_ARR_INDEX_64(index) \
901 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
903 #define REGISTER_NAMES \
905 REGNAMES_ARR_INDEX_64 (0), \
906 REGNAMES_ARR_INDEX_64 (64), \
907 REGNAMES_ARR_INDEX_8 (128), \
908 REGNAMES_ARR_INDEX_8 (136), \
909 REGNAMES_ARR_INDEX_8 (144), \
910 REGNAMES_ARR_INDEX_2 (152) \
913 #define ADDREGNAMES_SIZE 32
914 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
915 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
916 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
918 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
920 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
921 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
922 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
923 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
926 #define ADDREGNAMES_REGNO(index) \
927 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
930 #define ADDREGNAMES_ARR_INDEX_1(index) \
931 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
932 #define ADDREGNAMES_ARR_INDEX_2(index) \
933 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
934 #define ADDREGNAMES_ARR_INDEX_4(index) \
935 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
936 #define ADDREGNAMES_ARR_INDEX_8(index) \
937 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
938 #define ADDREGNAMES_ARR_INDEX_16(index) \
939 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
940 #define ADDREGNAMES_ARR_INDEX_32(index) \
941 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
943 #define ADDITIONAL_REGISTER_NAMES \
945 ADDREGNAMES_ARR_INDEX_32 (0) \
948 /* Number of actual hardware registers.
949 The hardware registers are assigned numbers for the compiler
950 from 0 to just below FIRST_PSEUDO_REGISTER.
951 All registers that the compiler knows about must be given numbers,
952 even those that are not normally considered general registers. */
954 /* There are many other relevant definitions in sh.md's md_constants. */
956 #define FIRST_GENERAL_REG R0_REG
957 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
958 #define FIRST_FP_REG DR0_REG
959 #define LAST_FP_REG (FIRST_FP_REG + \
960 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
961 #define FIRST_XD_REG XD0_REG
962 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
963 #define FIRST_TARGET_REG TR0_REG
964 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
966 #define GENERAL_REGISTER_P(REGNO) \
968 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
969 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
971 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
972 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
973 || ((REGNO) == FRAME_POINTER_REGNUM))
975 #define FP_REGISTER_P(REGNO) \
976 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
978 #define XD_REGISTER_P(REGNO) \
979 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
981 #define FP_OR_XD_REGISTER_P(REGNO) \
982 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
984 #define FP_ANY_REGISTER_P(REGNO) \
985 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
987 #define SPECIAL_REGISTER_P(REGNO) \
988 ((REGNO) == GBR_REG || (REGNO) == T_REG \
989 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
991 #define TARGET_REGISTER_P(REGNO) \
992 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
994 #define SHMEDIA_REGISTER_P(REGNO) \
995 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
996 || TARGET_REGISTER_P (REGNO))
998 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
999 that should be fixed. */
1000 #define VALID_REGISTER_P(REGNO) \
1001 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1002 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1003 || (REGNO) == FRAME_POINTER_REGNUM \
1004 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1005 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1007 /* The mode that should be generally used to store a register by
1008 itself in the stack, or to load it back. */
1009 #define REGISTER_NATURAL_MODE(REGNO) \
1010 (FP_REGISTER_P (REGNO) ? SFmode \
1011 : XD_REGISTER_P (REGNO) ? DFmode \
1012 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1016 #define FIRST_PSEUDO_REGISTER 154
1018 /* Don't count soft frame pointer. */
1019 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1021 /* 1 for registers that have pervasive standard uses
1022 and are not available for the register allocator.
1024 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1025 It is 32 bits wide for SH2. */
1027 #define FIXED_REGISTERS \
1029 /* Regular registers. */ \
1030 0, 0, 0, 0, 0, 0, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 1, \
1032 /* r16 is reserved, r18 is the former pr. */ \
1033 1, 0, 0, 0, 0, 0, 0, 0, \
1034 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1035 /* r26 is a global variable data pointer; r27 is for constants. */ \
1036 1, 1, 1, 1, 0, 0, 0, 0, \
1037 0, 0, 0, 0, 0, 0, 0, 0, \
1038 0, 0, 0, 0, 0, 0, 0, 0, \
1039 0, 0, 0, 0, 0, 0, 0, 0, \
1040 0, 0, 0, 0, 0, 0, 0, 1, \
1041 /* FP registers. */ \
1042 0, 0, 0, 0, 0, 0, 0, 0, \
1043 0, 0, 0, 0, 0, 0, 0, 0, \
1044 0, 0, 0, 0, 0, 0, 0, 0, \
1045 0, 0, 0, 0, 0, 0, 0, 0, \
1046 0, 0, 0, 0, 0, 0, 0, 0, \
1047 0, 0, 0, 0, 0, 0, 0, 0, \
1048 0, 0, 0, 0, 0, 0, 0, 0, \
1049 0, 0, 0, 0, 0, 0, 0, 0, \
1050 /* Branch target registers. */ \
1051 0, 0, 0, 0, 0, 0, 0, 0, \
1052 /* XD registers. */ \
1053 0, 0, 0, 0, 0, 0, 0, 0, \
1054 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1055 1, 1, 1, 1, 1, 1, 0, 1, \
1060 /* 1 for registers not available across function calls.
1061 These must include the FIXED_REGISTERS and also any
1062 registers that can be used without being saved.
1063 The latter must include the registers where values are returned
1064 and the register where structure-value addresses are passed.
1065 Aside from that, you can include as many other registers as you like. */
1067 #define CALL_USED_REGISTERS \
1069 /* Regular registers. */ \
1070 1, 1, 1, 1, 1, 1, 1, 1, \
1071 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1072 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1073 across SH5 function calls. */ \
1074 0, 0, 0, 0, 0, 0, 0, 1, \
1075 1, 1, 1, 1, 1, 1, 1, 1, \
1076 1, 1, 1, 1, 0, 0, 0, 0, \
1077 0, 0, 0, 0, 1, 1, 1, 1, \
1078 1, 1, 1, 1, 0, 0, 0, 0, \
1079 0, 0, 0, 0, 0, 0, 0, 0, \
1080 0, 0, 0, 0, 1, 1, 1, 1, \
1081 /* FP registers. */ \
1082 1, 1, 1, 1, 1, 1, 1, 1, \
1083 1, 1, 1, 1, 0, 0, 0, 0, \
1084 1, 1, 1, 1, 1, 1, 1, 1, \
1085 1, 1, 1, 1, 1, 1, 1, 1, \
1086 1, 1, 1, 1, 0, 0, 0, 0, \
1087 0, 0, 0, 0, 0, 0, 0, 0, \
1088 0, 0, 0, 0, 0, 0, 0, 0, \
1089 0, 0, 0, 0, 0, 0, 0, 0, \
1090 /* Branch target registers. */ \
1091 1, 1, 1, 1, 1, 0, 0, 0, \
1092 /* XD registers. */ \
1093 1, 1, 1, 1, 1, 1, 0, 0, \
1094 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1095 1, 1, 1, 1, 1, 1, 1, 1, \
1100 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1101 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1102 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1104 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1105 across SHcompact function calls. We can't tell whether a called
1106 function is SHmedia or SHcompact, so we assume it may be when
1107 compiling SHmedia code with the 32-bit ABI, since that's the only
1108 ABI that can be linked with SHcompact code. */
1109 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1111 && GET_MODE_SIZE (MODE) > 4 \
1112 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1113 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1114 || TARGET_REGISTER_P (REGNO) \
1115 || (REGNO) == PR_MEDIA_REG))
1117 /* Return number of consecutive hard regs needed starting at reg REGNO
1118 to hold something of mode MODE.
1119 This is ordinarily the length in words of a value of mode MODE
1120 but can be less for certain modes in special long registers.
1122 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1124 #define HARD_REGNO_NREGS(REGNO, MODE) \
1125 (XD_REGISTER_P (REGNO) \
1126 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1127 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1128 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1129 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1131 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1132 We can allow any mode in any general register. The special registers
1133 only allow SImode. Don't allow any mode in the PR. */
1135 /* We cannot hold DCmode values in the XD registers because alter_reg
1136 handles subregs of them incorrectly. We could work around this by
1137 spacing the XD registers like the DR registers, but this would require
1138 additional memory in every compilation to hold larger register vectors.
1139 We could hold SFmode / SCmode values in XD registers, but that
1140 would require a tertiary reload when reloading from / to memory,
1141 and a secondary reload to reload from / to general regs; that
1142 seems to be a loosing proposition. */
1143 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1144 it won't be ferried through GP registers first. */
1145 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1146 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1147 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1148 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1150 : (MODE) == V2SFmode \
1151 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1152 || GENERAL_REGISTER_P (REGNO)) \
1153 : (MODE) == V4SFmode \
1154 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1155 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1156 : (MODE) == V16SFmode \
1158 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1159 : (REGNO) == FIRST_XD_REG) \
1160 : FP_REGISTER_P (REGNO) \
1161 ? ((MODE) == SFmode || (MODE) == SImode \
1162 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1163 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1164 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1165 || (MODE) == V2SFmode || (MODE) == TImode))) \
1166 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1167 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1168 && (MODE) == TImode \
1169 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1170 : XD_REGISTER_P (REGNO) \
1171 ? (MODE) == DFmode \
1172 : TARGET_REGISTER_P (REGNO) \
1173 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1174 : (REGNO) == PR_REG ? (MODE) == SImode \
1175 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1178 /* Value is 1 if it is a good idea to tie two pseudo registers
1179 when one has mode MODE1 and one has mode MODE2.
1180 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1181 for any hard reg, then this must be 0 for correct output.
1182 That's the case for xd registers: we don't hold SFmode values in
1183 them, so we can't tie an SFmode pseudos with one in another
1184 floating-point mode. */
1186 #define MODES_TIEABLE_P(MODE1, MODE2) \
1187 ((MODE1) == (MODE2) \
1188 || (TARGET_SHMEDIA \
1189 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1190 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1191 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1192 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1193 && (GET_MODE_SIZE (MODE2) <= 4)) \
1194 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1196 /* A C expression that is nonzero if hard register NEW_REG can be
1197 considered for use as a rename register for OLD_REG register */
1199 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1200 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1202 /* Specify the registers used for certain standard purposes.
1203 The values of these macros are register numbers. */
1205 /* Define this if the program counter is overloaded on a register. */
1206 /* #define PC_REGNUM 15*/
1208 /* Register to use for pushing function arguments. */
1209 #define STACK_POINTER_REGNUM SP_REG
1211 /* Base register for access to local variables of the function. */
1212 #define HARD_FRAME_POINTER_REGNUM FP_REG
1214 /* Base register for access to local variables of the function. */
1215 #define FRAME_POINTER_REGNUM 153
1217 /* Fake register that holds the address on the stack of the
1218 current function's return address. */
1219 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1221 /* Register to hold the addressing base for position independent
1222 code access to data items. */
1223 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1225 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1227 /* Value should be nonzero if functions must have frame pointers.
1228 Zero means the frame pointer need not be set up (and parms may be accessed
1229 via the stack pointer) in functions that seem suitable. */
1231 #define FRAME_POINTER_REQUIRED 0
1233 /* Definitions for register eliminations.
1235 We have three registers that can be eliminated on the SH. First, the
1236 frame pointer register can often be eliminated in favor of the stack
1237 pointer register. Secondly, the argument pointer register can always be
1238 eliminated; it is replaced with either the stack or frame pointer.
1239 Third, there is the return address pointer, which can also be replaced
1240 with either the stack or the frame pointer. */
1242 /* This is an array of structures. Each structure initializes one pair
1243 of eliminable registers. The "from" register number is given first,
1244 followed by "to". Eliminations of the same "from" register are listed
1245 in order of preference. */
1247 /* If you add any registers here that are not actually hard registers,
1248 and that have any alternative of elimination that doesn't always
1249 apply, you need to amend calc_live_regs to exclude it, because
1250 reload spills all eliminable registers where it sees an
1251 can_eliminate == 0 entry, thus making them 'live' .
1252 If you add any hard registers that can be eliminated in different
1253 ways, you have to patch reload to spill them only when all alternatives
1254 of elimination fail. */
1256 #define ELIMINABLE_REGS \
1257 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1258 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1259 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1260 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1261 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1262 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1263 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1265 /* Given FROM and TO register numbers, say whether this elimination
1267 #define CAN_ELIMINATE(FROM, TO) \
1268 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1270 /* Define the offset between two registers, one to be eliminated, and the other
1271 its replacement, at the start of a routine. */
1273 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1274 OFFSET = initial_elimination_offset ((FROM), (TO))
1276 /* Base register for access to arguments of the function. */
1277 #define ARG_POINTER_REGNUM AP_REG
1279 /* Register in which the static-chain is passed to a function. */
1280 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1282 /* Don't default to pcc-struct-return, because we have already specified
1283 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1286 #define DEFAULT_PCC_STRUCT_RETURN 0
1288 #define SHMEDIA_REGS_STACK_ADJUST() \
1289 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1290 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1291 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1295 /* Define the classes of registers for register constraints in the
1296 machine description. Also define ranges of constants.
1298 One of the classes must always be named ALL_REGS and include all hard regs.
1299 If there is more than one class, another class must be named NO_REGS
1300 and contain no registers.
1302 The name GENERAL_REGS must be the name of a class (or an alias for
1303 another name such as ALL_REGS). This is the class of registers
1304 that is allowed by "g" or "r" in a register constraint.
1305 Also, registers outside this class are allocated only when
1306 instructions express preferences for them.
1308 The classes must be numbered in nondecreasing order; that is,
1309 a larger-numbered class must never be contained completely
1310 in a smaller-numbered class.
1312 For any two classes, it is very desirable that there be another
1313 class that represents their union. */
1315 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1316 be used as the destination of some of the arithmetic ops. There are
1317 also some special purpose registers; the T bit register, the
1318 Procedure Return Register and the Multiply Accumulate Registers. */
1319 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1320 reg_class_subunion. We don't want to have an actual union class
1321 of these, because it would only be used when both classes are calculated
1322 to give the same cost, but there is only one FPUL register.
1323 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1324 applying to the actual instruction alternative considered. E.g., the
1325 y/r alternative of movsi_ie is considered to have no more cost that
1326 the r/r alternative, which is patently untrue. */
1349 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1351 /* Give names of register classes as strings for dump file. */
1352 #define REG_CLASS_NAMES \
1367 "GENERAL_FP_REGS", \
1372 /* Define which registers fit in which classes.
1373 This is an initializer for a vector of HARD_REG_SET
1374 of length N_REG_CLASSES. */
1376 #define REG_CLASS_CONTENTS \
1379 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1381 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1383 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1385 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1387 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1389 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1390 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1391 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1392 /* GENERAL_REGS: */ \
1393 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1395 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1397 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1398 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1399 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1401 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1403 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1404 /* GENERAL_FP_REGS: */ \
1405 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1406 /* TARGET_REGS: */ \
1407 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1409 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1412 /* The same information, inverted:
1413 Return the class number of the smallest class containing
1414 reg number REGNO. This could be a conditional expression
1415 or could index an array. */
1417 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1418 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1420 /* When defined, the compiler allows registers explicitly used in the
1421 rtl to be used as spill registers but prevents the compiler from
1422 extending the lifetime of these registers. */
1424 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1426 /* The order in which register should be allocated. */
1427 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1428 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1429 spilled or used otherwise, we better have the FP_REGS allocated first. */
1430 #define REG_ALLOC_ORDER \
1431 {/* Caller-saved FPRs */ \
1432 65, 66, 67, 68, 69, 70, 71, 64, \
1433 72, 73, 74, 75, 80, 81, 82, 83, \
1434 84, 85, 86, 87, 88, 89, 90, 91, \
1435 92, 93, 94, 95, 96, 97, 98, 99, \
1436 /* Callee-saved FPRs */ \
1437 76, 77, 78, 79,100,101,102,103, \
1438 104,105,106,107,108,109,110,111, \
1439 112,113,114,115,116,117,118,119, \
1440 120,121,122,123,124,125,126,127, \
1441 136,137,138,139,140,141,142,143, \
1443 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1444 1, 2, 3, 7, 6, 5, 4, 0, \
1445 8, 9, 17, 19, 20, 21, 22, 23, \
1446 36, 37, 38, 39, 40, 41, 42, 43, \
1448 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1449 10, 11, 12, 13, 14, 18, \
1450 /* SH5 callee-saved GPRs */ \
1451 28, 29, 30, 31, 32, 33, 34, 35, \
1452 44, 45, 46, 47, 48, 49, 50, 51, \
1453 52, 53, 54, 55, 56, 57, 58, 59, \
1455 /* SH5 branch target registers */ \
1456 128,129,130,131,132,133,134,135, \
1457 /* Fixed registers */ \
1458 15, 16, 24, 25, 26, 27, 63,144, \
1459 145,146,147,148,149,152,153 }
1461 /* The class value for index registers, and the one for base regs. */
1462 #define INDEX_REG_CLASS \
1463 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1464 #define BASE_REG_CLASS GENERAL_REGS
1466 /* Get reg_class from a letter such as appears in the machine
1468 extern enum reg_class reg_class_from_letter[];
1470 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1471 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1472 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1474 /* Overview of uppercase letter constraints:
1475 A: Addresses (constraint len == 3)
1476 Ac4: sh4 cache operations
1477 Ac5: sh5 cache operations
1478 Bxx: miscellaneous constraints
1479 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1481 C: Constants other than only CONST_INT (constraint len == 3)
1482 C16: 16 bit constant, literal or symbolic
1483 Csy: label or symbol
1484 Cpg: non-explicit constants that can be directly loaded into a general
1485 purpose register in PIC code. like 's' except we don't allow
1487 IJKLMNOP: CONT_INT constants
1489 J16: 0xffffffff00000000 | 0x00000000ffffffff
1490 Kxx: unsigned xx bit
1494 Q: pc relative load operand
1495 Rxx: reserved for exotic register classes.
1496 S: extra memory (storage) constraints (constraint len == 3)
1497 Sua: unaligned memory operations
1501 unused CONST_INT constraint letters: LO
1502 unused EXTRA_CONSTRAINT letters: D T U Y */
1504 #define CONSTRAINT_LEN(C,STR) \
1505 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1506 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1507 || (C) == 'R' || (C) == 'S') \
1508 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1510 /* The letters I, J, K, L and M in a register constraint string
1511 can be used to stand for particular ranges of immediate operands.
1512 This macro defines what the ranges are.
1513 C is the letter, and VALUE is a constant value.
1514 Return 1 if VALUE is in the range specified by C.
1515 I08: arithmetic operand -127..128, as used in add, sub, etc
1516 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1517 P27: shift operand 1,2,8 or 16
1518 K08: logical operand 0..255, as used in and, or, etc.
1521 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1522 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1525 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1526 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1527 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1528 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1529 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1530 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1531 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1532 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1533 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1534 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1536 #define CONST_OK_FOR_I(VALUE, STR) \
1537 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1538 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1539 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1540 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1541 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1544 #define CONST_OK_FOR_J16(VALUE) \
1545 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1546 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1547 #define CONST_OK_FOR_J(VALUE, STR) \
1548 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1551 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1552 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1553 #define CONST_OK_FOR_K(VALUE, STR) \
1554 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1556 #define CONST_OK_FOR_P27(VALUE) \
1557 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1558 #define CONST_OK_FOR_P(VALUE, STR) \
1559 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1561 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1562 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1563 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1564 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1565 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1566 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1567 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1568 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1569 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1572 /* Similar, but for floating constants, and defining letters G and H.
1573 Here VALUE is the CONST_DOUBLE rtx itself. */
1575 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1576 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1577 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1580 /* Given an rtx X being reloaded into a reg required to be
1581 in class CLASS, return the class of reg to actually use.
1582 In general this is just CLASS; but on some machines
1583 in some cases it is preferable to use a more restrictive class. */
1585 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1586 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1587 && (GET_CODE (X) == CONST_DOUBLE \
1588 || GET_CODE (X) == SYMBOL_REF \
1589 || PIC_DIRECT_ADDR_P (X)) \
1593 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1594 ((((REGCLASS_HAS_FP_REG (CLASS) \
1595 && (GET_CODE (X) == REG \
1596 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1597 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1598 && TARGET_FMOVD)))) \
1599 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1600 && GET_CODE (X) == REG \
1601 && FP_REGISTER_P (REGNO (X)))) \
1602 && ! TARGET_SHMEDIA \
1603 && ((MODE) == SFmode || (MODE) == SImode)) \
1605 : (((CLASS) == FPUL_REGS \
1606 || (REGCLASS_HAS_FP_REG (CLASS) \
1607 && ! TARGET_SHMEDIA && MODE == SImode)) \
1608 && (GET_CODE (X) == MEM \
1609 || (GET_CODE (X) == REG \
1610 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1611 || REGNO (X) == T_REG \
1612 || system_reg_operand (X, VOIDmode))))) \
1614 : (((CLASS) == TARGET_REGS \
1615 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1616 && !EXTRA_CONSTRAINT_Csy (X) \
1617 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1619 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1620 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1621 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1623 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1624 && TARGET_REGISTER_P (REGNO (X))) \
1625 ? GENERAL_REGS : (ELSE))
1627 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1628 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1630 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1631 ((REGCLASS_HAS_FP_REG (CLASS) \
1632 && ! TARGET_SHMEDIA \
1633 && immediate_operand ((X), (MODE)) \
1634 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1635 && (MODE) == SFmode && fldi_ok ())) \
1637 : ((CLASS) == FPUL_REGS \
1638 && ((GET_CODE (X) == REG \
1639 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1640 || REGNO (X) == T_REG)) \
1641 || GET_CODE (X) == PLUS)) \
1643 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1644 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1647 : ((CLASS) == FPSCR_REGS \
1648 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1649 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1651 : (REGCLASS_HAS_FP_REG (CLASS) \
1653 && immediate_operand ((X), (MODE)) \
1654 && (X) != CONST0_RTX (GET_MODE (X)) \
1655 && GET_MODE (X) != V4SFmode) \
1657 : (((MODE) == QImode || (MODE) == HImode) \
1658 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1660 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1661 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1663 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1665 /* Return the maximum number of consecutive registers
1666 needed to represent mode MODE in a register of class CLASS.
1668 If TARGET_SHMEDIA, we need two FP registers per word.
1669 Otherwise we will need at most one register per word. */
1670 #define CLASS_MAX_NREGS(CLASS, MODE) \
1672 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1673 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1674 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1676 /* If defined, gives a class of registers that cannot be used as the
1677 operand of a SUBREG that changes the mode of the object illegally. */
1678 /* ??? We need to renumber the internal numbers for the frnn registers
1679 when in little endian in order to allow mode size changes. */
1681 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1682 sh_cannot_change_mode_class (FROM, TO, CLASS)
1684 /* Stack layout; function entry, exit and calling. */
1686 /* Define the number of registers that can hold parameters.
1687 These macros are used only in other macro definitions below. */
1689 #define NPARM_REGS(MODE) \
1690 (TARGET_FPU_ANY && (MODE) == SFmode \
1691 ? (TARGET_SH5 ? 12 : 8) \
1692 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1693 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1694 ? (TARGET_SH5 ? 12 : 8) \
1695 : (TARGET_SH5 ? 8 : 4))
1697 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1698 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1700 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1701 #define FIRST_FP_RET_REG FIRST_FP_REG
1703 /* Define this if pushing a word on the stack
1704 makes the stack pointer a smaller address. */
1705 #define STACK_GROWS_DOWNWARD
1707 /* Define this macro to nonzero if the addresses of local variable slots
1708 are at negative offsets from the frame pointer. */
1709 #define FRAME_GROWS_DOWNWARD 1
1711 /* Offset from the frame pointer to the first local variable slot to
1713 #define STARTING_FRAME_OFFSET 0
1715 /* If we generate an insn to push BYTES bytes,
1716 this says how many the stack pointer really advances by. */
1717 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1718 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1719 do correct alignment. */
1721 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1724 /* Offset of first parameter from the argument pointer register value. */
1725 #define FIRST_PARM_OFFSET(FNDECL) 0
1727 /* Value is the number of byte of arguments automatically
1728 popped when returning from a subroutine call.
1729 FUNDECL is the declaration node of the function (as a tree),
1730 FUNTYPE is the data type of the function (as a tree),
1731 or for a library call it is an identifier node for the subroutine name.
1732 SIZE is the number of bytes of arguments passed on the stack.
1734 On the SH, the caller does not pop any of its arguments that were passed
1736 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1738 /* Value is the number of bytes of arguments automatically popped when
1739 calling a subroutine.
1740 CUM is the accumulated argument list.
1742 On SHcompact, the call trampoline pops arguments off the stack. */
1743 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1745 /* Some subroutine macros specific to this machine. */
1747 #define BASE_RETURN_VALUE_REG(MODE) \
1748 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1749 ? FIRST_FP_RET_REG \
1750 : TARGET_FPU_ANY && (MODE) == SCmode \
1751 ? FIRST_FP_RET_REG \
1752 : (TARGET_FPU_DOUBLE \
1753 && ((MODE) == DFmode || (MODE) == SFmode \
1754 || (MODE) == DCmode || (MODE) == SCmode )) \
1755 ? FIRST_FP_RET_REG \
1758 #define BASE_ARG_REG(MODE) \
1759 ((TARGET_SH2E && ((MODE) == SFmode)) \
1760 ? FIRST_FP_PARM_REG \
1761 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1762 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1763 ? FIRST_FP_PARM_REG \
1766 /* Define how to find the value returned by a function.
1767 VALTYPE is the data type of the value (as a tree).
1768 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1769 otherwise, FUNC is 0.
1770 For the SH, this is like LIBCALL_VALUE, except that we must change the
1771 mode like PROMOTE_MODE does.
1772 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1773 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1775 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1777 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1778 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1779 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1780 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1781 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1782 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1783 || TREE_CODE (VALTYPE) == REAL_TYPE \
1784 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1785 && sh_promote_prototypes (VALTYPE) \
1786 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1787 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1789 /* Define how to find the value returned by a library function
1790 assuming the value has mode MODE. */
1791 #define LIBCALL_VALUE(MODE) \
1792 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1794 /* 1 if N is a possible register number for a function value. */
1795 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1796 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1797 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1799 /* 1 if N is a possible register number for function argument passing. */
1800 /* ??? There are some callers that pass REGNO as int, and others that pass
1801 it as unsigned. We get warnings unless we do casts everywhere. */
1802 #define FUNCTION_ARG_REGNO_P(REGNO) \
1803 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1804 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1805 || (TARGET_FPU_ANY \
1806 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1807 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1808 + NPARM_REGS (SFmode))))
1810 /* Define a data type for recording info about an argument list
1811 during the scan of that argument list. This data type should
1812 hold all necessary information about the function itself
1813 and about the args processed so far, enough to enable macros
1814 such as FUNCTION_ARG to determine where the next arg should go.
1816 On SH, this is a single integer, which is a number of words
1817 of arguments scanned so far (including the invisible argument,
1818 if any, which holds the structure-value-address).
1819 Thus NARGREGS or more means all following args should go on the stack. */
1821 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1825 /* Nonzero if a prototype is available for the function. */
1827 /* The number of an odd floating-point register, that should be used
1828 for the next argument of type float. */
1829 int free_single_fp_reg;
1830 /* Whether we're processing an outgoing function call. */
1832 /* The number of general-purpose registers that should have been
1833 used to pass partial arguments, that are passed totally on the
1834 stack. On SHcompact, a call trampoline will pop them off the
1835 stack before calling the actual function, and, if the called
1836 function is implemented in SHcompact mode, the incoming arguments
1837 decoder will push such arguments back onto the stack. For
1838 incoming arguments, STACK_REGS also takes into account other
1839 arguments passed by reference, that the decoder will also push
1842 /* The number of general-purpose registers that should have been
1843 used to pass arguments, if the arguments didn't have to be passed
1846 /* Set as by shcompact_byref if the current argument is to be passed
1850 /* call_cookie is a bitmask used by call expanders, as well as
1851 function prologue and epilogues, to allow SHcompact to comply
1852 with the SH5 32-bit ABI, that requires 64-bit registers to be
1853 used even though only the lower 32-bit half is visible in
1854 SHcompact mode. The strategy is to call SHmedia trampolines.
1856 The alternatives for each of the argument-passing registers are
1857 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1858 contents from the address in it; (d) add 8 to it, storing the
1859 result in the next register, then (c); (e) copy it from some
1860 floating-point register,
1862 Regarding copies from floating-point registers, r2 may only be
1863 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1864 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1865 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1866 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1869 The bit mask is structured as follows:
1871 - 1 bit to tell whether to set up a return trampoline.
1873 - 3 bits to count the number consecutive registers to pop off the
1876 - 4 bits for each of r9, r8, r7 and r6.
1878 - 3 bits for each of r5, r4, r3 and r2.
1880 - 3 bits set to 0 (the most significant ones)
1883 1098 7654 3210 9876 5432 1098 7654 3210
1884 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1885 2223 3344 4555 6666 7777 8888 9999 SSS-
1887 - If F is set, the register must be copied from an FP register,
1888 whose number is encoded in the remaining bits.
1890 - Else, if L is set, the register must be loaded from the address
1891 contained in it. If the P bit is *not* set, the address of the
1892 following dword should be computed first, and stored in the
1895 - Else, if P is set, the register alone should be popped off the
1898 - After all this processing, the number of registers represented
1899 in SSS will be popped off the stack. This is an optimization
1900 for pushing/popping consecutive registers, typically used for
1901 varargs and large arguments partially passed in registers.
1903 - If T is set, a return trampoline will be set up for 64-bit
1904 return values to be split into 2 32-bit registers. */
1905 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1906 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1907 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1908 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1909 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1910 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1911 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1912 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1913 #define CALL_COOKIE_INT_REG(REG, VAL) \
1914 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1915 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1916 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1919 /* This is set to nonzero when the call in question must use the Renesas ABI,
1920 even without the -mrenesas option. */
1924 #define CUMULATIVE_ARGS struct sh_args
1926 #define GET_SH_ARG_CLASS(MODE) \
1927 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1929 /* There's no mention of complex float types in the SH5 ABI, so we
1930 should presumably handle them as aggregate types. */ \
1931 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1933 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1934 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1935 ? SH_ARG_FLOAT : SH_ARG_INT)
1937 #define ROUND_ADVANCE(SIZE) \
1938 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1940 /* Round a register number up to a proper boundary for an arg of mode
1943 The SH doesn't care about double alignment, so we only
1944 round doubles to even regs when asked to explicitly. */
1946 #define ROUND_REG(CUM, MODE) \
1947 (((TARGET_ALIGN_DOUBLE \
1948 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1949 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1950 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1951 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1952 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1953 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1955 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1956 for a call to a function whose data type is FNTYPE.
1957 For a library call, FNTYPE is 0.
1959 On SH, the offset always starts at 0: the first parm reg is always
1960 the same reg for a given argument class.
1962 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1964 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1965 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1967 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1968 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1970 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1971 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1972 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1973 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1975 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1976 This macro is only used in this file. */
1978 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1980 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1981 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1982 || ! (AGGREGATE_TYPE_P (TYPE) \
1983 || (!TARGET_FPU_ANY \
1984 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1985 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1986 && ! (CUM).force_mem \
1988 ? ((MODE) == BLKmode \
1989 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1990 + int_size_in_bytes (TYPE)) \
1991 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1992 : ((ROUND_REG((CUM), (MODE)) \
1993 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1994 <= NPARM_REGS (MODE))) \
1995 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1997 /* By accident we got stuck with passing SCmode on SH4 little endian
1998 in two registers that are nominally successive - which is different from
1999 two single SFmode values, where we take endianness translation into
2000 account. That does not work at all if an odd number of registers is
2001 already in use, so that got fixed, but library functions are still more
2002 likely to use complex numbers without mixing them with SFmode arguments
2003 (which in C would have to be structures), so for the sake of ABI
2004 compatibility the way SCmode values are passed when an even number of
2005 FP registers is in use remains different from a pair of SFmode values for
2008 foo (double); a: fr5,fr4
2009 foo (float a, float b); a: fr5 b: fr4
2010 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2011 this should be the other way round...
2012 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2013 #define FUNCTION_ARG_SCmode_WART 1
2015 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2016 register in SHcompact mode, it must be padded in the most
2017 significant end. This means that passing it by reference wouldn't
2018 pad properly on a big-endian machine. In this particular case, we
2019 pass this argument on the stack, in a way that the call trampoline
2020 will load its value into the appropriate register. */
2021 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2022 ((MODE) == BLKmode \
2023 && TARGET_SHCOMPACT \
2024 && ! TARGET_LITTLE_ENDIAN \
2025 && int_size_in_bytes (TYPE) > 4 \
2026 && int_size_in_bytes (TYPE) < 8)
2028 /* Minimum alignment for an argument to be passed by callee-copy
2029 reference. We need such arguments to be aligned to 8 byte
2030 boundaries, because they'll be loaded using quad loads. */
2031 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2033 /* The SH5 ABI requires floating-point arguments to be passed to
2034 functions without a prototype in both an FP register and a regular
2035 register or the stack. When passing the argument in both FP and
2036 general-purpose registers, list the FP register first. */
2037 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2043 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2044 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2045 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2050 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2051 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2052 + (CUM).arg_count[(int) SH_ARG_INT]) \
2053 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2054 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2057 /* The SH5 ABI requires regular registers or stack slots to be
2058 reserved for floating-point arguments. Registers are taken care of
2059 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2060 Unfortunately, there's no way to just reserve a stack slot, so
2061 we'll end up needlessly storing a copy of the argument in the
2062 stack. For incoming arguments, however, the PARALLEL will be
2063 optimized to the register-only form, and the value in the stack
2064 slot won't be used at all. */
2065 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2066 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2067 ? gen_rtx_REG ((MODE), (REG)) \
2068 : gen_rtx_PARALLEL ((MODE), \
2071 (VOIDmode, NULL_RTX, \
2074 (VOIDmode, gen_rtx_REG ((MODE), \
2078 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2080 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2081 || (MODE) == DCmode) \
2082 && ((CUM).arg_count[(int) SH_ARG_INT] \
2083 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2085 /* Perform any needed actions needed for a function that is receiving a
2086 variable number of arguments. */
2088 /* Implement `va_start' for varargs and stdarg. */
2089 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2090 sh_va_start (valist, nextarg)
2092 /* Call the function profiler with a given profile label.
2093 We use two .aligns, so as to make sure that both the .long is aligned
2094 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2095 from the trapa instruction. */
2097 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2099 if (TARGET_SHMEDIA) \
2101 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2102 fprintf((STREAM), "\ttrapa\tr0\n"); \
2103 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2107 fprintf((STREAM), "\t.align\t2\n"); \
2108 fprintf((STREAM), "\ttrapa\t#33\n"); \
2109 fprintf((STREAM), "\t.align\t2\n"); \
2110 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2114 /* Define this macro if the code for function profiling should come
2115 before the function prologue. Normally, the profiling code comes
2118 #define PROFILE_BEFORE_PROLOGUE
2120 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2121 the stack pointer does not matter. The value is tested only in
2122 functions that have frame pointers.
2123 No definition is equivalent to always zero. */
2125 #define EXIT_IGNORE_STACK 1
2128 On the SH, the trampoline looks like
2129 2 0002 D202 mov.l l2,r2
2130 1 0000 D301 mov.l l1,r3
2133 5 0008 00000000 l1: .long area
2134 6 000c 00000000 l2: .long function */
2136 /* Length in units of the trampoline for entering a nested function. */
2137 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2139 /* Alignment required for a trampoline in bits . */
2140 #define TRAMPOLINE_ALIGNMENT \
2141 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2142 : TARGET_SHMEDIA ? 256 : 64)
2144 /* Emit RTL insns to initialize the variable parts of a trampoline.
2145 FNADDR is an RTX for the address of the function's pure code.
2146 CXT is an RTX for the static chain value for the function. */
2148 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2149 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2151 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2153 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2155 if (TARGET_SHMEDIA) \
2156 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2157 gen_reg_rtx (Pmode), 0, \
2161 /* A C expression whose value is RTL representing the value of the return
2162 address for the frame COUNT steps up from the current frame.
2163 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2164 can ignore COUNT. */
2166 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2167 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2169 /* A C expression whose value is RTL representing the location of the
2170 incoming return address at the beginning of any function, before the
2171 prologue. This RTL is either a REG, indicating that the return
2172 value is saved in REG, or a MEM representing a location in
2174 #define INCOMING_RETURN_ADDR_RTX \
2175 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2177 /* Addressing modes, and classification of registers for them. */
2178 #define HAVE_POST_INCREMENT TARGET_SH1
2179 #define HAVE_PRE_DECREMENT TARGET_SH1
2181 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2183 #define USE_LOAD_PRE_DECREMENT(mode) 0
2184 #define USE_STORE_POST_INCREMENT(mode) 0
2185 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2188 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2189 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2190 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2192 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2193 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2194 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2196 /* Macros to check register numbers against specific register classes. */
2198 /* These assume that REGNO is a hard or pseudo reg number.
2199 They give nonzero only if REGNO is a hard reg of the suitable class
2200 or a pseudo reg currently allocated to a suitable hard reg.
2201 Since they use reg_renumber, they are safe only once reg_renumber
2202 has been allocated, which happens in local-alloc.c. */
2204 #define REGNO_OK_FOR_BASE_P(REGNO) \
2205 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2206 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2207 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2209 ? (GENERAL_REGISTER_P (REGNO) \
2210 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2211 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2213 /* Maximum number of registers that can appear in a valid memory
2216 #define MAX_REGS_PER_ADDRESS 2
2218 /* Recognize any constant value that is a valid address. */
2220 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2222 /* Nonzero if the constant value X is a legitimate general operand. */
2224 #define LEGITIMATE_CONSTANT_P(X) \
2226 ? ((GET_MODE (X) != DFmode \
2227 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2228 || (X) == CONST0_RTX (GET_MODE (X)) \
2229 || ! TARGET_SHMEDIA_FPU \
2230 || TARGET_SHMEDIA64) \
2231 : (GET_CODE (X) != CONST_DOUBLE \
2232 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2233 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2235 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2236 and check its validity for a certain class.
2237 We have two alternate definitions for each of them.
2238 The usual definition accepts all pseudo regs; the other rejects
2239 them unless they have been allocated suitable hard regs.
2240 The symbol REG_OK_STRICT causes the latter definition to be used. */
2242 #ifndef REG_OK_STRICT
2244 /* Nonzero if X is a hard reg that can be used as a base reg
2245 or if it is a pseudo reg. */
2246 #define REG_OK_FOR_BASE_P(X) \
2247 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2249 /* Nonzero if X is a hard reg that can be used as an index
2250 or if it is a pseudo reg. */
2251 #define REG_OK_FOR_INDEX_P(X) \
2252 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2253 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2255 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2256 or if X is a pseudo reg. */
2257 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2258 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2259 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2263 /* Nonzero if X is a hard reg that can be used as a base reg. */
2264 #define REG_OK_FOR_BASE_P(X) \
2265 REGNO_OK_FOR_BASE_P (REGNO (X))
2267 /* Nonzero if X is a hard reg that can be used as an index. */
2268 #define REG_OK_FOR_INDEX_P(X) \
2269 REGNO_OK_FOR_INDEX_P (REGNO (X))
2271 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2272 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2273 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2277 /* The 'Q' constraint is a pc relative load operand. */
2278 #define EXTRA_CONSTRAINT_Q(OP) \
2279 (GET_CODE (OP) == MEM \
2280 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2281 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2282 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2283 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2284 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2286 /* Extra address constraints. */
2287 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2289 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2290 operand is not SCRATCH (i.e. REG) then R0 is probably being
2291 used, hence mova is being used, hence do not select this pattern */
2292 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2293 #define EXTRA_CONSTRAINT_B(OP, STR) \
2294 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2297 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2298 #define EXTRA_CONSTRAINT_C16(OP) \
2299 (GET_CODE (OP) == CONST \
2300 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2301 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2302 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2303 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2304 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2305 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2306 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2307 && (MOVI_SHORI_BASE_OPERAND_P \
2308 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2309 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2312 /* Check whether OP is a datalabel unspec. */
2313 #define DATALABEL_REF_NO_CONST_P(OP) \
2314 (GET_CODE (OP) == UNSPEC \
2315 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2316 && XVECLEN ((OP), 0) == 1 \
2317 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2319 #define GOT_ENTRY_P(OP) \
2320 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2321 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2323 #define GOTPLT_ENTRY_P(OP) \
2324 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2325 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2327 #define UNSPEC_GOTOFF_P(OP) \
2328 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2330 #define GOTOFF_P(OP) \
2331 (GET_CODE (OP) == CONST \
2332 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2333 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2334 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2335 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2337 #define PIC_ADDR_P(OP) \
2338 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2339 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2341 #define PIC_OFFSET_P(OP) \
2343 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2344 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2346 #define PIC_DIRECT_ADDR_P(OP) \
2347 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2349 #define NON_PIC_REFERENCE_P(OP) \
2350 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2351 || (GET_CODE (OP) == CONST \
2352 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2353 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2354 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2355 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2356 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2357 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2358 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2359 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2361 #define PIC_REFERENCE_P(OP) \
2362 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2363 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2365 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2367 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2368 || PIC_OFFSET_P (OP)) \
2369 : NON_PIC_REFERENCE_P (OP))
2371 /* The `Csy' constraint is a label or a symbol. */
2372 #define EXTRA_CONSTRAINT_Csy(OP) \
2373 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2375 /* A zero in any shape or form. */
2376 #define EXTRA_CONSTRAINT_Z(OP) \
2377 ((OP) == CONST0_RTX (GET_MODE (OP)))
2379 /* Any vector constant we can handle. */
2380 #define EXTRA_CONSTRAINT_W(OP) \
2381 (GET_CODE (OP) == CONST_VECTOR \
2382 && (sh_rep_vec ((OP), VOIDmode) \
2383 || (HOST_BITS_PER_WIDE_INT >= 64 \
2384 ? sh_const_vec ((OP), VOIDmode) \
2385 : sh_1el_vec ((OP), VOIDmode))))
2387 /* A non-explicit constant that can be loaded directly into a general purpose
2388 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2389 #define EXTRA_CONSTRAINT_Cpg(OP) \
2391 && GET_CODE (OP) != CONST_INT \
2392 && GET_CODE (OP) != CONST_DOUBLE \
2394 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2395 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2396 && GET_CODE (OP) != LABEL_REF)))
2397 #define EXTRA_CONSTRAINT_C(OP, STR) \
2398 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2399 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2400 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2403 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2404 #define EXTRA_CONSTRAINT_Sr0(OP) \
2405 (memory_operand((OP), GET_MODE (OP)) \
2406 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2407 #define EXTRA_CONSTRAINT_Sua(OP) \
2408 (memory_operand((OP), GET_MODE (OP)) \
2409 && GET_CODE (XEXP (OP, 0)) != PLUS)
2410 #define EXTRA_CONSTRAINT_S(OP, STR) \
2411 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2412 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2415 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2416 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2417 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2418 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2419 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2420 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2421 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2422 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2425 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2426 that is a valid memory address for an instruction.
2427 The MODE argument is the machine mode for the MEM expression
2428 that wants to use this address. */
2430 #define MODE_DISP_OK_4(X,MODE) \
2431 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2432 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2434 #define MODE_DISP_OK_8(X,MODE) \
2435 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2436 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2438 #undef MODE_DISP_OK_4
2439 #define MODE_DISP_OK_4(X,MODE) \
2440 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2441 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2442 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2443 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2445 #undef MODE_DISP_OK_8
2446 #define MODE_DISP_OK_8(X,MODE) \
2447 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2448 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2449 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2450 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2452 #define BASE_REGISTER_RTX_P(X) \
2453 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2454 || (GET_CODE (X) == SUBREG \
2455 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2456 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2457 && GET_CODE (SUBREG_REG (X)) == REG \
2458 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2460 /* Since this must be r0, which is a single register class, we must check
2461 SUBREGs more carefully, to be sure that we don't accept one that extends
2462 outside the class. */
2463 #define INDEX_REGISTER_RTX_P(X) \
2464 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2465 || (GET_CODE (X) == SUBREG \
2466 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2467 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2468 && GET_CODE (SUBREG_REG (X)) == REG \
2469 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2471 /* Jump to LABEL if X is a valid address RTX. This must also take
2472 REG_OK_STRICT into account when deciding about valid registers, but it uses
2473 the above macros so we are in luck.
2481 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2482 into the FRx registers. We implement this by setting the maximum offset
2483 to zero when the value is SFmode. This also restricts loading of SFmode
2484 values into the integer registers, but that can't be helped. */
2486 /* The SH allows a displacement in a QI or HI amode, but only when the
2487 other operand is R0. GCC doesn't handle this very well, so we forgo
2490 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2491 DI can be any number 0..60. */
2493 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2495 if (GET_CODE (OP) == CONST_INT) \
2497 if (TARGET_SHMEDIA) \
2500 /* Check if this the address of an unaligned load / store. */\
2501 if ((MODE) == VOIDmode) \
2503 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2507 MODE_SIZE = GET_MODE_SIZE (MODE); \
2508 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2509 && INTVAL (OP) >= -512 * MODE_SIZE \
2510 && INTVAL (OP) < 512 * MODE_SIZE) \
2515 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2516 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2520 #define ALLOW_INDEXED_ADDRESS \
2521 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2523 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2525 if (BASE_REGISTER_RTX_P (X)) \
2527 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2528 && ! TARGET_SHMEDIA \
2529 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2531 else if (GET_CODE (X) == PLUS \
2532 && ((MODE) != PSImode || reload_completed)) \
2534 rtx xop0 = XEXP ((X), 0); \
2535 rtx xop1 = XEXP ((X), 1); \
2536 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2537 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2538 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2539 || ((xop0 == stack_pointer_rtx \
2540 || xop0 == hard_frame_pointer_rtx) \
2541 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2542 || ((xop1 == stack_pointer_rtx \
2543 || xop1 == hard_frame_pointer_rtx) \
2544 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2545 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2546 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2547 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2548 && TARGET_FMOVD && MODE == DFmode))) \
2550 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2552 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2558 /* Try machine-dependent ways of modifying an illegitimate address
2559 to be legitimate. If we find one, return the new, valid address.
2560 This macro is used in only one place: `memory_address' in explow.c.
2562 OLDX is the address as it was before break_out_memory_refs was called.
2563 In some cases it is useful to look at this to decide what needs to be done.
2565 MODE and WIN are passed so that this macro can use
2566 GO_IF_LEGITIMATE_ADDRESS.
2568 It is always safe for this macro to do nothing. It exists to recognize
2569 opportunities to optimize the output.
2571 For the SH, if X is almost suitable for indexing, but the offset is
2572 out of range, convert it into a normal form so that cse has a chance
2573 of reducing the number of address registers used. */
2575 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2578 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2579 if (GET_CODE (X) == PLUS \
2580 && (GET_MODE_SIZE (MODE) == 4 \
2581 || GET_MODE_SIZE (MODE) == 8) \
2582 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2583 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2584 && ! TARGET_SHMEDIA \
2585 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2586 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2588 rtx index_rtx = XEXP ((X), 1); \
2589 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2592 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2593 /* On rare occasions, we might get an unaligned pointer \
2594 that is indexed in a way to give an aligned address. \
2595 Therefore, keep the lower two bits in offset_base. */ \
2596 /* Instead of offset_base 128..131 use 124..127, so that \
2597 simple add suffices. */ \
2600 offset_base = ((offset + 4) & ~60) - 4; \
2603 offset_base = offset & ~60; \
2604 /* Sometimes the normal form does not suit DImode. We \
2605 could avoid that by using smaller ranges, but that \
2606 would give less optimized code when SImode is \
2608 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2610 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2611 GEN_INT (offset_base), NULL_RTX, 0, \
2614 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2620 /* A C compound statement that attempts to replace X, which is an address
2621 that needs reloading, with a valid memory address for an operand of
2622 mode MODE. WIN is a C statement label elsewhere in the code.
2624 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2625 of the address. That will allow inheritance of the address reloads. */
2627 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2629 if (GET_CODE (X) == PLUS \
2630 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2631 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2632 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2633 && ! TARGET_SHMEDIA \
2634 && ! (TARGET_SH4 && (MODE) == DFmode) \
2635 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2636 && (ALLOW_INDEXED_ADDRESS \
2637 || XEXP ((X), 0) == stack_pointer_rtx \
2638 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2640 rtx index_rtx = XEXP (X, 1); \
2641 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2644 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2646 push_reload (X, NULL_RTX, &X, NULL, \
2647 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2651 if (TARGET_SH2E && MODE == SFmode) \
2654 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2655 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2659 /* Instead of offset_base 128..131 use 124..127, so that \
2660 simple add suffices. */ \
2663 offset_base = ((offset + 4) & ~60) - 4; \
2666 offset_base = offset & ~60; \
2667 /* Sometimes the normal form does not suit DImode. We \
2668 could avoid that by using smaller ranges, but that \
2669 would give less optimized code when SImode is \
2671 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2673 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2674 GEN_INT (offset_base)); \
2675 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2676 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2677 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2682 /* We must re-recognize what we created before. */ \
2683 else if (GET_CODE (X) == PLUS \
2684 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2685 && GET_CODE (XEXP (X, 0)) == PLUS \
2686 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2687 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2688 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2689 && ! TARGET_SHMEDIA \
2690 && ! (TARGET_SH2E && MODE == SFmode)) \
2692 /* Because this address is so complex, we know it must have \
2693 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2694 it is already unshared, and needs no further unsharing. */ \
2695 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2696 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2701 /* Go to LABEL if ADDR (a legitimate address expression)
2702 has an effect that depends on the machine mode it is used for.
2704 ??? Strictly speaking, we should also include all indexed addressing,
2705 because the index scale factor is the length of the operand.
2706 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2707 high if we did that. So we rely on reload to fix things up. */
2709 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2711 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2715 /* Specify the machine mode that this machine uses
2716 for the index in the tablejump instruction. */
2717 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2719 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2720 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2721 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2722 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2723 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2724 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2727 /* Define as C expression which evaluates to nonzero if the tablejump
2728 instruction expects the table to contain offsets from the address of the
2730 Do not define this if the table should contain absolute addresses. */
2731 #define CASE_VECTOR_PC_RELATIVE 1
2733 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2734 #define FLOAT_TYPE_SIZE 32
2736 /* Since the SH2e has only `float' support, it is desirable to make all
2737 floating point types equivalent to `float'. */
2738 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2740 /* 'char' is signed by default. */
2741 #define DEFAULT_SIGNED_CHAR 1
2743 /* The type of size_t unsigned int. */
2744 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2747 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2749 #define WCHAR_TYPE "short unsigned int"
2750 #define WCHAR_TYPE_SIZE 16
2752 #define SH_ELF_WCHAR_TYPE "long int"
2754 /* Max number of bytes we can move from memory to memory
2755 in one reasonably fast instruction. */
2756 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2758 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2759 MOVE_MAX is not a compile-time constant. */
2760 #define MAX_MOVE_MAX 8
2762 /* Max number of bytes we want move_by_pieces to be able to copy
2764 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2766 /* Define if operations between registers always perform the operation
2767 on the full register even if a narrower mode is specified. */
2768 #define WORD_REGISTER_OPERATIONS
2770 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2771 will either zero-extend or sign-extend. The value of this macro should
2772 be the code that says which one of the two operations is implicitly
2773 done, UNKNOWN if none. */
2774 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2775 /* FP registers can load SImode values, but don't implicitly sign-extend
2777 #define LOAD_EXTEND_OP(MODE) \
2778 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2779 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2781 /* Define if loading short immediate values into registers sign extends. */
2782 #define SHORT_IMMEDIATES_SIGN_EXTEND
2784 /* Nonzero if access to memory by bytes is no faster than for words. */
2785 #define SLOW_BYTE_ACCESS 1
2787 /* Immediate shift counts are truncated by the output routines (or was it
2788 the assembler?). Shift counts in a register are truncated by SH. Note
2789 that the native compiler puts too large (> 32) immediate shift counts
2790 into a register and shifts by the register, letting the SH decide what
2791 to do instead of doing that itself. */
2792 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2793 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2794 expects - the sign bit is significant - so it appears that we need to
2795 leave this zero for correct SH3 code. */
2796 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2798 /* All integers have the same format so truncation is easy. */
2799 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2800 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2801 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2803 /* Define this if addresses of constant functions
2804 shouldn't be put through pseudo regs where they can be cse'd.
2805 Desirable on machines where ordinary constants are expensive
2806 but a CALL with constant address is cheap. */
2807 /*#define NO_FUNCTION_CSE 1*/
2809 /* The machine modes of pointers and functions. */
2810 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2811 #define FUNCTION_MODE Pmode
2813 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2814 are actually function calls with some special constraints on arguments
2817 These macros tell reorg that the references to arguments and
2818 register clobbers for insns of type sfunc do not appear to happen
2819 until after the millicode call. This allows reorg to put insns
2820 which set the argument registers into the delay slot of the millicode
2821 call -- thus they act more like traditional CALL_INSNs.
2823 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2824 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2827 #define INSN_SETS_ARE_DELAYED(X) \
2828 ((GET_CODE (X) == INSN \
2829 && GET_CODE (PATTERN (X)) != SEQUENCE \
2830 && GET_CODE (PATTERN (X)) != USE \
2831 && GET_CODE (PATTERN (X)) != CLOBBER \
2832 && get_attr_is_sfunc (X)))
2834 #define INSN_REFERENCES_ARE_DELAYED(X) \
2835 ((GET_CODE (X) == INSN \
2836 && GET_CODE (PATTERN (X)) != SEQUENCE \
2837 && GET_CODE (PATTERN (X)) != USE \
2838 && GET_CODE (PATTERN (X)) != CLOBBER \
2839 && get_attr_is_sfunc (X)))
2842 /* Position Independent Code. */
2844 /* We can't directly access anything that contains a symbol,
2845 nor can we indirect via the constant pool. */
2846 #define LEGITIMATE_PIC_OPERAND_P(X) \
2847 ((! nonpic_symbol_mentioned_p (X) \
2848 && (GET_CODE (X) != SYMBOL_REF \
2849 || ! CONSTANT_POOL_ADDRESS_P (X) \
2850 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2851 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2853 #define SYMBOLIC_CONST_P(X) \
2854 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2855 && nonpic_symbol_mentioned_p (X))
2857 /* Compute extra cost of moving data between one register class
2860 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2861 uses this information. Hence, the general register <-> floating point
2862 register information here is not used for SFmode. */
2864 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2865 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2866 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2868 #define REGCLASS_HAS_FP_REG(CLASS) \
2869 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2870 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2872 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2873 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2875 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2876 would be so that people with slow memory systems could generate
2877 different code that does fewer memory accesses. */
2879 /* A C expression for the cost of a branch instruction. A value of 1
2880 is the default; other values are interpreted relative to that.
2881 The SH1 does not have delay slots, hence we get a pipeline stall
2882 at every branch. The SH4 is superscalar, so the single delay slot
2883 is not sufficient to keep both pipelines filled. */
2884 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2886 /* Assembler output control. */
2888 /* A C string constant describing how to begin a comment in the target
2889 assembler language. The compiler assumes that the comment will end at
2890 the end of the line. */
2891 #define ASM_COMMENT_START "!"
2893 #define ASM_APP_ON ""
2894 #define ASM_APP_OFF ""
2895 #define FILE_ASM_OP "\t.file\n"
2896 #define SET_ASM_OP "\t.set\t"
2898 /* How to change between sections. */
2900 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2901 #define DATA_SECTION_ASM_OP "\t.data"
2903 #if defined CRT_BEGIN || defined CRT_END
2904 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2905 # undef TEXT_SECTION_ASM_OP
2906 # if __SHMEDIA__ == 1 && __SH5__ == 32
2907 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2909 # define TEXT_SECTION_ASM_OP "\t.text"
2914 /* If defined, a C expression whose value is a string containing the
2915 assembler operation to identify the following data as
2916 uninitialized global data. If not defined, and neither
2917 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2918 uninitialized global data will be output in the data section if
2919 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2921 #ifndef BSS_SECTION_ASM_OP
2922 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2925 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2926 separate, explicit argument. If you define this macro, it is used
2927 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2928 handling the required alignment of the variable. The alignment is
2929 specified as the number of bits.
2931 Try to use function `asm_output_aligned_bss' defined in file
2932 `varasm.c' when defining this macro. */
2933 #ifndef ASM_OUTPUT_ALIGNED_BSS
2934 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2935 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2938 /* Define this so that jump tables go in same section as the current function,
2939 which could be text or it could be a user defined section. */
2940 #define JUMP_TABLES_IN_TEXT_SECTION 1
2942 #undef DO_GLOBAL_CTORS_BODY
2943 #define DO_GLOBAL_CTORS_BODY \
2945 typedef (*pfunc)(); \
2946 extern pfunc __ctors[]; \
2947 extern pfunc __ctors_end[]; \
2949 for (p = __ctors_end; p > __ctors; ) \
2955 #undef DO_GLOBAL_DTORS_BODY
2956 #define DO_GLOBAL_DTORS_BODY \
2958 typedef (*pfunc)(); \
2959 extern pfunc __dtors[]; \
2960 extern pfunc __dtors_end[]; \
2962 for (p = __dtors; p < __dtors_end; p++) \
2968 #define ASM_OUTPUT_REG_PUSH(file, v) \
2970 if (TARGET_SHMEDIA) \
2972 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2973 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2976 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2979 #define ASM_OUTPUT_REG_POP(file, v) \
2981 if (TARGET_SHMEDIA) \
2983 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2984 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2987 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2990 /* DBX register number for a given compiler register number. */
2991 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2993 /* svr4.h undefines this macro, yet we really want to use the same numbers
2994 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2995 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2996 register exists, so we should return -1 for invalid register numbers. */
2997 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2999 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3000 used to use the encodings 245..260, but that doesn't make sense:
3001 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3002 the FP registers stay the same when switching between compact and media
3003 mode. Hence, we also need to use the same dwarf frame columns.
3004 Likewise, we need to support unwind information for SHmedia registers
3005 even in compact code. */
3006 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3007 (IN_RANGE ((REGNO), \
3008 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3009 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3010 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3011 : ((int) (REGNO) >= FIRST_FP_REG \
3013 <= (FIRST_FP_REG + \
3014 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3015 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3016 + (TARGET_SH5 ? 77 : 25)) \
3017 : XD_REGISTER_P (REGNO) \
3018 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3019 : TARGET_REGISTER_P (REGNO) \
3020 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3021 : (REGNO) == PR_REG \
3022 ? (TARGET_SH5 ? 18 : 17) \
3023 : (REGNO) == PR_MEDIA_REG \
3024 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3025 : (REGNO) == T_REG \
3026 ? (TARGET_SH5 ? 242 : 18) \
3027 : (REGNO) == GBR_REG \
3028 ? (TARGET_SH5 ? 238 : 19) \
3029 : (REGNO) == MACH_REG \
3030 ? (TARGET_SH5 ? 239 : 20) \
3031 : (REGNO) == MACL_REG \
3032 ? (TARGET_SH5 ? 240 : 21) \
3033 : (REGNO) == FPUL_REG \
3034 ? (TARGET_SH5 ? 244 : 23) \
3037 /* This is how to output a reference to a symbol_ref. On SH5,
3038 references to non-code symbols must be preceded by `datalabel'. */
3039 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3042 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3043 fputs ("datalabel ", (FILE)); \
3044 assemble_name ((FILE), XSTR ((SYM), 0)); \
3048 /* This is how to output an assembler line
3049 that says to advance the location counter
3050 to a multiple of 2**LOG bytes. */
3052 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3054 fprintf ((FILE), "\t.align %d\n", (LOG))
3056 /* Globalizing directive for a label. */
3057 #define GLOBAL_ASM_OP "\t.global\t"
3059 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3061 /* Output a relative address table. */
3063 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3064 switch (GET_MODE (BODY)) \
3069 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3073 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3078 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3082 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3087 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3091 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3097 /* Output an absolute table element. */
3099 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3100 if (! optimize || TARGET_BIGTABLE) \
3101 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3103 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3106 /* A C statement to be executed just prior to the output of
3107 assembler code for INSN, to modify the extracted operands so
3108 they will be output differently.
3110 Here the argument OPVEC is the vector containing the operands
3111 extracted from INSN, and NOPERANDS is the number of elements of
3112 the vector which contain meaningful data for this insn.
3113 The contents of this vector are what will be used to convert the insn
3114 template into assembler code, so you can change the assembler output
3115 by changing the contents of the vector. */
3117 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3118 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3120 /* Print operand X (an rtx) in assembler syntax to file FILE.
3121 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3122 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3124 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3126 /* Print a memory address as an operand to reference that memory location. */
3128 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3130 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3131 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3132 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3134 /* Recognize machine-specific patterns that may appear within
3135 constants. Used for PIC-specific UNSPECs. */
3136 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3138 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3140 switch (XINT ((X), 1)) \
3142 case UNSPEC_DATALABEL: \
3143 fputs ("datalabel ", (STREAM)); \
3144 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3147 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3148 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3151 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3152 fputs ("@GOT", (STREAM)); \
3154 case UNSPEC_GOTOFF: \
3155 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3156 fputs ("@GOTOFF", (STREAM)); \
3159 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3160 fputs ("@PLT", (STREAM)); \
3162 case UNSPEC_GOTPLT: \
3163 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3164 fputs ("@GOTPLT", (STREAM)); \
3166 case UNSPEC_DTPOFF: \
3167 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3168 fputs ("@DTPOFF", (STREAM)); \
3170 case UNSPEC_GOTTPOFF: \
3171 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3172 fputs ("@GOTTPOFF", (STREAM)); \
3174 case UNSPEC_TPOFF: \
3175 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3176 fputs ("@TPOFF", (STREAM)); \
3178 case UNSPEC_CALLER: \
3181 /* LPCS stands for Label for PIC Call Site. */ \
3182 ASM_GENERATE_INTERNAL_LABEL \
3183 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3184 assemble_name ((STREAM), name); \
3197 extern struct rtx_def *sh_compare_op0;
3198 extern struct rtx_def *sh_compare_op1;
3200 /* Which processor to schedule for. The elements of the enumeration must
3201 match exactly the cpu attribute in the sh.md file. */
3203 enum processor_type {
3215 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3216 extern enum processor_type sh_cpu;
3218 extern int optimize; /* needed for gen_casesi. */
3220 enum mdep_reorg_phase_e
3222 SH_BEFORE_MDEP_REORG,
3223 SH_INSERT_USES_LABELS,
3224 SH_SHORTEN_BRANCHES0,
3226 SH_SHORTEN_BRANCHES1,
3230 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3232 /* Handle Renesas compiler's pragmas. */
3233 #define REGISTER_TARGET_PRAGMAS() do { \
3234 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3235 c_register_pragma (0, "trapa", sh_pr_trapa); \
3236 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3239 /* Set when processing a function with pragma interrupt turned on. */
3241 extern int pragma_interrupt;
3243 /* Set when processing a function with interrupt attribute. */
3245 extern int current_function_interrupt;
3247 /* Set to an RTX containing the address of the stack to switch to
3248 for interrupt functions. */
3249 extern struct rtx_def *sp_switch;
3252 /* Instructions with unfilled delay slots take up an
3253 extra two bytes for the nop in the delay slot.
3254 sh-dsp parallel processing insns are four bytes long. */
3256 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3257 (LENGTH) += sh_insn_length_adjustment (X);
3259 /* Define this macro if it is advisable to hold scalars in registers
3260 in a wider mode than that declared by the program. In such cases,
3261 the value is constrained to be within the bounds of the declared
3262 type, but kept valid in the wider mode. The signedness of the
3263 extension may differ from that of the type.
3265 Leaving the unsignedp unchanged gives better code than always setting it
3266 to 0. This is despite the fact that we have only signed char and short
3267 load instructions. */
3268 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3269 if (GET_MODE_CLASS (MODE) == MODE_INT \
3270 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3271 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3272 (MODE) = (TARGET_SH1 ? SImode \
3273 : TARGET_SHMEDIA32 ? SImode : DImode);
3275 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3277 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3279 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3280 and popping arguments. However, we do have push/pop instructions, and
3281 rather limited offsets (4 bits) in load/store instructions, so it isn't
3282 clear if this would give better code. If implemented, should check for
3283 compatibility problems. */
3285 #define SH_DYNAMIC_SHIFT_COST \
3286 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3289 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3291 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3293 #define ACTUAL_NORMAL_MODE(ENTITY) \
3294 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3296 #define NORMAL_MODE(ENTITY) \
3297 (sh_cfun_interrupt_handler_p () \
3298 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3299 : ACTUAL_NORMAL_MODE (ENTITY))
3301 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3303 #define MODE_EXIT(ENTITY) \
3304 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3306 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3307 && (REGNO) == FPSCR_REG)
3309 #define MODE_NEEDED(ENTITY, INSN) \
3310 (recog_memoized (INSN) >= 0 \
3311 ? get_attr_fp_mode (INSN) \
3314 #define MODE_AFTER(MODE, INSN) \
3316 && recog_memoized (INSN) >= 0 \
3317 && get_attr_fp_set (INSN) != FP_SET_NONE \
3318 ? (int) get_attr_fp_set (INSN) \
3321 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3322 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3324 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3325 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3327 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3328 sh_can_redirect_branch ((INSN), (SEQ))
3330 #define DWARF_FRAME_RETURN_COLUMN \
3331 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3333 #define EH_RETURN_DATA_REGNO(N) \
3334 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3336 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3337 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3339 /* We have to distinguish between code and data, so that we apply
3340 datalabel where and only where appropriate. Use sdataN for data. */
3341 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3342 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3343 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3344 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3346 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3347 indirect are handled automatically. */
3348 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3350 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3351 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3353 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3354 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3359 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3360 /* SH constant pool breaks the devices in crtstuff.c to control section
3361 in where code resides. We have to write it as asm code. */
3362 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3363 asm (SECTION_OP "\n\
3369 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3370 2:\n" TEXT_SECTION_ASM_OP);
3371 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3373 #define SIMULTANEOUS_PREFETCHES 2
3375 /* FIXME: middle-end support for highpart optimizations is missing. */
3376 #define high_life_started reload_in_progress
3378 #endif /* ! GCC_SH_H */
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