1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
27 #include "config/vxworks-dummy.h"
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
37 #define TARGET_CPU_CPP_BUILTINS() \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
45 builtin_define ("__sh1__"); \
48 builtin_define ("__sh2__"); \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
94 builtin_define ("__HITACHI__"); \
95 builtin_define (TARGET_LITTLE_ENDIAN \
96 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
99 /* We can not debug without a frame pointer. */
100 /* #define CAN_DEBUG_WITHOUT_FP */
102 #define CONDITIONAL_REGISTER_USAGE do \
105 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
106 if (! VALID_REGISTER_P (regno)) \
107 fixed_regs[regno] = call_used_regs[regno] = 1; \
108 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
111 call_used_regs[FIRST_GENERAL_REG + 8] \
112 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
113 call_really_used_regs[FIRST_GENERAL_REG + 8] \
114 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
116 if (TARGET_SHMEDIA) \
118 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
119 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
120 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
124 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
127 /* Renesas saves and restores mac registers on call. */ \
128 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
130 call_really_used_regs[MACH_REG] = 0; \
131 call_really_used_regs[MACL_REG] = 0; \
133 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
134 regno <= LAST_FP_REG; regno += 2) \
135 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
136 if (TARGET_SHMEDIA) \
138 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
139 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
140 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
143 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
144 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
145 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
148 /* Nonzero if this is an ELF target - compile time only */
151 /* Nonzero if we should generate code using type 2E insns. */
152 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
154 /* Nonzero if we should generate code using type 2A insns. */
155 #define TARGET_SH2A TARGET_HARD_SH2A
156 /* Nonzero if we should generate code using type 2A SF insns. */
157 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
158 /* Nonzero if we should generate code using type 2A DF insns. */
159 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
161 /* Nonzero if we should generate code using type 3E insns. */
162 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
164 /* Nonzero if the cache line size is 32. */
165 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
167 /* Nonzero if we schedule for a superscalar implementation. */
168 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
170 /* Nonzero if the target has separate instruction and data caches. */
171 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
173 /* Nonzero if a double-precision FPU is available. */
174 #define TARGET_FPU_DOUBLE \
175 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
177 /* Nonzero if an FPU is available. */
178 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
180 /* Nonzero if we should generate code using type 4 insns. */
182 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
184 /* Nonzero if we're generating code for the common subset of
185 instructions present on both SH4a and SH4al-dsp. */
186 #define TARGET_SH4A_ARCH TARGET_SH4A
188 /* Nonzero if we're generating code for SH4a, unless the use of the
189 FPU is disabled (which makes it compatible with SH4al-dsp). */
190 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
192 /* Nonzero if we should generate code using the SHcompact instruction
193 set and 32-bit ABI. */
194 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
196 /* Nonzero if we should generate code using the SHmedia instruction
198 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
200 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
202 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
204 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
206 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
208 /* Nonzero if we should generate code using SHmedia FPU instructions. */
209 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
211 /* This is not used by the SH2E calling convention */
212 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
213 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
214 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
216 #ifndef TARGET_CPU_DEFAULT
217 #define TARGET_CPU_DEFAULT SELECT_SH1
218 #define SUPPORT_SH1 1
219 #define SUPPORT_SH2E 1
220 #define SUPPORT_SH4 1
221 #define SUPPORT_SH4_SINGLE 1
222 #define SUPPORT_SH2A 1
223 #define SUPPORT_SH2A_SINGLE 1
226 #define TARGET_DIVIDE_INV \
227 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
228 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
229 || sh_div_strategy == SH_DIV_INV_CALL \
230 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
231 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
232 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
233 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
234 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
235 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
236 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
237 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
238 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
239 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
240 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
241 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
243 #define SELECT_SH1 (MASK_SH1)
244 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
245 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
247 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
248 | MASK_HARD_SH2A_DOUBLE \
249 | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
251 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
252 | MASK_SH1 | MASK_FPU_SINGLE)
253 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
254 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
255 | MASK_SH2 | MASK_SH1)
256 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
257 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
258 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
259 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
260 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
262 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
263 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
264 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
265 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
266 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
267 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
268 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
269 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
270 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
271 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
272 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
275 #define SUPPORT_SH2 1
278 #define SUPPORT_SH3 1
279 #define SUPPORT_SH2A_NOFPU 1
282 #define SUPPORT_SH4_NOFPU 1
284 #if SUPPORT_SH4_NOFPU
285 #define SUPPORT_SH4A_NOFPU 1
286 #define SUPPORT_SH4AL 1
290 #define SUPPORT_SH3E 1
291 #define SUPPORT_SH2A_SINGLE_ONLY 1
294 #define SUPPORT_SH4_SINGLE_ONLY 1
296 #if SUPPORT_SH4_SINGLE_ONLY
297 #define SUPPORT_SH4A_SINGLE_ONLY 1
301 #define SUPPORT_SH4A 1
304 #if SUPPORT_SH4_SINGLE
305 #define SUPPORT_SH4A_SINGLE 1
308 #if SUPPORT_SH5_COMPAT
309 #define SUPPORT_SH5_32MEDIA 1
312 #if SUPPORT_SH5_COMPACT_NOFPU
313 #define SUPPORT_SH5_32MEDIA_NOFPU 1
316 #define SUPPORT_ANY_SH5_32MEDIA \
317 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
318 #define SUPPORT_ANY_SH5_64MEDIA \
319 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
320 #define SUPPORT_ANY_SH5 \
321 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
323 /* Reset all target-selection flags. */
324 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
325 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
326 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
328 /* This defaults us to big-endian. */
329 #ifndef TARGET_ENDIAN_DEFAULT
330 #define TARGET_ENDIAN_DEFAULT 0
333 #ifndef TARGET_OPT_DEFAULT
334 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
337 #define TARGET_DEFAULT \
338 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
340 #ifndef SH_MULTILIB_CPU_DEFAULT
341 #define SH_MULTILIB_CPU_DEFAULT "m1"
344 #if TARGET_ENDIAN_DEFAULT
345 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
347 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
350 #define CPP_SPEC " %(subtarget_cpp_spec) "
352 #ifndef SUBTARGET_CPP_SPEC
353 #define SUBTARGET_CPP_SPEC ""
356 #ifndef SUBTARGET_EXTRA_SPECS
357 #define SUBTARGET_EXTRA_SPECS
360 #define EXTRA_SPECS \
361 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
362 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
363 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
364 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
365 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
366 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
367 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
368 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
369 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
370 SUBTARGET_EXTRA_SPECS
372 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
373 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
375 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
378 #define SH_ASM_SPEC \
379 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
380 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
382 %{m2a-single:--isa=sh2a} \
383 %{m2a-single-only:--isa=sh2a} \
384 %{m2a-nofpu:--isa=sh2a-nofpu} \
385 %{m5-compact*:--isa=SHcompact} \
386 %{m5-32media*:--isa=SHmedia --abi=32} \
387 %{m5-64media*:--isa=SHmedia --abi=64} \
388 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
390 #define ASM_SPEC SH_ASM_SPEC
392 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
393 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
394 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
396 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
400 #if STRICT_NOFPU == 1
401 /* Strict nofpu means that the compiler should tell the assembler
402 to reject FPU instructions. E.g. from ASM inserts. */
403 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
404 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
406 /* If there were an -isa option for sh5-nofpu then it would also go here. */
407 #define SUBTARGET_ASM_ISA_SPEC \
408 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
410 #else /* ! STRICT_NOFPU */
411 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
414 #ifndef SUBTARGET_ASM_SPEC
415 #define SUBTARGET_ASM_SPEC ""
418 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
419 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
421 #define LINK_EMUL_PREFIX "sh%{ml:l}"
424 #if TARGET_CPU_DEFAULT & MASK_SH5
425 #if TARGET_CPU_DEFAULT & MASK_SH_E
426 #define LINK_DEFAULT_CPU_EMUL "32"
427 #if TARGET_CPU_DEFAULT & MASK_SH1
428 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
430 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
431 #endif /* MASK_SH1 */
432 #else /* !MASK_SH_E */
433 #define LINK_DEFAULT_CPU_EMUL "64"
434 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
435 #endif /* MASK_SH_E */
436 #define ASM_ISA_DEFAULT_SPEC \
437 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
438 #else /* !MASK_SH5 */
439 #define LINK_DEFAULT_CPU_EMUL ""
440 #define ASM_ISA_DEFAULT_SPEC ""
441 #endif /* MASK_SH5 */
443 #define SUBTARGET_LINK_EMUL_SUFFIX ""
444 #define SUBTARGET_LINK_SPEC ""
446 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
447 so that we can undo the damage without code replication. */
448 #define LINK_SPEC SH_LINK_SPEC
450 #define SH_LINK_SPEC "\
451 -m %(link_emul_prefix)\
452 %{m5-compact*|m5-32media*:32}\
454 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
455 %(subtarget_link_emul_suffix) \
456 %{mrelax:-relax} %(subtarget_link_spec)"
458 #ifndef SH_DIV_STR_FOR_SIZE
459 #define SH_DIV_STR_FOR_SIZE "call"
462 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
463 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
467 flag_omit_frame_pointer = -1; \
469 sh_div_str = "inv:minlat"; \
473 target_flags |= MASK_SMALLCODE; \
474 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
478 TARGET_CBRANCHDI4 = 1; \
479 TARGET_EXPAND_CBRANCHDI4 = 1; \
481 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
482 haven't been parsed yet, hence we'd read only the default. \
483 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
484 it's OK to always set flag_branch_target_load_optimize. */ \
487 flag_branch_target_load_optimize = 1; \
489 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
491 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
492 here, so leave it to OVERRIDE_OPTIONS to set \
493 flag_finite_math_only. We set it to 2 here so we know if the user \
494 explicitly requested this to be on or off. */ \
495 flag_finite_math_only = 2; \
496 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
497 the user explicitly requested this to be on or off. */ \
498 if (flag_schedule_insns > 0) \
499 flag_schedule_insns = 2; \
501 set_param_value ("simultaneous-prefetches", 2); \
504 #define ASSEMBLER_DIALECT assembler_dialect
506 extern int assembler_dialect;
508 enum sh_divide_strategy_e {
509 /* SH5 strategies. */
512 SH_DIV_FP, /* We could do this also for SH4. */
520 /* SH1 .. SH4 strategies. Because of the small number of registers
521 available, the compiler uses knowledge of the actual set of registers
522 being clobbered by the different functions called. */
523 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
524 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
525 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
529 extern enum sh_divide_strategy_e sh_div_strategy;
531 #ifndef SH_DIV_STRATEGY_DEFAULT
532 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
535 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
537 #define OVERRIDE_OPTIONS \
541 SUBTARGET_OVERRIDE_OPTIONS; \
542 if (flag_finite_math_only == 2) \
543 flag_finite_math_only \
544 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
545 if (TARGET_SH2E && !flag_finite_math_only) \
546 target_flags |= MASK_IEEE; \
548 assembler_dialect = 0; \
556 if (TARGET_SH2A_DOUBLE) \
557 target_flags |= MASK_FMOVD; \
565 assembler_dialect = 1; \
568 if (TARGET_SH4A_ARCH) \
570 assembler_dialect = 1; \
576 target_flags |= MASK_ALIGN_DOUBLE; \
577 if (TARGET_SHMEDIA_FPU) \
578 target_flags |= MASK_FMOVD; \
579 if (TARGET_SHMEDIA) \
581 /* There are no delay slots on SHmedia. */ \
582 flag_delayed_branch = 0; \
583 /* Relaxation isn't yet supported for SHmedia */ \
584 target_flags &= ~MASK_RELAX; \
585 /* After reload, if conversion does little good but can cause \
587 - find_if_block doesn't do anything for SH because we don't\
588 have conditional execution patterns. (We use conditional\
589 move patterns, which are handled differently, and only \
591 - find_cond_trap doesn't do anything for the SH because we \
592 don't have conditional traps. \
593 - find_if_case_1 uses redirect_edge_and_branch_force in \
594 the only path that does an optimization, and this causes \
595 an ICE when branch targets are in registers. \
596 - find_if_case_2 doesn't do anything for the SHmedia after \
597 reload except when it can redirect a tablejump - and \
598 that's rather rare. */ \
599 flag_if_conversion2 = 0; \
600 if (! strcmp (sh_div_str, "call")) \
601 sh_div_strategy = SH_DIV_CALL; \
602 else if (! strcmp (sh_div_str, "call2")) \
603 sh_div_strategy = SH_DIV_CALL2; \
604 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
605 sh_div_strategy = SH_DIV_FP; \
606 else if (! strcmp (sh_div_str, "inv")) \
607 sh_div_strategy = SH_DIV_INV; \
608 else if (! strcmp (sh_div_str, "inv:minlat")) \
609 sh_div_strategy = SH_DIV_INV_MINLAT; \
610 else if (! strcmp (sh_div_str, "inv20u")) \
611 sh_div_strategy = SH_DIV_INV20U; \
612 else if (! strcmp (sh_div_str, "inv20l")) \
613 sh_div_strategy = SH_DIV_INV20L; \
614 else if (! strcmp (sh_div_str, "inv:call2")) \
615 sh_div_strategy = SH_DIV_INV_CALL2; \
616 else if (! strcmp (sh_div_str, "inv:call")) \
617 sh_div_strategy = SH_DIV_INV_CALL; \
618 else if (! strcmp (sh_div_str, "inv:fp")) \
620 if (TARGET_FPU_ANY) \
621 sh_div_strategy = SH_DIV_INV_FP; \
623 sh_div_strategy = SH_DIV_INV; \
625 TARGET_CBRANCHDI4 = 0; \
627 /* -fprofile-arcs needs a working libgcov . In unified tree \
628 configurations with newlib, this requires to configure with \
629 --with-newlib --with-headers. But there is no way to check \
630 here we have a working libgcov, so just assume that we have. */\
632 warning (0, "profiling is still experimental for this target");\
636 /* Only the sh64-elf assembler fully supports .quad properly. */\
637 targetm.asm_out.aligned_op.di = NULL; \
638 targetm.asm_out.unaligned_op.di = NULL; \
642 if (! strcmp (sh_div_str, "call-div1")) \
643 sh_div_strategy = SH_DIV_CALL_DIV1; \
644 else if (! strcmp (sh_div_str, "call-fp") \
645 && (TARGET_FPU_DOUBLE \
646 || (TARGET_HARD_SH4 && TARGET_SH2E) \
647 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
648 sh_div_strategy = SH_DIV_CALL_FP; \
649 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
650 sh_div_strategy = SH_DIV_CALL_TABLE; \
652 /* Pick one that makes most sense for the target in general. \
653 It is not much good to use different functions depending \
654 on -Os, since then we'll end up with two different functions \
655 when some of the code is compiled for size, and some for \
658 /* SH4 tends to emphasize speed. */ \
659 if (TARGET_HARD_SH4) \
660 sh_div_strategy = SH_DIV_CALL_TABLE; \
661 /* These have their own way of doing things. */ \
662 else if (TARGET_SH2A) \
663 sh_div_strategy = SH_DIV_INTRINSIC; \
664 /* ??? Should we use the integer SHmedia function instead? */ \
665 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
666 sh_div_strategy = SH_DIV_CALL_FP; \
667 /* SH1 .. SH3 cores often go into small-footprint systems, so \
668 default to the smallest implementation available. */ \
669 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
670 sh_div_strategy = SH_DIV_CALL_TABLE; \
672 sh_div_strategy = SH_DIV_CALL_DIV1; \
675 TARGET_PRETEND_CMOVE = 0; \
676 if (sh_divsi3_libfunc[0]) \
677 ; /* User supplied - leave it alone. */ \
678 else if (TARGET_DIVIDE_CALL_FP) \
679 sh_divsi3_libfunc = "__sdivsi3_i4"; \
680 else if (TARGET_DIVIDE_CALL_TABLE) \
681 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
682 else if (TARGET_SH5) \
683 sh_divsi3_libfunc = "__sdivsi3_1"; \
685 sh_divsi3_libfunc = "__sdivsi3"; \
686 if (sh_branch_cost == -1) \
688 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
690 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
691 if (! VALID_REGISTER_P (regno)) \
692 sh_register_names[regno][0] = '\0'; \
694 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
695 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
696 sh_additional_register_names[regno][0] = '\0'; \
698 if (flag_omit_frame_pointer < 0) \
700 /* The debugging information is sufficient, \
701 but gdb doesn't implement this yet */ \
703 flag_omit_frame_pointer \
704 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
706 flag_omit_frame_pointer = 0; \
709 if ((flag_pic && ! TARGET_PREFERGOT) \
710 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
711 flag_no_function_cse = 1; \
713 if (SMALL_REGISTER_CLASSES) \
715 /* Never run scheduling before reload, since that can \
716 break global alloc, and generates slower code anyway due \
717 to the pressure on R0. */ \
718 /* Enable sched1 for SH4; ready queue will be reordered by \
719 the target hooks when pressure is high. We can not do this for \
720 SH3 and lower as they give spill failures for R0. */ \
721 if (!TARGET_HARD_SH4) \
722 flag_schedule_insns = 0; \
723 /* ??? Current exception handling places basic block boundaries \
724 after call_insns. It causes the high pressure on R0 and gives \
725 spill failures for R0 in reload. See PR 22553 and the thread \
727 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
728 else if (flag_exceptions) \
730 if (flag_schedule_insns == 1) \
731 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
732 flag_schedule_insns = 0; \
736 if (align_loops == 0) \
737 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
738 if (align_jumps == 0) \
739 align_jumps = 1 << CACHE_LOG; \
740 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
741 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
743 /* Allocation boundary (in *bytes*) for the code of a function. \
744 SH1: 32 bit alignment is faster, because instructions are always \
745 fetched as a pair from a longword boundary. \
746 SH2 .. SH5 : align to cache line start. */ \
747 if (align_functions == 0) \
749 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
750 /* The linker relaxation code breaks when a function contains \
751 alignments that are larger than that at the start of a \
752 compilation unit. */ \
756 = align_loops > align_jumps ? align_loops : align_jumps; \
758 /* Also take possible .long constants / mova tables int account. */\
761 if (align_functions < min_align) \
762 align_functions = min_align; \
766 /* Target machine storage layout. */
768 /* Define this if most significant bit is lowest numbered
769 in instructions that operate on numbered bit-fields. */
771 #define BITS_BIG_ENDIAN 0
773 /* Define this if most significant byte of a word is the lowest numbered. */
774 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
776 /* Define this if most significant word of a multiword number is the lowest
778 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
780 /* Define this to set the endianness to use in libgcc2.c, which can
781 not depend on target_flags. */
782 #if defined(__LITTLE_ENDIAN__)
783 #define LIBGCC2_WORDS_BIG_ENDIAN 0
785 #define LIBGCC2_WORDS_BIG_ENDIAN 1
788 #define MAX_BITS_PER_WORD 64
790 /* Width in bits of an `int'. We want just 32-bits, even if words are
792 #define INT_TYPE_SIZE 32
794 /* Width in bits of a `long'. */
795 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
797 /* Width in bits of a `long long'. */
798 #define LONG_LONG_TYPE_SIZE 64
800 /* Width in bits of a `long double'. */
801 #define LONG_DOUBLE_TYPE_SIZE 64
803 /* Width of a word, in units (bytes). */
804 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
805 #define MIN_UNITS_PER_WORD 4
807 /* Scaling factor for Dwarf data offsets for CFI information.
808 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
809 SHmedia; however, since we do partial register saves for the registers
810 visible to SHcompact, and for target registers for SHMEDIA32, we have
811 to allow saves that are only 4-byte aligned. */
812 #define DWARF_CIE_DATA_ALIGNMENT -4
814 /* Width in bits of a pointer.
815 See also the macro `Pmode' defined below. */
816 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
818 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
819 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
821 /* Boundary (in *bits*) on which stack pointer should be aligned. */
822 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
824 /* The log (base 2) of the cache line size, in bytes. Processors prior to
825 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
826 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
827 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
829 /* ABI given & required minimum allocation boundary (in *bits*) for the
830 code of a function. */
831 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
833 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
834 the vbit must go into the delta field of
835 pointers-to-member-functions. */
836 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
837 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
839 /* Alignment of field after `int : 0' in a structure. */
840 #define EMPTY_FIELD_BOUNDARY 32
842 /* No data type wants to be aligned rounder than this. */
843 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
845 /* The best alignment to use in cases where we have a choice. */
846 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
848 /* Make strings word-aligned so strcpy from constants will be faster. */
849 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
850 ((TREE_CODE (EXP) == STRING_CST \
851 && (ALIGN) < FASTEST_ALIGNMENT) \
852 ? FASTEST_ALIGNMENT : (ALIGN))
854 /* get_mode_alignment assumes complex values are always held in multiple
855 registers, but that is not the case on the SH; CQImode and CHImode are
856 held in a single integer register. SH5 also holds CSImode and SCmode
857 values in integer registers. This is relevant for argument passing on
858 SHcompact as we use a stack temp in order to pass CSImode by reference. */
859 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
860 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
861 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
862 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
863 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
865 /* Make arrays of chars word-aligned for the same reasons. */
866 #define DATA_ALIGNMENT(TYPE, ALIGN) \
867 (TREE_CODE (TYPE) == ARRAY_TYPE \
868 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
869 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
871 /* Number of bits which any structure or union's size must be a
872 multiple of. Each structure or union's size is rounded up to a
874 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
876 /* Set this nonzero if move instructions will actually fail to work
877 when given unaligned data. */
878 #define STRICT_ALIGNMENT 1
880 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
881 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
882 barrier_align (LABEL_AFTER_BARRIER)
884 #define LOOP_ALIGN(A_LABEL) \
885 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
886 ? 0 : sh_loop_align (A_LABEL))
888 #define LABEL_ALIGN(A_LABEL) \
890 (PREV_INSN (A_LABEL) \
891 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
892 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
893 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
894 /* explicit alignment insn in constant tables. */ \
895 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
898 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
899 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
901 /* The base two logarithm of the known minimum alignment of an insn length. */
902 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
903 (GET_CODE (A_INSN) == INSN \
904 ? 1 << TARGET_SHMEDIA \
905 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
906 ? 1 << TARGET_SHMEDIA \
909 /* Standard register usage. */
911 /* Register allocation for the Renesas calling convention:
917 r14 frame pointer/call saved
919 ap arg pointer (doesn't really exist, always eliminated)
920 pr subroutine return address
922 mach multiply/accumulate result, high part
923 macl multiply/accumulate result, low part.
924 fpul fp/int communication register
925 rap return address pointer register
927 fr1..fr3 scratch floating point registers
929 fr12..fr15 call saved floating point registers */
931 #define MAX_REGISTER_NAME_LENGTH 5
932 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
934 #define SH_REGISTER_NAMES_INITIALIZER \
936 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
937 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
938 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
939 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
940 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
941 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
942 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
943 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
944 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
945 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
946 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
947 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
948 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
949 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
950 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
951 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
952 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
953 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
954 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
958 #define REGNAMES_ARR_INDEX_1(index) \
959 (sh_register_names[index])
960 #define REGNAMES_ARR_INDEX_2(index) \
961 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
962 #define REGNAMES_ARR_INDEX_4(index) \
963 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
964 #define REGNAMES_ARR_INDEX_8(index) \
965 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
966 #define REGNAMES_ARR_INDEX_16(index) \
967 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
968 #define REGNAMES_ARR_INDEX_32(index) \
969 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
970 #define REGNAMES_ARR_INDEX_64(index) \
971 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
973 #define REGISTER_NAMES \
975 REGNAMES_ARR_INDEX_64 (0), \
976 REGNAMES_ARR_INDEX_64 (64), \
977 REGNAMES_ARR_INDEX_8 (128), \
978 REGNAMES_ARR_INDEX_8 (136), \
979 REGNAMES_ARR_INDEX_8 (144), \
980 REGNAMES_ARR_INDEX_2 (152) \
983 #define ADDREGNAMES_SIZE 32
984 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
985 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
986 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
988 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
990 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
991 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
992 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
993 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
996 #define ADDREGNAMES_REGNO(index) \
997 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1000 #define ADDREGNAMES_ARR_INDEX_1(index) \
1001 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1002 #define ADDREGNAMES_ARR_INDEX_2(index) \
1003 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1004 #define ADDREGNAMES_ARR_INDEX_4(index) \
1005 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1006 #define ADDREGNAMES_ARR_INDEX_8(index) \
1007 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1008 #define ADDREGNAMES_ARR_INDEX_16(index) \
1009 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1010 #define ADDREGNAMES_ARR_INDEX_32(index) \
1011 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1013 #define ADDITIONAL_REGISTER_NAMES \
1015 ADDREGNAMES_ARR_INDEX_32 (0) \
1018 /* Number of actual hardware registers.
1019 The hardware registers are assigned numbers for the compiler
1020 from 0 to just below FIRST_PSEUDO_REGISTER.
1021 All registers that the compiler knows about must be given numbers,
1022 even those that are not normally considered general registers. */
1024 /* There are many other relevant definitions in sh.md's md_constants. */
1026 #define FIRST_GENERAL_REG R0_REG
1027 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1028 #define FIRST_FP_REG DR0_REG
1029 #define LAST_FP_REG (FIRST_FP_REG + \
1030 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1031 #define FIRST_XD_REG XD0_REG
1032 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1033 #define FIRST_TARGET_REG TR0_REG
1034 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1036 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1038 #define FIRST_BANKED_REG R0_REG
1039 #define LAST_BANKED_REG R7_REG
1041 #define BANKED_REGISTER_P(REGNO) \
1042 IN_RANGE ((REGNO), \
1043 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1044 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1046 #define GENERAL_REGISTER_P(REGNO) \
1047 IN_RANGE ((REGNO), \
1048 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1049 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1051 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1052 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1053 || ((REGNO) == FRAME_POINTER_REGNUM))
1055 #define FP_REGISTER_P(REGNO) \
1056 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1058 #define XD_REGISTER_P(REGNO) \
1059 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1061 #define FP_OR_XD_REGISTER_P(REGNO) \
1062 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1064 #define FP_ANY_REGISTER_P(REGNO) \
1065 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1067 #define SPECIAL_REGISTER_P(REGNO) \
1068 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1069 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1071 #define TARGET_REGISTER_P(REGNO) \
1072 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1074 #define SHMEDIA_REGISTER_P(REGNO) \
1075 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1076 || TARGET_REGISTER_P (REGNO))
1078 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1079 that should be fixed. */
1080 #define VALID_REGISTER_P(REGNO) \
1081 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1082 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1083 || (REGNO) == FRAME_POINTER_REGNUM \
1084 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1085 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1087 /* The mode that should be generally used to store a register by
1088 itself in the stack, or to load it back. */
1089 #define REGISTER_NATURAL_MODE(REGNO) \
1090 (FP_REGISTER_P (REGNO) ? SFmode \
1091 : XD_REGISTER_P (REGNO) ? DFmode \
1092 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1096 #define FIRST_PSEUDO_REGISTER 154
1098 /* Don't count soft frame pointer. */
1099 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1101 /* 1 for registers that have pervasive standard uses
1102 and are not available for the register allocator.
1104 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1105 It is 32 bits wide for SH2. */
1107 #define FIXED_REGISTERS \
1109 /* Regular registers. */ \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 1, \
1112 /* r16 is reserved, r18 is the former pr. */ \
1113 1, 0, 0, 0, 0, 0, 0, 0, \
1114 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1115 /* r26 is a global variable data pointer; r27 is for constants. */ \
1116 1, 1, 1, 1, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, \
1120 0, 0, 0, 0, 0, 0, 0, 1, \
1121 /* FP registers. */ \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 0, 0, 0, 0, 0, 0, 0, 0, \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, \
1128 0, 0, 0, 0, 0, 0, 0, 0, \
1129 0, 0, 0, 0, 0, 0, 0, 0, \
1130 /* Branch target registers. */ \
1131 0, 0, 0, 0, 0, 0, 0, 0, \
1132 /* XD registers. */ \
1133 0, 0, 0, 0, 0, 0, 0, 0, \
1134 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1135 1, 1, 1, 1, 1, 1, 0, 1, \
1140 /* 1 for registers not available across function calls.
1141 These must include the FIXED_REGISTERS and also any
1142 registers that can be used without being saved.
1143 The latter must include the registers where values are returned
1144 and the register where structure-value addresses are passed.
1145 Aside from that, you can include as many other registers as you like. */
1147 #define CALL_USED_REGISTERS \
1149 /* Regular registers. */ \
1150 1, 1, 1, 1, 1, 1, 1, 1, \
1151 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1152 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1153 across SH5 function calls. */ \
1154 0, 0, 0, 0, 0, 0, 0, 1, \
1155 1, 1, 1, 1, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 0, 0, 0, 0, 1, 1, 1, 1, \
1158 1, 1, 1, 1, 0, 0, 0, 0, \
1159 0, 0, 0, 0, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 1, 1, 1, 1, \
1161 /* FP registers. */ \
1162 1, 1, 1, 1, 1, 1, 1, 1, \
1163 1, 1, 1, 1, 0, 0, 0, 0, \
1164 1, 1, 1, 1, 1, 1, 1, 1, \
1165 1, 1, 1, 1, 1, 1, 1, 1, \
1166 1, 1, 1, 1, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 /* Branch target registers. */ \
1171 1, 1, 1, 1, 1, 0, 0, 0, \
1172 /* XD registers. */ \
1173 1, 1, 1, 1, 1, 1, 0, 0, \
1174 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1175 1, 1, 1, 1, 1, 1, 1, 1, \
1180 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1181 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1182 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1184 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1185 across SHcompact function calls. We can't tell whether a called
1186 function is SHmedia or SHcompact, so we assume it may be when
1187 compiling SHmedia code with the 32-bit ABI, since that's the only
1188 ABI that can be linked with SHcompact code. */
1189 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1191 && GET_MODE_SIZE (MODE) > 4 \
1192 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1193 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1194 || TARGET_REGISTER_P (REGNO) \
1195 || (REGNO) == PR_MEDIA_REG))
1197 /* Return number of consecutive hard regs needed starting at reg REGNO
1198 to hold something of mode MODE.
1199 This is ordinarily the length in words of a value of mode MODE
1200 but can be less for certain modes in special long registers.
1202 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1204 #define HARD_REGNO_NREGS(REGNO, MODE) \
1205 (XD_REGISTER_P (REGNO) \
1206 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1207 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1208 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1209 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1211 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1212 We can allow any mode in any general register. The special registers
1213 only allow SImode. Don't allow any mode in the PR. */
1215 /* We cannot hold DCmode values in the XD registers because alter_reg
1216 handles subregs of them incorrectly. We could work around this by
1217 spacing the XD registers like the DR registers, but this would require
1218 additional memory in every compilation to hold larger register vectors.
1219 We could hold SFmode / SCmode values in XD registers, but that
1220 would require a tertiary reload when reloading from / to memory,
1221 and a secondary reload to reload from / to general regs; that
1222 seems to be a loosing proposition. */
1223 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1224 it won't be ferried through GP registers first. */
1225 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1226 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1227 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1228 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1230 : (MODE) == V2SFmode \
1231 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1232 || GENERAL_REGISTER_P (REGNO)) \
1233 : (MODE) == V4SFmode \
1234 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1235 || GENERAL_REGISTER_P (REGNO)) \
1236 : (MODE) == V16SFmode \
1238 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1239 : (REGNO) == FIRST_XD_REG) \
1240 : FP_REGISTER_P (REGNO) \
1241 ? ((MODE) == SFmode || (MODE) == SImode \
1242 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1243 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1244 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1245 || (MODE) == V2SFmode || (MODE) == TImode))) \
1246 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1247 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1248 && (MODE) == TImode \
1249 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1250 : XD_REGISTER_P (REGNO) \
1251 ? (MODE) == DFmode \
1252 : TARGET_REGISTER_P (REGNO) \
1253 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1254 : (REGNO) == PR_REG ? (MODE) == SImode \
1255 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1258 /* Value is 1 if it is a good idea to tie two pseudo registers
1259 when one has mode MODE1 and one has mode MODE2.
1260 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1261 for any hard reg, then this must be 0 for correct output.
1262 That's the case for xd registers: we don't hold SFmode values in
1263 them, so we can't tie an SFmode pseudos with one in another
1264 floating-point mode. */
1266 #define MODES_TIEABLE_P(MODE1, MODE2) \
1267 ((MODE1) == (MODE2) \
1268 || (TARGET_SHMEDIA \
1269 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1270 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1271 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1272 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1273 && (GET_MODE_SIZE (MODE2) <= 4)) \
1274 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1276 /* A C expression that is nonzero if hard register NEW_REG can be
1277 considered for use as a rename register for OLD_REG register */
1279 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1280 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1282 /* Specify the registers used for certain standard purposes.
1283 The values of these macros are register numbers. */
1285 /* Define this if the program counter is overloaded on a register. */
1286 /* #define PC_REGNUM 15*/
1288 /* Register to use for pushing function arguments. */
1289 #define STACK_POINTER_REGNUM SP_REG
1291 /* Base register for access to local variables of the function. */
1292 #define HARD_FRAME_POINTER_REGNUM FP_REG
1294 /* Base register for access to local variables of the function. */
1295 #define FRAME_POINTER_REGNUM 153
1297 /* Fake register that holds the address on the stack of the
1298 current function's return address. */
1299 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1301 /* Register to hold the addressing base for position independent
1302 code access to data items. */
1303 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1305 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1307 /* Value should be nonzero if functions must have frame pointers.
1308 Zero means the frame pointer need not be set up (and parms may be accessed
1309 via the stack pointer) in functions that seem suitable. */
1311 #define FRAME_POINTER_REQUIRED 0
1313 /* Definitions for register eliminations.
1315 We have three registers that can be eliminated on the SH. First, the
1316 frame pointer register can often be eliminated in favor of the stack
1317 pointer register. Secondly, the argument pointer register can always be
1318 eliminated; it is replaced with either the stack or frame pointer.
1319 Third, there is the return address pointer, which can also be replaced
1320 with either the stack or the frame pointer. */
1322 /* This is an array of structures. Each structure initializes one pair
1323 of eliminable registers. The "from" register number is given first,
1324 followed by "to". Eliminations of the same "from" register are listed
1325 in order of preference. */
1327 /* If you add any registers here that are not actually hard registers,
1328 and that have any alternative of elimination that doesn't always
1329 apply, you need to amend calc_live_regs to exclude it, because
1330 reload spills all eliminable registers where it sees an
1331 can_eliminate == 0 entry, thus making them 'live' .
1332 If you add any hard registers that can be eliminated in different
1333 ways, you have to patch reload to spill them only when all alternatives
1334 of elimination fail. */
1336 #define ELIMINABLE_REGS \
1337 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1338 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1339 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1340 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1341 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1342 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1343 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1345 /* Given FROM and TO register numbers, say whether this elimination
1347 #define CAN_ELIMINATE(FROM, TO) \
1348 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1350 /* Define the offset between two registers, one to be eliminated, and the other
1351 its replacement, at the start of a routine. */
1353 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1354 OFFSET = initial_elimination_offset ((FROM), (TO))
1356 /* Base register for access to arguments of the function. */
1357 #define ARG_POINTER_REGNUM AP_REG
1359 /* Register in which the static-chain is passed to a function. */
1360 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1362 /* Don't default to pcc-struct-return, because we have already specified
1363 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1366 #define DEFAULT_PCC_STRUCT_RETURN 0
1368 #define SHMEDIA_REGS_STACK_ADJUST() \
1369 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1370 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1371 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1375 /* Define the classes of registers for register constraints in the
1376 machine description. Also define ranges of constants.
1378 One of the classes must always be named ALL_REGS and include all hard regs.
1379 If there is more than one class, another class must be named NO_REGS
1380 and contain no registers.
1382 The name GENERAL_REGS must be the name of a class (or an alias for
1383 another name such as ALL_REGS). This is the class of registers
1384 that is allowed by "g" or "r" in a register constraint.
1385 Also, registers outside this class are allocated only when
1386 instructions express preferences for them.
1388 The classes must be numbered in nondecreasing order; that is,
1389 a larger-numbered class must never be contained completely
1390 in a smaller-numbered class.
1392 For any two classes, it is very desirable that there be another
1393 class that represents their union. */
1395 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1396 be used as the destination of some of the arithmetic ops. There are
1397 also some special purpose registers; the T bit register, the
1398 Procedure Return Register and the Multiply Accumulate Registers. */
1399 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1400 reg_class_subunion. We don't want to have an actual union class
1401 of these, because it would only be used when both classes are calculated
1402 to give the same cost, but there is only one FPUL register.
1403 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1404 applying to the actual instruction alternative considered. E.g., the
1405 y/r alternative of movsi_ie is considered to have no more cost that
1406 the r/r alternative, which is patently untrue. */
1430 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1432 /* Give names of register classes as strings for dump file. */
1433 #define REG_CLASS_NAMES \
1448 "GENERAL_FP_REGS", \
1449 "GENERAL_DF_REGS", \
1454 /* Define which registers fit in which classes.
1455 This is an initializer for a vector of HARD_REG_SET
1456 of length N_REG_CLASSES. */
1458 #define REG_CLASS_CONTENTS \
1461 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1463 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1465 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1467 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1469 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1471 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1472 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1473 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1474 /* GENERAL_REGS: */ \
1475 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1477 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1479 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1480 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1481 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1483 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1485 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1486 /* GENERAL_FP_REGS: */ \
1487 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1488 /* GENERAL_DF_REGS: */ \
1489 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1490 /* TARGET_REGS: */ \
1491 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1493 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1496 /* The same information, inverted:
1497 Return the class number of the smallest class containing
1498 reg number REGNO. This could be a conditional expression
1499 or could index an array. */
1501 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1502 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1504 /* When defined, the compiler allows registers explicitly used in the
1505 rtl to be used as spill registers but prevents the compiler from
1506 extending the lifetime of these registers. */
1508 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1510 /* The order in which register should be allocated. */
1511 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1512 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1513 spilled or used otherwise, we better have the FP_REGS allocated first. */
1514 #define REG_ALLOC_ORDER \
1515 {/* Caller-saved FPRs */ \
1516 65, 66, 67, 68, 69, 70, 71, 64, \
1517 72, 73, 74, 75, 80, 81, 82, 83, \
1518 84, 85, 86, 87, 88, 89, 90, 91, \
1519 92, 93, 94, 95, 96, 97, 98, 99, \
1520 /* Callee-saved FPRs */ \
1521 76, 77, 78, 79,100,101,102,103, \
1522 104,105,106,107,108,109,110,111, \
1523 112,113,114,115,116,117,118,119, \
1524 120,121,122,123,124,125,126,127, \
1525 136,137,138,139,140,141,142,143, \
1527 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1528 1, 2, 3, 7, 6, 5, 4, 0, \
1529 8, 9, 17, 19, 20, 21, 22, 23, \
1530 36, 37, 38, 39, 40, 41, 42, 43, \
1532 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1533 10, 11, 12, 13, 14, 18, \
1534 /* SH5 callee-saved GPRs */ \
1535 28, 29, 30, 31, 32, 33, 34, 35, \
1536 44, 45, 46, 47, 48, 49, 50, 51, \
1537 52, 53, 54, 55, 56, 57, 58, 59, \
1539 /* SH5 branch target registers */ \
1540 128,129,130,131,132,133,134,135, \
1541 /* Fixed registers */ \
1542 15, 16, 24, 25, 26, 27, 63,144, \
1543 145,146,147,148,149,152,153 }
1545 /* The class value for index registers, and the one for base regs. */
1546 #define INDEX_REG_CLASS \
1547 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1548 #define BASE_REG_CLASS GENERAL_REGS
1550 /* Defines for sh.md and constraints.md. */
1552 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1553 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1554 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1555 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1556 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1557 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1558 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1559 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1561 #define CONST_OK_FOR_J16(VALUE) \
1562 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1563 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1565 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1566 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1568 /* Given an rtx X being reloaded into a reg required to be
1569 in class CLASS, return the class of reg to actually use.
1570 In general this is just CLASS; but on some machines
1571 in some cases it is preferable to use a more restrictive class. */
1573 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1574 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1575 && (GET_CODE (X) == CONST_DOUBLE \
1576 || GET_CODE (X) == SYMBOL_REF \
1577 || PIC_DIRECT_ADDR_P (X)) \
1582 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1583 ((((REGCLASS_HAS_FP_REG (CLASS) \
1584 && (GET_CODE (X) == REG \
1585 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1586 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1587 && TARGET_FMOVD)))) \
1588 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1589 && GET_CODE (X) == REG \
1590 && FP_REGISTER_P (REGNO (X)))) \
1591 && ! TARGET_SHMEDIA \
1592 && ((MODE) == SFmode || (MODE) == SImode)) \
1594 : (((CLASS) == FPUL_REGS \
1595 || (REGCLASS_HAS_FP_REG (CLASS) \
1596 && ! TARGET_SHMEDIA && MODE == SImode)) \
1597 && (GET_CODE (X) == MEM \
1598 || (GET_CODE (X) == REG \
1599 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1600 || REGNO (X) == T_REG \
1601 || system_reg_operand (X, VOIDmode))))) \
1603 : (((CLASS) == TARGET_REGS \
1604 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1605 && !satisfies_constraint_Csy (X) \
1606 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1608 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1609 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1610 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1612 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1613 && TARGET_REGISTER_P (REGNO (X))) \
1614 ? GENERAL_REGS : (ELSE))
1616 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1617 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1619 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1620 ((REGCLASS_HAS_FP_REG (CLASS) \
1621 && ! TARGET_SHMEDIA \
1622 && immediate_operand ((X), (MODE)) \
1623 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1624 && (MODE) == SFmode && fldi_ok ())) \
1626 : ((CLASS) == FPUL_REGS \
1627 && ((GET_CODE (X) == REG \
1628 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1629 || REGNO (X) == T_REG)) \
1630 || GET_CODE (X) == PLUS)) \
1632 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1633 ? (satisfies_constraint_I08 (X) \
1636 : ((CLASS) == FPSCR_REGS \
1637 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1638 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1640 : (REGCLASS_HAS_FP_REG (CLASS) \
1642 && immediate_operand ((X), (MODE)) \
1643 && (X) != CONST0_RTX (GET_MODE (X)) \
1644 && GET_MODE (X) != V4SFmode) \
1646 : (((MODE) == QImode || (MODE) == HImode) \
1647 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1649 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1650 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1652 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1655 /* Return the maximum number of consecutive registers
1656 needed to represent mode MODE in a register of class CLASS.
1658 If TARGET_SHMEDIA, we need two FP registers per word.
1659 Otherwise we will need at most one register per word. */
1660 #define CLASS_MAX_NREGS(CLASS, MODE) \
1662 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1663 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1664 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1666 /* If defined, gives a class of registers that cannot be used as the
1667 operand of a SUBREG that changes the mode of the object illegally. */
1668 /* ??? We need to renumber the internal numbers for the frnn registers
1669 when in little endian in order to allow mode size changes. */
1671 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1672 sh_cannot_change_mode_class (FROM, TO, CLASS)
1674 /* Stack layout; function entry, exit and calling. */
1676 /* Define the number of registers that can hold parameters.
1677 These macros are used only in other macro definitions below. */
1679 #define NPARM_REGS(MODE) \
1680 (TARGET_FPU_ANY && (MODE) == SFmode \
1681 ? (TARGET_SH5 ? 12 : 8) \
1682 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1683 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1684 ? (TARGET_SH5 ? 12 : 8) \
1685 : (TARGET_SH5 ? 8 : 4))
1687 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1688 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1690 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1691 #define FIRST_FP_RET_REG FIRST_FP_REG
1693 /* Define this if pushing a word on the stack
1694 makes the stack pointer a smaller address. */
1695 #define STACK_GROWS_DOWNWARD
1697 /* Define this macro to nonzero if the addresses of local variable slots
1698 are at negative offsets from the frame pointer. */
1699 #define FRAME_GROWS_DOWNWARD 1
1701 /* Offset from the frame pointer to the first local variable slot to
1703 #define STARTING_FRAME_OFFSET 0
1705 /* If we generate an insn to push BYTES bytes,
1706 this says how many the stack pointer really advances by. */
1707 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1708 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1709 do correct alignment. */
1711 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1714 /* Offset of first parameter from the argument pointer register value. */
1715 #define FIRST_PARM_OFFSET(FNDECL) 0
1717 /* Value is the number of byte of arguments automatically
1718 popped when returning from a subroutine call.
1719 FUNDECL is the declaration node of the function (as a tree),
1720 FUNTYPE is the data type of the function (as a tree),
1721 or for a library call it is an identifier node for the subroutine name.
1722 SIZE is the number of bytes of arguments passed on the stack.
1724 On the SH, the caller does not pop any of its arguments that were passed
1726 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1728 /* Value is the number of bytes of arguments automatically popped when
1729 calling a subroutine.
1730 CUM is the accumulated argument list.
1732 On SHcompact, the call trampoline pops arguments off the stack. */
1733 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1735 /* Some subroutine macros specific to this machine. */
1737 #define BASE_RETURN_VALUE_REG(MODE) \
1738 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1739 ? FIRST_FP_RET_REG \
1740 : TARGET_FPU_ANY && (MODE) == SCmode \
1741 ? FIRST_FP_RET_REG \
1742 : (TARGET_FPU_DOUBLE \
1743 && ((MODE) == DFmode || (MODE) == SFmode \
1744 || (MODE) == DCmode || (MODE) == SCmode )) \
1745 ? FIRST_FP_RET_REG \
1748 #define BASE_ARG_REG(MODE) \
1749 ((TARGET_SH2E && ((MODE) == SFmode)) \
1750 ? FIRST_FP_PARM_REG \
1751 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1752 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1753 ? FIRST_FP_PARM_REG \
1756 /* Define how to find the value returned by a function.
1757 VALTYPE is the data type of the value (as a tree).
1758 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1759 otherwise, FUNC is 0.
1760 For the SH, this is like LIBCALL_VALUE, except that we must change the
1761 mode like PROMOTE_MODE does.
1762 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1763 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1765 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1767 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1768 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1769 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1770 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1771 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1772 || TREE_CODE (VALTYPE) == REAL_TYPE \
1773 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1774 && sh_promote_prototypes (VALTYPE) \
1775 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1776 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1778 /* Define how to find the value returned by a library function
1779 assuming the value has mode MODE. */
1780 #define LIBCALL_VALUE(MODE) \
1781 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1783 /* 1 if N is a possible register number for a function value. */
1784 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1785 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1786 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1788 /* 1 if N is a possible register number for function argument passing. */
1789 /* ??? There are some callers that pass REGNO as int, and others that pass
1790 it as unsigned. We get warnings unless we do casts everywhere. */
1791 #define FUNCTION_ARG_REGNO_P(REGNO) \
1792 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1793 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1794 || (TARGET_FPU_ANY \
1795 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1796 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1797 + NPARM_REGS (SFmode))))
1799 /* Define a data type for recording info about an argument list
1800 during the scan of that argument list. This data type should
1801 hold all necessary information about the function itself
1802 and about the args processed so far, enough to enable macros
1803 such as FUNCTION_ARG to determine where the next arg should go.
1805 On SH, this is a single integer, which is a number of words
1806 of arguments scanned so far (including the invisible argument,
1807 if any, which holds the structure-value-address).
1808 Thus NARGREGS or more means all following args should go on the stack. */
1810 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1814 /* Nonzero if a prototype is available for the function. */
1816 /* The number of an odd floating-point register, that should be used
1817 for the next argument of type float. */
1818 int free_single_fp_reg;
1819 /* Whether we're processing an outgoing function call. */
1821 /* The number of general-purpose registers that should have been
1822 used to pass partial arguments, that are passed totally on the
1823 stack. On SHcompact, a call trampoline will pop them off the
1824 stack before calling the actual function, and, if the called
1825 function is implemented in SHcompact mode, the incoming arguments
1826 decoder will push such arguments back onto the stack. For
1827 incoming arguments, STACK_REGS also takes into account other
1828 arguments passed by reference, that the decoder will also push
1831 /* The number of general-purpose registers that should have been
1832 used to pass arguments, if the arguments didn't have to be passed
1835 /* Set as by shcompact_byref if the current argument is to be passed
1839 /* call_cookie is a bitmask used by call expanders, as well as
1840 function prologue and epilogues, to allow SHcompact to comply
1841 with the SH5 32-bit ABI, that requires 64-bit registers to be
1842 used even though only the lower 32-bit half is visible in
1843 SHcompact mode. The strategy is to call SHmedia trampolines.
1845 The alternatives for each of the argument-passing registers are
1846 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1847 contents from the address in it; (d) add 8 to it, storing the
1848 result in the next register, then (c); (e) copy it from some
1849 floating-point register,
1851 Regarding copies from floating-point registers, r2 may only be
1852 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1853 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1854 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1855 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1858 The bit mask is structured as follows:
1860 - 1 bit to tell whether to set up a return trampoline.
1862 - 3 bits to count the number consecutive registers to pop off the
1865 - 4 bits for each of r9, r8, r7 and r6.
1867 - 3 bits for each of r5, r4, r3 and r2.
1869 - 3 bits set to 0 (the most significant ones)
1872 1098 7654 3210 9876 5432 1098 7654 3210
1873 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1874 2223 3344 4555 6666 7777 8888 9999 SSS-
1876 - If F is set, the register must be copied from an FP register,
1877 whose number is encoded in the remaining bits.
1879 - Else, if L is set, the register must be loaded from the address
1880 contained in it. If the P bit is *not* set, the address of the
1881 following dword should be computed first, and stored in the
1884 - Else, if P is set, the register alone should be popped off the
1887 - After all this processing, the number of registers represented
1888 in SSS will be popped off the stack. This is an optimization
1889 for pushing/popping consecutive registers, typically used for
1890 varargs and large arguments partially passed in registers.
1892 - If T is set, a return trampoline will be set up for 64-bit
1893 return values to be split into 2 32-bit registers. */
1896 /* This is set to nonzero when the call in question must use the Renesas ABI,
1897 even without the -mrenesas option. */
1901 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1902 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1903 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1904 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1905 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1906 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1907 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1908 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1909 #define CALL_COOKIE_INT_REG(REG, VAL) \
1910 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1911 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1912 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1914 #define CUMULATIVE_ARGS struct sh_args
1916 #define GET_SH_ARG_CLASS(MODE) \
1917 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1919 /* There's no mention of complex float types in the SH5 ABI, so we
1920 should presumably handle them as aggregate types. */ \
1921 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1923 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1924 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1925 ? SH_ARG_FLOAT : SH_ARG_INT)
1927 #define ROUND_ADVANCE(SIZE) \
1928 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1930 /* Round a register number up to a proper boundary for an arg of mode
1933 The SH doesn't care about double alignment, so we only
1934 round doubles to even regs when asked to explicitly. */
1936 #define ROUND_REG(CUM, MODE) \
1937 (((TARGET_ALIGN_DOUBLE \
1938 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1939 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1940 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1941 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1942 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1943 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1945 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1946 for a call to a function whose data type is FNTYPE.
1947 For a library call, FNTYPE is 0.
1949 On SH, the offset always starts at 0: the first parm reg is always
1950 the same reg for a given argument class.
1952 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1954 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1955 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1957 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1958 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1960 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1961 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1962 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1963 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1965 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1966 This macro is only used in this file. */
1968 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1970 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1971 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1972 || ! (AGGREGATE_TYPE_P (TYPE) \
1973 || (!TARGET_FPU_ANY \
1974 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1975 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1976 && ! (CUM).force_mem \
1978 ? ((MODE) == BLKmode \
1979 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1980 + int_size_in_bytes (TYPE)) \
1981 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1982 : ((ROUND_REG((CUM), (MODE)) \
1983 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1984 <= NPARM_REGS (MODE))) \
1985 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1987 /* By accident we got stuck with passing SCmode on SH4 little endian
1988 in two registers that are nominally successive - which is different from
1989 two single SFmode values, where we take endianness translation into
1990 account. That does not work at all if an odd number of registers is
1991 already in use, so that got fixed, but library functions are still more
1992 likely to use complex numbers without mixing them with SFmode arguments
1993 (which in C would have to be structures), so for the sake of ABI
1994 compatibility the way SCmode values are passed when an even number of
1995 FP registers is in use remains different from a pair of SFmode values for
1998 foo (double); a: fr5,fr4
1999 foo (float a, float b); a: fr5 b: fr4
2000 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2001 this should be the other way round...
2002 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2003 #define FUNCTION_ARG_SCmode_WART 1
2005 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2006 register in SHcompact mode, it must be padded in the most
2007 significant end. This means that passing it by reference wouldn't
2008 pad properly on a big-endian machine. In this particular case, we
2009 pass this argument on the stack, in a way that the call trampoline
2010 will load its value into the appropriate register. */
2011 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2012 ((MODE) == BLKmode \
2013 && TARGET_SHCOMPACT \
2014 && ! TARGET_LITTLE_ENDIAN \
2015 && int_size_in_bytes (TYPE) > 4 \
2016 && int_size_in_bytes (TYPE) < 8)
2018 /* Minimum alignment for an argument to be passed by callee-copy
2019 reference. We need such arguments to be aligned to 8 byte
2020 boundaries, because they'll be loaded using quad loads. */
2021 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2023 /* The SH5 ABI requires floating-point arguments to be passed to
2024 functions without a prototype in both an FP register and a regular
2025 register or the stack. When passing the argument in both FP and
2026 general-purpose registers, list the FP register first. */
2027 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2033 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2034 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2035 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2040 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2041 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2042 + (CUM).arg_count[(int) SH_ARG_INT]) \
2043 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2044 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2047 /* The SH5 ABI requires regular registers or stack slots to be
2048 reserved for floating-point arguments. Registers are taken care of
2049 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2050 Unfortunately, there's no way to just reserve a stack slot, so
2051 we'll end up needlessly storing a copy of the argument in the
2052 stack. For incoming arguments, however, the PARALLEL will be
2053 optimized to the register-only form, and the value in the stack
2054 slot won't be used at all. */
2055 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2056 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2057 ? gen_rtx_REG ((MODE), (REG)) \
2058 : gen_rtx_PARALLEL ((MODE), \
2061 (VOIDmode, NULL_RTX, \
2064 (VOIDmode, gen_rtx_REG ((MODE), \
2068 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2070 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2071 || (MODE) == DCmode) \
2072 && ((CUM).arg_count[(int) SH_ARG_INT] \
2073 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2074 : GET_MODE_SIZE (MODE)) \
2075 + 7) / 8) > NPARM_REGS (SImode))
2077 /* Perform any needed actions needed for a function that is receiving a
2078 variable number of arguments. */
2080 /* Implement `va_start' for varargs and stdarg. */
2081 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2082 sh_va_start (valist, nextarg)
2084 /* Call the function profiler with a given profile label.
2085 We use two .aligns, so as to make sure that both the .long is aligned
2086 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2087 from the trapa instruction. */
2089 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2091 if (TARGET_SHMEDIA) \
2093 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2094 fprintf((STREAM), "\ttrapa\tr0\n"); \
2095 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2099 fprintf((STREAM), "\t.align\t2\n"); \
2100 fprintf((STREAM), "\ttrapa\t#33\n"); \
2101 fprintf((STREAM), "\t.align\t2\n"); \
2102 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2106 /* Define this macro if the code for function profiling should come
2107 before the function prologue. Normally, the profiling code comes
2110 #define PROFILE_BEFORE_PROLOGUE
2112 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2113 the stack pointer does not matter. The value is tested only in
2114 functions that have frame pointers.
2115 No definition is equivalent to always zero. */
2117 #define EXIT_IGNORE_STACK 1
2120 On the SH, the trampoline looks like
2121 2 0002 D202 mov.l l2,r2
2122 1 0000 D301 mov.l l1,r3
2125 5 0008 00000000 l1: .long area
2126 6 000c 00000000 l2: .long function */
2128 /* Length in units of the trampoline for entering a nested function. */
2129 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2131 /* Alignment required for a trampoline in bits . */
2132 #define TRAMPOLINE_ALIGNMENT \
2133 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2134 : TARGET_SHMEDIA ? 256 : 64)
2136 /* Emit RTL insns to initialize the variable parts of a trampoline.
2137 FNADDR is an RTX for the address of the function's pure code.
2138 CXT is an RTX for the static chain value for the function. */
2140 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2141 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2143 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2145 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2147 if (TARGET_SHMEDIA) \
2148 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2149 gen_reg_rtx (Pmode), 0, \
2153 /* A C expression whose value is RTL representing the value of the return
2154 address for the frame COUNT steps up from the current frame.
2155 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2156 can ignore COUNT. */
2158 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2159 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2161 /* A C expression whose value is RTL representing the location of the
2162 incoming return address at the beginning of any function, before the
2163 prologue. This RTL is either a REG, indicating that the return
2164 value is saved in REG, or a MEM representing a location in
2166 #define INCOMING_RETURN_ADDR_RTX \
2167 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2169 /* Addressing modes, and classification of registers for them. */
2170 #define HAVE_POST_INCREMENT TARGET_SH1
2171 #define HAVE_PRE_DECREMENT TARGET_SH1
2173 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2175 #define USE_LOAD_PRE_DECREMENT(mode) 0
2176 #define USE_STORE_POST_INCREMENT(mode) 0
2177 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2180 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2181 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2182 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2184 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2185 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2186 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2188 /* Macros to check register numbers against specific register classes. */
2190 /* These assume that REGNO is a hard or pseudo reg number.
2191 They give nonzero only if REGNO is a hard reg of the suitable class
2192 or a pseudo reg currently allocated to a suitable hard reg.
2193 Since they use reg_renumber, they are safe only once reg_renumber
2194 has been allocated, which happens in local-alloc.c. */
2196 #define REGNO_OK_FOR_BASE_P(REGNO) \
2197 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2198 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2199 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2201 ? (GENERAL_REGISTER_P (REGNO) \
2202 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2203 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2205 /* Maximum number of registers that can appear in a valid memory
2208 #define MAX_REGS_PER_ADDRESS 2
2210 /* Recognize any constant value that is a valid address. */
2212 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2214 /* Nonzero if the constant value X is a legitimate general operand. */
2215 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2217 #define LEGITIMATE_CONSTANT_P(X) \
2219 ? ((GET_MODE (X) != DFmode \
2220 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2221 || (X) == CONST0_RTX (GET_MODE (X)) \
2222 || ! TARGET_SHMEDIA_FPU \
2223 || TARGET_SHMEDIA64) \
2224 : (GET_CODE (X) != CONST_DOUBLE \
2225 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2226 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2228 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2229 and check its validity for a certain class.
2230 We have two alternate definitions for each of them.
2231 The usual definition accepts all pseudo regs; the other rejects
2232 them unless they have been allocated suitable hard regs.
2233 The symbol REG_OK_STRICT causes the latter definition to be used. */
2235 #ifndef REG_OK_STRICT
2237 /* Nonzero if X is a hard reg that can be used as a base reg
2238 or if it is a pseudo reg. */
2239 #define REG_OK_FOR_BASE_P(X) \
2240 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2242 /* Nonzero if X is a hard reg that can be used as an index
2243 or if it is a pseudo reg. */
2244 #define REG_OK_FOR_INDEX_P(X) \
2245 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2246 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2248 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2249 or if X is a pseudo reg. */
2250 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2251 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2252 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2256 /* Nonzero if X is a hard reg that can be used as a base reg. */
2257 #define REG_OK_FOR_BASE_P(X) \
2258 REGNO_OK_FOR_BASE_P (REGNO (X))
2260 /* Nonzero if X is a hard reg that can be used as an index. */
2261 #define REG_OK_FOR_INDEX_P(X) \
2262 REGNO_OK_FOR_INDEX_P (REGNO (X))
2264 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2265 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2266 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2270 /* Macros for extra constraints. */
2272 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2273 ((GET_CODE ((OP)) == LABEL_REF) \
2274 || (GET_CODE ((OP)) == CONST \
2275 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2276 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2277 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2279 #define IS_LITERAL_OR_SYMBOLIC_S16_P(OP) \
2280 (GET_CODE ((OP)) == SIGN_EXTEND \
2281 && (GET_MODE ((OP)) == DImode \
2282 || GET_MODE ((OP)) == SImode) \
2283 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2284 && GET_MODE (XEXP ((OP), 0)) == HImode \
2285 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2286 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2287 && (MOVI_SHORI_BASE_OPERAND_P \
2288 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2289 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2291 #define IS_LITERAL_OR_SYMBOLIC_U16_P(OP) \
2292 (GET_CODE ((OP)) == ZERO_EXTEND \
2293 && (GET_MODE ((OP)) == DImode \
2294 || GET_MODE ((OP)) == SImode) \
2295 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2296 && GET_MODE (XEXP ((OP), 0)) == HImode \
2297 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2298 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2299 && (MOVI_SHORI_BASE_OPERAND_P \
2300 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2301 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2303 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2305 && GET_CODE (OP) != CONST_INT \
2306 && GET_CODE (OP) != CONST_DOUBLE \
2308 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2309 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2310 && GET_CODE (OP) != LABEL_REF)))
2312 /* Check whether OP is a datalabel unspec. */
2313 #define DATALABEL_REF_NO_CONST_P(OP) \
2314 (GET_CODE (OP) == UNSPEC \
2315 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2316 && XVECLEN ((OP), 0) == 1 \
2317 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2319 #define GOT_ENTRY_P(OP) \
2320 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2321 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2323 #define GOTPLT_ENTRY_P(OP) \
2324 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2325 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2327 #define UNSPEC_GOTOFF_P(OP) \
2328 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2330 #define GOTOFF_P(OP) \
2331 (GET_CODE (OP) == CONST \
2332 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2333 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2334 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2335 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2337 #define PIC_ADDR_P(OP) \
2338 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2339 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2341 #define PIC_OFFSET_P(OP) \
2343 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2344 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2346 #define PIC_DIRECT_ADDR_P(OP) \
2347 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2349 #define NON_PIC_REFERENCE_P(OP) \
2350 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2351 || (GET_CODE (OP) == CONST \
2352 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2353 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2354 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2355 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2356 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2357 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2358 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2359 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2361 #define PIC_REFERENCE_P(OP) \
2362 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2363 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2365 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2367 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2368 || PIC_OFFSET_P (OP)) \
2369 : NON_PIC_REFERENCE_P (OP))
2371 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2372 that is a valid memory address for an instruction.
2373 The MODE argument is the machine mode for the MEM expression
2374 that wants to use this address. */
2376 #define MODE_DISP_OK_4(X,MODE) \
2377 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2378 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2380 #define MODE_DISP_OK_8(X,MODE) \
2381 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2382 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2384 #undef MODE_DISP_OK_4
2385 #define MODE_DISP_OK_4(X,MODE) \
2386 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2387 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2388 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2389 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2391 #undef MODE_DISP_OK_8
2392 #define MODE_DISP_OK_8(X,MODE) \
2393 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2394 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2395 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2396 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2398 #define BASE_REGISTER_RTX_P(X) \
2399 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2400 || (GET_CODE (X) == SUBREG \
2401 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2402 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2403 && GET_CODE (SUBREG_REG (X)) == REG \
2404 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2406 /* Since this must be r0, which is a single register class, we must check
2407 SUBREGs more carefully, to be sure that we don't accept one that extends
2408 outside the class. */
2409 #define INDEX_REGISTER_RTX_P(X) \
2410 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2411 || (GET_CODE (X) == SUBREG \
2412 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2413 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2414 && GET_CODE (SUBREG_REG (X)) == REG \
2415 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2417 /* Jump to LABEL if X is a valid address RTX. This must also take
2418 REG_OK_STRICT into account when deciding about valid registers, but it uses
2419 the above macros so we are in luck.
2427 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2428 into the FRx registers. We implement this by setting the maximum offset
2429 to zero when the value is SFmode. This also restricts loading of SFmode
2430 values into the integer registers, but that can't be helped. */
2432 /* The SH allows a displacement in a QI or HI amode, but only when the
2433 other operand is R0. GCC doesn't handle this very well, so we forgo
2436 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2437 DI can be any number 0..60. */
2439 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2441 if (GET_CODE (OP) == CONST_INT) \
2443 if (TARGET_SHMEDIA) \
2446 /* Check if this the address of an unaligned load / store. */\
2447 if ((MODE) == VOIDmode) \
2449 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2453 MODE_SIZE = GET_MODE_SIZE (MODE); \
2454 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2455 && INTVAL (OP) >= -512 * MODE_SIZE \
2456 && INTVAL (OP) < 512 * MODE_SIZE) \
2461 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2462 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2466 #define ALLOW_INDEXED_ADDRESS \
2467 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2469 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2471 if (BASE_REGISTER_RTX_P (X)) \
2473 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2474 && ! TARGET_SHMEDIA \
2475 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2477 else if (GET_CODE (X) == PLUS \
2478 && ((MODE) != PSImode || reload_completed)) \
2480 rtx xop0 = XEXP ((X), 0); \
2481 rtx xop1 = XEXP ((X), 1); \
2482 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2483 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2484 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2485 || ((xop0 == stack_pointer_rtx \
2486 || xop0 == hard_frame_pointer_rtx) \
2487 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2488 || ((xop1 == stack_pointer_rtx \
2489 || xop1 == hard_frame_pointer_rtx) \
2490 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2491 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2492 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2493 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2494 && TARGET_FMOVD && MODE == DFmode))) \
2496 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2498 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2504 /* Try machine-dependent ways of modifying an illegitimate address
2505 to be legitimate. If we find one, return the new, valid address.
2506 This macro is used in only one place: `memory_address' in explow.c.
2508 OLDX is the address as it was before break_out_memory_refs was called.
2509 In some cases it is useful to look at this to decide what needs to be done.
2511 MODE and WIN are passed so that this macro can use
2512 GO_IF_LEGITIMATE_ADDRESS.
2514 It is always safe for this macro to do nothing. It exists to recognize
2515 opportunities to optimize the output.
2517 For the SH, if X is almost suitable for indexing, but the offset is
2518 out of range, convert it into a normal form so that cse has a chance
2519 of reducing the number of address registers used. */
2521 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2524 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2525 if (GET_CODE (X) == PLUS \
2526 && (GET_MODE_SIZE (MODE) == 4 \
2527 || GET_MODE_SIZE (MODE) == 8) \
2528 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2529 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2530 && ! TARGET_SHMEDIA \
2531 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2532 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2534 rtx index_rtx = XEXP ((X), 1); \
2535 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2538 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2539 /* On rare occasions, we might get an unaligned pointer \
2540 that is indexed in a way to give an aligned address. \
2541 Therefore, keep the lower two bits in offset_base. */ \
2542 /* Instead of offset_base 128..131 use 124..127, so that \
2543 simple add suffices. */ \
2546 offset_base = ((offset + 4) & ~60) - 4; \
2549 offset_base = offset & ~60; \
2550 /* Sometimes the normal form does not suit DImode. We \
2551 could avoid that by using smaller ranges, but that \
2552 would give less optimized code when SImode is \
2554 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2556 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2557 GEN_INT (offset_base), NULL_RTX, 0, \
2560 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2566 /* A C compound statement that attempts to replace X, which is an address
2567 that needs reloading, with a valid memory address for an operand of
2568 mode MODE. WIN is a C statement label elsewhere in the code.
2570 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2571 of the address. That will allow inheritance of the address reloads. */
2573 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2575 if (GET_CODE (X) == PLUS \
2576 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2577 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2578 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2579 && ! TARGET_SHMEDIA \
2580 && ! (TARGET_SH4 && (MODE) == DFmode) \
2581 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2582 && (ALLOW_INDEXED_ADDRESS \
2583 || XEXP ((X), 0) == stack_pointer_rtx \
2584 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2586 rtx index_rtx = XEXP (X, 1); \
2587 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2590 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2592 push_reload (X, NULL_RTX, &X, NULL, \
2593 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2597 if (TARGET_SH2E && MODE == SFmode) \
2600 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2601 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2605 /* Instead of offset_base 128..131 use 124..127, so that \
2606 simple add suffices. */ \
2609 offset_base = ((offset + 4) & ~60) - 4; \
2612 offset_base = offset & ~60; \
2613 /* Sometimes the normal form does not suit DImode. We \
2614 could avoid that by using smaller ranges, but that \
2615 would give less optimized code when SImode is \
2617 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2619 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2620 GEN_INT (offset_base)); \
2621 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2622 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2623 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2628 /* We must re-recognize what we created before. */ \
2629 else if (GET_CODE (X) == PLUS \
2630 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2631 && GET_CODE (XEXP (X, 0)) == PLUS \
2632 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2633 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2634 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2635 && ! TARGET_SHMEDIA \
2636 && ! (TARGET_SH2E && MODE == SFmode)) \
2638 /* Because this address is so complex, we know it must have \
2639 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2640 it is already unshared, and needs no further unsharing. */ \
2641 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2642 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2647 /* Go to LABEL if ADDR (a legitimate address expression)
2648 has an effect that depends on the machine mode it is used for.
2650 ??? Strictly speaking, we should also include all indexed addressing,
2651 because the index scale factor is the length of the operand.
2652 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2653 high if we did that. So we rely on reload to fix things up.
2655 Auto-increment addressing is now treated in recog.c. */
2657 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2659 /* Specify the machine mode that this machine uses
2660 for the index in the tablejump instruction. */
2661 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2663 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2664 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2665 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2666 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2667 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2668 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2671 /* Define as C expression which evaluates to nonzero if the tablejump
2672 instruction expects the table to contain offsets from the address of the
2674 Do not define this if the table should contain absolute addresses. */
2675 #define CASE_VECTOR_PC_RELATIVE 1
2677 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2678 #define FLOAT_TYPE_SIZE 32
2680 /* Since the SH2e has only `float' support, it is desirable to make all
2681 floating point types equivalent to `float'. */
2682 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2684 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2685 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2687 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2690 /* 'char' is signed by default. */
2691 #define DEFAULT_SIGNED_CHAR 1
2693 /* The type of size_t unsigned int. */
2694 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2697 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2699 #define WCHAR_TYPE "short unsigned int"
2700 #define WCHAR_TYPE_SIZE 16
2702 #define SH_ELF_WCHAR_TYPE "long int"
2704 /* Max number of bytes we can move from memory to memory
2705 in one reasonably fast instruction. */
2706 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2708 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2709 MOVE_MAX is not a compile-time constant. */
2710 #define MAX_MOVE_MAX 8
2712 /* Max number of bytes we want move_by_pieces to be able to copy
2714 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2716 /* Define if operations between registers always perform the operation
2717 on the full register even if a narrower mode is specified. */
2718 #define WORD_REGISTER_OPERATIONS
2720 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2721 will either zero-extend or sign-extend. The value of this macro should
2722 be the code that says which one of the two operations is implicitly
2723 done, UNKNOWN if none. */
2724 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2725 /* FP registers can load SImode values, but don't implicitly sign-extend
2727 #define LOAD_EXTEND_OP(MODE) \
2728 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2729 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2731 /* Define if loading short immediate values into registers sign extends. */
2732 #define SHORT_IMMEDIATES_SIGN_EXTEND
2734 /* Nonzero if access to memory by bytes is no faster than for words. */
2735 #define SLOW_BYTE_ACCESS 1
2737 /* Immediate shift counts are truncated by the output routines (or was it
2738 the assembler?). Shift counts in a register are truncated by SH. Note
2739 that the native compiler puts too large (> 32) immediate shift counts
2740 into a register and shifts by the register, letting the SH decide what
2741 to do instead of doing that itself. */
2742 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2743 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2744 expects - the sign bit is significant - so it appears that we need to
2745 leave this zero for correct SH3 code. */
2746 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2748 /* All integers have the same format so truncation is easy. */
2749 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2750 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2751 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2753 /* Define this if addresses of constant functions
2754 shouldn't be put through pseudo regs where they can be cse'd.
2755 Desirable on machines where ordinary constants are expensive
2756 but a CALL with constant address is cheap. */
2757 /*#define NO_FUNCTION_CSE 1*/
2759 /* The machine modes of pointers and functions. */
2760 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2761 #define FUNCTION_MODE Pmode
2763 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2764 are actually function calls with some special constraints on arguments
2767 These macros tell reorg that the references to arguments and
2768 register clobbers for insns of type sfunc do not appear to happen
2769 until after the millicode call. This allows reorg to put insns
2770 which set the argument registers into the delay slot of the millicode
2771 call -- thus they act more like traditional CALL_INSNs.
2773 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2774 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2777 #define INSN_SETS_ARE_DELAYED(X) \
2778 ((GET_CODE (X) == INSN \
2779 && GET_CODE (PATTERN (X)) != SEQUENCE \
2780 && GET_CODE (PATTERN (X)) != USE \
2781 && GET_CODE (PATTERN (X)) != CLOBBER \
2782 && get_attr_is_sfunc (X)))
2784 #define INSN_REFERENCES_ARE_DELAYED(X) \
2785 ((GET_CODE (X) == INSN \
2786 && GET_CODE (PATTERN (X)) != SEQUENCE \
2787 && GET_CODE (PATTERN (X)) != USE \
2788 && GET_CODE (PATTERN (X)) != CLOBBER \
2789 && get_attr_is_sfunc (X)))
2792 /* Position Independent Code. */
2794 /* We can't directly access anything that contains a symbol,
2795 nor can we indirect via the constant pool. */
2796 #define LEGITIMATE_PIC_OPERAND_P(X) \
2797 ((! nonpic_symbol_mentioned_p (X) \
2798 && (GET_CODE (X) != SYMBOL_REF \
2799 || ! CONSTANT_POOL_ADDRESS_P (X) \
2800 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2801 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2803 #define SYMBOLIC_CONST_P(X) \
2804 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2805 && nonpic_symbol_mentioned_p (X))
2807 /* Compute extra cost of moving data between one register class
2810 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2811 uses this information. Hence, the general register <-> floating point
2812 register information here is not used for SFmode. */
2814 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2815 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2816 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2818 #define REGCLASS_HAS_FP_REG(CLASS) \
2819 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2820 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2822 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2823 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2825 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2826 would be so that people with slow memory systems could generate
2827 different code that does fewer memory accesses. */
2829 /* A C expression for the cost of a branch instruction. A value of 1
2830 is the default; other values are interpreted relative to that.
2831 The SH1 does not have delay slots, hence we get a pipeline stall
2832 at every branch. The SH4 is superscalar, so the single delay slot
2833 is not sufficient to keep both pipelines filled. */
2834 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2836 /* Assembler output control. */
2838 /* A C string constant describing how to begin a comment in the target
2839 assembler language. The compiler assumes that the comment will end at
2840 the end of the line. */
2841 #define ASM_COMMENT_START "!"
2843 #define ASM_APP_ON ""
2844 #define ASM_APP_OFF ""
2845 #define FILE_ASM_OP "\t.file\n"
2846 #define SET_ASM_OP "\t.set\t"
2848 /* How to change between sections. */
2850 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2851 #define DATA_SECTION_ASM_OP "\t.data"
2853 #if defined CRT_BEGIN || defined CRT_END
2854 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2855 # undef TEXT_SECTION_ASM_OP
2856 # if __SHMEDIA__ == 1 && __SH5__ == 32
2857 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2859 # define TEXT_SECTION_ASM_OP "\t.text"
2864 /* If defined, a C expression whose value is a string containing the
2865 assembler operation to identify the following data as
2866 uninitialized global data. If not defined, and neither
2867 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2868 uninitialized global data will be output in the data section if
2869 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2871 #ifndef BSS_SECTION_ASM_OP
2872 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2875 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2876 separate, explicit argument. If you define this macro, it is used
2877 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2878 handling the required alignment of the variable. The alignment is
2879 specified as the number of bits.
2881 Try to use function `asm_output_aligned_bss' defined in file
2882 `varasm.c' when defining this macro. */
2883 #ifndef ASM_OUTPUT_ALIGNED_BSS
2884 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2885 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2888 /* Define this so that jump tables go in same section as the current function,
2889 which could be text or it could be a user defined section. */
2890 #define JUMP_TABLES_IN_TEXT_SECTION 1
2892 #undef DO_GLOBAL_CTORS_BODY
2893 #define DO_GLOBAL_CTORS_BODY \
2895 typedef (*pfunc)(); \
2896 extern pfunc __ctors[]; \
2897 extern pfunc __ctors_end[]; \
2899 for (p = __ctors_end; p > __ctors; ) \
2905 #undef DO_GLOBAL_DTORS_BODY
2906 #define DO_GLOBAL_DTORS_BODY \
2908 typedef (*pfunc)(); \
2909 extern pfunc __dtors[]; \
2910 extern pfunc __dtors_end[]; \
2912 for (p = __dtors; p < __dtors_end; p++) \
2918 #define ASM_OUTPUT_REG_PUSH(file, v) \
2920 if (TARGET_SHMEDIA) \
2922 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2923 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2926 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2929 #define ASM_OUTPUT_REG_POP(file, v) \
2931 if (TARGET_SHMEDIA) \
2933 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2934 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2937 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2940 /* DBX register number for a given compiler register number. */
2941 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2943 /* svr4.h undefines this macro, yet we really want to use the same numbers
2944 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2945 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2946 register exists, so we should return -1 for invalid register numbers. */
2947 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2949 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2950 used to use the encodings 245..260, but that doesn't make sense:
2951 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2952 the FP registers stay the same when switching between compact and media
2953 mode. Hence, we also need to use the same dwarf frame columns.
2954 Likewise, we need to support unwind information for SHmedia registers
2955 even in compact code. */
2956 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2957 (IN_RANGE ((REGNO), \
2958 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2959 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2960 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2961 : ((int) (REGNO) >= FIRST_FP_REG \
2963 <= (FIRST_FP_REG + \
2964 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2965 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2966 + (TARGET_SH5 ? 77 : 25)) \
2967 : XD_REGISTER_P (REGNO) \
2968 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2969 : TARGET_REGISTER_P (REGNO) \
2970 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2971 : (REGNO) == PR_REG \
2972 ? (TARGET_SH5 ? 18 : 17) \
2973 : (REGNO) == PR_MEDIA_REG \
2974 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2975 : (REGNO) == T_REG \
2976 ? (TARGET_SH5 ? 242 : 18) \
2977 : (REGNO) == GBR_REG \
2978 ? (TARGET_SH5 ? 238 : 19) \
2979 : (REGNO) == MACH_REG \
2980 ? (TARGET_SH5 ? 239 : 20) \
2981 : (REGNO) == MACL_REG \
2982 ? (TARGET_SH5 ? 240 : 21) \
2983 : (REGNO) == FPUL_REG \
2984 ? (TARGET_SH5 ? 244 : 23) \
2987 /* This is how to output a reference to a symbol_ref. On SH5,
2988 references to non-code symbols must be preceded by `datalabel'. */
2989 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2992 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2993 fputs ("datalabel ", (FILE)); \
2994 assemble_name ((FILE), XSTR ((SYM), 0)); \
2998 /* This is how to output an assembler line
2999 that says to advance the location counter
3000 to a multiple of 2**LOG bytes. */
3002 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3004 fprintf ((FILE), "\t.align %d\n", (LOG))
3006 /* Globalizing directive for a label. */
3007 #define GLOBAL_ASM_OP "\t.global\t"
3009 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3011 /* Output a relative address table. */
3013 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3014 switch (GET_MODE (BODY)) \
3019 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3023 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3028 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3032 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3037 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3041 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3047 /* Output an absolute table element. */
3049 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3050 if (! optimize || TARGET_BIGTABLE) \
3051 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3053 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3056 /* A C statement to be executed just prior to the output of
3057 assembler code for INSN, to modify the extracted operands so
3058 they will be output differently.
3060 Here the argument OPVEC is the vector containing the operands
3061 extracted from INSN, and NOPERANDS is the number of elements of
3062 the vector which contain meaningful data for this insn.
3063 The contents of this vector are what will be used to convert the insn
3064 template into assembler code, so you can change the assembler output
3065 by changing the contents of the vector. */
3067 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3068 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3070 /* Print operand X (an rtx) in assembler syntax to file FILE.
3071 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3072 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3074 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3076 /* Print a memory address as an operand to reference that memory location. */
3078 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3080 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3081 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3082 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3084 /* Recognize machine-specific patterns that may appear within
3085 constants. Used for PIC-specific UNSPECs. */
3086 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3088 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3090 switch (XINT ((X), 1)) \
3092 case UNSPEC_DATALABEL: \
3093 fputs ("datalabel ", (STREAM)); \
3094 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3097 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3098 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3101 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3102 fputs ("@GOT", (STREAM)); \
3104 case UNSPEC_GOTOFF: \
3105 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3106 fputs ("@GOTOFF", (STREAM)); \
3109 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3110 fputs ("@PLT", (STREAM)); \
3112 case UNSPEC_GOTPLT: \
3113 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3114 fputs ("@GOTPLT", (STREAM)); \
3116 case UNSPEC_DTPOFF: \
3117 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3118 fputs ("@DTPOFF", (STREAM)); \
3120 case UNSPEC_GOTTPOFF: \
3121 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3122 fputs ("@GOTTPOFF", (STREAM)); \
3124 case UNSPEC_TPOFF: \
3125 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3126 fputs ("@TPOFF", (STREAM)); \
3128 case UNSPEC_CALLER: \
3131 /* LPCS stands for Label for PIC Call Site. */ \
3132 ASM_GENERATE_INTERNAL_LABEL \
3133 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3134 assemble_name ((STREAM), name); \
3147 extern struct rtx_def *sh_compare_op0;
3148 extern struct rtx_def *sh_compare_op1;
3150 /* Which processor to schedule for. The elements of the enumeration must
3151 match exactly the cpu attribute in the sh.md file. */
3153 enum processor_type {
3165 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3166 extern enum processor_type sh_cpu;
3168 extern int optimize; /* needed for gen_casesi. */
3170 enum mdep_reorg_phase_e
3172 SH_BEFORE_MDEP_REORG,
3173 SH_INSERT_USES_LABELS,
3174 SH_SHORTEN_BRANCHES0,
3176 SH_SHORTEN_BRANCHES1,
3180 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3182 /* Handle Renesas compiler's pragmas. */
3183 #define REGISTER_TARGET_PRAGMAS() do { \
3184 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3185 c_register_pragma (0, "trapa", sh_pr_trapa); \
3186 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3189 extern tree sh_deferred_function_attributes;
3190 extern tree *sh_deferred_function_attributes_tail;
3192 /* Set when processing a function with interrupt attribute. */
3194 extern int current_function_interrupt;
3197 /* Instructions with unfilled delay slots take up an
3198 extra two bytes for the nop in the delay slot.
3199 sh-dsp parallel processing insns are four bytes long. */
3201 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3202 (LENGTH) += sh_insn_length_adjustment (X);
3204 /* Define this macro if it is advisable to hold scalars in registers
3205 in a wider mode than that declared by the program. In such cases,
3206 the value is constrained to be within the bounds of the declared
3207 type, but kept valid in the wider mode. The signedness of the
3208 extension may differ from that of the type.
3210 Leaving the unsignedp unchanged gives better code than always setting it
3211 to 0. This is despite the fact that we have only signed char and short
3212 load instructions. */
3213 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3214 if (GET_MODE_CLASS (MODE) == MODE_INT \
3215 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3216 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3217 (MODE) = (TARGET_SH1 ? SImode \
3218 : TARGET_SHMEDIA32 ? SImode : DImode);
3220 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3222 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3224 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3225 and popping arguments. However, we do have push/pop instructions, and
3226 rather limited offsets (4 bits) in load/store instructions, so it isn't
3227 clear if this would give better code. If implemented, should check for
3228 compatibility problems. */
3230 #define SH_DYNAMIC_SHIFT_COST \
3231 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3234 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3236 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3238 #define ACTUAL_NORMAL_MODE(ENTITY) \
3239 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3241 #define NORMAL_MODE(ENTITY) \
3242 (sh_cfun_interrupt_handler_p () \
3243 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3244 : ACTUAL_NORMAL_MODE (ENTITY))
3246 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3248 #define MODE_EXIT(ENTITY) \
3249 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3251 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3252 && (REGNO) == FPSCR_REG)
3254 #define MODE_NEEDED(ENTITY, INSN) \
3255 (recog_memoized (INSN) >= 0 \
3256 ? get_attr_fp_mode (INSN) \
3259 #define MODE_AFTER(MODE, INSN) \
3261 && recog_memoized (INSN) >= 0 \
3262 && get_attr_fp_set (INSN) != FP_SET_NONE \
3263 ? (int) get_attr_fp_set (INSN) \
3266 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3267 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3269 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3270 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3272 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3273 sh_can_redirect_branch ((INSN), (SEQ))
3275 #define DWARF_FRAME_RETURN_COLUMN \
3276 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3278 #define EH_RETURN_DATA_REGNO(N) \
3279 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3281 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3282 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3284 /* We have to distinguish between code and data, so that we apply
3285 datalabel where and only where appropriate. Use sdataN for data. */
3286 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3287 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3288 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3289 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3291 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3292 indirect are handled automatically. */
3293 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3295 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3296 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3298 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3299 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3304 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3305 /* SH constant pool breaks the devices in crtstuff.c to control section
3306 in where code resides. We have to write it as asm code. */
3307 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3308 asm (SECTION_OP "\n\
3314 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3315 2:\n" TEXT_SECTION_ASM_OP);
3316 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3318 /* FIXME: middle-end support for highpart optimizations is missing. */
3319 #define high_life_started reload_in_progress
3321 #endif /* ! GCC_SH_H */
OSDN Git Service
