1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "config/vxworks-dummy.h"
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
36 #define TARGET_CPU_CPP_BUILTINS() \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
44 builtin_define ("__sh1__"); \
47 builtin_define ("__sh2__"); \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
101 #define CONDITIONAL_REGISTER_USAGE do \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
115 if (TARGET_SHMEDIA) \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
147 /* Nonzero if this is an ELF target - compile time only */
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
179 /* Nonzero if we should generate code using type 4 insns. */
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
195 /* Nonzero if we should generate code using the SHmedia instruction
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
274 #define SUPPORT_SH2 1
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
281 #define SUPPORT_SH4_NOFPU 1
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
293 #define SUPPORT_SH4_SINGLE_ONLY 1
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
300 #define SUPPORT_SH4A 1
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
389 #define ASM_SPEC SH_ASM_SPEC
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
466 flag_omit_frame_pointer = -1; \
468 sh_div_str = "inv:minlat"; \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
486 flag_branch_target_load_optimize = 1; \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
500 set_param_value ("simultaneous-prefetches", 2); \
503 #define ASSEMBLER_DIALECT assembler_dialect
505 extern int assembler_dialect;
507 enum sh_divide_strategy_e {
508 /* SH5 strategies. */
511 SH_DIV_FP, /* We could do this also for SH4. */
519 /* SH1 .. SH4 strategies. Because of the small number of registers
520 available, the compiler uses knowledge of the actual set of registers
521 being clobbered by the different functions called. */
522 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
523 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
524 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
528 extern enum sh_divide_strategy_e sh_div_strategy;
530 #ifndef SH_DIV_STRATEGY_DEFAULT
531 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
536 #define OVERRIDE_OPTIONS \
540 SUBTARGET_OVERRIDE_OPTIONS; \
541 if (flag_finite_math_only == 2) \
542 flag_finite_math_only \
543 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
544 if (TARGET_SH2E && !flag_finite_math_only) \
545 target_flags |= MASK_IEEE; \
547 assembler_dialect = 0; \
555 if (TARGET_SH2A_DOUBLE) \
556 target_flags |= MASK_FMOVD; \
564 assembler_dialect = 1; \
567 if (TARGET_SH4A_ARCH) \
569 assembler_dialect = 1; \
575 target_flags |= MASK_ALIGN_DOUBLE; \
576 if (TARGET_SHMEDIA_FPU) \
577 target_flags |= MASK_FMOVD; \
578 if (TARGET_SHMEDIA) \
580 /* There are no delay slots on SHmedia. */ \
581 flag_delayed_branch = 0; \
582 /* Relaxation isn't yet supported for SHmedia */ \
583 target_flags &= ~MASK_RELAX; \
584 /* After reload, if conversion does little good but can cause \
586 - find_if_block doesn't do anything for SH because we don't\
587 have conditional execution patterns. (We use conditional\
588 move patterns, which are handled differently, and only \
590 - find_cond_trap doesn't do anything for the SH because we \
591 don't have conditional traps. \
592 - find_if_case_1 uses redirect_edge_and_branch_force in \
593 the only path that does an optimization, and this causes \
594 an ICE when branch targets are in registers. \
595 - find_if_case_2 doesn't do anything for the SHmedia after \
596 reload except when it can redirect a tablejump - and \
597 that's rather rare. */ \
598 flag_if_conversion2 = 0; \
599 if (! strcmp (sh_div_str, "call")) \
600 sh_div_strategy = SH_DIV_CALL; \
601 else if (! strcmp (sh_div_str, "call2")) \
602 sh_div_strategy = SH_DIV_CALL2; \
603 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
604 sh_div_strategy = SH_DIV_FP; \
605 else if (! strcmp (sh_div_str, "inv")) \
606 sh_div_strategy = SH_DIV_INV; \
607 else if (! strcmp (sh_div_str, "inv:minlat")) \
608 sh_div_strategy = SH_DIV_INV_MINLAT; \
609 else if (! strcmp (sh_div_str, "inv20u")) \
610 sh_div_strategy = SH_DIV_INV20U; \
611 else if (! strcmp (sh_div_str, "inv20l")) \
612 sh_div_strategy = SH_DIV_INV20L; \
613 else if (! strcmp (sh_div_str, "inv:call2")) \
614 sh_div_strategy = SH_DIV_INV_CALL2; \
615 else if (! strcmp (sh_div_str, "inv:call")) \
616 sh_div_strategy = SH_DIV_INV_CALL; \
617 else if (! strcmp (sh_div_str, "inv:fp")) \
619 if (TARGET_FPU_ANY) \
620 sh_div_strategy = SH_DIV_INV_FP; \
622 sh_div_strategy = SH_DIV_INV; \
624 TARGET_CBRANCHDI4 = 0; \
626 /* -fprofile-arcs needs a working libgcov . In unified tree \
627 configurations with newlib, this requires to configure with \
628 --with-newlib --with-headers. But there is no way to check \
629 here we have a working libgcov, so just assume that we have. */\
631 warning (0, "profiling is still experimental for this target");\
635 /* Only the sh64-elf assembler fully supports .quad properly. */\
636 targetm.asm_out.aligned_op.di = NULL; \
637 targetm.asm_out.unaligned_op.di = NULL; \
641 if (! strcmp (sh_div_str, "call-div1")) \
642 sh_div_strategy = SH_DIV_CALL_DIV1; \
643 else if (! strcmp (sh_div_str, "call-fp") \
644 && (TARGET_FPU_DOUBLE \
645 || (TARGET_HARD_SH4 && TARGET_SH2E) \
646 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
647 sh_div_strategy = SH_DIV_CALL_FP; \
648 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
649 sh_div_strategy = SH_DIV_CALL_TABLE; \
651 /* Pick one that makes most sense for the target in general. \
652 It is not much good to use different functions depending \
653 on -Os, since then we'll end up with two different functions \
654 when some of the code is compiled for size, and some for \
657 /* SH4 tends to emphasize speed. */ \
658 if (TARGET_HARD_SH4) \
659 sh_div_strategy = SH_DIV_CALL_TABLE; \
660 /* These have their own way of doing things. */ \
661 else if (TARGET_SH2A) \
662 sh_div_strategy = SH_DIV_INTRINSIC; \
663 /* ??? Should we use the integer SHmedia function instead? */ \
664 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
665 sh_div_strategy = SH_DIV_CALL_FP; \
666 /* SH1 .. SH3 cores often go into small-footprint systems, so \
667 default to the smallest implementation available. */ \
668 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
669 sh_div_strategy = SH_DIV_CALL_TABLE; \
671 sh_div_strategy = SH_DIV_CALL_DIV1; \
674 TARGET_PRETEND_CMOVE = 0; \
675 if (sh_divsi3_libfunc[0]) \
676 ; /* User supplied - leave it alone. */ \
677 else if (TARGET_DIVIDE_CALL_FP) \
678 sh_divsi3_libfunc = "__sdivsi3_i4"; \
679 else if (TARGET_DIVIDE_CALL_TABLE) \
680 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
681 else if (TARGET_SH5) \
682 sh_divsi3_libfunc = "__sdivsi3_1"; \
684 sh_divsi3_libfunc = "__sdivsi3"; \
685 if (sh_branch_cost == -1) \
687 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
689 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
690 if (! VALID_REGISTER_P (regno)) \
691 sh_register_names[regno][0] = '\0'; \
693 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
694 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
695 sh_additional_register_names[regno][0] = '\0'; \
697 if (flag_omit_frame_pointer < 0) \
699 /* The debugging information is sufficient, \
700 but gdb doesn't implement this yet */ \
702 flag_omit_frame_pointer \
703 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
705 flag_omit_frame_pointer = 0; \
708 if ((flag_pic && ! TARGET_PREFERGOT) \
709 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
710 flag_no_function_cse = 1; \
712 if (SMALL_REGISTER_CLASSES) \
714 /* Never run scheduling before reload, since that can \
715 break global alloc, and generates slower code anyway due \
716 to the pressure on R0. */ \
717 /* Enable sched1 for SH4; ready queue will be reordered by \
718 the target hooks when pressure is high. We can not do this for \
719 SH3 and lower as they give spill failures for R0. */ \
720 if (!TARGET_HARD_SH4) \
721 flag_schedule_insns = 0; \
722 /* ??? Current exception handling places basic block boundaries \
723 after call_insns. It causes the high pressure on R0 and gives \
724 spill failures for R0 in reload. See PR 22553 and the thread \
726 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
727 else if (flag_exceptions) \
729 if (flag_schedule_insns == 1) \
730 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
731 flag_schedule_insns = 0; \
735 if (align_loops == 0) \
736 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
737 if (align_jumps == 0) \
738 align_jumps = 1 << CACHE_LOG; \
739 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
740 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
742 /* Allocation boundary (in *bytes*) for the code of a function. \
743 SH1: 32 bit alignment is faster, because instructions are always \
744 fetched as a pair from a longword boundary. \
745 SH2 .. SH5 : align to cache line start. */ \
746 if (align_functions == 0) \
748 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
749 /* The linker relaxation code breaks when a function contains \
750 alignments that are larger than that at the start of a \
751 compilation unit. */ \
755 = align_loops > align_jumps ? align_loops : align_jumps; \
757 /* Also take possible .long constants / mova tables int account. */\
760 if (align_functions < min_align) \
761 align_functions = min_align; \
765 /* Target machine storage layout. */
767 /* Define this if most significant bit is lowest numbered
768 in instructions that operate on numbered bit-fields. */
770 #define BITS_BIG_ENDIAN 0
772 /* Define this if most significant byte of a word is the lowest numbered. */
773 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
775 /* Define this if most significant word of a multiword number is the lowest
777 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
779 /* Define this to set the endianness to use in libgcc2.c, which can
780 not depend on target_flags. */
781 #if defined(__LITTLE_ENDIAN__)
782 #define LIBGCC2_WORDS_BIG_ENDIAN 0
784 #define LIBGCC2_WORDS_BIG_ENDIAN 1
787 #define MAX_BITS_PER_WORD 64
789 /* Width in bits of an `int'. We want just 32-bits, even if words are
791 #define INT_TYPE_SIZE 32
793 /* Width in bits of a `long'. */
794 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
796 /* Width in bits of a `long long'. */
797 #define LONG_LONG_TYPE_SIZE 64
799 /* Width in bits of a `long double'. */
800 #define LONG_DOUBLE_TYPE_SIZE 64
802 /* Width of a word, in units (bytes). */
803 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
804 #define MIN_UNITS_PER_WORD 4
806 /* Scaling factor for Dwarf data offsets for CFI information.
807 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
808 SHmedia; however, since we do partial register saves for the registers
809 visible to SHcompact, and for target registers for SHMEDIA32, we have
810 to allow saves that are only 4-byte aligned. */
811 #define DWARF_CIE_DATA_ALIGNMENT -4
813 /* Width in bits of a pointer.
814 See also the macro `Pmode' defined below. */
815 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
817 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
818 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
820 /* Boundary (in *bits*) on which stack pointer should be aligned. */
821 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
823 /* The log (base 2) of the cache line size, in bytes. Processors prior to
824 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
825 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
826 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
828 /* ABI given & required minimum allocation boundary (in *bits*) for the
829 code of a function. */
830 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
832 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
833 the vbit must go into the delta field of
834 pointers-to-member-functions. */
835 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
836 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
838 /* Alignment of field after `int : 0' in a structure. */
839 #define EMPTY_FIELD_BOUNDARY 32
841 /* No data type wants to be aligned rounder than this. */
842 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
844 /* The best alignment to use in cases where we have a choice. */
845 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
847 /* Make strings word-aligned so strcpy from constants will be faster. */
848 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
849 ((TREE_CODE (EXP) == STRING_CST \
850 && (ALIGN) < FASTEST_ALIGNMENT) \
851 ? FASTEST_ALIGNMENT : (ALIGN))
853 /* get_mode_alignment assumes complex values are always held in multiple
854 registers, but that is not the case on the SH; CQImode and CHImode are
855 held in a single integer register. SH5 also holds CSImode and SCmode
856 values in integer registers. This is relevant for argument passing on
857 SHcompact as we use a stack temp in order to pass CSImode by reference. */
858 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
859 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
860 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
861 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
862 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
864 /* Make arrays of chars word-aligned for the same reasons. */
865 #define DATA_ALIGNMENT(TYPE, ALIGN) \
866 (TREE_CODE (TYPE) == ARRAY_TYPE \
867 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
868 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
870 /* Number of bits which any structure or union's size must be a
871 multiple of. Each structure or union's size is rounded up to a
873 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
875 /* Set this nonzero if move instructions will actually fail to work
876 when given unaligned data. */
877 #define STRICT_ALIGNMENT 1
879 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
880 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
881 barrier_align (LABEL_AFTER_BARRIER)
883 #define LOOP_ALIGN(A_LABEL) \
884 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
885 ? 0 : sh_loop_align (A_LABEL))
887 #define LABEL_ALIGN(A_LABEL) \
889 (PREV_INSN (A_LABEL) \
890 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
891 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
892 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
893 /* explicit alignment insn in constant tables. */ \
894 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
897 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
898 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
900 /* The base two logarithm of the known minimum alignment of an insn length. */
901 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
902 (GET_CODE (A_INSN) == INSN \
903 ? 1 << TARGET_SHMEDIA \
904 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
905 ? 1 << TARGET_SHMEDIA \
908 /* Standard register usage. */
910 /* Register allocation for the Renesas calling convention:
916 r14 frame pointer/call saved
918 ap arg pointer (doesn't really exist, always eliminated)
919 pr subroutine return address
921 mach multiply/accumulate result, high part
922 macl multiply/accumulate result, low part.
923 fpul fp/int communication register
924 rap return address pointer register
926 fr1..fr3 scratch floating point registers
928 fr12..fr15 call saved floating point registers */
930 #define MAX_REGISTER_NAME_LENGTH 5
931 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
933 #define SH_REGISTER_NAMES_INITIALIZER \
935 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
936 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
937 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
938 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
939 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
940 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
941 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
942 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
943 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
944 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
945 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
946 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
947 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
948 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
949 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
950 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
951 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
952 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
953 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
957 #define REGNAMES_ARR_INDEX_1(index) \
958 (sh_register_names[index])
959 #define REGNAMES_ARR_INDEX_2(index) \
960 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
961 #define REGNAMES_ARR_INDEX_4(index) \
962 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
963 #define REGNAMES_ARR_INDEX_8(index) \
964 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
965 #define REGNAMES_ARR_INDEX_16(index) \
966 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
967 #define REGNAMES_ARR_INDEX_32(index) \
968 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
969 #define REGNAMES_ARR_INDEX_64(index) \
970 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
972 #define REGISTER_NAMES \
974 REGNAMES_ARR_INDEX_64 (0), \
975 REGNAMES_ARR_INDEX_64 (64), \
976 REGNAMES_ARR_INDEX_8 (128), \
977 REGNAMES_ARR_INDEX_8 (136), \
978 REGNAMES_ARR_INDEX_8 (144), \
979 REGNAMES_ARR_INDEX_2 (152) \
982 #define ADDREGNAMES_SIZE 32
983 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
984 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
985 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
987 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
989 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
990 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
991 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
992 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
995 #define ADDREGNAMES_REGNO(index) \
996 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
999 #define ADDREGNAMES_ARR_INDEX_1(index) \
1000 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1001 #define ADDREGNAMES_ARR_INDEX_2(index) \
1002 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1003 #define ADDREGNAMES_ARR_INDEX_4(index) \
1004 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1005 #define ADDREGNAMES_ARR_INDEX_8(index) \
1006 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1007 #define ADDREGNAMES_ARR_INDEX_16(index) \
1008 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1009 #define ADDREGNAMES_ARR_INDEX_32(index) \
1010 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1012 #define ADDITIONAL_REGISTER_NAMES \
1014 ADDREGNAMES_ARR_INDEX_32 (0) \
1017 /* Number of actual hardware registers.
1018 The hardware registers are assigned numbers for the compiler
1019 from 0 to just below FIRST_PSEUDO_REGISTER.
1020 All registers that the compiler knows about must be given numbers,
1021 even those that are not normally considered general registers. */
1023 /* There are many other relevant definitions in sh.md's md_constants. */
1025 #define FIRST_GENERAL_REG R0_REG
1026 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1027 #define FIRST_FP_REG DR0_REG
1028 #define LAST_FP_REG (FIRST_FP_REG + \
1029 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1030 #define FIRST_XD_REG XD0_REG
1031 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1032 #define FIRST_TARGET_REG TR0_REG
1033 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1035 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1037 #define FIRST_BANKED_REG R0_REG
1038 #define LAST_BANKED_REG R7_REG
1040 #define BANKED_REGISTER_P(REGNO) \
1041 IN_RANGE ((REGNO), \
1042 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1043 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1045 #define GENERAL_REGISTER_P(REGNO) \
1046 IN_RANGE ((REGNO), \
1047 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1048 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1050 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1051 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1052 || ((REGNO) == FRAME_POINTER_REGNUM))
1054 #define FP_REGISTER_P(REGNO) \
1055 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1057 #define XD_REGISTER_P(REGNO) \
1058 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1060 #define FP_OR_XD_REGISTER_P(REGNO) \
1061 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1063 #define FP_ANY_REGISTER_P(REGNO) \
1064 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1066 #define SPECIAL_REGISTER_P(REGNO) \
1067 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1068 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1070 #define TARGET_REGISTER_P(REGNO) \
1071 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1073 #define SHMEDIA_REGISTER_P(REGNO) \
1074 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1075 || TARGET_REGISTER_P (REGNO))
1077 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1078 that should be fixed. */
1079 #define VALID_REGISTER_P(REGNO) \
1080 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1081 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1082 || (REGNO) == FRAME_POINTER_REGNUM \
1083 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1084 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1086 /* The mode that should be generally used to store a register by
1087 itself in the stack, or to load it back. */
1088 #define REGISTER_NATURAL_MODE(REGNO) \
1089 (FP_REGISTER_P (REGNO) ? SFmode \
1090 : XD_REGISTER_P (REGNO) ? DFmode \
1091 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1095 #define FIRST_PSEUDO_REGISTER 154
1097 /* Don't count soft frame pointer. */
1098 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1100 /* 1 for registers that have pervasive standard uses
1101 and are not available for the register allocator.
1103 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1104 It is 32 bits wide for SH2. */
1106 #define FIXED_REGISTERS \
1108 /* Regular registers. */ \
1109 0, 0, 0, 0, 0, 0, 0, 0, \
1110 0, 0, 0, 0, 0, 0, 0, 1, \
1111 /* r16 is reserved, r18 is the former pr. */ \
1112 1, 0, 0, 0, 0, 0, 0, 0, \
1113 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1114 /* r26 is a global variable data pointer; r27 is for constants. */ \
1115 1, 1, 1, 1, 0, 0, 0, 0, \
1116 0, 0, 0, 0, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 1, \
1120 /* FP registers. */ \
1121 0, 0, 0, 0, 0, 0, 0, 0, \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 0, 0, 0, 0, 0, 0, 0, 0, \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, \
1128 0, 0, 0, 0, 0, 0, 0, 0, \
1129 /* Branch target registers. */ \
1130 0, 0, 0, 0, 0, 0, 0, 0, \
1131 /* XD registers. */ \
1132 0, 0, 0, 0, 0, 0, 0, 0, \
1133 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1134 1, 1, 1, 1, 1, 1, 0, 1, \
1139 /* 1 for registers not available across function calls.
1140 These must include the FIXED_REGISTERS and also any
1141 registers that can be used without being saved.
1142 The latter must include the registers where values are returned
1143 and the register where structure-value addresses are passed.
1144 Aside from that, you can include as many other registers as you like. */
1146 #define CALL_USED_REGISTERS \
1148 /* Regular registers. */ \
1149 1, 1, 1, 1, 1, 1, 1, 1, \
1150 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1151 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1152 across SH5 function calls. */ \
1153 0, 0, 0, 0, 0, 0, 0, 1, \
1154 1, 1, 1, 1, 1, 1, 1, 1, \
1155 1, 1, 1, 1, 0, 0, 0, 0, \
1156 0, 0, 0, 0, 1, 1, 1, 1, \
1157 1, 1, 1, 1, 0, 0, 0, 0, \
1158 0, 0, 0, 0, 0, 0, 0, 0, \
1159 0, 0, 0, 0, 1, 1, 1, 1, \
1160 /* FP registers. */ \
1161 1, 1, 1, 1, 1, 1, 1, 1, \
1162 1, 1, 1, 1, 0, 0, 0, 0, \
1163 1, 1, 1, 1, 1, 1, 1, 1, \
1164 1, 1, 1, 1, 1, 1, 1, 1, \
1165 1, 1, 1, 1, 0, 0, 0, 0, \
1166 0, 0, 0, 0, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 /* Branch target registers. */ \
1170 1, 1, 1, 1, 1, 0, 0, 0, \
1171 /* XD registers. */ \
1172 1, 1, 1, 1, 1, 1, 0, 0, \
1173 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1174 1, 1, 1, 1, 1, 1, 1, 1, \
1179 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1180 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1181 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1183 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1184 across SHcompact function calls. We can't tell whether a called
1185 function is SHmedia or SHcompact, so we assume it may be when
1186 compiling SHmedia code with the 32-bit ABI, since that's the only
1187 ABI that can be linked with SHcompact code. */
1188 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1190 && GET_MODE_SIZE (MODE) > 4 \
1191 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1192 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1193 || TARGET_REGISTER_P (REGNO) \
1194 || (REGNO) == PR_MEDIA_REG))
1196 /* Return number of consecutive hard regs needed starting at reg REGNO
1197 to hold something of mode MODE.
1198 This is ordinarily the length in words of a value of mode MODE
1199 but can be less for certain modes in special long registers.
1201 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1203 #define HARD_REGNO_NREGS(REGNO, MODE) \
1204 (XD_REGISTER_P (REGNO) \
1205 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1206 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1207 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1208 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1210 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1211 We can allow any mode in any general register. The special registers
1212 only allow SImode. Don't allow any mode in the PR. */
1214 /* We cannot hold DCmode values in the XD registers because alter_reg
1215 handles subregs of them incorrectly. We could work around this by
1216 spacing the XD registers like the DR registers, but this would require
1217 additional memory in every compilation to hold larger register vectors.
1218 We could hold SFmode / SCmode values in XD registers, but that
1219 would require a tertiary reload when reloading from / to memory,
1220 and a secondary reload to reload from / to general regs; that
1221 seems to be a loosing proposition. */
1222 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1223 it won't be ferried through GP registers first. */
1224 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1225 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1226 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1227 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1229 : (MODE) == V2SFmode \
1230 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1231 || GENERAL_REGISTER_P (REGNO)) \
1232 : (MODE) == V4SFmode \
1233 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1234 || GENERAL_REGISTER_P (REGNO)) \
1235 : (MODE) == V16SFmode \
1237 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1238 : (REGNO) == FIRST_XD_REG) \
1239 : FP_REGISTER_P (REGNO) \
1240 ? ((MODE) == SFmode || (MODE) == SImode \
1241 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1242 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1243 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1244 || (MODE) == V2SFmode || (MODE) == TImode))) \
1245 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1246 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1247 && (MODE) == TImode \
1248 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1249 : XD_REGISTER_P (REGNO) \
1250 ? (MODE) == DFmode \
1251 : TARGET_REGISTER_P (REGNO) \
1252 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1253 : (REGNO) == PR_REG ? (MODE) == SImode \
1254 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1257 /* Value is 1 if it is a good idea to tie two pseudo registers
1258 when one has mode MODE1 and one has mode MODE2.
1259 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1260 for any hard reg, then this must be 0 for correct output.
1261 That's the case for xd registers: we don't hold SFmode values in
1262 them, so we can't tie an SFmode pseudos with one in another
1263 floating-point mode. */
1265 #define MODES_TIEABLE_P(MODE1, MODE2) \
1266 ((MODE1) == (MODE2) \
1267 || (TARGET_SHMEDIA \
1268 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1269 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1270 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1271 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1272 && (GET_MODE_SIZE (MODE2) <= 4)) \
1273 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1275 /* A C expression that is nonzero if hard register NEW_REG can be
1276 considered for use as a rename register for OLD_REG register */
1278 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1279 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1281 /* Specify the registers used for certain standard purposes.
1282 The values of these macros are register numbers. */
1284 /* Define this if the program counter is overloaded on a register. */
1285 /* #define PC_REGNUM 15*/
1287 /* Register to use for pushing function arguments. */
1288 #define STACK_POINTER_REGNUM SP_REG
1290 /* Base register for access to local variables of the function. */
1291 #define HARD_FRAME_POINTER_REGNUM FP_REG
1293 /* Base register for access to local variables of the function. */
1294 #define FRAME_POINTER_REGNUM 153
1296 /* Fake register that holds the address on the stack of the
1297 current function's return address. */
1298 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1300 /* Register to hold the addressing base for position independent
1301 code access to data items. */
1302 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1304 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1306 /* Value should be nonzero if functions must have frame pointers.
1307 Zero means the frame pointer need not be set up (and parms may be accessed
1308 via the stack pointer) in functions that seem suitable. */
1310 #define FRAME_POINTER_REQUIRED 0
1312 /* Definitions for register eliminations.
1314 We have three registers that can be eliminated on the SH. First, the
1315 frame pointer register can often be eliminated in favor of the stack
1316 pointer register. Secondly, the argument pointer register can always be
1317 eliminated; it is replaced with either the stack or frame pointer.
1318 Third, there is the return address pointer, which can also be replaced
1319 with either the stack or the frame pointer. */
1321 /* This is an array of structures. Each structure initializes one pair
1322 of eliminable registers. The "from" register number is given first,
1323 followed by "to". Eliminations of the same "from" register are listed
1324 in order of preference. */
1326 /* If you add any registers here that are not actually hard registers,
1327 and that have any alternative of elimination that doesn't always
1328 apply, you need to amend calc_live_regs to exclude it, because
1329 reload spills all eliminable registers where it sees an
1330 can_eliminate == 0 entry, thus making them 'live' .
1331 If you add any hard registers that can be eliminated in different
1332 ways, you have to patch reload to spill them only when all alternatives
1333 of elimination fail. */
1335 #define ELIMINABLE_REGS \
1336 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1337 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1338 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1339 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1340 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1341 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1342 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1344 /* Given FROM and TO register numbers, say whether this elimination
1346 #define CAN_ELIMINATE(FROM, TO) \
1347 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1349 /* Define the offset between two registers, one to be eliminated, and the other
1350 its replacement, at the start of a routine. */
1352 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1353 OFFSET = initial_elimination_offset ((FROM), (TO))
1355 /* Base register for access to arguments of the function. */
1356 #define ARG_POINTER_REGNUM AP_REG
1358 /* Register in which the static-chain is passed to a function. */
1359 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1361 /* Don't default to pcc-struct-return, because we have already specified
1362 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1365 #define DEFAULT_PCC_STRUCT_RETURN 0
1367 #define SHMEDIA_REGS_STACK_ADJUST() \
1368 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1369 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1370 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1374 /* Define the classes of registers for register constraints in the
1375 machine description. Also define ranges of constants.
1377 One of the classes must always be named ALL_REGS and include all hard regs.
1378 If there is more than one class, another class must be named NO_REGS
1379 and contain no registers.
1381 The name GENERAL_REGS must be the name of a class (or an alias for
1382 another name such as ALL_REGS). This is the class of registers
1383 that is allowed by "g" or "r" in a register constraint.
1384 Also, registers outside this class are allocated only when
1385 instructions express preferences for them.
1387 The classes must be numbered in nondecreasing order; that is,
1388 a larger-numbered class must never be contained completely
1389 in a smaller-numbered class.
1391 For any two classes, it is very desirable that there be another
1392 class that represents their union. */
1394 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1395 be used as the destination of some of the arithmetic ops. There are
1396 also some special purpose registers; the T bit register, the
1397 Procedure Return Register and the Multiply Accumulate Registers. */
1398 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1399 reg_class_subunion. We don't want to have an actual union class
1400 of these, because it would only be used when both classes are calculated
1401 to give the same cost, but there is only one FPUL register.
1402 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1403 applying to the actual instruction alternative considered. E.g., the
1404 y/r alternative of movsi_ie is considered to have no more cost that
1405 the r/r alternative, which is patently untrue. */
1429 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1431 /* Give names of register classes as strings for dump file. */
1432 #define REG_CLASS_NAMES \
1447 "GENERAL_FP_REGS", \
1448 "GENERAL_DF_REGS", \
1453 /* Define which registers fit in which classes.
1454 This is an initializer for a vector of HARD_REG_SET
1455 of length N_REG_CLASSES. */
1457 #define REG_CLASS_CONTENTS \
1460 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1462 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1464 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1466 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1468 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1470 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1471 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1472 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1473 /* GENERAL_REGS: */ \
1474 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1476 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1478 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1479 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1480 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1482 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1484 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1485 /* GENERAL_FP_REGS: */ \
1486 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1487 /* GENERAL_DF_REGS: */ \
1488 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1489 /* TARGET_REGS: */ \
1490 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1492 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1495 /* The same information, inverted:
1496 Return the class number of the smallest class containing
1497 reg number REGNO. This could be a conditional expression
1498 or could index an array. */
1500 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1501 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1503 /* When defined, the compiler allows registers explicitly used in the
1504 rtl to be used as spill registers but prevents the compiler from
1505 extending the lifetime of these registers. */
1507 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1509 /* The order in which register should be allocated. */
1510 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1511 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1512 spilled or used otherwise, we better have the FP_REGS allocated first. */
1513 #define REG_ALLOC_ORDER \
1514 {/* Caller-saved FPRs */ \
1515 65, 66, 67, 68, 69, 70, 71, 64, \
1516 72, 73, 74, 75, 80, 81, 82, 83, \
1517 84, 85, 86, 87, 88, 89, 90, 91, \
1518 92, 93, 94, 95, 96, 97, 98, 99, \
1519 /* Callee-saved FPRs */ \
1520 76, 77, 78, 79,100,101,102,103, \
1521 104,105,106,107,108,109,110,111, \
1522 112,113,114,115,116,117,118,119, \
1523 120,121,122,123,124,125,126,127, \
1524 136,137,138,139,140,141,142,143, \
1526 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1527 1, 2, 3, 7, 6, 5, 4, 0, \
1528 8, 9, 17, 19, 20, 21, 22, 23, \
1529 36, 37, 38, 39, 40, 41, 42, 43, \
1531 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1532 10, 11, 12, 13, 14, 18, \
1533 /* SH5 callee-saved GPRs */ \
1534 28, 29, 30, 31, 32, 33, 34, 35, \
1535 44, 45, 46, 47, 48, 49, 50, 51, \
1536 52, 53, 54, 55, 56, 57, 58, 59, \
1538 /* SH5 branch target registers */ \
1539 128,129,130,131,132,133,134,135, \
1540 /* Fixed registers */ \
1541 15, 16, 24, 25, 26, 27, 63,144, \
1542 145,146,147,148,149,152,153 }
1544 /* The class value for index registers, and the one for base regs. */
1545 #define INDEX_REG_CLASS \
1546 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1547 #define BASE_REG_CLASS GENERAL_REGS
1549 /* Defines for sh.md and constraints.md. */
1551 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1552 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1553 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1554 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1555 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1556 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1557 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1558 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1560 #define CONST_OK_FOR_J16(VALUE) \
1561 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1562 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1564 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1565 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1567 /* Given an rtx X being reloaded into a reg required to be
1568 in class CLASS, return the class of reg to actually use.
1569 In general this is just CLASS; but on some machines
1570 in some cases it is preferable to use a more restrictive class. */
1572 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1573 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1574 && (GET_CODE (X) == CONST_DOUBLE \
1575 || GET_CODE (X) == SYMBOL_REF \
1576 || PIC_DIRECT_ADDR_P (X)) \
1581 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1582 ((((REGCLASS_HAS_FP_REG (CLASS) \
1583 && (GET_CODE (X) == REG \
1584 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1585 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1586 && TARGET_FMOVD)))) \
1587 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1588 && GET_CODE (X) == REG \
1589 && FP_REGISTER_P (REGNO (X)))) \
1590 && ! TARGET_SHMEDIA \
1591 && ((MODE) == SFmode || (MODE) == SImode)) \
1593 : (((CLASS) == FPUL_REGS \
1594 || (REGCLASS_HAS_FP_REG (CLASS) \
1595 && ! TARGET_SHMEDIA && MODE == SImode)) \
1596 && (GET_CODE (X) == MEM \
1597 || (GET_CODE (X) == REG \
1598 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1599 || REGNO (X) == T_REG \
1600 || system_reg_operand (X, VOIDmode))))) \
1602 : (((CLASS) == TARGET_REGS \
1603 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1604 && !satisfies_constraint_Csy (X) \
1605 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1607 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1608 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1609 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1611 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1612 && TARGET_REGISTER_P (REGNO (X))) \
1613 ? GENERAL_REGS : (ELSE))
1615 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1616 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1618 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1619 ((REGCLASS_HAS_FP_REG (CLASS) \
1620 && ! TARGET_SHMEDIA \
1621 && immediate_operand ((X), (MODE)) \
1622 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1623 && (MODE) == SFmode && fldi_ok ())) \
1625 : ((CLASS) == FPUL_REGS \
1626 && ((GET_CODE (X) == REG \
1627 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1628 || REGNO (X) == T_REG)) \
1629 || GET_CODE (X) == PLUS)) \
1631 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1632 ? (satisfies_constraint_I08 (X) \
1635 : ((CLASS) == FPSCR_REGS \
1636 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1637 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1639 : (REGCLASS_HAS_FP_REG (CLASS) \
1641 && immediate_operand ((X), (MODE)) \
1642 && (X) != CONST0_RTX (GET_MODE (X)) \
1643 && GET_MODE (X) != V4SFmode) \
1645 : (((MODE) == QImode || (MODE) == HImode) \
1646 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1648 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1649 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1651 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1654 /* Return the maximum number of consecutive registers
1655 needed to represent mode MODE in a register of class CLASS.
1657 If TARGET_SHMEDIA, we need two FP registers per word.
1658 Otherwise we will need at most one register per word. */
1659 #define CLASS_MAX_NREGS(CLASS, MODE) \
1661 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1662 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1663 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1665 /* If defined, gives a class of registers that cannot be used as the
1666 operand of a SUBREG that changes the mode of the object illegally. */
1667 /* ??? We need to renumber the internal numbers for the frnn registers
1668 when in little endian in order to allow mode size changes. */
1670 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1671 sh_cannot_change_mode_class (FROM, TO, CLASS)
1673 /* Stack layout; function entry, exit and calling. */
1675 /* Define the number of registers that can hold parameters.
1676 These macros are used only in other macro definitions below. */
1678 #define NPARM_REGS(MODE) \
1679 (TARGET_FPU_ANY && (MODE) == SFmode \
1680 ? (TARGET_SH5 ? 12 : 8) \
1681 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1682 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1683 ? (TARGET_SH5 ? 12 : 8) \
1684 : (TARGET_SH5 ? 8 : 4))
1686 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1687 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1689 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1690 #define FIRST_FP_RET_REG FIRST_FP_REG
1692 /* Define this if pushing a word on the stack
1693 makes the stack pointer a smaller address. */
1694 #define STACK_GROWS_DOWNWARD
1696 /* Define this macro to nonzero if the addresses of local variable slots
1697 are at negative offsets from the frame pointer. */
1698 #define FRAME_GROWS_DOWNWARD 1
1700 /* Offset from the frame pointer to the first local variable slot to
1702 #define STARTING_FRAME_OFFSET 0
1704 /* If we generate an insn to push BYTES bytes,
1705 this says how many the stack pointer really advances by. */
1706 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1707 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1708 do correct alignment. */
1710 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1713 /* Offset of first parameter from the argument pointer register value. */
1714 #define FIRST_PARM_OFFSET(FNDECL) 0
1716 /* Value is the number of byte of arguments automatically
1717 popped when returning from a subroutine call.
1718 FUNDECL is the declaration node of the function (as a tree),
1719 FUNTYPE is the data type of the function (as a tree),
1720 or for a library call it is an identifier node for the subroutine name.
1721 SIZE is the number of bytes of arguments passed on the stack.
1723 On the SH, the caller does not pop any of its arguments that were passed
1725 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1727 /* Value is the number of bytes of arguments automatically popped when
1728 calling a subroutine.
1729 CUM is the accumulated argument list.
1731 On SHcompact, the call trampoline pops arguments off the stack. */
1732 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1734 /* Some subroutine macros specific to this machine. */
1736 #define BASE_RETURN_VALUE_REG(MODE) \
1737 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1738 ? FIRST_FP_RET_REG \
1739 : TARGET_FPU_ANY && (MODE) == SCmode \
1740 ? FIRST_FP_RET_REG \
1741 : (TARGET_FPU_DOUBLE \
1742 && ((MODE) == DFmode || (MODE) == SFmode \
1743 || (MODE) == DCmode || (MODE) == SCmode )) \
1744 ? FIRST_FP_RET_REG \
1747 #define BASE_ARG_REG(MODE) \
1748 ((TARGET_SH2E && ((MODE) == SFmode)) \
1749 ? FIRST_FP_PARM_REG \
1750 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1751 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1752 ? FIRST_FP_PARM_REG \
1755 /* Define how to find the value returned by a function.
1756 VALTYPE is the data type of the value (as a tree).
1757 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1758 otherwise, FUNC is 0.
1759 For the SH, this is like LIBCALL_VALUE, except that we must change the
1760 mode like PROMOTE_MODE does.
1761 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1762 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1764 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1766 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1767 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1768 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1769 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1770 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1771 || TREE_CODE (VALTYPE) == REAL_TYPE \
1772 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1773 && sh_promote_prototypes (VALTYPE) \
1774 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1775 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1777 /* Define how to find the value returned by a library function
1778 assuming the value has mode MODE. */
1779 #define LIBCALL_VALUE(MODE) \
1780 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1782 /* 1 if N is a possible register number for a function value. */
1783 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1784 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1785 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1787 /* 1 if N is a possible register number for function argument passing. */
1788 /* ??? There are some callers that pass REGNO as int, and others that pass
1789 it as unsigned. We get warnings unless we do casts everywhere. */
1790 #define FUNCTION_ARG_REGNO_P(REGNO) \
1791 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1792 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1793 || (TARGET_FPU_ANY \
1794 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1795 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1796 + NPARM_REGS (SFmode))))
1798 /* Define a data type for recording info about an argument list
1799 during the scan of that argument list. This data type should
1800 hold all necessary information about the function itself
1801 and about the args processed so far, enough to enable macros
1802 such as FUNCTION_ARG to determine where the next arg should go.
1804 On SH, this is a single integer, which is a number of words
1805 of arguments scanned so far (including the invisible argument,
1806 if any, which holds the structure-value-address).
1807 Thus NARGREGS or more means all following args should go on the stack. */
1809 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1813 /* Nonzero if a prototype is available for the function. */
1815 /* The number of an odd floating-point register, that should be used
1816 for the next argument of type float. */
1817 int free_single_fp_reg;
1818 /* Whether we're processing an outgoing function call. */
1820 /* The number of general-purpose registers that should have been
1821 used to pass partial arguments, that are passed totally on the
1822 stack. On SHcompact, a call trampoline will pop them off the
1823 stack before calling the actual function, and, if the called
1824 function is implemented in SHcompact mode, the incoming arguments
1825 decoder will push such arguments back onto the stack. For
1826 incoming arguments, STACK_REGS also takes into account other
1827 arguments passed by reference, that the decoder will also push
1830 /* The number of general-purpose registers that should have been
1831 used to pass arguments, if the arguments didn't have to be passed
1834 /* Set as by shcompact_byref if the current argument is to be passed
1838 /* call_cookie is a bitmask used by call expanders, as well as
1839 function prologue and epilogues, to allow SHcompact to comply
1840 with the SH5 32-bit ABI, that requires 64-bit registers to be
1841 used even though only the lower 32-bit half is visible in
1842 SHcompact mode. The strategy is to call SHmedia trampolines.
1844 The alternatives for each of the argument-passing registers are
1845 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1846 contents from the address in it; (d) add 8 to it, storing the
1847 result in the next register, then (c); (e) copy it from some
1848 floating-point register,
1850 Regarding copies from floating-point registers, r2 may only be
1851 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1852 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1853 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1854 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1857 The bit mask is structured as follows:
1859 - 1 bit to tell whether to set up a return trampoline.
1861 - 3 bits to count the number consecutive registers to pop off the
1864 - 4 bits for each of r9, r8, r7 and r6.
1866 - 3 bits for each of r5, r4, r3 and r2.
1868 - 3 bits set to 0 (the most significant ones)
1871 1098 7654 3210 9876 5432 1098 7654 3210
1872 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1873 2223 3344 4555 6666 7777 8888 9999 SSS-
1875 - If F is set, the register must be copied from an FP register,
1876 whose number is encoded in the remaining bits.
1878 - Else, if L is set, the register must be loaded from the address
1879 contained in it. If the P bit is *not* set, the address of the
1880 following dword should be computed first, and stored in the
1883 - Else, if P is set, the register alone should be popped off the
1886 - After all this processing, the number of registers represented
1887 in SSS will be popped off the stack. This is an optimization
1888 for pushing/popping consecutive registers, typically used for
1889 varargs and large arguments partially passed in registers.
1891 - If T is set, a return trampoline will be set up for 64-bit
1892 return values to be split into 2 32-bit registers. */
1895 /* This is set to nonzero when the call in question must use the Renesas ABI,
1896 even without the -mrenesas option. */
1900 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1901 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1902 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1903 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1904 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1905 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1906 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1907 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1908 #define CALL_COOKIE_INT_REG(REG, VAL) \
1909 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1910 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1911 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1913 #define CUMULATIVE_ARGS struct sh_args
1915 #define GET_SH_ARG_CLASS(MODE) \
1916 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1918 /* There's no mention of complex float types in the SH5 ABI, so we
1919 should presumably handle them as aggregate types. */ \
1920 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1922 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1923 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1924 ? SH_ARG_FLOAT : SH_ARG_INT)
1926 #define ROUND_ADVANCE(SIZE) \
1927 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1929 /* Round a register number up to a proper boundary for an arg of mode
1932 The SH doesn't care about double alignment, so we only
1933 round doubles to even regs when asked to explicitly. */
1935 #define ROUND_REG(CUM, MODE) \
1936 (((TARGET_ALIGN_DOUBLE \
1937 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1938 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1939 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1940 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1941 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1942 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1944 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1945 for a call to a function whose data type is FNTYPE.
1946 For a library call, FNTYPE is 0.
1948 On SH, the offset always starts at 0: the first parm reg is always
1949 the same reg for a given argument class.
1951 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1953 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1954 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1956 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1957 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1959 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1960 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1961 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1962 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1964 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1965 This macro is only used in this file. */
1967 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1969 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1970 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1971 || ! (AGGREGATE_TYPE_P (TYPE) \
1972 || (!TARGET_FPU_ANY \
1973 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1974 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1975 && ! (CUM).force_mem \
1977 ? ((MODE) == BLKmode \
1978 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1979 + int_size_in_bytes (TYPE)) \
1980 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1981 : ((ROUND_REG((CUM), (MODE)) \
1982 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1983 <= NPARM_REGS (MODE))) \
1984 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1986 /* By accident we got stuck with passing SCmode on SH4 little endian
1987 in two registers that are nominally successive - which is different from
1988 two single SFmode values, where we take endianness translation into
1989 account. That does not work at all if an odd number of registers is
1990 already in use, so that got fixed, but library functions are still more
1991 likely to use complex numbers without mixing them with SFmode arguments
1992 (which in C would have to be structures), so for the sake of ABI
1993 compatibility the way SCmode values are passed when an even number of
1994 FP registers is in use remains different from a pair of SFmode values for
1997 foo (double); a: fr5,fr4
1998 foo (float a, float b); a: fr5 b: fr4
1999 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2000 this should be the other way round...
2001 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2002 #define FUNCTION_ARG_SCmode_WART 1
2004 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2005 register in SHcompact mode, it must be padded in the most
2006 significant end. This means that passing it by reference wouldn't
2007 pad properly on a big-endian machine. In this particular case, we
2008 pass this argument on the stack, in a way that the call trampoline
2009 will load its value into the appropriate register. */
2010 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2011 ((MODE) == BLKmode \
2012 && TARGET_SHCOMPACT \
2013 && ! TARGET_LITTLE_ENDIAN \
2014 && int_size_in_bytes (TYPE) > 4 \
2015 && int_size_in_bytes (TYPE) < 8)
2017 /* Minimum alignment for an argument to be passed by callee-copy
2018 reference. We need such arguments to be aligned to 8 byte
2019 boundaries, because they'll be loaded using quad loads. */
2020 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2022 /* The SH5 ABI requires floating-point arguments to be passed to
2023 functions without a prototype in both an FP register and a regular
2024 register or the stack. When passing the argument in both FP and
2025 general-purpose registers, list the FP register first. */
2026 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2032 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2033 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2034 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2039 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2040 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2041 + (CUM).arg_count[(int) SH_ARG_INT]) \
2042 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2043 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2046 /* The SH5 ABI requires regular registers or stack slots to be
2047 reserved for floating-point arguments. Registers are taken care of
2048 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2049 Unfortunately, there's no way to just reserve a stack slot, so
2050 we'll end up needlessly storing a copy of the argument in the
2051 stack. For incoming arguments, however, the PARALLEL will be
2052 optimized to the register-only form, and the value in the stack
2053 slot won't be used at all. */
2054 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2055 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2056 ? gen_rtx_REG ((MODE), (REG)) \
2057 : gen_rtx_PARALLEL ((MODE), \
2060 (VOIDmode, NULL_RTX, \
2063 (VOIDmode, gen_rtx_REG ((MODE), \
2067 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2069 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2070 || (MODE) == DCmode) \
2071 && ((CUM).arg_count[(int) SH_ARG_INT] \
2072 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2073 : GET_MODE_SIZE (MODE)) \
2074 + 7) / 8) > NPARM_REGS (SImode))
2076 /* Perform any needed actions needed for a function that is receiving a
2077 variable number of arguments. */
2079 /* Implement `va_start' for varargs and stdarg. */
2080 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2081 sh_va_start (valist, nextarg)
2083 /* Call the function profiler with a given profile label.
2084 We use two .aligns, so as to make sure that both the .long is aligned
2085 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2086 from the trapa instruction. */
2088 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2090 if (TARGET_SHMEDIA) \
2092 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2093 fprintf((STREAM), "\ttrapa\tr0\n"); \
2094 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2098 fprintf((STREAM), "\t.align\t2\n"); \
2099 fprintf((STREAM), "\ttrapa\t#33\n"); \
2100 fprintf((STREAM), "\t.align\t2\n"); \
2101 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2105 /* Define this macro if the code for function profiling should come
2106 before the function prologue. Normally, the profiling code comes
2109 #define PROFILE_BEFORE_PROLOGUE
2111 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2112 the stack pointer does not matter. The value is tested only in
2113 functions that have frame pointers.
2114 No definition is equivalent to always zero. */
2116 #define EXIT_IGNORE_STACK 1
2119 On the SH, the trampoline looks like
2120 2 0002 D202 mov.l l2,r2
2121 1 0000 D301 mov.l l1,r3
2124 5 0008 00000000 l1: .long area
2125 6 000c 00000000 l2: .long function */
2127 /* Length in units of the trampoline for entering a nested function. */
2128 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2130 /* Alignment required for a trampoline in bits . */
2131 #define TRAMPOLINE_ALIGNMENT \
2132 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2133 : TARGET_SHMEDIA ? 256 : 64)
2135 /* Emit RTL insns to initialize the variable parts of a trampoline.
2136 FNADDR is an RTX for the address of the function's pure code.
2137 CXT is an RTX for the static chain value for the function. */
2139 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2140 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2142 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2144 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2146 if (TARGET_SHMEDIA) \
2147 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2148 gen_reg_rtx (Pmode), 0, \
2152 /* A C expression whose value is RTL representing the value of the return
2153 address for the frame COUNT steps up from the current frame.
2154 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2155 can ignore COUNT. */
2157 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2158 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2160 /* A C expression whose value is RTL representing the location of the
2161 incoming return address at the beginning of any function, before the
2162 prologue. This RTL is either a REG, indicating that the return
2163 value is saved in REG, or a MEM representing a location in
2165 #define INCOMING_RETURN_ADDR_RTX \
2166 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2168 /* Addressing modes, and classification of registers for them. */
2169 #define HAVE_POST_INCREMENT TARGET_SH1
2170 #define HAVE_PRE_DECREMENT TARGET_SH1
2172 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2174 #define USE_LOAD_PRE_DECREMENT(mode) 0
2175 #define USE_STORE_POST_INCREMENT(mode) 0
2176 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2179 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2180 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2181 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2183 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2184 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2185 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2187 /* Macros to check register numbers against specific register classes. */
2189 /* These assume that REGNO is a hard or pseudo reg number.
2190 They give nonzero only if REGNO is a hard reg of the suitable class
2191 or a pseudo reg currently allocated to a suitable hard reg.
2192 Since they use reg_renumber, they are safe only once reg_renumber
2193 has been allocated, which happens in local-alloc.c. */
2195 #define REGNO_OK_FOR_BASE_P(REGNO) \
2196 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2197 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2198 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2200 ? (GENERAL_REGISTER_P (REGNO) \
2201 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2202 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2204 /* Maximum number of registers that can appear in a valid memory
2207 #define MAX_REGS_PER_ADDRESS 2
2209 /* Recognize any constant value that is a valid address. */
2211 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2213 /* Nonzero if the constant value X is a legitimate general operand. */
2214 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2216 #define LEGITIMATE_CONSTANT_P(X) \
2218 ? ((GET_MODE (X) != DFmode \
2219 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2220 || (X) == CONST0_RTX (GET_MODE (X)) \
2221 || ! TARGET_SHMEDIA_FPU \
2222 || TARGET_SHMEDIA64) \
2223 : (GET_CODE (X) != CONST_DOUBLE \
2224 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2225 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2227 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2228 and check its validity for a certain class.
2229 We have two alternate definitions for each of them.
2230 The usual definition accepts all pseudo regs; the other rejects
2231 them unless they have been allocated suitable hard regs.
2232 The symbol REG_OK_STRICT causes the latter definition to be used. */
2234 #ifndef REG_OK_STRICT
2236 /* Nonzero if X is a hard reg that can be used as a base reg
2237 or if it is a pseudo reg. */
2238 #define REG_OK_FOR_BASE_P(X) \
2239 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2241 /* Nonzero if X is a hard reg that can be used as an index
2242 or if it is a pseudo reg. */
2243 #define REG_OK_FOR_INDEX_P(X) \
2244 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2245 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2247 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2248 or if X is a pseudo reg. */
2249 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2250 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2251 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2255 /* Nonzero if X is a hard reg that can be used as a base reg. */
2256 #define REG_OK_FOR_BASE_P(X) \
2257 REGNO_OK_FOR_BASE_P (REGNO (X))
2259 /* Nonzero if X is a hard reg that can be used as an index. */
2260 #define REG_OK_FOR_INDEX_P(X) \
2261 REGNO_OK_FOR_INDEX_P (REGNO (X))
2263 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2264 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2265 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2269 /* Macros for extra constraints. */
2271 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2272 ((GET_CODE ((OP)) == LABEL_REF) \
2273 || (GET_CODE ((OP)) == CONST \
2274 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2275 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2276 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2278 #define IS_LITERAL_OR_SYMBOLIC_S16_P(OP) \
2279 (GET_CODE ((OP)) == SIGN_EXTEND \
2280 && (GET_MODE ((OP)) == DImode \
2281 || GET_MODE ((OP)) == SImode) \
2282 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2283 && GET_MODE (XEXP ((OP), 0)) == HImode \
2284 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2285 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2286 && (MOVI_SHORI_BASE_OPERAND_P \
2287 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2288 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2290 #define IS_LITERAL_OR_SYMBOLIC_U16_P(OP) \
2291 (GET_CODE ((OP)) == ZERO_EXTEND \
2292 && (GET_MODE ((OP)) == DImode \
2293 || GET_MODE ((OP)) == SImode) \
2294 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2295 && GET_MODE (XEXP ((OP), 0)) == HImode \
2296 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2297 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2298 && (MOVI_SHORI_BASE_OPERAND_P \
2299 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2300 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2302 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2304 && GET_CODE (OP) != CONST_INT \
2305 && GET_CODE (OP) != CONST_DOUBLE \
2307 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2308 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2309 && GET_CODE (OP) != LABEL_REF)))
2311 /* Check whether OP is a datalabel unspec. */
2312 #define DATALABEL_REF_NO_CONST_P(OP) \
2313 (GET_CODE (OP) == UNSPEC \
2314 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2315 && XVECLEN ((OP), 0) == 1 \
2316 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2318 #define GOT_ENTRY_P(OP) \
2319 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2320 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2322 #define GOTPLT_ENTRY_P(OP) \
2323 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2324 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2326 #define UNSPEC_GOTOFF_P(OP) \
2327 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2329 #define GOTOFF_P(OP) \
2330 (GET_CODE (OP) == CONST \
2331 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2332 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2333 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2334 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2336 #define PIC_ADDR_P(OP) \
2337 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2338 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2340 #define PIC_OFFSET_P(OP) \
2342 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2343 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2345 #define PIC_DIRECT_ADDR_P(OP) \
2346 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2348 #define NON_PIC_REFERENCE_P(OP) \
2349 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2350 || (GET_CODE (OP) == CONST \
2351 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2352 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2353 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2354 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2355 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2356 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2357 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2358 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2360 #define PIC_REFERENCE_P(OP) \
2361 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2362 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2364 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2366 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2367 || PIC_OFFSET_P (OP)) \
2368 : NON_PIC_REFERENCE_P (OP))
2370 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2371 that is a valid memory address for an instruction.
2372 The MODE argument is the machine mode for the MEM expression
2373 that wants to use this address. */
2375 #define MODE_DISP_OK_4(X,MODE) \
2376 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2377 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2379 #define MODE_DISP_OK_8(X,MODE) \
2380 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2381 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2383 #undef MODE_DISP_OK_4
2384 #define MODE_DISP_OK_4(X,MODE) \
2385 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2386 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2387 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2388 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2390 #undef MODE_DISP_OK_8
2391 #define MODE_DISP_OK_8(X,MODE) \
2392 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2393 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2394 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2395 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2397 #define BASE_REGISTER_RTX_P(X) \
2398 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2399 || (GET_CODE (X) == SUBREG \
2400 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2401 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2402 && GET_CODE (SUBREG_REG (X)) == REG \
2403 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2405 /* Since this must be r0, which is a single register class, we must check
2406 SUBREGs more carefully, to be sure that we don't accept one that extends
2407 outside the class. */
2408 #define INDEX_REGISTER_RTX_P(X) \
2409 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2410 || (GET_CODE (X) == SUBREG \
2411 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2412 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2413 && GET_CODE (SUBREG_REG (X)) == REG \
2414 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2416 /* Jump to LABEL if X is a valid address RTX. This must also take
2417 REG_OK_STRICT into account when deciding about valid registers, but it uses
2418 the above macros so we are in luck.
2426 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2427 into the FRx registers. We implement this by setting the maximum offset
2428 to zero when the value is SFmode. This also restricts loading of SFmode
2429 values into the integer registers, but that can't be helped. */
2431 /* The SH allows a displacement in a QI or HI amode, but only when the
2432 other operand is R0. GCC doesn't handle this very well, so we forgo
2435 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2436 DI can be any number 0..60. */
2438 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2440 if (GET_CODE (OP) == CONST_INT) \
2442 if (TARGET_SHMEDIA) \
2445 /* Check if this the address of an unaligned load / store. */\
2446 if ((MODE) == VOIDmode) \
2448 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2452 MODE_SIZE = GET_MODE_SIZE (MODE); \
2453 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2454 && INTVAL (OP) >= -512 * MODE_SIZE \
2455 && INTVAL (OP) < 512 * MODE_SIZE) \
2460 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2461 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2465 #define ALLOW_INDEXED_ADDRESS \
2466 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2468 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2470 if (BASE_REGISTER_RTX_P (X)) \
2472 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2473 && ! TARGET_SHMEDIA \
2474 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2476 else if (GET_CODE (X) == PLUS \
2477 && ((MODE) != PSImode || reload_completed)) \
2479 rtx xop0 = XEXP ((X), 0); \
2480 rtx xop1 = XEXP ((X), 1); \
2481 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2482 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2483 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2484 || ((xop0 == stack_pointer_rtx \
2485 || xop0 == hard_frame_pointer_rtx) \
2486 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2487 || ((xop1 == stack_pointer_rtx \
2488 || xop1 == hard_frame_pointer_rtx) \
2489 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2490 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2491 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2492 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2493 && TARGET_FMOVD && MODE == DFmode))) \
2495 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2497 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2503 /* Try machine-dependent ways of modifying an illegitimate address
2504 to be legitimate. If we find one, return the new, valid address.
2505 This macro is used in only one place: `memory_address' in explow.c.
2507 OLDX is the address as it was before break_out_memory_refs was called.
2508 In some cases it is useful to look at this to decide what needs to be done.
2510 MODE and WIN are passed so that this macro can use
2511 GO_IF_LEGITIMATE_ADDRESS.
2513 It is always safe for this macro to do nothing. It exists to recognize
2514 opportunities to optimize the output.
2516 For the SH, if X is almost suitable for indexing, but the offset is
2517 out of range, convert it into a normal form so that cse has a chance
2518 of reducing the number of address registers used. */
2520 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2523 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2524 if (GET_CODE (X) == PLUS \
2525 && (GET_MODE_SIZE (MODE) == 4 \
2526 || GET_MODE_SIZE (MODE) == 8) \
2527 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2528 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2529 && ! TARGET_SHMEDIA \
2530 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2531 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2533 rtx index_rtx = XEXP ((X), 1); \
2534 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2537 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2538 /* On rare occasions, we might get an unaligned pointer \
2539 that is indexed in a way to give an aligned address. \
2540 Therefore, keep the lower two bits in offset_base. */ \
2541 /* Instead of offset_base 128..131 use 124..127, so that \
2542 simple add suffices. */ \
2545 offset_base = ((offset + 4) & ~60) - 4; \
2548 offset_base = offset & ~60; \
2549 /* Sometimes the normal form does not suit DImode. We \
2550 could avoid that by using smaller ranges, but that \
2551 would give less optimized code when SImode is \
2553 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2555 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2556 GEN_INT (offset_base), NULL_RTX, 0, \
2559 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2565 /* A C compound statement that attempts to replace X, which is an address
2566 that needs reloading, with a valid memory address for an operand of
2567 mode MODE. WIN is a C statement label elsewhere in the code.
2569 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2570 of the address. That will allow inheritance of the address reloads. */
2572 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2574 if (GET_CODE (X) == PLUS \
2575 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2576 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2577 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2578 && ! TARGET_SHMEDIA \
2579 && ! (TARGET_SH4 && (MODE) == DFmode) \
2580 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2581 && (ALLOW_INDEXED_ADDRESS \
2582 || XEXP ((X), 0) == stack_pointer_rtx \
2583 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2585 rtx index_rtx = XEXP (X, 1); \
2586 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2589 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2591 push_reload (X, NULL_RTX, &X, NULL, \
2592 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2596 if (TARGET_SH2E && MODE == SFmode) \
2599 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2600 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2604 /* Instead of offset_base 128..131 use 124..127, so that \
2605 simple add suffices. */ \
2608 offset_base = ((offset + 4) & ~60) - 4; \
2611 offset_base = offset & ~60; \
2612 /* Sometimes the normal form does not suit DImode. We \
2613 could avoid that by using smaller ranges, but that \
2614 would give less optimized code when SImode is \
2616 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2618 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2619 GEN_INT (offset_base)); \
2620 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2621 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2622 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2627 /* We must re-recognize what we created before. */ \
2628 else if (GET_CODE (X) == PLUS \
2629 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2630 && GET_CODE (XEXP (X, 0)) == PLUS \
2631 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2632 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2633 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2634 && ! TARGET_SHMEDIA \
2635 && ! (TARGET_SH2E && MODE == SFmode)) \
2637 /* Because this address is so complex, we know it must have \
2638 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2639 it is already unshared, and needs no further unsharing. */ \
2640 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2641 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2646 /* Go to LABEL if ADDR (a legitimate address expression)
2647 has an effect that depends on the machine mode it is used for.
2649 ??? Strictly speaking, we should also include all indexed addressing,
2650 because the index scale factor is the length of the operand.
2651 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2652 high if we did that. So we rely on reload to fix things up.
2654 Auto-increment addressing is now treated in recog.c. */
2656 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2658 /* Specify the machine mode that this machine uses
2659 for the index in the tablejump instruction. */
2660 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2662 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2663 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2664 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2665 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2666 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2667 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2670 /* Define as C expression which evaluates to nonzero if the tablejump
2671 instruction expects the table to contain offsets from the address of the
2673 Do not define this if the table should contain absolute addresses. */
2674 #define CASE_VECTOR_PC_RELATIVE 1
2676 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2677 #define FLOAT_TYPE_SIZE 32
2679 /* Since the SH2e has only `float' support, it is desirable to make all
2680 floating point types equivalent to `float'. */
2681 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2683 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2684 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2686 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2689 /* 'char' is signed by default. */
2690 #define DEFAULT_SIGNED_CHAR 1
2692 /* The type of size_t unsigned int. */
2693 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2696 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2698 #define WCHAR_TYPE "short unsigned int"
2699 #define WCHAR_TYPE_SIZE 16
2701 #define SH_ELF_WCHAR_TYPE "long int"
2703 /* Max number of bytes we can move from memory to memory
2704 in one reasonably fast instruction. */
2705 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2707 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2708 MOVE_MAX is not a compile-time constant. */
2709 #define MAX_MOVE_MAX 8
2711 /* Max number of bytes we want move_by_pieces to be able to copy
2713 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2715 /* Define if operations between registers always perform the operation
2716 on the full register even if a narrower mode is specified. */
2717 #define WORD_REGISTER_OPERATIONS
2719 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2720 will either zero-extend or sign-extend. The value of this macro should
2721 be the code that says which one of the two operations is implicitly
2722 done, UNKNOWN if none. */
2723 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2724 /* FP registers can load SImode values, but don't implicitly sign-extend
2726 #define LOAD_EXTEND_OP(MODE) \
2727 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2728 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2730 /* Define if loading short immediate values into registers sign extends. */
2731 #define SHORT_IMMEDIATES_SIGN_EXTEND
2733 /* Nonzero if access to memory by bytes is no faster than for words. */
2734 #define SLOW_BYTE_ACCESS 1
2736 /* Immediate shift counts are truncated by the output routines (or was it
2737 the assembler?). Shift counts in a register are truncated by SH. Note
2738 that the native compiler puts too large (> 32) immediate shift counts
2739 into a register and shifts by the register, letting the SH decide what
2740 to do instead of doing that itself. */
2741 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2742 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2743 expects - the sign bit is significant - so it appears that we need to
2744 leave this zero for correct SH3 code. */
2745 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2747 /* All integers have the same format so truncation is easy. */
2748 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2749 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2750 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2752 /* Define this if addresses of constant functions
2753 shouldn't be put through pseudo regs where they can be cse'd.
2754 Desirable on machines where ordinary constants are expensive
2755 but a CALL with constant address is cheap. */
2756 /*#define NO_FUNCTION_CSE 1*/
2758 /* The machine modes of pointers and functions. */
2759 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2760 #define FUNCTION_MODE Pmode
2762 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2763 are actually function calls with some special constraints on arguments
2766 These macros tell reorg that the references to arguments and
2767 register clobbers for insns of type sfunc do not appear to happen
2768 until after the millicode call. This allows reorg to put insns
2769 which set the argument registers into the delay slot of the millicode
2770 call -- thus they act more like traditional CALL_INSNs.
2772 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2773 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2776 #define INSN_SETS_ARE_DELAYED(X) \
2777 ((GET_CODE (X) == INSN \
2778 && GET_CODE (PATTERN (X)) != SEQUENCE \
2779 && GET_CODE (PATTERN (X)) != USE \
2780 && GET_CODE (PATTERN (X)) != CLOBBER \
2781 && get_attr_is_sfunc (X)))
2783 #define INSN_REFERENCES_ARE_DELAYED(X) \
2784 ((GET_CODE (X) == INSN \
2785 && GET_CODE (PATTERN (X)) != SEQUENCE \
2786 && GET_CODE (PATTERN (X)) != USE \
2787 && GET_CODE (PATTERN (X)) != CLOBBER \
2788 && get_attr_is_sfunc (X)))
2791 /* Position Independent Code. */
2793 /* We can't directly access anything that contains a symbol,
2794 nor can we indirect via the constant pool. */
2795 #define LEGITIMATE_PIC_OPERAND_P(X) \
2796 ((! nonpic_symbol_mentioned_p (X) \
2797 && (GET_CODE (X) != SYMBOL_REF \
2798 || ! CONSTANT_POOL_ADDRESS_P (X) \
2799 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2800 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2802 #define SYMBOLIC_CONST_P(X) \
2803 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2804 && nonpic_symbol_mentioned_p (X))
2806 /* Compute extra cost of moving data between one register class
2809 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2810 uses this information. Hence, the general register <-> floating point
2811 register information here is not used for SFmode. */
2813 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2814 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2815 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2817 #define REGCLASS_HAS_FP_REG(CLASS) \
2818 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2819 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2821 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2822 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2824 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2825 would be so that people with slow memory systems could generate
2826 different code that does fewer memory accesses. */
2828 /* A C expression for the cost of a branch instruction. A value of 1
2829 is the default; other values are interpreted relative to that.
2830 The SH1 does not have delay slots, hence we get a pipeline stall
2831 at every branch. The SH4 is superscalar, so the single delay slot
2832 is not sufficient to keep both pipelines filled. */
2833 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2835 /* Assembler output control. */
2837 /* A C string constant describing how to begin a comment in the target
2838 assembler language. The compiler assumes that the comment will end at
2839 the end of the line. */
2840 #define ASM_COMMENT_START "!"
2842 #define ASM_APP_ON ""
2843 #define ASM_APP_OFF ""
2844 #define FILE_ASM_OP "\t.file\n"
2845 #define SET_ASM_OP "\t.set\t"
2847 /* How to change between sections. */
2849 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2850 #define DATA_SECTION_ASM_OP "\t.data"
2852 #if defined CRT_BEGIN || defined CRT_END
2853 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2854 # undef TEXT_SECTION_ASM_OP
2855 # if __SHMEDIA__ == 1 && __SH5__ == 32
2856 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2858 # define TEXT_SECTION_ASM_OP "\t.text"
2863 /* If defined, a C expression whose value is a string containing the
2864 assembler operation to identify the following data as
2865 uninitialized global data. If not defined, and neither
2866 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2867 uninitialized global data will be output in the data section if
2868 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2870 #ifndef BSS_SECTION_ASM_OP
2871 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2874 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2875 separate, explicit argument. If you define this macro, it is used
2876 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2877 handling the required alignment of the variable. The alignment is
2878 specified as the number of bits.
2880 Try to use function `asm_output_aligned_bss' defined in file
2881 `varasm.c' when defining this macro. */
2882 #ifndef ASM_OUTPUT_ALIGNED_BSS
2883 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2884 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2887 /* Define this so that jump tables go in same section as the current function,
2888 which could be text or it could be a user defined section. */
2889 #define JUMP_TABLES_IN_TEXT_SECTION 1
2891 #undef DO_GLOBAL_CTORS_BODY
2892 #define DO_GLOBAL_CTORS_BODY \
2894 typedef void (*pfunc) (void); \
2895 extern pfunc __ctors[]; \
2896 extern pfunc __ctors_end[]; \
2898 for (p = __ctors_end; p > __ctors; ) \
2904 #undef DO_GLOBAL_DTORS_BODY
2905 #define DO_GLOBAL_DTORS_BODY \
2907 typedef void (*pfunc) (void); \
2908 extern pfunc __dtors[]; \
2909 extern pfunc __dtors_end[]; \
2911 for (p = __dtors; p < __dtors_end; p++) \
2917 #define ASM_OUTPUT_REG_PUSH(file, v) \
2919 if (TARGET_SHMEDIA) \
2921 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2922 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2925 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2928 #define ASM_OUTPUT_REG_POP(file, v) \
2930 if (TARGET_SHMEDIA) \
2932 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2933 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2936 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2939 /* DBX register number for a given compiler register number. */
2940 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2942 /* svr4.h undefines this macro, yet we really want to use the same numbers
2943 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2944 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2945 register exists, so we should return -1 for invalid register numbers. */
2946 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2948 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2949 used to use the encodings 245..260, but that doesn't make sense:
2950 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2951 the FP registers stay the same when switching between compact and media
2952 mode. Hence, we also need to use the same dwarf frame columns.
2953 Likewise, we need to support unwind information for SHmedia registers
2954 even in compact code. */
2955 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2956 (IN_RANGE ((REGNO), \
2957 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2958 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2959 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2960 : ((int) (REGNO) >= FIRST_FP_REG \
2962 <= (FIRST_FP_REG + \
2963 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2964 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2965 + (TARGET_SH5 ? 77 : 25)) \
2966 : XD_REGISTER_P (REGNO) \
2967 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2968 : TARGET_REGISTER_P (REGNO) \
2969 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2970 : (REGNO) == PR_REG \
2971 ? (TARGET_SH5 ? 18 : 17) \
2972 : (REGNO) == PR_MEDIA_REG \
2973 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2974 : (REGNO) == T_REG \
2975 ? (TARGET_SH5 ? 242 : 18) \
2976 : (REGNO) == GBR_REG \
2977 ? (TARGET_SH5 ? 238 : 19) \
2978 : (REGNO) == MACH_REG \
2979 ? (TARGET_SH5 ? 239 : 20) \
2980 : (REGNO) == MACL_REG \
2981 ? (TARGET_SH5 ? 240 : 21) \
2982 : (REGNO) == FPUL_REG \
2983 ? (TARGET_SH5 ? 244 : 23) \
2986 /* This is how to output a reference to a symbol_ref. On SH5,
2987 references to non-code symbols must be preceded by `datalabel'. */
2988 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2991 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2992 fputs ("datalabel ", (FILE)); \
2993 assemble_name ((FILE), XSTR ((SYM), 0)); \
2997 /* This is how to output an assembler line
2998 that says to advance the location counter
2999 to a multiple of 2**LOG bytes. */
3001 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3003 fprintf ((FILE), "\t.align %d\n", (LOG))
3005 /* Globalizing directive for a label. */
3006 #define GLOBAL_ASM_OP "\t.global\t"
3008 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3010 /* Output a relative address table. */
3012 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3013 switch (GET_MODE (BODY)) \
3018 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3022 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3027 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3031 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3036 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3040 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3046 /* Output an absolute table element. */
3048 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3049 if (! optimize || TARGET_BIGTABLE) \
3050 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3052 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3055 /* A C statement to be executed just prior to the output of
3056 assembler code for INSN, to modify the extracted operands so
3057 they will be output differently.
3059 Here the argument OPVEC is the vector containing the operands
3060 extracted from INSN, and NOPERANDS is the number of elements of
3061 the vector which contain meaningful data for this insn.
3062 The contents of this vector are what will be used to convert the insn
3063 template into assembler code, so you can change the assembler output
3064 by changing the contents of the vector. */
3066 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3067 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3069 /* Print operand X (an rtx) in assembler syntax to file FILE.
3070 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3071 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3073 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3075 /* Print a memory address as an operand to reference that memory location. */
3077 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3079 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3080 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3081 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3083 /* Recognize machine-specific patterns that may appear within
3084 constants. Used for PIC-specific UNSPECs. */
3085 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3087 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3089 switch (XINT ((X), 1)) \
3091 case UNSPEC_DATALABEL: \
3092 fputs ("datalabel ", (STREAM)); \
3093 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3096 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3097 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3100 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3101 fputs ("@GOT", (STREAM)); \
3103 case UNSPEC_GOTOFF: \
3104 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3105 fputs ("@GOTOFF", (STREAM)); \
3108 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3109 fputs ("@PLT", (STREAM)); \
3111 case UNSPEC_GOTPLT: \
3112 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3113 fputs ("@GOTPLT", (STREAM)); \
3115 case UNSPEC_DTPOFF: \
3116 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3117 fputs ("@DTPOFF", (STREAM)); \
3119 case UNSPEC_GOTTPOFF: \
3120 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3121 fputs ("@GOTTPOFF", (STREAM)); \
3123 case UNSPEC_TPOFF: \
3124 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3125 fputs ("@TPOFF", (STREAM)); \
3127 case UNSPEC_CALLER: \
3130 /* LPCS stands for Label for PIC Call Site. */ \
3131 ASM_GENERATE_INTERNAL_LABEL \
3132 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3133 assemble_name ((STREAM), name); \
3146 extern struct rtx_def *sh_compare_op0;
3147 extern struct rtx_def *sh_compare_op1;
3149 /* Which processor to schedule for. The elements of the enumeration must
3150 match exactly the cpu attribute in the sh.md file. */
3152 enum processor_type {
3164 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3165 extern enum processor_type sh_cpu;
3167 extern int optimize; /* needed for gen_casesi. */
3169 enum mdep_reorg_phase_e
3171 SH_BEFORE_MDEP_REORG,
3172 SH_INSERT_USES_LABELS,
3173 SH_SHORTEN_BRANCHES0,
3175 SH_SHORTEN_BRANCHES1,
3179 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3181 /* Handle Renesas compiler's pragmas. */
3182 #define REGISTER_TARGET_PRAGMAS() do { \
3183 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3184 c_register_pragma (0, "trapa", sh_pr_trapa); \
3185 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3188 extern tree sh_deferred_function_attributes;
3189 extern tree *sh_deferred_function_attributes_tail;
3191 /* Set when processing a function with interrupt attribute. */
3193 extern int current_function_interrupt;
3196 /* Instructions with unfilled delay slots take up an
3197 extra two bytes for the nop in the delay slot.
3198 sh-dsp parallel processing insns are four bytes long. */
3200 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3201 (LENGTH) += sh_insn_length_adjustment (X);
3203 /* Define this macro if it is advisable to hold scalars in registers
3204 in a wider mode than that declared by the program. In such cases,
3205 the value is constrained to be within the bounds of the declared
3206 type, but kept valid in the wider mode. The signedness of the
3207 extension may differ from that of the type.
3209 Leaving the unsignedp unchanged gives better code than always setting it
3210 to 0. This is despite the fact that we have only signed char and short
3211 load instructions. */
3212 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3213 if (GET_MODE_CLASS (MODE) == MODE_INT \
3214 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3215 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3216 (MODE) = (TARGET_SH1 ? SImode \
3217 : TARGET_SHMEDIA32 ? SImode : DImode);
3219 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3221 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3223 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3224 and popping arguments. However, we do have push/pop instructions, and
3225 rather limited offsets (4 bits) in load/store instructions, so it isn't
3226 clear if this would give better code. If implemented, should check for
3227 compatibility problems. */
3229 #define SH_DYNAMIC_SHIFT_COST \
3230 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3233 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3235 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3237 #define ACTUAL_NORMAL_MODE(ENTITY) \
3238 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3240 #define NORMAL_MODE(ENTITY) \
3241 (sh_cfun_interrupt_handler_p () \
3242 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3243 : ACTUAL_NORMAL_MODE (ENTITY))
3245 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3247 #define MODE_EXIT(ENTITY) \
3248 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3250 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3251 && (REGNO) == FPSCR_REG)
3253 #define MODE_NEEDED(ENTITY, INSN) \
3254 (recog_memoized (INSN) >= 0 \
3255 ? get_attr_fp_mode (INSN) \
3258 #define MODE_AFTER(MODE, INSN) \
3260 && recog_memoized (INSN) >= 0 \
3261 && get_attr_fp_set (INSN) != FP_SET_NONE \
3262 ? (int) get_attr_fp_set (INSN) \
3265 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3266 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3268 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3269 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3271 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3272 sh_can_redirect_branch ((INSN), (SEQ))
3274 #define DWARF_FRAME_RETURN_COLUMN \
3275 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3277 #define EH_RETURN_DATA_REGNO(N) \
3278 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3280 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3281 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3283 /* We have to distinguish between code and data, so that we apply
3284 datalabel where and only where appropriate. Use sdataN for data. */
3285 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3286 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3287 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3288 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3290 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3291 indirect are handled automatically. */
3292 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3294 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3295 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3297 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3298 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3303 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3304 /* SH constant pool breaks the devices in crtstuff.c to control section
3305 in where code resides. We have to write it as asm code. */
3306 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3307 asm (SECTION_OP "\n\
3313 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3314 2:\n" TEXT_SECTION_ASM_OP);
3315 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3317 /* FIXME: middle-end support for highpart optimizations is missing. */
3318 #define high_life_started reload_in_progress
3320 #endif /* ! GCC_SH_H */
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