1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 #define TARGET_VERSION \
30 fputs (" (Hitachi SH)", stderr);
32 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
33 include it here, because bconfig.h is also included by gencodes.c . */
34 /* ??? No longer true. */
35 extern int code_for_indirect_jump_scratch;
37 #define TARGET_CPU_CPP_BUILTINS() \
39 builtin_define ("__sh__"); \
40 builtin_assert ("cpu=sh"); \
41 builtin_assert ("machine=sh"); \
42 switch ((int) sh_cpu) \
45 builtin_define ("__sh1__"); \
48 builtin_define ("__sh2__"); \
50 case PROCESSOR_SH2E: \
51 builtin_define ("__SH2E__"); \
53 case PROCESSOR_SH2A: \
54 builtin_define ("__SH2A__"); \
55 builtin_define (TARGET_SH2A_DOUBLE \
56 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
57 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
58 : "__SH2A_NOFPU__"); \
61 builtin_define ("__sh3__"); \
62 builtin_define ("__SH3__"); \
63 if (TARGET_HARD_SH4) \
64 builtin_define ("__SH4_NOFPU__"); \
66 case PROCESSOR_SH3E: \
67 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
70 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
72 case PROCESSOR_SH4A: \
73 builtin_define ("__SH4A__"); \
74 builtin_define (TARGET_SH4 \
75 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
76 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
81 builtin_define_with_value ("__SH5__", \
82 TARGET_SHMEDIA64 ? "64" : "32", 0); \
83 builtin_define_with_value ("__SHMEDIA__", \
84 TARGET_SHMEDIA ? "1" : "0", 0); \
85 if (! TARGET_FPU_DOUBLE) \
86 builtin_define ("__SH4_NOFPU__"); \
90 builtin_define ("__SH_FPU_ANY__"); \
91 if (TARGET_FPU_DOUBLE) \
92 builtin_define ("__SH_FPU_DOUBLE__"); \
94 builtin_define ("__HITACHI__"); \
96 builtin_define ("__FMOVD_ENABLED__"); \
97 builtin_define (TARGET_LITTLE_ENDIAN \
98 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
101 /* We can not debug without a frame pointer. */
102 /* #define CAN_DEBUG_WITHOUT_FP */
104 #define CONDITIONAL_REGISTER_USAGE do \
107 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
108 if (! VALID_REGISTER_P (regno)) \
109 fixed_regs[regno] = call_used_regs[regno] = 1; \
110 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
113 call_used_regs[FIRST_GENERAL_REG + 8] \
114 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
115 call_really_used_regs[FIRST_GENERAL_REG + 8] \
116 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
118 if (TARGET_SHMEDIA) \
120 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
121 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
122 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
126 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
127 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
129 /* Renesas saves and restores mac registers on call. */ \
130 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
132 call_really_used_regs[MACH_REG] = 0; \
133 call_really_used_regs[MACL_REG] = 0; \
135 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
136 regno <= LAST_FP_REG; regno += 2) \
137 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
138 if (TARGET_SHMEDIA) \
140 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
141 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
142 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
146 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
147 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
150 /* Nonzero if this is an ELF target - compile time only */
153 /* Nonzero if we should generate code using type 2E insns. */
154 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
156 /* Nonzero if we should generate code using type 2A insns. */
157 #define TARGET_SH2A TARGET_HARD_SH2A
158 /* Nonzero if we should generate code using type 2A SF insns. */
159 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
160 /* Nonzero if we should generate code using type 2A DF insns. */
161 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
163 /* Nonzero if we should generate code using type 3E insns. */
164 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
166 /* Nonzero if the cache line size is 32. */
167 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
169 /* Nonzero if we schedule for a superscalar implementation. */
170 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
172 /* Nonzero if the target has separate instruction and data caches. */
173 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
175 /* Nonzero if a double-precision FPU is available. */
176 #define TARGET_FPU_DOUBLE \
177 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
179 /* Nonzero if an FPU is available. */
180 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
182 /* Nonzero if we should generate code using type 4 insns. */
184 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
186 /* Nonzero if we're generating code for the common subset of
187 instructions present on both SH4a and SH4al-dsp. */
188 #define TARGET_SH4A_ARCH TARGET_SH4A
190 /* Nonzero if we're generating code for SH4a, unless the use of the
191 FPU is disabled (which makes it compatible with SH4al-dsp). */
192 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
194 /* Nonzero if we should generate code using the SHcompact instruction
195 set and 32-bit ABI. */
196 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
198 /* Nonzero if we should generate code using the SHmedia instruction
200 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
202 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
204 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
206 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
208 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
210 /* Nonzero if we should generate code using SHmedia FPU instructions. */
211 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
213 /* This is not used by the SH2E calling convention */
214 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
215 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
216 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
218 #ifndef TARGET_CPU_DEFAULT
219 #define TARGET_CPU_DEFAULT SELECT_SH1
220 #define SUPPORT_SH1 1
221 #define SUPPORT_SH2E 1
222 #define SUPPORT_SH4 1
223 #define SUPPORT_SH4_SINGLE 1
224 #define SUPPORT_SH2A 1
225 #define SUPPORT_SH2A_SINGLE 1
228 #define TARGET_DIVIDE_INV \
229 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
230 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
231 || sh_div_strategy == SH_DIV_INV_CALL \
232 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
233 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
234 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
235 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
236 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
237 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
238 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
239 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
240 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
241 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
242 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
243 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
245 #define SELECT_SH1 (MASK_SH1)
246 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
247 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
249 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
250 | MASK_HARD_SH2A_DOUBLE \
251 | MASK_SH2 | MASK_SH1)
252 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
253 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
254 | MASK_SH1 | MASK_FPU_SINGLE)
255 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
256 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
257 | MASK_SH2 | MASK_SH1)
258 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
259 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
260 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
261 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
262 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
264 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
265 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
266 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
267 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
268 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
269 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
270 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
271 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
272 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
273 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
274 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
277 #define SUPPORT_SH2 1
280 #define SUPPORT_SH3 1
281 #define SUPPORT_SH2A_NOFPU 1
284 #define SUPPORT_SH4_NOFPU 1
286 #if SUPPORT_SH4_NOFPU
287 #define SUPPORT_SH4A_NOFPU 1
288 #define SUPPORT_SH4AL 1
292 #define SUPPORT_SH3E 1
293 #define SUPPORT_SH2A_SINGLE_ONLY 1
296 #define SUPPORT_SH4_SINGLE_ONLY 1
298 #if SUPPORT_SH4_SINGLE_ONLY
299 #define SUPPORT_SH4A_SINGLE_ONLY 1
303 #define SUPPORT_SH4A 1
306 #if SUPPORT_SH4_SINGLE
307 #define SUPPORT_SH4A_SINGLE 1
310 #if SUPPORT_SH5_COMPAT
311 #define SUPPORT_SH5_32MEDIA 1
314 #if SUPPORT_SH5_COMPACT_NOFPU
315 #define SUPPORT_SH5_32MEDIA_NOFPU 1
318 #define SUPPORT_ANY_SH5_32MEDIA \
319 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
320 #define SUPPORT_ANY_SH5_64MEDIA \
321 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
322 #define SUPPORT_ANY_SH5 \
323 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
325 /* Reset all target-selection flags. */
326 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
327 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
328 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
330 /* This defaults us to big-endian. */
331 #ifndef TARGET_ENDIAN_DEFAULT
332 #define TARGET_ENDIAN_DEFAULT 0
335 #ifndef TARGET_OPT_DEFAULT
336 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
339 #define TARGET_DEFAULT \
340 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
342 #ifndef SH_MULTILIB_CPU_DEFAULT
343 #define SH_MULTILIB_CPU_DEFAULT "m1"
346 #if TARGET_ENDIAN_DEFAULT
347 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
349 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
352 #define CPP_SPEC " %(subtarget_cpp_spec) "
354 #ifndef SUBTARGET_CPP_SPEC
355 #define SUBTARGET_CPP_SPEC ""
358 #ifndef SUBTARGET_EXTRA_SPECS
359 #define SUBTARGET_EXTRA_SPECS
362 #define EXTRA_SPECS \
363 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
364 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
365 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
366 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
367 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
368 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
369 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
370 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
371 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
372 SUBTARGET_EXTRA_SPECS
374 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
375 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
377 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
380 #define SH_ASM_SPEC \
381 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
382 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
384 %{m2a-single:--isa=sh2a} \
385 %{m2a-single-only:--isa=sh2a} \
386 %{m2a-nofpu:--isa=sh2a-nofpu} \
387 %{m5-compact*:--isa=SHcompact} \
388 %{m5-32media*:--isa=SHmedia --abi=32} \
389 %{m5-64media*:--isa=SHmedia --abi=64} \
390 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
392 #define ASM_SPEC SH_ASM_SPEC
394 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
395 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
396 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
398 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
402 #if STRICT_NOFPU == 1
403 /* Strict nofpu means that the compiler should tell the assembler
404 to reject FPU instructions. E.g. from ASM inserts. */
405 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
406 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
408 /* If there were an -isa option for sh5-nofpu then it would also go here. */
409 #define SUBTARGET_ASM_ISA_SPEC \
410 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
412 #else /* ! STRICT_NOFPU */
413 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
416 #ifndef SUBTARGET_ASM_SPEC
417 #define SUBTARGET_ASM_SPEC ""
420 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
421 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
423 #define LINK_EMUL_PREFIX "sh%{ml:l}"
426 #if TARGET_CPU_DEFAULT & MASK_SH5
427 #if TARGET_CPU_DEFAULT & MASK_SH_E
428 #define LINK_DEFAULT_CPU_EMUL "32"
429 #if TARGET_CPU_DEFAULT & MASK_SH1
430 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
432 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
433 #endif /* MASK_SH1 */
434 #else /* !MASK_SH_E */
435 #define LINK_DEFAULT_CPU_EMUL "64"
436 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
437 #endif /* MASK_SH_E */
438 #define ASM_ISA_DEFAULT_SPEC \
439 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
440 #else /* !MASK_SH5 */
441 #define LINK_DEFAULT_CPU_EMUL ""
442 #define ASM_ISA_DEFAULT_SPEC ""
443 #endif /* MASK_SH5 */
445 #define SUBTARGET_LINK_EMUL_SUFFIX ""
446 #define SUBTARGET_LINK_SPEC ""
448 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
449 so that we can undo the damage without code replication. */
450 #define LINK_SPEC SH_LINK_SPEC
452 #define SH_LINK_SPEC "\
453 -m %(link_emul_prefix)\
454 %{m5-compact*|m5-32media*:32}\
456 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
457 %(subtarget_link_emul_suffix) \
458 %{mrelax:-relax} %(subtarget_link_spec)"
460 #ifndef SH_DIV_STR_FOR_SIZE
461 #define SH_DIV_STR_FOR_SIZE "call"
464 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
466 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) sh_optimization_options (LEVEL, SIZE)
468 #define ASSEMBLER_DIALECT assembler_dialect
470 extern int assembler_dialect;
472 enum sh_divide_strategy_e {
473 /* SH5 strategies. */
476 SH_DIV_FP, /* We could do this also for SH4. */
484 /* SH1 .. SH4 strategies. Because of the small number of registers
485 available, the compiler uses knowledge of the actual set of registers
486 being clobbered by the different functions called. */
487 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
488 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
489 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
493 extern enum sh_divide_strategy_e sh_div_strategy;
495 #ifndef SH_DIV_STRATEGY_DEFAULT
496 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
499 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
501 extern const char *sh_fixed_range_str;
503 #define OVERRIDE_OPTIONS sh_override_options ()
506 /* Target machine storage layout. */
508 /* Define this if most significant bit is lowest numbered
509 in instructions that operate on numbered bit-fields. */
511 #define BITS_BIG_ENDIAN 0
513 /* Define this if most significant byte of a word is the lowest numbered. */
514 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
516 /* Define this if most significant word of a multiword number is the lowest
518 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
520 /* Define this to set the endianness to use in libgcc2.c, which can
521 not depend on target_flags. */
522 #if defined(__LITTLE_ENDIAN__)
523 #define LIBGCC2_WORDS_BIG_ENDIAN 0
525 #define LIBGCC2_WORDS_BIG_ENDIAN 1
528 #define MAX_BITS_PER_WORD 64
530 /* Width in bits of an `int'. We want just 32-bits, even if words are
532 #define INT_TYPE_SIZE 32
534 /* Width in bits of a `long'. */
535 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
537 /* Width in bits of a `long long'. */
538 #define LONG_LONG_TYPE_SIZE 64
540 /* Width in bits of a `long double'. */
541 #define LONG_DOUBLE_TYPE_SIZE 64
543 /* Width of a word, in units (bytes). */
544 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
545 #define MIN_UNITS_PER_WORD 4
547 /* Scaling factor for Dwarf data offsets for CFI information.
548 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
549 SHmedia; however, since we do partial register saves for the registers
550 visible to SHcompact, and for target registers for SHMEDIA32, we have
551 to allow saves that are only 4-byte aligned. */
552 #define DWARF_CIE_DATA_ALIGNMENT -4
554 /* Width in bits of a pointer.
555 See also the macro `Pmode' defined below. */
556 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
558 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
559 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
561 /* Boundary (in *bits*) on which stack pointer should be aligned. */
562 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
564 /* The log (base 2) of the cache line size, in bytes. Processors prior to
565 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
566 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
567 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
569 /* ABI given & required minimum allocation boundary (in *bits*) for the
570 code of a function. */
571 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
573 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
574 the vbit must go into the delta field of
575 pointers-to-member-functions. */
576 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
577 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
579 /* Alignment of field after `int : 0' in a structure. */
580 #define EMPTY_FIELD_BOUNDARY 32
582 /* No data type wants to be aligned rounder than this. */
583 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
585 /* The best alignment to use in cases where we have a choice. */
586 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
588 /* Make strings word-aligned so strcpy from constants will be faster. */
589 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
590 ((TREE_CODE (EXP) == STRING_CST \
591 && (ALIGN) < FASTEST_ALIGNMENT) \
592 ? FASTEST_ALIGNMENT : (ALIGN))
594 /* get_mode_alignment assumes complex values are always held in multiple
595 registers, but that is not the case on the SH; CQImode and CHImode are
596 held in a single integer register. SH5 also holds CSImode and SCmode
597 values in integer registers. This is relevant for argument passing on
598 SHcompact as we use a stack temp in order to pass CSImode by reference. */
599 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
600 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
601 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
602 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
603 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
605 /* Make arrays of chars word-aligned for the same reasons. */
606 #define DATA_ALIGNMENT(TYPE, ALIGN) \
607 (TREE_CODE (TYPE) == ARRAY_TYPE \
608 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
609 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
611 /* Number of bits which any structure or union's size must be a
612 multiple of. Each structure or union's size is rounded up to a
614 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
616 /* Set this nonzero if move instructions will actually fail to work
617 when given unaligned data. */
618 #define STRICT_ALIGNMENT 1
620 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
621 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
622 barrier_align (LABEL_AFTER_BARRIER)
624 #define LOOP_ALIGN(A_LABEL) \
625 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
626 ? 0 : sh_loop_align (A_LABEL))
628 #define LABEL_ALIGN(A_LABEL) \
630 (PREV_INSN (A_LABEL) \
631 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
632 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
633 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
634 /* explicit alignment insn in constant tables. */ \
635 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
638 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
639 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
641 /* The base two logarithm of the known minimum alignment of an insn length. */
642 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
643 (NONJUMP_INSN_P (A_INSN) \
644 ? 1 << TARGET_SHMEDIA \
645 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
646 ? 1 << TARGET_SHMEDIA \
649 /* Standard register usage. */
651 /* Register allocation for the Renesas calling convention:
657 r14 frame pointer/call saved
659 ap arg pointer (doesn't really exist, always eliminated)
660 pr subroutine return address
662 mach multiply/accumulate result, high part
663 macl multiply/accumulate result, low part.
664 fpul fp/int communication register
665 rap return address pointer register
667 fr1..fr3 scratch floating point registers
669 fr12..fr15 call saved floating point registers */
671 #define MAX_REGISTER_NAME_LENGTH 5
672 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
674 #define SH_REGISTER_NAMES_INITIALIZER \
676 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
677 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
678 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
679 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
680 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
681 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
682 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
683 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
684 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
685 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
686 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
687 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
688 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
689 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
690 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
691 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
692 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
693 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
694 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
698 #define REGNAMES_ARR_INDEX_1(index) \
699 (sh_register_names[index])
700 #define REGNAMES_ARR_INDEX_2(index) \
701 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
702 #define REGNAMES_ARR_INDEX_4(index) \
703 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
704 #define REGNAMES_ARR_INDEX_8(index) \
705 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
706 #define REGNAMES_ARR_INDEX_16(index) \
707 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
708 #define REGNAMES_ARR_INDEX_32(index) \
709 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
710 #define REGNAMES_ARR_INDEX_64(index) \
711 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
713 #define REGISTER_NAMES \
715 REGNAMES_ARR_INDEX_64 (0), \
716 REGNAMES_ARR_INDEX_64 (64), \
717 REGNAMES_ARR_INDEX_8 (128), \
718 REGNAMES_ARR_INDEX_8 (136), \
719 REGNAMES_ARR_INDEX_8 (144), \
720 REGNAMES_ARR_INDEX_2 (152) \
723 #define ADDREGNAMES_SIZE 32
724 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
725 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
726 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
728 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
730 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
731 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
732 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
733 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
736 #define ADDREGNAMES_REGNO(index) \
737 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
740 #define ADDREGNAMES_ARR_INDEX_1(index) \
741 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
742 #define ADDREGNAMES_ARR_INDEX_2(index) \
743 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
744 #define ADDREGNAMES_ARR_INDEX_4(index) \
745 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
746 #define ADDREGNAMES_ARR_INDEX_8(index) \
747 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
748 #define ADDREGNAMES_ARR_INDEX_16(index) \
749 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
750 #define ADDREGNAMES_ARR_INDEX_32(index) \
751 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
753 #define ADDITIONAL_REGISTER_NAMES \
755 ADDREGNAMES_ARR_INDEX_32 (0) \
758 /* Number of actual hardware registers.
759 The hardware registers are assigned numbers for the compiler
760 from 0 to just below FIRST_PSEUDO_REGISTER.
761 All registers that the compiler knows about must be given numbers,
762 even those that are not normally considered general registers. */
764 /* There are many other relevant definitions in sh.md's md_constants. */
766 #define FIRST_GENERAL_REG R0_REG
767 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
768 #define FIRST_FP_REG DR0_REG
769 #define LAST_FP_REG (FIRST_FP_REG + \
770 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
771 #define FIRST_XD_REG XD0_REG
772 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
773 #define FIRST_TARGET_REG TR0_REG
774 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
776 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
778 #define FIRST_BANKED_REG R0_REG
779 #define LAST_BANKED_REG R7_REG
781 #define BANKED_REGISTER_P(REGNO) \
783 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
784 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
786 #define GENERAL_REGISTER_P(REGNO) \
788 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
789 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
791 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
792 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
793 || ((REGNO) == FRAME_POINTER_REGNUM))
795 #define FP_REGISTER_P(REGNO) \
796 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
798 #define XD_REGISTER_P(REGNO) \
799 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
801 #define FP_OR_XD_REGISTER_P(REGNO) \
802 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
804 #define FP_ANY_REGISTER_P(REGNO) \
805 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
807 #define SPECIAL_REGISTER_P(REGNO) \
808 ((REGNO) == GBR_REG || (REGNO) == T_REG \
809 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
811 #define TARGET_REGISTER_P(REGNO) \
812 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
814 #define SHMEDIA_REGISTER_P(REGNO) \
815 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
816 || TARGET_REGISTER_P (REGNO))
818 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
819 that should be fixed. */
820 #define VALID_REGISTER_P(REGNO) \
821 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
822 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
823 || (REGNO) == FRAME_POINTER_REGNUM \
824 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
825 || (TARGET_SH2E && (REGNO) == FPUL_REG))
827 /* The mode that should be generally used to store a register by
828 itself in the stack, or to load it back. */
829 #define REGISTER_NATURAL_MODE(REGNO) \
830 (FP_REGISTER_P (REGNO) ? SFmode \
831 : XD_REGISTER_P (REGNO) ? DFmode \
832 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
836 #define FIRST_PSEUDO_REGISTER 154
838 /* Don't count soft frame pointer. */
839 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
841 /* 1 for registers that have pervasive standard uses
842 and are not available for the register allocator.
844 Mach register is fixed 'cause it's only 10 bits wide for SH1.
845 It is 32 bits wide for SH2. */
847 #define FIXED_REGISTERS \
849 /* Regular registers. */ \
850 0, 0, 0, 0, 0, 0, 0, 0, \
851 0, 0, 0, 0, 0, 0, 0, 1, \
852 /* r16 is reserved, r18 is the former pr. */ \
853 1, 0, 0, 0, 0, 0, 0, 0, \
854 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
855 /* r26 is a global variable data pointer; r27 is for constants. */ \
856 1, 1, 1, 1, 0, 0, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 1, \
861 /* FP registers. */ \
862 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 0, 0, 0, 0, 0, 0, 0, 0, \
869 0, 0, 0, 0, 0, 0, 0, 0, \
870 /* Branch target registers. */ \
871 0, 0, 0, 0, 0, 0, 0, 0, \
872 /* XD registers. */ \
873 0, 0, 0, 0, 0, 0, 0, 0, \
874 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
875 1, 1, 1, 1, 1, 1, 0, 1, \
880 /* 1 for registers not available across function calls.
881 These must include the FIXED_REGISTERS and also any
882 registers that can be used without being saved.
883 The latter must include the registers where values are returned
884 and the register where structure-value addresses are passed.
885 Aside from that, you can include as many other registers as you like. */
887 #define CALL_USED_REGISTERS \
889 /* Regular registers. */ \
890 1, 1, 1, 1, 1, 1, 1, 1, \
891 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
892 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
893 across SH5 function calls. */ \
894 0, 0, 0, 0, 0, 0, 0, 1, \
895 1, 1, 1, 1, 1, 1, 1, 1, \
896 1, 1, 1, 1, 0, 0, 0, 0, \
897 0, 0, 0, 0, 1, 1, 1, 1, \
898 1, 1, 1, 1, 0, 0, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, \
900 0, 0, 0, 0, 1, 1, 1, 1, \
901 /* FP registers. */ \
902 1, 1, 1, 1, 1, 1, 1, 1, \
903 1, 1, 1, 1, 0, 0, 0, 0, \
904 1, 1, 1, 1, 1, 1, 1, 1, \
905 1, 1, 1, 1, 1, 1, 1, 1, \
906 1, 1, 1, 1, 0, 0, 0, 0, \
907 0, 0, 0, 0, 0, 0, 0, 0, \
908 0, 0, 0, 0, 0, 0, 0, 0, \
909 0, 0, 0, 0, 0, 0, 0, 0, \
910 /* Branch target registers. */ \
911 1, 1, 1, 1, 1, 0, 0, 0, \
912 /* XD registers. */ \
913 1, 1, 1, 1, 1, 1, 0, 0, \
914 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
915 1, 1, 1, 1, 1, 1, 1, 1, \
920 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
921 fixed, like PIC_OFFSET_TABLE_REGNUM. */
922 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
924 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
925 across SHcompact function calls. We can't tell whether a called
926 function is SHmedia or SHcompact, so we assume it may be when
927 compiling SHmedia code with the 32-bit ABI, since that's the only
928 ABI that can be linked with SHcompact code. */
929 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
931 && GET_MODE_SIZE (MODE) > 4 \
932 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
933 && (REGNO) <= FIRST_GENERAL_REG + 15) \
934 || TARGET_REGISTER_P (REGNO) \
935 || (REGNO) == PR_MEDIA_REG))
937 /* Return number of consecutive hard regs needed starting at reg REGNO
938 to hold something of mode MODE.
939 This is ordinarily the length in words of a value of mode MODE
940 but can be less for certain modes in special long registers.
942 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
944 #define HARD_REGNO_NREGS(REGNO, MODE) \
945 (XD_REGISTER_P (REGNO) \
946 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
947 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
948 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
949 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
951 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
953 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
954 sh_hard_regno_mode_ok ((REGNO), (MODE))
956 /* Value is 1 if it is a good idea to tie two pseudo registers
957 when one has mode MODE1 and one has mode MODE2.
958 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
959 for any hard reg, then this must be 0 for correct output.
960 That's the case for xd registers: we don't hold SFmode values in
961 them, so we can't tie an SFmode pseudos with one in another
962 floating-point mode. */
964 #define MODES_TIEABLE_P(MODE1, MODE2) \
965 ((MODE1) == (MODE2) \
967 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
968 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
969 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
970 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
971 && (GET_MODE_SIZE (MODE2) <= 4)) \
972 : ((MODE1) != SFmode && (MODE2) != SFmode))))
974 /* A C expression that is nonzero if hard register NEW_REG can be
975 considered for use as a rename register for OLD_REG register */
977 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
978 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
980 /* Specify the registers used for certain standard purposes.
981 The values of these macros are register numbers. */
983 /* Define this if the program counter is overloaded on a register. */
984 /* #define PC_REGNUM 15*/
986 /* Register to use for pushing function arguments. */
987 #define STACK_POINTER_REGNUM SP_REG
989 /* Base register for access to local variables of the function. */
990 #define HARD_FRAME_POINTER_REGNUM FP_REG
992 /* Base register for access to local variables of the function. */
993 #define FRAME_POINTER_REGNUM 153
995 /* Fake register that holds the address on the stack of the
996 current function's return address. */
997 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
999 /* Register to hold the addressing base for position independent
1000 code access to data items. */
1001 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1003 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1005 /* Definitions for register eliminations.
1007 We have three registers that can be eliminated on the SH. First, the
1008 frame pointer register can often be eliminated in favor of the stack
1009 pointer register. Secondly, the argument pointer register can always be
1010 eliminated; it is replaced with either the stack or frame pointer.
1011 Third, there is the return address pointer, which can also be replaced
1012 with either the stack or the frame pointer. */
1014 /* This is an array of structures. Each structure initializes one pair
1015 of eliminable registers. The "from" register number is given first,
1016 followed by "to". Eliminations of the same "from" register are listed
1017 in order of preference. */
1019 /* If you add any registers here that are not actually hard registers,
1020 and that have any alternative of elimination that doesn't always
1021 apply, you need to amend calc_live_regs to exclude it, because
1022 reload spills all eliminable registers where it sees an
1023 can_eliminate == 0 entry, thus making them 'live' .
1024 If you add any hard registers that can be eliminated in different
1025 ways, you have to patch reload to spill them only when all alternatives
1026 of elimination fail. */
1028 #define ELIMINABLE_REGS \
1029 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1030 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1031 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1032 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1033 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1034 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1035 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1037 /* Define the offset between two registers, one to be eliminated, and the other
1038 its replacement, at the start of a routine. */
1040 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1041 OFFSET = initial_elimination_offset ((FROM), (TO))
1043 /* Base register for access to arguments of the function. */
1044 #define ARG_POINTER_REGNUM AP_REG
1046 /* Register in which the static-chain is passed to a function. */
1047 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1049 /* Don't default to pcc-struct-return, because we have already specified
1050 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1053 #define DEFAULT_PCC_STRUCT_RETURN 0
1055 #define SHMEDIA_REGS_STACK_ADJUST() \
1056 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1057 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1058 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1062 /* Define the classes of registers for register constraints in the
1063 machine description. Also define ranges of constants.
1065 One of the classes must always be named ALL_REGS and include all hard regs.
1066 If there is more than one class, another class must be named NO_REGS
1067 and contain no registers.
1069 The name GENERAL_REGS must be the name of a class (or an alias for
1070 another name such as ALL_REGS). This is the class of registers
1071 that is allowed by "g" or "r" in a register constraint.
1072 Also, registers outside this class are allocated only when
1073 instructions express preferences for them.
1075 The classes must be numbered in nondecreasing order; that is,
1076 a larger-numbered class must never be contained completely
1077 in a smaller-numbered class.
1079 For any two classes, it is very desirable that there be another
1080 class that represents their union. */
1082 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1083 be used as the destination of some of the arithmetic ops. There are
1084 also some special purpose registers; the T bit register, the
1085 Procedure Return Register and the Multiply Accumulate Registers. */
1086 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1087 reg_class_subunion. We don't want to have an actual union class
1088 of these, because it would only be used when both classes are calculated
1089 to give the same cost, but there is only one FPUL register.
1090 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1091 applying to the actual instruction alternative considered. E.g., the
1092 y/r alternative of movsi_ie is considered to have no more cost that
1093 the r/r alternative, which is patently untrue. */
1117 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1119 /* Give names of register classes as strings for dump file. */
1120 #define REG_CLASS_NAMES \
1135 "GENERAL_FP_REGS", \
1136 "GENERAL_DF_REGS", \
1141 /* Define which registers fit in which classes.
1142 This is an initializer for a vector of HARD_REG_SET
1143 of length N_REG_CLASSES. */
1145 #define REG_CLASS_CONTENTS \
1148 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1150 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1152 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1154 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1158 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1159 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1160 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1161 /* GENERAL_REGS: */ \
1162 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1164 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1166 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1167 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1168 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1170 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1172 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1173 /* GENERAL_FP_REGS: */ \
1174 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1175 /* GENERAL_DF_REGS: */ \
1176 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1177 /* TARGET_REGS: */ \
1178 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1180 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1183 /* The same information, inverted:
1184 Return the class number of the smallest class containing
1185 reg number REGNO. This could be a conditional expression
1186 or could index an array. */
1188 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1189 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1191 /* The following macro defines cover classes for Integrated Register
1192 Allocator. Cover classes is a set of non-intersected register
1193 classes covering all hard registers used for register allocation
1194 purpose. Any move between two registers of a cover class should be
1195 cheaper than load or store of the registers. The macro value is
1196 array of register classes with LIM_REG_CLASSES used as the end
1199 #define IRA_COVER_CLASSES \
1201 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1202 FPUL_REGS, LIM_REG_CLASSES \
1205 /* When defined, the compiler allows registers explicitly used in the
1206 rtl to be used as spill registers but prevents the compiler from
1207 extending the lifetime of these registers. */
1209 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1211 /* The order in which register should be allocated. */
1212 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1213 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1214 spilled or used otherwise, we better have the FP_REGS allocated first. */
1215 #define REG_ALLOC_ORDER \
1216 {/* Caller-saved FPRs */ \
1217 65, 66, 67, 68, 69, 70, 71, 64, \
1218 72, 73, 74, 75, 80, 81, 82, 83, \
1219 84, 85, 86, 87, 88, 89, 90, 91, \
1220 92, 93, 94, 95, 96, 97, 98, 99, \
1221 /* Callee-saved FPRs */ \
1222 76, 77, 78, 79,100,101,102,103, \
1223 104,105,106,107,108,109,110,111, \
1224 112,113,114,115,116,117,118,119, \
1225 120,121,122,123,124,125,126,127, \
1226 136,137,138,139,140,141,142,143, \
1228 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1229 1, 2, 3, 7, 6, 5, 4, 0, \
1230 8, 9, 17, 19, 20, 21, 22, 23, \
1231 36, 37, 38, 39, 40, 41, 42, 43, \
1233 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1234 10, 11, 12, 13, 14, 18, \
1235 /* SH5 callee-saved GPRs */ \
1236 28, 29, 30, 31, 32, 33, 34, 35, \
1237 44, 45, 46, 47, 48, 49, 50, 51, \
1238 52, 53, 54, 55, 56, 57, 58, 59, \
1240 /* SH5 branch target registers */ \
1241 128,129,130,131,132,133,134,135, \
1242 /* Fixed registers */ \
1243 15, 16, 24, 25, 26, 27, 63,144, \
1244 145,146,147,148,149,152,153 }
1246 /* The class value for index registers, and the one for base regs. */
1247 #define INDEX_REG_CLASS \
1248 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1249 #define BASE_REG_CLASS GENERAL_REGS
1251 /* Defines for sh.md and constraints.md. */
1253 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1254 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1255 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1256 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1257 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1258 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1259 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1260 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1262 #define CONST_OK_FOR_J16(VALUE) \
1263 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1264 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1266 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1267 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1269 /* Given an rtx X being reloaded into a reg required to be
1270 in class CLASS, return the class of reg to actually use.
1271 In general this is just CLASS; but on some machines
1272 in some cases it is preferable to use a more restrictive class. */
1274 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1275 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1276 && (GET_CODE (X) == CONST_DOUBLE \
1277 || GET_CODE (X) == SYMBOL_REF \
1278 || PIC_ADDR_P (X)) \
1283 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1284 ((((REGCLASS_HAS_FP_REG (CLASS) \
1286 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1287 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1288 && TARGET_FMOVD)))) \
1289 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1291 && FP_REGISTER_P (REGNO (X)))) \
1292 && ! TARGET_SHMEDIA \
1293 && ((MODE) == SFmode || (MODE) == SImode)) \
1295 : (((CLASS) == FPUL_REGS \
1296 || (REGCLASS_HAS_FP_REG (CLASS) \
1297 && ! TARGET_SHMEDIA && MODE == SImode)) \
1300 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1301 || REGNO (X) == T_REG \
1302 || system_reg_operand (X, VOIDmode))))) \
1304 : (((CLASS) == TARGET_REGS \
1305 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1306 && !satisfies_constraint_Csy (X) \
1307 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1309 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1310 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1311 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1313 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1314 && TARGET_REGISTER_P (REGNO (X))) \
1315 ? GENERAL_REGS : (ELSE))
1317 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1318 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1320 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1321 ((REGCLASS_HAS_FP_REG (CLASS) \
1322 && ! TARGET_SHMEDIA \
1323 && immediate_operand ((X), (MODE)) \
1324 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1325 && (MODE) == SFmode && fldi_ok ())) \
1327 : ((CLASS) == FPUL_REGS \
1329 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1330 || REGNO (X) == T_REG)) \
1331 || GET_CODE (X) == PLUS)) \
1333 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1334 ? (satisfies_constraint_I08 (X) \
1337 : ((CLASS) == FPSCR_REGS \
1338 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1339 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1341 : (REGCLASS_HAS_FP_REG (CLASS) \
1343 && immediate_operand ((X), (MODE)) \
1344 && (X) != CONST0_RTX (GET_MODE (X)) \
1345 && GET_MODE (X) != V4SFmode) \
1347 : (((MODE) == QImode || (MODE) == HImode) \
1348 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1350 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1351 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1353 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1356 /* Return the maximum number of consecutive registers
1357 needed to represent mode MODE in a register of class CLASS.
1359 If TARGET_SHMEDIA, we need two FP registers per word.
1360 Otherwise we will need at most one register per word. */
1361 #define CLASS_MAX_NREGS(CLASS, MODE) \
1363 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1364 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1365 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1367 /* If defined, gives a class of registers that cannot be used as the
1368 operand of a SUBREG that changes the mode of the object illegally. */
1369 /* ??? We need to renumber the internal numbers for the frnn registers
1370 when in little endian in order to allow mode size changes. */
1372 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1373 sh_cannot_change_mode_class (FROM, TO, CLASS)
1375 /* Stack layout; function entry, exit and calling. */
1377 /* Define the number of registers that can hold parameters.
1378 These macros are used only in other macro definitions below. */
1380 #define NPARM_REGS(MODE) \
1381 (TARGET_FPU_ANY && (MODE) == SFmode \
1382 ? (TARGET_SH5 ? 12 : 8) \
1383 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1384 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1385 ? (TARGET_SH5 ? 12 : 8) \
1386 : (TARGET_SH5 ? 8 : 4))
1388 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1389 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1391 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1392 #define FIRST_FP_RET_REG FIRST_FP_REG
1394 /* Define this if pushing a word on the stack
1395 makes the stack pointer a smaller address. */
1396 #define STACK_GROWS_DOWNWARD
1398 /* Define this macro to nonzero if the addresses of local variable slots
1399 are at negative offsets from the frame pointer. */
1400 #define FRAME_GROWS_DOWNWARD 1
1402 /* Offset from the frame pointer to the first local variable slot to
1404 #define STARTING_FRAME_OFFSET 0
1406 /* If we generate an insn to push BYTES bytes,
1407 this says how many the stack pointer really advances by. */
1408 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1409 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1410 do correct alignment. */
1412 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1415 /* Offset of first parameter from the argument pointer register value. */
1416 #define FIRST_PARM_OFFSET(FNDECL) 0
1418 /* Value is the number of byte of arguments automatically
1419 popped when returning from a subroutine call.
1420 FUNDECL is the declaration node of the function (as a tree),
1421 FUNTYPE is the data type of the function (as a tree),
1422 or for a library call it is an identifier node for the subroutine name.
1423 SIZE is the number of bytes of arguments passed on the stack.
1425 On the SH, the caller does not pop any of its arguments that were passed
1427 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1429 /* Value is the number of bytes of arguments automatically popped when
1430 calling a subroutine.
1431 CUM is the accumulated argument list.
1433 On SHcompact, the call trampoline pops arguments off the stack. */
1434 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1436 /* Some subroutine macros specific to this machine. */
1438 #define BASE_RETURN_VALUE_REG(MODE) \
1439 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1440 ? FIRST_FP_RET_REG \
1441 : TARGET_FPU_ANY && (MODE) == SCmode \
1442 ? FIRST_FP_RET_REG \
1443 : (TARGET_FPU_DOUBLE \
1444 && ((MODE) == DFmode || (MODE) == SFmode \
1445 || (MODE) == DCmode || (MODE) == SCmode )) \
1446 ? FIRST_FP_RET_REG \
1449 #define BASE_ARG_REG(MODE) \
1450 ((TARGET_SH2E && ((MODE) == SFmode)) \
1451 ? FIRST_FP_PARM_REG \
1452 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1453 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1454 ? FIRST_FP_PARM_REG \
1457 #define FUNCTION_VALUE_REGNO_P(REGNO) sh_function_value_regno_p (REGNO)
1459 /* 1 if N is a possible register number for function argument passing. */
1460 /* ??? There are some callers that pass REGNO as int, and others that pass
1461 it as unsigned. We get warnings unless we do casts everywhere. */
1462 #define FUNCTION_ARG_REGNO_P(REGNO) \
1463 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1464 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1465 || (TARGET_FPU_ANY \
1466 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1467 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1468 + NPARM_REGS (SFmode))))
1470 /* Define a data type for recording info about an argument list
1471 during the scan of that argument list. This data type should
1472 hold all necessary information about the function itself
1473 and about the args processed so far, enough to enable macros
1474 such as FUNCTION_ARG to determine where the next arg should go.
1476 On SH, this is a single integer, which is a number of words
1477 of arguments scanned so far (including the invisible argument,
1478 if any, which holds the structure-value-address).
1479 Thus NARGREGS or more means all following args should go on the stack. */
1481 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1485 /* Nonzero if a prototype is available for the function. */
1487 /* The number of an odd floating-point register, that should be used
1488 for the next argument of type float. */
1489 int free_single_fp_reg;
1490 /* Whether we're processing an outgoing function call. */
1492 /* The number of general-purpose registers that should have been
1493 used to pass partial arguments, that are passed totally on the
1494 stack. On SHcompact, a call trampoline will pop them off the
1495 stack before calling the actual function, and, if the called
1496 function is implemented in SHcompact mode, the incoming arguments
1497 decoder will push such arguments back onto the stack. For
1498 incoming arguments, STACK_REGS also takes into account other
1499 arguments passed by reference, that the decoder will also push
1502 /* The number of general-purpose registers that should have been
1503 used to pass arguments, if the arguments didn't have to be passed
1506 /* Set as by shcompact_byref if the current argument is to be passed
1510 /* call_cookie is a bitmask used by call expanders, as well as
1511 function prologue and epilogues, to allow SHcompact to comply
1512 with the SH5 32-bit ABI, that requires 64-bit registers to be
1513 used even though only the lower 32-bit half is visible in
1514 SHcompact mode. The strategy is to call SHmedia trampolines.
1516 The alternatives for each of the argument-passing registers are
1517 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1518 contents from the address in it; (d) add 8 to it, storing the
1519 result in the next register, then (c); (e) copy it from some
1520 floating-point register,
1522 Regarding copies from floating-point registers, r2 may only be
1523 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1524 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1525 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1526 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1529 The bit mask is structured as follows:
1531 - 1 bit to tell whether to set up a return trampoline.
1533 - 3 bits to count the number consecutive registers to pop off the
1536 - 4 bits for each of r9, r8, r7 and r6.
1538 - 3 bits for each of r5, r4, r3 and r2.
1540 - 3 bits set to 0 (the most significant ones)
1543 1098 7654 3210 9876 5432 1098 7654 3210
1544 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1545 2223 3344 4555 6666 7777 8888 9999 SSS-
1547 - If F is set, the register must be copied from an FP register,
1548 whose number is encoded in the remaining bits.
1550 - Else, if L is set, the register must be loaded from the address
1551 contained in it. If the P bit is *not* set, the address of the
1552 following dword should be computed first, and stored in the
1555 - Else, if P is set, the register alone should be popped off the
1558 - After all this processing, the number of registers represented
1559 in SSS will be popped off the stack. This is an optimization
1560 for pushing/popping consecutive registers, typically used for
1561 varargs and large arguments partially passed in registers.
1563 - If T is set, a return trampoline will be set up for 64-bit
1564 return values to be split into 2 32-bit registers. */
1567 /* This is set to nonzero when the call in question must use the Renesas ABI,
1568 even without the -mrenesas option. */
1572 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1573 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1574 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1575 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1576 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1577 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1578 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1579 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1580 #define CALL_COOKIE_INT_REG(REG, VAL) \
1581 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1582 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1583 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1585 #define CUMULATIVE_ARGS struct sh_args
1587 #define GET_SH_ARG_CLASS(MODE) \
1588 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1590 /* There's no mention of complex float types in the SH5 ABI, so we
1591 should presumably handle them as aggregate types. */ \
1592 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1594 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1595 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1596 ? SH_ARG_FLOAT : SH_ARG_INT)
1598 #define ROUND_ADVANCE(SIZE) \
1599 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1601 /* Round a register number up to a proper boundary for an arg of mode
1604 The SH doesn't care about double alignment, so we only
1605 round doubles to even regs when asked to explicitly. */
1607 #define ROUND_REG(CUM, MODE) \
1608 (((TARGET_ALIGN_DOUBLE \
1609 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1610 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1611 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1612 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1613 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1614 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1616 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1617 for a call to a function whose data type is FNTYPE.
1618 For a library call, FNTYPE is 0.
1620 On SH, the offset always starts at 0: the first parm reg is always
1621 the same reg for a given argument class.
1623 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1625 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1626 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1628 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1629 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1631 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1632 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1633 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1634 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1636 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1637 This macro is only used in this file. */
1639 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1641 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1642 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1643 || ! (AGGREGATE_TYPE_P (TYPE) \
1644 || (!TARGET_FPU_ANY \
1645 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1646 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1647 && ! (CUM).force_mem \
1649 ? ((MODE) == BLKmode \
1650 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1651 + int_size_in_bytes (TYPE)) \
1652 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1653 : ((ROUND_REG((CUM), (MODE)) \
1654 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1655 <= NPARM_REGS (MODE))) \
1656 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1658 /* By accident we got stuck with passing SCmode on SH4 little endian
1659 in two registers that are nominally successive - which is different from
1660 two single SFmode values, where we take endianness translation into
1661 account. That does not work at all if an odd number of registers is
1662 already in use, so that got fixed, but library functions are still more
1663 likely to use complex numbers without mixing them with SFmode arguments
1664 (which in C would have to be structures), so for the sake of ABI
1665 compatibility the way SCmode values are passed when an even number of
1666 FP registers is in use remains different from a pair of SFmode values for
1669 foo (double); a: fr5,fr4
1670 foo (float a, float b); a: fr5 b: fr4
1671 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1672 this should be the other way round...
1673 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1674 #define FUNCTION_ARG_SCmode_WART 1
1676 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1677 register in SHcompact mode, it must be padded in the most
1678 significant end. This means that passing it by reference wouldn't
1679 pad properly on a big-endian machine. In this particular case, we
1680 pass this argument on the stack, in a way that the call trampoline
1681 will load its value into the appropriate register. */
1682 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1683 ((MODE) == BLKmode \
1684 && TARGET_SHCOMPACT \
1685 && ! TARGET_LITTLE_ENDIAN \
1686 && int_size_in_bytes (TYPE) > 4 \
1687 && int_size_in_bytes (TYPE) < 8)
1689 /* Minimum alignment for an argument to be passed by callee-copy
1690 reference. We need such arguments to be aligned to 8 byte
1691 boundaries, because they'll be loaded using quad loads. */
1692 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1694 /* The SH5 ABI requires floating-point arguments to be passed to
1695 functions without a prototype in both an FP register and a regular
1696 register or the stack. When passing the argument in both FP and
1697 general-purpose registers, list the FP register first. */
1698 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1704 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1705 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1706 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1711 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1712 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1713 + (CUM).arg_count[(int) SH_ARG_INT]) \
1714 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1715 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1718 /* The SH5 ABI requires regular registers or stack slots to be
1719 reserved for floating-point arguments. Registers are taken care of
1720 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1721 Unfortunately, there's no way to just reserve a stack slot, so
1722 we'll end up needlessly storing a copy of the argument in the
1723 stack. For incoming arguments, however, the PARALLEL will be
1724 optimized to the register-only form, and the value in the stack
1725 slot won't be used at all. */
1726 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1727 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1728 ? gen_rtx_REG ((MODE), (REG)) \
1729 : gen_rtx_PARALLEL ((MODE), \
1732 (VOIDmode, NULL_RTX, \
1735 (VOIDmode, gen_rtx_REG ((MODE), \
1739 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1741 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1742 || (MODE) == DCmode) \
1743 && ((CUM).arg_count[(int) SH_ARG_INT] \
1744 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1745 : GET_MODE_SIZE (MODE)) \
1746 + 7) / 8) > NPARM_REGS (SImode))
1748 /* Perform any needed actions needed for a function that is receiving a
1749 variable number of arguments. */
1751 /* Call the function profiler with a given profile label.
1752 We use two .aligns, so as to make sure that both the .long is aligned
1753 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1754 from the trapa instruction. */
1756 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1758 if (TARGET_SHMEDIA) \
1760 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1761 fprintf((STREAM), "\ttrapa\tr0\n"); \
1762 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1766 fprintf((STREAM), "\t.align\t2\n"); \
1767 fprintf((STREAM), "\ttrapa\t#33\n"); \
1768 fprintf((STREAM), "\t.align\t2\n"); \
1769 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1773 /* Define this macro if the code for function profiling should come
1774 before the function prologue. Normally, the profiling code comes
1777 #define PROFILE_BEFORE_PROLOGUE
1779 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1780 the stack pointer does not matter. The value is tested only in
1781 functions that have frame pointers.
1782 No definition is equivalent to always zero. */
1784 #define EXIT_IGNORE_STACK 1
1787 On the SH, the trampoline looks like
1788 2 0002 D202 mov.l l2,r2
1789 1 0000 D301 mov.l l1,r3
1792 5 0008 00000000 l1: .long area
1793 6 000c 00000000 l2: .long function */
1795 /* Length in units of the trampoline for entering a nested function. */
1796 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1798 /* Alignment required for a trampoline in bits . */
1799 #define TRAMPOLINE_ALIGNMENT \
1800 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
1801 : TARGET_SHMEDIA ? 256 : 64)
1803 /* A C expression whose value is RTL representing the value of the return
1804 address for the frame COUNT steps up from the current frame.
1805 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1806 can ignore COUNT. */
1808 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1809 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1811 /* A C expression whose value is RTL representing the location of the
1812 incoming return address at the beginning of any function, before the
1813 prologue. This RTL is either a REG, indicating that the return
1814 value is saved in REG, or a MEM representing a location in
1816 #define INCOMING_RETURN_ADDR_RTX \
1817 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1819 /* Addressing modes, and classification of registers for them. */
1820 #define HAVE_POST_INCREMENT TARGET_SH1
1821 #define HAVE_PRE_DECREMENT TARGET_SH1
1823 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1825 #define USE_LOAD_PRE_DECREMENT(mode) 0
1826 #define USE_STORE_POST_INCREMENT(mode) 0
1827 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1830 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1831 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1832 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1834 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1835 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1836 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1838 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1840 /* Macros to check register numbers against specific register classes. */
1842 /* These assume that REGNO is a hard or pseudo reg number.
1843 They give nonzero only if REGNO is a hard reg of the suitable class
1844 or a pseudo reg currently allocated to a suitable hard reg.
1845 Since they use reg_renumber, they are safe only once reg_renumber
1846 has been allocated, which happens in local-alloc.c. */
1848 #define REGNO_OK_FOR_BASE_P(REGNO) \
1849 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1850 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1851 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1853 ? (GENERAL_REGISTER_P (REGNO) \
1854 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1855 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1857 /* Maximum number of registers that can appear in a valid memory
1860 #define MAX_REGS_PER_ADDRESS 2
1862 /* Recognize any constant value that is a valid address. */
1864 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1866 /* Nonzero if the constant value X is a legitimate general operand. */
1867 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
1869 #define LEGITIMATE_CONSTANT_P(X) \
1871 ? ((GET_MODE (X) != DFmode \
1872 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
1873 || (X) == CONST0_RTX (GET_MODE (X)) \
1874 || ! TARGET_SHMEDIA_FPU \
1875 || TARGET_SHMEDIA64) \
1876 : (GET_CODE (X) != CONST_DOUBLE \
1877 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1878 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
1880 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1881 and check its validity for a certain class.
1882 The suitable hard regs are always accepted and all pseudo regs
1883 are also accepted if STRICT is not set. */
1885 /* Nonzero if X is a reg that can be used as a base reg. */
1886 #define REG_OK_FOR_BASE_P(X, STRICT) \
1887 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1888 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1890 /* Nonzero if X is a reg that can be used as an index. */
1891 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1892 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1893 : REGNO (X) == R0_REG) \
1894 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1896 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1897 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1898 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1899 : REGNO (X) == R0_REG && OFFSET == 0) \
1900 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1902 /* Macros for extra constraints. */
1904 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1905 ((GET_CODE ((OP)) == LABEL_REF) \
1906 || (GET_CODE ((OP)) == CONST \
1907 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1908 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1909 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1911 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1913 && !CONST_INT_P (OP) \
1914 && GET_CODE (OP) != CONST_DOUBLE \
1916 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1917 && !PIC_ADDR_P (OP) \
1918 && GET_CODE (OP) != LABEL_REF)))
1920 /* Check whether OP is a datalabel unspec. */
1921 #define DATALABEL_REF_NO_CONST_P(OP) \
1922 (GET_CODE (OP) == UNSPEC \
1923 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1924 && XVECLEN ((OP), 0) == 1 \
1925 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1927 #define GOT_ENTRY_P(OP) \
1928 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1929 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1931 #define GOTPLT_ENTRY_P(OP) \
1932 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1933 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1935 #define UNSPEC_GOTOFF_P(OP) \
1936 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1938 #define GOTOFF_P(OP) \
1939 (GET_CODE (OP) == CONST \
1940 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1941 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1942 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1943 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1945 #define PIC_ADDR_P(OP) \
1946 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1947 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1949 #define PCREL_SYMOFF_P(OP) \
1950 (GET_CODE (OP) == CONST \
1951 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1952 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1954 #define NON_PIC_REFERENCE_P(OP) \
1955 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1956 || (GET_CODE (OP) == CONST \
1957 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1958 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1959 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1960 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1961 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1962 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1963 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1964 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1966 #define PIC_REFERENCE_P(OP) \
1967 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1968 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1970 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1972 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1973 || PCREL_SYMOFF_P (OP)) \
1974 : NON_PIC_REFERENCE_P (OP))
1976 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1977 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1978 || (GET_CODE (X) == SUBREG \
1979 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1980 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1981 && REG_P (SUBREG_REG (X)) \
1982 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1984 /* Since this must be r0, which is a single register class, we must check
1985 SUBREGs more carefully, to be sure that we don't accept one that extends
1986 outside the class. */
1987 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1988 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1989 || (GET_CODE (X) == SUBREG \
1990 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1991 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1992 && REG_P (SUBREG_REG (X)) \
1993 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1995 #ifdef REG_OK_STRICT
1996 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1997 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1999 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
2000 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
2003 #define ALLOW_INDEXED_ADDRESS \
2004 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2006 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, WIN) \
2008 if (sh_legitimate_index_p ((MODE), (OP))) \
2012 /* A C compound statement that attempts to replace X, which is an address
2013 that needs reloading, with a valid memory address for an operand of
2014 mode MODE. WIN is a C statement label elsewhere in the code. */
2016 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2018 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
2022 /* Specify the machine mode that this machine uses
2023 for the index in the tablejump instruction. */
2024 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2026 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2027 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2028 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2029 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2030 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2031 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2034 /* Define as C expression which evaluates to nonzero if the tablejump
2035 instruction expects the table to contain offsets from the address of the
2037 Do not define this if the table should contain absolute addresses. */
2038 #define CASE_VECTOR_PC_RELATIVE 1
2040 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2041 #define FLOAT_TYPE_SIZE 32
2043 /* Since the SH2e has only `float' support, it is desirable to make all
2044 floating point types equivalent to `float'. */
2045 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2047 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH2A_SINGLE_ONLY__) || defined( __SH4_SINGLE_ONLY__)
2048 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2050 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2053 /* 'char' is signed by default. */
2054 #define DEFAULT_SIGNED_CHAR 1
2056 /* The type of size_t unsigned int. */
2057 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2060 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2062 #define WCHAR_TYPE "short unsigned int"
2063 #define WCHAR_TYPE_SIZE 16
2065 #define SH_ELF_WCHAR_TYPE "long int"
2067 /* Max number of bytes we can move from memory to memory
2068 in one reasonably fast instruction. */
2069 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2071 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2072 MOVE_MAX is not a compile-time constant. */
2073 #define MAX_MOVE_MAX 8
2075 /* Max number of bytes we want move_by_pieces to be able to copy
2077 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2079 /* Define if operations between registers always perform the operation
2080 on the full register even if a narrower mode is specified. */
2081 #define WORD_REGISTER_OPERATIONS
2083 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2084 will either zero-extend or sign-extend. The value of this macro should
2085 be the code that says which one of the two operations is implicitly
2086 done, UNKNOWN if none. */
2087 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2088 /* FP registers can load SImode values, but don't implicitly sign-extend
2090 #define LOAD_EXTEND_OP(MODE) \
2091 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2092 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2094 /* Define if loading short immediate values into registers sign extends. */
2095 #define SHORT_IMMEDIATES_SIGN_EXTEND
2097 /* Nonzero if access to memory by bytes is no faster than for words. */
2098 #define SLOW_BYTE_ACCESS 1
2100 /* Immediate shift counts are truncated by the output routines (or was it
2101 the assembler?). Shift counts in a register are truncated by SH. Note
2102 that the native compiler puts too large (> 32) immediate shift counts
2103 into a register and shifts by the register, letting the SH decide what
2104 to do instead of doing that itself. */
2105 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2106 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2107 expects - the sign bit is significant - so it appears that we need to
2108 leave this zero for correct SH3 code. */
2109 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2111 /* All integers have the same format so truncation is easy. */
2112 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2113 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2114 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2116 /* Define this if addresses of constant functions
2117 shouldn't be put through pseudo regs where they can be cse'd.
2118 Desirable on machines where ordinary constants are expensive
2119 but a CALL with constant address is cheap. */
2120 /*#define NO_FUNCTION_CSE 1*/
2122 /* The machine modes of pointers and functions. */
2123 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2124 #define FUNCTION_MODE Pmode
2126 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2127 are actually function calls with some special constraints on arguments
2130 These macros tell reorg that the references to arguments and
2131 register clobbers for insns of type sfunc do not appear to happen
2132 until after the millicode call. This allows reorg to put insns
2133 which set the argument registers into the delay slot of the millicode
2134 call -- thus they act more like traditional CALL_INSNs.
2136 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2137 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2140 #define INSN_SETS_ARE_DELAYED(X) \
2141 ((NONJUMP_INSN_P (X) \
2142 && GET_CODE (PATTERN (X)) != SEQUENCE \
2143 && GET_CODE (PATTERN (X)) != USE \
2144 && GET_CODE (PATTERN (X)) != CLOBBER \
2145 && get_attr_is_sfunc (X)))
2147 #define INSN_REFERENCES_ARE_DELAYED(X) \
2148 ((NONJUMP_INSN_P (X) \
2149 && GET_CODE (PATTERN (X)) != SEQUENCE \
2150 && GET_CODE (PATTERN (X)) != USE \
2151 && GET_CODE (PATTERN (X)) != CLOBBER \
2152 && get_attr_is_sfunc (X)))
2155 /* Position Independent Code. */
2157 /* We can't directly access anything that contains a symbol,
2158 nor can we indirect via the constant pool. */
2159 #define LEGITIMATE_PIC_OPERAND_P(X) \
2160 ((! nonpic_symbol_mentioned_p (X) \
2161 && (GET_CODE (X) != SYMBOL_REF \
2162 || ! CONSTANT_POOL_ADDRESS_P (X) \
2163 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2164 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2166 #define SYMBOLIC_CONST_P(X) \
2167 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2168 && nonpic_symbol_mentioned_p (X))
2170 /* Compute extra cost of moving data between one register class
2173 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2174 uses this information. Hence, the general register <-> floating point
2175 register information here is not used for SFmode. */
2177 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2178 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2179 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2181 #define REGCLASS_HAS_FP_REG(CLASS) \
2182 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2183 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2185 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2186 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2188 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2189 would be so that people with slow memory systems could generate
2190 different code that does fewer memory accesses. */
2192 /* A C expression for the cost of a branch instruction. A value of 1
2193 is the default; other values are interpreted relative to that.
2194 The SH1 does not have delay slots, hence we get a pipeline stall
2195 at every branch. The SH4 is superscalar, so the single delay slot
2196 is not sufficient to keep both pipelines filled. */
2197 #define BRANCH_COST(speed_p, predictable_p) \
2198 (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2200 /* Assembler output control. */
2202 /* A C string constant describing how to begin a comment in the target
2203 assembler language. The compiler assumes that the comment will end at
2204 the end of the line. */
2205 #define ASM_COMMENT_START "!"
2207 #define ASM_APP_ON ""
2208 #define ASM_APP_OFF ""
2209 #define FILE_ASM_OP "\t.file\n"
2210 #define SET_ASM_OP "\t.set\t"
2212 /* How to change between sections. */
2214 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2215 #define DATA_SECTION_ASM_OP "\t.data"
2217 #if defined CRT_BEGIN || defined CRT_END
2218 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2219 # undef TEXT_SECTION_ASM_OP
2220 # if __SHMEDIA__ == 1 && __SH5__ == 32
2221 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2223 # define TEXT_SECTION_ASM_OP "\t.text"
2228 /* If defined, a C expression whose value is a string containing the
2229 assembler operation to identify the following data as
2230 uninitialized global data. If not defined, and neither
2231 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2232 uninitialized global data will be output in the data section if
2233 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2235 #ifndef BSS_SECTION_ASM_OP
2236 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2239 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2240 separate, explicit argument. If you define this macro, it is used
2241 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2242 handling the required alignment of the variable. The alignment is
2243 specified as the number of bits.
2245 Try to use function `asm_output_aligned_bss' defined in file
2246 `varasm.c' when defining this macro. */
2247 #ifndef ASM_OUTPUT_ALIGNED_BSS
2248 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2249 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2252 /* Define this so that jump tables go in same section as the current function,
2253 which could be text or it could be a user defined section. */
2254 #define JUMP_TABLES_IN_TEXT_SECTION 1
2256 #undef DO_GLOBAL_CTORS_BODY
2257 #define DO_GLOBAL_CTORS_BODY \
2259 typedef void (*pfunc) (void); \
2260 extern pfunc __ctors[]; \
2261 extern pfunc __ctors_end[]; \
2263 for (p = __ctors_end; p > __ctors; ) \
2269 #undef DO_GLOBAL_DTORS_BODY
2270 #define DO_GLOBAL_DTORS_BODY \
2272 typedef void (*pfunc) (void); \
2273 extern pfunc __dtors[]; \
2274 extern pfunc __dtors_end[]; \
2276 for (p = __dtors; p < __dtors_end; p++) \
2282 #define ASM_OUTPUT_REG_PUSH(file, v) \
2284 if (TARGET_SHMEDIA) \
2286 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2287 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2290 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2293 #define ASM_OUTPUT_REG_POP(file, v) \
2295 if (TARGET_SHMEDIA) \
2297 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2298 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2301 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2304 /* DBX register number for a given compiler register number. */
2305 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2307 /* svr4.h undefines this macro, yet we really want to use the same numbers
2308 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2309 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2310 register exists, so we should return -1 for invalid register numbers. */
2311 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2313 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2314 used to use the encodings 245..260, but that doesn't make sense:
2315 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2316 the FP registers stay the same when switching between compact and media
2317 mode. Hence, we also need to use the same dwarf frame columns.
2318 Likewise, we need to support unwind information for SHmedia registers
2319 even in compact code. */
2320 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2321 (IN_RANGE ((REGNO), \
2322 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2323 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2324 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2325 : ((int) (REGNO) >= FIRST_FP_REG \
2327 <= (FIRST_FP_REG + \
2328 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2329 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2330 + (TARGET_SH5 ? 77 : 25)) \
2331 : XD_REGISTER_P (REGNO) \
2332 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2333 : TARGET_REGISTER_P (REGNO) \
2334 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2335 : (REGNO) == PR_REG \
2336 ? (TARGET_SH5 ? 18 : 17) \
2337 : (REGNO) == PR_MEDIA_REG \
2338 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2339 : (REGNO) == GBR_REG \
2340 ? (TARGET_SH5 ? 238 : 18) \
2341 : (REGNO) == MACH_REG \
2342 ? (TARGET_SH5 ? 239 : 20) \
2343 : (REGNO) == MACL_REG \
2344 ? (TARGET_SH5 ? 240 : 21) \
2345 : (REGNO) == T_REG \
2346 ? (TARGET_SH5 ? 242 : 22) \
2347 : (REGNO) == FPUL_REG \
2348 ? (TARGET_SH5 ? 244 : 23) \
2349 : (REGNO) == FPSCR_REG \
2350 ? (TARGET_SH5 ? 243 : 24) \
2353 /* This is how to output a reference to a symbol_ref. On SH5,
2354 references to non-code symbols must be preceded by `datalabel'. */
2355 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2358 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2359 fputs ("datalabel ", (FILE)); \
2360 assemble_name ((FILE), XSTR ((SYM), 0)); \
2364 /* This is how to output an assembler line
2365 that says to advance the location counter
2366 to a multiple of 2**LOG bytes. */
2368 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2370 fprintf ((FILE), "\t.align %d\n", (LOG))
2372 /* Globalizing directive for a label. */
2373 #define GLOBAL_ASM_OP "\t.global\t"
2375 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2377 /* Output a relative address table. */
2379 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2380 switch (GET_MODE (BODY)) \
2385 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2389 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2394 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2398 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2403 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2407 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2413 /* Output an absolute table element. */
2415 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2416 if (! optimize || TARGET_BIGTABLE) \
2417 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2419 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2422 /* A C statement to be executed just prior to the output of
2423 assembler code for INSN, to modify the extracted operands so
2424 they will be output differently.
2426 Here the argument OPVEC is the vector containing the operands
2427 extracted from INSN, and NOPERANDS is the number of elements of
2428 the vector which contain meaningful data for this insn.
2429 The contents of this vector are what will be used to convert the insn
2430 template into assembler code, so you can change the assembler output
2431 by changing the contents of the vector. */
2433 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2434 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2436 /* Print operand X (an rtx) in assembler syntax to file FILE.
2437 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2438 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2440 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2442 /* Print a memory address as an operand to reference that memory location. */
2444 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2446 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2447 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
2448 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
2450 /* Recognize machine-specific patterns that may appear within
2451 constants. Used for PIC-specific UNSPECs. */
2452 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2454 if (GET_CODE (X) == UNSPEC) \
2456 switch (XINT ((X), 1)) \
2458 case UNSPEC_DATALABEL: \
2459 fputs ("datalabel ", (STREAM)); \
2460 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2463 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
2464 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2467 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2468 fputs ("@GOT", (STREAM)); \
2470 case UNSPEC_GOTOFF: \
2471 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2472 fputs ("@GOTOFF", (STREAM)); \
2475 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2476 fputs ("@PLT", (STREAM)); \
2478 case UNSPEC_GOTPLT: \
2479 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2480 fputs ("@GOTPLT", (STREAM)); \
2482 case UNSPEC_DTPOFF: \
2483 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2484 fputs ("@DTPOFF", (STREAM)); \
2486 case UNSPEC_GOTTPOFF: \
2487 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2488 fputs ("@GOTTPOFF", (STREAM)); \
2490 case UNSPEC_TPOFF: \
2491 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2492 fputs ("@TPOFF", (STREAM)); \
2494 case UNSPEC_CALLER: \
2497 /* LPCS stands for Label for PIC Call Site. */ \
2498 ASM_GENERATE_INTERNAL_LABEL \
2499 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2500 assemble_name ((STREAM), name); \
2503 case UNSPEC_EXTRACT_S16: \
2504 case UNSPEC_EXTRACT_U16: \
2508 val = XVECEXP (X, 0, 0); \
2509 shift = XVECEXP (X, 0, 1); \
2510 fputc ('(', STREAM); \
2511 if (shift != const0_rtx) \
2512 fputc ('(', STREAM); \
2513 if (GET_CODE (val) == CONST \
2514 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) \
2516 fputc ('(', STREAM); \
2517 output_addr_const (STREAM, val); \
2518 fputc (')', STREAM); \
2521 output_addr_const (STREAM, val); \
2522 if (shift != const0_rtx) \
2524 fputs (" >> ", STREAM); \
2525 output_addr_const (STREAM, shift); \
2526 fputc (')', STREAM); \
2528 fputs (" & 65535)", STREAM); \
2531 case UNSPEC_SYMOFF: \
2532 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2533 fputc ('-', STREAM); \
2534 if (GET_CODE (XVECEXP (X, 0, 1)) == CONST) \
2536 fputc ('(', STREAM); \
2537 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2538 fputc (')', STREAM); \
2541 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2543 case UNSPEC_PCREL_SYMOFF: \
2544 output_addr_const (STREAM, XVECEXP (X, 0, 0)); \
2545 fputs ("-(", STREAM); \
2546 output_addr_const (STREAM, XVECEXP (X, 0, 1)); \
2547 fputs ("-.)", STREAM); \
2559 extern struct rtx_def *sh_compare_op0;
2560 extern struct rtx_def *sh_compare_op1;
2562 /* Which processor to schedule for. The elements of the enumeration must
2563 match exactly the cpu attribute in the sh.md file. */
2565 enum processor_type {
2577 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2578 extern enum processor_type sh_cpu;
2580 extern int optimize; /* needed for gen_casesi. */
2582 enum mdep_reorg_phase_e
2584 SH_BEFORE_MDEP_REORG,
2585 SH_INSERT_USES_LABELS,
2586 SH_SHORTEN_BRANCHES0,
2588 SH_SHORTEN_BRANCHES1,
2592 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2594 /* Handle Renesas compiler's pragmas. */
2595 #define REGISTER_TARGET_PRAGMAS() do { \
2596 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2597 c_register_pragma (0, "trapa", sh_pr_trapa); \
2598 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2601 extern tree sh_deferred_function_attributes;
2602 extern tree *sh_deferred_function_attributes_tail;
2604 /* Set when processing a function with interrupt attribute. */
2606 extern int current_function_interrupt;
2609 /* Instructions with unfilled delay slots take up an
2610 extra two bytes for the nop in the delay slot.
2611 sh-dsp parallel processing insns are four bytes long. */
2613 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2614 (LENGTH) += sh_insn_length_adjustment (X);
2616 /* Define this macro if it is advisable to hold scalars in registers
2617 in a wider mode than that declared by the program. In such cases,
2618 the value is constrained to be within the bounds of the declared
2619 type, but kept valid in the wider mode. The signedness of the
2620 extension may differ from that of the type.
2622 Leaving the unsignedp unchanged gives better code than always setting it
2623 to 0. This is despite the fact that we have only signed char and short
2624 load instructions. */
2625 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2626 if (GET_MODE_CLASS (MODE) == MODE_INT \
2627 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2628 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2629 (MODE) = (TARGET_SH1 ? SImode \
2630 : TARGET_SHMEDIA32 ? SImode : DImode);
2632 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2634 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2636 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2637 and popping arguments. However, we do have push/pop instructions, and
2638 rather limited offsets (4 bits) in load/store instructions, so it isn't
2639 clear if this would give better code. If implemented, should check for
2640 compatibility problems. */
2642 #define SH_DYNAMIC_SHIFT_COST \
2643 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2646 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2648 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2650 #define ACTUAL_NORMAL_MODE(ENTITY) \
2651 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2653 #define NORMAL_MODE(ENTITY) \
2654 (sh_cfun_interrupt_handler_p () \
2655 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2656 : ACTUAL_NORMAL_MODE (ENTITY))
2658 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2660 #define MODE_EXIT(ENTITY) \
2661 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2663 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2664 && (REGNO) == FPSCR_REG)
2666 #define MODE_NEEDED(ENTITY, INSN) \
2667 (recog_memoized (INSN) >= 0 \
2668 ? get_attr_fp_mode (INSN) \
2671 #define MODE_AFTER(MODE, INSN) \
2673 && recog_memoized (INSN) >= 0 \
2674 && get_attr_fp_set (INSN) != FP_SET_NONE \
2675 ? (int) get_attr_fp_set (INSN) \
2678 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2679 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2681 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2682 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2684 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2685 sh_can_redirect_branch ((INSN), (SEQ))
2687 #define DWARF_FRAME_RETURN_COLUMN \
2688 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2690 #define EH_RETURN_DATA_REGNO(N) \
2691 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2693 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2694 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2696 /* We have to distinguish between code and data, so that we apply
2697 datalabel where and only where appropriate. Use sdataN for data. */
2698 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2699 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2700 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2701 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2703 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2704 indirect are handled automatically. */
2705 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2707 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2708 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2710 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2711 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2716 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2717 /* SH constant pool breaks the devices in crtstuff.c to control section
2718 in where code resides. We have to write it as asm code. */
2719 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2720 asm (SECTION_OP "\n\
2726 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2727 2:\n" TEXT_SECTION_ASM_OP);
2728 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2730 /* FIXME: middle-end support for highpart optimizations is missing. */
2731 #define high_life_started reload_in_progress
2733 #endif /* ! GCC_SH_H */
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