1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
45 #include "langhooks.h"
47 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
49 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
50 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
52 /* These are some macros to abstract register modes. */
53 #define CONST_OK_FOR_ADD(size) \
54 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
55 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
56 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
57 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
59 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
60 int current_function_interrupt;
62 /* ??? The pragma interrupt support will not work for SH3. */
63 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
64 output code for the next function appropriate for an interrupt handler. */
67 /* This is set by the trap_exit attribute for functions. It specifies
68 a trap number to be used in a trapa instruction at function exit
69 (instead of an rte instruction). */
72 /* This is used by the sp_switch attribute for functions. It specifies
73 a variable holding the address of the stack the interrupt function
74 should switch to/from at entry/exit. */
77 /* This is set by #pragma trapa, and is similar to the above, except that
78 the compiler doesn't emit code to preserve all registers. */
79 static int pragma_trapa;
81 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
82 which has a separate set of low regs for User and Supervisor modes.
83 This should only be used for the lowest level of interrupts. Higher levels
84 of interrupts must save the registers in case they themselves are
86 int pragma_nosave_low_regs;
88 /* This is used for communication between SETUP_INCOMING_VARARGS and
89 sh_expand_prologue. */
90 int current_function_anonymous_args;
92 /* Global variables for machine-dependent things. */
94 /* Which cpu are we scheduling for. */
95 enum processor_type sh_cpu;
97 /* Saved operands from the last compare to use when we generate an scc
103 /* Provides the class number of the smallest class containing
106 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
108 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
109 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
110 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
125 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
126 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
141 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
142 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
143 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
144 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
145 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
149 char sh_register_names[FIRST_PSEUDO_REGISTER] \
150 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
152 char sh_additional_register_names[ADDREGNAMES_SIZE] \
153 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
154 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
156 /* Provide reg_class from a letter such as appears in the machine
159 const enum reg_class reg_class_from_letter[] =
161 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
162 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
163 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
164 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
165 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
166 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
167 /* y */ FPUL_REGS, /* z */ R0_REGS
170 int assembler_dialect;
172 static void split_branches PARAMS ((rtx));
173 static int branch_dest PARAMS ((rtx));
174 static void force_into PARAMS ((rtx, rtx));
175 static void print_slot PARAMS ((rtx));
176 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
177 static void dump_table PARAMS ((rtx));
178 static int hi_const PARAMS ((rtx));
179 static int broken_move PARAMS ((rtx));
180 static int mova_p PARAMS ((rtx));
181 static rtx find_barrier PARAMS ((int, rtx, rtx));
182 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
183 static rtx gen_block_redirect PARAMS ((rtx, int, int));
184 static void output_stack_adjust PARAMS ((int, rtx, int, rtx (*) (rtx)));
185 static rtx frame_insn PARAMS ((rtx));
186 static rtx push PARAMS ((int));
187 static void pop PARAMS ((int));
188 static void push_regs PARAMS ((HOST_WIDE_INT *));
189 static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
190 static void mark_use PARAMS ((rtx, rtx *));
191 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
192 static rtx mark_constant_pool_use PARAMS ((rtx));
193 const struct attribute_spec sh_attribute_table[];
194 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
195 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
196 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
197 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
198 static void sh_insert_attributes PARAMS ((tree, tree *));
199 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
200 static int sh_use_dfa_interface PARAMS ((void));
201 static int sh_issue_rate PARAMS ((void));
203 static bool sh_cannot_modify_jumps_p PARAMS ((void));
204 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
206 static void sh_encode_section_info PARAMS ((tree, int));
207 static const char *sh_strip_name_encoding PARAMS ((const char *));
208 static void sh_init_builtins (void);
209 static void sh_media_init_builtins (void);
210 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
213 /* Initialize the GCC target structure. */
214 #undef TARGET_ATTRIBUTE_TABLE
215 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
217 /* The next two are used for debug info when compiling with -gdwarf. */
218 #undef TARGET_ASM_UNALIGNED_HI_OP
219 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
220 #undef TARGET_ASM_UNALIGNED_SI_OP
221 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
223 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
224 #undef TARGET_ASM_UNALIGNED_DI_OP
225 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
226 #undef TARGET_ASM_ALIGNED_DI_OP
227 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
229 #undef TARGET_ASM_FUNCTION_EPILOGUE
230 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
232 #undef TARGET_INSERT_ATTRIBUTES
233 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
235 #undef TARGET_SCHED_ADJUST_COST
236 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
238 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
239 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
241 #undef TARGET_SCHED_ISSUE_RATE
242 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
244 #undef TARGET_CANNOT_MODIFY_JUMPS_P
245 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
247 #undef TARGET_MS_BITFIELD_LAYOUT_P
248 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
250 #undef TARGET_ENCODE_SECTION_INFO
251 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
252 #undef TARGET_STRIP_NAME_ENCODING
253 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
255 #undef TARGET_INIT_BUILTINS
256 #define TARGET_INIT_BUILTINS sh_init_builtins
257 #undef TARGET_EXPAND_BUILTIN
258 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
260 struct gcc_target targetm = TARGET_INITIALIZER;
262 /* Print the operand address in x to the stream. */
265 print_operand_address (stream, x)
269 switch (GET_CODE (x))
273 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
278 rtx base = XEXP (x, 0);
279 rtx index = XEXP (x, 1);
281 switch (GET_CODE (index))
284 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
285 reg_names[true_regnum (base)]);
291 int base_num = true_regnum (base);
292 int index_num = true_regnum (index);
294 fprintf (stream, "@(r0,%s)",
295 reg_names[MAX (base_num, index_num)]);
307 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
311 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
315 x = mark_constant_pool_use (x);
316 output_addr_const (stream, x);
321 /* Print operand x (an rtx) in assembler syntax to file stream
322 according to modifier code.
324 '.' print a .s if insn needs delay slot
325 ',' print LOCAL_LABEL_PREFIX
326 '@' print trap, rte or rts depending upon pragma interruptness
327 '#' output a nop if there is nothing to put in the delay slot
328 ''' print likelyhood suffix (/u for unlikely).
329 'O' print a constant without the #
330 'R' print the LSW of a dp value - changes if in little endian
331 'S' print the MSW of a dp value - changes if in little endian
332 'T' print the next word of a dp value - same as 'R' in big endian mode.
333 'M' print an `x' if `m' will print `base,index'.
334 'N' print 'r63' if the operand is (const_int 0).
335 'm' print a pair `base,offset' or `base,index', for LD and ST.
336 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
337 'o' output an operator. */
340 print_operand (stream, x, code)
349 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
350 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
353 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
357 fprintf (stream, "trapa #%d", trap_exit);
358 else if (sh_cfun_interrupt_handler_p ())
359 fprintf (stream, "rte");
361 fprintf (stream, "rts");
364 /* Output a nop if there's nothing in the delay slot. */
365 if (dbr_sequence_length () == 0)
366 fprintf (stream, "\n\tnop");
370 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
372 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
373 fputs ("/u", stream);
377 x = mark_constant_pool_use (x);
378 output_addr_const (stream, x);
381 fputs (reg_names[REGNO (x) + LSW], (stream));
384 fputs (reg_names[REGNO (x) + MSW], (stream));
387 /* Next word of a double. */
388 switch (GET_CODE (x))
391 fputs (reg_names[REGNO (x) + 1], (stream));
394 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
395 && GET_CODE (XEXP (x, 0)) != POST_INC)
396 x = adjust_address (x, SImode, 4);
397 print_operand_address (stream, XEXP (x, 0));
404 switch (GET_CODE (x))
406 case PLUS: fputs ("add", stream); break;
407 case MINUS: fputs ("sub", stream); break;
408 case MULT: fputs ("mul", stream); break;
409 case DIV: fputs ("div", stream); break;
410 case EQ: fputs ("eq", stream); break;
411 case NE: fputs ("ne", stream); break;
412 case GT: case LT: fputs ("gt", stream); break;
413 case GE: case LE: fputs ("ge", stream); break;
414 case GTU: case LTU: fputs ("gtu", stream); break;
415 case GEU: case LEU: fputs ("geu", stream); break;
421 if (GET_CODE (x) == MEM
422 && GET_CODE (XEXP (x, 0)) == PLUS
423 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
424 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
429 if (GET_CODE (x) != MEM)
432 switch (GET_CODE (x))
436 print_operand (stream, x, 0);
437 fputs (", 0", stream);
441 print_operand (stream, XEXP (x, 0), 0);
442 fputs (", ", stream);
443 print_operand (stream, XEXP (x, 1), 0);
452 if (x == CONST0_RTX (GET_MODE (x)))
454 fprintf ((stream), "r63");
459 if (GET_CODE (x) == CONST_INT)
461 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
468 switch (GET_CODE (x))
470 /* FIXME: We need this on SHmedia32 because reload generates
471 some sign-extended HI or QI loads into DImode registers
472 but, because Pmode is SImode, the address ends up with a
473 subreg:SI of the DImode register. Maybe reload should be
474 fixed so as to apply alter_subreg to such loads? */
476 if (SUBREG_BYTE (x) != 0
477 || GET_CODE (SUBREG_REG (x)) != REG)
484 if (FP_REGISTER_P (REGNO (x))
485 && GET_MODE (x) == V16SFmode)
486 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
487 else if (FP_REGISTER_P (REGNO (x))
488 && GET_MODE (x) == V4SFmode)
489 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
490 else if (GET_CODE (x) == REG
491 && GET_MODE (x) == V2SFmode)
492 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
493 else if (FP_REGISTER_P (REGNO (x))
494 && GET_MODE_SIZE (GET_MODE (x)) > 4)
495 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
497 fputs (reg_names[REGNO (x)], (stream));
501 output_address (XEXP (x, 0));
506 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
507 && GET_MODE (XEXP (x, 0)) == DImode
508 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
509 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
511 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
514 if (GET_CODE (val) == ASHIFTRT)
517 if (GET_CODE (XEXP (val, 0)) == CONST)
519 output_addr_const (stream, XEXP (val, 0));
520 if (GET_CODE (XEXP (val, 0)) == CONST)
522 fputs (" >> ", stream);
523 output_addr_const (stream, XEXP (val, 1));
528 if (GET_CODE (val) == CONST)
530 output_addr_const (stream, val);
531 if (GET_CODE (val) == CONST)
534 fputs (" & 65535)", stream);
542 output_addr_const (stream, x);
549 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
551 force_into (value, target)
554 value = force_operand (value, target);
555 if (! rtx_equal_p (value, target))
556 emit_insn (gen_move_insn (target, value));
559 /* Emit code to perform a block move. Choose the best method.
561 OPERANDS[0] is the destination.
562 OPERANDS[1] is the source.
563 OPERANDS[2] is the size.
564 OPERANDS[3] is the alignment safe to use. */
567 expand_block_move (operands)
570 int align = INTVAL (operands[3]);
571 int constp = (GET_CODE (operands[2]) == CONST_INT);
572 int bytes = (constp ? INTVAL (operands[2]) : 0);
574 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
575 alignment, or if it isn't a multiple of 4 bytes, then fail. */
576 if (! constp || align < 4 || (bytes % 4 != 0))
583 else if (bytes == 12)
588 rtx r4 = gen_rtx (REG, SImode, 4);
589 rtx r5 = gen_rtx (REG, SImode, 5);
591 entry_name = get_identifier ("__movstrSI12_i4");
593 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
594 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
595 force_into (XEXP (operands[0], 0), r4);
596 force_into (XEXP (operands[1], 0), r5);
597 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
600 else if (! TARGET_SMALLCODE)
606 rtx r4 = gen_rtx (REG, SImode, 4);
607 rtx r5 = gen_rtx (REG, SImode, 5);
608 rtx r6 = gen_rtx (REG, SImode, 6);
610 entry_name = get_identifier (bytes & 4
612 : "__movstr_i4_even");
613 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
614 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
615 force_into (XEXP (operands[0], 0), r4);
616 force_into (XEXP (operands[1], 0), r5);
619 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
620 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
632 rtx r4 = gen_rtx_REG (SImode, 4);
633 rtx r5 = gen_rtx_REG (SImode, 5);
635 sprintf (entry, "__movstrSI%d", bytes);
636 entry_name = get_identifier (entry);
637 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
638 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
639 force_into (XEXP (operands[0], 0), r4);
640 force_into (XEXP (operands[1], 0), r5);
641 emit_insn (gen_block_move_real (func_addr_rtx));
645 /* This is the same number of bytes as a memcpy call, but to a different
646 less common function name, so this will occasionally use more space. */
647 if (! TARGET_SMALLCODE)
652 int final_switch, while_loop;
653 rtx r4 = gen_rtx_REG (SImode, 4);
654 rtx r5 = gen_rtx_REG (SImode, 5);
655 rtx r6 = gen_rtx_REG (SImode, 6);
657 entry_name = get_identifier ("__movstr");
658 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
659 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
660 force_into (XEXP (operands[0], 0), r4);
661 force_into (XEXP (operands[1], 0), r5);
663 /* r6 controls the size of the move. 16 is decremented from it
664 for each 64 bytes moved. Then the negative bit left over is used
665 as an index into a list of move instructions. e.g., a 72 byte move
666 would be set up with size(r6) = 14, for one iteration through the
667 big while loop, and a switch of -2 for the last part. */
669 final_switch = 16 - ((bytes / 4) % 16);
670 while_loop = ((bytes / 4) / 16 - 1) * 16;
671 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
672 emit_insn (gen_block_lump_real (func_addr_rtx));
679 /* Prepare operands for a move define_expand; specifically, one of the
680 operands must be in a register. */
683 prepare_move_operands (operands, mode)
685 enum machine_mode mode;
687 if ((mode == SImode || mode == DImode) && flag_pic)
690 if (SYMBOLIC_CONST_P (operands[1]))
692 if (GET_CODE (operands[0]) == MEM)
693 operands[1] = force_reg (Pmode, operands[1]);
694 else if (GET_CODE (operands[1]) == LABEL_REF
695 && target_reg_operand (operands[0], mode))
699 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
700 operands[1] = legitimize_pic_address (operands[1], mode, temp);
703 else if (GET_CODE (operands[1]) == CONST
704 && GET_CODE (XEXP (operands[1], 0)) == PLUS
705 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
707 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
708 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
710 operands[1] = expand_binop (mode, add_optab, temp,
711 XEXP (XEXP (operands[1], 0), 1),
712 no_new_pseudos ? temp
713 : gen_reg_rtx (Pmode),
718 if (! reload_in_progress && ! reload_completed)
720 /* Copy the source to a register if both operands aren't registers. */
721 if (! register_operand (operands[0], mode)
722 && ! register_operand (operands[1], mode))
723 operands[1] = copy_to_mode_reg (mode, operands[1]);
725 /* This case can happen while generating code to move the result
726 of a library call to the target. Reject `st r0,@(rX,rY)' because
727 reload will fail to find a spill register for rX, since r0 is already
728 being used for the source. */
729 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
730 && GET_CODE (operands[0]) == MEM
731 && GET_CODE (XEXP (operands[0], 0)) == PLUS
732 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
733 operands[1] = copy_to_mode_reg (mode, operands[1]);
739 /* Prepare the operands for an scc instruction; make sure that the
740 compare has been done. */
742 prepare_scc_operands (code)
745 rtx t_reg = gen_rtx_REG (SImode, T_REG);
746 enum rtx_code oldcode = code;
747 enum machine_mode mode;
749 /* First need a compare insn. */
753 /* It isn't possible to handle this case. */
772 rtx tmp = sh_compare_op0;
773 sh_compare_op0 = sh_compare_op1;
774 sh_compare_op1 = tmp;
777 mode = GET_MODE (sh_compare_op0);
778 if (mode == VOIDmode)
779 mode = GET_MODE (sh_compare_op1);
781 sh_compare_op0 = force_reg (mode, sh_compare_op0);
782 if ((code != EQ && code != NE
783 && (sh_compare_op1 != const0_rtx
784 || code == GTU || code == GEU || code == LTU || code == LEU))
785 || (mode == DImode && sh_compare_op1 != const0_rtx)
786 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
787 sh_compare_op1 = force_reg (mode, sh_compare_op1);
789 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
790 (mode == SFmode ? emit_sf_insn : emit_df_insn)
791 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
792 gen_rtx (SET, VOIDmode, t_reg,
793 gen_rtx (code, SImode,
794 sh_compare_op0, sh_compare_op1)),
795 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
797 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
798 gen_rtx (code, SImode, sh_compare_op0,
804 /* Called from the md file, set up the operands of a compare instruction. */
807 from_compare (operands, code)
811 enum machine_mode mode = GET_MODE (sh_compare_op0);
813 if (mode == VOIDmode)
814 mode = GET_MODE (sh_compare_op1);
817 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
819 /* Force args into regs, since we can't use constants here. */
820 sh_compare_op0 = force_reg (mode, sh_compare_op0);
821 if (sh_compare_op1 != const0_rtx
822 || code == GTU || code == GEU
823 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
824 sh_compare_op1 = force_reg (mode, sh_compare_op1);
826 if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
828 from_compare (operands, GT);
829 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
832 insn = gen_rtx_SET (VOIDmode,
833 gen_rtx_REG (SImode, T_REG),
834 gen_rtx (code, SImode, sh_compare_op0,
836 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
838 insn = gen_rtx (PARALLEL, VOIDmode,
840 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
841 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
847 /* Functions to output assembly code. */
849 /* Return a sequence of instructions to perform DI or DF move.
851 Since the SH cannot move a DI or DF in one instruction, we have
852 to take care when we see overlapping source and dest registers. */
855 output_movedouble (insn, operands, mode)
856 rtx insn ATTRIBUTE_UNUSED;
858 enum machine_mode mode;
860 rtx dst = operands[0];
861 rtx src = operands[1];
863 if (GET_CODE (dst) == MEM
864 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
865 return "mov.l %T1,%0\n\tmov.l %1,%0";
867 if (register_operand (dst, mode)
868 && register_operand (src, mode))
870 if (REGNO (src) == MACH_REG)
871 return "sts mach,%S0\n\tsts macl,%R0";
873 /* When mov.d r1,r2 do r2->r3 then r1->r2;
874 when mov.d r1,r0 do r1->r0 then r2->r1. */
876 if (REGNO (src) + 1 == REGNO (dst))
877 return "mov %T1,%T0\n\tmov %1,%0";
879 return "mov %1,%0\n\tmov %T1,%T0";
881 else if (GET_CODE (src) == CONST_INT)
883 if (INTVAL (src) < 0)
884 output_asm_insn ("mov #-1,%S0", operands);
886 output_asm_insn ("mov #0,%S0", operands);
890 else if (GET_CODE (src) == MEM)
893 int dreg = REGNO (dst);
894 rtx inside = XEXP (src, 0);
896 if (GET_CODE (inside) == REG)
897 ptrreg = REGNO (inside);
898 else if (GET_CODE (inside) == SUBREG)
899 ptrreg = subreg_regno (inside);
900 else if (GET_CODE (inside) == PLUS)
902 ptrreg = REGNO (XEXP (inside, 0));
903 /* ??? A r0+REG address shouldn't be possible here, because it isn't
904 an offsettable address. Unfortunately, offsettable addresses use
905 QImode to check the offset, and a QImode offsettable address
906 requires r0 for the other operand, which is not currently
907 supported, so we can't use the 'o' constraint.
908 Thus we must check for and handle r0+REG addresses here.
909 We punt for now, since this is likely very rare. */
910 if (GET_CODE (XEXP (inside, 1)) == REG)
913 else if (GET_CODE (inside) == LABEL_REF)
914 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
915 else if (GET_CODE (inside) == POST_INC)
916 return "mov.l %1,%0\n\tmov.l %1,%T0";
920 /* Work out the safe way to copy. Copy into the second half first. */
922 return "mov.l %T1,%T0\n\tmov.l %1,%0";
925 return "mov.l %1,%0\n\tmov.l %T1,%T0";
928 /* Print an instruction which would have gone into a delay slot after
929 another instruction, but couldn't because the other instruction expanded
930 into a sequence where putting the slot insn at the end wouldn't work. */
936 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
938 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
942 output_far_jump (insn, op)
946 struct { rtx lab, reg, op; } this;
947 rtx braf_base_lab = NULL_RTX;
950 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
952 this.lab = gen_label_rtx ();
956 && offset - get_attr_length (insn) <= 32766)
959 jump = "mov.w %O0,%1; braf %1";
967 jump = "mov.l %O0,%1; braf %1";
969 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
972 jump = "mov.l %O0,%1; jmp @%1";
974 /* If we have a scratch register available, use it. */
975 if (GET_CODE (PREV_INSN (insn)) == INSN
976 && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
978 this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
979 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
980 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
981 output_asm_insn (jump, &this.lab);
982 if (dbr_sequence_length ())
983 print_slot (final_sequence);
985 output_asm_insn ("nop", 0);
989 /* Output the delay slot insn first if any. */
990 if (dbr_sequence_length ())
991 print_slot (final_sequence);
993 this.reg = gen_rtx_REG (SImode, 13);
994 /* We must keep the stack aligned to 8-byte boundaries on SH5.
995 Fortunately, MACL is fixed and call-clobbered, and we never
996 need its value across jumps, so save r13 in it instead of in
999 output_asm_insn ("lds r13, macl", 0);
1001 output_asm_insn ("mov.l r13,@-r15", 0);
1002 output_asm_insn (jump, &this.lab);
1004 output_asm_insn ("sts macl, r13", 0);
1006 output_asm_insn ("mov.l @r15+,r13", 0);
1008 if (far && flag_pic && TARGET_SH2)
1010 braf_base_lab = gen_label_rtx ();
1011 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1012 CODE_LABEL_NUMBER (braf_base_lab));
1015 output_asm_insn (".align 2", 0);
1016 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1018 if (far && flag_pic)
1021 this.lab = braf_base_lab;
1022 output_asm_insn (".long %O2-%O0", &this.lab);
1025 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1029 /* Local label counter, used for constants in the pool and inside
1030 pattern branches. */
1032 static int lf = 100;
1034 /* Output code for ordinary branches. */
1037 output_branch (logic, insn, operands)
1042 switch (get_attr_length (insn))
1045 /* This can happen if filling the delay slot has caused a forward
1046 branch to exceed its range (we could reverse it, but only
1047 when we know we won't overextend other branches; this should
1048 best be handled by relaxation).
1049 It can also happen when other condbranches hoist delay slot insn
1050 from their destination, thus leading to code size increase.
1051 But the branch will still be in the range -4092..+4098 bytes. */
1056 /* The call to print_slot will clobber the operands. */
1057 rtx op0 = operands[0];
1059 /* If the instruction in the delay slot is annulled (true), then
1060 there is no delay slot where we can put it now. The only safe
1061 place for it is after the label. final will do that by default. */
1064 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1066 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1067 ASSEMBLER_DIALECT ? "/" : ".", label);
1068 print_slot (final_sequence);
1071 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1073 output_asm_insn ("bra\t%l0", &op0);
1074 fprintf (asm_out_file, "\tnop\n");
1075 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
1079 /* When relaxing, handle this like a short branch. The linker
1080 will fix it up if it still doesn't fit after relaxation. */
1082 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1084 /* There should be no longer branches now - that would
1085 indicate that something has destroyed the branches set
1086 up in machine_dependent_reorg. */
1092 output_branchy_insn (code, template, insn, operands)
1094 const char *template;
1098 rtx next_insn = NEXT_INSN (insn);
1100 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1102 rtx src = SET_SRC (PATTERN (next_insn));
1103 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1105 /* Following branch not taken */
1106 operands[9] = gen_label_rtx ();
1107 emit_label_after (operands[9], next_insn);
1108 INSN_ADDRESSES_NEW (operands[9],
1109 INSN_ADDRESSES (INSN_UID (next_insn))
1110 + get_attr_length (next_insn));
1115 int offset = (branch_dest (next_insn)
1116 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1117 if (offset >= -252 && offset <= 258)
1119 if (GET_CODE (src) == IF_THEN_ELSE)
1121 src = XEXP (src, 1);
1127 operands[9] = gen_label_rtx ();
1128 emit_label_after (operands[9], insn);
1129 INSN_ADDRESSES_NEW (operands[9],
1130 INSN_ADDRESSES (INSN_UID (insn))
1131 + get_attr_length (insn));
1136 output_ieee_ccmpeq (insn, operands)
1137 rtx insn, *operands;
1139 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1142 /* Output to FILE the start of the assembler file. */
1145 output_file_start (file)
1148 output_file_directive (file, main_input_filename);
1150 /* Switch to the data section so that the coffsem symbol
1151 isn't in the text section. */
1154 if (TARGET_LITTLE_ENDIAN)
1155 fprintf (file, "\t.little\n");
1157 if (TARGET_SHCOMPACT)
1158 fprintf (file, "\t.mode\tSHcompact\n");
1159 else if (TARGET_SHMEDIA)
1160 fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1161 TARGET_SHMEDIA64 ? 64 : 32);
1164 /* Actual number of instructions used to make a shift by N. */
1165 static const char ashiftrt_insns[] =
1166 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1168 /* Left shift and logical right shift are the same. */
1169 static const char shift_insns[] =
1170 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1172 /* Individual shift amounts needed to get the above length sequences.
1173 One bit right shifts clobber the T bit, so when possible, put one bit
1174 shifts in the middle of the sequence, so the ends are eligible for
1175 branch delay slots. */
1176 static const short shift_amounts[32][5] = {
1177 {0}, {1}, {2}, {2, 1},
1178 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1179 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1180 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1181 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1182 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1183 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1184 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1186 /* Likewise, but for shift amounts < 16, up to three highmost bits
1187 might be clobbered. This is typically used when combined with some
1188 kind of sign or zero extension. */
1190 static const char ext_shift_insns[] =
1191 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1193 static const short ext_shift_amounts[32][4] = {
1194 {0}, {1}, {2}, {2, 1},
1195 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1196 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1197 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1198 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1199 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1200 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1201 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1203 /* Assuming we have a value that has been sign-extended by at least one bit,
1204 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1205 to shift it by N without data loss, and quicker than by other means? */
1206 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1208 /* This is used in length attributes in sh.md to help compute the length
1209 of arbitrary constant shift instructions. */
1212 shift_insns_rtx (insn)
1215 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1216 int shift_count = INTVAL (XEXP (set_src, 1));
1217 enum rtx_code shift_code = GET_CODE (set_src);
1222 return ashiftrt_insns[shift_count];
1225 return shift_insns[shift_count];
1231 /* Return the cost of a shift. */
1242 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1244 if (GET_MODE (x) == DImode
1245 && GET_CODE (XEXP (x, 1)) == CONST_INT
1246 && INTVAL (XEXP (x, 1)) == 1)
1249 /* Everything else is invalid, because there is no pattern for it. */
1252 /* If shift by a non constant, then this will be expensive. */
1253 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1254 return SH_DYNAMIC_SHIFT_COST;
1256 value = INTVAL (XEXP (x, 1));
1258 /* Otherwise, return the true cost in instructions. */
1259 if (GET_CODE (x) == ASHIFTRT)
1261 int cost = ashiftrt_insns[value];
1262 /* If SH3, then we put the constant in a reg and use shad. */
1263 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1264 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1268 return shift_insns[value];
1271 /* Return the cost of an AND operation. */
1279 /* Anding with a register is a single cycle and instruction. */
1280 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1283 i = INTVAL (XEXP (x, 1));
1287 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1288 && CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1289 || EXTRA_CONSTRAINT_S (XEXP (x, 1)))
1295 /* These constants are single cycle extu.[bw] instructions. */
1296 if (i == 0xff || i == 0xffff)
1298 /* Constants that can be used in an and immediate instruction is a single
1299 cycle, but this requires r0, so make it a little more expensive. */
1300 if (CONST_OK_FOR_L (i))
1302 /* Constants that can be loaded with a mov immediate and an and.
1303 This case is probably unnecessary. */
1304 if (CONST_OK_FOR_I (i))
1306 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1307 This case is probably unnecessary. */
1311 /* Return the cost of an addition or a subtraction. */
1317 /* Adding a register is a single cycle insn. */
1318 if (GET_CODE (XEXP (x, 1)) == REG
1319 || GET_CODE (XEXP (x, 1)) == SUBREG)
1322 /* Likewise for small constants. */
1323 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1324 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1328 switch (GET_CODE (XEXP (x, 1)))
1333 return TARGET_SHMEDIA64 ? 5 : 3;
1336 if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1338 else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16))
1340 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1348 /* Any other constant requires a 2 cycle pc-relative load plus an
1353 /* Return the cost of a multiply. */
1356 rtx x ATTRIBUTE_UNUSED;
1363 /* We have a mul insn, so we can never take more than the mul and the
1364 read of the mac reg, but count more because of the latency and extra
1366 if (TARGET_SMALLCODE)
1371 /* If we're aiming at small code, then just count the number of
1372 insns in a multiply call sequence. */
1373 if (TARGET_SMALLCODE)
1376 /* Otherwise count all the insns in the routine we'd be calling too. */
1380 /* Code to expand a shift. */
1383 gen_ashift (type, n, reg)
1388 /* Negative values here come from the shift_amounts array. */
1401 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1405 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1407 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1410 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1415 /* Same for HImode */
1418 gen_ashift_hi (type, n, reg)
1423 /* Negative values here come from the shift_amounts array. */
1437 /* We don't have HImode right shift operations because using the
1438 ordinary 32 bit shift instructions for that doesn't generate proper
1439 zero/sign extension.
1440 gen_ashift_hi is only called in contexts where we know that the
1441 sign extension works out correctly. */
1444 if (GET_CODE (reg) == SUBREG)
1446 offset = SUBREG_BYTE (reg);
1447 reg = SUBREG_REG (reg);
1449 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1453 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1458 /* Output RTL to split a constant shift into its component SH constant
1459 shift instructions. */
1462 gen_shifty_op (code, operands)
1466 int value = INTVAL (operands[2]);
1469 /* Truncate the shift count in case it is out of bounds. */
1470 value = value & 0x1f;
1474 if (code == LSHIFTRT)
1476 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1477 emit_insn (gen_movt (operands[0]));
1480 else if (code == ASHIFT)
1482 /* There is a two instruction sequence for 31 bit left shifts,
1483 but it requires r0. */
1484 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1486 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1487 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1492 else if (value == 0)
1494 /* This can happen when not optimizing. We must output something here
1495 to prevent the compiler from aborting in final.c after the try_split
1497 emit_insn (gen_nop ());
1501 max = shift_insns[value];
1502 for (i = 0; i < max; i++)
1503 gen_ashift (code, shift_amounts[value][i], operands[0]);
1506 /* Same as above, but optimized for values where the topmost bits don't
1510 gen_shifty_hi_op (code, operands)
1514 int value = INTVAL (operands[2]);
1516 void (*gen_fun) PARAMS ((int, int, rtx));
1518 /* This operation is used by and_shl for SImode values with a few
1519 high bits known to be cleared. */
1523 emit_insn (gen_nop ());
1527 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1530 max = ext_shift_insns[value];
1531 for (i = 0; i < max; i++)
1532 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1535 /* When shifting right, emit the shifts in reverse order, so that
1536 solitary negative values come first. */
1537 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1538 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1541 /* Output RTL for an arithmetic right shift. */
1543 /* ??? Rewrite to use super-optimizer sequences. */
1546 expand_ashiftrt (operands)
1557 if (GET_CODE (operands[2]) != CONST_INT)
1559 rtx count = copy_to_mode_reg (SImode, operands[2]);
1560 emit_insn (gen_negsi2 (count, count));
1561 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1564 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1565 > 1 + SH_DYNAMIC_SHIFT_COST)
1568 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1569 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1573 if (GET_CODE (operands[2]) != CONST_INT)
1576 value = INTVAL (operands[2]) & 31;
1580 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1583 else if (value >= 16 && value <= 19)
1585 wrk = gen_reg_rtx (SImode);
1586 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1589 gen_ashift (ASHIFTRT, 1, wrk);
1590 emit_move_insn (operands[0], wrk);
1593 /* Expand a short sequence inline, longer call a magic routine. */
1594 else if (value <= 5)
1596 wrk = gen_reg_rtx (SImode);
1597 emit_move_insn (wrk, operands[1]);
1599 gen_ashift (ASHIFTRT, 1, wrk);
1600 emit_move_insn (operands[0], wrk);
1604 wrk = gen_reg_rtx (Pmode);
1606 /* Load the value into an arg reg and call a helper. */
1607 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1608 sprintf (func, "__ashiftrt_r4_%d", value);
1609 func_name = get_identifier (func);
1610 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1611 emit_move_insn (wrk, sym);
1612 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1613 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1618 sh_dynamicalize_shift_p (count)
1621 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1624 /* Try to find a good way to implement the combiner pattern
1625 [(set (match_operand:SI 0 "register_operand" "r")
1626 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1627 (match_operand:SI 2 "const_int_operand" "n"))
1628 (match_operand:SI 3 "const_int_operand" "n"))) .
1629 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1630 return 0 for simple right / left or left/right shift combination.
1631 return 1 for a combination of shifts with zero_extend.
1632 return 2 for a combination of shifts with an AND that needs r0.
1633 return 3 for a combination of shifts with an AND that needs an extra
1634 scratch register, when the three highmost bits of the AND mask are clear.
1635 return 4 for a combination of shifts with an AND that needs an extra
1636 scratch register, when any of the three highmost bits of the AND mask
1638 If ATTRP is set, store an initial right shift width in ATTRP[0],
1639 and the instruction length in ATTRP[1] . These values are not valid
1641 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1642 shift_amounts for the last shift value that is to be used before the
1645 shl_and_kind (left_rtx, mask_rtx, attrp)
1646 rtx left_rtx, mask_rtx;
1649 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1650 int left = INTVAL (left_rtx), right;
1652 int cost, best_cost = 10000;
1653 int best_right = 0, best_len = 0;
1657 if (left < 0 || left > 31)
1659 if (GET_CODE (mask_rtx) == CONST_INT)
1660 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1662 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1663 /* Can this be expressed as a right shift / left shift pair ? */
1664 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1665 right = exact_log2 (lsb);
1666 mask2 = ~(mask + lsb - 1);
1667 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1668 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1670 best_cost = shift_insns[right] + shift_insns[right + left];
1671 /* mask has no trailing zeroes <==> ! right */
1672 else if (! right && mask2 == ~(lsb2 - 1))
1674 int late_right = exact_log2 (lsb2);
1675 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1677 /* Try to use zero extend */
1678 if (mask2 == ~(lsb2 - 1))
1682 for (width = 8; width <= 16; width += 8)
1684 /* Can we zero-extend right away? */
1685 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1688 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1689 if (cost < best_cost)
1700 /* ??? Could try to put zero extend into initial right shift,
1701 or even shift a bit left before the right shift. */
1702 /* Determine value of first part of left shift, to get to the
1703 zero extend cut-off point. */
1704 first = width - exact_log2 (lsb2) + right;
1705 if (first >= 0 && right + left - first >= 0)
1707 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1708 + ext_shift_insns[right + left - first];
1709 if (cost < best_cost)
1721 /* Try to use r0 AND pattern */
1722 for (i = 0; i <= 2; i++)
1726 if (! CONST_OK_FOR_L (mask >> i))
1728 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1729 if (cost < best_cost)
1734 best_len = cost - 1;
1737 /* Try to use a scratch register to hold the AND operand. */
1738 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
1739 for (i = 0; i <= 2; i++)
1743 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1744 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1745 if (cost < best_cost)
1750 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1756 attrp[0] = best_right;
1757 attrp[1] = best_len;
1762 /* This is used in length attributes of the unnamed instructions
1763 corresponding to shl_and_kind return values of 1 and 2. */
1765 shl_and_length (insn)
1768 rtx set_src, left_rtx, mask_rtx;
1771 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1772 left_rtx = XEXP (XEXP (set_src, 0), 1);
1773 mask_rtx = XEXP (set_src, 1);
1774 shl_and_kind (left_rtx, mask_rtx, attributes);
1775 return attributes[1];
1778 /* This is used in length attribute of the and_shl_scratch instruction. */
1781 shl_and_scr_length (insn)
1784 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1785 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1786 rtx op = XEXP (set_src, 0);
1787 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1788 op = XEXP (XEXP (op, 0), 0);
1789 return len + shift_insns[INTVAL (XEXP (op, 1))];
1792 /* Generating rtl? */
1793 extern int rtx_equal_function_value_matters;
1795 /* Generate rtl for instructions for which shl_and_kind advised a particular
1796 method of generating them, i.e. returned zero. */
1799 gen_shl_and (dest, left_rtx, mask_rtx, source)
1800 rtx dest, left_rtx, mask_rtx, source;
1803 unsigned HOST_WIDE_INT mask;
1804 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1805 int right, total_shift;
1806 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
1808 right = attributes[0];
1809 total_shift = INTVAL (left_rtx) + right;
1810 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1817 int first = attributes[2];
1822 emit_insn ((mask << right) <= 0xff
1823 ? gen_zero_extendqisi2(dest,
1824 gen_lowpart (QImode, source))
1825 : gen_zero_extendhisi2(dest,
1826 gen_lowpart (HImode, source)));
1830 emit_insn (gen_movsi (dest, source));
1834 operands[2] = GEN_INT (right);
1835 gen_shifty_hi_op (LSHIFTRT, operands);
1839 operands[2] = GEN_INT (first);
1840 gen_shifty_hi_op (ASHIFT, operands);
1841 total_shift -= first;
1845 emit_insn (mask <= 0xff
1846 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1847 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1848 if (total_shift > 0)
1850 operands[2] = GEN_INT (total_shift);
1851 gen_shifty_hi_op (ASHIFT, operands);
1856 shift_gen_fun = gen_shifty_op;
1858 /* If the topmost bit that matters is set, set the topmost bits
1859 that don't matter. This way, we might be able to get a shorter
1861 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
1862 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1864 /* Don't expand fine-grained when combining, because that will
1865 make the pattern fail. */
1866 if (rtx_equal_function_value_matters
1867 || reload_in_progress || reload_completed)
1871 /* Cases 3 and 4 should be handled by this split
1872 only while combining */
1877 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1880 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1885 operands[2] = GEN_INT (total_shift);
1886 shift_gen_fun (ASHIFT, operands);
1893 if (kind != 4 && total_shift < 16)
1895 neg = -ext_shift_amounts[total_shift][1];
1897 neg -= ext_shift_amounts[total_shift][2];
1901 emit_insn (gen_and_shl_scratch (dest, source,
1904 GEN_INT (total_shift + neg),
1906 emit_insn (gen_movsi (dest, dest));
1913 /* Try to find a good way to implement the combiner pattern
1914 [(set (match_operand:SI 0 "register_operand" "=r")
1915 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1916 (match_operand:SI 2 "const_int_operand" "n")
1917 (match_operand:SI 3 "const_int_operand" "n")
1919 (clobber (reg:SI T_REG))]
1920 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1921 return 0 for simple left / right shift combination.
1922 return 1 for left shift / 8 bit sign extend / left shift.
1923 return 2 for left shift / 16 bit sign extend / left shift.
1924 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1925 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1926 return 5 for left shift / 16 bit sign extend / right shift
1927 return 6 for < 8 bit sign extend / left shift.
1928 return 7 for < 8 bit sign extend / left shift / single right shift.
1929 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1932 shl_sext_kind (left_rtx, size_rtx, costp)
1933 rtx left_rtx, size_rtx;
1936 int left, size, insize, ext;
1937 int cost, best_cost;
1940 left = INTVAL (left_rtx);
1941 size = INTVAL (size_rtx);
1942 insize = size - left;
1945 /* Default to left / right shift. */
1947 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1950 /* 16 bit shift / sign extend / 16 bit shift */
1951 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1952 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1953 below, by alternative 3 or something even better. */
1954 if (cost < best_cost)
1960 /* Try a plain sign extend between two shifts. */
1961 for (ext = 16; ext >= insize; ext -= 8)
1965 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1966 if (cost < best_cost)
1968 kind = ext / (unsigned) 8;
1972 /* Check if we can do a sloppy shift with a final signed shift
1973 restoring the sign. */
1974 if (EXT_SHIFT_SIGNED (size - ext))
1975 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1976 /* If not, maybe it's still cheaper to do the second shift sloppy,
1977 and do a final sign extend? */
1978 else if (size <= 16)
1979 cost = ext_shift_insns[ext - insize] + 1
1980 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1983 if (cost < best_cost)
1985 kind = ext / (unsigned) 8 + 2;
1989 /* Check if we can sign extend in r0 */
1992 cost = 3 + shift_insns[left];
1993 if (cost < best_cost)
1998 /* Try the same with a final signed shift. */
2001 cost = 3 + ext_shift_insns[left + 1] + 1;
2002 if (cost < best_cost)
2011 /* Try to use a dynamic shift. */
2012 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2013 if (cost < best_cost)
2024 /* Function to be used in the length attribute of the instructions
2025 implementing this pattern. */
2028 shl_sext_length (insn)
2031 rtx set_src, left_rtx, size_rtx;
2034 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2035 left_rtx = XEXP (XEXP (set_src, 0), 1);
2036 size_rtx = XEXP (set_src, 1);
2037 shl_sext_kind (left_rtx, size_rtx, &cost);
2041 /* Generate rtl for this pattern */
2044 gen_shl_sext (dest, left_rtx, size_rtx, source)
2045 rtx dest, left_rtx, size_rtx, source;
2048 int left, size, insize, cost;
2051 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2052 left = INTVAL (left_rtx);
2053 size = INTVAL (size_rtx);
2054 insize = size - left;
2062 int ext = kind & 1 ? 8 : 16;
2063 int shift2 = size - ext;
2065 /* Don't expand fine-grained when combining, because that will
2066 make the pattern fail. */
2067 if (! rtx_equal_function_value_matters
2068 && ! reload_in_progress && ! reload_completed)
2070 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2071 emit_insn (gen_movsi (dest, source));
2075 emit_insn (gen_movsi (dest, source));
2079 operands[2] = GEN_INT (ext - insize);
2080 gen_shifty_hi_op (ASHIFT, operands);
2083 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2084 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2089 operands[2] = GEN_INT (shift2);
2090 gen_shifty_op (ASHIFT, operands);
2097 if (EXT_SHIFT_SIGNED (shift2))
2099 operands[2] = GEN_INT (shift2 + 1);
2100 gen_shifty_op (ASHIFT, operands);
2101 operands[2] = GEN_INT (1);
2102 gen_shifty_op (ASHIFTRT, operands);
2105 operands[2] = GEN_INT (shift2);
2106 gen_shifty_hi_op (ASHIFT, operands);
2110 operands[2] = GEN_INT (-shift2);
2111 gen_shifty_hi_op (LSHIFTRT, operands);
2113 emit_insn (size <= 8
2114 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2115 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2122 if (! rtx_equal_function_value_matters
2123 && ! reload_in_progress && ! reload_completed)
2124 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2128 operands[2] = GEN_INT (16 - insize);
2129 gen_shifty_hi_op (ASHIFT, operands);
2130 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2132 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2134 gen_ashift (ASHIFTRT, 1, dest);
2139 /* Don't expand fine-grained when combining, because that will
2140 make the pattern fail. */
2141 if (! rtx_equal_function_value_matters
2142 && ! reload_in_progress && ! reload_completed)
2144 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2145 emit_insn (gen_movsi (dest, source));
2148 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2149 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2150 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2152 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2153 gen_shifty_op (ASHIFT, operands);
2155 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2163 /* Prefix a symbol_ref name with "datalabel". */
2166 gen_datalabel_ref (sym)
2169 if (GET_CODE (sym) == LABEL_REF)
2170 return gen_rtx_CONST (GET_MODE (sym),
2171 gen_rtx_UNSPEC (GET_MODE (sym),
2175 if (GET_CODE (sym) != SYMBOL_REF)
2178 XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL);
2184 /* The SH cannot load a large constant into a register, constants have to
2185 come from a pc relative load. The reference of a pc relative load
2186 instruction must be less than 1k infront of the instruction. This
2187 means that we often have to dump a constant inside a function, and
2188 generate code to branch around it.
2190 It is important to minimize this, since the branches will slow things
2191 down and make things bigger.
2193 Worst case code looks like:
2211 We fix this by performing a scan before scheduling, which notices which
2212 instructions need to have their operands fetched from the constant table
2213 and builds the table.
2217 scan, find an instruction which needs a pcrel move. Look forward, find the
2218 last barrier which is within MAX_COUNT bytes of the requirement.
2219 If there isn't one, make one. Process all the instructions between
2220 the find and the barrier.
2222 In the above example, we can tell that L3 is within 1k of L1, so
2223 the first move can be shrunk from the 3 insn+constant sequence into
2224 just 1 insn, and the constant moved to L3 to make:
2235 Then the second move becomes the target for the shortening process. */
2239 rtx value; /* Value in table. */
2240 rtx label; /* Label of value. */
2241 rtx wend; /* End of window. */
2242 enum machine_mode mode; /* Mode of value. */
2245 /* The maximum number of constants that can fit into one pool, since
2246 the pc relative range is 0...1020 bytes and constants are at least 4
2249 #define MAX_POOL_SIZE (1020/4)
2250 static pool_node pool_vector[MAX_POOL_SIZE];
2251 static int pool_size;
2252 static rtx pool_window_label;
2253 static int pool_window_last;
2255 /* ??? If we need a constant in HImode which is the truncated value of a
2256 constant we need in SImode, we could combine the two entries thus saving
2257 two bytes. Is this common enough to be worth the effort of implementing
2260 /* ??? This stuff should be done at the same time that we shorten branches.
2261 As it is now, we must assume that all branches are the maximum size, and
2262 this causes us to almost always output constant pools sooner than
2265 /* Add a constant to the pool and return its label. */
2268 add_constant (x, mode, last_value)
2270 enum machine_mode mode;
2274 rtx lab, new, ref, newref;
2276 /* First see if we've already got it. */
2277 for (i = 0; i < pool_size; i++)
2279 if (x->code == pool_vector[i].value->code
2280 && mode == pool_vector[i].mode)
2282 if (x->code == CODE_LABEL)
2284 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2287 if (rtx_equal_p (x, pool_vector[i].value))
2292 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2294 new = gen_label_rtx ();
2295 LABEL_REFS (new) = pool_vector[i].label;
2296 pool_vector[i].label = lab = new;
2298 if (lab && pool_window_label)
2300 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2301 ref = pool_vector[pool_window_last].wend;
2302 LABEL_NEXTREF (newref) = ref;
2303 pool_vector[pool_window_last].wend = newref;
2306 pool_window_label = new;
2307 pool_window_last = i;
2313 /* Need a new one. */
2314 pool_vector[pool_size].value = x;
2315 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2318 lab = gen_label_rtx ();
2319 pool_vector[pool_size].mode = mode;
2320 pool_vector[pool_size].label = lab;
2321 pool_vector[pool_size].wend = NULL_RTX;
2322 if (lab && pool_window_label)
2324 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2325 ref = pool_vector[pool_window_last].wend;
2326 LABEL_NEXTREF (newref) = ref;
2327 pool_vector[pool_window_last].wend = newref;
2330 pool_window_label = lab;
2331 pool_window_last = pool_size;
2336 /* Output the literal table. */
2347 /* Do two passes, first time dump out the HI sized constants. */
2349 for (i = 0; i < pool_size; i++)
2351 pool_node *p = &pool_vector[i];
2353 if (p->mode == HImode)
2357 scan = emit_insn_after (gen_align_2 (), scan);
2360 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2361 scan = emit_label_after (lab, scan);
2362 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2364 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2366 lab = XEXP (ref, 0);
2367 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2370 else if (p->mode == DImode || p->mode == DFmode)
2376 if (TARGET_SHCOMPACT && have_di)
2378 rtx align_insn = NULL_RTX;
2380 scan = emit_label_after (gen_label_rtx (), scan);
2381 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2384 for (i = 0; i < pool_size; i++)
2386 pool_node *p = &pool_vector[i];
2396 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2397 emit_label_before (lab, align_insn);
2398 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2400 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2402 lab = XEXP (ref, 0);
2403 emit_insn_before (gen_consttable_window_end (lab),
2406 delete_insn (align_insn);
2407 align_insn = NULL_RTX;
2412 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2413 scan = emit_label_after (lab, scan);
2414 scan = emit_insn_after (gen_consttable_4 (p->value,
2416 need_align = ! need_align;
2423 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2427 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2428 scan = emit_label_after (lab, scan);
2429 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2437 if (p->mode != HImode)
2439 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2441 lab = XEXP (ref, 0);
2442 scan = emit_insn_after (gen_consttable_window_end (lab),
2451 for (i = 0; i < pool_size; i++)
2453 pool_node *p = &pool_vector[i];
2464 scan = emit_label_after (gen_label_rtx (), scan);
2465 scan = emit_insn_after (gen_align_4 (), scan);
2467 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2468 scan = emit_label_after (lab, scan);
2469 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2477 scan = emit_label_after (gen_label_rtx (), scan);
2478 scan = emit_insn_after (gen_align_4 (), scan);
2480 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2481 scan = emit_label_after (lab, scan);
2482 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2490 if (p->mode != HImode)
2492 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2494 lab = XEXP (ref, 0);
2495 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2500 scan = emit_insn_after (gen_consttable_end (), scan);
2501 scan = emit_barrier_after (scan);
2503 pool_window_label = NULL_RTX;
2504 pool_window_last = 0;
2507 /* Return non-zero if constant would be an ok source for a
2508 mov.w instead of a mov.l. */
2514 return (GET_CODE (src) == CONST_INT
2515 && INTVAL (src) >= -32768
2516 && INTVAL (src) <= 32767);
2519 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2521 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2522 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2523 need to fix it if the input value is CONST_OK_FOR_I. */
2529 if (GET_CODE (insn) == INSN)
2531 rtx pat = PATTERN (insn);
2532 if (GET_CODE (pat) == PARALLEL)
2533 pat = XVECEXP (pat, 0, 0);
2534 if (GET_CODE (pat) == SET
2535 /* We can load any 8 bit value if we don't care what the high
2536 order bits end up as. */
2537 && GET_MODE (SET_DEST (pat)) != QImode
2538 && (CONSTANT_P (SET_SRC (pat))
2539 /* Match mova_const. */
2540 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2541 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2542 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2544 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2545 && (fp_zero_operand (SET_SRC (pat))
2546 || fp_one_operand (SET_SRC (pat)))
2547 /* ??? If this is a -m4 or -m4-single compilation, in general
2548 we don't know the current setting of fpscr, so disable fldi.
2549 There is an exception if this was a register-register move
2550 before reload - and hence it was ascertained that we have
2551 single precision setting - and in a post-reload optimization
2552 we changed this to do a constant load. In that case
2553 we don't have an r0 clobber, hence we must use fldi. */
2554 && (! TARGET_SH4 || TARGET_FMOVD
2555 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2557 && GET_CODE (SET_DEST (pat)) == REG
2558 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2559 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2560 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2571 return (GET_CODE (insn) == INSN
2572 && GET_CODE (PATTERN (insn)) == SET
2573 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2574 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2575 /* Don't match mova_const. */
2576 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2579 /* Find the last barrier from insn FROM which is close enough to hold the
2580 constant pool. If we can't find one, then create one near the end of
2584 find_barrier (num_mova, mova, from)
2595 int leading_mova = num_mova;
2596 rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
2600 /* For HImode: range is 510, add 4 because pc counts from address of
2601 second instruction after this one, subtract 2 for the jump instruction
2602 that we may need to emit before the table, subtract 2 for the instruction
2603 that fills the jump delay slot (in very rare cases, reorg will take an
2604 instruction from after the constant pool or will leave the delay slot
2605 empty). This gives 510.
2606 For SImode: range is 1020, add 4 because pc counts from address of
2607 second instruction after this one, subtract 2 in case pc is 2 byte
2608 aligned, subtract 2 for the jump instruction that we may need to emit
2609 before the table, subtract 2 for the instruction that fills the jump
2610 delay slot. This gives 1018. */
2612 /* The branch will always be shortened now that the reference address for
2613 forward branches is the successor address, thus we need no longer make
2614 adjustments to the [sh]i_limit for -O0. */
2619 while (from && count_si < si_limit && count_hi < hi_limit)
2621 int inc = get_attr_length (from);
2624 if (GET_CODE (from) == CODE_LABEL)
2627 new_align = 1 << label_to_alignment (from);
2628 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2629 new_align = 1 << barrier_align (from);
2635 if (GET_CODE (from) == BARRIER)
2638 found_barrier = from;
2640 /* If we are at the end of the function, or in front of an alignment
2641 instruction, we need not insert an extra alignment. We prefer
2642 this kind of barrier. */
2643 if (barrier_align (from) > 2)
2644 good_barrier = from;
2647 if (broken_move (from))
2650 enum machine_mode mode;
2652 pat = PATTERN (from);
2653 if (GET_CODE (pat) == PARALLEL)
2654 pat = XVECEXP (pat, 0, 0);
2655 src = SET_SRC (pat);
2656 dst = SET_DEST (pat);
2657 mode = GET_MODE (dst);
2659 /* We must explicitly check the mode, because sometimes the
2660 front end will generate code to load unsigned constants into
2661 HImode targets without properly sign extending them. */
2663 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2666 /* We put the short constants before the long constants, so
2667 we must count the length of short constants in the range
2668 for the long constants. */
2669 /* ??? This isn't optimal, but is easy to do. */
2674 /* We dump DF/DI constants before SF/SI ones, because
2675 the limit is the same, but the alignment requirements
2676 are higher. We may waste up to 4 additional bytes
2677 for alignment, and the DF/DI constant may have
2678 another SF/SI constant placed before it. */
2679 if (TARGET_SHCOMPACT
2681 && (mode == DFmode || mode == DImode))
2686 while (si_align > 2 && found_si + si_align - 2 > count_si)
2688 if (found_si > count_si)
2689 count_si = found_si;
2690 found_si += GET_MODE_SIZE (mode);
2692 si_limit -= GET_MODE_SIZE (mode);
2695 /* See the code in machine_dependent_reorg, which has a similar if
2696 statement that generates a new mova insn in many cases. */
2697 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
2707 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
2709 if (found_si > count_si)
2710 count_si = found_si;
2712 else if (GET_CODE (from) == JUMP_INSN
2713 && (GET_CODE (PATTERN (from)) == ADDR_VEC
2714 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
2718 if (barrier_align (next_real_insn (from)) == CACHE_LOG)
2720 /* We have just passed the barrier in front of the
2721 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2722 the ADDR_DIFF_VEC is accessed as data, just like our pool
2723 constants, this is a good opportunity to accommodate what
2724 we have gathered so far.
2725 If we waited any longer, we could end up at a barrier in
2726 front of code, which gives worse cache usage for separated
2727 instruction / data caches. */
2728 good_barrier = found_barrier;
2733 rtx body = PATTERN (from);
2734 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2737 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2738 else if (GET_CODE (from) == JUMP_INSN
2740 && ! TARGET_SMALLCODE)
2746 if (new_align > si_align)
2748 si_limit -= (count_si - 1) & (new_align - si_align);
2749 si_align = new_align;
2751 count_si = (count_si + new_align - 1) & -new_align;
2756 if (new_align > hi_align)
2758 hi_limit -= (count_hi - 1) & (new_align - hi_align);
2759 hi_align = new_align;
2761 count_hi = (count_hi + new_align - 1) & -new_align;
2763 from = NEXT_INSN (from);
2770 /* Try as we might, the leading mova is out of range. Change
2771 it into a load (which will become a pcload) and retry. */
2772 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2773 INSN_CODE (mova) = -1;
2774 return find_barrier (0, 0, mova);
2778 /* Insert the constant pool table before the mova instruction,
2779 to prevent the mova label reference from going out of range. */
2781 good_barrier = found_barrier = barrier_before_mova;
2787 if (good_barrier && next_real_insn (found_barrier))
2788 found_barrier = good_barrier;
2792 /* We didn't find a barrier in time to dump our stuff,
2793 so we'll make one. */
2794 rtx label = gen_label_rtx ();
2796 /* If we exceeded the range, then we must back up over the last
2797 instruction we looked at. Otherwise, we just need to undo the
2798 NEXT_INSN at the end of the loop. */
2799 if (count_hi > hi_limit || count_si > si_limit)
2800 from = PREV_INSN (PREV_INSN (from));
2802 from = PREV_INSN (from);
2804 /* Walk back to be just before any jump or label.
2805 Putting it before a label reduces the number of times the branch
2806 around the constant pool table will be hit. Putting it before
2807 a jump makes it more likely that the bra delay slot will be
2809 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2810 || GET_CODE (from) == CODE_LABEL)
2811 from = PREV_INSN (from);
2813 from = emit_jump_insn_after (gen_jump (label), from);
2814 JUMP_LABEL (from) = label;
2815 LABEL_NUSES (label) = 1;
2816 found_barrier = emit_barrier_after (from);
2817 emit_label_after (label, found_barrier);
2820 return found_barrier;
2823 /* If the instruction INSN is implemented by a special function, and we can
2824 positively find the register that is used to call the sfunc, and this
2825 register is not used anywhere else in this instruction - except as the
2826 destination of a set, return this register; else, return 0. */
2828 sfunc_uses_reg (insn)
2832 rtx pattern, part, reg_part, reg;
2834 if (GET_CODE (insn) != INSN)
2836 pattern = PATTERN (insn);
2837 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
2840 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2842 part = XVECEXP (pattern, 0, i);
2843 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
2848 reg = XEXP (reg_part, 0);
2849 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2851 part = XVECEXP (pattern, 0, i);
2852 if (part == reg_part || GET_CODE (part) == CLOBBER)
2854 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2855 && GET_CODE (SET_DEST (part)) == REG)
2856 ? SET_SRC (part) : part)))
2862 /* See if the only way in which INSN uses REG is by calling it, or by
2863 setting it while calling it. Set *SET to a SET rtx if the register
2867 noncall_uses_reg (reg, insn, set)
2876 reg2 = sfunc_uses_reg (insn);
2877 if (reg2 && REGNO (reg2) == REGNO (reg))
2879 pattern = single_set (insn);
2881 && GET_CODE (SET_DEST (pattern)) == REG
2882 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2886 if (GET_CODE (insn) != CALL_INSN)
2888 /* We don't use rtx_equal_p because we don't care if the mode is
2890 pattern = single_set (insn);
2892 && GET_CODE (SET_DEST (pattern)) == REG
2893 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2899 par = PATTERN (insn);
2900 if (GET_CODE (par) == PARALLEL)
2901 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2903 part = XVECEXP (par, 0, i);
2904 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2907 return reg_mentioned_p (reg, SET_SRC (pattern));
2913 pattern = PATTERN (insn);
2915 if (GET_CODE (pattern) == PARALLEL)
2919 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2920 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2922 pattern = XVECEXP (pattern, 0, 0);
2925 if (GET_CODE (pattern) == SET)
2927 if (reg_mentioned_p (reg, SET_DEST (pattern)))
2929 /* We don't use rtx_equal_p, because we don't care if the
2930 mode is different. */
2931 if (GET_CODE (SET_DEST (pattern)) != REG
2932 || REGNO (reg) != REGNO (SET_DEST (pattern)))
2938 pattern = SET_SRC (pattern);
2941 if (GET_CODE (pattern) != CALL
2942 || GET_CODE (XEXP (pattern, 0)) != MEM
2943 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2949 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2950 general registers. Bits 0..15 mean that the respective registers
2951 are used as inputs in the instruction. Bits 16..31 mean that the
2952 registers 0..15, respectively, are used as outputs, or are clobbered.
2953 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2955 regs_used (x, is_dest)
2964 code = GET_CODE (x);
2969 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2970 << (REGNO (x) + is_dest));
2974 rtx y = SUBREG_REG (x);
2976 if (GET_CODE (y) != REG)
2979 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
2981 subreg_regno_offset (REGNO (y),
2984 GET_MODE (x)) + is_dest));
2988 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
2990 /* If there was a return value, it must have been indicated with USE. */
3005 fmt = GET_RTX_FORMAT (code);
3007 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3012 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3013 used |= regs_used (XVECEXP (x, i, j), is_dest);
3015 else if (fmt[i] == 'e')
3016 used |= regs_used (XEXP (x, i), is_dest);
3021 /* Create an instruction that prevents redirection of a conditional branch
3022 to the destination of the JUMP with address ADDR.
3023 If the branch needs to be implemented as an indirect jump, try to find
3024 a scratch register for it.
3025 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3026 If any preceding insn that doesn't fit into a delay slot is good enough,
3027 pass 1. Pass 2 if a definite blocking insn is needed.
3028 -1 is used internally to avoid deep recursion.
3029 If a blocking instruction is made or recognized, return it. */
3032 gen_block_redirect (jump, addr, need_block)
3034 int addr, need_block;
3037 rtx prev = prev_nonnote_insn (jump);
3040 /* First, check if we already have an instruction that satisfies our need. */
3041 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3043 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3045 if (GET_CODE (PATTERN (prev)) == USE
3046 || GET_CODE (PATTERN (prev)) == CLOBBER
3047 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3049 else if ((need_block &= ~1) < 0)
3051 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3054 /* We can't use JUMP_LABEL here because it might be undefined
3055 when not optimizing. */
3056 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3057 /* If the branch is out of range, try to find a scratch register for it. */
3059 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3063 /* Don't look for the stack pointer as a scratch register,
3064 it would cause trouble if an interrupt occurred. */
3065 unsigned try = 0x7fff, used;
3066 int jump_left = flag_expensive_optimizations + 1;
3068 /* It is likely that the most recent eligible instruction is wanted for
3069 the delay slot. Therefore, find out which registers it uses, and
3070 try to avoid using them. */
3072 for (scan = jump; (scan = PREV_INSN (scan)); )
3076 if (INSN_DELETED_P (scan))
3078 code = GET_CODE (scan);
3079 if (code == CODE_LABEL || code == JUMP_INSN)
3082 && GET_CODE (PATTERN (scan)) != USE
3083 && GET_CODE (PATTERN (scan)) != CLOBBER
3084 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3086 try &= ~regs_used (PATTERN (scan), 0);
3090 for (used = dead = 0, scan = JUMP_LABEL (jump);
3091 (scan = NEXT_INSN (scan)); )
3095 if (INSN_DELETED_P (scan))
3097 code = GET_CODE (scan);
3098 if (GET_RTX_CLASS (code) == 'i')
3100 used |= regs_used (PATTERN (scan), 0);
3101 if (code == CALL_INSN)
3102 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3103 dead |= (used >> 16) & ~used;
3109 if (code == JUMP_INSN)
3111 if (jump_left-- && simplejump_p (scan))
3112 scan = JUMP_LABEL (scan);
3118 /* Mask out the stack pointer again, in case it was
3119 the only 'free' register we have found. */
3122 /* If the immediate destination is still in range, check for possible
3123 threading with a jump beyond the delay slot insn.
3124 Don't check if we are called recursively; the jump has been or will be
3125 checked in a different invocation then. */
3127 else if (optimize && need_block >= 0)
3129 rtx next = next_active_insn (next_active_insn (dest));
3130 if (next && GET_CODE (next) == JUMP_INSN
3131 && GET_CODE (PATTERN (next)) == SET
3132 && recog_memoized (next) == CODE_FOR_jump)
3134 dest = JUMP_LABEL (next);
3136 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3138 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3144 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3146 /* It would be nice if we could convert the jump into an indirect
3147 jump / far branch right now, and thus exposing all constituent
3148 instructions to further optimization. However, reorg uses
3149 simplejump_p to determine if there is an unconditional jump where
3150 it should try to schedule instructions from the target of the
3151 branch; simplejump_p fails for indirect jumps even if they have
3153 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3154 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3156 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3159 else if (need_block)
3160 /* We can't use JUMP_LABEL here because it might be undefined
3161 when not optimizing. */
3162 return emit_insn_before (gen_block_branch_redirect
3163 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3168 #define CONDJUMP_MIN -252
3169 #define CONDJUMP_MAX 262
3172 /* A label (to be placed) in front of the jump
3173 that jumps to our ultimate destination. */
3175 /* Where we are going to insert it if we cannot move the jump any farther,
3176 or the jump itself if we have picked up an existing jump. */
3178 /* The ultimate destination. */
3180 struct far_branch *prev;
3181 /* If the branch has already been created, its address;
3182 else the address of its first prospective user. */
3186 static void gen_far_branch PARAMS ((struct far_branch *));
3187 enum mdep_reorg_phase_e mdep_reorg_phase;
3190 struct far_branch *bp;
3192 rtx insn = bp->insert_place;
3194 rtx label = gen_label_rtx ();
3196 emit_label_after (label, insn);
3199 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3200 LABEL_NUSES (bp->far_label)++;
3203 jump = emit_jump_insn_after (gen_return (), insn);
3204 /* Emit a barrier so that reorg knows that any following instructions
3205 are not reachable via a fall-through path.
3206 But don't do this when not optimizing, since we wouldn't supress the
3207 alignment for the barrier then, and could end up with out-of-range
3208 pc-relative loads. */
3210 emit_barrier_after (jump);
3211 emit_label_after (bp->near_label, insn);
3212 JUMP_LABEL (jump) = bp->far_label;
3213 if (! invert_jump (insn, label, 1))
3215 /* Prevent reorg from undoing our splits. */
3216 gen_block_redirect (jump, bp->address += 2, 2);
3219 /* Fix up ADDR_DIFF_VECs. */
3221 fixup_addr_diff_vecs (first)
3226 for (insn = first; insn; insn = NEXT_INSN (insn))
3228 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3230 if (GET_CODE (insn) != JUMP_INSN
3231 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3233 pat = PATTERN (insn);
3234 vec_lab = XEXP (XEXP (pat, 0), 0);
3236 /* Search the matching casesi_jump_2. */
3237 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3239 if (GET_CODE (prev) != JUMP_INSN)
3241 prevpat = PATTERN (prev);
3242 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3244 x = XVECEXP (prevpat, 0, 1);
3245 if (GET_CODE (x) != USE)
3248 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3252 /* Emit the reference label of the braf where it belongs, right after
3253 the casesi_jump_2 (i.e. braf). */
3254 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3255 emit_label_after (braf_label, prev);
3257 /* Fix up the ADDR_DIF_VEC to be relative
3258 to the reference address of the braf. */
3259 XEXP (XEXP (pat, 0), 0) = braf_label;
3263 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3264 a barrier. Return the base 2 logarithm of the desired alignment. */
3266 barrier_align (barrier_or_label)
3267 rtx barrier_or_label;
3269 rtx next = next_real_insn (barrier_or_label), pat, prev;
3270 int slot, credit, jump_to_next;
3275 pat = PATTERN (next);
3277 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3280 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3281 /* This is a barrier in front of a constant table. */
3284 prev = prev_real_insn (barrier_or_label);
3285 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3287 pat = PATTERN (prev);
3288 /* If this is a very small table, we want to keep the alignment after
3289 the table to the minimum for proper code alignment. */
3290 return ((TARGET_SMALLCODE
3291 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3292 <= (unsigned)1 << (CACHE_LOG - 2)))
3293 ? 1 << TARGET_SHMEDIA : CACHE_LOG);
3296 if (TARGET_SMALLCODE)
3299 if (! TARGET_SH2 || ! optimize)
3302 /* When fixing up pcloads, a constant table might be inserted just before
3303 the basic block that ends with the barrier. Thus, we can't trust the
3304 instruction lengths before that. */
3305 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3307 /* Check if there is an immediately preceding branch to the insn beyond
3308 the barrier. We must weight the cost of discarding useful information
3309 from the current cache line when executing this branch and there is
3310 an alignment, against that of fetching unneeded insn in front of the
3311 branch target when there is no alignment. */
3313 /* There are two delay_slot cases to consider. One is the simple case
3314 where the preceding branch is to the insn beyond the barrier (simple
3315 delay slot filling), and the other is where the preceding branch has
3316 a delay slot that is a duplicate of the insn after the barrier
3317 (fill_eager_delay_slots) and the branch is to the insn after the insn
3318 after the barrier. */
3320 /* PREV is presumed to be the JUMP_INSN for the barrier under
3321 investigation. Skip to the insn before it. */
3322 prev = prev_real_insn (prev);
3324 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3325 credit >= 0 && prev && GET_CODE (prev) == INSN;
3326 prev = prev_real_insn (prev))
3329 if (GET_CODE (PATTERN (prev)) == USE
3330 || GET_CODE (PATTERN (prev)) == CLOBBER)
3332 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3334 prev = XVECEXP (PATTERN (prev), 0, 1);
3335 if (INSN_UID (prev) == INSN_UID (next))
3337 /* Delay slot was filled with insn at jump target. */
3344 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3346 credit -= get_attr_length (prev);
3349 && GET_CODE (prev) == JUMP_INSN
3350 && JUMP_LABEL (prev))
3354 || next_real_insn (JUMP_LABEL (prev)) == next
3355 /* If relax_delay_slots() decides NEXT was redundant
3356 with some previous instruction, it will have
3357 redirected PREV's jump to the following insn. */
3358 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3359 /* There is no upper bound on redundant instructions
3360 that might have been skipped, but we must not put an
3361 alignment where none had been before. */
3362 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3364 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3365 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch))))
3367 rtx pat = PATTERN (prev);
3368 if (GET_CODE (pat) == PARALLEL)
3369 pat = XVECEXP (pat, 0, 0);
3370 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3379 /* If we are inside a phony loop, almost any kind of label can turn up as the
3380 first one in the loop. Aligning a braf label causes incorrect switch
3381 destination addresses; we can detect braf labels because they are
3382 followed by a BARRIER.
3383 Applying loop alignment to small constant or switch tables is a waste
3384 of space, so we suppress this too. */
3386 sh_loop_align (label)
3392 next = next_nonnote_insn (next);
3393 while (next && GET_CODE (next) == CODE_LABEL);
3397 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3398 || recog_memoized (next) == CODE_FOR_consttable_2)
3407 /* Exported to toplev.c.
3409 Do a final pass over the function, just before delayed branch
3413 machine_dependent_reorg (first)
3418 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3419 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3421 /* We must split call insns before introducing `mova's. If we're
3422 optimizing, they'll have already been split. Otherwise, make
3423 sure we don't split them too late. */
3425 split_all_insns_noflow ();
3430 /* If relaxing, generate pseudo-ops to associate function calls with
3431 the symbols they call. It does no harm to not generate these
3432 pseudo-ops. However, when we can generate them, it enables to
3433 linker to potentially relax the jsr to a bsr, and eliminate the
3434 register load and, possibly, the constant pool entry. */
3436 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3439 /* Remove all REG_LABEL notes. We want to use them for our own
3440 purposes. This works because none of the remaining passes
3441 need to look at them.
3443 ??? But it may break in the future. We should use a machine
3444 dependent REG_NOTE, or some other approach entirely. */
3445 for (insn = first; insn; insn = NEXT_INSN (insn))
3451 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3452 remove_note (insn, note);
3456 for (insn = first; insn; insn = NEXT_INSN (insn))
3458 rtx pattern, reg, link, set, scan, dies, label;
3459 int rescan = 0, foundinsn = 0;
3461 if (GET_CODE (insn) == CALL_INSN)
3463 pattern = PATTERN (insn);
3465 if (GET_CODE (pattern) == PARALLEL)
3466 pattern = XVECEXP (pattern, 0, 0);
3467 if (GET_CODE (pattern) == SET)
3468 pattern = SET_SRC (pattern);
3470 if (GET_CODE (pattern) != CALL
3471 || GET_CODE (XEXP (pattern, 0)) != MEM)
3474 reg = XEXP (XEXP (pattern, 0), 0);
3478 reg = sfunc_uses_reg (insn);
3483 if (GET_CODE (reg) != REG)
3486 /* This is a function call via REG. If the only uses of REG
3487 between the time that it is set and the time that it dies
3488 are in function calls, then we can associate all the
3489 function calls with the setting of REG. */
3491 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3493 if (REG_NOTE_KIND (link) != 0)
3495 set = single_set (XEXP (link, 0));
3496 if (set && rtx_equal_p (reg, SET_DEST (set)))
3498 link = XEXP (link, 0);
3505 /* ??? Sometimes global register allocation will have
3506 deleted the insn pointed to by LOG_LINKS. Try
3507 scanning backward to find where the register is set. */
3508 for (scan = PREV_INSN (insn);
3509 scan && GET_CODE (scan) != CODE_LABEL;
3510 scan = PREV_INSN (scan))
3512 if (! INSN_P (scan))
3515 if (! reg_mentioned_p (reg, scan))
3518 if (noncall_uses_reg (reg, scan, &set))
3532 /* The register is set at LINK. */
3534 /* We can only optimize the function call if the register is
3535 being set to a symbol. In theory, we could sometimes
3536 optimize calls to a constant location, but the assembler
3537 and linker do not support that at present. */
3538 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3539 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3542 /* Scan forward from LINK to the place where REG dies, and
3543 make sure that the only insns which use REG are
3544 themselves function calls. */
3546 /* ??? This doesn't work for call targets that were allocated
3547 by reload, since there may not be a REG_DEAD note for the
3551 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3555 /* Don't try to trace forward past a CODE_LABEL if we haven't
3556 seen INSN yet. Ordinarily, we will only find the setting insn
3557 in LOG_LINKS if it is in the same basic block. However,
3558 cross-jumping can insert code labels in between the load and
3559 the call, and can result in situations where a single call
3560 insn may have two targets depending on where we came from. */
3562 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3565 if (! INSN_P (scan))
3568 /* Don't try to trace forward past a JUMP. To optimize
3569 safely, we would have to check that all the
3570 instructions at the jump destination did not use REG. */
3572 if (GET_CODE (scan) == JUMP_INSN)
3575 if (! reg_mentioned_p (reg, scan))
3578 if (noncall_uses_reg (reg, scan, &scanset))
3585 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3587 /* There is a function call to this register other
3588 than the one we are checking. If we optimize
3589 this call, we need to rescan again below. */
3593 /* ??? We shouldn't have to worry about SCANSET here.
3594 We should just be able to check for a REG_DEAD note
3595 on a function call. However, the REG_DEAD notes are
3596 apparently not dependable around libcalls; c-torture
3597 execute/920501-2 is a test case. If SCANSET is set,
3598 then this insn sets the register, so it must have
3599 died earlier. Unfortunately, this will only handle
3600 the cases in which the register is, in fact, set in a
3603 /* ??? We shouldn't have to use FOUNDINSN here.
3604 However, the LOG_LINKS fields are apparently not
3605 entirely reliable around libcalls;
3606 newlib/libm/math/e_pow.c is a test case. Sometimes
3607 an insn will appear in LOG_LINKS even though it is
3608 not the most recent insn which sets the register. */
3612 || find_reg_note (scan, REG_DEAD, reg)))
3621 /* Either there was a branch, or some insn used REG
3622 other than as a function call address. */
3626 /* Create a code label, and put it in a REG_LABEL note on
3627 the insn which sets the register, and on each call insn
3628 which uses the register. In final_prescan_insn we look
3629 for the REG_LABEL notes, and output the appropriate label
3632 label = gen_label_rtx ();
3633 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3635 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3644 scan = NEXT_INSN (scan);
3646 && ((GET_CODE (scan) == CALL_INSN
3647 && reg_mentioned_p (reg, scan))
3648 || ((reg2 = sfunc_uses_reg (scan))
3649 && REGNO (reg2) == REGNO (reg))))
3651 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3653 while (scan != dies);
3659 fixup_addr_diff_vecs (first);
3663 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3664 shorten_branches (first);
3666 /* Scan the function looking for move instructions which have to be
3667 changed to pc-relative loads and insert the literal tables. */
3669 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3670 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3677 else if (GET_CODE (insn) == JUMP_INSN
3678 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3686 /* Some code might have been inserted between the mova and
3687 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3688 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3689 total += get_attr_length (scan);
3691 /* range of mova is 1020, add 4 because pc counts from address of
3692 second instruction after this one, subtract 2 in case pc is 2
3693 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3694 cancels out with alignment effects of the mova itself. */
3697 /* Change the mova into a load, and restart scanning
3698 there. broken_move will then return true for mova. */
3699 SET_SRC (PATTERN (mova))
3700 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3701 INSN_CODE (mova) = -1;
3705 if (broken_move (insn))
3708 /* Scan ahead looking for a barrier to stick the constant table
3710 rtx barrier = find_barrier (num_mova, mova, insn);
3711 rtx last_float_move, last_float = 0, *last_float_addr;
3712 int may_need_align = 1;
3714 if (num_mova && ! mova_p (mova))
3716 /* find_barrier had to change the first mova into a
3717 pcload; thus, we have to start with this new pcload. */
3721 /* Now find all the moves between the points and modify them. */
3722 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3724 if (GET_CODE (scan) == CODE_LABEL)
3726 if (broken_move (scan))
3728 rtx *patp = &PATTERN (scan), pat = *patp;
3732 enum machine_mode mode;
3734 if (GET_CODE (pat) == PARALLEL)
3735 patp = &XVECEXP (pat, 0, 0), pat = *patp;
3736 src = SET_SRC (pat);
3737 dst = SET_DEST (pat);
3738 mode = GET_MODE (dst);
3740 if (mode == SImode && hi_const (src)
3741 && REGNO (dst) != FPUL_REG)
3746 while (GET_CODE (dst) == SUBREG)
3748 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
3749 GET_MODE (SUBREG_REG (dst)),
3752 dst = SUBREG_REG (dst);
3754 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
3757 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3759 /* This must be an insn that clobbers r0. */
3760 rtx clobber = XVECEXP (PATTERN (scan), 0,
3761 XVECLEN (PATTERN (scan), 0) - 1);
3763 if (GET_CODE (clobber) != CLOBBER
3764 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
3768 && reg_set_between_p (r0_rtx, last_float_move, scan))
3770 if (TARGET_SHCOMPACT)
3772 /* The first SFmode constant after a DFmode
3773 constant may be pulled before a sequence
3774 of DFmode constants, so the second SFmode
3775 needs a label, just in case. */
3776 if (GET_MODE_SIZE (mode) == 4)
3778 if (last_float && may_need_align)
3783 && (GET_MODE_SIZE (GET_MODE (last_float))
3784 != GET_MODE_SIZE (mode)))
3787 if (GET_MODE_SIZE (mode) == 4)
3791 lab = add_constant (src, mode, last_float);
3793 emit_insn_before (gen_mova (lab), scan);
3796 /* There will be a REG_UNUSED note for r0 on
3797 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3798 lest reorg:mark_target_live_regs will not
3799 consider r0 to be used, and we end up with delay
3800 slot insn in front of SCAN that clobbers r0. */
3802 = find_regno_note (last_float_move, REG_UNUSED, 0);
3804 /* If we are not optimizing, then there may not be
3807 PUT_MODE (note, REG_INC);
3809 *last_float_addr = r0_inc_rtx;
3811 last_float_move = scan;
3813 newsrc = gen_rtx (MEM, mode,
3814 (((TARGET_SH4 && ! TARGET_FMOVD)
3815 || REGNO (dst) == FPUL_REG)
3818 last_float_addr = &XEXP (newsrc, 0);
3820 /* Remove the clobber of r0. */
3821 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
3822 RTX_UNCHANGING_P (newsrc) = 1;
3824 /* This is a mova needing a label. Create it. */
3825 else if (GET_CODE (src) == UNSPEC
3826 && XINT (src, 1) == UNSPEC_MOVA
3827 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
3829 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
3830 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
3831 newsrc = gen_rtx_UNSPEC (SImode,
3832 gen_rtvec (1, newsrc),
3837 lab = add_constant (src, mode, 0);
3838 newsrc = gen_rtx_MEM (mode,
3839 gen_rtx_LABEL_REF (VOIDmode, lab));
3840 RTX_UNCHANGING_P (newsrc) = 1;
3842 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
3843 INSN_CODE (scan) = -1;
3846 dump_table (barrier);
3851 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
3852 INSN_ADDRESSES_FREE ();
3853 split_branches (first);
3855 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3856 also has an effect on the register that holds the addres of the sfunc.
3857 Insert an extra dummy insn in front of each sfunc that pretends to
3858 use this register. */
3859 if (flag_delayed_branch)
3861 for (insn = first; insn; insn = NEXT_INSN (insn))
3863 rtx reg = sfunc_uses_reg (insn);
3867 emit_insn_before (gen_use_sfunc_addr (reg), insn);
3871 /* fpscr is not actually a user variable, but we pretend it is for the
3872 sake of the previous optimization passes, since we want it handled like
3873 one. However, we don't have any debugging information for it, so turn
3874 it into a non-user variable now. */
3876 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3878 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
3882 get_dest_uid (label, max_uid)
3886 rtx dest = next_real_insn (label);
3889 /* This can happen for an undefined label. */
3891 dest_uid = INSN_UID (dest);
3892 /* If this is a newly created branch redirection blocking instruction,
3893 we cannot index the branch_uid or insn_addresses arrays with its
3894 uid. But then, we won't need to, because the actual destination is
3895 the following branch. */
3896 while (dest_uid >= max_uid)
3898 dest = NEXT_INSN (dest);
3899 dest_uid = INSN_UID (dest);
3901 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
3906 /* Split condbranches that are out of range. Also add clobbers for
3907 scratch registers that are needed in far jumps.
3908 We do this before delay slot scheduling, so that it can take our
3909 newly created instructions into account. It also allows us to
3910 find branches with common targets more easily. */
3913 split_branches (first)
3917 struct far_branch **uid_branch, *far_branch_list = 0;
3918 int max_uid = get_max_uid ();
3920 /* Find out which branches are out of range. */
3921 shorten_branches (first);
3923 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
3924 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
3926 for (insn = first; insn; insn = NEXT_INSN (insn))
3927 if (! INSN_P (insn))
3929 else if (INSN_DELETED_P (insn))
3931 /* Shorten_branches would split this instruction again,
3932 so transform it into a note. */
3933 PUT_CODE (insn, NOTE);
3934 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
3935 NOTE_SOURCE_FILE (insn) = 0;
3937 else if (GET_CODE (insn) == JUMP_INSN
3938 /* Don't mess with ADDR_DIFF_VEC */
3939 && (GET_CODE (PATTERN (insn)) == SET
3940 || GET_CODE (PATTERN (insn)) == RETURN))
3942 enum attr_type type = get_attr_type (insn);
3943 if (type == TYPE_CBRANCH)
3947 if (get_attr_length (insn) > 4)
3949 rtx src = SET_SRC (PATTERN (insn));
3950 rtx olabel = XEXP (XEXP (src, 1), 0);
3951 int addr = INSN_ADDRESSES (INSN_UID (insn));
3953 int dest_uid = get_dest_uid (olabel, max_uid);
3954 struct far_branch *bp = uid_branch[dest_uid];
3956 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3957 the label if the LABEL_NUSES count drops to zero. There is
3958 always a jump_optimize pass that sets these values, but it
3959 proceeds to delete unreferenced code, and then if not
3960 optimizing, to un-delete the deleted instructions, thus
3961 leaving labels with too low uses counts. */
3964 JUMP_LABEL (insn) = olabel;
3965 LABEL_NUSES (olabel)++;
3969 bp = (struct far_branch *) alloca (sizeof *bp);
3970 uid_branch[dest_uid] = bp;
3971 bp->prev = far_branch_list;
3972 far_branch_list = bp;
3974 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
3975 LABEL_NUSES (bp->far_label)++;
3979 label = bp->near_label;
3980 if (! label && bp->address - addr >= CONDJUMP_MIN)
3982 rtx block = bp->insert_place;
3984 if (GET_CODE (PATTERN (block)) == RETURN)
3985 block = PREV_INSN (block);
3987 block = gen_block_redirect (block,
3989 label = emit_label_after (gen_label_rtx (),
3991 bp->near_label = label;
3993 else if (label && ! NEXT_INSN (label))
3995 if (addr + 2 - bp->address <= CONDJUMP_MAX)
3996 bp->insert_place = insn;
3998 gen_far_branch (bp);
4002 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4004 bp->near_label = label = gen_label_rtx ();
4005 bp->insert_place = insn;
4008 if (! redirect_jump (insn, label, 1))
4013 /* get_attr_length (insn) == 2 */
4014 /* Check if we have a pattern where reorg wants to redirect
4015 the branch to a label from an unconditional branch that
4017 /* We can't use JUMP_LABEL here because it might be undefined
4018 when not optimizing. */
4019 /* A syntax error might cause beyond to be NULL_RTX. */
4021 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4025 && (GET_CODE (beyond) == JUMP_INSN
4026 || ((beyond = next_active_insn (beyond))
4027 && GET_CODE (beyond) == JUMP_INSN))
4028 && GET_CODE (PATTERN (beyond)) == SET
4029 && recog_memoized (beyond) == CODE_FOR_jump
4031 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4032 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4034 gen_block_redirect (beyond,
4035 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4038 next = next_active_insn (insn);
4040 if ((GET_CODE (next) == JUMP_INSN
4041 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4042 && GET_CODE (PATTERN (next)) == SET
4043 && recog_memoized (next) == CODE_FOR_jump
4045 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4046 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4048 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4050 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4052 int addr = INSN_ADDRESSES (INSN_UID (insn));
4055 struct far_branch *bp;
4057 if (type == TYPE_JUMP)
4059 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4060 dest_uid = get_dest_uid (far_label, max_uid);
4063 /* Parse errors can lead to labels outside
4065 if (! NEXT_INSN (far_label))
4070 JUMP_LABEL (insn) = far_label;
4071 LABEL_NUSES (far_label)++;
4073 redirect_jump (insn, NULL_RTX, 1);
4077 bp = uid_branch[dest_uid];
4080 bp = (struct far_branch *) alloca (sizeof *bp);
4081 uid_branch[dest_uid] = bp;
4082 bp->prev = far_branch_list;
4083 far_branch_list = bp;
4085 bp->far_label = far_label;
4087 LABEL_NUSES (far_label)++;
4089 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4090 if (addr - bp->address <= CONDJUMP_MAX)
4091 emit_label_after (bp->near_label, PREV_INSN (insn));
4094 gen_far_branch (bp);
4100 bp->insert_place = insn;
4102 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4104 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4107 /* Generate all pending far branches,
4108 and free our references to the far labels. */
4109 while (far_branch_list)
4111 if (far_branch_list->near_label
4112 && ! NEXT_INSN (far_branch_list->near_label))
4113 gen_far_branch (far_branch_list);
4115 && far_branch_list->far_label
4116 && ! --LABEL_NUSES (far_branch_list->far_label))
4117 delete_insn (far_branch_list->far_label);
4118 far_branch_list = far_branch_list->prev;
4121 /* Instruction length information is no longer valid due to the new
4122 instructions that have been generated. */
4123 init_insn_lengths ();
4126 /* Dump out instruction addresses, which is useful for debugging the
4127 constant pool table stuff.
4129 If relaxing, output the label and pseudo-ops used to link together
4130 calls and the instruction which set the registers. */
4132 /* ??? This is unnecessary, and probably should be deleted. This makes
4133 the insn_addresses declaration above unnecessary. */
4135 /* ??? The addresses printed by this routine for insns are nonsense for
4136 insns which are inside of a sequence where none of the inner insns have
4137 variable length. This is because the second pass of shorten_branches
4138 does not bother to update them. */
4141 final_prescan_insn (insn, opvec, noperands)
4143 rtx *opvec ATTRIBUTE_UNUSED;
4144 int noperands ATTRIBUTE_UNUSED;
4146 if (TARGET_DUMPISIZE)
4147 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4153 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4158 pattern = PATTERN (insn);
4159 if (GET_CODE (pattern) == PARALLEL)
4160 pattern = XVECEXP (pattern, 0, 0);
4161 if (GET_CODE (pattern) == CALL
4162 || (GET_CODE (pattern) == SET
4163 && (GET_CODE (SET_SRC (pattern)) == CALL
4164 || get_attr_type (insn) == TYPE_SFUNC)))
4165 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4166 CODE_LABEL_NUMBER (XEXP (note, 0)));
4167 else if (GET_CODE (pattern) == SET)
4168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4169 CODE_LABEL_NUMBER (XEXP (note, 0)));
4176 /* Dump out any constants accumulated in the final pass. These will
4180 output_jump_label_table ()
4186 fprintf (asm_out_file, "\t.align 2\n");
4187 for (i = 0; i < pool_size; i++)
4189 pool_node *p = &pool_vector[i];
4191 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4192 CODE_LABEL_NUMBER (p->label));
4193 output_asm_insn (".long %O0", &p->value);
4201 /* A full frame looks like:
4205 [ if current_function_anonymous_args
4218 local-0 <- fp points here. */
4220 /* Number of bytes pushed for anonymous args, used to pass information
4221 between expand_prologue and expand_epilogue. */
4223 static int extra_push;
4225 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4226 to be adjusted, and TEMP, if nonnegative, holds the register number
4227 of a general register that we may clobber. */
4230 output_stack_adjust (size, reg, temp, emit_fn)
4234 rtx (*emit_fn) PARAMS ((rtx));
4238 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4243 if (CONST_OK_FOR_ADD (size))
4244 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4245 /* Try to do it with two partial adjustments; however, we must make
4246 sure that the stack is properly aligned at all times, in case
4247 an interrupt occurs between the two partial adjustments. */
4248 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4249 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4251 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4252 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4259 /* If TEMP is invalid, we could temporarily save a general
4260 register to MACL. However, there is currently no need
4261 to handle this case, so just abort when we see it. */
4264 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4266 /* If SIZE is negative, subtract the positive value.
4267 This sometimes allows a constant pool entry to be shared
4268 between prologue and epilogue code. */
4271 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4272 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4276 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4277 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4279 if (emit_fn == frame_insn)
4281 = (gen_rtx_EXPR_LIST
4282 (REG_FRAME_RELATED_EXPR,
4283 gen_rtx_SET (VOIDmode, reg,
4284 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4295 RTX_FRAME_RELATED_P (x) = 1;
4299 /* Output RTL to push register RN onto the stack. */
4307 x = gen_push_fpul ();
4308 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4309 && FP_OR_XD_REGISTER_P (rn))
4311 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4313 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4315 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4316 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4318 x = gen_push (gen_rtx_REG (SImode, rn));
4322 = gen_rtx_EXPR_LIST (REG_INC,
4323 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4327 /* Output RTL to pop register RN from the stack. */
4335 x = gen_pop_fpul ();
4336 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4337 && FP_OR_XD_REGISTER_P (rn))
4339 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4341 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4343 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4344 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4346 x = gen_pop (gen_rtx_REG (SImode, rn));
4350 = gen_rtx_EXPR_LIST (REG_INC,
4351 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4354 /* Generate code to push the regs specified in the mask. */
4358 HOST_WIDE_INT *mask;
4362 /* Push PR last; this gives better latencies after the prologue, and
4363 candidates for the return delay slot when there are no general
4364 registers pushed. */
4365 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4366 if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
4368 if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4372 /* Work out the registers which need to be saved, both as a mask and a
4373 count of saved words.
4375 If doing a pragma interrupt function, then push all regs used by the
4376 function, and if we call another function (we can tell by looking at PR),
4377 make sure that all the regs it clobbers are safe too. */
4380 calc_live_regs (count_ptr, live_regs_mask)
4382 HOST_WIDE_INT *live_regs_mask;
4386 int interrupt_handler;
4389 interrupt_handler = sh_cfun_interrupt_handler_p ();
4391 for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
4392 live_regs_mask[count] = 0;
4393 /* If we can save a lot of saves by switching to double mode, do that. */
4394 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4395 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4396 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4397 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4400 target_flags &= ~FPU_SINGLE_BIT;
4403 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4404 knows how to use it. That means the pseudo originally allocated for
4405 the initial value can become the PR_MEDIA_REG hard register, as seen for
4406 execute/20010122-1.c:test9. */
4408 pr_live = regs_ever_live[PR_MEDIA_REG];
4411 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4412 pr_live = (pr_initial
4413 ? REGNO (pr_initial) != (PR_REG) : regs_ever_live[PR_REG]);
4415 /* Force PR to be live if the prologue has to call the SHmedia
4416 argument decoder or register saver. */
4417 if (TARGET_SHCOMPACT
4418 && ((current_function_args_info.call_cookie
4419 & ~ CALL_COOKIE_RET_TRAMP (1))
4420 || current_function_has_nonlocal_label))
4422 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4424 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4426 : (interrupt_handler && ! pragma_trapa)
4427 ? (/* Need to save all the regs ever live. */
4428 (regs_ever_live[reg]
4429 || (call_used_regs[reg]
4430 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4432 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4433 && reg != RETURN_ADDRESS_POINTER_REGNUM
4434 && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
4435 : (/* Only push those regs which are used and need to be saved. */
4436 regs_ever_live[reg] && ! call_used_regs[reg]))
4438 live_regs_mask[reg / 32] |= 1 << (reg % 32);
4439 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4441 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4442 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4444 if (FP_REGISTER_P (reg))
4446 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4448 live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
4449 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4452 else if (XD_REGISTER_P (reg))
4454 /* Must switch to double mode to access these registers. */
4455 target_flags &= ~FPU_SINGLE_BIT;
4464 /* Code to generate prologue and epilogue sequences */
4466 /* PUSHED is the number of bytes that are bing pushed on the
4467 stack for register saves. Return the frame size, padded
4468 appropriately so that the stack stays properly aligned. */
4469 static HOST_WIDE_INT
4470 rounded_frame_size (pushed)
4473 HOST_WIDE_INT size = get_frame_size ();
4474 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4476 return ((size + pushed + align - 1) & -align) - pushed;
4479 /* Choose a call-clobbered target-branch register that remains
4480 unchanged along the whole function. We set it up as the return
4481 value in the prologue. */
4483 sh_media_register_for_return ()
4488 if (! current_function_is_leaf)
4491 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4493 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4494 if (call_used_regs[regno] && ! regs_ever_live[regno])
4501 sh_expand_prologue ()
4503 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4506 int save_flags = target_flags;
4508 current_function_interrupt = sh_cfun_interrupt_handler_p ();
4510 /* We have pretend args if we had an object sent partially in registers
4511 and partially on the stack, e.g. a large structure. */
4512 output_stack_adjust (-current_function_pretend_args_size
4513 - current_function_args_info.stack_regs * 8,
4514 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4518 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
4519 /* We're going to use the PIC register to load the address of the
4520 incoming-argument decoder and/or of the return trampoline from
4521 the GOT, so make sure the PIC register is preserved and
4523 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4525 if (TARGET_SHCOMPACT
4526 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4530 /* First, make all registers with incoming arguments that will
4531 be pushed onto the stack live, so that register renaming
4532 doesn't overwrite them. */
4533 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
4534 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
4535 >= NPARM_REGS (SImode) - reg)
4536 for (; reg < NPARM_REGS (SImode); reg++)
4537 emit_insn (gen_shcompact_preserve_incoming_args
4538 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4539 else if (CALL_COOKIE_INT_REG_GET
4540 (current_function_args_info.call_cookie, reg) == 1)
4541 emit_insn (gen_shcompact_preserve_incoming_args
4542 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4544 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
4546 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
4547 GEN_INT (current_function_args_info.call_cookie));
4548 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
4549 gen_rtx_REG (SImode, R0_REG));
4551 else if (TARGET_SHMEDIA)
4553 int tr = sh_media_register_for_return ();
4557 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
4558 gen_rtx_REG (DImode, PR_MEDIA_REG));
4560 /* If this function only exits with sibcalls, this copy
4561 will be flagged as dead. */
4562 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4568 /* Emit the code for SETUP_VARARGS. */
4569 if (current_function_stdarg)
4571 /* This is not used by the SH3E calling convention */
4572 if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI)
4574 /* Push arg regs as if they'd been provided by caller in stack. */
4575 for (i = 0; i < NPARM_REGS(SImode); i++)
4577 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4580 if (i >= (NPARM_REGS(SImode)
4581 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4585 RTX_FRAME_RELATED_P (insn) = 0;
4591 /* If we're supposed to switch stacks at function entry, do so now. */
4593 emit_insn (gen_sp_switch_1 ());
4595 calc_live_regs (&d, live_regs_mask);
4596 /* ??? Maybe we could save some switching if we can move a mode switch
4597 that already happens to be at the function start into the prologue. */
4598 if (target_flags != save_flags)
4599 emit_insn (gen_toggle_sz ());
4606 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4607 int offset_in_r0 = -1;
4610 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
4611 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4612 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4614 offset = d + d_rounding;
4615 output_stack_adjust (-offset, stack_pointer_rtx, 1, frame_insn);
4617 /* We loop twice: first, we save 8-byte aligned registers in the
4618 higher addresses, that are known to be aligned. Then, we
4619 proceed to saving 32-bit registers that don't need 8-byte
4621 for (align = 1; align >= 0; align--)
4622 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
4623 if (live_regs_mask[i/32] & (1 << (i % 32)))
4625 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4627 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
4629 if (mode == SFmode && (i % 2) == 1
4630 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4631 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4638 /* If we're doing the aligned pass and this is not aligned,
4639 or we're doing the unaligned pass and this is aligned,
4641 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4645 offset -= GET_MODE_SIZE (mode);
4647 reg_rtx = gen_rtx_REG (mode, reg);
4649 mem_rtx = gen_rtx_MEM (mode,
4650 gen_rtx_PLUS (Pmode,
4654 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
4660 if (HAVE_PRE_DECREMENT
4661 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
4662 || mem_rtx == NULL_RTX
4663 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4665 pre_dec = gen_rtx_MEM (mode,
4666 gen_rtx_PRE_DEC (Pmode, r0));
4668 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
4677 offset += GET_MODE_SIZE (mode);
4681 if (mem_rtx != NULL_RTX)
4684 if (offset_in_r0 == -1)
4686 emit_move_insn (r0, GEN_INT (offset));
4687 offset_in_r0 = offset;
4689 else if (offset != offset_in_r0)
4694 GEN_INT (offset - offset_in_r0)));
4695 offset_in_r0 += offset - offset_in_r0;
4698 if (pre_dec != NULL_RTX)
4704 (Pmode, r0, stack_pointer_rtx));
4708 offset -= GET_MODE_SIZE (mode);
4709 offset_in_r0 -= GET_MODE_SIZE (mode);
4714 mem_rtx = gen_rtx_MEM (mode, r0);
4716 mem_rtx = gen_rtx_MEM (mode,
4717 gen_rtx_PLUS (Pmode,
4721 /* We must not use an r0-based address for target-branch
4722 registers or for special registers without pre-dec
4723 memory addresses, since we store their values in r0
4725 if (TARGET_REGISTER_P (i)
4726 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4727 && mem_rtx != pre_dec))
4731 if (TARGET_REGISTER_P (i)
4732 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4733 && mem_rtx != pre_dec))
4735 rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
4737 emit_move_insn (r0mode, reg_rtx);
4745 emit_move_insn (mem_rtx, reg_rtx);
4748 if (offset != d_rounding)
4752 push_regs (live_regs_mask);
4754 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4756 rtx insn = get_last_insn ();
4757 rtx last = emit_insn (gen_GOTaddr2picreg ());
4759 /* Mark these insns as possibly dead. Sometimes, flow2 may
4760 delete all uses of the PIC register. In this case, let it
4761 delete the initialization too. */
4764 insn = NEXT_INSN (insn);
4766 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4770 while (insn != last);
4773 if (SHMEDIA_REGS_STACK_ADJUST ())
4775 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4776 gen_rtx_SYMBOL_REF (Pmode,
4778 ? "__GCC_push_shmedia_regs"
4779 : "__GCC_push_shmedia_regs_nofpu"));
4780 /* This must NOT go through the PLT, otherwise mach and macl
4781 may be clobbered. */
4782 emit_insn (gen_shmedia_save_restore_regs_compact
4783 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4786 if (target_flags != save_flags)
4788 rtx insn = emit_insn (gen_toggle_sz ());
4790 /* If we're lucky, a mode switch in the function body will
4791 overwrite fpscr, turning this insn dead. Tell flow this
4792 insn is ok to delete. */
4793 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4798 target_flags = save_flags;
4800 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
4801 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4803 if (frame_pointer_needed)
4804 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
4806 if (TARGET_SHCOMPACT
4807 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4809 /* This must NOT go through the PLT, otherwise mach and macl
4810 may be clobbered. */
4811 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4812 gen_rtx_SYMBOL_REF (Pmode,
4813 "__GCC_shcompact_incoming_args"));
4814 emit_insn (gen_shcompact_incoming_args ());
4819 sh_expand_epilogue ()
4821 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4825 int save_flags = target_flags;
4828 calc_live_regs (&d, live_regs_mask);
4830 if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
4831 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4832 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4834 frame_size = rounded_frame_size (d) - d_rounding;
4836 if (frame_pointer_needed)
4838 output_stack_adjust (frame_size, frame_pointer_rtx, 7, emit_insn);
4840 /* We must avoid moving the stack pointer adjustment past code
4841 which reads from the local frame, else an interrupt could
4842 occur after the SP adjustment and clobber data in the local
4844 emit_insn (gen_blockage ());
4845 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
4847 else if (frame_size)
4849 /* We must avoid moving the stack pointer adjustment past code
4850 which reads from the local frame, else an interrupt could
4851 occur after the SP adjustment and clobber data in the local
4853 emit_insn (gen_blockage ());
4854 output_stack_adjust (frame_size, stack_pointer_rtx, 7, emit_insn);
4857 if (SHMEDIA_REGS_STACK_ADJUST ())
4859 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4860 gen_rtx_SYMBOL_REF (Pmode,
4862 ? "__GCC_pop_shmedia_regs"
4863 : "__GCC_pop_shmedia_regs_nofpu"));
4864 /* This must NOT go through the PLT, otherwise mach and macl
4865 may be clobbered. */
4866 emit_insn (gen_shmedia_save_restore_regs_compact
4867 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
4870 /* Pop all the registers. */
4872 if (target_flags != save_flags)
4873 emit_insn (gen_toggle_sz ());
4876 int offset = d_rounding;
4877 int offset_in_r0 = -1;
4880 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4882 /* We loop twice: first, we save 8-byte aligned registers in the
4883 higher addresses, that are known to be aligned. Then, we
4884 proceed to saving 32-bit registers that don't need 8-byte
4886 for (align = 0; align <= 1; align++)
4887 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4888 if (live_regs_mask[i/32] & (1 << (i % 32)))
4890 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4892 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
4894 if (mode == SFmode && (i % 2) == 0
4895 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4896 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4902 /* If we're doing the aligned pass and this is not aligned,
4903 or we're doing the unaligned pass and this is aligned,
4905 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4909 reg_rtx = gen_rtx_REG (mode, reg);
4911 mem_rtx = gen_rtx_MEM (mode,
4912 gen_rtx_PLUS (Pmode,
4916 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
4922 if (HAVE_POST_INCREMENT
4923 && (offset == offset_in_r0
4924 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
4925 && mem_rtx == NULL_RTX)
4926 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4928 post_inc = gen_rtx_MEM (mode,
4929 gen_rtx_POST_INC (Pmode, r0));
4931 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
4934 post_inc = NULL_RTX;
4943 if (mem_rtx != NULL_RTX)
4946 if (offset_in_r0 == -1)
4948 emit_move_insn (r0, GEN_INT (offset));
4949 offset_in_r0 = offset;
4951 else if (offset != offset_in_r0)
4956 GEN_INT (offset - offset_in_r0)));
4957 offset_in_r0 += offset - offset_in_r0;
4960 if (post_inc != NULL_RTX)
4966 (Pmode, r0, stack_pointer_rtx));
4972 offset_in_r0 += GET_MODE_SIZE (mode);
4975 mem_rtx = gen_rtx_MEM (mode, r0);
4977 mem_rtx = gen_rtx_MEM (mode,
4978 gen_rtx_PLUS (Pmode,
4982 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
4983 && mem_rtx != post_inc)
4987 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
4988 && mem_rtx != post_inc)
4990 insn = emit_move_insn (r0, mem_rtx);
4993 else if (TARGET_REGISTER_P (i))
4995 rtx r1 = gen_rtx_REG (mode, R1_REG);
4997 insn = emit_move_insn (r1, mem_rtx);
5001 insn = emit_move_insn (reg_rtx, mem_rtx);
5003 offset += GET_MODE_SIZE (mode);
5006 if (offset != d + d_rounding)
5013 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5015 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5017 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5019 if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
5023 if (target_flags != save_flags)
5024 emit_insn (gen_toggle_sz ());
5025 target_flags = save_flags;
5027 output_stack_adjust (extra_push + current_function_pretend_args_size
5029 + current_function_args_info.stack_regs * 8,
5030 stack_pointer_rtx, 7, emit_insn);
5032 /* Switch back to the normal stack if necessary. */
5034 emit_insn (gen_sp_switch_2 ());
5036 /* Tell flow the insn that pops PR isn't dead. */
5037 /* PR_REG will never be live in SHmedia mode, and we don't need to
5038 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5039 by the return pattern. */
5040 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5041 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5044 static int sh_need_epilogue_known = 0;
5049 if (! sh_need_epilogue_known)
5054 sh_expand_epilogue ();
5055 epilogue = get_insns ();
5057 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5059 return sh_need_epilogue_known > 0;
5062 /* Clear variables at function end. */
5065 sh_output_function_epilogue (file, size)
5066 FILE *file ATTRIBUTE_UNUSED;
5067 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5069 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5070 sh_need_epilogue_known = 0;
5071 sp_switch = NULL_RTX;
5075 sh_builtin_saveregs ()
5077 /* First unnamed integer register. */
5078 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5079 /* Number of integer registers we need to save. */
5080 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5081 /* First unnamed SFmode float reg */
5082 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5083 /* Number of SFmode float regs to save. */
5084 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5087 HOST_WIDE_INT alias_set;
5093 int pushregs = n_intregs;
5095 while (pushregs < NPARM_REGS (SImode) - 1
5096 && (CALL_COOKIE_INT_REG_GET
5097 (current_function_args_info.call_cookie,
5098 NPARM_REGS (SImode) - pushregs)
5101 current_function_args_info.call_cookie
5102 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5107 if (pushregs == NPARM_REGS (SImode))
5108 current_function_args_info.call_cookie
5109 |= (CALL_COOKIE_INT_REG (0, 1)
5110 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5112 current_function_args_info.call_cookie
5113 |= CALL_COOKIE_STACKSEQ (pushregs);
5115 current_function_pretend_args_size += 8 * n_intregs;
5117 if (TARGET_SHCOMPACT)
5121 if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5)
5123 error ("__builtin_saveregs not supported by this subtarget");
5130 /* Allocate block of memory for the regs. */
5131 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5132 Or can assign_stack_local accept a 0 SIZE argument? */
5133 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5136 regbuf = gen_rtx_MEM (BLKmode,
5137 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5138 else if (n_floatregs & 1)
5142 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5143 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5144 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5145 regbuf = change_address (regbuf, BLKmode, addr);
5148 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5149 alias_set = get_varargs_alias_set ();
5150 set_mem_alias_set (regbuf, alias_set);
5153 This is optimized to only save the regs that are necessary. Explicitly
5154 named args need not be saved. */
5156 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5157 adjust_address (regbuf, BLKmode,
5158 n_floatregs * UNITS_PER_WORD),
5159 n_intregs, n_intregs * UNITS_PER_WORD);
5162 /* Return the address of the regbuf. */
5163 return XEXP (regbuf, 0);
5166 This is optimized to only save the regs that are necessary. Explicitly
5167 named args need not be saved.
5168 We explicitly build a pointer to the buffer because it halves the insn
5169 count when not optimizing (otherwise the pointer is built for each reg
5171 We emit the moves in reverse order so that we can use predecrement. */
5173 fpregs = gen_reg_rtx (Pmode);
5174 emit_move_insn (fpregs, XEXP (regbuf, 0));
5175 emit_insn (gen_addsi3 (fpregs, fpregs,
5176 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5180 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5182 emit_insn (gen_addsi3 (fpregs, fpregs,
5183 GEN_INT (-2 * UNITS_PER_WORD)));
5184 mem = gen_rtx_MEM (DFmode, fpregs);
5185 set_mem_alias_set (mem, alias_set);
5186 emit_move_insn (mem,
5187 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5189 regno = first_floatreg;
5192 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5193 mem = gen_rtx_MEM (SFmode, fpregs);
5194 set_mem_alias_set (mem, alias_set);
5195 emit_move_insn (mem,
5196 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5197 - (TARGET_LITTLE_ENDIAN != 0)));
5201 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5205 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5206 mem = gen_rtx_MEM (SFmode, fpregs);
5207 set_mem_alias_set (mem, alias_set);
5208 emit_move_insn (mem,
5209 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5212 /* Return the address of the regbuf. */
5213 return XEXP (regbuf, 0);
5216 /* Define the `__builtin_va_list' type for the ABI. */
5221 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5224 if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5225 return ptr_type_node;
5227 record = make_node (RECORD_TYPE);
5229 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5231 f_next_o_limit = build_decl (FIELD_DECL,
5232 get_identifier ("__va_next_o_limit"),
5234 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5236 f_next_fp_limit = build_decl (FIELD_DECL,
5237 get_identifier ("__va_next_fp_limit"),
5239 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5242 DECL_FIELD_CONTEXT (f_next_o) = record;
5243 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5244 DECL_FIELD_CONTEXT (f_next_fp) = record;
5245 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5246 DECL_FIELD_CONTEXT (f_next_stack) = record;
5248 TYPE_FIELDS (record) = f_next_o;
5249 TREE_CHAIN (f_next_o) = f_next_o_limit;
5250 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5251 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5252 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5254 layout_type (record);
5259 /* Implement `va_start' for varargs and stdarg. */
5262 sh_va_start (valist, nextarg)
5266 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5267 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5273 expand_builtin_saveregs ();
5274 std_expand_builtin_va_start (valist, nextarg);
5278 if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5280 std_expand_builtin_va_start (valist, nextarg);
5284 f_next_o = TYPE_FIELDS (va_list_type_node);
5285 f_next_o_limit = TREE_CHAIN (f_next_o);
5286 f_next_fp = TREE_CHAIN (f_next_o_limit);
5287 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5288 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5290 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5291 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5292 valist, f_next_o_limit);
5293 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
5294 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5295 valist, f_next_fp_limit);
5296 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5297 valist, f_next_stack);
5299 /* Call __builtin_saveregs. */
5300 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
5301 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
5302 TREE_SIDE_EFFECTS (t) = 1;
5303 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5305 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
5310 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5311 build_int_2 (UNITS_PER_WORD * nfp, 0)));
5312 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
5313 TREE_SIDE_EFFECTS (t) = 1;
5314 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5316 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
5317 TREE_SIDE_EFFECTS (t) = 1;
5318 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5320 nint = current_function_args_info.arg_count[SH_ARG_INT];
5325 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5326 build_int_2 (UNITS_PER_WORD * nint, 0)));
5327 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
5328 TREE_SIDE_EFFECTS (t) = 1;
5329 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5331 u = make_tree (ptr_type_node, nextarg);
5332 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
5333 TREE_SIDE_EFFECTS (t) = 1;
5334 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5337 /* Implement `va_arg'. */
5340 sh_va_arg (valist, type)
5343 HOST_WIDE_INT size, rsize;
5344 tree tmp, pptr_type_node;
5347 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
5349 size = int_size_in_bytes (type);
5350 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5351 pptr_type_node = build_pointer_type (ptr_type_node);
5354 type = build_pointer_type (type);
5356 if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
5358 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5359 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5361 rtx lab_false, lab_over;
5363 f_next_o = TYPE_FIELDS (va_list_type_node);
5364 f_next_o_limit = TREE_CHAIN (f_next_o);
5365 f_next_fp = TREE_CHAIN (f_next_o_limit);
5366 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5367 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5369 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5370 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5371 valist, f_next_o_limit);
5372 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
5374 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5375 valist, f_next_fp_limit);
5376 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5377 valist, f_next_stack);
5381 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
5382 || (TREE_CODE (type) == COMPLEX_TYPE
5383 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
5388 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
5391 addr_rtx = gen_reg_rtx (Pmode);
5392 lab_false = gen_label_rtx ();
5393 lab_over = gen_label_rtx ();
5398 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5399 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5401 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
5403 expand_expr (next_fp_limit, NULL_RTX,
5404 Pmode, EXPAND_NORMAL),
5405 GE, const1_rtx, Pmode, 1, lab_false);
5407 if (TYPE_ALIGN (type) > BITS_PER_WORD
5408 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
5409 && (n_floatregs & 1)))
5411 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
5412 build_int_2 (UNITS_PER_WORD, 0));
5413 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
5414 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
5415 TREE_SIDE_EFFECTS (tmp) = 1;
5416 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5419 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
5420 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5422 emit_move_insn (addr_rtx, r);
5424 emit_jump_insn (gen_jump (lab_over));
5426 emit_label (lab_false);
5428 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5429 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5431 emit_move_insn (addr_rtx, r);
5435 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
5436 build_int_2 (rsize, 0));
5438 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
5440 expand_expr (next_o_limit, NULL_RTX,
5441 Pmode, EXPAND_NORMAL),
5442 GT, const1_rtx, Pmode, 1, lab_false);
5444 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
5445 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5447 emit_move_insn (addr_rtx, r);
5449 emit_jump_insn (gen_jump (lab_over));
5451 emit_label (lab_false);
5453 if (size > 4 && ! TARGET_SH4)
5455 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
5456 TREE_SIDE_EFFECTS (tmp) = 1;
5457 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5460 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5461 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5463 emit_move_insn (addr_rtx, r);
5466 emit_label (lab_over);
5468 tmp = make_tree (pptr_type_node, addr_rtx);
5469 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
5472 /* ??? In va-sh.h, there had been code to make values larger than
5473 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5475 result = std_expand_builtin_va_arg (valist, type);
5478 #ifdef POINTERS_EXTEND_UNSIGNED
5479 if (GET_MODE (addr) != Pmode)
5480 addr = convert_memory_address (Pmode, result);
5482 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
5483 set_mem_alias_set (result, get_varargs_alias_set ());
5485 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5486 argument to the varargs alias set. */
5490 /* Define the offset between two registers, one to be eliminated, and
5491 the other its replacement, at the start of a routine. */
5494 initial_elimination_offset (from, to)
5499 int regs_saved_rounding = 0;
5500 int total_saved_regs_space;
5501 int total_auto_space;
5502 int save_flags = target_flags;
5505 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5506 calc_live_regs (®s_saved, live_regs_mask);
5507 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
5508 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
5509 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5510 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
5512 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
5513 copy_flags = target_flags;
5514 target_flags = save_flags;
5516 total_saved_regs_space = regs_saved + regs_saved_rounding;
5518 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
5519 return total_saved_regs_space + total_auto_space
5520 + current_function_args_info.byref_regs * 8;
5522 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5523 return total_saved_regs_space + total_auto_space
5524 + current_function_args_info.byref_regs * 8;
5526 /* Initial gap between fp and sp is 0. */
5527 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5530 if (from == RETURN_ADDRESS_POINTER_REGNUM
5531 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
5535 int i, n = total_saved_regs_space;
5537 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5539 n += total_auto_space;
5541 /* If it wasn't saved, there's not much we can do. */
5542 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5545 target_flags = copy_flags;
5547 /* We loop twice: first, check 8-byte aligned registers,
5548 that are stored in the higher addresses, that are known
5549 to be aligned. Then, check 32-bit registers that don't
5550 need 8-byte alignment. */
5551 for (align = 1; align >= 0; align--)
5552 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5553 if (live_regs_mask[i/32] & (1 << (i % 32)))
5555 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5557 if (mode == SFmode && (i % 2) == 1
5558 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5559 && (live_regs_mask[(i ^ 1) / 32]
5560 & (1 << ((i ^ 1) % 32))))
5566 /* If we're doing the aligned pass and this is not aligned,
5567 or we're doing the unaligned pass and this is aligned,
5569 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5573 n -= GET_MODE_SIZE (mode);
5577 target_flags = save_flags;
5585 return total_auto_space;
5591 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5595 sh_pr_interrupt (pfile)
5596 cpp_reader *pfile ATTRIBUTE_UNUSED;
5598 pragma_interrupt = 1;
5603 cpp_reader *pfile ATTRIBUTE_UNUSED;
5605 pragma_interrupt = pragma_trapa = 1;
5609 sh_pr_nosave_low_regs (pfile)
5610 cpp_reader *pfile ATTRIBUTE_UNUSED;
5612 pragma_nosave_low_regs = 1;
5615 /* Generate 'handle_interrupt' attribute for decls */
5618 sh_insert_attributes (node, attributes)
5622 if (! pragma_interrupt
5623 || TREE_CODE (node) != FUNCTION_DECL)
5626 /* We are only interested in fields. */
5627 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
5630 /* Add a 'handle_interrupt' attribute. */
5631 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
5636 /* Supported attributes:
5638 interrupt_handler -- specifies this function is an interrupt handler.
5640 sp_switch -- specifies an alternate stack for an interrupt handler
5643 trap_exit -- use a trapa to exit an interrupt function instead of
5644 an rte instruction. */
5646 const struct attribute_spec sh_attribute_table[] =
5648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5649 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
5650 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
5651 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
5652 { NULL, 0, 0, false, false, false, NULL }
5655 /* Handle an "interrupt_handler" attribute; arguments as in
5656 struct attribute_spec.handler. */
5658 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
5661 tree args ATTRIBUTE_UNUSED;
5662 int flags ATTRIBUTE_UNUSED;
5665 if (TREE_CODE (*node) != FUNCTION_DECL)
5667 warning ("`%s' attribute only applies to functions",
5668 IDENTIFIER_POINTER (name));
5669 *no_add_attrs = true;
5675 /* Handle an "sp_switch" attribute; arguments as in
5676 struct attribute_spec.handler. */
5678 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
5682 int flags ATTRIBUTE_UNUSED;
5685 if (TREE_CODE (*node) != FUNCTION_DECL)
5687 warning ("`%s' attribute only applies to functions",
5688 IDENTIFIER_POINTER (name));
5689 *no_add_attrs = true;
5691 else if (!pragma_interrupt)
5693 /* The sp_switch attribute only has meaning for interrupt functions. */
5694 warning ("`%s' attribute only applies to interrupt functions",
5695 IDENTIFIER_POINTER (name));
5696 *no_add_attrs = true;
5698 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
5700 /* The argument must be a constant string. */
5701 warning ("`%s' attribute argument not a string constant",
5702 IDENTIFIER_POINTER (name));
5703 *no_add_attrs = true;
5707 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
5708 TREE_STRING_POINTER (TREE_VALUE (args)));
5714 /* Handle an "trap_exit" attribute; arguments as in
5715 struct attribute_spec.handler. */
5717 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
5721 int flags ATTRIBUTE_UNUSED;
5724 if (TREE_CODE (*node) != FUNCTION_DECL)
5726 warning ("`%s' attribute only applies to functions",
5727 IDENTIFIER_POINTER (name));
5728 *no_add_attrs = true;
5730 else if (!pragma_interrupt)
5732 /* The trap_exit attribute only has meaning for interrupt functions. */
5733 warning ("`%s' attribute only applies to interrupt functions",
5734 IDENTIFIER_POINTER (name));
5735 *no_add_attrs = true;
5737 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
5739 /* The argument must be a constant integer. */
5740 warning ("`%s' attribute argument not an integer constant",
5741 IDENTIFIER_POINTER (name));
5742 *no_add_attrs = true;
5746 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
5753 sh_cfun_interrupt_handler_p (void)
5755 return (lookup_attribute ("interrupt_handler",
5756 DECL_ATTRIBUTES (current_function_decl))
5760 /* Predicates used by the templates. */
5762 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5763 Used only in general_movsrc_operand. */
5766 system_reg_operand (op, mode)
5768 enum machine_mode mode ATTRIBUTE_UNUSED;
5780 /* Returns 1 if OP can be source of a simple move operation.
5781 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5782 invalid as are subregs of system registers. */
5785 general_movsrc_operand (op, mode)
5787 enum machine_mode mode;
5789 if (GET_CODE (op) == MEM)
5791 rtx inside = XEXP (op, 0);
5792 if (GET_CODE (inside) == CONST)
5793 inside = XEXP (inside, 0);
5795 if (GET_CODE (inside) == LABEL_REF)
5798 if (GET_CODE (inside) == PLUS
5799 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
5800 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
5803 /* Only post inc allowed. */
5804 if (GET_CODE (inside) == PRE_DEC)
5808 if ((mode == QImode || mode == HImode)
5809 && (GET_CODE (op) == SUBREG
5810 && GET_CODE (XEXP (op, 0)) == REG
5811 && system_reg_operand (XEXP (op, 0), mode)))
5814 return general_operand (op, mode);
5817 /* Returns 1 if OP can be a destination of a move.
5818 Same as general_operand, but no preinc allowed. */
5821 general_movdst_operand (op, mode)
5823 enum machine_mode mode;
5825 /* Only pre dec allowed. */
5826 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
5829 return general_operand (op, mode);
5832 /* Returns 1 if OP is a normal arithmetic register. */
5835 arith_reg_operand (op, mode)
5837 enum machine_mode mode;
5839 if (register_operand (op, mode))
5843 if (GET_CODE (op) == REG)
5845 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
5846 regno = REGNO (SUBREG_REG (op));
5850 return (regno != T_REG && regno != PR_REG
5851 && ! TARGET_REGISTER_P (regno)
5852 && (regno != FPUL_REG || TARGET_SH4)
5853 && regno != MACH_REG && regno != MACL_REG);
5858 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
5859 because this would lead to missing sign extensions when truncating from
5860 DImode to SImode. */
5862 arith_reg_dest (op, mode)
5864 enum machine_mode mode;
5866 if (mode == DImode && GET_CODE (op) == SUBREG
5867 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
5869 return arith_reg_operand (op, mode);
5873 int_gpr_dest (op, mode)
5875 enum machine_mode mode ATTRIBUTE_UNUSED;
5877 enum machine_mode op_mode = GET_MODE (op);
5879 if (GET_MODE_CLASS (op_mode) != MODE_INT
5880 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
5882 if (! reload_completed)
5884 return true_regnum (op) <= LAST_GENERAL_REG;
5888 fp_arith_reg_operand (op, mode)
5890 enum machine_mode mode;
5892 if (register_operand (op, mode))
5896 if (GET_CODE (op) == REG)
5898 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
5899 regno = REGNO (SUBREG_REG (op));
5903 return (regno >= FIRST_PSEUDO_REGISTER
5904 || FP_REGISTER_P (regno));
5909 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
5912 arith_operand (op, mode)
5914 enum machine_mode mode;
5916 if (arith_reg_operand (op, mode))
5921 /* FIXME: We should be checking whether the CONST_INT fits in a
5922 CONST_OK_FOR_J here, but this causes reload_cse to crash when
5923 attempting to transform a sequence of two 64-bit sets of the
5924 same register from literal constants into a set and an add,
5925 when the difference is too wide for an add. */
5926 if (GET_CODE (op) == CONST_INT
5927 || EXTRA_CONSTRAINT_S (op))
5932 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
5938 /* Returns 1 if OP is a valid source operand for a compare insn. */
5941 arith_reg_or_0_operand (op, mode)
5943 enum machine_mode mode;
5945 if (arith_reg_operand (op, mode))
5948 if (EXTRA_CONSTRAINT_U (op))
5954 /* Return 1 if OP is a valid source operand for an SHmedia operation
5955 that takes either a register or a 6-bit immediate. */
5958 shmedia_6bit_operand (op, mode)
5960 enum machine_mode mode;
5962 return (arith_reg_operand (op, mode)
5963 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))));
5966 /* Returns 1 if OP is a valid source operand for a logical operation. */
5969 logical_operand (op, mode)
5971 enum machine_mode mode;
5973 if (arith_reg_operand (op, mode))
5978 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op)))
5983 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
5990 and_operand (op, mode)
5992 enum machine_mode mode;
5994 if (logical_operand (op, mode))
5997 /* Check mshflo.l / mshflhi.l opportunities. */
6000 && GET_CODE (op) == CONST_INT
6001 && (INTVAL (op) == (unsigned) 0xffffffff
6002 || INTVAL (op) == (HOST_WIDE_INT) -1 << 32))
6008 /* Nonzero if OP is a floating point value with value 0.0. */
6011 fp_zero_operand (op)
6016 if (GET_MODE (op) != SFmode)
6019 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6020 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
6023 /* Nonzero if OP is a floating point value with value 1.0. */
6031 if (GET_MODE (op) != SFmode)
6034 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6035 return REAL_VALUES_EQUAL (r, dconst1);
6038 /* For -m4 and -m4-single-only, mode switching is used. If we are
6039 compiling without -mfmovd, movsf_ie isn't taken into account for
6040 mode switching. We could check in machine_dependent_reorg for
6041 cases where we know we are in single precision mode, but there is
6042 interface to find that out during reload, so we must avoid
6043 choosing an fldi alternative during reload and thus failing to
6044 allocate a scratch register for the constant loading. */
6048 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
6052 tertiary_reload_operand (op, mode)
6054 enum machine_mode mode ATTRIBUTE_UNUSED;
6056 enum rtx_code code = GET_CODE (op);
6057 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
6061 fpscr_operand (op, mode)
6063 enum machine_mode mode ATTRIBUTE_UNUSED;
6065 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
6066 && GET_MODE (op) == PSImode);
6070 fpul_operand (op, mode)
6072 enum machine_mode mode;
6075 return fp_arith_reg_operand (op, mode);
6077 return (GET_CODE (op) == REG
6078 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6079 && GET_MODE (op) == mode);
6083 symbol_ref_operand (op, mode)
6085 enum machine_mode mode ATTRIBUTE_UNUSED;
6087 return (GET_CODE (op) == SYMBOL_REF);
6091 commutative_float_operator (op, mode)
6093 enum machine_mode mode;
6095 if (GET_MODE (op) != mode)
6097 switch (GET_CODE (op))
6109 noncommutative_float_operator (op, mode)
6111 enum machine_mode mode;
6113 if (GET_MODE (op) != mode)
6115 switch (GET_CODE (op))
6127 unary_float_operator (op, mode)
6129 enum machine_mode mode;
6131 if (GET_MODE (op) != mode)
6133 switch (GET_CODE (op))
6146 binary_float_operator (op, mode)
6148 enum machine_mode mode;
6150 if (GET_MODE (op) != mode)
6152 switch (GET_CODE (op))
6166 equality_comparison_operator (op, mode)
6168 enum machine_mode mode;
6170 return ((mode == VOIDmode || GET_MODE (op) == mode)
6171 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
6174 int greater_comparison_operator (op, mode)
6176 enum machine_mode mode;
6178 if (mode != VOIDmode && GET_MODE (op) == mode)
6180 switch (GET_CODE (op))
6192 int less_comparison_operator (op, mode)
6194 enum machine_mode mode;
6196 if (mode != VOIDmode && GET_MODE (op) == mode)
6198 switch (GET_CODE (op))
6210 /* Accept pseudos and branch target registers. */
6212 target_reg_operand (op, mode)
6214 enum machine_mode mode;
6217 || GET_MODE (op) != DImode)
6220 if (GET_CODE (op) == SUBREG)
6223 if (GET_CODE (op) != REG)
6226 /* We must protect ourselves from matching pseudos that are virtual
6227 register, because they will eventually be replaced with hardware
6228 registers that aren't branch-target registers. */
6229 if (REGNO (op) > LAST_VIRTUAL_REGISTER
6230 || TARGET_REGISTER_P (REGNO (op)))
6236 /* Same as target_reg_operand, except that label_refs and symbol_refs
6237 are accepted before reload. */
6239 target_operand (op, mode)
6241 enum machine_mode mode;
6246 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
6247 && EXTRA_CONSTRAINT_T (op))
6248 return ! reload_completed;
6250 return target_reg_operand (op, mode);
6254 mextr_bit_offset (op, mode)
6256 enum machine_mode mode ATTRIBUTE_UNUSED;
6260 if (GET_CODE (op) != CONST_INT)
6263 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
6267 extend_reg_operand (op, mode)
6269 enum machine_mode mode;
6271 return (GET_CODE (op) == TRUNCATE
6273 : arith_reg_operand) (op, mode);
6277 trunc_hi_operand (op, mode)
6279 enum machine_mode mode;
6281 enum machine_mode op_mode = GET_MODE (op);
6283 if (op_mode != SImode && op_mode != DImode
6284 && op_mode != V4HImode && op_mode != V2SImode)
6286 return extend_reg_operand (op, mode);
6290 extend_reg_or_0_operand (op, mode)
6292 enum machine_mode mode;
6294 return (GET_CODE (op) == TRUNCATE
6296 : arith_reg_or_0_operand) (op, mode);
6300 general_extend_operand (op, mode)
6302 enum machine_mode mode;
6304 return (GET_CODE (op) == TRUNCATE
6306 : nonimmediate_operand) (op, mode);
6310 inqhi_operand (op, mode)
6312 enum machine_mode mode;
6314 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
6317 /* Can't use true_regnum here because copy_cost wants to know about
6318 SECONDARY_INPUT_RELOAD_CLASS. */
6319 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
6323 sh_rep_vec (v, mode)
6325 enum machine_mode mode;
6330 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
6331 || (GET_MODE (v) != mode && mode != VOIDmode))
6333 i = XVECLEN (v, 0) - 2;
6334 x = XVECEXP (v, 0, i + 1);
6335 if (GET_MODE_UNIT_SIZE (mode) == 1)
6337 y = XVECEXP (v, 0, i);
6338 for (i -= 2 ; i >= 0; i -= 2)
6339 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
6340 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
6345 if (XVECEXP (v, 0, i) != x)
6350 /* Determine if V is a constant vector matching MODE with only one element
6351 that is not a sign extension. Two byte-sized elements count as one. */
6353 sh_1el_vec (v, mode)
6355 enum machine_mode mode;
6358 int i, last, least, sign_ix;
6361 if (GET_CODE (v) != CONST_VECTOR
6362 || (GET_MODE (v) != mode && mode != VOIDmode))
6364 /* Determine numbers of last and of least significat elements. */
6365 last = XVECLEN (v, 0) - 1;
6366 least = TARGET_LITTLE_ENDIAN ? 0 : last;
6367 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
6370 if (GET_MODE_UNIT_SIZE (mode) == 1)
6371 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
6372 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
6374 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
6375 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
6376 ? constm1_rtx : const0_rtx);
6377 i = XVECLEN (v, 0) - 1;
6379 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
6386 sh_const_vec (v, mode)
6388 enum machine_mode mode;
6392 if (GET_CODE (v) != CONST_VECTOR
6393 || (GET_MODE (v) != mode && mode != VOIDmode))
6395 i = XVECLEN (v, 0) - 1;
6397 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
6402 /* Return the destination address of a branch. */
6405 branch_dest (branch)
6408 rtx dest = SET_SRC (PATTERN (branch));
6411 if (GET_CODE (dest) == IF_THEN_ELSE)
6412 dest = XEXP (dest, 1);
6413 dest = XEXP (dest, 0);
6414 dest_uid = INSN_UID (dest);
6415 return INSN_ADDRESSES (dest_uid);
6418 /* Return non-zero if REG is not used after INSN.
6419 We assume REG is a reload reg, and therefore does
6420 not live past labels. It may live past calls or jumps though. */
6422 reg_unused_after (reg, insn)
6429 /* If the reg is set by this instruction, then it is safe for our
6430 case. Disregard the case where this is a store to memory, since
6431 we are checking a register used in the store address. */
6432 set = single_set (insn);
6433 if (set && GET_CODE (SET_DEST (set)) != MEM
6434 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6437 while ((insn = NEXT_INSN (insn)))
6439 code = GET_CODE (insn);
6442 /* If this is a label that existed before reload, then the register
6443 if dead here. However, if this is a label added by reorg, then
6444 the register may still be live here. We can't tell the difference,
6445 so we just ignore labels completely. */
6446 if (code == CODE_LABEL)
6451 if (code == JUMP_INSN)
6454 /* If this is a sequence, we must handle them all at once.
6455 We could have for instance a call that sets the target register,
6456 and an insn in a delay slot that uses the register. In this case,
6457 we must return 0. */
6458 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
6463 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6465 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
6466 rtx set = single_set (this_insn);
6468 if (GET_CODE (this_insn) == CALL_INSN)
6470 else if (GET_CODE (this_insn) == JUMP_INSN)
6472 if (INSN_ANNULLED_BRANCH_P (this_insn))
6477 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6479 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6481 if (GET_CODE (SET_DEST (set)) != MEM)
6487 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
6492 else if (code == JUMP_INSN)
6495 else if (GET_RTX_CLASS (code) == 'i')
6497 rtx set = single_set (insn);
6499 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6501 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6502 return GET_CODE (SET_DEST (set)) != MEM;
6503 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
6507 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
6515 static GTY(()) rtx fpscr_rtx;
6521 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
6522 REG_USERVAR_P (fpscr_rtx) = 1;
6523 mark_user_reg (fpscr_rtx);
6525 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
6526 mark_user_reg (fpscr_rtx);
6545 expand_sf_unop (fun, operands)
6546 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6549 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6553 expand_sf_binop (fun, operands)
6554 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6557 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
6562 expand_df_unop (fun, operands)
6563 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6566 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6570 expand_df_binop (fun, operands)
6571 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6574 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
6578 /* ??? gcc does flow analysis strictly after common subexpression
6579 elimination. As a result, common subespression elimination fails
6580 when there are some intervening statements setting the same register.
6581 If we did nothing about this, this would hurt the precision switching
6582 for SH4 badly. There is some cse after reload, but it is unable to
6583 undo the extra register pressure from the unused instructions, and
6584 it cannot remove auto-increment loads.
6586 A C code example that shows this flow/cse weakness for (at least) SH
6587 and sparc (as of gcc ss-970706) is this:
6601 So we add another pass before common subexpression elimination, to
6602 remove assignments that are dead due to a following assignment in the
6603 same basic block. */
6606 mark_use (x, reg_set_block)
6607 rtx x, *reg_set_block;
6613 code = GET_CODE (x);
6618 int regno = REGNO (x);
6619 int nregs = (regno < FIRST_PSEUDO_REGISTER
6620 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
6624 reg_set_block[regno + nregs - 1] = 0;
6631 rtx dest = SET_DEST (x);
6633 if (GET_CODE (dest) == SUBREG)
6634 dest = SUBREG_REG (dest);
6635 if (GET_CODE (dest) != REG)
6636 mark_use (dest, reg_set_block);
6637 mark_use (SET_SRC (x), reg_set_block);
6644 const char *fmt = GET_RTX_FORMAT (code);
6646 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6649 mark_use (XEXP (x, i), reg_set_block);
6650 else if (fmt[i] == 'E')
6651 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6652 mark_use (XVECEXP (x, i, j), reg_set_block);
6659 static rtx get_free_reg PARAMS ((HARD_REG_SET));
6661 /* This function returns a register to use to load the address to load
6662 the fpscr from. Currently it always returns r1 or r7, but when we are
6663 able to use pseudo registers after combine, or have a better mechanism
6664 for choosing a register, it should be done here. */
6665 /* REGS_LIVE is the liveness information for the point for which we
6666 need this allocation. In some bare-bones exit blocks, r1 is live at the
6667 start. We can even have all of r0..r3 being live:
6668 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6669 INSN before which new insns are placed with will clobber the register
6670 we return. If a basic block consists only of setting the return value
6671 register to a pseudo and using that register, the return value is not
6672 live before or after this block, yet we we'll insert our insns right in
6676 get_free_reg (regs_live)
6677 HARD_REG_SET regs_live;
6679 if (! TEST_HARD_REG_BIT (regs_live, 1))
6680 return gen_rtx_REG (Pmode, 1);
6682 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6683 there shouldn't be anything but a jump before the function end. */
6684 if (! TEST_HARD_REG_BIT (regs_live, 7))
6685 return gen_rtx_REG (Pmode, 7);
6690 /* This function will set the fpscr from memory.
6691 MODE is the mode we are setting it to. */
6693 fpscr_set_from_mem (mode, regs_live)
6695 HARD_REG_SET regs_live;
6697 enum attr_fp_mode fp_mode = mode;
6698 rtx addr_reg = get_free_reg (regs_live);
6700 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
6701 emit_insn (gen_fpu_switch1 (addr_reg));
6703 emit_insn (gen_fpu_switch0 (addr_reg));
6706 /* Is the given character a logical line separator for the assembler? */
6707 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6708 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6712 sh_insn_length_adjustment (insn)
6715 /* Instructions with unfilled delay slots take up an extra two bytes for
6716 the nop in the delay slot. */
6717 if (((GET_CODE (insn) == INSN
6718 && GET_CODE (PATTERN (insn)) != USE
6719 && GET_CODE (PATTERN (insn)) != CLOBBER)
6720 || GET_CODE (insn) == CALL_INSN
6721 || (GET_CODE (insn) == JUMP_INSN
6722 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
6723 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
6724 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
6725 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
6728 /* sh-dsp parallel processing insn take four bytes instead of two. */
6730 if (GET_CODE (insn) == INSN)
6733 rtx body = PATTERN (insn);
6734 const char *template;
6736 int maybe_label = 1;
6738 if (GET_CODE (body) == ASM_INPUT)
6739 template = XSTR (body, 0);
6740 else if (asm_noperands (body) >= 0)
6742 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
6751 while (c == ' ' || c == '\t');
6752 /* all sh-dsp parallel-processing insns start with p.
6753 The only non-ppi sh insn starting with p is pref.
6754 The only ppi starting with pr is prnd. */
6755 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
6757 /* The repeat pseudo-insn expands two three insns, a total of
6758 six bytes in size. */
6759 else if ((c == 'r' || c == 'R')
6760 && ! strncasecmp ("epeat", template, 5))
6762 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
6764 /* If this is a label, it is obviously not a ppi insn. */
6765 if (c == ':' && maybe_label)
6770 else if (c == '\'' || c == '"')
6775 maybe_label = c != ':';
6783 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6784 isn't protected by a PIC unspec. */
6786 nonpic_symbol_mentioned_p (x)
6789 register const char *fmt;
6792 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
6793 || GET_CODE (x) == PC)
6796 /* We don't want to look into the possible MEM location of a
6797 CONST_DOUBLE, since we're not going to use it, in general. */
6798 if (GET_CODE (x) == CONST_DOUBLE)
6801 if (GET_CODE (x) == UNSPEC
6802 && (XINT (x, 1) == UNSPEC_PIC
6803 || XINT (x, 1) == UNSPEC_GOT
6804 || XINT (x, 1) == UNSPEC_GOTOFF
6805 || XINT (x, 1) == UNSPEC_GOTPLT
6806 || XINT (x, 1) == UNSPEC_PLT))
6809 fmt = GET_RTX_FORMAT (GET_CODE (x));
6810 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6817 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
6820 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
6827 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6828 @GOTOFF in `reg'. */
6830 legitimize_pic_address (orig, mode, reg)
6832 enum machine_mode mode ATTRIBUTE_UNUSED;
6835 if (GET_CODE (orig) == LABEL_REF
6836 || (GET_CODE (orig) == SYMBOL_REF
6837 && (CONSTANT_POOL_ADDRESS_P (orig)
6838 /* SYMBOL_REF_FLAG is set on static symbols. */
6839 || SYMBOL_REF_FLAG (orig))))
6842 reg = gen_reg_rtx (Pmode);
6844 emit_insn (gen_symGOTOFF2reg (reg, orig));
6847 else if (GET_CODE (orig) == SYMBOL_REF)
6850 reg = gen_reg_rtx (Pmode);
6852 emit_insn (gen_symGOT2reg (reg, orig));
6858 /* Mark the use of a constant in the literal table. If the constant
6859 has multiple labels, make it unique. */
6861 mark_constant_pool_use (x)
6864 rtx insn, lab, pattern;
6869 switch (GET_CODE (x))
6879 /* Get the first label in the list of labels for the same constant
6880 and delete another labels in the list. */
6882 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
6884 if (GET_CODE (insn) != CODE_LABEL
6885 || LABEL_REFS (insn) != NEXT_INSN (insn))
6890 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
6891 INSN_DELETED_P (insn) = 1;
6893 /* Mark constants in a window. */
6894 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
6896 if (GET_CODE (insn) != INSN)
6899 pattern = PATTERN (insn);
6900 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
6903 switch (XINT (pattern, 1))
6905 case UNSPECV_CONST2:
6906 case UNSPECV_CONST4:
6907 case UNSPECV_CONST8:
6908 XVECEXP (pattern, 0, 1) = const1_rtx;
6910 case UNSPECV_WINDOW_END:
6911 if (XVECEXP (pattern, 0, 0) == x)
6914 case UNSPECV_CONST_END:
6924 /* Return true if it's possible to redirect BRANCH1 to the destination
6925 of an unconditional jump BRANCH2. We only want to do this if the
6926 resulting branch will have a short displacement. */
6928 sh_can_redirect_branch (branch1, branch2)
6932 if (flag_expensive_optimizations && simplejump_p (branch2))
6934 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
6938 for (distance = 0, insn = NEXT_INSN (branch1);
6939 insn && distance < 256;
6940 insn = PREV_INSN (insn))
6945 distance += get_attr_length (insn);
6947 for (distance = 0, insn = NEXT_INSN (branch1);
6948 insn && distance < 256;
6949 insn = NEXT_INSN (insn))
6954 distance += get_attr_length (insn);
6960 /* Return non-zero if register old_reg can be renamed to register new_reg. */
6962 sh_hard_regno_rename_ok (old_reg, new_reg)
6963 unsigned int old_reg ATTRIBUTE_UNUSED;
6964 unsigned int new_reg;
6967 /* Interrupt functions can only use registers that have already been
6968 saved by the prologue, even if they would normally be
6971 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
6977 /* A C statement (sans semicolon) to update the integer variable COST
6978 based on the relationship between INSN that is dependent on
6979 DEP_INSN through the dependence LINK. The default is to make no
6980 adjustment to COST. This can be used for example to specify to
6981 the scheduler that an output- or anti-dependence does not incur
6982 the same cost as a data-dependence. */
6984 sh_adjust_cost (insn, link, dep_insn, cost)
6986 rtx link ATTRIBUTE_UNUSED;
6994 /* On SHmedia, if the dependence is an anti-dependence or
6995 output-dependence, there is no cost. */
6996 if (REG_NOTE_KIND (link) != 0)
6999 if (get_attr_is_mac_media (insn)
7000 && get_attr_is_mac_media (dep_insn))
7003 else if (GET_CODE(insn) == CALL_INSN)
7005 /* The only input for a call that is timing-critical is the
7006 function's address. */
7007 rtx call = PATTERN (insn);
7009 if (GET_CODE (call) == PARALLEL)
7010 call = XVECEXP (call, 0 ,0);
7011 if (GET_CODE (call) == SET)
7012 call = SET_SRC (call);
7013 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
7014 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
7017 /* All sfunc calls are parallels with at least four components.
7018 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7019 else if (GET_CODE (PATTERN (insn)) == PARALLEL
7020 && XVECLEN (PATTERN (insn), 0) >= 4
7021 && (reg = sfunc_uses_reg (insn)))
7023 /* Likewise, the most timing critical input for an sfuncs call
7024 is the function address. However, sfuncs typically start
7025 using their arguments pretty quickly.
7026 Assume a four cycle delay before they are needed. */
7027 if (! reg_set_p (reg, dep_insn))
7028 cost -= TARGET_SUPERSCALAR ? 40 : 4;
7030 /* Adjust load_si / pcload_si type insns latency. Use the known
7031 nominal latency and form of the insn to speed up the check. */
7033 && GET_CODE (PATTERN (dep_insn)) == SET
7034 /* Latency for dmpy type insns is also 3, so check the that
7035 it's actually a move insn. */
7036 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))
7039 && GET_CODE (PATTERN (dep_insn)) == SET
7040 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode)
7046 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7047 'special function' patterns (type sfunc) that clobber pr, but that
7048 do not look like function calls to leaf_function_p. Hence we must
7049 do this extra check. */
7053 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
7056 /* This Function Returns non zero if DFA based scheduler
7057 interface is to be used.At present supported only for
7060 sh_use_dfa_interface()
7068 /* This function returns "2" that signifies dual issue
7069 for SH4 processor.To be used by DFA pipeline description. */
7079 /* SHmedia requires registers for branches, so we can't generate new
7080 branches past reload. */
7082 sh_cannot_modify_jumps_p ()
7084 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
7088 sh_ms_bitfield_layout_p (record_type)
7089 tree record_type ATTRIBUTE_UNUSED;
7094 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
7095 may access it using GOTOFF instead of GOT. */
7098 sh_encode_section_info (decl, first)
7105 rtl = DECL_RTL (decl);
7107 rtl = TREE_CST_RTL (decl);
7108 if (GET_CODE (rtl) != MEM)
7110 symbol = XEXP (rtl, 0);
7111 if (GET_CODE (symbol) != SYMBOL_REF)
7115 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
7117 if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL)
7118 XEXP (rtl, 0) = gen_datalabel_ref (symbol);
7121 /* Undo the effects of the above. */
7124 sh_strip_name_encoding (str)
7127 STRIP_DATALABEL_ENCODING (str, str);
7134 On the SH1..SH4, the trampoline looks like
7135 2 0002 D202 mov.l l2,r2
7136 1 0000 D301 mov.l l1,r3
7139 5 0008 00000000 l1: .long area
7140 6 000c 00000000 l2: .long function
7142 SH5 (compact) uses r1 instead of r3 for the static chain. */
7145 /* Emit RTL insns to initialize the variable parts of a trampoline.
7146 FNADDR is an RTX for the address of the function's pure code.
7147 CXT is an RTX for the static chain value for the function. */
7150 sh_initialize_trampoline (tramp, fnaddr, cxt)
7151 rtx tramp, fnaddr, cxt;
7153 if (TARGET_SHMEDIA64)
7158 rtx movi1 = GEN_INT (0xcc000010);
7159 rtx shori1 = GEN_INT (0xc8000010);
7162 /* The following trampoline works within a +- 128 KB range for cxt:
7163 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7164 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7165 gettr tr1,r1; blink tr0,r63 */
7166 /* Address rounding makes it hard to compute the exact bounds of the
7167 offset for this trampoline, but we have a rather generous offset
7168 range, so frame_offset should do fine as an upper bound. */
7169 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
7171 /* ??? could optimize this trampoline initialization
7172 by writing DImode words with two insns each. */
7173 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
7174 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
7175 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
7176 insn = gen_rtx_AND (DImode, insn, mask);
7177 /* Or in ptb/u .,tr1 pattern */
7178 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
7179 insn = force_operand (insn, NULL_RTX);
7180 insn = gen_lowpart (SImode, insn);
7181 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
7182 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
7183 insn = gen_rtx_AND (DImode, insn, mask);
7184 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
7185 insn = gen_lowpart (SImode, insn);
7186 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
7187 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
7188 insn = gen_rtx_AND (DImode, insn, mask);
7189 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7190 insn = gen_lowpart (SImode, insn);
7191 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
7192 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
7193 insn = gen_rtx_AND (DImode, insn, mask);
7194 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7195 insn = gen_lowpart (SImode, insn);
7196 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7198 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
7199 insn = gen_rtx_AND (DImode, insn, mask);
7200 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7201 insn = gen_lowpart (SImode, insn);
7202 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
7204 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
7205 GEN_INT (0x6bf10600));
7206 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
7207 GEN_INT (0x4415fc10));
7208 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
7209 GEN_INT (0x4401fff0));
7210 emit_insn (gen_ic_invalidate_line (tramp));
7213 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
7214 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
7216 tramp_templ = gen_datalabel_ref (tramp_templ);
7217 dst = gen_rtx_MEM (BLKmode, tramp);
7218 src = gen_rtx_MEM (BLKmode, tramp_templ);
7219 set_mem_align (dst, 256);
7220 set_mem_align (src, 64);
7221 emit_block_move (dst, src, GEN_INT (fixed_len));
7223 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
7225 emit_move_insn (gen_rtx_MEM (Pmode,
7226 plus_constant (tramp,
7228 + GET_MODE_SIZE (Pmode))),
7230 emit_insn (gen_ic_invalidate_line (tramp));
7233 else if (TARGET_SHMEDIA)
7235 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7236 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7237 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
7238 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
7239 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7240 rotated 10 right, and higer 16 bit of every 32 selected. */
7242 = force_reg (V2HImode, (simplify_gen_subreg
7243 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
7244 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
7245 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
7247 tramp = force_reg (Pmode, tramp);
7248 fnaddr = force_reg (SImode, fnaddr);
7249 cxt = force_reg (SImode, cxt);
7250 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
7251 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
7253 emit_insn (gen_rotldi3_mextr (quad0, quad0,
7254 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7255 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
7256 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
7257 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
7258 gen_rtx_SUBREG (V2HImode, cxt, 0),
7260 emit_insn (gen_rotldi3_mextr (cxtload, cxtload,
7261 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7262 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
7263 if (TARGET_LITTLE_ENDIAN)
7265 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
7266 emit_insn (gen_mextr4 (quad2, cxtload, blink));
7270 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
7271 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
7273 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
7274 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
7275 emit_insn (gen_ic_invalidate_line (tramp));
7278 else if (TARGET_SHCOMPACT)
7280 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
7283 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7284 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
7286 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7287 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
7289 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7291 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7295 if (TARGET_USERMODE)
7296 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),
7297 0, VOIDmode, 1, tramp, SImode);
7299 emit_insn (gen_ic_invalidate_line (tramp));
7304 /* Machine specific built-in functions. */
7306 struct builtin_description
7308 const enum insn_code icode;
7309 const char *const name;
7313 /* describe number and signedness of arguments; arg[0] == result
7314 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7315 static const char signature_args[][4] =
7317 #define SH_BLTIN_V2SI2 0
7319 #define SH_BLTIN_V4HI2 1
7321 #define SH_BLTIN_V2SI3 2
7323 #define SH_BLTIN_V4HI3 3
7325 #define SH_BLTIN_V8QI3 4
7327 #define SH_BLTIN_MAC_HISI 5
7329 #define SH_BLTIN_SH_HI 6
7331 #define SH_BLTIN_SH_SI 7
7333 #define SH_BLTIN_V4HI2V2SI 8
7335 #define SH_BLTIN_V4HI2V8QI 9
7337 #define SH_BLTIN_SISF 10
7339 #define SH_BLTIN_LDUA_L 11
7341 #define SH_BLTIN_LDUA_Q 12
7343 #define SH_BLTIN_STUA_L 13
7345 #define SH_BLTIN_STUA_Q 14
7347 #define SH_BLTIN_UDI 15
7349 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7350 #define SH_BLTIN_2 16
7351 #define SH_BLTIN_SU 16
7353 #define SH_BLTIN_3 17
7354 #define SH_BLTIN_SUS 17
7356 #define SH_BLTIN_PSSV 18
7358 #define SH_BLTIN_XXUU 19
7359 #define SH_BLTIN_UUUU 19
7361 #define SH_BLTIN_PV 20
7364 /* mcmv: operands considered unsigned. */
7365 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7366 /* mperm: control value considered unsigned int. */
7367 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7368 /* mshards_q: returns signed short. */
7369 /* nsb: takes long long arg, returns unsigned char. */
7370 static const struct builtin_description bdesc[] =
7372 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
7373 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
7374 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
7375 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
7376 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
7377 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
7378 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
7380 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7381 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7383 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
7384 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
7385 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
7386 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
7387 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
7388 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
7389 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
7390 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
7391 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
7392 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
7393 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
7394 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
7395 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
7396 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
7397 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
7398 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
7399 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
7400 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
7401 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
7402 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
7403 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
7404 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
7405 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
7406 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
7407 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
7408 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
7409 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
7410 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
7411 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
7412 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
7413 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
7414 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
7415 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
7416 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
7417 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
7418 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
7419 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
7420 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
7421 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
7422 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
7423 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
7424 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
7425 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
7426 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
7427 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
7428 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
7429 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
7430 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
7431 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
7432 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
7433 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
7434 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
7435 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
7436 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
7438 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7439 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7440 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7441 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7442 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7443 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7444 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7445 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7446 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7447 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7448 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7449 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7450 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7451 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7452 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7453 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7455 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
7456 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
7458 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
7459 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
7464 sh_media_init_builtins ()
7466 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
7467 const struct builtin_description *d;
7469 memset (shared, 0, sizeof shared);
7470 for (d = bdesc; d - bdesc < (int) (sizeof bdesc / sizeof bdesc[0]); d++)
7472 tree type, arg_type;
7473 int signature = d->signature;
7476 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
7477 type = shared[signature];
7480 int has_result = signature_args[signature][0] != 0;
7482 if (signature_args[signature][1] == 8
7483 && (insn_data[d->icode].operand[has_result].mode != Pmode))
7485 if (! TARGET_FPU_ANY
7486 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
7488 type = void_list_node;
7491 int arg = signature_args[signature][i];
7492 int opno = i - 1 + has_result;
7495 arg_type = ptr_type_node;
7497 arg_type = ((*lang_hooks.types.type_for_mode)
7498 (insn_data[d->icode].operand[opno].mode,
7503 arg_type = void_type_node;
7506 type = tree_cons (NULL_TREE, arg_type, type);
7508 type = build_function_type (arg_type, type);
7509 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
7510 shared[signature] = type;
7512 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
7521 sh_media_init_builtins ();
7524 /* Expand an expression EXP that calls a built-in function,
7525 with result going to TARGET if that's convenient
7526 (and in mode MODE if that's convenient).
7527 SUBTARGET may be used as the target for computing one of EXP's operands.
7528 IGNORE is nonzero if the value is to be ignored. */
7531 sh_expand_builtin (exp, target, subtarget, mode, ignore)
7534 rtx subtarget ATTRIBUTE_UNUSED;
7535 enum machine_mode mode ATTRIBUTE_UNUSED;
7538 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7539 tree arglist = TREE_OPERAND (exp, 1);
7540 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7541 const struct builtin_description *d = &bdesc[fcode];
7542 enum insn_code icode = d->icode;
7543 int signature = d->signature;
7544 enum machine_mode tmode = VOIDmode;
7549 if (signature_args[signature][0])
7554 tmode = insn_data[icode].operand[0].mode;
7556 || GET_MODE (target) != tmode
7557 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7558 target = gen_reg_rtx (tmode);
7564 for (i = 1; i <= 3; i++, nop++)
7567 enum machine_mode opmode, argmode;
7569 if (! signature_args[signature][i])
7571 arg = TREE_VALUE (arglist);
7572 arglist = TREE_CHAIN (arglist);
7573 opmode = insn_data[icode].operand[nop].mode;
7574 argmode = TYPE_MODE (TREE_TYPE (arg));
7575 if (argmode != opmode)
7576 arg = build1 (NOP_EXPR,
7577 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
7578 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
7579 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
7580 op[nop] = copy_to_mode_reg (opmode, op[nop]);
7586 pat = (*insn_data[d->icode].genfun) (op[0]);
7589 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
7592 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
7595 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
7605 sh_expand_unop_v2sf (code, op0, op1)
7609 rtx sel0 = const0_rtx;
7610 rtx sel1 = const1_rtx;
7611 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
7612 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
7614 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
7615 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
7619 sh_expand_binop_v2sf (code, op0, op1, op2)
7623 rtx sel0 = const0_rtx;
7624 rtx sel1 = const1_rtx;
7625 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx) = gen_binary_sf_op;
7626 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
7628 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
7629 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));