1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
40 #include "diagnostic-core.h"
42 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
57 #include "alloc-pool.h"
58 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt;
85 tree sh_deferred_function_attributes;
86 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles = 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid = 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static void split_branches (rtx);
172 static int branch_dest (rtx);
173 static void force_into (rtx, rtx);
174 static void print_slot (rtx);
175 static rtx add_constant (rtx, enum machine_mode, rtx);
176 static void dump_table (rtx, rtx);
177 static int hi_const (rtx);
178 static int broken_move (rtx);
179 static int mova_p (rtx);
180 static rtx find_barrier (int, rtx, rtx);
181 static int noncall_uses_reg (rtx, rtx, rtx *);
182 static rtx gen_block_redirect (rtx, int, int);
183 static void sh_reorg (void);
184 static void sh_option_override (void);
185 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
186 static rtx frame_insn (rtx);
187 static rtx push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET *, int);
190 static int calc_live_regs (HARD_REG_SET *);
191 static HOST_WIDE_INT rounded_frame_size (int);
192 static bool sh_frame_pointer_required (void);
193 static rtx mark_constant_pool_use (rtx);
194 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_resbank_handler_attribute (tree *, tree,
197 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
199 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
202 static void sh_print_operand (FILE *, rtx, int);
203 static void sh_print_operand_address (FILE *, rtx);
204 static bool sh_print_operand_punct_valid_p (unsigned char code);
205 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
206 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
207 static void sh_insert_attributes (tree, tree *);
208 static const char *sh_check_pch_target_flags (int);
209 static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
210 static int sh_adjust_cost (rtx, rtx, rtx, int);
211 static int sh_issue_rate (void);
212 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
213 static short find_set_regmode_weight (rtx, enum machine_mode);
214 static short find_insn_regmode_weight (rtx, enum machine_mode);
215 static void find_regmode_weight (basic_block, enum machine_mode);
216 static int find_r0_life_regions (basic_block);
217 static void sh_md_init_global (FILE *, int, int);
218 static void sh_md_finish_global (FILE *, int);
219 static int rank_for_reorder (const void *, const void *);
220 static void swap_reorder (rtx *, int);
221 static void ready_reorder (rtx *, int);
222 static short high_pressure (enum machine_mode);
223 static int sh_reorder (FILE *, int, rtx *, int *, int);
224 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
225 static void sh_md_init (FILE *, int, int);
226 static int sh_variable_issue (FILE *, int, rtx, int);
228 static bool sh_function_ok_for_sibcall (tree, tree);
230 static bool sh_cannot_modify_jumps_p (void);
231 static reg_class_t sh_target_reg_class (void);
232 static bool sh_optimize_target_register_callee_saved (bool);
233 static bool sh_ms_bitfield_layout_p (const_tree);
235 static void sh_init_builtins (void);
236 static tree sh_builtin_decl (unsigned, bool);
237 static void sh_media_init_builtins (void);
238 static tree sh_media_builtin_decl (unsigned, bool);
239 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
240 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
241 static void sh_file_start (void);
242 static int flow_dependent_p (rtx, rtx);
243 static void flow_dependent_p_1 (rtx, const_rtx, void *);
244 static int shiftcosts (rtx);
245 static int and_xor_ior_costs (rtx, int);
246 static int addsubcosts (rtx);
247 static int multcosts (rtx);
248 static bool unspec_caller_rtx_p (rtx);
249 static bool sh_cannot_copy_insn_p (rtx);
250 static bool sh_rtx_costs (rtx, int, int, int, int *, bool);
251 static int sh_address_cost (rtx, bool);
252 static int sh_pr_n_sets (void);
253 static rtx sh_allocate_initial_value (rtx);
254 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
255 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
257 struct secondary_reload_info *);
258 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
259 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
260 static rtx sh_delegitimize_address (rtx);
261 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
262 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
263 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
264 static int scavenge_reg (HARD_REG_SET *s);
265 struct save_schedule_s;
266 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
267 struct save_schedule_s *, int);
269 static rtx sh_struct_value_rtx (tree, int);
270 static rtx sh_function_value (const_tree, const_tree, bool);
271 static bool sh_function_value_regno_p (const unsigned int);
272 static rtx sh_libcall_value (enum machine_mode, const_rtx);
273 static bool sh_return_in_memory (const_tree, const_tree);
274 static rtx sh_builtin_saveregs (void);
275 static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode, tree, int *, int);
276 static bool sh_strict_argument_naming (cumulative_args_t);
277 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
278 static tree sh_build_builtin_va_list (void);
279 static void sh_va_start (tree, rtx);
280 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
281 static bool sh_promote_prototypes (const_tree);
282 static enum machine_mode sh_promote_function_mode (const_tree type,
287 static bool sh_pass_by_reference (cumulative_args_t, enum machine_mode,
289 static bool sh_callee_copies (cumulative_args_t, enum machine_mode,
291 static int sh_arg_partial_bytes (cumulative_args_t, enum machine_mode,
293 static void sh_function_arg_advance (cumulative_args_t, enum machine_mode,
295 static rtx sh_function_arg (cumulative_args_t, enum machine_mode,
297 static bool sh_scalar_mode_supported_p (enum machine_mode);
298 static int sh_dwarf_calling_convention (const_tree);
299 static void sh_encode_section_info (tree, rtx, int);
300 static int sh2a_function_vector_p (tree);
301 static void sh_trampoline_init (rtx, tree, rtx);
302 static rtx sh_trampoline_adjust_address (rtx);
303 static void sh_conditional_register_usage (void);
304 static bool sh_legitimate_constant_p (enum machine_mode, rtx);
306 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
308 static const struct attribute_spec sh_attribute_table[] =
310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
311 affects_type_identity } */
312 { "interrupt_handler", 0, 0, true, false, false,
313 sh_handle_interrupt_handler_attribute, false },
314 { "sp_switch", 1, 1, true, false, false,
315 sh_handle_sp_switch_attribute, false },
316 { "trap_exit", 1, 1, true, false, false,
317 sh_handle_trap_exit_attribute, false },
318 { "renesas", 0, 0, false, true, false,
319 sh_handle_renesas_attribute, false },
320 { "trapa_handler", 0, 0, true, false, false,
321 sh_handle_interrupt_handler_attribute, false },
322 { "nosave_low_regs", 0, 0, true, false, false,
323 sh_handle_interrupt_handler_attribute, false },
324 { "resbank", 0, 0, true, false, false,
325 sh_handle_resbank_handler_attribute, false },
326 { "function_vector", 1, 1, true, false, false,
327 sh2a_handle_function_vector_handler_attribute, false },
328 { NULL, 0, 0, false, false, false, NULL, false }
331 /* Initialize the GCC target structure. */
332 #undef TARGET_ATTRIBUTE_TABLE
333 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
335 /* The next two are used for debug info when compiling with -gdwarf. */
336 #undef TARGET_ASM_UNALIGNED_HI_OP
337 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
338 #undef TARGET_ASM_UNALIGNED_SI_OP
339 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
341 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
342 #undef TARGET_ASM_UNALIGNED_DI_OP
343 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
344 #undef TARGET_ASM_ALIGNED_DI_OP
345 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
347 #undef TARGET_OPTION_OVERRIDE
348 #define TARGET_OPTION_OVERRIDE sh_option_override
350 #undef TARGET_PRINT_OPERAND
351 #define TARGET_PRINT_OPERAND sh_print_operand
352 #undef TARGET_PRINT_OPERAND_ADDRESS
353 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
354 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
355 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
356 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
357 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
359 #undef TARGET_ASM_FUNCTION_EPILOGUE
360 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
362 #undef TARGET_ASM_OUTPUT_MI_THUNK
363 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
365 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
366 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
368 #undef TARGET_ASM_FILE_START
369 #define TARGET_ASM_FILE_START sh_file_start
370 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
371 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
373 #undef TARGET_REGISTER_MOVE_COST
374 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
376 #undef TARGET_INSERT_ATTRIBUTES
377 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
379 #undef TARGET_SCHED_ADJUST_COST
380 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
382 #undef TARGET_SCHED_ISSUE_RATE
383 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
385 /* The next 5 hooks have been implemented for reenabling sched1. With the
386 help of these macros we are limiting the movement of insns in sched1 to
387 reduce the register pressure. The overall idea is to keep count of SImode
388 and SFmode regs required by already scheduled insns. When these counts
389 cross some threshold values; give priority to insns that free registers.
390 The insn that frees registers is most likely to be the insn with lowest
391 LUID (original insn order); but such an insn might be there in the stalled
392 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
393 upto a max of 8 cycles so that such insns may move from Q -> R.
395 The description of the hooks are as below:
397 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
398 scheduler; it is called inside the sched_init function just after
399 find_insn_reg_weights function call. It is used to calculate the SImode
400 and SFmode weights of insns of basic blocks; much similar to what
401 find_insn_reg_weights does.
402 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
404 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
405 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
408 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
409 high; reorder the ready queue so that the insn with lowest LUID will be
412 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
413 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
415 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
416 can be returned from TARGET_SCHED_REORDER2.
418 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
420 #undef TARGET_SCHED_DFA_NEW_CYCLE
421 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
423 #undef TARGET_SCHED_INIT_GLOBAL
424 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
426 #undef TARGET_SCHED_FINISH_GLOBAL
427 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
429 #undef TARGET_SCHED_VARIABLE_ISSUE
430 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
432 #undef TARGET_SCHED_REORDER
433 #define TARGET_SCHED_REORDER sh_reorder
435 #undef TARGET_SCHED_REORDER2
436 #define TARGET_SCHED_REORDER2 sh_reorder2
438 #undef TARGET_SCHED_INIT
439 #define TARGET_SCHED_INIT sh_md_init
441 #undef TARGET_DELEGITIMIZE_ADDRESS
442 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
444 #undef TARGET_LEGITIMIZE_ADDRESS
445 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
447 #undef TARGET_CANNOT_MODIFY_JUMPS_P
448 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
449 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
450 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
451 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
452 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
453 sh_optimize_target_register_callee_saved
455 #undef TARGET_MS_BITFIELD_LAYOUT_P
456 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
458 #undef TARGET_INIT_BUILTINS
459 #define TARGET_INIT_BUILTINS sh_init_builtins
460 #undef TARGET_BUILTIN_DECL
461 #define TARGET_BUILTIN_DECL sh_builtin_decl
462 #undef TARGET_EXPAND_BUILTIN
463 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
465 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
466 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
468 #undef TARGET_CANNOT_COPY_INSN_P
469 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
470 #undef TARGET_RTX_COSTS
471 #define TARGET_RTX_COSTS sh_rtx_costs
472 #undef TARGET_ADDRESS_COST
473 #define TARGET_ADDRESS_COST sh_address_cost
474 #undef TARGET_ALLOCATE_INITIAL_VALUE
475 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
477 #undef TARGET_MACHINE_DEPENDENT_REORG
478 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
480 #undef TARGET_DWARF_REGISTER_SPAN
481 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
484 #undef TARGET_HAVE_TLS
485 #define TARGET_HAVE_TLS true
488 #undef TARGET_PROMOTE_PROTOTYPES
489 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
490 #undef TARGET_PROMOTE_FUNCTION_MODE
491 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
493 #undef TARGET_FUNCTION_VALUE
494 #define TARGET_FUNCTION_VALUE sh_function_value
495 #undef TARGET_FUNCTION_VALUE_REGNO_P
496 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
497 #undef TARGET_LIBCALL_VALUE
498 #define TARGET_LIBCALL_VALUE sh_libcall_value
499 #undef TARGET_STRUCT_VALUE_RTX
500 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
501 #undef TARGET_RETURN_IN_MEMORY
502 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
504 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
505 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
506 #undef TARGET_SETUP_INCOMING_VARARGS
507 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
508 #undef TARGET_STRICT_ARGUMENT_NAMING
509 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
510 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
511 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
512 #undef TARGET_MUST_PASS_IN_STACK
513 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
514 #undef TARGET_PASS_BY_REFERENCE
515 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
516 #undef TARGET_CALLEE_COPIES
517 #define TARGET_CALLEE_COPIES sh_callee_copies
518 #undef TARGET_ARG_PARTIAL_BYTES
519 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
520 #undef TARGET_FUNCTION_ARG
521 #define TARGET_FUNCTION_ARG sh_function_arg
522 #undef TARGET_FUNCTION_ARG_ADVANCE
523 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
525 #undef TARGET_BUILD_BUILTIN_VA_LIST
526 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
527 #undef TARGET_EXPAND_BUILTIN_VA_START
528 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
529 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
530 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
532 #undef TARGET_SCALAR_MODE_SUPPORTED_P
533 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
534 #undef TARGET_VECTOR_MODE_SUPPORTED_P
535 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
537 #undef TARGET_CHECK_PCH_TARGET_FLAGS
538 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
540 #undef TARGET_DWARF_CALLING_CONVENTION
541 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
543 #undef TARGET_FRAME_POINTER_REQUIRED
544 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
546 /* Return regmode weight for insn. */
547 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
549 /* Return current register pressure for regmode. */
550 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
552 #undef TARGET_ENCODE_SECTION_INFO
553 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
555 #undef TARGET_SECONDARY_RELOAD
556 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
558 #undef TARGET_PREFERRED_RELOAD_CLASS
559 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
561 #undef TARGET_CONDITIONAL_REGISTER_USAGE
562 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
564 #undef TARGET_LEGITIMATE_ADDRESS_P
565 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
567 #undef TARGET_TRAMPOLINE_INIT
568 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
569 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
570 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
572 #undef TARGET_LEGITIMATE_CONSTANT_P
573 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
575 /* Machine-specific symbol_ref flags. */
576 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
578 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
579 is used by optabs.c atomic op expansion code as well as in sync.md. */
580 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
581 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
583 struct gcc_target targetm = TARGET_INITIALIZER;
585 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
586 various options, and do some machine dependent initialization. */
588 sh_option_override (void)
592 SUBTARGET_OVERRIDE_OPTIONS;
593 if (optimize > 1 && !optimize_size)
594 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
595 if (flag_finite_math_only == 2)
596 flag_finite_math_only
597 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
598 if (TARGET_SH2E && !flag_finite_math_only)
599 target_flags |= MASK_IEEE;
600 sh_cpu = PROCESSOR_SH1;
601 assembler_dialect = 0;
603 sh_cpu = PROCESSOR_SH2;
605 sh_cpu = PROCESSOR_SH2E;
607 sh_cpu = PROCESSOR_SH2A;
609 sh_cpu = PROCESSOR_SH3;
611 sh_cpu = PROCESSOR_SH3E;
614 assembler_dialect = 1;
615 sh_cpu = PROCESSOR_SH4;
617 if (TARGET_SH4A_ARCH)
619 assembler_dialect = 1;
620 sh_cpu = PROCESSOR_SH4A;
624 sh_cpu = PROCESSOR_SH5;
625 target_flags |= MASK_ALIGN_DOUBLE;
626 if (TARGET_SHMEDIA_FPU)
627 target_flags |= MASK_FMOVD;
630 /* There are no delay slots on SHmedia. */
631 flag_delayed_branch = 0;
632 /* Relaxation isn't yet supported for SHmedia */
633 target_flags &= ~MASK_RELAX;
634 /* After reload, if conversion does little good but can cause
636 - find_if_block doesn't do anything for SH because we don't
637 have conditional execution patterns. (We use conditional
638 move patterns, which are handled differently, and only
640 - find_cond_trap doesn't do anything for the SH because we
641 don't have conditional traps.
642 - find_if_case_1 uses redirect_edge_and_branch_force in
643 the only path that does an optimization, and this causes
644 an ICE when branch targets are in registers.
645 - find_if_case_2 doesn't do anything for the SHmedia after
646 reload except when it can redirect a tablejump - and
647 that's rather rare. */
648 flag_if_conversion2 = 0;
649 if (! strcmp (sh_div_str, "call"))
650 sh_div_strategy = SH_DIV_CALL;
651 else if (! strcmp (sh_div_str, "call2"))
652 sh_div_strategy = SH_DIV_CALL2;
653 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
654 sh_div_strategy = SH_DIV_FP;
655 else if (! strcmp (sh_div_str, "inv"))
656 sh_div_strategy = SH_DIV_INV;
657 else if (! strcmp (sh_div_str, "inv:minlat"))
658 sh_div_strategy = SH_DIV_INV_MINLAT;
659 else if (! strcmp (sh_div_str, "inv20u"))
660 sh_div_strategy = SH_DIV_INV20U;
661 else if (! strcmp (sh_div_str, "inv20l"))
662 sh_div_strategy = SH_DIV_INV20L;
663 else if (! strcmp (sh_div_str, "inv:call2"))
664 sh_div_strategy = SH_DIV_INV_CALL2;
665 else if (! strcmp (sh_div_str, "inv:call"))
666 sh_div_strategy = SH_DIV_INV_CALL;
667 else if (! strcmp (sh_div_str, "inv:fp"))
670 sh_div_strategy = SH_DIV_INV_FP;
672 sh_div_strategy = SH_DIV_INV;
674 TARGET_CBRANCHDI4 = 0;
675 /* Assembler CFI isn't yet fully supported for SHmedia. */
676 flag_dwarf2_cfi_asm = 0;
681 /* Only the sh64-elf assembler fully supports .quad properly. */
682 targetm.asm_out.aligned_op.di = NULL;
683 targetm.asm_out.unaligned_op.di = NULL;
687 if (! strcmp (sh_div_str, "call-div1"))
688 sh_div_strategy = SH_DIV_CALL_DIV1;
689 else if (! strcmp (sh_div_str, "call-fp")
690 && (TARGET_FPU_DOUBLE
691 || (TARGET_HARD_SH4 && TARGET_SH2E)
692 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
693 sh_div_strategy = SH_DIV_CALL_FP;
694 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
695 sh_div_strategy = SH_DIV_CALL_TABLE;
697 /* Pick one that makes most sense for the target in general.
698 It is not much good to use different functions depending
699 on -Os, since then we'll end up with two different functions
700 when some of the code is compiled for size, and some for
703 /* SH4 tends to emphasize speed. */
705 sh_div_strategy = SH_DIV_CALL_TABLE;
706 /* These have their own way of doing things. */
707 else if (TARGET_SH2A)
708 sh_div_strategy = SH_DIV_INTRINSIC;
709 /* ??? Should we use the integer SHmedia function instead? */
710 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
711 sh_div_strategy = SH_DIV_CALL_FP;
712 /* SH1 .. SH3 cores often go into small-footprint systems, so
713 default to the smallest implementation available. */
714 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
715 sh_div_strategy = SH_DIV_CALL_TABLE;
717 sh_div_strategy = SH_DIV_CALL_DIV1;
720 TARGET_PRETEND_CMOVE = 0;
721 if (sh_divsi3_libfunc[0])
722 ; /* User supplied - leave it alone. */
723 else if (TARGET_DIVIDE_CALL_FP)
724 sh_divsi3_libfunc = "__sdivsi3_i4";
725 else if (TARGET_DIVIDE_CALL_TABLE)
726 sh_divsi3_libfunc = "__sdivsi3_i4i";
728 sh_divsi3_libfunc = "__sdivsi3_1";
730 sh_divsi3_libfunc = "__sdivsi3";
731 if (sh_branch_cost == -1)
735 /* The SH1 does not have delay slots, hence we get a pipeline stall
736 at every branch. The SH4 is superscalar, so the single delay slot
737 is not sufficient to keep both pipelines filled. */
738 if (! TARGET_SH2 || TARGET_HARD_SH4)
742 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
743 if (! VALID_REGISTER_P (regno))
744 sh_register_names[regno][0] = '\0';
746 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
747 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
748 sh_additional_register_names[regno][0] = '\0';
750 if ((flag_pic && ! TARGET_PREFERGOT)
751 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
752 flag_no_function_cse = 1;
754 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
756 /* Never run scheduling before reload, since that can
757 break global alloc, and generates slower code anyway due
758 to the pressure on R0. */
759 /* Enable sched1 for SH4 if the user explicitly requests.
760 When sched1 is enabled, the ready queue will be reordered by
761 the target hooks if pressure is high. We can not do this for
762 PIC, SH3 and lower as they give spill failures for R0. */
763 if (!TARGET_HARD_SH4 || flag_pic)
764 flag_schedule_insns = 0;
765 /* ??? Current exception handling places basic block boundaries
766 after call_insns. It causes the high pressure on R0 and gives
767 spill failures for R0 in reload. See PR 22553 and the thread
769 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
770 else if (flag_exceptions)
772 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
773 warning (0, "ignoring -fschedule-insns because of exception handling bug");
774 flag_schedule_insns = 0;
776 else if (flag_schedule_insns
777 && !global_options_set.x_flag_schedule_insns)
778 flag_schedule_insns = 0;
781 /* Unwind info is not correct around the CFG unless either a frame
782 pointer is present or M_A_O_A is set. Fixing this requires rewriting
783 unwind info generation to be aware of the CFG and propagating states
785 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
786 || flag_exceptions || flag_non_call_exceptions)
787 && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS)
789 warning (0, "unwind tables currently require either a frame pointer "
790 "or -maccumulate-outgoing-args for correctness");
791 TARGET_ACCUMULATE_OUTGOING_ARGS = 1;
794 /* Unwinding with -freorder-blocks-and-partition does not work on this
795 architecture, because it requires far jumps to label crossing between
796 hot/cold sections which are rejected on this architecture. */
797 if (flag_reorder_blocks_and_partition)
801 inform (input_location,
802 "-freorder-blocks-and-partition does not work with "
803 "exceptions on this architecture");
804 flag_reorder_blocks_and_partition = 0;
805 flag_reorder_blocks = 1;
807 else if (flag_unwind_tables)
809 inform (input_location,
810 "-freorder-blocks-and-partition does not support unwind "
811 "info on this architecture");
812 flag_reorder_blocks_and_partition = 0;
813 flag_reorder_blocks = 1;
817 if (align_loops == 0)
818 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
819 if (align_jumps == 0)
820 align_jumps = 1 << CACHE_LOG;
821 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
822 align_jumps = TARGET_SHMEDIA ? 4 : 2;
824 /* Allocation boundary (in *bytes*) for the code of a function.
825 SH1: 32 bit alignment is faster, because instructions are always
826 fetched as a pair from a longword boundary.
827 SH2 .. SH5 : align to cache line start. */
828 if (align_functions == 0)
830 = optimize_size ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
831 /* The linker relaxation code breaks when a function contains
832 alignments that are larger than that at the start of a
837 = align_loops > align_jumps ? align_loops : align_jumps;
839 /* Also take possible .long constants / mova tables int account. */
842 if (align_functions < min_align)
843 align_functions = min_align;
846 if (sh_fixed_range_str)
847 sh_fix_range (sh_fixed_range_str);
849 /* This target defaults to strict volatile bitfields. */
850 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
851 flag_strict_volatile_bitfields = 1;
854 /* Print the operand address in x to the stream. */
857 sh_print_operand_address (FILE *stream, rtx x)
859 switch (GET_CODE (x))
863 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
868 rtx base = XEXP (x, 0);
869 rtx index = XEXP (x, 1);
871 switch (GET_CODE (index))
874 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
875 reg_names[true_regnum (base)]);
881 int base_num = true_regnum (base);
882 int index_num = true_regnum (index);
884 fprintf (stream, "@(r0,%s)",
885 reg_names[MAX (base_num, index_num)]);
896 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
900 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
904 x = mark_constant_pool_use (x);
905 output_addr_const (stream, x);
910 /* Print operand x (an rtx) in assembler syntax to file stream
911 according to modifier code.
913 '.' print a .s if insn needs delay slot
914 ',' print LOCAL_LABEL_PREFIX
915 '@' print trap, rte or rts depending upon pragma interruptness
916 '#' output a nop if there is nothing to put in the delay slot
917 ''' print likelihood suffix (/u for unlikely).
918 '>' print branch target if -fverbose-asm
919 'O' print a constant without the #
920 'R' print the LSW of a dp value - changes if in little endian
921 'S' print the MSW of a dp value - changes if in little endian
922 'T' print the next word of a dp value - same as 'R' in big endian mode.
923 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
924 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
925 'N' print 'r63' if the operand is (const_int 0).
926 'd' print a V2SF reg as dN instead of fpN.
927 'm' print a pair `base,offset' or `base,index', for LD and ST.
928 'U' Likewise for {LD,ST}{HI,LO}.
929 'V' print the position of a single bit set.
930 'W' print the position of a single bit cleared.
931 't' print a memory address which is a register.
932 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
933 'o' output an operator. */
936 sh_print_operand (FILE *stream, rtx x, int code)
939 enum machine_mode mode;
947 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
948 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
949 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
952 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
955 trapa_attr = lookup_attribute ("trap_exit",
956 DECL_ATTRIBUTES (current_function_decl));
958 fprintf (stream, "trapa #%ld",
959 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
960 else if (sh_cfun_interrupt_handler_p ())
962 if (sh_cfun_resbank_handler_p ())
963 fprintf (stream, "resbank\n");
964 fprintf (stream, "rte");
967 fprintf (stream, "rts");
970 /* Output a nop if there's nothing in the delay slot. */
971 if (dbr_sequence_length () == 0)
972 fprintf (stream, "\n\tnop");
976 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
978 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
979 fputs ("/u", stream);
983 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
985 fputs ("\t! target: ", stream);
986 output_addr_const (stream, JUMP_LABEL (current_output_insn));
990 x = mark_constant_pool_use (x);
991 output_addr_const (stream, x);
993 /* N.B.: %R / %S / %T adjust memory addresses by four.
994 For SHMEDIA, that means they can be used to access the first and
995 second 32 bit part of a 64 bit (or larger) value that
996 might be held in floating point registers or memory.
997 While they can be used to access 64 bit parts of a larger value
998 held in general purpose registers, that won't work with memory -
999 neither for fp registers, since the frxx names are used. */
1001 if (REG_P (x) || GET_CODE (x) == SUBREG)
1003 regno = true_regnum (x);
1004 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1005 fputs (reg_names[regno], (stream));
1009 x = adjust_address (x, SImode, 4 * LSW);
1010 sh_print_operand_address (stream, XEXP (x, 0));
1016 mode = GET_MODE (x);
1017 if (mode == VOIDmode)
1019 if (GET_MODE_SIZE (mode) >= 8)
1020 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1022 sh_print_operand (stream, sub, 0);
1024 output_operand_lossage ("invalid operand to %%R");
1028 if (REG_P (x) || GET_CODE (x) == SUBREG)
1030 regno = true_regnum (x);
1031 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1032 fputs (reg_names[regno], (stream));
1036 x = adjust_address (x, SImode, 4 * MSW);
1037 sh_print_operand_address (stream, XEXP (x, 0));
1043 mode = GET_MODE (x);
1044 if (mode == VOIDmode)
1046 if (GET_MODE_SIZE (mode) >= 8)
1047 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1049 sh_print_operand (stream, sub, 0);
1051 output_operand_lossage ("invalid operand to %%S");
1055 /* Next word of a double. */
1056 switch (GET_CODE (x))
1059 fputs (reg_names[REGNO (x) + 1], (stream));
1062 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1063 && GET_CODE (XEXP (x, 0)) != POST_INC)
1064 x = adjust_address (x, SImode, 4);
1065 sh_print_operand_address (stream, XEXP (x, 0));
1073 gcc_assert (MEM_P (x));
1075 switch (GET_CODE (x))
1079 sh_print_operand (stream, x, 0);
1087 switch (GET_CODE (x))
1089 case PLUS: fputs ("add", stream); break;
1090 case MINUS: fputs ("sub", stream); break;
1091 case MULT: fputs ("mul", stream); break;
1092 case DIV: fputs ("div", stream); break;
1093 case EQ: fputs ("eq", stream); break;
1094 case NE: fputs ("ne", stream); break;
1095 case GT: case LT: fputs ("gt", stream); break;
1096 case GE: case LE: fputs ("ge", stream); break;
1097 case GTU: case LTU: fputs ("gtu", stream); break;
1098 case GEU: case LEU: fputs ("geu", stream); break;
1107 && GET_CODE (XEXP (x, 0)) == PLUS
1108 && (REG_P (XEXP (XEXP (x, 0), 1))
1109 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1110 fputc ('x', stream);
1116 switch (GET_MODE (x))
1118 case QImode: fputs (".b", stream); break;
1119 case HImode: fputs (".w", stream); break;
1120 case SImode: fputs (".l", stream); break;
1121 case SFmode: fputs (".s", stream); break;
1122 case DFmode: fputs (".d", stream); break;
1123 default: gcc_unreachable ();
1130 gcc_assert (MEM_P (x));
1134 switch (GET_CODE (x))
1138 sh_print_operand (stream, x, 0);
1139 fputs (", 0", stream);
1143 sh_print_operand (stream, XEXP (x, 0), 0);
1144 fputs (", ", stream);
1145 sh_print_operand (stream, XEXP (x, 1), 0);
1155 int num = exact_log2 (INTVAL (x));
1156 gcc_assert (num >= 0);
1157 fprintf (stream, "#%d", num);
1163 int num = exact_log2 (~INTVAL (x));
1164 gcc_assert (num >= 0);
1165 fprintf (stream, "#%d", num);
1170 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1172 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1176 if (x == CONST0_RTX (GET_MODE (x)))
1178 fprintf ((stream), "r63");
1181 goto default_output;
1183 if (CONST_INT_P (x))
1185 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1193 mode = GET_MODE (x);
1195 switch (GET_CODE (x))
1199 rtx inner = XEXP (x, 0);
1201 enum machine_mode inner_mode;
1203 /* We might see SUBREGs with vector mode registers inside. */
1204 if (GET_CODE (inner) == SUBREG
1205 && (GET_MODE_SIZE (GET_MODE (inner))
1206 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1207 && subreg_lowpart_p (inner))
1208 inner = SUBREG_REG (inner);
1209 if (CONST_INT_P (inner))
1211 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1212 goto default_output;
1214 inner_mode = GET_MODE (inner);
1215 if (GET_CODE (inner) == SUBREG
1216 && (GET_MODE_SIZE (GET_MODE (inner))
1217 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1218 && REG_P (SUBREG_REG (inner)))
1220 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1221 GET_MODE (SUBREG_REG (inner)),
1222 SUBREG_BYTE (inner),
1224 inner = SUBREG_REG (inner);
1226 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1228 /* Floating point register pairs are always big endian;
1229 general purpose registers are 64 bit wide. */
1230 regno = REGNO (inner);
1231 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1232 - HARD_REGNO_NREGS (regno, mode))
1240 /* FIXME: We need this on SHmedia32 because reload generates
1241 some sign-extended HI or QI loads into DImode registers
1242 but, because Pmode is SImode, the address ends up with a
1243 subreg:SI of the DImode register. Maybe reload should be
1244 fixed so as to apply alter_subreg to such loads? */
1246 gcc_assert (trapping_target_operand (x, VOIDmode));
1247 x = XEXP (XEXP (x, 2), 0);
1248 goto default_output;
1250 gcc_assert (SUBREG_BYTE (x) == 0
1251 && REG_P (SUBREG_REG (x)));
1259 if (FP_REGISTER_P (regno)
1260 && mode == V16SFmode)
1261 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1262 else if (FP_REGISTER_P (REGNO (x))
1263 && mode == V4SFmode)
1264 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1266 && mode == V2SFmode)
1267 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1268 else if (FP_REGISTER_P (REGNO (x))
1269 && GET_MODE_SIZE (mode) > 4)
1270 fprintf ((stream), "d%s", reg_names[regno] + 1);
1272 fputs (reg_names[regno], (stream));
1276 output_address (XEXP (x, 0));
1281 fputc ('#', stream);
1282 output_addr_const (stream, x);
1290 sh_print_operand_punct_valid_p (unsigned char code)
1292 return (code == '.' || code == '#' || code == '@' || code == ','
1293 || code == '$' || code == '\'' || code == '>');
1296 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1299 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1301 if (GET_CODE (x) == UNSPEC)
1303 switch (XINT (x, 1))
1305 case UNSPEC_DATALABEL:
1306 fputs ("datalabel ", file);
1307 output_addr_const (file, XVECEXP (x, 0, 0));
1310 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1311 output_addr_const (file, XVECEXP (x, 0, 0));
1314 output_addr_const (file, XVECEXP (x, 0, 0));
1315 fputs ("@GOT", file);
1318 output_addr_const (file, XVECEXP (x, 0, 0));
1319 fputs ("@GOTOFF", file);
1322 output_addr_const (file, XVECEXP (x, 0, 0));
1323 fputs ("@PLT", file);
1326 output_addr_const (file, XVECEXP (x, 0, 0));
1327 fputs ("@GOTPLT", file);
1330 output_addr_const (file, XVECEXP (x, 0, 0));
1331 fputs ("@DTPOFF", file);
1333 case UNSPEC_GOTTPOFF:
1334 output_addr_const (file, XVECEXP (x, 0, 0));
1335 fputs ("@GOTTPOFF", file);
1338 output_addr_const (file, XVECEXP (x, 0, 0));
1339 fputs ("@TPOFF", file);
1344 /* LPCS stands for Label for PIC Call Site. */
1345 targetm.asm_out.generate_internal_label (name, "LPCS",
1346 INTVAL (XVECEXP (x, 0, 0)));
1347 assemble_name (file, name);
1350 case UNSPEC_EXTRACT_S16:
1351 case UNSPEC_EXTRACT_U16:
1355 val = XVECEXP (x, 0, 0);
1356 shift = XVECEXP (x, 0, 1);
1358 if (shift != const0_rtx)
1360 if (GET_CODE (val) == CONST
1361 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
1364 output_addr_const (file, val);
1368 output_addr_const (file, val);
1369 if (shift != const0_rtx)
1371 fputs (" >> ", file);
1372 output_addr_const (file, shift);
1375 fputs (" & 65535)", file);
1379 output_addr_const (file, XVECEXP (x, 0, 0));
1381 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1384 output_addr_const (file, XVECEXP (x, 0, 1));
1388 output_addr_const (file, XVECEXP (x, 0, 1));
1390 case UNSPEC_PCREL_SYMOFF:
1391 output_addr_const (file, XVECEXP (x, 0, 0));
1393 output_addr_const (file, XVECEXP (x, 0, 1));
1394 fputs ("-.)", file);
1406 /* Encode symbol attributes of a SYMBOL_REF into its
1407 SYMBOL_REF_FLAGS. */
1409 sh_encode_section_info (tree decl, rtx rtl, int first)
1411 default_encode_section_info (decl, rtl, first);
1413 if (TREE_CODE (decl) == FUNCTION_DECL
1414 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1415 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1418 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1420 force_into (rtx value, rtx target)
1422 value = force_operand (value, target);
1423 if (! rtx_equal_p (value, target))
1424 emit_insn (gen_move_insn (target, value));
1427 /* Emit code to perform a block move. Choose the best method.
1429 OPERANDS[0] is the destination.
1430 OPERANDS[1] is the source.
1431 OPERANDS[2] is the size.
1432 OPERANDS[3] is the alignment safe to use. */
1435 expand_block_move (rtx *operands)
1437 int align = INTVAL (operands[3]);
1438 int constp = (CONST_INT_P (operands[2]));
1439 int bytes = (constp ? INTVAL (operands[2]) : 0);
1444 /* If we could use mov.l to move words and dest is word-aligned, we
1445 can use movua.l for loads and still generate a relatively short
1446 and efficient sequence. */
1447 if (TARGET_SH4A_ARCH && align < 4
1448 && MEM_ALIGN (operands[0]) >= 32
1449 && can_move_by_pieces (bytes, 32))
1451 rtx dest = copy_rtx (operands[0]);
1452 rtx src = copy_rtx (operands[1]);
1453 /* We could use different pseudos for each copied word, but
1454 since movua can only load into r0, it's kind of
1456 rtx temp = gen_reg_rtx (SImode);
1457 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1460 while (copied + 4 <= bytes)
1462 rtx to = adjust_address (dest, SImode, copied);
1463 rtx from = adjust_automodify_address (src, BLKmode,
1466 set_mem_size (from, 4);
1467 emit_insn (gen_movua (temp, from));
1468 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1469 emit_move_insn (to, temp);
1474 move_by_pieces (adjust_address (dest, BLKmode, copied),
1475 adjust_automodify_address (src, BLKmode,
1477 bytes - copied, align, 0);
1482 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1483 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1484 if (align < 4 || (bytes % 4 != 0))
1487 if (TARGET_HARD_SH4)
1491 else if (bytes == 12)
1493 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1494 rtx r4 = gen_rtx_REG (SImode, 4);
1495 rtx r5 = gen_rtx_REG (SImode, 5);
1497 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1498 force_into (XEXP (operands[0], 0), r4);
1499 force_into (XEXP (operands[1], 0), r5);
1500 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1503 else if (! optimize_size)
1505 const char *entry_name;
1506 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1508 rtx r4 = gen_rtx_REG (SImode, 4);
1509 rtx r5 = gen_rtx_REG (SImode, 5);
1510 rtx r6 = gen_rtx_REG (SImode, 6);
1512 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1513 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1514 force_into (XEXP (operands[0], 0), r4);
1515 force_into (XEXP (operands[1], 0), r5);
1517 dwords = bytes >> 3;
1518 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1519 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1528 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1529 rtx r4 = gen_rtx_REG (SImode, 4);
1530 rtx r5 = gen_rtx_REG (SImode, 5);
1532 sprintf (entry, "__movmemSI%d", bytes);
1533 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1534 force_into (XEXP (operands[0], 0), r4);
1535 force_into (XEXP (operands[1], 0), r5);
1536 emit_insn (gen_block_move_real (func_addr_rtx));
1540 /* This is the same number of bytes as a memcpy call, but to a different
1541 less common function name, so this will occasionally use more space. */
1542 if (! optimize_size)
1544 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1545 int final_switch, while_loop;
1546 rtx r4 = gen_rtx_REG (SImode, 4);
1547 rtx r5 = gen_rtx_REG (SImode, 5);
1548 rtx r6 = gen_rtx_REG (SImode, 6);
1550 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1551 force_into (XEXP (operands[0], 0), r4);
1552 force_into (XEXP (operands[1], 0), r5);
1554 /* r6 controls the size of the move. 16 is decremented from it
1555 for each 64 bytes moved. Then the negative bit left over is used
1556 as an index into a list of move instructions. e.g., a 72 byte move
1557 would be set up with size(r6) = 14, for one iteration through the
1558 big while loop, and a switch of -2 for the last part. */
1560 final_switch = 16 - ((bytes / 4) % 16);
1561 while_loop = ((bytes / 4) / 16 - 1) * 16;
1562 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1563 emit_insn (gen_block_lump_real (func_addr_rtx));
1570 /* Prepare operands for a move define_expand; specifically, one of the
1571 operands must be in a register. */
1574 prepare_move_operands (rtx operands[], enum machine_mode mode)
1576 if ((mode == SImode || mode == DImode)
1578 && ! ((mode == Pmode || mode == ptr_mode)
1579 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1582 if (SYMBOLIC_CONST_P (operands[1]))
1584 if (MEM_P (operands[0]))
1585 operands[1] = force_reg (Pmode, operands[1]);
1586 else if (TARGET_SHMEDIA
1587 && GET_CODE (operands[1]) == LABEL_REF
1588 && target_reg_operand (operands[0], mode))
1592 temp = (!can_create_pseudo_p ()
1594 : gen_reg_rtx (Pmode));
1595 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1598 else if (GET_CODE (operands[1]) == CONST
1599 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1600 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1602 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1603 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1605 operands[1] = expand_binop (mode, add_optab, temp,
1606 XEXP (XEXP (operands[1], 0), 1),
1607 (!can_create_pseudo_p ()
1609 : gen_reg_rtx (Pmode)),
1610 0, OPTAB_LIB_WIDEN);
1614 if (! reload_in_progress && ! reload_completed)
1616 /* Copy the source to a register if both operands aren't registers. */
1617 if (! register_operand (operands[0], mode)
1618 && ! sh_register_operand (operands[1], mode))
1619 operands[1] = copy_to_mode_reg (mode, operands[1]);
1621 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1623 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1624 except that we can't use that function because it is static. */
1625 rtx new_rtx = change_address (operands[0], mode, 0);
1626 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1627 operands[0] = new_rtx;
1630 /* This case can happen while generating code to move the result
1631 of a library call to the target. Reject `st r0,@(rX,rY)' because
1632 reload will fail to find a spill register for rX, since r0 is already
1633 being used for the source. */
1635 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1636 && MEM_P (operands[0])
1637 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1638 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1639 operands[1] = copy_to_mode_reg (mode, operands[1]);
1642 if (mode == Pmode || mode == ptr_mode)
1645 enum tls_model tls_kind;
1649 if (GET_CODE (op1) == CONST
1650 && GET_CODE (XEXP (op1, 0)) == PLUS
1651 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1654 opc = XEXP (XEXP (op1, 0), 1);
1655 op1 = XEXP (XEXP (op1, 0), 0);
1660 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1662 rtx tga_op1, tga_ret, tmp, tmp2;
1665 && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC
1666 || tls_kind == TLS_MODEL_LOCAL_DYNAMIC
1667 || tls_kind == TLS_MODEL_INITIAL_EXEC))
1669 /* Don't schedule insns for getting GOT address when
1670 the first scheduling is enabled, to avoid spill
1672 if (flag_schedule_insns)
1673 emit_insn (gen_blockage ());
1674 emit_insn (gen_GOTaddr2picreg ());
1675 emit_use (gen_rtx_REG (SImode, PIC_REG));
1676 if (flag_schedule_insns)
1677 emit_insn (gen_blockage ());
1682 case TLS_MODEL_GLOBAL_DYNAMIC:
1683 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1684 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1685 tmp = gen_reg_rtx (Pmode);
1686 emit_move_insn (tmp, tga_ret);
1690 case TLS_MODEL_LOCAL_DYNAMIC:
1691 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1692 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1694 tmp = gen_reg_rtx (Pmode);
1695 emit_move_insn (tmp, tga_ret);
1697 if (register_operand (op0, Pmode))
1700 tmp2 = gen_reg_rtx (Pmode);
1702 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1706 case TLS_MODEL_INITIAL_EXEC:
1707 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1708 tmp = gen_sym2GOTTPOFF (op1);
1709 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1713 case TLS_MODEL_LOCAL_EXEC:
1714 tmp2 = gen_reg_rtx (Pmode);
1715 emit_insn (gen_load_gbr (tmp2));
1716 tmp = gen_reg_rtx (Pmode);
1717 emit_insn (gen_symTPOFF2reg (tmp, op1));
1719 if (register_operand (op0, Pmode))
1722 op1 = gen_reg_rtx (Pmode);
1724 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1731 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1740 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1741 enum rtx_code comparison)
1744 rtx scratch = NULL_RTX;
1746 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1747 comparison = GET_CODE (operands[0]);
1749 scratch = operands[4];
1750 if (CONST_INT_P (operands[1])
1751 && !CONST_INT_P (operands[2]))
1753 rtx tmp = operands[1];
1755 operands[1] = operands[2];
1757 comparison = swap_condition (comparison);
1759 if (CONST_INT_P (operands[2]))
1761 HOST_WIDE_INT val = INTVAL (operands[2]);
1762 if ((val == -1 || val == -0x81)
1763 && (comparison == GT || comparison == LE))
1765 comparison = (comparison == GT) ? GE : LT;
1766 operands[2] = gen_int_mode (val + 1, mode);
1768 else if ((val == 1 || val == 0x80)
1769 && (comparison == GE || comparison == LT))
1771 comparison = (comparison == GE) ? GT : LE;
1772 operands[2] = gen_int_mode (val - 1, mode);
1774 else if (val == 1 && (comparison == GEU || comparison == LTU))
1776 comparison = (comparison == GEU) ? NE : EQ;
1777 operands[2] = CONST0_RTX (mode);
1779 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1781 comparison = (comparison == GEU) ? GTU : LEU;
1782 operands[2] = gen_int_mode (val - 1, mode);
1784 else if (val == 0 && (comparison == GTU || comparison == LEU))
1785 comparison = (comparison == GTU) ? NE : EQ;
1786 else if (mode == SImode
1787 && ((val == 0x7fffffff
1788 && (comparison == GTU || comparison == LEU))
1789 || ((unsigned HOST_WIDE_INT) val
1790 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1791 && (comparison == GEU || comparison == LTU))))
1793 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1794 operands[2] = CONST0_RTX (mode);
1798 if (can_create_pseudo_p ())
1799 operands[1] = force_reg (mode, op1);
1800 /* When we are handling DImode comparisons, we want to keep constants so
1801 that we can optimize the component comparisons; however, memory loads
1802 are better issued as a whole so that they can be scheduled well.
1803 SImode equality comparisons allow I08 constants, but only when they
1804 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1805 into a register, that register might as well be r0, and we allow the
1806 constant. If it is already in a register, this is likely to be
1807 allocated to a different hard register, thus we load the constant into
1808 a register unless it is zero. */
1809 if (!REG_P (operands[2])
1810 && (!CONST_INT_P (operands[2])
1811 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1812 && ((comparison != EQ && comparison != NE)
1813 || (REG_P (op1) && REGNO (op1) != R0_REG)
1814 || !satisfies_constraint_I08 (operands[2])))))
1816 if (scratch && GET_MODE (scratch) == mode)
1818 emit_move_insn (scratch, operands[2]);
1819 operands[2] = scratch;
1821 else if (can_create_pseudo_p ())
1822 operands[2] = force_reg (mode, operands[2]);
1828 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1830 rtx (*branch_expander) (rtx) = gen_branch_true;
1833 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1836 case NE: case LT: case LE: case LTU: case LEU:
1837 comparison = reverse_condition (comparison);
1838 branch_expander = gen_branch_false;
1841 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1842 gen_rtx_fmt_ee (comparison, SImode,
1843 operands[1], operands[2])));
1844 jump = emit_jump_insn (branch_expander (operands[3]));
1845 if (probability >= 0)
1846 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1850 /* ??? How should we distribute probabilities when more than one branch
1851 is generated. So far we only have some ad-hoc observations:
1852 - If the operands are random, they are likely to differ in both parts.
1853 - If comparing items in a hash chain, the operands are random or equal;
1854 operation should be EQ or NE.
1855 - If items are searched in an ordered tree from the root, we can expect
1856 the highpart to be unequal about half of the time; operation should be
1857 an inequality comparison, operands non-constant, and overall probability
1858 about 50%. Likewise for quicksort.
1859 - Range checks will be often made against constants. Even if we assume for
1860 simplicity an even distribution of the non-constant operand over a
1861 sub-range here, the same probability could be generated with differently
1862 wide sub-ranges - as long as the ratio of the part of the subrange that
1863 is before the threshold to the part that comes after the threshold stays
1864 the same. Thus, we can't really tell anything here;
1865 assuming random distribution is at least simple.
1869 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1871 enum rtx_code msw_taken, msw_skip, lsw_taken;
1872 rtx skip_label = NULL_RTX;
1873 rtx op1h, op1l, op2h, op2l;
1876 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1877 rtx scratch = operands[4];
1879 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1880 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1881 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1882 op1l = gen_lowpart (SImode, operands[1]);
1883 op2l = gen_lowpart (SImode, operands[2]);
1884 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1885 prob = split_branch_probability;
1886 rev_prob = REG_BR_PROB_BASE - prob;
1889 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1890 That costs 1 cycle more when the first branch can be predicted taken,
1891 but saves us mispredicts because only one branch needs prediction.
1892 It also enables generating the cmpeqdi_t-1 pattern. */
1894 if (TARGET_CMPEQDI_T)
1896 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1897 emit_jump_insn (gen_branch_true (operands[3]));
1904 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1906 msw_skip_prob = rev_prob;
1907 if (REG_BR_PROB_BASE <= 65535)
1908 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1911 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1915 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1916 / ((HOST_WIDEST_INT) prob << 32)))
1922 if (TARGET_CMPEQDI_T)
1924 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1925 emit_jump_insn (gen_branch_false (operands[3]));
1929 msw_taken_prob = prob;
1934 msw_taken = comparison;
1935 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1937 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1938 msw_skip = swap_condition (msw_taken);
1942 if (op2l == CONST0_RTX (SImode))
1943 msw_taken = comparison;
1946 msw_taken = comparison == GE ? GT : GTU;
1947 msw_skip = swap_condition (msw_taken);
1952 msw_taken = comparison;
1953 if (op2l == CONST0_RTX (SImode))
1955 msw_skip = swap_condition (msw_taken);
1959 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1960 msw_taken = comparison;
1964 if (comparison == LE)
1966 else if (op2h != CONST0_RTX (SImode))
1970 msw_skip = swap_condition (LTU);
1973 msw_skip = swap_condition (msw_taken);
1976 default: return false;
1978 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1979 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1980 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1981 if (comparison != EQ && comparison != NE && num_branches > 1)
1983 if (!CONSTANT_P (operands[2])
1984 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1985 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1987 msw_taken_prob = prob / 2U;
1989 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1990 lsw_taken_prob = prob;
1994 msw_taken_prob = prob;
1995 msw_skip_prob = REG_BR_PROB_BASE;
1996 /* ??? If we have a constant op2h, should we use that when
1997 calculating lsw_taken_prob? */
1998 lsw_taken_prob = prob;
2003 operands[4] = NULL_RTX;
2004 if (reload_completed
2005 && ! arith_reg_or_0_operand (op2h, SImode)
2006 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
2007 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
2008 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
2010 emit_move_insn (scratch, operands[2]);
2011 operands[2] = scratch;
2013 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2014 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2015 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2017 rtx taken_label = operands[3];
2019 /* Operands were possibly modified, but msw_skip doesn't expect this.
2020 Always use the original ones. */
2021 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2025 if (reload_completed
2026 && ! arith_reg_or_0_operand (op2h, SImode)
2027 && (true_regnum (op1h) || (comparison != EQ && comparison != NE)))
2029 emit_move_insn (scratch, operands[2]);
2030 operands[2] = scratch;
2034 operands[3] = skip_label = gen_label_rtx ();
2035 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2036 operands[3] = taken_label;
2040 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2042 if (reload_completed
2043 && ! arith_reg_or_0_operand (op2l, SImode)
2044 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2046 emit_move_insn (scratch, operands[2]);
2047 operands[2] = scratch;
2049 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2051 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2052 emit_label (skip_label);
2056 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2059 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2061 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2063 insn = gen_rtx_PARALLEL (VOIDmode,
2065 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2066 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2072 /* Prepare the operands for an scc instruction; make sure that the
2073 compare has been done and the result is in T_REG. */
2075 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2077 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2078 enum rtx_code oldcode = code;
2079 enum machine_mode mode;
2081 /* First need a compare insn. */
2085 /* It isn't possible to handle this case. */
2102 if (code != oldcode)
2109 mode = GET_MODE (op0);
2110 if (mode == VOIDmode)
2111 mode = GET_MODE (op1);
2113 op0 = force_reg (mode, op0);
2114 if ((code != EQ && code != NE
2115 && (op1 != const0_rtx
2116 || code == GTU || code == GEU || code == LTU || code == LEU))
2117 || (mode == DImode && op1 != const0_rtx)
2118 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2119 op1 = force_reg (mode, op1);
2121 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2122 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2127 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2130 rtx target = gen_reg_rtx (SImode);
2133 gcc_assert (TARGET_SHMEDIA);
2142 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2143 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2153 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2154 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2172 rtx t2 = gen_reg_rtx (DImode);
2173 emit_insn (gen_extendsidi2 (t2, target));
2177 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2180 /* Called from the md file, set up the operands of a compare instruction. */
2183 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2185 enum rtx_code code = GET_CODE (operands[0]);
2186 enum rtx_code branch_code;
2187 rtx op0 = operands[1];
2188 rtx op1 = operands[2];
2190 bool need_ccmpeq = false;
2192 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2194 op0 = force_reg (mode, op0);
2195 op1 = force_reg (mode, op1);
2199 if (code != EQ || mode == DImode)
2201 /* Force args into regs, since we can't use constants here. */
2202 op0 = force_reg (mode, op0);
2203 if (op1 != const0_rtx || code == GTU || code == GEU)
2204 op1 = force_reg (mode, op1);
2208 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2211 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2212 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2214 tem = op0, op0 = op1, op1 = tem;
2215 code = swap_condition (code);
2218 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2221 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2226 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2227 to EQ/GT respectively. */
2228 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2245 branch_code = reverse_condition (code);
2251 insn = gen_rtx_SET (VOIDmode,
2252 gen_rtx_REG (SImode, T_REG),
2253 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2255 sh_emit_set_t_insn (insn, mode);
2257 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2259 if (branch_code == code)
2260 emit_jump_insn (gen_branch_true (operands[3]));
2262 emit_jump_insn (gen_branch_false (operands[3]));
2266 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2268 enum rtx_code code = GET_CODE (operands[1]);
2269 rtx op0 = operands[2];
2270 rtx op1 = operands[3];
2272 bool invert = false;
2275 op0 = force_reg (mode, op0);
2276 if ((code != EQ && code != NE
2277 && (op1 != const0_rtx
2278 || code == GTU || code == GEU || code == LTU || code == LEU))
2279 || (mode == DImode && op1 != const0_rtx)
2280 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2281 op1 = force_reg (mode, op1);
2283 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2285 if (code == LT || code == LE)
2287 code = swap_condition (code);
2288 tem = op0, op0 = op1, op1 = tem;
2294 lab = gen_label_rtx ();
2295 sh_emit_scc_to_t (EQ, op0, op1);
2296 emit_jump_insn (gen_branch_true (lab));
2313 sh_emit_scc_to_t (code, op0, op1);
2317 emit_insn (gen_movnegt (operands[0]));
2319 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2322 /* Functions to output assembly code. */
2324 /* Return a sequence of instructions to perform DI or DF move.
2326 Since the SH cannot move a DI or DF in one instruction, we have
2327 to take care when we see overlapping source and dest registers. */
2330 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2331 enum machine_mode mode)
2333 rtx dst = operands[0];
2334 rtx src = operands[1];
2337 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2338 return "mov.l %T1,%0\n\tmov.l %1,%0";
2340 if (register_operand (dst, mode)
2341 && register_operand (src, mode))
2343 if (REGNO (src) == MACH_REG)
2344 return "sts mach,%S0\n\tsts macl,%R0";
2346 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2347 when mov.d r1,r0 do r1->r0 then r2->r1. */
2349 if (REGNO (src) + 1 == REGNO (dst))
2350 return "mov %T1,%T0\n\tmov %1,%0";
2352 return "mov %1,%0\n\tmov %T1,%T0";
2354 else if (CONST_INT_P (src))
2356 if (INTVAL (src) < 0)
2357 output_asm_insn ("mov #-1,%S0", operands);
2359 output_asm_insn ("mov #0,%S0", operands);
2361 return "mov %1,%R0";
2363 else if (MEM_P (src))
2366 int dreg = REGNO (dst);
2367 rtx inside = XEXP (src, 0);
2369 switch (GET_CODE (inside))
2372 ptrreg = REGNO (inside);
2376 ptrreg = subreg_regno (inside);
2380 ptrreg = REGNO (XEXP (inside, 0));
2381 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2382 an offsettable address. Unfortunately, offsettable addresses use
2383 QImode to check the offset, and a QImode offsettable address
2384 requires r0 for the other operand, which is not currently
2385 supported, so we can't use the 'o' constraint.
2386 Thus we must check for and handle r0+REG addresses here.
2387 We punt for now, since this is likely very rare. */
2388 gcc_assert (!REG_P (XEXP (inside, 1)));
2392 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2394 return "mov.l %1,%0\n\tmov.l %1,%T0";
2399 /* Work out the safe way to copy. Copy into the second half first. */
2401 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2404 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2407 /* Print an instruction which would have gone into a delay slot after
2408 another instruction, but couldn't because the other instruction expanded
2409 into a sequence where putting the slot insn at the end wouldn't work. */
2412 print_slot (rtx insn)
2414 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2416 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2420 output_far_jump (rtx insn, rtx op)
2422 struct { rtx lab, reg, op; } this_jmp;
2423 rtx braf_base_lab = NULL_RTX;
2426 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2429 this_jmp.lab = gen_label_rtx ();
2433 && offset - get_attr_length (insn) <= 32766)
2436 jump = "mov.w %O0,%1; braf %1";
2444 jump = "mov.l %O0,%1; braf %1";
2446 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2449 jump = "mov.l %O0,%1; jmp @%1";
2451 /* If we have a scratch register available, use it. */
2452 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2453 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2455 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2456 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2457 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2458 output_asm_insn (jump, &this_jmp.lab);
2459 if (dbr_sequence_length ())
2460 print_slot (final_sequence);
2462 output_asm_insn ("nop", 0);
2466 /* Output the delay slot insn first if any. */
2467 if (dbr_sequence_length ())
2468 print_slot (final_sequence);
2470 this_jmp.reg = gen_rtx_REG (SImode, 13);
2471 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2472 Fortunately, MACL is fixed and call-clobbered, and we never
2473 need its value across jumps, so save r13 in it instead of in
2476 output_asm_insn ("lds r13, macl", 0);
2478 output_asm_insn ("mov.l r13,@-r15", 0);
2479 output_asm_insn (jump, &this_jmp.lab);
2481 output_asm_insn ("sts macl, r13", 0);
2483 output_asm_insn ("mov.l @r15+,r13", 0);
2485 if (far && flag_pic && TARGET_SH2)
2487 braf_base_lab = gen_label_rtx ();
2488 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2489 CODE_LABEL_NUMBER (braf_base_lab));
2492 output_asm_insn (".align 2", 0);
2493 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2495 if (far && flag_pic)
2498 this_jmp.lab = braf_base_lab;
2499 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2502 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2506 /* Local label counter, used for constants in the pool and inside
2507 pattern branches. */
2509 static int lf = 100;
2511 /* Output code for ordinary branches. */
2514 output_branch (int logic, rtx insn, rtx *operands)
2516 switch (get_attr_length (insn))
2519 /* This can happen if filling the delay slot has caused a forward
2520 branch to exceed its range (we could reverse it, but only
2521 when we know we won't overextend other branches; this should
2522 best be handled by relaxation).
2523 It can also happen when other condbranches hoist delay slot insn
2524 from their destination, thus leading to code size increase.
2525 But the branch will still be in the range -4092..+4098 bytes. */
2530 /* The call to print_slot will clobber the operands. */
2531 rtx op0 = operands[0];
2533 /* If the instruction in the delay slot is annulled (true), then
2534 there is no delay slot where we can put it now. The only safe
2535 place for it is after the label. final will do that by default. */
2538 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2539 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2541 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2542 ASSEMBLER_DIALECT ? "/" : ".", label);
2543 print_slot (final_sequence);
2546 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2548 output_asm_insn ("bra\t%l0", &op0);
2549 fprintf (asm_out_file, "\tnop\n");
2550 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2554 /* When relaxing, handle this like a short branch. The linker
2555 will fix it up if it still doesn't fit after relaxation. */
2557 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2559 /* These are for SH2e, in which we have to account for the
2560 extra nop because of the hardware bug in annulled branches. */
2566 gcc_assert (!final_sequence
2567 || !(INSN_ANNULLED_BRANCH_P
2568 (XVECEXP (final_sequence, 0, 0))));
2569 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2571 ASSEMBLER_DIALECT ? "/" : ".", label);
2572 fprintf (asm_out_file, "\tnop\n");
2573 output_asm_insn ("bra\t%l0", operands);
2574 fprintf (asm_out_file, "\tnop\n");
2575 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2579 /* When relaxing, fall through. */
2584 sprintf (buffer, "b%s%ss\t%%l0",
2586 ASSEMBLER_DIALECT ? "/" : ".");
2587 output_asm_insn (buffer, &operands[0]);
2592 /* There should be no longer branches now - that would
2593 indicate that something has destroyed the branches set
2594 up in machine_dependent_reorg. */
2599 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2600 fill in operands 9 as a label to the successor insn.
2601 We try to use jump threading where possible.
2602 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2603 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2604 follow jmp and bt, if the address is in range. */
2606 output_branchy_insn (enum rtx_code code, const char *templ,
2607 rtx insn, rtx *operands)
2609 rtx next_insn = NEXT_INSN (insn);
2611 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2613 rtx src = SET_SRC (PATTERN (next_insn));
2614 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2616 /* Following branch not taken */
2617 operands[9] = gen_label_rtx ();
2618 emit_label_after (operands[9], next_insn);
2619 INSN_ADDRESSES_NEW (operands[9],
2620 INSN_ADDRESSES (INSN_UID (next_insn))
2621 + get_attr_length (next_insn));
2626 int offset = (branch_dest (next_insn)
2627 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2628 if (offset >= -252 && offset <= 258)
2630 if (GET_CODE (src) == IF_THEN_ELSE)
2632 src = XEXP (src, 1);
2638 operands[9] = gen_label_rtx ();
2639 emit_label_after (operands[9], insn);
2640 INSN_ADDRESSES_NEW (operands[9],
2641 INSN_ADDRESSES (INSN_UID (insn))
2642 + get_attr_length (insn));
2647 output_ieee_ccmpeq (rtx insn, rtx *operands)
2649 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2653 /* Output the start of the assembler file. */
2656 sh_file_start (void)
2658 default_file_start ();
2661 /* We need to show the text section with the proper
2662 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2663 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2664 will complain. We can teach GAS specifically about the
2665 default attributes for our choice of text section, but
2666 then we would have to change GAS again if/when we change
2667 the text section name. */
2668 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2670 /* Switch to the data section so that the coffsem symbol
2671 isn't in the text section. */
2672 switch_to_section (data_section);
2674 if (TARGET_LITTLE_ENDIAN)
2675 fputs ("\t.little\n", asm_out_file);
2679 if (TARGET_SHCOMPACT)
2680 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2681 else if (TARGET_SHMEDIA)
2682 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2683 TARGET_SHMEDIA64 ? 64 : 32);
2687 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2690 unspec_caller_rtx_p (rtx pat)
2695 split_const (pat, &base, &offset);
2696 if (GET_CODE (base) == UNSPEC)
2698 if (XINT (base, 1) == UNSPEC_CALLER)
2700 for (i = 0; i < XVECLEN (base, 0); i++)
2701 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2707 /* Indicate that INSN cannot be duplicated. This is true for insn
2708 that generates a unique label. */
2711 sh_cannot_copy_insn_p (rtx insn)
2715 if (!reload_completed || !flag_pic)
2718 if (!NONJUMP_INSN_P (insn))
2720 if (asm_noperands (insn) >= 0)
2723 pat = PATTERN (insn);
2724 if (GET_CODE (pat) != SET)
2726 pat = SET_SRC (pat);
2728 if (unspec_caller_rtx_p (pat))
2734 /* Actual number of instructions used to make a shift by N. */
2735 static const char ashiftrt_insns[] =
2736 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2738 /* Left shift and logical right shift are the same. */
2739 static const char shift_insns[] =
2740 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2742 /* Individual shift amounts needed to get the above length sequences.
2743 One bit right shifts clobber the T bit, so when possible, put one bit
2744 shifts in the middle of the sequence, so the ends are eligible for
2745 branch delay slots. */
2746 static const short shift_amounts[32][5] = {
2747 {0}, {1}, {2}, {2, 1},
2748 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2749 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2750 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2751 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2752 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2753 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2754 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2756 /* Likewise, but for shift amounts < 16, up to three highmost bits
2757 might be clobbered. This is typically used when combined with some
2758 kind of sign or zero extension. */
2760 static const char ext_shift_insns[] =
2761 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2763 static const short ext_shift_amounts[32][4] = {
2764 {0}, {1}, {2}, {2, 1},
2765 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2766 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2767 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2768 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2769 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2770 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2771 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2773 /* Assuming we have a value that has been sign-extended by at least one bit,
2774 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2775 to shift it by N without data loss, and quicker than by other means? */
2776 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2778 /* This is used in length attributes in sh.md to help compute the length
2779 of arbitrary constant shift instructions. */
2782 shift_insns_rtx (rtx insn)
2784 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2785 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2786 enum rtx_code shift_code = GET_CODE (set_src);
2791 return ashiftrt_insns[shift_count];
2794 return shift_insns[shift_count];
2800 /* Return the cost of a shift. */
2807 /* There is no pattern for constant first operand. */
2808 if (CONST_INT_P (XEXP (x, 0)))
2812 return COSTS_N_INSNS (1);
2814 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2816 if (GET_MODE (x) == DImode
2817 && CONST_INT_P (XEXP (x, 1))
2818 && INTVAL (XEXP (x, 1)) == 1)
2819 return COSTS_N_INSNS (2);
2821 /* Everything else is invalid, because there is no pattern for it. */
2824 /* If shift by a non constant, then this will be expensive. */
2825 if (!CONST_INT_P (XEXP (x, 1)))
2826 return COSTS_N_INSNS (SH_DYNAMIC_SHIFT_COST);
2828 /* Otherwise, return the true cost in instructions. Cope with out of range
2829 shift counts more or less arbitrarily. */
2830 value = INTVAL (XEXP (x, 1)) & 31;
2832 if (GET_CODE (x) == ASHIFTRT)
2834 int cost = ashiftrt_insns[value];
2835 /* If SH3, then we put the constant in a reg and use shad. */
2836 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2837 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2838 return COSTS_N_INSNS (cost);
2841 return COSTS_N_INSNS (shift_insns[value]);
2844 /* Return the cost of an AND/XOR/IOR operation. */
2847 and_xor_ior_costs (rtx x, int code)
2851 /* A logical operation with two registers is a single cycle
2853 if (!CONST_INT_P (XEXP (x, 1)))
2856 i = INTVAL (XEXP (x, 1));
2860 if (satisfies_constraint_I10 (XEXP (x, 1))
2861 || satisfies_constraint_J16 (XEXP (x, 1)))
2864 return 1 + rtx_cost (XEXP (x, 1), AND, 1, !optimize_size);
2867 /* These constants are single cycle extu.[bw] instructions. */
2868 if ((i == 0xff || i == 0xffff) && code == AND)
2870 /* Constants that can be used in an instruction as an immediate are
2871 a single cycle, but this requires r0, so make it a little more
2873 if (CONST_OK_FOR_K08 (i))
2875 /* Constants that can be loaded with a mov immediate need one more cycle.
2876 This case is probably unnecessary. */
2877 if (CONST_OK_FOR_I08 (i))
2879 /* Any other constant requires an additional 2 cycle pc-relative load.
2880 This case is probably unnecessary. */
2884 /* Return the cost of an addition or a subtraction. */
2889 /* Adding a register is a single cycle insn. */
2890 if (REG_P (XEXP (x, 1))
2891 || GET_CODE (XEXP (x, 1)) == SUBREG)
2894 /* Likewise for small constants. */
2895 if (CONST_INT_P (XEXP (x, 1))
2896 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2900 switch (GET_CODE (XEXP (x, 1)))
2905 return TARGET_SHMEDIA64 ? 5 : 3;
2908 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2910 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2912 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2920 /* Any other constant requires a 2 cycle pc-relative load plus an
2925 /* Return the cost of a multiply. */
2927 multcosts (rtx x ATTRIBUTE_UNUSED)
2929 if (sh_multcost >= 0)
2932 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2933 accept constants. Ideally, we would use a cost of one or two and
2934 add the cost of the operand, but disregard the latter when inside loops
2935 and loop invariant code motion is still to follow.
2936 Using a multiply first and splitting it later if it's a loss
2937 doesn't work because of different sign / zero extension semantics
2938 of multiplies vs. shifts. */
2939 return optimize_size ? 2 : 3;
2943 /* We have a mul insn, so we can never take more than the mul and the
2944 read of the mac reg, but count more because of the latency and extra
2951 /* If we're aiming at small code, then just count the number of
2952 insns in a multiply call sequence. */
2956 /* Otherwise count all the insns in the routine we'd be calling too. */
2960 /* Compute a (partial) cost for rtx X. Return true if the complete
2961 cost has been computed, and false if subexpressions should be
2962 scanned. In either case, *TOTAL contains the cost result. */
2965 sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2966 int *total, bool speed ATTRIBUTE_UNUSED)
2973 if (INTVAL (x) == 0)
2975 else if (outer_code == AND && and_operand ((x), DImode))
2977 else if ((outer_code == IOR || outer_code == XOR
2978 || outer_code == PLUS)
2979 && CONST_OK_FOR_I10 (INTVAL (x)))
2981 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2982 *total = COSTS_N_INSNS (outer_code != SET);
2983 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2984 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2985 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2986 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2988 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2991 if (CONST_OK_FOR_I08 (INTVAL (x)))
2993 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2994 && CONST_OK_FOR_K08 (INTVAL (x)))
2996 /* prepare_cmp_insn will force costly constants int registers before
2997 the cbranch[sd]i4 patterns can see them, so preserve potentially
2998 interesting ones not covered by I08 above. */
2999 else if (outer_code == COMPARE
3000 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3001 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3002 || INTVAL (x) == 0x7fffffff
3003 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3010 /* An and with a constant compared against zero is
3011 most likely going to be a TST #imm, R0 instruction.
3012 Notice that this does not catch the zero_extract variants from
3014 if (GET_CODE (XEXP (x, 0)) == AND
3015 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 0)
3026 if (TARGET_SHMEDIA64)
3027 *total = COSTS_N_INSNS (4);
3028 else if (TARGET_SHMEDIA32)
3029 *total = COSTS_N_INSNS (2);
3036 *total = COSTS_N_INSNS (4);
3037 /* prepare_cmp_insn will force costly constants int registers before
3038 the cbranchdi4 pattern can see them, so preserve potentially
3039 interesting ones. */
3040 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3046 if (x == CONST0_RTX (GET_MODE (x)))
3048 else if (sh_1el_vec (x, VOIDmode))
3049 *total = outer_code != SET;
3050 if (sh_rep_vec (x, VOIDmode))
3051 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3052 + (outer_code != SET));
3053 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3058 *total = COSTS_N_INSNS (addsubcosts (x));
3064 *total = COSTS_N_INSNS (and_xor_ior_costs (x, code));
3068 *total = COSTS_N_INSNS (multcosts (x));
3074 *total = shiftcosts (x);
3081 *total = COSTS_N_INSNS (20);
3085 if (sh_1el_vec (x, VOIDmode))
3086 *total = outer_code != SET;
3087 if (sh_rep_vec (x, VOIDmode))
3088 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3089 + (outer_code != SET));
3090 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3103 /* Compute the cost of an address. For the SH, all valid addresses are
3104 the same cost. Use a slightly higher cost for reg + reg addressing,
3105 since it increases pressure on r0. */
3108 sh_address_cost (rtx X,
3109 bool speed ATTRIBUTE_UNUSED)
3111 return (GET_CODE (X) == PLUS
3112 && ! CONSTANT_P (XEXP (X, 1))
3113 && ! TARGET_SHMEDIA ? 1 : 0);
3116 /* Code to expand a shift. */
3119 gen_ashift (int type, int n, rtx reg)
3121 /* Negative values here come from the shift_amounts array. */
3134 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3138 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3140 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3143 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3148 /* Same for HImode */
3151 gen_ashift_hi (int type, int n, rtx reg)
3153 /* Negative values here come from the shift_amounts array. */
3167 /* We don't have HImode right shift operations because using the
3168 ordinary 32 bit shift instructions for that doesn't generate proper
3169 zero/sign extension.
3170 gen_ashift_hi is only called in contexts where we know that the
3171 sign extension works out correctly. */
3174 if (GET_CODE (reg) == SUBREG)
3176 offset = SUBREG_BYTE (reg);
3177 reg = SUBREG_REG (reg);
3179 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3183 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3188 /* Output RTL to split a constant shift into its component SH constant
3189 shift instructions. */
3192 gen_shifty_op (int code, rtx *operands)
3194 int value = INTVAL (operands[2]);
3197 /* Truncate the shift count in case it is out of bounds. */
3202 if (code == LSHIFTRT)
3204 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3205 emit_insn (gen_movt (operands[0]));
3208 else if (code == ASHIFT)
3210 /* There is a two instruction sequence for 31 bit left shifts,
3211 but it requires r0. */
3212 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3214 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3215 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3220 else if (value == 0)
3222 /* This can happen even when optimizing, if there were subregs before
3223 reload. Don't output a nop here, as this is never optimized away;
3224 use a no-op move instead. */
3225 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3229 max = shift_insns[value];
3230 for (i = 0; i < max; i++)
3231 gen_ashift (code, shift_amounts[value][i], operands[0]);
3234 /* Same as above, but optimized for values where the topmost bits don't
3238 gen_shifty_hi_op (int code, rtx *operands)
3240 int value = INTVAL (operands[2]);
3242 void (*gen_fun) (int, int, rtx);
3244 /* This operation is used by and_shl for SImode values with a few
3245 high bits known to be cleared. */
3249 emit_insn (gen_nop ());
3253 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3256 max = ext_shift_insns[value];
3257 for (i = 0; i < max; i++)
3258 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3261 /* When shifting right, emit the shifts in reverse order, so that
3262 solitary negative values come first. */
3263 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3264 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3267 /* Output RTL for an arithmetic right shift. */
3269 /* ??? Rewrite to use super-optimizer sequences. */
3272 expand_ashiftrt (rtx *operands)
3278 if (TARGET_SH3 || TARGET_SH2A)
3280 if (!CONST_INT_P (operands[2]))
3282 rtx count = copy_to_mode_reg (SImode, operands[2]);
3283 emit_insn (gen_negsi2 (count, count));
3284 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3287 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3288 > 1 + SH_DYNAMIC_SHIFT_COST)
3291 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3292 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3296 if (!CONST_INT_P (operands[2]))
3299 value = INTVAL (operands[2]) & 31;
3303 /* If we are called from abs expansion, arrange things so that we
3304 we can use a single MT instruction that doesn't clobber the source,
3305 if LICM can hoist out the load of the constant zero. */
3306 if (currently_expanding_to_rtl)
3308 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3310 emit_insn (gen_mov_neg_si_t (operands[0]));
3313 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3316 else if (value >= 16 && value <= 19)
3318 wrk = gen_reg_rtx (SImode);
3319 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3322 gen_ashift (ASHIFTRT, 1, wrk);
3323 emit_move_insn (operands[0], wrk);
3326 /* Expand a short sequence inline, longer call a magic routine. */
3327 else if (value <= 5)
3329 wrk = gen_reg_rtx (SImode);
3330 emit_move_insn (wrk, operands[1]);
3332 gen_ashift (ASHIFTRT, 1, wrk);
3333 emit_move_insn (operands[0], wrk);
3337 wrk = gen_reg_rtx (Pmode);
3339 /* Load the value into an arg reg and call a helper. */
3340 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3341 sprintf (func, "__ashiftrt_r4_%d", value);
3342 function_symbol (wrk, func, SFUNC_STATIC);
3343 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3344 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3349 sh_dynamicalize_shift_p (rtx count)
3351 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3354 /* Try to find a good way to implement the combiner pattern
3355 [(set (match_operand:SI 0 "register_operand" "r")
3356 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3357 (match_operand:SI 2 "const_int_operand" "n"))
3358 (match_operand:SI 3 "const_int_operand" "n"))) .
3359 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3360 return 0 for simple right / left or left/right shift combination.
3361 return 1 for a combination of shifts with zero_extend.
3362 return 2 for a combination of shifts with an AND that needs r0.
3363 return 3 for a combination of shifts with an AND that needs an extra
3364 scratch register, when the three highmost bits of the AND mask are clear.
3365 return 4 for a combination of shifts with an AND that needs an extra
3366 scratch register, when any of the three highmost bits of the AND mask
3368 If ATTRP is set, store an initial right shift width in ATTRP[0],
3369 and the instruction length in ATTRP[1] . These values are not valid
3371 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3372 shift_amounts for the last shift value that is to be used before the
3375 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3377 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3378 int left = INTVAL (left_rtx), right;
3380 int cost, best_cost = 10000;
3381 int best_right = 0, best_len = 0;
3385 if (left < 0 || left > 31)
3387 if (CONST_INT_P (mask_rtx))
3388 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3390 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3391 /* Can this be expressed as a right shift / left shift pair? */
3392 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3393 right = exact_log2 (lsb);
3394 mask2 = ~(mask + lsb - 1);
3395 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3396 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3398 best_cost = shift_insns[right] + shift_insns[right + left];
3399 /* mask has no trailing zeroes <==> ! right */
3400 else if (! right && mask2 == ~(lsb2 - 1))
3402 int late_right = exact_log2 (lsb2);
3403 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3405 /* Try to use zero extend. */
3406 if (mask2 == ~(lsb2 - 1))
3410 for (width = 8; width <= 16; width += 8)
3412 /* Can we zero-extend right away? */
3413 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3416 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3417 if (cost < best_cost)
3428 /* ??? Could try to put zero extend into initial right shift,
3429 or even shift a bit left before the right shift. */
3430 /* Determine value of first part of left shift, to get to the
3431 zero extend cut-off point. */
3432 first = width - exact_log2 (lsb2) + right;
3433 if (first >= 0 && right + left - first >= 0)
3435 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3436 + ext_shift_insns[right + left - first];
3437 if (cost < best_cost)
3449 /* Try to use r0 AND pattern */
3450 for (i = 0; i <= 2; i++)
3454 if (! CONST_OK_FOR_K08 (mask >> i))
3456 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3457 if (cost < best_cost)
3462 best_len = cost - 1;
3465 /* Try to use a scratch register to hold the AND operand. */
3466 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3467 for (i = 0; i <= 2; i++)
3471 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3472 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3473 if (cost < best_cost)
3478 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3484 attrp[0] = best_right;
3485 attrp[1] = best_len;
3490 /* This is used in length attributes of the unnamed instructions
3491 corresponding to shl_and_kind return values of 1 and 2. */
3493 shl_and_length (rtx insn)
3495 rtx set_src, left_rtx, mask_rtx;
3498 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3499 left_rtx = XEXP (XEXP (set_src, 0), 1);
3500 mask_rtx = XEXP (set_src, 1);
3501 shl_and_kind (left_rtx, mask_rtx, attributes);
3502 return attributes[1];
3505 /* This is used in length attribute of the and_shl_scratch instruction. */
3508 shl_and_scr_length (rtx insn)
3510 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3511 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3512 rtx op = XEXP (set_src, 0);
3513 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3514 op = XEXP (XEXP (op, 0), 0);
3515 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3518 /* Generate rtl for instructions for which shl_and_kind advised a particular
3519 method of generating them, i.e. returned zero. */
3522 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3525 unsigned HOST_WIDE_INT mask;
3526 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3527 int right, total_shift;
3528 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3530 right = attributes[0];
3531 total_shift = INTVAL (left_rtx) + right;
3532 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3539 int first = attributes[2];
3544 emit_insn ((mask << right) <= 0xff
3545 ? gen_zero_extendqisi2 (dest,
3546 gen_lowpart (QImode, source))
3547 : gen_zero_extendhisi2 (dest,
3548 gen_lowpart (HImode, source)));
3552 emit_insn (gen_movsi (dest, source));
3556 operands[2] = GEN_INT (right);
3557 gen_shifty_hi_op (LSHIFTRT, operands);
3561 operands[2] = GEN_INT (first);
3562 gen_shifty_hi_op (ASHIFT, operands);
3563 total_shift -= first;
3567 emit_insn (mask <= 0xff
3568 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3569 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3570 if (total_shift > 0)
3572 operands[2] = GEN_INT (total_shift);
3573 gen_shifty_hi_op (ASHIFT, operands);
3578 shift_gen_fun = gen_shifty_op;
3580 /* If the topmost bit that matters is set, set the topmost bits
3581 that don't matter. This way, we might be able to get a shorter
3583 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3584 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3586 /* Don't expand fine-grained when combining, because that will
3587 make the pattern fail. */
3588 if (currently_expanding_to_rtl
3589 || reload_in_progress || reload_completed)
3593 /* Cases 3 and 4 should be handled by this split
3594 only while combining */
3595 gcc_assert (kind <= 2);
3598 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3601 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3606 operands[2] = GEN_INT (total_shift);
3607 shift_gen_fun (ASHIFT, operands);
3614 if (kind != 4 && total_shift < 16)
3616 neg = -ext_shift_amounts[total_shift][1];
3618 neg -= ext_shift_amounts[total_shift][2];
3622 emit_insn (gen_and_shl_scratch (dest, source,
3625 GEN_INT (total_shift + neg),
3627 emit_insn (gen_movsi (dest, dest));
3634 /* Try to find a good way to implement the combiner pattern
3635 [(set (match_operand:SI 0 "register_operand" "=r")
3636 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3637 (match_operand:SI 2 "const_int_operand" "n")
3638 (match_operand:SI 3 "const_int_operand" "n")
3640 (clobber (reg:SI T_REG))]
3641 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3642 return 0 for simple left / right shift combination.
3643 return 1 for left shift / 8 bit sign extend / left shift.
3644 return 2 for left shift / 16 bit sign extend / left shift.
3645 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3646 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3647 return 5 for left shift / 16 bit sign extend / right shift
3648 return 6 for < 8 bit sign extend / left shift.
3649 return 7 for < 8 bit sign extend / left shift / single right shift.
3650 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3653 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3655 int left, size, insize, ext;
3656 int cost = 0, best_cost;
3659 left = INTVAL (left_rtx);
3660 size = INTVAL (size_rtx);
3661 insize = size - left;
3662 gcc_assert (insize > 0);
3663 /* Default to left / right shift. */
3665 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3668 /* 16 bit shift / sign extend / 16 bit shift */
3669 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3670 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3671 below, by alternative 3 or something even better. */
3672 if (cost < best_cost)
3678 /* Try a plain sign extend between two shifts. */
3679 for (ext = 16; ext >= insize; ext -= 8)
3683 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3684 if (cost < best_cost)
3686 kind = ext / (unsigned) 8;
3690 /* Check if we can do a sloppy shift with a final signed shift
3691 restoring the sign. */
3692 if (EXT_SHIFT_SIGNED (size - ext))
3693 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3694 /* If not, maybe it's still cheaper to do the second shift sloppy,
3695 and do a final sign extend? */
3696 else if (size <= 16)
3697 cost = ext_shift_insns[ext - insize] + 1
3698 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3701 if (cost < best_cost)
3703 kind = ext / (unsigned) 8 + 2;
3707 /* Check if we can sign extend in r0 */
3710 cost = 3 + shift_insns[left];
3711 if (cost < best_cost)
3716 /* Try the same with a final signed shift. */
3719 cost = 3 + ext_shift_insns[left + 1] + 1;
3720 if (cost < best_cost)
3727 if (TARGET_SH3 || TARGET_SH2A)
3729 /* Try to use a dynamic shift. */
3730 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3731 if (cost < best_cost)
3742 /* Function to be used in the length attribute of the instructions
3743 implementing this pattern. */
3746 shl_sext_length (rtx insn)
3748 rtx set_src, left_rtx, size_rtx;
3751 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3752 left_rtx = XEXP (XEXP (set_src, 0), 1);
3753 size_rtx = XEXP (set_src, 1);
3754 shl_sext_kind (left_rtx, size_rtx, &cost);
3758 /* Generate rtl for this pattern */
3761 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3764 int left, size, insize, cost;
3767 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3768 left = INTVAL (left_rtx);
3769 size = INTVAL (size_rtx);
3770 insize = size - left;
3778 int ext = kind & 1 ? 8 : 16;
3779 int shift2 = size - ext;
3781 /* Don't expand fine-grained when combining, because that will
3782 make the pattern fail. */
3783 if (! currently_expanding_to_rtl
3784 && ! reload_in_progress && ! reload_completed)
3786 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3787 emit_insn (gen_movsi (dest, source));
3791 emit_insn (gen_movsi (dest, source));
3795 operands[2] = GEN_INT (ext - insize);
3796 gen_shifty_hi_op (ASHIFT, operands);
3799 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3800 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3805 operands[2] = GEN_INT (shift2);
3806 gen_shifty_op (ASHIFT, operands);
3813 if (EXT_SHIFT_SIGNED (shift2))
3815 operands[2] = GEN_INT (shift2 + 1);
3816 gen_shifty_op (ASHIFT, operands);
3817 operands[2] = const1_rtx;
3818 gen_shifty_op (ASHIFTRT, operands);
3821 operands[2] = GEN_INT (shift2);
3822 gen_shifty_hi_op (ASHIFT, operands);
3826 operands[2] = GEN_INT (-shift2);
3827 gen_shifty_hi_op (LSHIFTRT, operands);
3829 emit_insn (size <= 8
3830 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3831 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3838 if (! currently_expanding_to_rtl
3839 && ! reload_in_progress && ! reload_completed)
3840 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3844 operands[2] = GEN_INT (16 - insize);
3845 gen_shifty_hi_op (ASHIFT, operands);
3846 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3848 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3850 gen_ashift (ASHIFTRT, 1, dest);
3855 /* Don't expand fine-grained when combining, because that will
3856 make the pattern fail. */
3857 if (! currently_expanding_to_rtl
3858 && ! reload_in_progress && ! reload_completed)
3860 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3861 emit_insn (gen_movsi (dest, source));
3864 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3865 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3866 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3868 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3869 gen_shifty_op (ASHIFT, operands);
3871 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3879 /* Prefix a symbol_ref name with "datalabel". */
3882 gen_datalabel_ref (rtx sym)
3886 if (GET_CODE (sym) == LABEL_REF)
3887 return gen_rtx_CONST (GET_MODE (sym),
3888 gen_rtx_UNSPEC (GET_MODE (sym),
3892 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3894 str = XSTR (sym, 0);
3895 /* Share all SYMBOL_REF strings with the same value - that is important
3897 str = IDENTIFIER_POINTER (get_identifier (str));
3898 XSTR (sym, 0) = str;
3904 static alloc_pool label_ref_list_pool;
3906 typedef struct label_ref_list_d
3909 struct label_ref_list_d *next;
3910 } *label_ref_list_t;
3912 /* The SH cannot load a large constant into a register, constants have to
3913 come from a pc relative load. The reference of a pc relative load
3914 instruction must be less than 1k in front of the instruction. This
3915 means that we often have to dump a constant inside a function, and
3916 generate code to branch around it.
3918 It is important to minimize this, since the branches will slow things
3919 down and make things bigger.
3921 Worst case code looks like:
3939 We fix this by performing a scan before scheduling, which notices which
3940 instructions need to have their operands fetched from the constant table
3941 and builds the table.
3945 scan, find an instruction which needs a pcrel move. Look forward, find the
3946 last barrier which is within MAX_COUNT bytes of the requirement.
3947 If there isn't one, make one. Process all the instructions between
3948 the find and the barrier.
3950 In the above example, we can tell that L3 is within 1k of L1, so
3951 the first move can be shrunk from the 3 insn+constant sequence into
3952 just 1 insn, and the constant moved to L3 to make:
3963 Then the second move becomes the target for the shortening process. */
3967 rtx value; /* Value in table. */
3968 rtx label; /* Label of value. */
3969 label_ref_list_t wend; /* End of window. */
3970 enum machine_mode mode; /* Mode of value. */
3972 /* True if this constant is accessed as part of a post-increment
3973 sequence. Note that HImode constants are never accessed in this way. */
3974 bool part_of_sequence_p;
3977 /* The maximum number of constants that can fit into one pool, since
3978 constants in the range 0..510 are at least 2 bytes long, and in the
3979 range from there to 1018 at least 4 bytes. */
3981 #define MAX_POOL_SIZE 372
3982 static pool_node pool_vector[MAX_POOL_SIZE];
3983 static int pool_size;
3984 static rtx pool_window_label;
3985 static int pool_window_last;
3987 static int max_labelno_before_reorg;
3989 /* ??? If we need a constant in HImode which is the truncated value of a
3990 constant we need in SImode, we could combine the two entries thus saving
3991 two bytes. Is this common enough to be worth the effort of implementing
3994 /* ??? This stuff should be done at the same time that we shorten branches.
3995 As it is now, we must assume that all branches are the maximum size, and
3996 this causes us to almost always output constant pools sooner than
3999 /* Add a constant to the pool and return its label. */
4002 add_constant (rtx x, enum machine_mode mode, rtx last_value)
4006 label_ref_list_t ref, newref;
4008 /* First see if we've already got it. */
4009 for (i = 0; i < pool_size; i++)
4011 if (x->code == pool_vector[i].value->code
4012 && mode == pool_vector[i].mode)
4014 if (x->code == CODE_LABEL)
4016 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4019 if (rtx_equal_p (x, pool_vector[i].value))
4024 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4026 new_rtx = gen_label_rtx ();
4027 LABEL_REFS (new_rtx) = pool_vector[i].label;
4028 pool_vector[i].label = lab = new_rtx;
4030 if (lab && pool_window_label)
4032 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4033 newref->label = pool_window_label;
4034 ref = pool_vector[pool_window_last].wend;
4036 pool_vector[pool_window_last].wend = newref;
4039 pool_window_label = new_rtx;
4040 pool_window_last = i;
4046 /* Need a new one. */
4047 pool_vector[pool_size].value = x;
4048 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4051 pool_vector[pool_size - 1].part_of_sequence_p = true;
4054 lab = gen_label_rtx ();
4055 pool_vector[pool_size].mode = mode;
4056 pool_vector[pool_size].label = lab;
4057 pool_vector[pool_size].wend = NULL;
4058 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4059 if (lab && pool_window_label)
4061 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4062 newref->label = pool_window_label;
4063 ref = pool_vector[pool_window_last].wend;
4065 pool_vector[pool_window_last].wend = newref;
4068 pool_window_label = lab;
4069 pool_window_last = pool_size;
4074 /* Output the literal table. START, if nonzero, is the first instruction
4075 this table is needed for, and also indicates that there is at least one
4076 casesi_worker_2 instruction; We have to emit the operand3 labels from
4077 these insns at a 4-byte aligned position. BARRIER is the barrier
4078 after which we are to place the table. */
4081 dump_table (rtx start, rtx barrier)
4087 label_ref_list_t ref;
4090 /* Do two passes, first time dump out the HI sized constants. */
4092 for (i = 0; i < pool_size; i++)
4094 pool_node *p = &pool_vector[i];
4096 if (p->mode == HImode)
4100 scan = emit_insn_after (gen_align_2 (), scan);
4103 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4104 scan = emit_label_after (lab, scan);
4105 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4107 for (ref = p->wend; ref; ref = ref->next)
4110 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4113 else if (p->mode == DFmode)
4121 scan = emit_insn_after (gen_align_4 (), scan);
4123 for (; start != barrier; start = NEXT_INSN (start))
4124 if (NONJUMP_INSN_P (start)
4125 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4127 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4128 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4130 scan = emit_label_after (lab, scan);
4133 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4135 rtx align_insn = NULL_RTX;
4137 scan = emit_label_after (gen_label_rtx (), scan);
4138 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4141 for (i = 0; i < pool_size; i++)
4143 pool_node *p = &pool_vector[i];
4151 if (align_insn && !p->part_of_sequence_p)
4153 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4154 emit_label_before (lab, align_insn);
4155 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4157 for (ref = p->wend; ref; ref = ref->next)
4160 emit_insn_before (gen_consttable_window_end (lab),
4163 delete_insn (align_insn);
4164 align_insn = NULL_RTX;
4169 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4170 scan = emit_label_after (lab, scan);
4171 scan = emit_insn_after (gen_consttable_4 (p->value,
4173 need_align = ! need_align;
4179 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4184 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4185 scan = emit_label_after (lab, scan);
4186 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4193 if (p->mode != HImode)
4195 for (ref = p->wend; ref; ref = ref->next)
4198 scan = emit_insn_after (gen_consttable_window_end (lab),
4207 for (i = 0; i < pool_size; i++)
4209 pool_node *p = &pool_vector[i];
4220 scan = emit_label_after (gen_label_rtx (), scan);
4221 scan = emit_insn_after (gen_align_4 (), scan);
4223 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4224 scan = emit_label_after (lab, scan);
4225 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4233 scan = emit_label_after (gen_label_rtx (), scan);
4234 scan = emit_insn_after (gen_align_4 (), scan);
4236 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4237 scan = emit_label_after (lab, scan);
4238 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4245 if (p->mode != HImode)
4247 for (ref = p->wend; ref; ref = ref->next)
4250 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4255 scan = emit_insn_after (gen_consttable_end (), scan);
4256 scan = emit_barrier_after (scan);
4258 pool_window_label = NULL_RTX;
4259 pool_window_last = 0;
4262 /* Return nonzero if constant would be an ok source for a
4263 mov.w instead of a mov.l. */
4268 return (CONST_INT_P (src)
4269 && INTVAL (src) >= -32768
4270 && INTVAL (src) <= 32767);
4273 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4275 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4277 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4278 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4279 need to fix it if the input value is CONST_OK_FOR_I08. */
4282 broken_move (rtx insn)
4284 if (NONJUMP_INSN_P (insn))
4286 rtx pat = PATTERN (insn);
4287 if (GET_CODE (pat) == PARALLEL)
4288 pat = XVECEXP (pat, 0, 0);
4289 if (GET_CODE (pat) == SET
4290 /* We can load any 8-bit value if we don't care what the high
4291 order bits end up as. */
4292 && GET_MODE (SET_DEST (pat)) != QImode
4293 && (CONSTANT_P (SET_SRC (pat))
4294 /* Match mova_const. */
4295 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4296 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4297 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4299 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4300 && (fp_zero_operand (SET_SRC (pat))
4301 || fp_one_operand (SET_SRC (pat)))
4302 /* In general we don't know the current setting of fpscr, so disable fldi.
4303 There is an exception if this was a register-register move
4304 before reload - and hence it was ascertained that we have
4305 single precision setting - and in a post-reload optimization
4306 we changed this to do a constant load. In that case
4307 we don't have an r0 clobber, hence we must use fldi. */
4309 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4311 && REG_P (SET_DEST (pat))
4312 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4314 && GET_MODE (SET_DEST (pat)) == SImode
4315 && (satisfies_constraint_I20 (SET_SRC (pat))
4316 || satisfies_constraint_I28 (SET_SRC (pat))))
4317 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4327 return (NONJUMP_INSN_P (insn)
4328 && GET_CODE (PATTERN (insn)) == SET
4329 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4330 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4331 /* Don't match mova_const. */
4332 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4335 /* Fix up a mova from a switch that went out of range. */
4337 fixup_mova (rtx mova)
4339 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4342 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4343 INSN_CODE (mova) = -1;
4348 rtx lab = gen_label_rtx ();
4349 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4353 worker = NEXT_INSN (worker);
4355 && !LABEL_P (worker)
4356 && !JUMP_P (worker));
4357 } while (NOTE_P (worker)
4358 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4359 wpat = PATTERN (worker);
4360 wpat0 = XVECEXP (wpat, 0, 0);
4361 wpat1 = XVECEXP (wpat, 0, 1);
4362 wsrc = SET_SRC (wpat0);
4363 PATTERN (worker) = (gen_casesi_worker_2
4364 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4365 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4367 INSN_CODE (worker) = -1;
4368 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4369 base = gen_rtx_LABEL_REF (Pmode, lab);
4370 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4371 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4372 INSN_CODE (mova) = -1;
4376 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4377 *num_mova, and check if the new mova is not nested within the first one.
4378 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4379 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4381 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4383 int n_addr = 0; /* Initialization to shut up spurious warning. */
4384 int f_target, n_target = 0; /* Likewise. */
4388 /* If NEW_MOVA has no address yet, it will be handled later. */
4389 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4392 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4393 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4394 if (n_addr > n_target || n_addr + 1022 < n_target)
4396 /* Change the mova into a load.
4397 broken_move will then return true for it. */
4398 fixup_mova (new_mova);
4404 *first_mova = new_mova;
4409 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4414 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4415 > n_target - n_addr)
4417 fixup_mova (*first_mova);
4422 fixup_mova (new_mova);
4427 /* Find the last barrier from insn FROM which is close enough to hold the
4428 constant pool. If we can't find one, then create one near the end of
4432 find_barrier (int num_mova, rtx mova, rtx from)
4441 int leading_mova = num_mova;
4442 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4446 rtx last_got = NULL_RTX;
4447 rtx last_symoff = NULL_RTX;
4449 /* For HImode: range is 510, add 4 because pc counts from address of
4450 second instruction after this one, subtract 2 for the jump instruction
4451 that we may need to emit before the table, subtract 2 for the instruction
4452 that fills the jump delay slot (in very rare cases, reorg will take an
4453 instruction from after the constant pool or will leave the delay slot
4454 empty). This gives 510.
4455 For SImode: range is 1020, add 4 because pc counts from address of
4456 second instruction after this one, subtract 2 in case pc is 2 byte
4457 aligned, subtract 2 for the jump instruction that we may need to emit
4458 before the table, subtract 2 for the instruction that fills the jump
4459 delay slot. This gives 1018. */
4461 /* The branch will always be shortened now that the reference address for
4462 forward branches is the successor address, thus we need no longer make
4463 adjustments to the [sh]i_limit for -O0. */
4468 while (from && count_si < si_limit && count_hi < hi_limit)
4470 int inc = get_attr_length (from);
4473 /* If this is a label that existed at the time of the compute_alignments
4474 call, determine the alignment. N.B. When find_barrier recurses for
4475 an out-of-reach mova, we might see labels at the start of previously
4476 inserted constant tables. */
4478 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4481 new_align = 1 << label_to_alignment (from);
4482 else if (BARRIER_P (prev_nonnote_insn (from)))
4483 new_align = 1 << barrier_align (from);
4488 /* In case we are scanning a constant table because of recursion, check
4489 for explicit alignments. If the table is long, we might be forced
4490 to emit the new table in front of it; the length of the alignment
4491 might be the last straw. */
4492 else if (NONJUMP_INSN_P (from)
4493 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4494 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4495 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4496 /* When we find the end of a constant table, paste the new constant
4497 at the end. That is better than putting it in front because
4498 this way, we don't need extra alignment for adding a 4-byte-aligned
4499 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4500 else if (NONJUMP_INSN_P (from)
4501 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4502 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4505 if (BARRIER_P (from))
4509 found_barrier = from;
4511 /* If we are at the end of the function, or in front of an alignment
4512 instruction, we need not insert an extra alignment. We prefer
4513 this kind of barrier. */
4514 if (barrier_align (from) > 2)
4515 good_barrier = from;
4517 /* If we are at the end of a hot/cold block, dump the constants
4519 next = NEXT_INSN (from);
4522 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4526 if (broken_move (from))
4529 enum machine_mode mode;
4531 pat = PATTERN (from);
4532 if (GET_CODE (pat) == PARALLEL)
4533 pat = XVECEXP (pat, 0, 0);
4534 src = SET_SRC (pat);
4535 dst = SET_DEST (pat);
4536 mode = GET_MODE (dst);
4538 /* GOT pcrelat setting comes in pair of
4541 instructions. (plus add r0,r12).
4542 Remember if we see one without the other. */
4543 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4544 last_got = last_got ? NULL_RTX : from;
4545 else if (PIC_ADDR_P (src))
4546 last_got = last_got ? NULL_RTX : from;
4548 /* We must explicitly check the mode, because sometimes the
4549 front end will generate code to load unsigned constants into
4550 HImode targets without properly sign extending them. */
4552 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4555 /* We put the short constants before the long constants, so
4556 we must count the length of short constants in the range
4557 for the long constants. */
4558 /* ??? This isn't optimal, but is easy to do. */
4563 /* We dump DF/DI constants before SF/SI ones, because
4564 the limit is the same, but the alignment requirements
4565 are higher. We may waste up to 4 additional bytes
4566 for alignment, and the DF/DI constant may have
4567 another SF/SI constant placed before it. */
4568 if (TARGET_SHCOMPACT
4570 && (mode == DFmode || mode == DImode))
4575 while (si_align > 2 && found_si + si_align - 2 > count_si)
4577 if (found_si > count_si)
4578 count_si = found_si;
4579 found_si += GET_MODE_SIZE (mode);
4581 si_limit -= GET_MODE_SIZE (mode);
4587 switch (untangle_mova (&num_mova, &mova, from))
4592 rtx src = SET_SRC (PATTERN (from));
4593 if (GET_CODE (src) == CONST
4594 && GET_CODE (XEXP (src, 0)) == UNSPEC
4595 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4599 case 0: return find_barrier (0, 0, mova);
4604 = good_barrier ? good_barrier : found_barrier;
4608 if (found_si > count_si)
4609 count_si = found_si;
4611 else if (JUMP_TABLE_DATA_P (from))
4613 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4615 && (prev_nonnote_insn (from)
4616 == XEXP (MOVA_LABELREF (mova), 0))))
4618 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4620 /* We have just passed the barrier in front of the
4621 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4622 the ADDR_DIFF_VEC is accessed as data, just like our pool
4623 constants, this is a good opportunity to accommodate what
4624 we have gathered so far.
4625 If we waited any longer, we could end up at a barrier in
4626 front of code, which gives worse cache usage for separated
4627 instruction / data caches. */
4628 good_barrier = found_barrier;
4633 rtx body = PATTERN (from);
4634 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4637 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4638 else if (JUMP_P (from)
4643 /* There is a possibility that a bf is transformed into a bf/s by the
4644 delay slot scheduler. */
4645 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4646 && get_attr_type (from) == TYPE_CBRANCH
4647 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4653 if (new_align > si_align)
4655 si_limit -= (count_si - 1) & (new_align - si_align);
4656 si_align = new_align;
4658 count_si = (count_si + new_align - 1) & -new_align;
4663 if (new_align > hi_align)
4665 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4666 hi_align = new_align;
4668 count_hi = (count_hi + new_align - 1) & -new_align;
4670 from = NEXT_INSN (from);
4677 /* Try as we might, the leading mova is out of range. Change
4678 it into a load (which will become a pcload) and retry. */
4680 return find_barrier (0, 0, mova);
4684 /* Insert the constant pool table before the mova instruction,
4685 to prevent the mova label reference from going out of range. */
4687 good_barrier = found_barrier = barrier_before_mova;
4693 if (good_barrier && next_real_insn (found_barrier))
4694 found_barrier = good_barrier;
4698 /* We didn't find a barrier in time to dump our stuff,
4699 so we'll make one. */
4700 rtx label = gen_label_rtx ();
4702 /* Don't emit a constant table in the middle of insns for
4703 casesi_worker_2. This is a bit overkill but is enough
4704 because casesi_worker_2 wouldn't appear so frequently. */
4708 /* If we exceeded the range, then we must back up over the last
4709 instruction we looked at. Otherwise, we just need to undo the
4710 NEXT_INSN at the end of the loop. */
4711 if (PREV_INSN (from) != orig
4712 && (count_hi > hi_limit || count_si > si_limit))
4713 from = PREV_INSN (PREV_INSN (from));
4715 from = PREV_INSN (from);
4717 /* Don't emit a constant table int the middle of global pointer setting,
4718 since that that would move the addressing base GOT into another table.
4719 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4720 in the pool anyway, so just move up the whole constant pool.
4721 However, avoid doing so when the last single GOT mov is the starting
4722 insn itself. Going past above the start insn would create a negative
4723 offset, causing errors. */
4724 if (last_got && last_got != orig)
4725 from = PREV_INSN (last_got);
4727 /* Don't insert the constant pool table at the position which
4728 may be the landing pad. */
4731 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4732 from = PREV_INSN (from);
4734 /* Walk back to be just before any jump or label.
4735 Putting it before a label reduces the number of times the branch
4736 around the constant pool table will be hit. Putting it before
4737 a jump makes it more likely that the bra delay slot will be
4739 while (NOTE_P (from) || JUMP_P (from)
4741 from = PREV_INSN (from);
4743 /* Make sure we do not split between a call and its corresponding
4744 CALL_ARG_LOCATION note. */
4747 rtx next = NEXT_INSN (from);
4748 if (next && NOTE_P (next)
4749 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
4753 from = emit_jump_insn_after (gen_jump (label), from);
4754 JUMP_LABEL (from) = label;
4755 LABEL_NUSES (label) = 1;
4756 found_barrier = emit_barrier_after (from);
4757 emit_label_after (label, found_barrier);
4760 return found_barrier;
4763 /* If the instruction INSN is implemented by a special function, and we can
4764 positively find the register that is used to call the sfunc, and this
4765 register is not used anywhere else in this instruction - except as the
4766 destination of a set, return this register; else, return 0. */
4768 sfunc_uses_reg (rtx insn)
4771 rtx pattern, part, reg_part, reg;
4773 if (!NONJUMP_INSN_P (insn))
4775 pattern = PATTERN (insn);
4776 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4779 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4781 part = XVECEXP (pattern, 0, i);
4782 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4787 reg = XEXP (reg_part, 0);
4788 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4790 part = XVECEXP (pattern, 0, i);
4791 if (part == reg_part || GET_CODE (part) == CLOBBER)
4793 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4794 && REG_P (SET_DEST (part)))
4795 ? SET_SRC (part) : part)))
4801 /* See if the only way in which INSN uses REG is by calling it, or by
4802 setting it while calling it. Set *SET to a SET rtx if the register
4806 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4812 reg2 = sfunc_uses_reg (insn);
4813 if (reg2 && REGNO (reg2) == REGNO (reg))
4815 pattern = single_set (insn);
4817 && REG_P (SET_DEST (pattern))
4818 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4824 /* We don't use rtx_equal_p because we don't care if the mode is
4826 pattern = single_set (insn);
4828 && REG_P (SET_DEST (pattern))
4829 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4835 par = PATTERN (insn);
4836 if (GET_CODE (par) == PARALLEL)
4837 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4839 part = XVECEXP (par, 0, i);
4840 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4843 return reg_mentioned_p (reg, SET_SRC (pattern));
4849 pattern = PATTERN (insn);
4851 if (GET_CODE (pattern) == PARALLEL)
4855 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4856 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4858 pattern = XVECEXP (pattern, 0, 0);
4861 if (GET_CODE (pattern) == SET)
4863 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4865 /* We don't use rtx_equal_p, because we don't care if the
4866 mode is different. */
4867 if (!REG_P (SET_DEST (pattern))
4868 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4874 pattern = SET_SRC (pattern);
4877 if (GET_CODE (pattern) != CALL
4878 || !MEM_P (XEXP (pattern, 0))
4879 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4885 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4886 general registers. Bits 0..15 mean that the respective registers
4887 are used as inputs in the instruction. Bits 16..31 mean that the
4888 registers 0..15, respectively, are used as outputs, or are clobbered.
4889 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4891 regs_used (rtx x, int is_dest)
4899 code = GET_CODE (x);
4904 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4905 << (REGNO (x) + is_dest));
4909 rtx y = SUBREG_REG (x);
4914 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4916 subreg_regno_offset (REGNO (y),
4919 GET_MODE (x)) + is_dest));
4923 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4925 /* If there was a return value, it must have been indicated with USE. */
4940 fmt = GET_RTX_FORMAT (code);
4942 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4947 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4948 used |= regs_used (XVECEXP (x, i, j), is_dest);
4950 else if (fmt[i] == 'e')
4951 used |= regs_used (XEXP (x, i), is_dest);
4956 /* Create an instruction that prevents redirection of a conditional branch
4957 to the destination of the JUMP with address ADDR.
4958 If the branch needs to be implemented as an indirect jump, try to find
4959 a scratch register for it.
4960 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4961 If any preceding insn that doesn't fit into a delay slot is good enough,
4962 pass 1. Pass 2 if a definite blocking insn is needed.
4963 -1 is used internally to avoid deep recursion.
4964 If a blocking instruction is made or recognized, return it. */
4967 gen_block_redirect (rtx jump, int addr, int need_block)
4970 rtx prev = prev_nonnote_insn (jump);
4973 /* First, check if we already have an instruction that satisfies our need. */
4974 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4976 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4978 if (GET_CODE (PATTERN (prev)) == USE
4979 || GET_CODE (PATTERN (prev)) == CLOBBER
4980 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4982 else if ((need_block &= ~1) < 0)
4984 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4987 if (GET_CODE (PATTERN (jump)) == RETURN)
4991 /* Reorg even does nasty things with return insns that cause branches
4992 to go out of range - see find_end_label and callers. */
4993 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4995 /* We can't use JUMP_LABEL here because it might be undefined
4996 when not optimizing. */
4997 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4998 /* If the branch is out of range, try to find a scratch register for it. */
5000 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5004 /* Don't look for the stack pointer as a scratch register,
5005 it would cause trouble if an interrupt occurred. */
5006 unsigned attempt = 0x7fff, used;
5007 int jump_left = flag_expensive_optimizations + 1;
5009 /* It is likely that the most recent eligible instruction is wanted for
5010 the delay slot. Therefore, find out which registers it uses, and
5011 try to avoid using them. */
5013 for (scan = jump; (scan = PREV_INSN (scan)); )
5017 if (INSN_DELETED_P (scan))
5019 code = GET_CODE (scan);
5020 if (code == CODE_LABEL || code == JUMP_INSN)
5023 && GET_CODE (PATTERN (scan)) != USE
5024 && GET_CODE (PATTERN (scan)) != CLOBBER
5025 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5027 attempt &= ~regs_used (PATTERN (scan), 0);
5031 for (used = dead = 0, scan = JUMP_LABEL (jump);
5032 (scan = NEXT_INSN (scan)); )
5036 if (INSN_DELETED_P (scan))
5038 code = GET_CODE (scan);
5041 used |= regs_used (PATTERN (scan), 0);
5042 if (code == CALL_INSN)
5043 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5044 dead |= (used >> 16) & ~used;
5050 if (code == JUMP_INSN)
5052 if (jump_left-- && simplejump_p (scan))
5053 scan = JUMP_LABEL (scan);
5059 /* Mask out the stack pointer again, in case it was
5060 the only 'free' register we have found. */
5063 /* If the immediate destination is still in range, check for possible
5064 threading with a jump beyond the delay slot insn.
5065 Don't check if we are called recursively; the jump has been or will be
5066 checked in a different invocation then. */
5068 else if (optimize && need_block >= 0)
5070 rtx next = next_active_insn (next_active_insn (dest));
5071 if (next && JUMP_P (next)
5072 && GET_CODE (PATTERN (next)) == SET
5073 && recog_memoized (next) == CODE_FOR_jump_compact)
5075 dest = JUMP_LABEL (next);
5077 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5079 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5085 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5087 /* It would be nice if we could convert the jump into an indirect
5088 jump / far branch right now, and thus exposing all constituent
5089 instructions to further optimization. However, reorg uses
5090 simplejump_p to determine if there is an unconditional jump where
5091 it should try to schedule instructions from the target of the
5092 branch; simplejump_p fails for indirect jumps even if they have
5094 rtx insn = emit_insn_before (gen_indirect_jump_scratch
5095 (reg, GEN_INT (unspec_bbr_uid++)),
5097 /* ??? We would like this to have the scope of the jump, but that
5098 scope will change when a delay slot insn of an inner scope is added.
5099 Hence, after delay slot scheduling, we'll have to expect
5100 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5103 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
5104 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5107 else if (need_block)
5108 /* We can't use JUMP_LABEL here because it might be undefined
5109 when not optimizing. */
5110 return emit_insn_before (gen_block_branch_redirect
5111 (GEN_INT (unspec_bbr_uid++)),
5116 #define CONDJUMP_MIN -252
5117 #define CONDJUMP_MAX 262
5120 /* A label (to be placed) in front of the jump
5121 that jumps to our ultimate destination. */
5123 /* Where we are going to insert it if we cannot move the jump any farther,
5124 or the jump itself if we have picked up an existing jump. */
5126 /* The ultimate destination. */
5128 struct far_branch *prev;
5129 /* If the branch has already been created, its address;
5130 else the address of its first prospective user. */
5134 static void gen_far_branch (struct far_branch *);
5135 enum mdep_reorg_phase_e mdep_reorg_phase;
5137 gen_far_branch (struct far_branch *bp)
5139 rtx insn = bp->insert_place;
5141 rtx label = gen_label_rtx ();
5144 emit_label_after (label, insn);
5147 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5148 LABEL_NUSES (bp->far_label)++;
5151 jump = emit_jump_insn_after (gen_return (), insn);
5153 /* Emit a barrier so that reorg knows that any following instructions
5154 are not reachable via a fall-through path.
5155 But don't do this when not optimizing, since we wouldn't suppress the
5156 alignment for the barrier then, and could end up with out-of-range
5157 pc-relative loads. */
5159 emit_barrier_after (jump);
5160 emit_label_after (bp->near_label, insn);
5163 JUMP_LABEL (jump) = bp->far_label;
5166 rtx pat = PATTERN (jump);
5167 gcc_assert (ANY_RETURN_P (pat));
5168 JUMP_LABEL (jump) = pat;
5171 ok = invert_jump (insn, label, 1);
5174 /* If we are branching around a jump (rather than a return), prevent
5175 reorg from using an insn from the jump target as the delay slot insn -
5176 when reorg did this, it pessimized code (we rather hide the delay slot)
5177 and it could cause branches to go out of range. */
5180 (gen_stuff_delay_slot
5181 (GEN_INT (unspec_bbr_uid++),
5182 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5184 /* Prevent reorg from undoing our splits. */
5185 gen_block_redirect (jump, bp->address += 2, 2);
5188 /* Fix up ADDR_DIFF_VECs. */
5190 fixup_addr_diff_vecs (rtx first)
5194 for (insn = first; insn; insn = NEXT_INSN (insn))
5196 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5199 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5201 pat = PATTERN (insn);
5202 vec_lab = XEXP (XEXP (pat, 0), 0);
5204 /* Search the matching casesi_jump_2. */
5205 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5209 prevpat = PATTERN (prev);
5210 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5212 x = XVECEXP (prevpat, 0, 1);
5213 if (GET_CODE (x) != USE)
5216 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5219 /* FIXME: This is a bug in the optimizer, but it seems harmless
5220 to just avoid panicing. */
5224 /* Emit the reference label of the braf where it belongs, right after
5225 the casesi_jump_2 (i.e. braf). */
5226 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5227 emit_label_after (braf_label, prev);
5229 /* Fix up the ADDR_DIF_VEC to be relative
5230 to the reference address of the braf. */
5231 XEXP (XEXP (pat, 0), 0) = braf_label;
5235 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5236 a barrier. Return the base 2 logarithm of the desired alignment. */
5238 barrier_align (rtx barrier_or_label)
5240 rtx next = next_real_insn (barrier_or_label), pat, prev;
5241 int slot, credit, jump_to_next = 0;
5246 pat = PATTERN (next);
5248 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5251 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5252 /* This is a barrier in front of a constant table. */
5255 prev = prev_real_insn (barrier_or_label);
5256 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5258 pat = PATTERN (prev);
5259 /* If this is a very small table, we want to keep the alignment after
5260 the table to the minimum for proper code alignment. */
5261 return ((optimize_size
5262 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5263 <= (unsigned) 1 << (CACHE_LOG - 2)))
5264 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5270 if (! TARGET_SH2 || ! optimize)
5271 return align_jumps_log;
5273 /* When fixing up pcloads, a constant table might be inserted just before
5274 the basic block that ends with the barrier. Thus, we can't trust the
5275 instruction lengths before that. */
5276 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5278 /* Check if there is an immediately preceding branch to the insn beyond
5279 the barrier. We must weight the cost of discarding useful information
5280 from the current cache line when executing this branch and there is
5281 an alignment, against that of fetching unneeded insn in front of the
5282 branch target when there is no alignment. */
5284 /* There are two delay_slot cases to consider. One is the simple case
5285 where the preceding branch is to the insn beyond the barrier (simple
5286 delay slot filling), and the other is where the preceding branch has
5287 a delay slot that is a duplicate of the insn after the barrier
5288 (fill_eager_delay_slots) and the branch is to the insn after the insn
5289 after the barrier. */
5291 /* PREV is presumed to be the JUMP_INSN for the barrier under
5292 investigation. Skip to the insn before it. */
5293 prev = prev_real_insn (prev);
5295 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5296 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5297 prev = prev_real_insn (prev))
5300 if (GET_CODE (PATTERN (prev)) == USE
5301 || GET_CODE (PATTERN (prev)) == CLOBBER)
5303 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5305 prev = XVECEXP (PATTERN (prev), 0, 1);
5306 if (INSN_UID (prev) == INSN_UID (next))
5308 /* Delay slot was filled with insn at jump target. */
5315 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5317 credit -= get_attr_length (prev);
5319 if (prev && jump_to_label_p (prev))
5323 || next_real_insn (JUMP_LABEL (prev)) == next
5324 /* If relax_delay_slots() decides NEXT was redundant
5325 with some previous instruction, it will have
5326 redirected PREV's jump to the following insn. */
5327 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5328 /* There is no upper bound on redundant instructions
5329 that might have been skipped, but we must not put an
5330 alignment where none had been before. */
5331 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5333 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5334 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5335 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5337 rtx pat = PATTERN (prev);
5338 if (GET_CODE (pat) == PARALLEL)
5339 pat = XVECEXP (pat, 0, 0);
5340 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5346 return align_jumps_log;
5349 /* If we are inside a phony loop, almost any kind of label can turn up as the
5350 first one in the loop. Aligning a braf label causes incorrect switch
5351 destination addresses; we can detect braf labels because they are
5352 followed by a BARRIER.
5353 Applying loop alignment to small constant or switch tables is a waste
5354 of space, so we suppress this too. */
5356 sh_loop_align (rtx label)
5361 next = next_nonnote_insn (next);
5362 while (next && LABEL_P (next));
5366 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5367 || recog_memoized (next) == CODE_FOR_consttable_2)
5370 return align_loops_log;
5373 /* Do a final pass over the function, just before delayed branch
5379 rtx first, insn, mova = NULL_RTX;
5381 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5382 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5384 first = get_insns ();
5385 max_labelno_before_reorg = max_label_num ();
5387 /* We must split call insns before introducing `mova's. If we're
5388 optimizing, they'll have already been split. Otherwise, make
5389 sure we don't split them too late. */
5391 split_all_insns_noflow ();
5396 /* If relaxing, generate pseudo-ops to associate function calls with
5397 the symbols they call. It does no harm to not generate these
5398 pseudo-ops. However, when we can generate them, it enables the
5399 linker to potentially relax the jsr to a bsr, and eliminate the
5400 register load and, possibly, the constant pool entry. */
5402 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5405 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5406 own purposes. This works because none of the remaining passes
5407 need to look at them.
5409 ??? But it may break in the future. We should use a machine
5410 dependent REG_NOTE, or some other approach entirely. */
5411 for (insn = first; insn; insn = NEXT_INSN (insn))
5417 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5419 remove_note (insn, note);
5423 for (insn = first; insn; insn = NEXT_INSN (insn))
5425 rtx pattern, reg, link, set, scan, dies, label;
5426 int rescan = 0, foundinsn = 0;
5430 pattern = PATTERN (insn);
5432 if (GET_CODE (pattern) == PARALLEL)
5433 pattern = XVECEXP (pattern, 0, 0);
5434 if (GET_CODE (pattern) == SET)
5435 pattern = SET_SRC (pattern);
5437 if (GET_CODE (pattern) != CALL
5438 || !MEM_P (XEXP (pattern, 0)))
5441 reg = XEXP (XEXP (pattern, 0), 0);
5445 reg = sfunc_uses_reg (insn);
5453 /* Try scanning backward to find where the register is set. */
5455 for (scan = PREV_INSN (insn);
5456 scan && !LABEL_P (scan);
5457 scan = PREV_INSN (scan))
5459 if (! INSN_P (scan))
5462 if (! reg_mentioned_p (reg, scan))
5465 if (noncall_uses_reg (reg, scan, &set))
5478 /* The register is set at LINK. */
5480 /* We can only optimize the function call if the register is
5481 being set to a symbol. In theory, we could sometimes
5482 optimize calls to a constant location, but the assembler
5483 and linker do not support that at present. */
5484 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5485 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5488 /* Scan forward from LINK to the place where REG dies, and
5489 make sure that the only insns which use REG are
5490 themselves function calls. */
5492 /* ??? This doesn't work for call targets that were allocated
5493 by reload, since there may not be a REG_DEAD note for the
5497 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5501 /* Don't try to trace forward past a CODE_LABEL if we haven't
5502 seen INSN yet. Ordinarily, we will only find the setting insn
5503 if it is in the same basic block. However,
5504 cross-jumping can insert code labels in between the load and
5505 the call, and can result in situations where a single call
5506 insn may have two targets depending on where we came from. */
5508 if (LABEL_P (scan) && ! foundinsn)
5511 if (! INSN_P (scan))
5514 /* Don't try to trace forward past a JUMP. To optimize
5515 safely, we would have to check that all the
5516 instructions at the jump destination did not use REG. */
5521 if (! reg_mentioned_p (reg, scan))
5524 if (noncall_uses_reg (reg, scan, &scanset))
5531 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5533 /* There is a function call to this register other
5534 than the one we are checking. If we optimize
5535 this call, we need to rescan again below. */
5539 /* ??? We shouldn't have to worry about SCANSET here.
5540 We should just be able to check for a REG_DEAD note
5541 on a function call. However, the REG_DEAD notes are
5542 apparently not dependable around libcalls; c-torture
5543 execute/920501-2 is a test case. If SCANSET is set,
5544 then this insn sets the register, so it must have
5545 died earlier. Unfortunately, this will only handle
5546 the cases in which the register is, in fact, set in a
5549 /* ??? We shouldn't have to use FOUNDINSN here.
5550 This dates back to when we used LOG_LINKS to find
5551 the most recent insn which sets the register. */
5555 || find_reg_note (scan, REG_DEAD, reg)))
5564 /* Either there was a branch, or some insn used REG
5565 other than as a function call address. */
5569 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5570 on the insn which sets the register, and on each call insn
5571 which uses the register. In final_prescan_insn we look for
5572 the REG_LABEL_OPERAND notes, and output the appropriate label
5575 label = gen_label_rtx ();
5576 add_reg_note (link, REG_LABEL_OPERAND, label);
5577 add_reg_note (insn, REG_LABEL_OPERAND, label);
5585 scan = NEXT_INSN (scan);
5588 && reg_mentioned_p (reg, scan))
5589 || ((reg2 = sfunc_uses_reg (scan))
5590 && REGNO (reg2) == REGNO (reg))))
5591 add_reg_note (scan, REG_LABEL_OPERAND, label);
5593 while (scan != dies);
5599 fixup_addr_diff_vecs (first);
5603 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5604 shorten_branches (first);
5607 /* Scan the function looking for move instructions which have to be
5608 changed to pc-relative loads and insert the literal tables. */
5609 label_ref_list_pool = create_alloc_pool ("label references list",
5610 sizeof (struct label_ref_list_d),
5612 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5613 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5617 /* ??? basic block reordering can move a switch table dispatch
5618 below the switch table. Check if that has happened.
5619 We only have the addresses available when optimizing; but then,
5620 this check shouldn't be needed when not optimizing. */
5621 if (!untangle_mova (&num_mova, &mova, insn))
5627 else if (JUMP_P (insn)
5628 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5630 /* ??? loop invariant motion can also move a mova out of a
5631 loop. Since loop does this code motion anyway, maybe we
5632 should wrap UNSPEC_MOVA into a CONST, so that reload can
5635 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5636 || (prev_nonnote_insn (insn)
5637 == XEXP (MOVA_LABELREF (mova), 0))))
5644 /* Some code might have been inserted between the mova and
5645 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5646 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5647 total += get_attr_length (scan);
5649 /* range of mova is 1020, add 4 because pc counts from address of
5650 second instruction after this one, subtract 2 in case pc is 2
5651 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5652 cancels out with alignment effects of the mova itself. */
5655 /* Change the mova into a load, and restart scanning
5656 there. broken_move will then return true for mova. */
5661 if (broken_move (insn)
5662 || (NONJUMP_INSN_P (insn)
5663 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5666 /* Scan ahead looking for a barrier to stick the constant table
5668 rtx barrier = find_barrier (num_mova, mova, insn);
5669 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5670 int need_aligned_label = 0;
5672 if (num_mova && ! mova_p (mova))
5674 /* find_barrier had to change the first mova into a
5675 pcload; thus, we have to start with this new pcload. */
5679 /* Now find all the moves between the points and modify them. */
5680 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5684 if (NONJUMP_INSN_P (scan)
5685 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5686 need_aligned_label = 1;
5687 if (broken_move (scan))
5689 rtx *patp = &PATTERN (scan), pat = *patp;
5693 enum machine_mode mode;
5695 if (GET_CODE (pat) == PARALLEL)
5696 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5697 src = SET_SRC (pat);
5698 dst = SET_DEST (pat);
5699 mode = GET_MODE (dst);
5701 if (mode == SImode && hi_const (src)
5702 && REGNO (dst) != FPUL_REG)
5707 while (GET_CODE (dst) == SUBREG)
5709 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5710 GET_MODE (SUBREG_REG (dst)),
5713 dst = SUBREG_REG (dst);
5715 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5717 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5719 /* This must be an insn that clobbers r0. */
5720 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5721 XVECLEN (PATTERN (scan), 0)
5723 rtx clobber = *clobberp;
5725 gcc_assert (GET_CODE (clobber) == CLOBBER
5726 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5729 && reg_set_between_p (r0_rtx, last_float_move, scan))
5733 && GET_MODE_SIZE (mode) != 4
5734 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5736 lab = add_constant (src, mode, last_float);
5738 emit_insn_before (gen_mova (lab), scan);
5741 /* There will be a REG_UNUSED note for r0 on
5742 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5743 lest reorg:mark_target_live_regs will not
5744 consider r0 to be used, and we end up with delay
5745 slot insn in front of SCAN that clobbers r0. */
5747 = find_regno_note (last_float_move, REG_UNUSED, 0);
5749 /* If we are not optimizing, then there may not be
5752 PUT_REG_NOTE_KIND (note, REG_INC);
5754 *last_float_addr = r0_inc_rtx;
5756 last_float_move = scan;
5758 newsrc = gen_const_mem (mode,
5759 (((TARGET_SH4 && ! TARGET_FMOVD)
5760 || REGNO (dst) == FPUL_REG)
5763 last_float_addr = &XEXP (newsrc, 0);
5765 /* Remove the clobber of r0. */
5766 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5767 gen_rtx_SCRATCH (Pmode));
5769 /* This is a mova needing a label. Create it. */
5770 else if (GET_CODE (src) == UNSPEC
5771 && XINT (src, 1) == UNSPEC_MOVA
5772 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5774 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5775 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5776 newsrc = gen_rtx_UNSPEC (SImode,
5777 gen_rtvec (1, newsrc),
5782 lab = add_constant (src, mode, 0);
5783 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5784 newsrc = gen_const_mem (mode, newsrc);
5786 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5787 INSN_CODE (scan) = -1;
5790 dump_table (need_aligned_label ? insn : 0, barrier);
5794 free_alloc_pool (label_ref_list_pool);
5795 for (insn = first; insn; insn = NEXT_INSN (insn))
5796 PUT_MODE (insn, VOIDmode);
5798 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5799 INSN_ADDRESSES_FREE ();
5800 split_branches (first);
5802 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5803 also has an effect on the register that holds the address of the sfunc.
5804 Insert an extra dummy insn in front of each sfunc that pretends to
5805 use this register. */
5806 if (flag_delayed_branch)
5808 for (insn = first; insn; insn = NEXT_INSN (insn))
5810 rtx reg = sfunc_uses_reg (insn);
5814 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5818 /* fpscr is not actually a user variable, but we pretend it is for the
5819 sake of the previous optimization passes, since we want it handled like
5820 one. However, we don't have any debugging information for it, so turn
5821 it into a non-user variable now. */
5823 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5825 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5829 get_dest_uid (rtx label, int max_uid)
5831 rtx dest = next_real_insn (label);
5834 /* This can happen for an undefined label. */
5836 dest_uid = INSN_UID (dest);
5837 /* If this is a newly created branch redirection blocking instruction,
5838 we cannot index the branch_uid or insn_addresses arrays with its
5839 uid. But then, we won't need to, because the actual destination is
5840 the following branch. */
5841 while (dest_uid >= max_uid)
5843 dest = NEXT_INSN (dest);
5844 dest_uid = INSN_UID (dest);
5846 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5851 /* Split condbranches that are out of range. Also add clobbers for
5852 scratch registers that are needed in far jumps.
5853 We do this before delay slot scheduling, so that it can take our
5854 newly created instructions into account. It also allows us to
5855 find branches with common targets more easily. */
5858 split_branches (rtx first)
5861 struct far_branch **uid_branch, *far_branch_list = 0;
5862 int max_uid = get_max_uid ();
5865 /* Find out which branches are out of range. */
5866 shorten_branches (first);
5868 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5869 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5871 for (insn = first; insn; insn = NEXT_INSN (insn))
5872 if (! INSN_P (insn))
5874 else if (INSN_DELETED_P (insn))
5876 /* Shorten_branches would split this instruction again,
5877 so transform it into a note. */
5878 SET_INSN_DELETED (insn);
5880 else if (JUMP_P (insn)
5881 /* Don't mess with ADDR_DIFF_VEC */
5882 && (GET_CODE (PATTERN (insn)) == SET
5883 || GET_CODE (PATTERN (insn)) == RETURN))
5885 enum attr_type type = get_attr_type (insn);
5886 if (type == TYPE_CBRANCH)
5890 if (get_attr_length (insn) > 4)
5892 rtx src = SET_SRC (PATTERN (insn));
5893 rtx olabel = XEXP (XEXP (src, 1), 0);
5894 int addr = INSN_ADDRESSES (INSN_UID (insn));
5896 int dest_uid = get_dest_uid (olabel, max_uid);
5897 struct far_branch *bp = uid_branch[dest_uid];
5899 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5900 the label if the LABEL_NUSES count drops to zero. There is
5901 always a jump_optimize pass that sets these values, but it
5902 proceeds to delete unreferenced code, and then if not
5903 optimizing, to un-delete the deleted instructions, thus
5904 leaving labels with too low uses counts. */
5907 JUMP_LABEL (insn) = olabel;
5908 LABEL_NUSES (olabel)++;
5912 bp = (struct far_branch *) alloca (sizeof *bp);
5913 uid_branch[dest_uid] = bp;
5914 bp->prev = far_branch_list;
5915 far_branch_list = bp;
5917 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5918 LABEL_NUSES (bp->far_label)++;
5922 label = bp->near_label;
5923 if (! label && bp->address - addr >= CONDJUMP_MIN)
5925 rtx block = bp->insert_place;
5927 if (GET_CODE (PATTERN (block)) == RETURN)
5928 block = PREV_INSN (block);
5930 block = gen_block_redirect (block,
5932 label = emit_label_after (gen_label_rtx (),
5934 bp->near_label = label;
5936 else if (label && ! NEXT_INSN (label))
5938 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5939 bp->insert_place = insn;
5941 gen_far_branch (bp);
5945 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5947 bp->near_label = label = gen_label_rtx ();
5948 bp->insert_place = insn;
5951 ok = redirect_jump (insn, label, 0);
5956 /* get_attr_length (insn) == 2 */
5957 /* Check if we have a pattern where reorg wants to redirect
5958 the branch to a label from an unconditional branch that
5960 /* We can't use JUMP_LABEL here because it might be undefined
5961 when not optimizing. */
5962 /* A syntax error might cause beyond to be NULL_RTX. */
5964 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5969 || ((beyond = next_active_insn (beyond))
5970 && JUMP_P (beyond)))
5971 && GET_CODE (PATTERN (beyond)) == SET
5972 && recog_memoized (beyond) == CODE_FOR_jump_compact
5974 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5975 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5977 gen_block_redirect (beyond,
5978 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5981 next = next_active_insn (insn);
5985 || ((next = next_active_insn (next))
5987 && GET_CODE (PATTERN (next)) == SET
5988 && recog_memoized (next) == CODE_FOR_jump_compact
5990 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5991 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5993 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5995 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5997 int addr = INSN_ADDRESSES (INSN_UID (insn));
6000 struct far_branch *bp;
6002 if (type == TYPE_JUMP)
6004 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
6005 dest_uid = get_dest_uid (far_label, max_uid);
6008 /* Parse errors can lead to labels outside
6010 if (! NEXT_INSN (far_label))
6015 JUMP_LABEL (insn) = far_label;
6016 LABEL_NUSES (far_label)++;
6018 redirect_jump (insn, ret_rtx, 1);
6022 bp = uid_branch[dest_uid];
6025 bp = (struct far_branch *) alloca (sizeof *bp);
6026 uid_branch[dest_uid] = bp;
6027 bp->prev = far_branch_list;
6028 far_branch_list = bp;
6030 bp->far_label = far_label;
6032 LABEL_NUSES (far_label)++;
6034 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6035 if (addr - bp->address <= CONDJUMP_MAX)
6036 emit_label_after (bp->near_label, PREV_INSN (insn));
6039 gen_far_branch (bp);
6045 bp->insert_place = insn;
6047 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6049 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6052 /* Generate all pending far branches,
6053 and free our references to the far labels. */
6054 while (far_branch_list)
6056 if (far_branch_list->near_label
6057 && ! NEXT_INSN (far_branch_list->near_label))
6058 gen_far_branch (far_branch_list);
6060 && far_branch_list->far_label
6061 && ! --LABEL_NUSES (far_branch_list->far_label))
6062 delete_insn (far_branch_list->far_label);
6063 far_branch_list = far_branch_list->prev;
6066 /* Instruction length information is no longer valid due to the new
6067 instructions that have been generated. */
6068 init_insn_lengths ();
6071 /* Dump out instruction addresses, which is useful for debugging the
6072 constant pool table stuff.
6074 If relaxing, output the label and pseudo-ops used to link together
6075 calls and the instruction which set the registers. */
6077 /* ??? The addresses printed by this routine for insns are nonsense for
6078 insns which are inside of a sequence where none of the inner insns have
6079 variable length. This is because the second pass of shorten_branches
6080 does not bother to update them. */
6083 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6084 int noperands ATTRIBUTE_UNUSED)
6086 if (TARGET_DUMPISIZE)
6087 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6093 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
6098 pattern = PATTERN (insn);
6099 if (GET_CODE (pattern) == PARALLEL)
6100 pattern = XVECEXP (pattern, 0, 0);
6101 switch (GET_CODE (pattern))
6104 if (GET_CODE (SET_SRC (pattern)) != CALL
6105 && get_attr_type (insn) != TYPE_SFUNC)
6107 targetm.asm_out.internal_label
6108 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6111 /* else FALLTHROUGH */
6113 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6114 CODE_LABEL_NUMBER (XEXP (note, 0)));
6124 /* Dump out any constants accumulated in the final pass. These will
6128 output_jump_label_table (void)
6134 fprintf (asm_out_file, "\t.align 2\n");
6135 for (i = 0; i < pool_size; i++)
6137 pool_node *p = &pool_vector[i];
6139 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6140 CODE_LABEL_NUMBER (p->label));
6141 output_asm_insn (".long %O0", &p->value);
6149 /* A full frame looks like:
6153 [ if current_function_anonymous_args
6166 local-0 <- fp points here. */
6168 /* Number of bytes pushed for anonymous args, used to pass information
6169 between expand_prologue and expand_epilogue. */
6171 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6172 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6173 for an epilogue and a negative value means that it's for a sibcall
6174 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6175 all the registers that are about to be restored, and hence dead. */
6178 output_stack_adjust (int size, rtx reg, int epilogue_p,
6179 HARD_REG_SET *live_regs_mask, bool frame_p)
6181 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6184 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6186 /* This test is bogus, as output_stack_adjust is used to re-align the
6189 gcc_assert (!(size % align));
6192 if (CONST_OK_FOR_ADD (size))
6193 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6194 /* Try to do it with two partial adjustments; however, we must make
6195 sure that the stack is properly aligned at all times, in case
6196 an interrupt occurs between the two partial adjustments. */
6197 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6198 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6200 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6201 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6207 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6210 /* If TEMP is invalid, we could temporarily save a general
6211 register to MACL. However, there is currently no need
6212 to handle this case, so just die when we see it. */
6214 || current_function_interrupt
6215 || ! call_really_used_regs[temp] || fixed_regs[temp])
6217 if (temp < 0 && ! current_function_interrupt
6218 && (TARGET_SHMEDIA || epilogue_p >= 0))
6221 COPY_HARD_REG_SET (temps, call_used_reg_set);
6222 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6226 if (crtl->return_rtx)
6228 enum machine_mode mode;
6229 mode = GET_MODE (crtl->return_rtx);
6230 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6231 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6233 for (i = 0; i < nreg; i++)
6234 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6235 if (crtl->calls_eh_return)
6237 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6238 for (i = 0; i <= 3; i++)
6239 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6242 if (TARGET_SHMEDIA && epilogue_p < 0)
6243 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6244 CLEAR_HARD_REG_BIT (temps, i);
6245 if (epilogue_p <= 0)
6247 for (i = FIRST_PARM_REG;
6248 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6249 CLEAR_HARD_REG_BIT (temps, i);
6250 if (cfun->static_chain_decl != NULL)
6251 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6253 temp = scavenge_reg (&temps);
6255 if (temp < 0 && live_regs_mask)
6259 COPY_HARD_REG_SET (temps, *live_regs_mask);
6260 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6261 temp = scavenge_reg (&temps);
6265 rtx adj_reg, tmp_reg, mem;
6267 /* If we reached here, the most likely case is the (sibcall)
6268 epilogue for non SHmedia. Put a special push/pop sequence
6269 for such case as the last resort. This looks lengthy but
6270 would not be problem because it seems to be very
6273 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6276 /* ??? There is still the slight possibility that r4 or
6277 r5 have been reserved as fixed registers or assigned
6278 as global registers, and they change during an
6279 interrupt. There are possible ways to handle this:
6281 - If we are adjusting the frame pointer (r14), we can do
6282 with a single temp register and an ordinary push / pop
6284 - Grab any call-used or call-saved registers (i.e. not
6285 fixed or globals) for the temps we need. We might
6286 also grab r14 if we are adjusting the stack pointer.
6287 If we can't find enough available registers, issue
6288 a diagnostic and die - the user must have reserved
6289 way too many registers.
6290 But since all this is rather unlikely to happen and
6291 would require extra testing, we just die if r4 / r5
6292 are not available. */
6293 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6294 && !global_regs[4] && !global_regs[5]);
6296 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6297 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6298 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6299 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6300 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6301 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6302 emit_move_insn (mem, tmp_reg);
6303 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6304 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6305 emit_move_insn (mem, tmp_reg);
6306 emit_move_insn (reg, adj_reg);
6307 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6308 emit_move_insn (adj_reg, mem);
6309 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6310 emit_move_insn (tmp_reg, mem);
6311 /* Tell flow the insns that pop r4/r5 aren't dead. */
6316 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6318 /* If SIZE is negative, subtract the positive value.
6319 This sometimes allows a constant pool entry to be shared
6320 between prologue and epilogue code. */
6323 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6324 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6328 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6329 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6332 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6333 gen_rtx_SET (VOIDmode, reg,
6334 gen_rtx_PLUS (SImode, reg,
6344 RTX_FRAME_RELATED_P (x) = 1;
6348 /* Output RTL to push register RN onto the stack. */
6355 x = gen_push_fpul ();
6356 else if (rn == FPSCR_REG)
6357 x = gen_push_fpscr ();
6358 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6359 && FP_OR_XD_REGISTER_P (rn))
6361 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6363 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6365 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6366 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6368 x = gen_push (gen_rtx_REG (SImode, rn));
6371 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6375 /* Output RTL to pop register RN from the stack. */
6382 x = gen_pop_fpul ();
6383 else if (rn == FPSCR_REG)
6384 x = gen_pop_fpscr ();
6385 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6386 && FP_OR_XD_REGISTER_P (rn))
6388 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6390 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6392 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6393 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6395 x = gen_pop (gen_rtx_REG (SImode, rn));
6398 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6401 /* Generate code to push the regs specified in the mask. */
6404 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6406 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6409 /* Push PR last; this gives better latencies after the prologue, and
6410 candidates for the return delay slot when there are no general
6411 registers pushed. */
6412 for (; i < FIRST_PSEUDO_REGISTER; i++)
6414 /* If this is an interrupt handler, and the SZ bit varies,
6415 and we have to push any floating point register, we need
6416 to switch to the correct precision first. */
6417 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6418 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6420 HARD_REG_SET unsaved;
6423 COMPL_HARD_REG_SET (unsaved, *mask);
6424 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6428 && (i != FPSCR_REG || ! skip_fpscr)
6429 && TEST_HARD_REG_BIT (*mask, i))
6431 /* If the ISR has RESBANK attribute assigned, don't push any of
6432 the following registers - R0-R14, MACH, MACL and GBR. */
6433 if (! (sh_cfun_resbank_handler_p ()
6434 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6442 /* Push banked registers last to improve delay slot opportunities. */
6443 if (interrupt_handler)
6445 bool use_movml = false;
6449 unsigned int count = 0;
6451 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6452 if (TEST_HARD_REG_BIT (*mask, i))
6457 /* Use movml when all banked registers are pushed. */
6458 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6464 rtx x, mem, reg, set;
6465 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6467 /* We must avoid scheduling multiple store insn with another
6469 emit_insn (gen_blockage ());
6470 x = gen_movml_push_banked (sp_reg);
6472 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6474 mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4));
6475 reg = gen_rtx_REG (SImode, i);
6476 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg));
6479 set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32));
6480 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6481 emit_insn (gen_blockage ());
6484 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6485 if (TEST_HARD_REG_BIT (*mask, i))
6489 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6490 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6494 /* Calculate how much extra space is needed to save all callee-saved
6496 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6499 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6502 int stack_space = 0;
6503 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6505 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6506 if ((! call_really_used_regs[reg] || interrupt_handler)
6507 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6508 /* Leave space to save this target register on the stack,
6509 in case target register allocation wants to use it. */
6510 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6514 /* Decide whether we should reserve space for callee-save target registers,
6515 in case target register allocation wants to use them. REGS_SAVED is
6516 the space, in bytes, that is already required for register saves.
6517 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6520 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6521 HARD_REG_SET *live_regs_mask)
6525 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6528 /* Decide how much space to reserve for callee-save target registers
6529 in case target register allocation wants to use them.
6530 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6533 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6535 if (shmedia_space_reserved_for_target_registers)
6536 return shmedia_target_regs_stack_space (live_regs_mask);
6541 /* Work out the registers which need to be saved, both as a mask and a
6542 count of saved words. Return the count.
6544 If doing a pragma interrupt function, then push all regs used by the
6545 function, and if we call another function (we can tell by looking at PR),
6546 make sure that all the regs it clobbers are safe too. */
6549 calc_live_regs (HARD_REG_SET *live_regs_mask)
6554 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6555 bool nosave_low_regs;
6556 int pr_live, has_call;
6558 attrs = DECL_ATTRIBUTES (current_function_decl);
6559 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6560 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6561 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6562 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6564 CLEAR_HARD_REG_SET (*live_regs_mask);
6565 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6566 && df_regs_ever_live_p (FPSCR_REG))
6567 target_flags &= ~MASK_FPU_SINGLE;
6568 /* If we can save a lot of saves by switching to double mode, do that. */
6569 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6570 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6571 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6572 && (! call_really_used_regs[reg]
6573 || interrupt_handler)
6576 target_flags &= ~MASK_FPU_SINGLE;
6579 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6580 knows how to use it. That means the pseudo originally allocated for
6581 the initial value can become the PR_MEDIA_REG hard register, as seen for
6582 execute/20010122-1.c:test9. */
6584 /* ??? this function is called from initial_elimination_offset, hence we
6585 can't use the result of sh_media_register_for_return here. */
6586 pr_live = sh_pr_n_sets ();
6589 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6590 pr_live = (pr_initial
6591 ? (!REG_P (pr_initial)
6592 || REGNO (pr_initial) != (PR_REG))
6593 : df_regs_ever_live_p (PR_REG));
6594 /* For Shcompact, if not optimizing, we end up with a memory reference
6595 using the return address pointer for __builtin_return_address even
6596 though there is no actual need to put the PR register on the stack. */
6597 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6599 /* Force PR to be live if the prologue has to call the SHmedia
6600 argument decoder or register saver. */
6601 if (TARGET_SHCOMPACT
6602 && ((crtl->args.info.call_cookie
6603 & ~ CALL_COOKIE_RET_TRAMP (1))
6604 || crtl->saves_all_registers))
6606 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6607 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6609 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6612 ? (/* Need to save all the regs ever live. */
6613 (df_regs_ever_live_p (reg)
6614 || (call_really_used_regs[reg]
6615 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6616 || reg == PIC_OFFSET_TABLE_REGNUM)
6618 || (TARGET_SHMEDIA && has_call
6619 && REGISTER_NATURAL_MODE (reg) == SImode
6620 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6621 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6622 && reg != RETURN_ADDRESS_POINTER_REGNUM
6623 && reg != T_REG && reg != GBR_REG
6624 /* Push fpscr only on targets which have FPU */
6625 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6626 : (/* Only push those regs which are used and need to be saved. */
6629 && crtl->args.info.call_cookie
6630 && reg == PIC_OFFSET_TABLE_REGNUM)
6631 || (df_regs_ever_live_p (reg)
6632 && ((!call_really_used_regs[reg]
6633 && !(reg != PIC_OFFSET_TABLE_REGNUM
6634 && fixed_regs[reg] && call_used_regs[reg]))
6635 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6636 || (crtl->calls_eh_return
6637 && (reg == EH_RETURN_DATA_REGNO (0)
6638 || reg == EH_RETURN_DATA_REGNO (1)
6639 || reg == EH_RETURN_DATA_REGNO (2)
6640 || reg == EH_RETURN_DATA_REGNO (3)))
6641 || ((reg == MACL_REG || reg == MACH_REG)
6642 && df_regs_ever_live_p (reg)
6643 && sh_cfun_attr_renesas_p ())
6646 SET_HARD_REG_BIT (*live_regs_mask, reg);
6647 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6649 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6650 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6652 if (FP_REGISTER_P (reg))
6654 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6656 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6657 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6660 else if (XD_REGISTER_P (reg))
6662 /* Must switch to double mode to access these registers. */
6663 target_flags &= ~MASK_FPU_SINGLE;
6667 if (nosave_low_regs && reg == R8_REG)
6670 /* If we have a target register optimization pass after prologue / epilogue
6671 threading, we need to assume all target registers will be live even if
6673 if (flag_branch_target_load_optimize2
6674 && TARGET_SAVE_ALL_TARGET_REGS
6675 && shmedia_space_reserved_for_target_registers)
6676 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6677 if ((! call_really_used_regs[reg] || interrupt_handler)
6678 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6680 SET_HARD_REG_BIT (*live_regs_mask, reg);
6681 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6683 /* If this is an interrupt handler, we don't have any call-clobbered
6684 registers we can conveniently use for target register save/restore.
6685 Make sure we save at least one general purpose register when we need
6686 to save target registers. */
6687 if (interrupt_handler
6688 && hard_reg_set_intersect_p (*live_regs_mask,
6689 reg_class_contents[TARGET_REGS])
6690 && ! hard_reg_set_intersect_p (*live_regs_mask,
6691 reg_class_contents[GENERAL_REGS]))
6693 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6694 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6700 /* Code to generate prologue and epilogue sequences */
6702 /* PUSHED is the number of bytes that are being pushed on the
6703 stack for register saves. Return the frame size, padded
6704 appropriately so that the stack stays properly aligned. */
6705 static HOST_WIDE_INT
6706 rounded_frame_size (int pushed)
6708 HOST_WIDE_INT size = get_frame_size ();
6709 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6711 if (ACCUMULATE_OUTGOING_ARGS)
6712 size += crtl->outgoing_args_size;
6714 return ((size + pushed + align - 1) & -align) - pushed;
6717 /* Choose a call-clobbered target-branch register that remains
6718 unchanged along the whole function. We set it up as the return
6719 value in the prologue. */
6721 sh_media_register_for_return (void)
6726 if (! current_function_is_leaf)
6728 if (lookup_attribute ("interrupt_handler",
6729 DECL_ATTRIBUTES (current_function_decl)))
6731 if (sh_cfun_interrupt_handler_p ())
6734 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6736 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6737 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6743 /* The maximum registers we need to save are:
6744 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6745 - 32 floating point registers (for each pair, we save none,
6746 one single precision value, or a double precision value).
6747 - 8 target registers
6748 - add 1 entry for a delimiter. */
6749 #define MAX_SAVED_REGS (62+32+8)
6751 typedef struct save_entry_s
6760 /* There will be a delimiter entry with VOIDmode both at the start and the
6761 end of a filled in schedule. The end delimiter has the offset of the
6762 save with the smallest (i.e. most negative) offset. */
6763 typedef struct save_schedule_s
6765 save_entry entries[MAX_SAVED_REGS + 2];
6766 int temps[MAX_TEMPS+1];
6769 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6770 use reverse order. Returns the last entry written to (not counting
6771 the delimiter). OFFSET_BASE is a number to be added to all offset
6775 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6779 save_entry *entry = schedule->entries;
6783 if (! current_function_interrupt)
6784 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6785 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6786 && ! FUNCTION_ARG_REGNO_P (i)
6787 && i != FIRST_RET_REG
6788 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6789 && ! (crtl->calls_eh_return
6790 && (i == EH_RETURN_STACKADJ_REGNO
6791 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6792 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6793 schedule->temps[tmpx++] = i;
6795 entry->mode = VOIDmode;
6796 entry->offset = offset_base;
6798 /* We loop twice: first, we save 8-byte aligned registers in the
6799 higher addresses, that are known to be aligned. Then, we
6800 proceed to saving 32-bit registers that don't need 8-byte
6802 If this is an interrupt function, all registers that need saving
6803 need to be saved in full. moreover, we need to postpone saving
6804 target registers till we have saved some general purpose registers
6805 we can then use as scratch registers. */
6806 offset = offset_base;
6807 for (align = 1; align >= 0; align--)
6809 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6810 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6812 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6815 if (current_function_interrupt)
6817 if (TARGET_REGISTER_P (i))
6819 if (GENERAL_REGISTER_P (i))
6822 if (mode == SFmode && (i % 2) == 1
6823 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6824 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6831 /* If we're doing the aligned pass and this is not aligned,
6832 or we're doing the unaligned pass and this is aligned,
6834 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6838 if (current_function_interrupt
6839 && GENERAL_REGISTER_P (i)
6840 && tmpx < MAX_TEMPS)
6841 schedule->temps[tmpx++] = i;
6843 offset -= GET_MODE_SIZE (mode);
6846 entry->offset = offset;
6849 if (align && current_function_interrupt)
6850 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6851 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6853 offset -= GET_MODE_SIZE (DImode);
6855 entry->mode = DImode;
6856 entry->offset = offset;
6861 entry->mode = VOIDmode;
6862 entry->offset = offset;
6863 schedule->temps[tmpx] = -1;
6868 sh_expand_prologue (void)
6870 HARD_REG_SET live_regs_mask;
6873 int save_flags = target_flags;
6877 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6879 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6881 /* We have pretend args if we had an object sent partially in registers
6882 and partially on the stack, e.g. a large structure. */
6883 pretend_args = crtl->args.pretend_args_size;
6884 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6885 && (NPARM_REGS(SImode)
6886 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6889 output_stack_adjust (-pretend_args
6890 - crtl->args.info.stack_regs * 8,
6891 stack_pointer_rtx, 0, NULL, true);
6892 stack_usage = pretend_args + crtl->args.info.stack_regs * 8;
6894 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6895 /* We're going to use the PIC register to load the address of the
6896 incoming-argument decoder and/or of the return trampoline from
6897 the GOT, so make sure the PIC register is preserved and
6899 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6901 if (TARGET_SHCOMPACT
6902 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6906 /* First, make all registers with incoming arguments that will
6907 be pushed onto the stack live, so that register renaming
6908 doesn't overwrite them. */
6909 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6910 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6911 >= NPARM_REGS (SImode) - reg)
6912 for (; reg < NPARM_REGS (SImode); reg++)
6913 emit_insn (gen_shcompact_preserve_incoming_args
6914 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6915 else if (CALL_COOKIE_INT_REG_GET
6916 (crtl->args.info.call_cookie, reg) == 1)
6917 emit_insn (gen_shcompact_preserve_incoming_args
6918 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6920 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6922 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6923 GEN_INT (crtl->args.info.call_cookie));
6924 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6925 gen_rtx_REG (SImode, R0_REG));
6927 else if (TARGET_SHMEDIA)
6929 int tr = sh_media_register_for_return ();
6932 emit_move_insn (gen_rtx_REG (DImode, tr),
6933 gen_rtx_REG (DImode, PR_MEDIA_REG));
6936 /* Emit the code for SETUP_VARARGS. */
6939 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6941 /* Push arg regs as if they'd been provided by caller in stack. */
6942 for (i = 0; i < NPARM_REGS(SImode); i++)
6944 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6946 if (i >= (NPARM_REGS(SImode)
6947 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6951 stack_usage += GET_MODE_SIZE (SImode);
6956 /* If we're supposed to switch stacks at function entry, do so now. */
6960 /* The argument specifies a variable holding the address of the
6961 stack the interrupt function should switch to/from at entry/exit. */
6962 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6964 = ggc_strdup (TREE_STRING_POINTER (arg));
6965 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6967 lab = add_constant (sp_switch, SImode, 0);
6968 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6969 newsrc = gen_const_mem (SImode, newsrc);
6971 emit_insn (gen_sp_switch_1 (newsrc));
6974 d = calc_live_regs (&live_regs_mask);
6975 /* ??? Maybe we could save some switching if we can move a mode switch
6976 that already happens to be at the function start into the prologue. */
6977 if (target_flags != save_flags && ! current_function_interrupt)
6978 emit_insn (gen_toggle_sz ());
6982 int offset_base, offset;
6984 int offset_in_r0 = -1;
6986 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6987 int total_size, save_size;
6988 save_schedule schedule;
6992 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6993 && ! current_function_interrupt)
6994 r0 = gen_rtx_REG (Pmode, R0_REG);
6996 /* D is the actual number of bytes that we need for saving registers,
6997 however, in initial_elimination_offset we have committed to using
6998 an additional TREGS_SPACE amount of bytes - in order to keep both
6999 addresses to arguments supplied by the caller and local variables
7000 valid, we must keep this gap. Place it between the incoming
7001 arguments and the actually saved registers in a bid to optimize
7002 locality of reference. */
7003 total_size = d + tregs_space;
7004 total_size += rounded_frame_size (total_size);
7005 save_size = total_size - rounded_frame_size (d);
7006 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
7007 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7008 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
7010 /* If adjusting the stack in a single step costs nothing extra, do so.
7011 I.e. either if a single addi is enough, or we need a movi anyway,
7012 and we don't exceed the maximum offset range (the test for the
7013 latter is conservative for simplicity). */
7015 && (CONST_OK_FOR_I10 (-total_size)
7016 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
7017 && total_size <= 2044)))
7018 d_rounding = total_size - save_size;
7020 offset_base = d + d_rounding;
7022 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
7024 stack_usage += save_size + d_rounding;
7026 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
7027 tmp_pnt = schedule.temps;
7028 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7030 enum machine_mode mode = (enum machine_mode) entry->mode;
7031 unsigned int reg = entry->reg;
7032 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
7035 offset = entry->offset;
7037 reg_rtx = gen_rtx_REG (mode, reg);
7039 mem_rtx = gen_frame_mem (mode,
7040 gen_rtx_PLUS (Pmode,
7044 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7050 if (HAVE_PRE_DECREMENT
7051 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
7052 || mem_rtx == NULL_RTX
7053 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7055 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
7057 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
7062 offset += GET_MODE_SIZE (mode);
7066 if (mem_rtx != NULL_RTX)
7069 if (offset_in_r0 == -1)
7071 emit_move_insn (r0, GEN_INT (offset));
7072 offset_in_r0 = offset;
7074 else if (offset != offset_in_r0)
7079 GEN_INT (offset - offset_in_r0)));
7080 offset_in_r0 += offset - offset_in_r0;
7083 if (pre_dec != NULL_RTX)
7089 (Pmode, r0, stack_pointer_rtx));
7093 offset -= GET_MODE_SIZE (mode);
7094 offset_in_r0 -= GET_MODE_SIZE (mode);
7099 mem_rtx = gen_frame_mem (mode, r0);
7101 mem_rtx = gen_frame_mem (mode,
7102 gen_rtx_PLUS (Pmode,
7106 /* We must not use an r0-based address for target-branch
7107 registers or for special registers without pre-dec
7108 memory addresses, since we store their values in r0
7110 gcc_assert (!TARGET_REGISTER_P (reg)
7111 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7112 || mem_rtx == pre_dec));
7115 orig_reg_rtx = reg_rtx;
7116 if (TARGET_REGISTER_P (reg)
7117 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7118 && mem_rtx != pre_dec))
7120 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
7122 emit_move_insn (tmp_reg, reg_rtx);
7124 if (REGNO (tmp_reg) == R0_REG)
7128 gcc_assert (!refers_to_regno_p
7129 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
7132 if (*++tmp_pnt <= 0)
7133 tmp_pnt = schedule.temps;
7140 /* Mark as interesting for dwarf cfi generator */
7141 insn = emit_move_insn (mem_rtx, reg_rtx);
7142 RTX_FRAME_RELATED_P (insn) = 1;
7143 /* If we use an intermediate register for the save, we can't
7144 describe this exactly in cfi as a copy of the to-be-saved
7145 register into the temporary register and then the temporary
7146 register on the stack, because the temporary register can
7147 have a different natural size than the to-be-saved register.
7148 Thus, we gloss over the intermediate copy and pretend we do
7149 a direct save from the to-be-saved register. */
7150 if (REGNO (reg_rtx) != reg)
7154 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
7155 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7158 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
7160 rtx reg_rtx = gen_rtx_REG (mode, reg);
7162 rtx mem_rtx = gen_frame_mem (mode,
7163 gen_rtx_PLUS (Pmode,
7167 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
7168 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7173 gcc_assert (entry->offset == d_rounding);
7177 push_regs (&live_regs_mask, current_function_interrupt);
7181 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7182 emit_insn (gen_GOTaddr2picreg ());
7184 if (SHMEDIA_REGS_STACK_ADJUST ())
7186 /* This must NOT go through the PLT, otherwise mach and macl
7187 may be clobbered. */
7188 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7190 ? "__GCC_push_shmedia_regs"
7191 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7192 emit_insn (gen_shmedia_save_restore_regs_compact
7193 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7196 if (target_flags != save_flags && ! current_function_interrupt)
7197 emit_insn (gen_toggle_sz ());
7199 target_flags = save_flags;
7201 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7202 stack_pointer_rtx, 0, NULL, true);
7203 stack_usage += rounded_frame_size (d) - d_rounding;
7205 if (frame_pointer_needed)
7206 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7208 if (TARGET_SHCOMPACT
7209 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7211 /* This must NOT go through the PLT, otherwise mach and macl
7212 may be clobbered. */
7213 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7214 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7215 emit_insn (gen_shcompact_incoming_args ());
7218 /* If we are profiling, make sure no instructions are scheduled before
7219 the call to mcount. Similarly if some call instructions are swapped
7220 before frame related insns, it'll confuse the unwinder because
7221 currently SH has no unwind info for function epilogues. */
7222 if (crtl->profile || flag_exceptions || flag_unwind_tables)
7223 emit_insn (gen_blockage ());
7225 if (flag_stack_usage_info)
7226 current_function_static_stack_size = stack_usage;
7230 sh_expand_epilogue (bool sibcall_p)
7232 HARD_REG_SET live_regs_mask;
7236 int save_flags = target_flags;
7237 int frame_size, save_size;
7238 int fpscr_deferred = 0;
7239 int e = sibcall_p ? -1 : 1;
7241 d = calc_live_regs (&live_regs_mask);
7244 frame_size = rounded_frame_size (d);
7248 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7250 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7251 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7252 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7254 total_size = d + tregs_space;
7255 total_size += rounded_frame_size (total_size);
7256 save_size = total_size - frame_size;
7258 /* If adjusting the stack in a single step costs nothing extra, do so.
7259 I.e. either if a single addi is enough, or we need a movi anyway,
7260 and we don't exceed the maximum offset range (the test for the
7261 latter is conservative for simplicity). */
7263 && ! frame_pointer_needed
7264 && (CONST_OK_FOR_I10 (total_size)
7265 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7266 && total_size <= 2044)))
7267 d_rounding = frame_size;
7269 frame_size -= d_rounding;
7272 if (frame_pointer_needed)
7274 /* We must avoid scheduling the epilogue with previous basic blocks.
7275 See PR/18032 and PR/40313. */
7276 emit_insn (gen_blockage ());
7277 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7278 &live_regs_mask, false);
7280 /* We must avoid moving the stack pointer adjustment past code
7281 which reads from the local frame, else an interrupt could
7282 occur after the SP adjustment and clobber data in the local
7284 emit_insn (gen_blockage ());
7285 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7287 else if (frame_size)
7289 /* We must avoid moving the stack pointer adjustment past code
7290 which reads from the local frame, else an interrupt could
7291 occur after the SP adjustment and clobber data in the local
7293 emit_insn (gen_blockage ());
7294 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7295 &live_regs_mask, false);
7298 if (SHMEDIA_REGS_STACK_ADJUST ())
7300 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7302 ? "__GCC_pop_shmedia_regs"
7303 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7304 /* This must NOT go through the PLT, otherwise mach and macl
7305 may be clobbered. */
7306 emit_insn (gen_shmedia_save_restore_regs_compact
7307 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7310 /* Pop all the registers. */
7312 if (target_flags != save_flags && ! current_function_interrupt)
7313 emit_insn (gen_toggle_sz ());
7316 int offset_base, offset;
7317 int offset_in_r0 = -1;
7319 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7320 save_schedule schedule;
7324 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7325 offset_base = -entry[1].offset + d_rounding;
7326 tmp_pnt = schedule.temps;
7327 for (; entry->mode != VOIDmode; entry--)
7329 enum machine_mode mode = (enum machine_mode) entry->mode;
7330 int reg = entry->reg;
7331 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX;
7333 offset = offset_base + entry->offset;
7334 reg_rtx = gen_rtx_REG (mode, reg);
7336 mem_rtx = gen_frame_mem (mode,
7337 gen_rtx_PLUS (Pmode,
7341 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7344 if (HAVE_POST_INCREMENT
7345 && (offset == offset_in_r0
7346 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7347 && mem_rtx == NULL_RTX)
7348 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7350 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7352 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7353 post_inc = NULL_RTX;
7358 if (mem_rtx != NULL_RTX)
7361 if (offset_in_r0 == -1)
7363 emit_move_insn (r0, GEN_INT (offset));
7364 offset_in_r0 = offset;
7366 else if (offset != offset_in_r0)
7371 GEN_INT (offset - offset_in_r0)));
7372 offset_in_r0 += offset - offset_in_r0;
7375 if (post_inc != NULL_RTX)
7381 (Pmode, r0, stack_pointer_rtx));
7387 offset_in_r0 += GET_MODE_SIZE (mode);
7390 mem_rtx = gen_frame_mem (mode, r0);
7392 mem_rtx = gen_frame_mem (mode,
7393 gen_rtx_PLUS (Pmode,
7397 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7398 || mem_rtx == post_inc);
7401 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7402 && mem_rtx != post_inc)
7404 emit_move_insn (r0, mem_rtx);
7407 else if (TARGET_REGISTER_P (reg))
7409 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7411 /* Give the scheduler a bit of freedom by using up to
7412 MAX_TEMPS registers in a round-robin fashion. */
7413 emit_move_insn (tmp_reg, mem_rtx);
7416 tmp_pnt = schedule.temps;
7419 emit_move_insn (reg_rtx, mem_rtx);
7422 gcc_assert (entry->offset + offset_base == d + d_rounding);
7424 else /* ! TARGET_SH5 */
7429 /* For an ISR with RESBANK attribute assigned, don't pop PR
7431 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7432 && !sh_cfun_resbank_handler_p ())
7434 if (!frame_pointer_needed)
7435 emit_insn (gen_blockage ());
7439 /* Banked registers are popped first to avoid being scheduled in the
7440 delay slot. RTE switches banks before the ds instruction. */
7441 if (current_function_interrupt)
7443 bool use_movml = false;
7447 unsigned int count = 0;
7449 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7450 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7455 /* Use movml when all banked register are poped. */
7456 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7462 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7464 /* We must avoid scheduling multiple load insn with another
7466 emit_insn (gen_blockage ());
7467 emit_insn (gen_movml_pop_banked (sp_reg));
7468 emit_insn (gen_blockage ());
7471 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7472 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7475 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7478 last_reg = FIRST_PSEUDO_REGISTER;
7480 for (i = 0; i < last_reg; i++)
7482 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7484 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7485 && hard_reg_set_intersect_p (live_regs_mask,
7486 reg_class_contents[DF_REGS]))
7488 /* For an ISR with RESBANK attribute assigned, don't pop
7489 following registers, R0-R14, MACH, MACL and GBR. */
7490 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7491 && ! (sh_cfun_resbank_handler_p ()
7492 && ((j >= FIRST_GENERAL_REG
7493 && j < LAST_GENERAL_REG)
7499 if (j == FIRST_FP_REG && fpscr_deferred)
7503 if (target_flags != save_flags && ! current_function_interrupt)
7504 emit_insn (gen_toggle_sz ());
7505 target_flags = save_flags;
7507 output_stack_adjust (crtl->args.pretend_args_size
7508 + save_size + d_rounding
7509 + crtl->args.info.stack_regs * 8,
7510 stack_pointer_rtx, e, NULL, false);
7512 if (crtl->calls_eh_return)
7513 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7514 EH_RETURN_STACKADJ_RTX));
7516 /* Switch back to the normal stack if necessary. */
7517 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7518 emit_insn (gen_sp_switch_2 ());
7520 /* Tell flow the insn that pops PR isn't dead. */
7521 /* PR_REG will never be live in SHmedia mode, and we don't need to
7522 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7523 by the return pattern. */
7524 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7525 emit_use (gen_rtx_REG (SImode, PR_REG));
7528 static int sh_need_epilogue_known = 0;
7531 sh_need_epilogue (void)
7533 if (! sh_need_epilogue_known)
7538 sh_expand_epilogue (0);
7539 epilogue = get_insns ();
7541 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7543 return sh_need_epilogue_known > 0;
7546 /* Emit code to change the current function's return address to RA.
7547 TEMP is available as a scratch register, if needed. */
7550 sh_set_return_address (rtx ra, rtx tmp)
7552 HARD_REG_SET live_regs_mask;
7554 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7557 d = calc_live_regs (&live_regs_mask);
7559 /* If pr_reg isn't life, we can set it (or the register given in
7560 sh_media_register_for_return) directly. */
7561 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7567 int rr_regno = sh_media_register_for_return ();
7572 rr = gen_rtx_REG (DImode, rr_regno);
7575 rr = gen_rtx_REG (SImode, pr_reg);
7577 emit_insn (GEN_MOV (rr, ra));
7578 /* Tell flow the register for return isn't dead. */
7586 save_schedule schedule;
7589 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7590 offset = entry[1].offset;
7591 for (; entry->mode != VOIDmode; entry--)
7592 if (entry->reg == pr_reg)
7595 /* We can't find pr register. */
7599 offset = entry->offset - offset;
7600 pr_offset = (rounded_frame_size (d) + offset
7601 + SHMEDIA_REGS_STACK_ADJUST ());
7604 pr_offset = rounded_frame_size (d);
7606 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7608 if (frame_pointer_needed)
7609 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7611 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7613 tmp = gen_frame_mem (Pmode, tmp);
7614 emit_insn (GEN_MOV (tmp, ra));
7615 /* Tell this store isn't dead. */
7619 /* Clear variables at function end. */
7622 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7623 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7625 sh_need_epilogue_known = 0;
7629 sh_builtin_saveregs (void)
7631 /* First unnamed integer register. */
7632 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7633 /* Number of integer registers we need to save. */
7634 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7635 /* First unnamed SFmode float reg */
7636 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7637 /* Number of SFmode float regs to save. */
7638 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7641 alias_set_type alias_set;
7647 int pushregs = n_intregs;
7649 while (pushregs < NPARM_REGS (SImode) - 1
7650 && (CALL_COOKIE_INT_REG_GET
7651 (crtl->args.info.call_cookie,
7652 NPARM_REGS (SImode) - pushregs)
7655 crtl->args.info.call_cookie
7656 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7661 if (pushregs == NPARM_REGS (SImode))
7662 crtl->args.info.call_cookie
7663 |= (CALL_COOKIE_INT_REG (0, 1)
7664 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7666 crtl->args.info.call_cookie
7667 |= CALL_COOKIE_STACKSEQ (pushregs);
7669 crtl->args.pretend_args_size += 8 * n_intregs;
7671 if (TARGET_SHCOMPACT)
7675 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7677 error ("__builtin_saveregs not supported by this subtarget");
7684 /* Allocate block of memory for the regs. */
7685 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7686 Or can assign_stack_local accept a 0 SIZE argument? */
7687 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7690 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7691 else if (n_floatregs & 1)
7695 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7696 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7697 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7698 regbuf = change_address (regbuf, BLKmode, addr);
7700 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7704 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7705 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7706 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7707 emit_insn (gen_andsi3 (addr, addr, mask));
7708 regbuf = change_address (regbuf, BLKmode, addr);
7711 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7712 alias_set = get_varargs_alias_set ();
7713 set_mem_alias_set (regbuf, alias_set);
7716 This is optimized to only save the regs that are necessary. Explicitly
7717 named args need not be saved. */
7719 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7720 adjust_address (regbuf, BLKmode,
7721 n_floatregs * UNITS_PER_WORD),
7725 /* Return the address of the regbuf. */
7726 return XEXP (regbuf, 0);
7729 This is optimized to only save the regs that are necessary. Explicitly
7730 named args need not be saved.
7731 We explicitly build a pointer to the buffer because it halves the insn
7732 count when not optimizing (otherwise the pointer is built for each reg
7734 We emit the moves in reverse order so that we can use predecrement. */
7736 fpregs = copy_to_mode_reg (Pmode,
7737 plus_constant (XEXP (regbuf, 0),
7738 n_floatregs * UNITS_PER_WORD));
7739 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7742 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7744 emit_insn (gen_addsi3 (fpregs, fpregs,
7745 GEN_INT (-2 * UNITS_PER_WORD)));
7746 mem = change_address (regbuf, DFmode, fpregs);
7747 emit_move_insn (mem,
7748 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7750 regno = first_floatreg;
7753 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7754 mem = change_address (regbuf, SFmode, fpregs);
7755 emit_move_insn (mem,
7756 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7757 - (TARGET_LITTLE_ENDIAN != 0)));
7761 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7765 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7766 mem = change_address (regbuf, SFmode, fpregs);
7767 emit_move_insn (mem,
7768 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7771 /* Return the address of the regbuf. */
7772 return XEXP (regbuf, 0);
7775 /* Define the `__builtin_va_list' type for the ABI. */
7778 sh_build_builtin_va_list (void)
7780 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7781 tree record, type_decl;
7783 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7784 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7785 return ptr_type_node;
7787 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7788 type_decl = build_decl (BUILTINS_LOCATION,
7789 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7791 f_next_o = build_decl (BUILTINS_LOCATION,
7792 FIELD_DECL, get_identifier ("__va_next_o"),
7794 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7796 get_identifier ("__va_next_o_limit"),
7798 f_next_fp = build_decl (BUILTINS_LOCATION,
7799 FIELD_DECL, get_identifier ("__va_next_fp"),
7801 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7803 get_identifier ("__va_next_fp_limit"),
7805 f_next_stack = build_decl (BUILTINS_LOCATION,
7806 FIELD_DECL, get_identifier ("__va_next_stack"),
7809 DECL_FIELD_CONTEXT (f_next_o) = record;
7810 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7811 DECL_FIELD_CONTEXT (f_next_fp) = record;
7812 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7813 DECL_FIELD_CONTEXT (f_next_stack) = record;
7815 TYPE_STUB_DECL (record) = type_decl;
7816 TYPE_NAME (record) = type_decl;
7817 TYPE_FIELDS (record) = f_next_o;
7818 DECL_CHAIN (f_next_o) = f_next_o_limit;
7819 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7820 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7821 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7823 layout_type (record);
7828 /* Implement `va_start' for varargs and stdarg. */
7831 sh_va_start (tree valist, rtx nextarg)
7833 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7834 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7840 expand_builtin_saveregs ();
7841 std_expand_builtin_va_start (valist, nextarg);
7845 if ((! TARGET_SH2E && ! TARGET_SH4)
7846 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7848 std_expand_builtin_va_start (valist, nextarg);
7852 f_next_o = TYPE_FIELDS (va_list_type_node);
7853 f_next_o_limit = DECL_CHAIN (f_next_o);
7854 f_next_fp = DECL_CHAIN (f_next_o_limit);
7855 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7856 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7858 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7860 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7861 valist, f_next_o_limit, NULL_TREE);
7862 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7864 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7865 valist, f_next_fp_limit, NULL_TREE);
7866 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7867 valist, f_next_stack, NULL_TREE);
7869 /* Call __builtin_saveregs. */
7870 u = make_tree (sizetype, expand_builtin_saveregs ());
7871 u = fold_convert (ptr_type_node, u);
7872 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7873 TREE_SIDE_EFFECTS (t) = 1;
7874 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7876 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7881 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp);
7882 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7883 TREE_SIDE_EFFECTS (t) = 1;
7884 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7886 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7887 TREE_SIDE_EFFECTS (t) = 1;
7888 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7890 nint = crtl->args.info.arg_count[SH_ARG_INT];
7895 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint);
7896 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7897 TREE_SIDE_EFFECTS (t) = 1;
7898 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7900 u = make_tree (ptr_type_node, nextarg);
7901 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7902 TREE_SIDE_EFFECTS (t) = 1;
7903 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7906 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7907 member, return it. */
7909 find_sole_member (tree type)
7911 tree field, member = NULL_TREE;
7913 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
7915 if (TREE_CODE (field) != FIELD_DECL)
7917 if (!DECL_SIZE (field))
7919 if (integer_zerop (DECL_SIZE (field)))
7927 /* Implement `va_arg'. */
7930 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7931 gimple_seq *post_p ATTRIBUTE_UNUSED)
7933 HOST_WIDE_INT size, rsize;
7934 tree tmp, pptr_type_node;
7935 tree addr, lab_over = NULL, result = NULL;
7939 if (!VOID_TYPE_P (type))
7940 pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7942 pass_by_ref = false;
7945 type = build_pointer_type (type);
7947 size = int_size_in_bytes (type);
7948 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7949 pptr_type_node = build_pointer_type (ptr_type_node);
7951 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7952 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7954 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7955 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7960 f_next_o = TYPE_FIELDS (va_list_type_node);
7961 f_next_o_limit = DECL_CHAIN (f_next_o);
7962 f_next_fp = DECL_CHAIN (f_next_o_limit);
7963 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7964 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7966 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7968 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7969 valist, f_next_o_limit, NULL_TREE);
7970 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7971 valist, f_next_fp, NULL_TREE);
7972 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7973 valist, f_next_fp_limit, NULL_TREE);
7974 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7975 valist, f_next_stack, NULL_TREE);
7977 /* Structures with a single member with a distinct mode are passed
7978 like their member. This is relevant if the latter has a REAL_TYPE
7979 or COMPLEX_TYPE type. */
7981 while (TREE_CODE (eff_type) == RECORD_TYPE
7982 && (member = find_sole_member (eff_type))
7983 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7984 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7985 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7987 tree field_type = TREE_TYPE (member);
7989 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7990 eff_type = field_type;
7993 gcc_assert ((TYPE_ALIGN (eff_type)
7994 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7995 || (TYPE_ALIGN (eff_type)
7996 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
8001 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8003 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
8004 || (TREE_CODE (eff_type) == COMPLEX_TYPE
8005 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
8010 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
8013 addr = create_tmp_var (pptr_type_node, NULL);
8014 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8015 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8017 valist = build_simple_mem_ref (addr);
8021 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
8023 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
8025 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
8026 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8028 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
8029 tmp = next_fp_limit;
8030 if (size > 4 && !is_double)
8031 tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size);
8032 tmp = build2 (GE_EXPR, boolean_type_node,
8033 unshare_expr (next_fp_tmp), unshare_expr (tmp));
8034 cmp = build3 (COND_EXPR, void_type_node, tmp,
8035 build1 (GOTO_EXPR, void_type_node,
8036 unshare_expr (lab_false)), NULL_TREE);
8038 gimplify_and_add (cmp, pre_p);
8040 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
8041 || (is_double || size == 16))
8043 tmp = fold_convert (sizetype, next_fp_tmp);
8044 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
8045 size_int (UNITS_PER_WORD));
8046 tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp);
8047 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
8050 gimplify_and_add (cmp, pre_p);
8052 #ifdef FUNCTION_ARG_SCmode_WART
8053 if (TYPE_MODE (eff_type) == SCmode
8054 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
8056 tree subtype = TREE_TYPE (eff_type);
8060 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8061 imag = get_initialized_tmp_var (imag, pre_p, NULL);
8064 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8065 real = get_initialized_tmp_var (real, pre_p, NULL);
8067 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
8068 if (type != eff_type)
8069 result = build1 (VIEW_CONVERT_EXPR, type, result);
8070 result = get_initialized_tmp_var (result, pre_p, NULL);
8072 #endif /* FUNCTION_ARG_SCmode_WART */
8074 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8075 gimplify_and_add (tmp, pre_p);
8077 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8078 gimplify_and_add (tmp, pre_p);
8080 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8081 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8082 gimplify_assign (unshare_expr (next_fp_tmp),
8083 unshare_expr (valist), pre_p);
8085 gimplify_assign (unshare_expr (valist),
8086 unshare_expr (next_fp_tmp), post_p);
8087 valist = next_fp_tmp;
8091 tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize);
8092 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
8093 unshare_expr (next_o_limit));
8094 tmp = build3 (COND_EXPR, void_type_node, tmp,
8095 build1 (GOTO_EXPR, void_type_node,
8096 unshare_expr (lab_false)),
8098 gimplify_and_add (tmp, pre_p);
8100 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
8101 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8103 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8104 gimplify_and_add (tmp, pre_p);
8106 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8107 gimplify_and_add (tmp, pre_p);
8109 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8110 gimplify_assign (unshare_expr (next_o),
8111 unshare_expr (next_o_limit), pre_p);
8113 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8114 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8119 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8120 gimplify_and_add (tmp, pre_p);
8124 /* ??? In va-sh.h, there had been code to make values larger than
8125 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8127 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
8130 gimplify_assign (result, tmp, pre_p);
8131 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
8132 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8133 gimplify_and_add (tmp, pre_p);
8139 result = build_va_arg_indirect_ref (result);
8144 /* 64 bit floating points memory transfers are paired single precision loads
8145 or store. So DWARF information needs fixing in little endian (unless
8146 PR=SZ=1 in FPSCR). */
8148 sh_dwarf_register_span (rtx reg)
8150 unsigned regno = REGNO (reg);
8152 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8156 gen_rtx_PARALLEL (VOIDmode,
8158 gen_rtx_REG (SFmode, regno + 1),
8159 gen_rtx_REG (SFmode, regno)));
8162 static enum machine_mode
8163 sh_promote_function_mode (const_tree type, enum machine_mode mode,
8164 int *punsignedp, const_tree funtype,
8167 if (sh_promote_prototypes (funtype))
8168 return promote_mode (type, mode, punsignedp);
8170 return default_promote_function_mode (type, mode, punsignedp, funtype,
8175 sh_promote_prototypes (const_tree type)
8181 return ! sh_attr_renesas_p (type);
8184 /* Whether an argument must be passed by reference. On SHcompact, we
8185 pretend arguments wider than 32-bits that would have been passed in
8186 registers are passed by reference, so that an SHmedia trampoline
8187 loads them into the full 64-bits registers. */
8190 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8191 const_tree type, bool named)
8193 unsigned HOST_WIDE_INT size;
8196 size = int_size_in_bytes (type);
8198 size = GET_MODE_SIZE (mode);
8200 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8202 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8203 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8204 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8206 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8207 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8214 sh_pass_by_reference (cumulative_args_t cum_v, enum machine_mode mode,
8215 const_tree type, bool named)
8217 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8219 if (targetm.calls.must_pass_in_stack (mode, type))
8222 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8223 wants to know about pass-by-reference semantics for incoming
8228 if (TARGET_SHCOMPACT)
8230 cum->byref = shcompact_byref (cum, mode, type, named);
8231 return cum->byref != 0;
8238 sh_callee_copies (cumulative_args_t cum, enum machine_mode mode,
8239 const_tree type, bool named ATTRIBUTE_UNUSED)
8241 /* ??? How can it possibly be correct to return true only on the
8242 caller side of the equation? Is there someplace else in the
8243 sh backend that's magically producing the copies? */
8244 return (get_cumulative_args (cum)->outgoing
8245 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8246 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8250 sh_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8251 tree type, bool named ATTRIBUTE_UNUSED)
8253 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8257 && PASS_IN_REG_P (*cum, mode, type)
8258 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8259 && (ROUND_REG (*cum, mode)
8261 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8262 : ROUND_ADVANCE (int_size_in_bytes (type)))
8263 > NPARM_REGS (mode)))
8264 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8266 else if (!TARGET_SHCOMPACT
8267 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8268 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8270 return words * UNITS_PER_WORD;
8274 /* Define where to put the arguments to a function.
8275 Value is zero to push the argument on the stack,
8276 or a hard register in which to store the argument.
8278 MODE is the argument's machine mode.
8279 TYPE is the data type of the argument (as a tree).
8280 This is null for libcalls where that information may
8282 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8283 the preceding args and about the function being called.
8284 NAMED is nonzero if this argument is a named parameter
8285 (otherwise it is an extra parameter matching an ellipsis).
8287 On SH the first args are normally in registers
8288 and the rest are pushed. Any arg that starts within the first
8289 NPARM_REGS words is at least partially passed in a register unless
8290 its data type forbids. */
8293 sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode,
8294 const_tree type, bool named)
8296 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8298 if (! TARGET_SH5 && mode == VOIDmode)
8299 return GEN_INT (ca->renesas_abi ? 1 : 0);
8302 && PASS_IN_REG_P (*ca, mode, type)
8303 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8307 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8308 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8310 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8311 gen_rtx_REG (SFmode,
8313 + (ROUND_REG (*ca, mode) ^ 1)),
8315 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8316 gen_rtx_REG (SFmode,
8318 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8320 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8323 /* If the alignment of a DF value causes an SF register to be
8324 skipped, we will use that skipped register for the next SF
8326 if ((TARGET_HITACHI || ca->renesas_abi)
8327 && ca->free_single_fp_reg
8329 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8331 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8332 ^ (mode == SFmode && TARGET_SH4
8333 && TARGET_LITTLE_ENDIAN != 0
8334 && ! TARGET_HITACHI && ! ca->renesas_abi);
8335 return gen_rtx_REG (mode, regno);
8341 if (mode == VOIDmode && TARGET_SHCOMPACT)
8342 return GEN_INT (ca->call_cookie);
8344 /* The following test assumes unnamed arguments are promoted to
8346 if (mode == SFmode && ca->free_single_fp_reg)
8347 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8349 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8350 && (named || ! ca->prototype_p)
8351 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8353 if (! ca->prototype_p && TARGET_SHMEDIA)
8354 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8356 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8358 + ca->arg_count[(int) SH_ARG_FLOAT]);
8361 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8362 && (! TARGET_SHCOMPACT
8363 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8364 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8367 return gen_rtx_REG (mode, (FIRST_PARM_REG
8368 + ca->arg_count[(int) SH_ARG_INT]));
8377 /* Update the data in CUM to advance over an argument
8378 of mode MODE and data type TYPE.
8379 (TYPE is null for libcalls where that information may not be
8383 sh_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode,
8384 const_tree type, bool named)
8386 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8390 else if (TARGET_SH5)
8392 const_tree type2 = (ca->byref && type
8395 enum machine_mode mode2 = (ca->byref && type
8398 int dwords = ((ca->byref
8401 ? int_size_in_bytes (type2)
8402 : GET_MODE_SIZE (mode2)) + 7) / 8;
8403 int numregs = MIN (dwords, NPARM_REGS (SImode)
8404 - ca->arg_count[(int) SH_ARG_INT]);
8408 ca->arg_count[(int) SH_ARG_INT] += numregs;
8409 if (TARGET_SHCOMPACT
8410 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8413 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8415 /* N.B. We want this also for outgoing. */
8416 ca->stack_regs += numregs;
8421 ca->stack_regs += numregs;
8422 ca->byref_regs += numregs;
8426 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8430 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8433 else if (dwords > numregs)
8435 int pushregs = numregs;
8437 if (TARGET_SHCOMPACT)
8438 ca->stack_regs += numregs;
8439 while (pushregs < NPARM_REGS (SImode) - 1
8440 && (CALL_COOKIE_INT_REG_GET
8442 NPARM_REGS (SImode) - pushregs)
8446 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8450 if (numregs == NPARM_REGS (SImode))
8452 |= CALL_COOKIE_INT_REG (0, 1)
8453 | CALL_COOKIE_STACKSEQ (numregs - 1);
8456 |= CALL_COOKIE_STACKSEQ (numregs);
8459 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8460 && (named || ! ca->prototype_p))
8462 if (mode2 == SFmode && ca->free_single_fp_reg)
8463 ca->free_single_fp_reg = 0;
8464 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8465 < NPARM_REGS (SFmode))
8468 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8470 - ca->arg_count[(int) SH_ARG_FLOAT]);
8472 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8474 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8476 if (ca->outgoing && numregs > 0)
8480 |= (CALL_COOKIE_INT_REG
8481 (ca->arg_count[(int) SH_ARG_INT]
8482 - numregs + ((numfpregs - 2) / 2),
8483 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8486 while (numfpregs -= 2);
8488 else if (mode2 == SFmode && (named)
8489 && (ca->arg_count[(int) SH_ARG_FLOAT]
8490 < NPARM_REGS (SFmode)))
8491 ca->free_single_fp_reg
8492 = FIRST_FP_PARM_REG - numfpregs
8493 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8499 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8501 /* Note that we've used the skipped register. */
8502 if (mode == SFmode && ca->free_single_fp_reg)
8504 ca->free_single_fp_reg = 0;
8507 /* When we have a DF after an SF, there's an SF register that get
8508 skipped in order to align the DF value. We note this skipped
8509 register, because the next SF value will use it, and not the
8510 SF that follows the DF. */
8512 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8514 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8515 + BASE_ARG_REG (mode));
8519 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8520 || PASS_IN_REG_P (*ca, mode, type))
8521 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8522 = (ROUND_REG (*ca, mode)
8524 ? ROUND_ADVANCE (int_size_in_bytes (type))
8525 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8528 /* The Renesas calling convention doesn't quite fit into this scheme since
8529 the address is passed like an invisible argument, but one that is always
8530 passed in memory. */
8532 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8534 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8536 return gen_rtx_REG (Pmode, 2);
8539 /* Worker function for TARGET_FUNCTION_VALUE.
8541 For the SH, this is like LIBCALL_VALUE, except that we must change the
8542 mode like PROMOTE_MODE does.
8543 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8544 tested here has to be kept in sync with the one in explow.c:promote_mode.
8548 sh_function_value (const_tree valtype,
8549 const_tree fn_decl_or_type,
8550 bool outgoing ATTRIBUTE_UNUSED)
8553 && !DECL_P (fn_decl_or_type))
8554 fn_decl_or_type = NULL;
8556 return gen_rtx_REG (
8557 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8558 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8559 && (TREE_CODE (valtype) == INTEGER_TYPE
8560 || TREE_CODE (valtype) == ENUMERAL_TYPE
8561 || TREE_CODE (valtype) == BOOLEAN_TYPE
8562 || TREE_CODE (valtype) == REAL_TYPE
8563 || TREE_CODE (valtype) == OFFSET_TYPE))
8564 && sh_promote_prototypes (fn_decl_or_type)
8565 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8566 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8569 /* Worker function for TARGET_LIBCALL_VALUE. */
8572 sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8574 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8577 /* Return true if N is a possible register number of function value. */
8580 sh_function_value_regno_p (const unsigned int regno)
8582 return ((regno) == FIRST_RET_REG
8583 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8584 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8587 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8590 sh_return_in_memory (const_tree type, const_tree fndecl)
8594 if (TYPE_MODE (type) == BLKmode)
8595 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8597 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8601 return (TYPE_MODE (type) == BLKmode
8602 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8603 && TREE_CODE (type) == RECORD_TYPE));
8607 /* We actually emit the code in sh_expand_prologue. We used to use
8608 a static variable to flag that we need to emit this code, but that
8609 doesn't when inlining, when functions are deferred and then emitted
8610 later. Fortunately, we already have two flags that are part of struct
8611 function that tell if a function uses varargs or stdarg. */
8613 sh_setup_incoming_varargs (cumulative_args_t ca,
8614 enum machine_mode mode,
8616 int *pretend_arg_size,
8617 int second_time ATTRIBUTE_UNUSED)
8619 gcc_assert (cfun->stdarg);
8620 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8622 int named_parm_regs, anon_parm_regs;
8624 named_parm_regs = (ROUND_REG (*get_cumulative_args (ca), mode)
8626 ? ROUND_ADVANCE (int_size_in_bytes (type))
8627 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8628 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8629 if (anon_parm_regs > 0)
8630 *pretend_arg_size = anon_parm_regs * 4;
8635 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
8641 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
8643 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8645 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8649 /* Define the offset between two registers, one to be eliminated, and
8650 the other its replacement, at the start of a routine. */
8653 initial_elimination_offset (int from, int to)
8656 int regs_saved_rounding = 0;
8657 int total_saved_regs_space;
8658 int total_auto_space;
8659 int save_flags = target_flags;
8661 HARD_REG_SET live_regs_mask;
8663 shmedia_space_reserved_for_target_registers = false;
8664 regs_saved = calc_live_regs (&live_regs_mask);
8665 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8667 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8669 shmedia_space_reserved_for_target_registers = true;
8670 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8673 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8674 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8675 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8677 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8678 copy_flags = target_flags;
8679 target_flags = save_flags;
8681 total_saved_regs_space = regs_saved + regs_saved_rounding;
8683 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8684 return total_saved_regs_space + total_auto_space
8685 + crtl->args.info.byref_regs * 8;
8687 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8688 return total_saved_regs_space + total_auto_space
8689 + crtl->args.info.byref_regs * 8;
8691 /* Initial gap between fp and sp is 0. */
8692 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8695 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8696 return rounded_frame_size (0);
8698 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8699 return rounded_frame_size (0);
8701 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8702 && (to == HARD_FRAME_POINTER_REGNUM
8703 || to == STACK_POINTER_REGNUM));
8706 int n = total_saved_regs_space;
8707 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8708 save_schedule schedule;
8711 n += total_auto_space;
8713 /* If it wasn't saved, there's not much we can do. */
8714 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8717 target_flags = copy_flags;
8719 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8720 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8721 if (entry->reg == pr_reg)
8723 target_flags = save_flags;
8724 return entry->offset;
8729 return total_auto_space;
8732 /* Parse the -mfixed-range= option string. */
8734 sh_fix_range (const char *const_str)
8737 char *str, *dash, *comma;
8739 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8740 REG2 are either register names or register numbers. The effect
8741 of this option is to mark the registers in the range from REG1 to
8742 REG2 as ``fixed'' so they won't be used by the compiler. */
8744 i = strlen (const_str);
8745 str = (char *) alloca (i + 1);
8746 memcpy (str, const_str, i + 1);
8750 dash = strchr (str, '-');
8753 warning (0, "value of -mfixed-range must have form REG1-REG2");
8757 comma = strchr (dash + 1, ',');
8761 first = decode_reg_name (str);
8764 warning (0, "unknown register name: %s", str);
8768 last = decode_reg_name (dash + 1);
8771 warning (0, "unknown register name: %s", dash + 1);
8779 warning (0, "%s-%s is an empty range", str, dash + 1);
8783 for (i = first; i <= last; ++i)
8784 fixed_regs[i] = call_used_regs[i] = 1;
8794 /* Insert any deferred function attributes from earlier pragmas. */
8796 sh_insert_attributes (tree node, tree *attributes)
8800 if (TREE_CODE (node) != FUNCTION_DECL)
8803 /* We are only interested in fields. */
8807 /* Append the attributes to the deferred attributes. */
8808 *sh_deferred_function_attributes_tail = *attributes;
8809 attrs = sh_deferred_function_attributes;
8813 /* Some attributes imply or require the interrupt attribute. */
8814 if (!lookup_attribute ("interrupt_handler", attrs)
8815 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8817 /* If we have a trapa_handler, but no interrupt_handler attribute,
8818 insert an interrupt_handler attribute. */
8819 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8820 /* We can't use sh_pr_interrupt here because that's not in the
8823 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8824 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8825 if the interrupt attribute is missing, we ignore the attribute
8827 else if (lookup_attribute ("sp_switch", attrs)
8828 || lookup_attribute ("trap_exit", attrs)
8829 || lookup_attribute ("nosave_low_regs", attrs)
8830 || lookup_attribute ("resbank", attrs))
8834 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8836 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8837 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8838 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8839 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8840 warning (OPT_Wattributes,
8841 "%qE attribute only applies to interrupt functions",
8842 TREE_PURPOSE (attrs));
8845 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8847 tail = &TREE_CHAIN (*tail);
8850 attrs = *attributes;
8854 /* Install the processed list. */
8855 *attributes = attrs;
8857 /* Clear deferred attributes. */
8858 sh_deferred_function_attributes = NULL_TREE;
8859 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8864 /* Supported attributes:
8866 interrupt_handler -- specifies this function is an interrupt handler.
8868 trapa_handler - like above, but don't save all registers.
8870 sp_switch -- specifies an alternate stack for an interrupt handler
8873 trap_exit -- use a trapa to exit an interrupt function instead of
8876 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8877 This is useful on the SH3 and upwards,
8878 which has a separate set of low regs for User and Supervisor modes.
8879 This should only be used for the lowest level of interrupts. Higher levels
8880 of interrupts must save the registers in case they themselves are
8883 renesas -- use Renesas calling/layout conventions (functions and
8886 resbank -- In case of an ISR, use a register bank to save registers
8887 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8890 /* Handle a 'resbank' attribute. */
8892 sh_handle_resbank_handler_attribute (tree * node, tree name,
8893 tree args ATTRIBUTE_UNUSED,
8894 int flags ATTRIBUTE_UNUSED,
8895 bool * no_add_attrs)
8899 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8901 *no_add_attrs = true;
8903 if (TREE_CODE (*node) != FUNCTION_DECL)
8905 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8907 *no_add_attrs = true;
8913 /* Handle an "interrupt_handler" attribute; arguments as in
8914 struct attribute_spec.handler. */
8916 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8917 tree args ATTRIBUTE_UNUSED,
8918 int flags ATTRIBUTE_UNUSED,
8921 if (TREE_CODE (*node) != FUNCTION_DECL)
8923 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8925 *no_add_attrs = true;
8927 else if (TARGET_SHCOMPACT)
8929 error ("attribute interrupt_handler is not compatible with -m5-compact");
8930 *no_add_attrs = true;
8936 /* Handle an 'function_vector' attribute; arguments as in
8937 struct attribute_spec.handler. */
8939 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8940 tree args ATTRIBUTE_UNUSED,
8941 int flags ATTRIBUTE_UNUSED,
8942 bool * no_add_attrs)
8946 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8948 *no_add_attrs = true;
8950 else if (TREE_CODE (*node) != FUNCTION_DECL)
8952 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8954 *no_add_attrs = true;
8956 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8958 /* The argument must be a constant integer. */
8959 warning (OPT_Wattributes,
8960 "%qE attribute argument not an integer constant",
8962 *no_add_attrs = true;
8964 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8966 /* The argument value must be between 0 to 255. */
8967 warning (OPT_Wattributes,
8968 "%qE attribute argument should be between 0 to 255",
8970 *no_add_attrs = true;
8975 /* Returns 1 if current function has been assigned the attribute
8976 'function_vector'. */
8978 sh2a_is_function_vector_call (rtx x)
8980 if (GET_CODE (x) == SYMBOL_REF
8981 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8983 tree tr = SYMBOL_REF_DECL (x);
8985 if (sh2a_function_vector_p (tr))
8992 /* Returns the function vector number, if the attribute
8993 'function_vector' is assigned, otherwise returns zero. */
8995 sh2a_get_function_vector_number (rtx x)
9000 if ((GET_CODE (x) == SYMBOL_REF)
9001 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9003 t = SYMBOL_REF_DECL (x);
9005 if (TREE_CODE (t) != FUNCTION_DECL)
9008 list = SH_ATTRIBUTES (t);
9011 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9013 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
9017 list = TREE_CHAIN (list);
9026 /* Handle an "sp_switch" attribute; arguments as in
9027 struct attribute_spec.handler. */
9029 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
9030 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9032 if (TREE_CODE (*node) != FUNCTION_DECL)
9034 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9036 *no_add_attrs = true;
9038 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
9040 /* The argument must be a constant string. */
9041 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
9043 *no_add_attrs = true;
9049 /* Handle an "trap_exit" attribute; arguments as in
9050 struct attribute_spec.handler. */
9052 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
9053 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9055 if (TREE_CODE (*node) != FUNCTION_DECL)
9057 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9059 *no_add_attrs = true;
9061 /* The argument specifies a trap number to be used in a trapa instruction
9062 at function exit (instead of an rte instruction). */
9063 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9065 /* The argument must be a constant integer. */
9066 warning (OPT_Wattributes, "%qE attribute argument not an "
9067 "integer constant", name);
9068 *no_add_attrs = true;
9075 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
9076 tree name ATTRIBUTE_UNUSED,
9077 tree args ATTRIBUTE_UNUSED,
9078 int flags ATTRIBUTE_UNUSED,
9079 bool *no_add_attrs ATTRIBUTE_UNUSED)
9084 /* True if __attribute__((renesas)) or -mrenesas. */
9086 sh_attr_renesas_p (const_tree td)
9093 td = TREE_TYPE (td);
9094 if (td == error_mark_node)
9096 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
9100 /* True if __attribute__((renesas)) or -mrenesas, for the current
9103 sh_cfun_attr_renesas_p (void)
9105 return sh_attr_renesas_p (current_function_decl);
9109 sh_cfun_interrupt_handler_p (void)
9111 return (lookup_attribute ("interrupt_handler",
9112 DECL_ATTRIBUTES (current_function_decl))
9116 /* Returns 1 if FUNC has been assigned the attribute
9117 "function_vector". */
9119 sh2a_function_vector_p (tree func)
9122 if (TREE_CODE (func) != FUNCTION_DECL)
9125 list = SH_ATTRIBUTES (func);
9128 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9131 list = TREE_CHAIN (list);
9136 /* Returns TRUE if given tree has the "resbank" attribute. */
9139 sh_cfun_resbank_handler_p (void)
9141 return ((lookup_attribute ("resbank",
9142 DECL_ATTRIBUTES (current_function_decl))
9144 && (lookup_attribute ("interrupt_handler",
9145 DECL_ATTRIBUTES (current_function_decl))
9146 != NULL_TREE) && TARGET_SH2A);
9149 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9152 sh_check_pch_target_flags (int old_flags)
9154 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9155 | MASK_SH_E | MASK_HARD_SH4
9156 | MASK_FPU_SINGLE | MASK_SH4))
9157 return _("created and used with different architectures / ABIs");
9158 if ((old_flags ^ target_flags) & MASK_HITACHI)
9159 return _("created and used with different ABIs");
9160 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9161 return _("created and used with different endianness");
9165 /* Predicates used by the templates. */
9167 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9168 Used only in general_movsrc_operand. */
9171 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9183 /* Nonzero if OP is a floating point value with value 0.0. */
9186 fp_zero_operand (rtx op)
9190 if (GET_MODE (op) != SFmode)
9193 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9194 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
9197 /* Nonzero if OP is a floating point value with value 1.0. */
9200 fp_one_operand (rtx op)
9204 if (GET_MODE (op) != SFmode)
9207 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9208 return REAL_VALUES_EQUAL (r, dconst1);
9211 /* In general mode switching is used. If we are
9212 compiling without -mfmovd, movsf_ie isn't taken into account for
9213 mode switching. We could check in machine_dependent_reorg for
9214 cases where we know we are in single precision mode, but there is
9215 interface to find that out during reload, so we must avoid
9216 choosing an fldi alternative during reload and thus failing to
9217 allocate a scratch register for the constant loading. */
9224 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9226 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9228 if (GET_CODE (op) != SYMBOL_REF)
9229 return TLS_MODEL_NONE;
9230 return SYMBOL_REF_TLS_MODEL (op);
9233 /* Return the destination address of a branch. */
9236 branch_dest (rtx branch)
9238 rtx dest = SET_SRC (PATTERN (branch));
9241 if (GET_CODE (dest) == IF_THEN_ELSE)
9242 dest = XEXP (dest, 1);
9243 dest = XEXP (dest, 0);
9244 dest_uid = INSN_UID (dest);
9245 return INSN_ADDRESSES (dest_uid);
9248 /* Return nonzero if REG is not used after INSN.
9249 We assume REG is a reload reg, and therefore does
9250 not live past labels. It may live past calls or jumps though. */
9252 reg_unused_after (rtx reg, rtx insn)
9257 /* If the reg is set by this instruction, then it is safe for our
9258 case. Disregard the case where this is a store to memory, since
9259 we are checking a register used in the store address. */
9260 set = single_set (insn);
9261 if (set && !MEM_P (SET_DEST (set))
9262 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9265 while ((insn = NEXT_INSN (insn)))
9271 code = GET_CODE (insn);
9274 /* If this is a label that existed before reload, then the register
9275 is dead here. However, if this is a label added by reorg, then
9276 the register may still be live here. We can't tell the difference,
9277 so we just ignore labels completely. */
9278 if (code == CODE_LABEL)
9283 if (code == JUMP_INSN)
9286 /* If this is a sequence, we must handle them all at once.
9287 We could have for instance a call that sets the target register,
9288 and an insn in a delay slot that uses the register. In this case,
9289 we must return 0. */
9290 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9295 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9297 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9298 rtx set = single_set (this_insn);
9300 if (CALL_P (this_insn))
9302 else if (JUMP_P (this_insn))
9304 if (INSN_ANNULLED_BRANCH_P (this_insn))
9309 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9311 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9313 if (!MEM_P (SET_DEST (set)))
9319 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9324 else if (code == JUMP_INSN)
9328 set = single_set (insn);
9329 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9331 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9332 return !MEM_P (SET_DEST (set));
9333 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9336 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9344 static GTY(()) rtx fpscr_rtx;
9346 get_fpscr_rtx (void)
9350 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9351 REG_USERVAR_P (fpscr_rtx) = 1;
9352 mark_user_reg (fpscr_rtx);
9354 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9355 mark_user_reg (fpscr_rtx);
9359 static GTY(()) tree fpscr_values;
9362 emit_fpu_switch (rtx scratch, int index)
9366 if (fpscr_values == NULL)
9370 t = build_index_type (integer_one_node);
9371 t = build_array_type (integer_type_node, t);
9372 t = build_decl (BUILTINS_LOCATION,
9373 VAR_DECL, get_identifier ("__fpscr_values"), t);
9374 DECL_ARTIFICIAL (t) = 1;
9375 DECL_IGNORED_P (t) = 1;
9376 DECL_EXTERNAL (t) = 1;
9377 TREE_STATIC (t) = 1;
9378 TREE_PUBLIC (t) = 1;
9384 src = DECL_RTL (fpscr_values);
9385 if (!can_create_pseudo_p ())
9387 emit_move_insn (scratch, XEXP (src, 0));
9389 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9390 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9393 src = adjust_address (src, PSImode, index * 4);
9395 dst = get_fpscr_rtx ();
9396 emit_move_insn (dst, src);
9400 emit_sf_insn (rtx pat)
9406 emit_df_insn (rtx pat)
9412 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9414 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9418 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9420 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9425 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9427 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9431 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9433 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9437 static rtx get_free_reg (HARD_REG_SET);
9439 /* This function returns a register to use to load the address to load
9440 the fpscr from. Currently it always returns r1 or r7, but when we are
9441 able to use pseudo registers after combine, or have a better mechanism
9442 for choosing a register, it should be done here. */
9443 /* REGS_LIVE is the liveness information for the point for which we
9444 need this allocation. In some bare-bones exit blocks, r1 is live at the
9445 start. We can even have all of r0..r3 being live:
9446 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9447 INSN before which new insns are placed with will clobber the register
9448 we return. If a basic block consists only of setting the return value
9449 register to a pseudo and using that register, the return value is not
9450 live before or after this block, yet we we'll insert our insns right in
9454 get_free_reg (HARD_REG_SET regs_live)
9456 if (! TEST_HARD_REG_BIT (regs_live, 1))
9457 return gen_rtx_REG (Pmode, 1);
9459 /* Hard reg 1 is live; since this is a small register classes target,
9460 there shouldn't be anything but a jump before the function end. */
9461 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9462 return gen_rtx_REG (Pmode, 7);
9465 /* This function will set the fpscr from memory.
9466 MODE is the mode we are setting it to. */
9468 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9470 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9471 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9474 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9475 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9478 /* Is the given character a logical line separator for the assembler? */
9479 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9480 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9484 sh_insn_length_adjustment (rtx insn)
9486 /* Instructions with unfilled delay slots take up an extra two bytes for
9487 the nop in the delay slot. */
9488 if (((NONJUMP_INSN_P (insn)
9489 && GET_CODE (PATTERN (insn)) != USE
9490 && GET_CODE (PATTERN (insn)) != CLOBBER)
9492 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9493 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9494 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9497 /* SH2e has a bug that prevents the use of annulled branches, so if
9498 the delay slot is not filled, we'll have to put a NOP in it. */
9499 if (sh_cpu_attr == CPU_SH2E
9500 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
9501 && get_attr_type (insn) == TYPE_CBRANCH
9502 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9505 /* sh-dsp parallel processing insn take four bytes instead of two. */
9507 if (NONJUMP_INSN_P (insn))
9510 rtx body = PATTERN (insn);
9513 int maybe_label = 1;
9515 if (GET_CODE (body) == ASM_INPUT)
9516 templ = XSTR (body, 0);
9517 else if (asm_noperands (body) >= 0)
9519 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9528 while (c == ' ' || c == '\t');
9529 /* all sh-dsp parallel-processing insns start with p.
9530 The only non-ppi sh insn starting with p is pref.
9531 The only ppi starting with pr is prnd. */
9532 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9534 /* The repeat pseudo-insn expands two three insns, a total of
9535 six bytes in size. */
9536 else if ((c == 'r' || c == 'R')
9537 && ! strncasecmp ("epeat", templ, 5))
9539 while (c && c != '\n'
9540 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9542 /* If this is a label, it is obviously not a ppi insn. */
9543 if (c == ':' && maybe_label)
9548 else if (c == '\'' || c == '"')
9553 maybe_label = c != ':';
9561 /* Return TRUE for a valid displacement for the REG+disp addressing
9564 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9565 into the FRx registers. We implement this by setting the maximum offset
9566 to zero when the value is SFmode. This also restricts loading of SFmode
9567 values into the integer registers, but that can't be helped. */
9569 /* The SH allows a displacement in a QI or HI amode, but only when the
9570 other operand is R0. GCC doesn't handle this very well, so we forgot
9573 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9574 DI can be any number 0..60. */
9577 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9579 if (CONST_INT_P (op))
9585 /* Check if this is the address of an unaligned load / store. */
9586 if (mode == VOIDmode)
9587 return CONST_OK_FOR_I06 (INTVAL (op));
9589 size = GET_MODE_SIZE (mode);
9590 return (!(INTVAL (op) & (size - 1))
9591 && INTVAL (op) >= -512 * size
9592 && INTVAL (op) < 512 * size);
9597 if (GET_MODE_SIZE (mode) == 1
9598 && (unsigned) INTVAL (op) < 4096)
9602 if ((GET_MODE_SIZE (mode) == 4
9603 && (unsigned) INTVAL (op) < 64
9604 && !(INTVAL (op) & 3)
9605 && !(TARGET_SH2E && mode == SFmode))
9606 || (GET_MODE_SIZE (mode) == 4
9607 && (unsigned) INTVAL (op) < 16383
9608 && !(INTVAL (op) & 3) && TARGET_SH2A))
9611 if ((GET_MODE_SIZE (mode) == 8
9612 && (unsigned) INTVAL (op) < 60
9613 && !(INTVAL (op) & 3)
9614 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9615 || ((GET_MODE_SIZE (mode)==8)
9616 && (unsigned) INTVAL (op) < 8192
9617 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9618 && (TARGET_SH2A && mode == DFmode)))
9625 /* Recognize an RTL expression that is a valid memory address for
9627 The MODE argument is the machine mode for the MEM expression
9628 that wants to use this address.
9636 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9638 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9640 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9642 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9644 else if (GET_CODE (x) == PLUS
9645 && (mode != PSImode || reload_completed))
9647 rtx xop0 = XEXP (x, 0);
9648 rtx xop1 = XEXP (x, 1);
9650 if (GET_MODE_SIZE (mode) <= 8
9651 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9652 && sh_legitimate_index_p (mode, xop1))
9655 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9656 || ((xop0 == stack_pointer_rtx
9657 || xop0 == hard_frame_pointer_rtx)
9658 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9659 || ((xop1 == stack_pointer_rtx
9660 || xop1 == hard_frame_pointer_rtx)
9661 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9662 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9663 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9664 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9665 && TARGET_FMOVD && mode == DFmode)))
9667 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9668 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9670 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9671 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9679 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9680 isn't protected by a PIC unspec. */
9682 nonpic_symbol_mentioned_p (rtx x)
9684 register const char *fmt;
9687 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9688 || GET_CODE (x) == PC)
9691 /* We don't want to look into the possible MEM location of a
9692 CONST_DOUBLE, since we're not going to use it, in general. */
9693 if (GET_CODE (x) == CONST_DOUBLE)
9696 if (GET_CODE (x) == UNSPEC
9697 && (XINT (x, 1) == UNSPEC_PIC
9698 || XINT (x, 1) == UNSPEC_GOT
9699 || XINT (x, 1) == UNSPEC_GOTOFF
9700 || XINT (x, 1) == UNSPEC_GOTPLT
9701 || XINT (x, 1) == UNSPEC_GOTTPOFF
9702 || XINT (x, 1) == UNSPEC_DTPOFF
9703 || XINT (x, 1) == UNSPEC_TPOFF
9704 || XINT (x, 1) == UNSPEC_PLT
9705 || XINT (x, 1) == UNSPEC_SYMOFF
9706 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9709 fmt = GET_RTX_FORMAT (GET_CODE (x));
9710 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9716 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9717 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9720 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9727 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9728 @GOTOFF in `reg'. */
9730 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9733 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9736 if (GET_CODE (orig) == LABEL_REF
9737 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9740 reg = gen_reg_rtx (Pmode);
9742 emit_insn (gen_symGOTOFF2reg (reg, orig));
9745 else if (GET_CODE (orig) == SYMBOL_REF)
9748 reg = gen_reg_rtx (Pmode);
9750 emit_insn (gen_symGOT2reg (reg, orig));
9756 /* Try machine-dependent ways of modifying an illegitimate address
9757 to be legitimate. If we find one, return the new, valid address.
9758 Otherwise, return X.
9760 For the SH, if X is almost suitable for indexing, but the offset is
9761 out of range, convert it into a normal form so that CSE has a chance
9762 of reducing the number of address registers used. */
9765 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9768 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9770 if (GET_CODE (x) == PLUS
9771 && (GET_MODE_SIZE (mode) == 4
9772 || GET_MODE_SIZE (mode) == 8)
9773 && CONST_INT_P (XEXP (x, 1))
9774 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9776 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9777 && ! (TARGET_SH2E && mode == SFmode))
9779 rtx index_rtx = XEXP (x, 1);
9780 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9783 /* On rare occasions, we might get an unaligned pointer
9784 that is indexed in a way to give an aligned address.
9785 Therefore, keep the lower two bits in offset_base. */
9786 /* Instead of offset_base 128..131 use 124..127, so that
9787 simple add suffices. */
9789 offset_base = ((offset + 4) & ~60) - 4;
9791 offset_base = offset & ~60;
9793 /* Sometimes the normal form does not suit DImode. We
9794 could avoid that by using smaller ranges, but that
9795 would give less optimized code when SImode is
9797 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9799 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9800 GEN_INT (offset_base), NULL_RTX, 0,
9803 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9810 /* Attempt to replace *P, which is an address that needs reloading, with
9811 a valid memory address for an operand of mode MODE.
9812 Like for sh_legitimize_address, for the SH we try to get a normal form
9813 of the address. That will allow inheritance of the address reloads. */
9816 sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9819 enum reload_type type = (enum reload_type) itype;
9821 if (GET_CODE (*p) == PLUS
9822 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9823 && CONST_INT_P (XEXP (*p, 1))
9824 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
9826 && ! (TARGET_SH4 && mode == DFmode)
9827 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9828 && (ALLOW_INDEXED_ADDRESS
9829 || XEXP (*p, 0) == stack_pointer_rtx
9830 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9832 rtx index_rtx = XEXP (*p, 1);
9833 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9836 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9838 push_reload (*p, NULL_RTX, p, NULL,
9839 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9842 if (TARGET_SH2E && mode == SFmode)
9845 push_reload (*p, NULL_RTX, p, NULL,
9846 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9849 /* Instead of offset_base 128..131 use 124..127, so that
9850 simple add suffices. */
9852 offset_base = ((offset + 4) & ~60) - 4;
9854 offset_base = offset & ~60;
9855 /* Sometimes the normal form does not suit DImode. We could avoid
9856 that by using smaller ranges, but that would give less optimized
9857 code when SImode is prevalent. */
9858 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9860 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9861 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9862 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9863 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9867 /* We must re-recognize what we created before. */
9868 else if (GET_CODE (*p) == PLUS
9869 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9870 && GET_CODE (XEXP (*p, 0)) == PLUS
9871 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9872 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9873 && CONST_INT_P (XEXP (*p, 1))
9875 && ! (TARGET_SH2E && mode == SFmode))
9877 /* Because this address is so complex, we know it must have
9878 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9879 it is already unshared, and needs no further unsharing. */
9880 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9881 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9891 /* In the name of slightly smaller debug output, and to cater to
9892 general assembler lossage, recognize various UNSPEC sequences
9893 and turn them back into a direct symbol reference. */
9896 sh_delegitimize_address (rtx orig_x)
9900 orig_x = delegitimize_mem_from_attrs (orig_x);
9905 if (GET_CODE (x) == CONST)
9908 if (GET_CODE (y) == UNSPEC)
9910 if (XINT (y, 1) == UNSPEC_GOT
9911 || XINT (y, 1) == UNSPEC_GOTOFF
9912 || XINT (y, 1) == UNSPEC_SYMOFF)
9913 return XVECEXP (y, 0, 0);
9914 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
9916 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
9918 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
9920 if (GET_CODE (symplt) == UNSPEC
9921 && XINT (symplt, 1) == UNSPEC_PLT)
9922 return XVECEXP (symplt, 0, 0);
9925 else if (TARGET_SHMEDIA
9926 && (XINT (y, 1) == UNSPEC_EXTRACT_S16
9927 || XINT (y, 1) == UNSPEC_EXTRACT_U16))
9929 rtx offset = XVECEXP (y, 0, 1);
9931 x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset);
9933 x = replace_equiv_address_nv (orig_x, x);
9942 /* Mark the use of a constant in the literal table. If the constant
9943 has multiple labels, make it unique. */
9945 mark_constant_pool_use (rtx x)
9947 rtx insn, lab, pattern;
9952 switch (GET_CODE (x))
9962 /* Get the first label in the list of labels for the same constant
9963 and delete another labels in the list. */
9965 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9968 || LABEL_REFS (insn) != NEXT_INSN (insn))
9973 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9974 INSN_DELETED_P (insn) = 1;
9976 /* Mark constants in a window. */
9977 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9979 if (!NONJUMP_INSN_P (insn))
9982 pattern = PATTERN (insn);
9983 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9986 switch (XINT (pattern, 1))
9988 case UNSPECV_CONST2:
9989 case UNSPECV_CONST4:
9990 case UNSPECV_CONST8:
9991 XVECEXP (pattern, 0, 1) = const1_rtx;
9993 case UNSPECV_WINDOW_END:
9994 if (XVECEXP (pattern, 0, 0) == x)
9997 case UNSPECV_CONST_END:
10007 /* Return true if it's possible to redirect BRANCH1 to the destination
10008 of an unconditional jump BRANCH2. We only want to do this if the
10009 resulting branch will have a short displacement. */
10011 sh_can_redirect_branch (rtx branch1, rtx branch2)
10013 if (flag_expensive_optimizations && simplejump_p (branch2))
10015 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
10019 for (distance = 0, insn = NEXT_INSN (branch1);
10020 insn && distance < 256;
10021 insn = PREV_INSN (insn))
10026 distance += get_attr_length (insn);
10028 for (distance = 0, insn = NEXT_INSN (branch1);
10029 insn && distance < 256;
10030 insn = NEXT_INSN (insn))
10035 distance += get_attr_length (insn);
10041 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10043 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
10044 unsigned int new_reg)
10046 /* Interrupt functions can only use registers that have already been
10047 saved by the prologue, even if they would normally be
10050 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
10056 /* Function to update the integer COST
10057 based on the relationship between INSN that is dependent on
10058 DEP_INSN through the dependence LINK. The default is to make no
10059 adjustment to COST. This can be used for example to specify to
10060 the scheduler that an output- or anti-dependence does not incur
10061 the same cost as a data-dependence. The return value should be
10062 the new value for COST. */
10064 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
10068 if (TARGET_SHMEDIA)
10070 /* On SHmedia, if the dependence is an anti-dependence or
10071 output-dependence, there is no cost. */
10072 if (REG_NOTE_KIND (link) != 0)
10074 /* However, dependencies between target register loads and
10075 uses of the register in a subsequent block that are separated
10076 by a conditional branch are not modelled - we have to do with
10077 the anti-dependency between the target register load and the
10078 conditional branch that ends the current block. */
10079 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
10080 && GET_CODE (PATTERN (dep_insn)) == SET
10081 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
10082 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
10083 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
10085 int orig_cost = cost;
10086 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
10087 rtx target = ((! note
10088 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
10089 ? insn : JUMP_LABEL (insn));
10090 /* On the likely path, the branch costs 1, on the unlikely path,
10094 target = next_active_insn (target);
10095 while (target && ! flow_dependent_p (target, dep_insn)
10097 /* If two branches are executed in immediate succession, with the
10098 first branch properly predicted, this causes a stall at the
10099 second branch, hence we won't need the target for the
10100 second branch for two cycles after the launch of the first
10102 if (cost > orig_cost - 2)
10103 cost = orig_cost - 2;
10109 else if (get_attr_is_mac_media (insn)
10110 && get_attr_is_mac_media (dep_insn))
10113 else if (! reload_completed
10114 && GET_CODE (PATTERN (insn)) == SET
10115 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
10116 && GET_CODE (PATTERN (dep_insn)) == SET
10117 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
10120 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10121 that is needed at the target. */
10122 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
10123 && ! flow_dependent_p (insn, dep_insn))
10126 else if (REG_NOTE_KIND (link) == 0)
10128 enum attr_type type;
10131 if (recog_memoized (insn) < 0
10132 || recog_memoized (dep_insn) < 0)
10135 dep_set = single_set (dep_insn);
10137 /* The latency that we specify in the scheduling description refers
10138 to the actual output, not to an auto-increment register; for that,
10139 the latency is one. */
10140 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
10142 rtx set = single_set (insn);
10145 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
10146 && (!MEM_P (SET_DEST (set))
10147 || !reg_mentioned_p (SET_DEST (dep_set),
10148 XEXP (SET_DEST (set), 0))))
10151 /* The only input for a call that is timing-critical is the
10152 function's address. */
10155 rtx call = PATTERN (insn);
10157 if (GET_CODE (call) == PARALLEL)
10158 call = XVECEXP (call, 0 ,0);
10159 if (GET_CODE (call) == SET)
10160 call = SET_SRC (call);
10161 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
10162 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10163 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
10164 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
10165 cost -= TARGET_SH4_300 ? 3 : 6;
10167 /* Likewise, the most timing critical input for an sfuncs call
10168 is the function address. However, sfuncs typically start
10169 using their arguments pretty quickly.
10170 Assume a four cycle delay for SH4 before they are needed.
10171 Cached ST40-300 calls are quicker, so assume only a one
10173 ??? Maybe we should encode the delays till input registers
10174 are needed by sfuncs into the sfunc call insn. */
10175 /* All sfunc calls are parallels with at least four components.
10176 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10177 else if (GET_CODE (PATTERN (insn)) == PARALLEL
10178 && XVECLEN (PATTERN (insn), 0) >= 4
10179 && (reg = sfunc_uses_reg (insn)))
10181 if (! reg_set_p (reg, dep_insn))
10182 cost -= TARGET_SH4_300 ? 1 : 4;
10184 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
10186 enum attr_type dep_type = get_attr_type (dep_insn);
10188 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
10190 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
10191 && (type = get_attr_type (insn)) != TYPE_CALL
10192 && type != TYPE_SFUNC)
10194 /* When the preceding instruction loads the shift amount of
10195 the following SHAD/SHLD, the latency of the load is increased
10197 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10198 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
10199 && reg_overlap_mentioned_p (SET_DEST (dep_set),
10200 XEXP (SET_SRC (single_set (insn)),
10203 /* When an LS group instruction with a latency of less than
10204 3 cycles is followed by a double-precision floating-point
10205 instruction, FIPR, or FTRV, the latency of the first
10206 instruction is increased to 3 cycles. */
10208 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10209 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10211 /* The lsw register of a double-precision computation is ready one
10213 else if (reload_completed
10214 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10215 && (use_pat = single_set (insn))
10216 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10217 SET_SRC (use_pat)))
10220 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10221 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10224 else if (TARGET_SH4_300)
10226 /* Stores need their input register two cycles later. */
10227 if (dep_set && cost >= 1
10228 && ((type = get_attr_type (insn)) == TYPE_STORE
10229 || type == TYPE_PSTORE
10230 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10232 rtx set = single_set (insn);
10234 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10235 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10238 /* But don't reduce the cost below 1 if the address depends
10239 on a side effect of dep_insn. */
10241 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10247 /* An anti-dependence penalty of two applies if the first insn is a double
10248 precision fadd / fsub / fmul. */
10249 else if (!TARGET_SH4_300
10250 && REG_NOTE_KIND (link) == REG_DEP_ANTI
10251 && recog_memoized (dep_insn) >= 0
10252 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10253 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
10254 /* A lot of alleged anti-flow dependences are fake,
10255 so check this one is real. */
10256 && flow_dependent_p (dep_insn, insn))
10262 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10263 if DEP_INSN is anti-flow dependent on INSN. */
10265 flow_dependent_p (rtx insn, rtx dep_insn)
10267 rtx tmp = PATTERN (insn);
10269 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10270 return tmp == NULL_RTX;
10273 /* A helper function for flow_dependent_p called through note_stores. */
10275 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10277 rtx * pinsn = (rtx *) data;
10279 if (*pinsn && reg_referenced_p (x, *pinsn))
10283 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10284 'special function' patterns (type sfunc) that clobber pr, but that
10285 do not look like function calls to leaf_function_p. Hence we must
10286 do this extra check. */
10288 sh_pr_n_sets (void)
10290 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10293 /* Return where to allocate pseudo for a given hard register initial
10296 sh_allocate_initial_value (rtx hard_reg)
10300 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10302 if (current_function_is_leaf
10303 && ! sh_pr_n_sets ()
10304 && ! (TARGET_SHCOMPACT
10305 && ((crtl->args.info.call_cookie
10306 & ~ CALL_COOKIE_RET_TRAMP (1))
10307 || crtl->saves_all_registers)))
10310 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
10318 /* This function returns "2" to indicate dual issue for the SH4
10319 processor. To be used by the DFA pipeline description. */
10321 sh_issue_rate (void)
10323 if (TARGET_SUPERSCALAR)
10329 /* Functions for ready queue reordering for sched1. */
10331 /* Get weight for mode for a set x. */
10333 find_set_regmode_weight (rtx x, enum machine_mode mode)
10335 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10337 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10339 if (REG_P (SET_DEST (x)))
10341 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10351 /* Get regmode weight for insn. */
10353 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
10355 short reg_weight = 0;
10358 /* Increment weight for each register born here. */
10359 x = PATTERN (insn);
10360 reg_weight += find_set_regmode_weight (x, mode);
10361 if (GET_CODE (x) == PARALLEL)
10364 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10366 x = XVECEXP (PATTERN (insn), 0, j);
10367 reg_weight += find_set_regmode_weight (x, mode);
10370 /* Decrement weight for each register that dies here. */
10371 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10373 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10375 rtx note = XEXP (x, 0);
10376 if (REG_P (note) && GET_MODE (note) == mode)
10383 /* Calculate regmode weights for all insns of a basic block. */
10385 find_regmode_weight (basic_block b, enum machine_mode mode)
10387 rtx insn, next_tail, head, tail;
10389 get_ebb_head_tail (b, b, &head, &tail);
10390 next_tail = NEXT_INSN (tail);
10392 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10394 /* Handle register life information. */
10395 if (!INSN_P (insn))
10398 if (mode == SFmode)
10399 INSN_REGMODE_WEIGHT (insn, mode) =
10400 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10401 else if (mode == SImode)
10402 INSN_REGMODE_WEIGHT (insn, mode) =
10403 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10407 /* Comparison function for ready queue sorting. */
10409 rank_for_reorder (const void *x, const void *y)
10411 rtx tmp = *(const rtx *) y;
10412 rtx tmp2 = *(const rtx *) x;
10414 /* The insn in a schedule group should be issued the first. */
10415 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10416 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10418 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10419 minimizes instruction movement, thus minimizing sched's effect on
10420 register pressure. */
10421 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10424 /* Resort the array A in which only element at index N may be out of order. */
10426 swap_reorder (rtx *a, int n)
10428 rtx insn = a[n - 1];
10431 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10439 #define SCHED_REORDER(READY, N_READY) \
10442 if ((N_READY) == 2) \
10443 swap_reorder (READY, N_READY); \
10444 else if ((N_READY) > 2) \
10445 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10449 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10452 ready_reorder (rtx *ready, int nready)
10454 SCHED_REORDER (ready, nready);
10457 /* Count life regions of r0 for a block. */
10459 find_r0_life_regions (basic_block b)
10468 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10479 insn = BB_HEAD (b);
10481 r0_reg = gen_rtx_REG (SImode, R0_REG);
10486 if (find_regno_note (insn, REG_DEAD, R0_REG))
10492 && (pset = single_set (insn))
10493 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10494 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10502 insn = NEXT_INSN (insn);
10504 return set - death;
10507 /* Calculate regmode weights for all insns of all basic block. */
10509 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10510 int verbose ATTRIBUTE_UNUSED,
10515 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10516 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10517 r0_life_regions = 0;
10519 FOR_EACH_BB_REVERSE (b)
10521 find_regmode_weight (b, SImode);
10522 find_regmode_weight (b, SFmode);
10523 if (!reload_completed)
10524 r0_life_regions += find_r0_life_regions (b);
10527 CURR_REGMODE_PRESSURE (SImode) = 0;
10528 CURR_REGMODE_PRESSURE (SFmode) = 0;
10534 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10535 int verbose ATTRIBUTE_UNUSED)
10537 if (regmode_weight[0])
10539 free (regmode_weight[0]);
10540 regmode_weight[0] = NULL;
10542 if (regmode_weight[1])
10544 free (regmode_weight[1]);
10545 regmode_weight[1] = NULL;
10549 /* The scalar modes supported differs from the default version in TImode
10550 for 32-bit SHMEDIA. */
10552 sh_scalar_mode_supported_p (enum machine_mode mode)
10554 if (TARGET_SHMEDIA32 && mode == TImode)
10557 return default_scalar_mode_supported_p (mode);
10560 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10561 keep count of register pressures on SImode and SFmode. */
10563 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10564 int sched_verbose ATTRIBUTE_UNUSED,
10566 int can_issue_more)
10568 if (GET_CODE (PATTERN (insn)) != USE
10569 && GET_CODE (PATTERN (insn)) != CLOBBER)
10570 cached_can_issue_more = can_issue_more - 1;
10572 cached_can_issue_more = can_issue_more;
10574 if (reload_completed)
10575 return cached_can_issue_more;
10577 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10578 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10580 return cached_can_issue_more;
10584 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10585 int verbose ATTRIBUTE_UNUSED,
10586 int veclen ATTRIBUTE_UNUSED)
10588 CURR_REGMODE_PRESSURE (SImode) = 0;
10589 CURR_REGMODE_PRESSURE (SFmode) = 0;
10592 /* Some magic numbers. */
10593 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10594 functions that already have high pressure on r0. */
10595 #define R0_MAX_LIFE_REGIONS 2
10596 /* Register Pressure thresholds for SImode and SFmode registers. */
10597 #define SIMODE_MAX_WEIGHT 5
10598 #define SFMODE_MAX_WEIGHT 10
10600 /* Return true if the pressure is high for MODE. */
10602 high_pressure (enum machine_mode mode)
10604 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10605 functions that already have high pressure on r0. */
10606 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10609 if (mode == SFmode)
10610 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10612 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10615 /* Reorder ready queue if register pressure is high. */
10617 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10618 int sched_verbose ATTRIBUTE_UNUSED,
10621 int clock_var ATTRIBUTE_UNUSED)
10623 if (reload_completed)
10624 return sh_issue_rate ();
10626 if (high_pressure (SFmode) || high_pressure (SImode))
10628 ready_reorder (ready, *n_readyp);
10631 return sh_issue_rate ();
10634 /* Skip cycles if the current register pressure is high. */
10636 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10637 int sched_verbose ATTRIBUTE_UNUSED,
10638 rtx *ready ATTRIBUTE_UNUSED,
10639 int *n_readyp ATTRIBUTE_UNUSED,
10640 int clock_var ATTRIBUTE_UNUSED)
10642 if (reload_completed)
10643 return cached_can_issue_more;
10645 if (high_pressure(SFmode) || high_pressure (SImode))
10648 return cached_can_issue_more;
10651 /* Skip cycles without sorting the ready queue. This will move insn from
10652 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10653 queue by sh_reorder. */
10655 /* Generally, skipping these many cycles are sufficient for all insns to move
10657 #define MAX_SKIPS 8
10660 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10661 int sched_verbose ATTRIBUTE_UNUSED,
10662 rtx insn ATTRIBUTE_UNUSED,
10663 int last_clock_var,
10667 if (reload_completed)
10672 if ((clock_var - last_clock_var) < MAX_SKIPS)
10677 /* If this is the last cycle we are skipping, allow reordering of R. */
10678 if ((clock_var - last_clock_var) == MAX_SKIPS)
10690 /* SHmedia requires registers for branches, so we can't generate new
10691 branches past reload. */
10693 sh_cannot_modify_jumps_p (void)
10695 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10699 sh_target_reg_class (void)
10701 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10705 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10707 HARD_REG_SET dummy;
10712 if (! shmedia_space_reserved_for_target_registers)
10714 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10716 if (calc_live_regs (&dummy) >= 6 * 8)
10722 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10724 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10728 On the SH1..SH4, the trampoline looks like
10729 2 0002 D202 mov.l l2,r2
10730 1 0000 D301 mov.l l1,r3
10731 3 0004 422B jmp @r2
10733 5 0008 00000000 l1: .long area
10734 6 000c 00000000 l2: .long function
10736 SH5 (compact) uses r1 instead of r3 for the static chain. */
10739 /* Emit RTL insns to initialize the variable parts of a trampoline.
10740 FNADDR is an RTX for the address of the function's pure code.
10741 CXT is an RTX for the static chain value for the function. */
10744 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10746 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10747 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10749 if (TARGET_SHMEDIA64)
10754 rtx movi1 = GEN_INT (0xcc000010);
10755 rtx shori1 = GEN_INT (0xc8000010);
10758 /* The following trampoline works within a +- 128 KB range for cxt:
10759 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10760 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10761 gettr tr1,r1; blink tr0,r63 */
10762 /* Address rounding makes it hard to compute the exact bounds of the
10763 offset for this trampoline, but we have a rather generous offset
10764 range, so frame_offset should do fine as an upper bound. */
10765 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10767 /* ??? could optimize this trampoline initialization
10768 by writing DImode words with two insns each. */
10769 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10770 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10771 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10772 insn = gen_rtx_AND (DImode, insn, mask);
10773 /* Or in ptb/u .,tr1 pattern */
10774 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10775 insn = force_operand (insn, NULL_RTX);
10776 insn = gen_lowpart (SImode, insn);
10777 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10778 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10779 insn = gen_rtx_AND (DImode, insn, mask);
10780 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10781 insn = gen_lowpart (SImode, insn);
10782 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10783 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10784 insn = gen_rtx_AND (DImode, insn, mask);
10785 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10786 insn = gen_lowpart (SImode, insn);
10787 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10788 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10789 insn = gen_rtx_AND (DImode, insn, mask);
10790 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10791 insn = gen_lowpart (SImode, insn);
10792 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10793 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10794 insn = gen_rtx_AND (DImode, insn, mask);
10795 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10796 insn = gen_lowpart (SImode, insn);
10797 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10798 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10799 GEN_INT (0x6bf10600));
10800 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10801 GEN_INT (0x4415fc10));
10802 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10803 GEN_INT (0x4401fff0));
10804 emit_insn (gen_ic_invalidate_line (tramp));
10807 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10808 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10810 tramp_templ = gen_datalabel_ref (tramp_templ);
10812 src = gen_const_mem (BLKmode, tramp_templ);
10813 set_mem_align (dst, 256);
10814 set_mem_align (src, 64);
10815 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10817 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10818 emit_move_insn (adjust_address (tramp_mem, Pmode,
10819 fixed_len + GET_MODE_SIZE (Pmode)),
10821 emit_insn (gen_ic_invalidate_line (tramp));
10824 else if (TARGET_SHMEDIA)
10826 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10827 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10828 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10829 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10830 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10831 rotated 10 right, and higher 16 bit of every 32 selected. */
10833 = force_reg (V2HImode, (simplify_gen_subreg
10834 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10835 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10836 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10838 fnaddr = force_reg (SImode, fnaddr);
10839 cxt = force_reg (SImode, cxt);
10840 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10841 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10843 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10844 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10845 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10846 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10847 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10848 gen_rtx_SUBREG (V2HImode, cxt, 0),
10850 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10851 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10852 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10853 if (TARGET_LITTLE_ENDIAN)
10855 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10856 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10860 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10861 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10863 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10864 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10865 emit_insn (gen_ic_invalidate_line (tramp));
10868 else if (TARGET_SHCOMPACT)
10870 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10873 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10874 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10876 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10877 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10879 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10880 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10881 if (TARGET_HARVARD)
10883 if (!TARGET_INLINE_IC_INVALIDATE
10884 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10885 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10886 FUNCTION_ORDINARY),
10887 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10889 emit_insn (gen_ic_invalidate_line (tramp));
10893 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10896 sh_trampoline_adjust_address (rtx tramp)
10898 if (TARGET_SHMEDIA)
10899 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
10900 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
10904 /* FIXME: This is overly conservative. A SHcompact function that
10905 receives arguments ``by reference'' will have them stored in its
10906 own stack frame, so it must not pass pointers or references to
10907 these arguments to other functions by means of sibling calls. */
10908 /* If PIC, we cannot make sibling calls to global functions
10909 because the PLT requires r12 to be live. */
10911 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10914 && (! TARGET_SHCOMPACT
10915 || crtl->args.info.stack_regs == 0)
10916 && ! sh_cfun_interrupt_handler_p ()
10918 || (decl && ! TREE_PUBLIC (decl))
10919 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10922 /* Machine specific built-in functions. */
10924 struct builtin_description
10926 const enum insn_code icode;
10927 const char *const name;
10932 /* describe number and signedness of arguments; arg[0] == result
10933 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10934 /* 9: 64-bit pointer, 10: 32-bit pointer */
10935 static const char signature_args[][4] =
10937 #define SH_BLTIN_V2SI2 0
10939 #define SH_BLTIN_V4HI2 1
10941 #define SH_BLTIN_V2SI3 2
10943 #define SH_BLTIN_V4HI3 3
10945 #define SH_BLTIN_V8QI3 4
10947 #define SH_BLTIN_MAC_HISI 5
10949 #define SH_BLTIN_SH_HI 6
10951 #define SH_BLTIN_SH_SI 7
10953 #define SH_BLTIN_V4HI2V2SI 8
10955 #define SH_BLTIN_V4HI2V8QI 9
10957 #define SH_BLTIN_SISF 10
10959 #define SH_BLTIN_LDUA_L 11
10961 #define SH_BLTIN_LDUA_Q 12
10963 #define SH_BLTIN_STUA_L 13
10965 #define SH_BLTIN_STUA_Q 14
10967 #define SH_BLTIN_LDUA_L64 15
10969 #define SH_BLTIN_LDUA_Q64 16
10971 #define SH_BLTIN_STUA_L64 17
10973 #define SH_BLTIN_STUA_Q64 18
10975 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10976 #define SH_BLTIN_2 19
10977 #define SH_BLTIN_SU 19
10979 #define SH_BLTIN_3 20
10980 #define SH_BLTIN_SUS 20
10982 #define SH_BLTIN_PSSV 21
10984 #define SH_BLTIN_XXUU 22
10985 #define SH_BLTIN_UUUU 22
10987 #define SH_BLTIN_PV 23
10990 /* mcmv: operands considered unsigned. */
10991 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10992 /* mperm: control value considered unsigned int. */
10993 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10994 /* mshards_q: returns signed short. */
10995 /* nsb: takes long long arg, returns unsigned char. */
10996 static struct builtin_description bdesc[] =
10998 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
10999 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
11000 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
11001 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
11002 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
11003 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
11004 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
11005 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
11006 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
11007 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
11008 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
11009 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
11010 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
11011 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
11012 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
11013 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
11014 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
11015 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
11016 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
11017 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
11018 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
11019 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
11020 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
11021 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
11022 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
11023 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
11024 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
11025 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
11026 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
11027 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
11028 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
11029 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
11030 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
11031 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
11032 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
11033 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
11034 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
11035 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
11036 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
11037 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
11038 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
11039 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
11040 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
11041 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
11042 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
11043 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
11044 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
11045 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
11046 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
11047 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
11048 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
11049 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
11050 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
11051 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
11052 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
11053 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
11054 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
11055 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
11056 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
11057 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
11058 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
11059 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
11060 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
11061 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
11062 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
11063 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
11064 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
11065 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
11066 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
11067 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
11068 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
11069 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
11070 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
11071 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
11072 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
11073 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
11074 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
11075 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
11076 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
11077 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
11078 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
11079 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
11080 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
11081 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
11085 sh_media_init_builtins (void)
11087 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
11088 struct builtin_description *d;
11090 memset (shared, 0, sizeof shared);
11091 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
11093 tree type, arg_type = 0;
11094 int signature = d->signature;
11097 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
11098 type = shared[signature];
11101 int has_result = signature_args[signature][0] != 0;
11104 if ((signature_args[signature][1] & 8)
11105 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
11106 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
11108 if (! TARGET_FPU_ANY
11109 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
11111 for (i = 0; i < (int) ARRAY_SIZE (args); i++)
11112 args[i] = NULL_TREE;
11115 int arg = signature_args[signature][i];
11116 int opno = i - 1 + has_result;
11119 arg_type = ptr_type_node;
11121 arg_type = (*lang_hooks.types.type_for_mode)
11122 (insn_data[d->icode].operand[opno].mode,
11127 arg_type = void_type_node;
11130 args[i-1] = arg_type;
11132 type = build_function_type_list (arg_type, args[0], args[1],
11133 args[2], NULL_TREE);
11134 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
11135 shared[signature] = type;
11138 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
11143 /* Returns the shmedia builtin decl for CODE. */
11146 sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11148 if (code >= ARRAY_SIZE (bdesc))
11149 return error_mark_node;
11151 return bdesc[code].fndecl;
11154 /* Implements target hook vector_mode_supported_p. */
11156 sh_vector_mode_supported_p (enum machine_mode mode)
11159 && ((mode == V2SFmode)
11160 || (mode == V4SFmode)
11161 || (mode == V16SFmode)))
11164 else if (TARGET_SHMEDIA
11165 && ((mode == V8QImode)
11166 || (mode == V2HImode)
11167 || (mode == V4HImode)
11168 || (mode == V2SImode)))
11175 sh_frame_pointer_required (void)
11177 /* If needed override this in other tm.h files to cope with various OS
11178 lossage requiring a frame pointer. */
11179 if (SUBTARGET_FRAME_POINTER_REQUIRED)
11188 /* Implements target hook dwarf_calling_convention. Return an enum
11189 of dwarf_calling_convention. */
11191 sh_dwarf_calling_convention (const_tree func)
11193 if (sh_attr_renesas_p (func))
11194 return DW_CC_GNU_renesas_sh;
11196 return DW_CC_normal;
11200 sh_init_builtins (void)
11202 if (TARGET_SHMEDIA)
11203 sh_media_init_builtins ();
11206 /* Returns the sh builtin decl for CODE. */
11209 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11211 if (TARGET_SHMEDIA)
11212 return sh_media_builtin_decl (code, initialize_p);
11214 return error_mark_node;
11217 /* Expand an expression EXP that calls a built-in function,
11218 with result going to TARGET if that's convenient
11219 (and in mode MODE if that's convenient).
11220 SUBTARGET may be used as the target for computing one of EXP's operands.
11221 IGNORE is nonzero if the value is to be ignored. */
11224 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11225 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
11227 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11228 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11229 const struct builtin_description *d = &bdesc[fcode];
11230 enum insn_code icode = d->icode;
11231 int signature = d->signature;
11232 enum machine_mode tmode = VOIDmode;
11237 if (signature_args[signature][0])
11242 tmode = insn_data[icode].operand[0].mode;
11244 || GET_MODE (target) != tmode
11245 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11246 target = gen_reg_rtx (tmode);
11247 op[nop++] = target;
11252 for (i = 1; i <= 3; i++, nop++)
11255 enum machine_mode opmode, argmode;
11258 if (! signature_args[signature][i])
11260 arg = CALL_EXPR_ARG (exp, i - 1);
11261 if (arg == error_mark_node)
11263 if (signature_args[signature][i] & 8)
11266 optype = ptr_type_node;
11270 opmode = insn_data[icode].operand[nop].mode;
11271 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11273 argmode = TYPE_MODE (TREE_TYPE (arg));
11274 if (argmode != opmode)
11275 arg = build1 (NOP_EXPR, optype, arg);
11276 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
11277 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11278 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11284 pat = (*insn_data[d->icode].genfun) (op[0]);
11287 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11290 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11293 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11296 gcc_unreachable ();
11305 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
11307 rtx sel0 = const0_rtx;
11308 rtx sel1 = const1_rtx;
11309 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
11310 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11312 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11313 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11317 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
11319 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11321 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11322 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
11325 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11326 We can allow any mode in any general register. The special registers
11327 only allow SImode. Don't allow any mode in the PR.
11329 We cannot hold DCmode values in the XD registers because alter_reg
11330 handles subregs of them incorrectly. We could work around this by
11331 spacing the XD registers like the DR registers, but this would require
11332 additional memory in every compilation to hold larger register vectors.
11333 We could hold SFmode / SCmode values in XD registers, but that
11334 would require a tertiary reload when reloading from / to memory,
11335 and a secondary reload to reload from / to general regs; that
11336 seems to be a loosing proposition.
11338 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11339 it won't be ferried through GP registers first. */
11342 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11344 if (SPECIAL_REGISTER_P (regno))
11345 return mode == SImode;
11347 if (regno == FPUL_REG)
11348 return (mode == SImode || mode == SFmode);
11350 if (FP_REGISTER_P (regno) && mode == SFmode)
11353 if (mode == V2SFmode)
11355 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11356 || GENERAL_REGISTER_P (regno)))
11362 if (mode == V4SFmode)
11364 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11365 || GENERAL_REGISTER_P (regno))
11371 if (mode == V16SFmode)
11373 if (TARGET_SHMEDIA)
11375 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11381 return regno == FIRST_XD_REG;
11384 if (FP_REGISTER_P (regno))
11388 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11389 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11392 && (mode == DFmode || mode == DImode
11393 || mode == V2SFmode || mode == TImode)))
11394 && ((regno - FIRST_FP_REG) & 1) == 0)
11395 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11396 && ((regno - FIRST_FP_REG) & 3) == 0))
11402 if (XD_REGISTER_P (regno))
11403 return mode == DFmode;
11405 if (TARGET_REGISTER_P (regno))
11406 return (mode == DImode || mode == SImode || mode == PDImode);
11408 if (regno == PR_REG)
11409 return mode == SImode;
11411 if (regno == FPSCR_REG)
11412 return mode == PSImode;
11414 /* FIXME. This works around PR target/37633 for -O0. */
11415 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11417 unsigned int n = GET_MODE_SIZE (mode) / 8;
11419 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11420 && regno <= FIRST_GENERAL_REG + 14)
11427 /* Return the class of registers for which a mode change from FROM to TO
11430 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
11431 enum reg_class rclass)
11433 /* We want to enable the use of SUBREGs as a means to
11434 VEC_SELECT a single element of a vector. */
11435 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
11436 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
11438 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11440 if (TARGET_LITTLE_ENDIAN)
11442 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
11443 return reg_classes_intersect_p (DF_REGS, rclass);
11447 if (GET_MODE_SIZE (from) < 8)
11448 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11454 /* Return true if registers in machine mode MODE will likely be
11455 allocated to registers in small register classes. */
11458 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11460 return (! TARGET_SHMEDIA);
11463 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11464 that label is used. */
11467 sh_mark_label (rtx address, int nuses)
11469 if (GOTOFF_P (address))
11471 /* Extract the label or symbol. */
11472 address = XEXP (address, 0);
11473 if (GET_CODE (address) == PLUS)
11474 address = XEXP (address, 0);
11475 address = XVECEXP (address, 0, 0);
11477 if (GET_CODE (address) == LABEL_REF
11478 && LABEL_P (XEXP (address, 0)))
11479 LABEL_NUSES (XEXP (address, 0)) += nuses;
11482 /* Compute extra cost of moving data between one register class
11485 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11486 uses this information. Hence, the general register <-> floating point
11487 register information here is not used for SFmode. */
11490 sh_register_move_cost (enum machine_mode mode,
11491 reg_class_t srcclass, reg_class_t dstclass)
11493 if (dstclass == T_REGS || dstclass == PR_REGS)
11496 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11499 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11500 && REGCLASS_HAS_FP_REG (srcclass)
11501 && REGCLASS_HAS_FP_REG (dstclass))
11504 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11505 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11507 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11508 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11511 if ((REGCLASS_HAS_FP_REG (dstclass)
11512 && REGCLASS_HAS_GENERAL_REG (srcclass))
11513 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11514 && REGCLASS_HAS_FP_REG (srcclass)))
11516 /* Discourage trying to use fp regs for a pointer. This also
11517 discourages fp regs with SImode because Pmode is an alias
11518 of SImode on this target. See PR target/48596. */
11519 int addend = (mode == Pmode) ? 40 : 0;
11521 return (((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12) + addend)
11522 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11525 if ((dstclass == FPUL_REGS
11526 && REGCLASS_HAS_GENERAL_REG (srcclass))
11527 || (srcclass == FPUL_REGS
11528 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11531 if ((dstclass == FPUL_REGS
11532 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11533 || (srcclass == FPUL_REGS
11534 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11537 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11538 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11541 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11543 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11545 if (sh_gettrcost >= 0)
11546 return sh_gettrcost;
11547 else if (!TARGET_PT_FIXED)
11551 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11552 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11557 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11558 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11559 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11561 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11564 static rtx emit_load_ptr (rtx, rtx);
11567 emit_load_ptr (rtx reg, rtx addr)
11569 rtx mem = gen_const_mem (ptr_mode, addr);
11571 if (Pmode != ptr_mode)
11572 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11573 return emit_move_insn (reg, mem);
11577 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11578 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11581 CUMULATIVE_ARGS cum;
11582 int structure_value_byref = 0;
11583 rtx this_rtx, this_value, sibcall, insns, funexp;
11584 tree funtype = TREE_TYPE (function);
11585 int simple_add = CONST_OK_FOR_ADD (delta);
11587 rtx scratch0, scratch1, scratch2;
11590 reload_completed = 1;
11591 epilogue_completed = 1;
11592 current_function_uses_only_leaf_regs = 1;
11594 emit_note (NOTE_INSN_PROLOGUE_END);
11596 /* Find the "this" pointer. We have such a wide range of ABIs for the
11597 SH that it's best to do this completely machine independently.
11598 "this" is passed as first argument, unless a structure return pointer
11599 comes first, in which case "this" comes second. */
11600 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11601 #ifndef PCC_STATIC_STRUCT_RETURN
11602 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11603 structure_value_byref = 1;
11604 #endif /* not PCC_STATIC_STRUCT_RETURN */
11605 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11607 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11609 sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true);
11612 = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true);
11614 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11615 static chain pointer (even if you can't have nested virtual functions
11616 right now, someone might implement them sometime), and the rest of the
11617 registers are used for argument passing, are callee-saved, or reserved. */
11618 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11619 -ffixed-reg has been used. */
11620 if (! call_used_regs[0] || fixed_regs[0])
11621 error ("r0 needs to be available as a call-clobbered register");
11622 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11625 if (call_used_regs[1] && ! fixed_regs[1])
11626 scratch1 = gen_rtx_REG (ptr_mode, 1);
11627 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11628 pointing where to return struct values. */
11629 if (call_used_regs[3] && ! fixed_regs[3])
11630 scratch2 = gen_rtx_REG (Pmode, 3);
11632 else if (TARGET_SHMEDIA)
11634 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11635 if (i != REGNO (scratch0) &&
11636 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11638 scratch1 = gen_rtx_REG (ptr_mode, i);
11641 if (scratch1 == scratch0)
11642 error ("need a second call-clobbered general purpose register");
11643 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11644 if (call_used_regs[i] && ! fixed_regs[i])
11646 scratch2 = gen_rtx_REG (Pmode, i);
11649 if (scratch2 == scratch0)
11650 error ("need a call-clobbered target register");
11653 this_value = plus_constant (this_rtx, delta);
11655 && (simple_add || scratch0 != scratch1)
11656 && strict_memory_address_p (ptr_mode, this_value))
11658 emit_load_ptr (scratch0, this_value);
11663 ; /* Do nothing. */
11664 else if (simple_add)
11665 emit_move_insn (this_rtx, this_value);
11668 emit_move_insn (scratch1, GEN_INT (delta));
11669 emit_insn (gen_add2_insn (this_rtx, scratch1));
11677 emit_load_ptr (scratch0, this_rtx);
11679 offset_addr = plus_constant (scratch0, vcall_offset);
11680 if (strict_memory_address_p (ptr_mode, offset_addr))
11681 ; /* Do nothing. */
11682 else if (! TARGET_SH5 && scratch0 != scratch1)
11684 /* scratch0 != scratch1, and we have indexed loads. Get better
11685 schedule by loading the offset into r1 and using an indexed
11686 load - then the load of r1 can issue before the load from
11687 (this_rtx + delta) finishes. */
11688 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11689 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11691 else if (CONST_OK_FOR_ADD (vcall_offset))
11693 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11694 offset_addr = scratch0;
11696 else if (scratch0 != scratch1)
11698 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11699 emit_insn (gen_add2_insn (scratch0, scratch1));
11700 offset_addr = scratch0;
11703 gcc_unreachable (); /* FIXME */
11704 emit_load_ptr (scratch0, offset_addr);
11706 if (Pmode != ptr_mode)
11707 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11708 emit_insn (gen_add2_insn (this_rtx, scratch0));
11711 /* Generate a tail call to the target function. */
11712 if (! TREE_USED (function))
11714 assemble_external (function);
11715 TREE_USED (function) = 1;
11717 funexp = XEXP (DECL_RTL (function), 0);
11718 /* If the function is overridden, so is the thunk, hence we don't
11719 need GOT addressing even if this is a public symbol. */
11721 if (TARGET_SH1 && ! flag_weak)
11722 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11725 if (TARGET_SH2 && flag_pic)
11727 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11728 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11732 if (TARGET_SHMEDIA && flag_pic)
11734 funexp = gen_sym2PIC (funexp);
11735 PUT_MODE (funexp, Pmode);
11737 emit_move_insn (scratch2, funexp);
11738 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11739 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11741 sibcall = emit_call_insn (sibcall);
11742 SIBLING_CALL_P (sibcall) = 1;
11743 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11746 /* Run just enough of rest_of_compilation to do scheduling and get
11747 the insns emitted. Note that use_thunk calls
11748 assemble_start_function and assemble_end_function. */
11750 insn_locators_alloc ();
11751 insns = get_insns ();
11757 split_all_insns_noflow ();
11761 shorten_branches (insns);
11762 final_start_function (insns, file, 1);
11763 final (insns, file, 1);
11764 final_end_function ();
11766 reload_completed = 0;
11767 epilogue_completed = 0;
11771 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11775 /* If this is not an ordinary function, the name usually comes from a
11776 string literal or an sprintf buffer. Make sure we use the same
11777 string consistently, so that cse will be able to unify address loads. */
11778 if (kind != FUNCTION_ORDINARY)
11779 name = IDENTIFIER_POINTER (get_identifier (name));
11780 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11781 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11785 case FUNCTION_ORDINARY:
11789 rtx reg = target ? target : gen_reg_rtx (Pmode);
11791 emit_insn (gen_symGOT2reg (reg, sym));
11797 /* ??? To allow cse to work, we use GOTOFF relocations.
11798 we could add combiner patterns to transform this into
11799 straight pc-relative calls with sym2PIC / bsrf when
11800 label load and function call are still 1:1 and in the
11801 same basic block during combine. */
11802 rtx reg = target ? target : gen_reg_rtx (Pmode);
11804 emit_insn (gen_symGOTOFF2reg (reg, sym));
11809 if (target && sym != target)
11811 emit_move_insn (target, sym);
11817 /* Find the number of a general purpose register in S. */
11819 scavenge_reg (HARD_REG_SET *s)
11822 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11823 if (TEST_HARD_REG_BIT (*s, r))
11829 sh_get_pr_initial_val (void)
11833 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11834 PR register on SHcompact, because it might be clobbered by the prologue.
11835 We check first if that is known to be the case. */
11836 if (TARGET_SHCOMPACT
11837 && ((crtl->args.info.call_cookie
11838 & ~ CALL_COOKIE_RET_TRAMP (1))
11839 || crtl->saves_all_registers))
11840 return gen_frame_mem (SImode, return_address_pointer_rtx);
11842 /* If we haven't finished rtl generation, there might be a nonlocal label
11843 that we haven't seen yet.
11844 ??? get_hard_reg_initial_val fails if it is called after register
11845 allocation has started, unless it has been called before for the
11846 same register. And even then, we end in trouble if we didn't use
11847 the register in the same basic block before. So call
11848 get_hard_reg_initial_val now and wrap it in an unspec if we might
11849 need to replace it. */
11850 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11851 combine can put the pseudo returned by get_hard_reg_initial_val into
11852 instructions that need a general purpose registers, which will fail to
11853 be recognized when the pseudo becomes allocated to PR. */
11855 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11857 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11862 sh_expand_t_scc (rtx operands[])
11864 enum rtx_code code = GET_CODE (operands[1]);
11865 rtx target = operands[0];
11866 rtx op0 = operands[2];
11867 rtx op1 = operands[3];
11868 rtx result = target;
11871 if (!REG_P (op0) || REGNO (op0) != T_REG
11872 || !CONST_INT_P (op1))
11874 if (!REG_P (result))
11875 result = gen_reg_rtx (SImode);
11876 val = INTVAL (op1);
11877 if ((code == EQ && val == 1) || (code == NE && val == 0))
11878 emit_insn (gen_movt (result));
11879 else if (TARGET_SH2A && ((code == EQ && val == 0)
11880 || (code == NE && val == 1)))
11881 emit_insn (gen_xorsi3_movrt (result));
11882 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11884 emit_clobber (result);
11885 emit_insn (gen_subc (result, result, result));
11886 emit_insn (gen_addsi3 (result, result, const1_rtx));
11888 else if (code == EQ || code == NE)
11889 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11892 if (result != target)
11893 emit_move_insn (target, result);
11897 /* INSN is an sfunc; return the rtx that describes the address used. */
11899 extract_sfunc_addr (rtx insn)
11901 rtx pattern, part = NULL_RTX;
11904 pattern = PATTERN (insn);
11905 len = XVECLEN (pattern, 0);
11906 for (i = 0; i < len; i++)
11908 part = XVECEXP (pattern, 0, i);
11909 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11910 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11911 return XEXP (part, 0);
11913 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11914 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11917 /* Verify that the register in use_sfunc_addr still agrees with the address
11918 used in the sfunc. This prevents fill_slots_from_thread from changing
11920 INSN is the use_sfunc_addr instruction, and REG is the register it
11923 check_use_sfunc_addr (rtx insn, rtx reg)
11925 /* Search for the sfunc. It should really come right after INSN. */
11926 while ((insn = NEXT_INSN (insn)))
11928 if (LABEL_P (insn) || JUMP_P (insn))
11930 if (! INSN_P (insn))
11933 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11934 insn = XVECEXP (PATTERN (insn), 0, 0);
11935 if (GET_CODE (PATTERN (insn)) != PARALLEL
11936 || get_attr_type (insn) != TYPE_SFUNC)
11938 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11940 gcc_unreachable ();
11943 /* This function returns a constant rtx that represents pi / 2**15 in
11944 SFmode. it's used to scale SFmode angles, in radians, to a
11945 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11946 maps to 0x10000). */
11948 static GTY(()) rtx sh_fsca_sf2int_rtx;
11951 sh_fsca_sf2int (void)
11953 if (! sh_fsca_sf2int_rtx)
11955 REAL_VALUE_TYPE rv;
11957 real_from_string (&rv, "10430.378350470453");
11958 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11961 return sh_fsca_sf2int_rtx;
11964 /* This function returns a constant rtx that represents pi / 2**15 in
11965 DFmode. it's used to scale DFmode angles, in radians, to a
11966 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11967 maps to 0x10000). */
11969 static GTY(()) rtx sh_fsca_df2int_rtx;
11972 sh_fsca_df2int (void)
11974 if (! sh_fsca_df2int_rtx)
11976 REAL_VALUE_TYPE rv;
11978 real_from_string (&rv, "10430.378350470453");
11979 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11982 return sh_fsca_df2int_rtx;
11985 /* This function returns a constant rtx that represents 2**15 / pi in
11986 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11987 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11990 static GTY(()) rtx sh_fsca_int2sf_rtx;
11993 sh_fsca_int2sf (void)
11995 if (! sh_fsca_int2sf_rtx)
11997 REAL_VALUE_TYPE rv;
11999 real_from_string (&rv, "9.587379924285257e-5");
12000 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
12003 return sh_fsca_int2sf_rtx;
12006 /* Initialize the CUMULATIVE_ARGS structure. */
12009 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
12011 rtx libname ATTRIBUTE_UNUSED,
12013 signed int n_named_args,
12014 enum machine_mode mode)
12016 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
12017 pcum->free_single_fp_reg = 0;
12018 pcum->stack_regs = 0;
12019 pcum->byref_regs = 0;
12021 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
12023 /* XXX - Should we check TARGET_HITACHI here ??? */
12024 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
12028 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
12029 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
12030 pcum->prototype_p = prototype_p (fntype);
12031 pcum->arg_count [(int) SH_ARG_INT]
12032 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
12035 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12036 && pcum->arg_count [(int) SH_ARG_INT] == 0
12037 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
12038 ? int_size_in_bytes (TREE_TYPE (fntype))
12039 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
12040 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
12041 == FIRST_RET_REG));
12045 pcum->arg_count [(int) SH_ARG_INT] = 0;
12046 pcum->prototype_p = FALSE;
12047 if (mode != VOIDmode)
12049 pcum->call_cookie =
12050 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12051 && GET_MODE_SIZE (mode) > 4
12052 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
12054 /* If the default ABI is the Renesas ABI then all library
12055 calls must assume that the library will be using the
12056 Renesas ABI. So if the function would return its result
12057 in memory then we must force the address of this memory
12058 block onto the stack. Ideally we would like to call
12059 targetm.calls.return_in_memory() here but we do not have
12060 the TYPE or the FNDECL available so we synthesize the
12061 contents of that function as best we can. */
12063 (TARGET_DEFAULT & MASK_HITACHI)
12064 && (mode == BLKmode
12065 || (GET_MODE_SIZE (mode) > 4
12066 && !(mode == DFmode
12067 && TARGET_FPU_DOUBLE)));
12071 pcum->call_cookie = 0;
12072 pcum->force_mem = FALSE;
12077 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12078 not enter into CONST_DOUBLE for the replace.
12080 Note that copying is not done so X must not be shared unless all copies
12081 are to be modified.
12083 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12084 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12085 replacements[n*2+1] - and that we take mode changes into account.
12087 If a replacement is ambiguous, return NULL_RTX.
12089 If MODIFY is zero, don't modify any rtl in place,
12090 just return zero or nonzero for failure / success. */
12093 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
12098 /* The following prevents loops occurrence when we change MEM in
12099 CONST_DOUBLE onto the same CONST_DOUBLE. */
12100 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
12103 for (i = n_replacements - 1; i >= 0 ; i--)
12104 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
12105 return replacements[i*2+1];
12107 /* Allow this function to make replacements in EXPR_LISTs. */
12111 if (GET_CODE (x) == SUBREG)
12113 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
12114 n_replacements, modify);
12116 if (CONST_INT_P (new_rtx))
12118 x = simplify_subreg (GET_MODE (x), new_rtx,
12119 GET_MODE (SUBREG_REG (x)),
12125 SUBREG_REG (x) = new_rtx;
12129 else if (REG_P (x))
12131 unsigned regno = REGNO (x);
12132 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
12133 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12134 rtx result = NULL_RTX;
12136 for (i = n_replacements - 1; i >= 0; i--)
12138 rtx from = replacements[i*2];
12139 rtx to = replacements[i*2+1];
12140 unsigned from_regno, from_nregs, to_regno, new_regno;
12144 from_regno = REGNO (from);
12145 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
12146 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
12147 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
12149 if (regno < from_regno
12150 || regno + nregs > from_regno + nregs
12154 to_regno = REGNO (to);
12155 if (to_regno < FIRST_PSEUDO_REGISTER)
12157 new_regno = regno + to_regno - from_regno;
12158 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
12161 result = gen_rtx_REG (GET_MODE (x), new_regno);
12163 else if (GET_MODE (x) <= GET_MODE (to))
12164 result = gen_lowpart_common (GET_MODE (x), to);
12166 result = gen_lowpart_SUBREG (GET_MODE (x), to);
12169 return result ? result : x;
12171 else if (GET_CODE (x) == ZERO_EXTEND)
12173 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
12174 n_replacements, modify);
12176 if (CONST_INT_P (new_rtx))
12178 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
12179 new_rtx, GET_MODE (XEXP (x, 0)));
12184 XEXP (x, 0) = new_rtx;
12189 fmt = GET_RTX_FORMAT (GET_CODE (x));
12190 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
12196 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
12197 n_replacements, modify);
12201 XEXP (x, i) = new_rtx;
12203 else if (fmt[i] == 'E')
12204 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12206 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
12207 n_replacements, modify);
12211 XVECEXP (x, i, j) = new_rtx;
12219 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12221 enum rtx_code code = TRUNCATE;
12223 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12225 rtx inner = XEXP (x, 0);
12226 enum machine_mode inner_mode = GET_MODE (inner);
12228 if (inner_mode == mode)
12230 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12232 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12233 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12235 code = GET_CODE (x);
12239 return gen_rtx_fmt_e (code, mode, x);
12242 /* called via for_each_rtx after reload, to clean up truncates of
12243 registers that span multiple actual hard registers. */
12245 shmedia_cleanup_truncate (rtx *p, void *n_changes)
12249 if (GET_CODE (x) != TRUNCATE)
12252 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
12254 enum machine_mode reg_mode = GET_MODE (reg);
12255 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12256 subreg_lowpart_offset (DImode, reg_mode));
12257 *(int*) n_changes += 1;
12263 /* Load and store depend on the highpart of the address. However,
12264 set_attr_alternative does not give well-defined results before reload,
12265 so we must look at the rtl ourselves to see if any of the feeding
12266 registers is used in a memref. */
12268 /* Called by sh_contains_memref_p via for_each_rtx. */
12270 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12272 return (MEM_P (*loc));
12275 /* Return nonzero iff INSN contains a MEM. */
12277 sh_contains_memref_p (rtx insn)
12279 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12282 /* Return nonzero iff INSN loads a banked register. */
12284 sh_loads_bankedreg_p (rtx insn)
12286 if (GET_CODE (PATTERN (insn)) == SET)
12288 rtx op = SET_DEST (PATTERN(insn));
12289 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12296 /* FNADDR is the MEM expression from a call expander. Return an address
12297 to use in an SHmedia insn pattern. */
12299 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12303 fnaddr = XEXP (fnaddr, 0);
12304 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12305 if (flag_pic && is_sym)
12307 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12309 rtx reg = gen_reg_rtx (Pmode);
12311 /* We must not use GOTPLT for sibcalls, because PIC_REG
12312 must be restored before the PLT code gets to run. */
12314 emit_insn (gen_symGOT2reg (reg, fnaddr));
12316 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12321 fnaddr = gen_sym2PIC (fnaddr);
12322 PUT_MODE (fnaddr, Pmode);
12325 /* If ptabs might trap, make this visible to the rest of the compiler.
12326 We generally assume that symbols pertain to valid locations, but
12327 it is possible to generate invalid symbols with asm or linker tricks.
12328 In a list of functions where each returns its successor, an invalid
12329 symbol might denote an empty list. */
12330 if (!TARGET_PT_FIXED
12331 && (!is_sym || TARGET_INVALID_SYMBOLS)
12332 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12334 rtx tr = gen_reg_rtx (PDImode);
12336 emit_insn (gen_ptabs (tr, fnaddr));
12339 else if (! target_reg_operand (fnaddr, Pmode))
12340 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12344 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12347 sh_preferred_reload_class (rtx x, reg_class_t rclass)
12349 if (rclass == NO_REGS
12351 && (CONST_DOUBLE_P (x)
12352 || GET_CODE (x) == SYMBOL_REF
12353 || PIC_ADDR_P (x)))
12354 return GENERAL_REGS;
12359 /* Implement TARGET_SECONDARY_RELOAD. */
12362 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12363 enum machine_mode mode, secondary_reload_info *sri)
12365 enum reg_class rclass = (enum reg_class) rclass_i;
12369 if (REGCLASS_HAS_FP_REG (rclass)
12370 && ! TARGET_SHMEDIA
12371 && immediate_operand ((x), mode)
12372 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12373 && mode == SFmode && fldi_ok ()))
12377 sri->icode = CODE_FOR_reload_insf__frn;
12380 sri->icode = CODE_FOR_reload_indf__frn;
12383 /* ??? If we knew that we are in the appropriate mode -
12384 single precision - we could use a reload pattern directly. */
12389 if (rclass == FPUL_REGS
12391 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12392 || REGNO (x) == T_REG))
12393 || GET_CODE (x) == PLUS))
12394 return GENERAL_REGS;
12395 if (rclass == FPUL_REGS && immediate_operand (x, mode))
12397 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
12398 return GENERAL_REGS;
12399 else if (mode == SFmode)
12401 sri->icode = CODE_FOR_reload_insi__i_fpul;
12404 if (rclass == FPSCR_REGS
12405 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12406 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
12407 return GENERAL_REGS;
12408 if (REGCLASS_HAS_FP_REG (rclass)
12410 && immediate_operand (x, mode)
12411 && x != CONST0_RTX (GET_MODE (x))
12412 && GET_MODE (x) != V4SFmode)
12413 return GENERAL_REGS;
12414 if ((mode == QImode || mode == HImode)
12415 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12417 sri->icode = ((mode == QImode)
12418 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12421 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
12422 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
12423 return TARGET_REGS;
12424 } /* end of input-only processing. */
12426 if (((REGCLASS_HAS_FP_REG (rclass)
12428 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12429 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12430 && TARGET_FMOVD))))
12431 || (REGCLASS_HAS_GENERAL_REG (rclass)
12433 && FP_REGISTER_P (REGNO (x))))
12434 && ! TARGET_SHMEDIA
12435 && (mode == SFmode || mode == SImode))
12437 if ((rclass == FPUL_REGS
12438 || (REGCLASS_HAS_FP_REG (rclass)
12439 && ! TARGET_SHMEDIA && mode == SImode))
12442 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12443 || REGNO (x) == T_REG
12444 || system_reg_operand (x, VOIDmode)))))
12446 if (rclass == FPUL_REGS)
12447 return GENERAL_REGS;
12450 if ((rclass == TARGET_REGS
12451 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
12452 && !satisfies_constraint_Csy (x)
12453 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
12454 return GENERAL_REGS;
12455 if ((rclass == MAC_REGS || rclass == PR_REGS)
12456 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
12457 && rclass != REGNO_REG_CLASS (REGNO (x)))
12458 return GENERAL_REGS;
12459 if (rclass != GENERAL_REGS && REG_P (x)
12460 && TARGET_REGISTER_P (REGNO (x)))
12461 return GENERAL_REGS;
12463 /* If here fall back to loading FPUL register through general registers.
12464 This case can happen when movsi_ie insn is picked initially to
12465 load/store the FPUL register from/to another register, and then the
12466 other register is allocated on the stack. */
12467 if (rclass == FPUL_REGS && true_regnum (x) == -1)
12468 return GENERAL_REGS;
12474 sh_conditional_register_usage (void)
12477 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
12478 if (! VALID_REGISTER_P (regno))
12479 fixed_regs[regno] = call_used_regs[regno] = 1;
12480 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12483 call_used_regs[FIRST_GENERAL_REG + 8]
12484 = call_used_regs[FIRST_GENERAL_REG + 9] = 1;
12485 call_really_used_regs[FIRST_GENERAL_REG + 8]
12486 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;
12488 if (TARGET_SHMEDIA)
12490 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;
12491 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);
12492 regno_reg_class[FIRST_FP_REG] = FP_REGS;
12496 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12497 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12499 /* Renesas saves and restores mac registers on call. */
12500 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
12502 call_really_used_regs[MACH_REG] = 0;
12503 call_really_used_regs[MACL_REG] = 0;
12505 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);
12506 regno <= LAST_FP_REG; regno += 2)
12507 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);
12508 if (TARGET_SHMEDIA)
12510 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)
12511 if (! fixed_regs[regno] && call_really_used_regs[regno])
12512 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12515 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
12516 if (! fixed_regs[regno] && call_really_used_regs[regno])
12517 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12520 /* Implement TARGET_LEGITIMATE_CONSTANT_P
12522 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
12525 sh_legitimate_constant_p (enum machine_mode mode, rtx x)
12527 return (TARGET_SHMEDIA
12528 ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
12529 || x == CONST0_RTX (mode)
12530 || !TARGET_SHMEDIA_FPU
12531 || TARGET_SHMEDIA64)
12532 : (GET_CODE (x) != CONST_DOUBLE
12533 || mode == DFmode || mode == SFmode
12534 || mode == DImode || GET_MODE (x) == VOIDmode));
12537 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
12540 sh_init_sync_libfuncs (void)
12542 init_sync_libfuncs (UNITS_PER_WORD);