1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
46 #include "target-def.h"
48 #include "langhooks.h"
49 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
54 #include "tree-gimple.h"
56 #include "alloc-pool.h"
59 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
61 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
62 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
64 /* These are some macros to abstract register modes. */
65 #define CONST_OK_FOR_ADD(size) \
66 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
67 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
68 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
69 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
71 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
72 int current_function_interrupt;
74 tree sh_deferred_function_attributes;
75 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
77 /* Global variables for machine-dependent things. */
79 /* Which cpu are we scheduling for. */
80 enum processor_type sh_cpu;
82 /* Definitions used in ready queue reordering for first scheduling pass. */
84 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
85 static short *regmode_weight[2];
87 /* Total SFmode and SImode weights of scheduled insns. */
88 static int curr_regmode_pressure[2];
90 /* If true, skip cycles for Q -> R movement. */
91 static int skip_cycles = 0;
93 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
94 and returned from sh_reorder2. */
95 static short cached_can_issue_more;
97 /* Saved operands from the last compare to use when we generate an scc
103 /* Provides the class number of the smallest class containing
106 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
108 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
109 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
110 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
125 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
126 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
141 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
142 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
143 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
144 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
145 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
146 GENERAL_REGS, GENERAL_REGS,
149 char sh_register_names[FIRST_PSEUDO_REGISTER] \
150 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
152 char sh_additional_register_names[ADDREGNAMES_SIZE] \
153 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
154 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
156 /* Provide reg_class from a letter such as appears in the machine
157 description. *: target independently reserved letter.
158 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
160 enum reg_class reg_class_from_letter[] =
162 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
163 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
164 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
165 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
166 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
167 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
168 /* y */ FPUL_REGS, /* z */ R0_REGS
171 int assembler_dialect;
173 static bool shmedia_space_reserved_for_target_registers;
175 static bool sh_handle_option (size_t, const char *, int);
176 static void split_branches (rtx);
177 static int branch_dest (rtx);
178 static void force_into (rtx, rtx);
179 static void print_slot (rtx);
180 static rtx add_constant (rtx, enum machine_mode, rtx);
181 static void dump_table (rtx, rtx);
182 static int hi_const (rtx);
183 static int broken_move (rtx);
184 static int mova_p (rtx);
185 static rtx find_barrier (int, rtx, rtx);
186 static int noncall_uses_reg (rtx, rtx, rtx *);
187 static rtx gen_block_redirect (rtx, int, int);
188 static void sh_reorg (void);
189 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
190 static rtx frame_insn (rtx);
191 static rtx push (int);
192 static void pop (int);
193 static void push_regs (HARD_REG_SET *, int);
194 static int calc_live_regs (HARD_REG_SET *);
195 static void mark_use (rtx, rtx *);
196 static HOST_WIDE_INT rounded_frame_size (int);
197 static rtx mark_constant_pool_use (rtx);
198 const struct attribute_spec sh_attribute_table[];
199 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
202 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
203 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
204 static void sh_insert_attributes (tree, tree *);
205 static const char *sh_check_pch_target_flags (int);
206 static int sh_adjust_cost (rtx, rtx, rtx, int);
207 static int sh_issue_rate (void);
208 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
209 static short find_set_regmode_weight (rtx, enum machine_mode);
210 static short find_insn_regmode_weight (rtx, enum machine_mode);
211 static void find_regmode_weight (basic_block, enum machine_mode);
212 static void sh_md_init_global (FILE *, int, int);
213 static void sh_md_finish_global (FILE *, int);
214 static int rank_for_reorder (const void *, const void *);
215 static void swap_reorder (rtx *, int);
216 static void ready_reorder (rtx *, int);
217 static short high_pressure (enum machine_mode);
218 static int sh_reorder (FILE *, int, rtx *, int *, int);
219 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
220 static void sh_md_init (FILE *, int, int);
221 static int sh_variable_issue (FILE *, int, rtx, int);
223 static bool sh_function_ok_for_sibcall (tree, tree);
225 static bool sh_cannot_modify_jumps_p (void);
226 static int sh_target_reg_class (void);
227 static bool sh_optimize_target_register_callee_saved (bool);
228 static bool sh_ms_bitfield_layout_p (tree);
230 static void sh_init_builtins (void);
231 static void sh_media_init_builtins (void);
232 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
233 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
234 static void sh_file_start (void);
235 static int flow_dependent_p (rtx, rtx);
236 static void flow_dependent_p_1 (rtx, rtx, void *);
237 static int shiftcosts (rtx);
238 static int andcosts (rtx);
239 static int addsubcosts (rtx);
240 static int multcosts (rtx);
241 static bool unspec_caller_rtx_p (rtx);
242 static bool sh_cannot_copy_insn_p (rtx);
243 static bool sh_rtx_costs (rtx, int, int, int *);
244 static int sh_address_cost (rtx);
245 static int sh_pr_n_sets (void);
246 static rtx sh_allocate_initial_value (rtx);
247 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
248 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
249 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
250 static int scavenge_reg (HARD_REG_SET *s);
251 struct save_schedule_s;
252 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
253 struct save_schedule_s *, int);
255 static rtx sh_struct_value_rtx (tree, int);
256 static bool sh_return_in_memory (tree, tree);
257 static rtx sh_builtin_saveregs (void);
258 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
259 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
260 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
261 static tree sh_build_builtin_va_list (void);
262 static tree sh_gimplify_va_arg_expr (tree, tree, tree *, tree *);
263 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
265 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
267 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
269 static int sh_dwarf_calling_convention (tree);
272 /* Initialize the GCC target structure. */
273 #undef TARGET_ATTRIBUTE_TABLE
274 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
276 /* The next two are used for debug info when compiling with -gdwarf. */
277 #undef TARGET_ASM_UNALIGNED_HI_OP
278 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
279 #undef TARGET_ASM_UNALIGNED_SI_OP
280 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
282 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
283 #undef TARGET_ASM_UNALIGNED_DI_OP
284 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
285 #undef TARGET_ASM_ALIGNED_DI_OP
286 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
288 #undef TARGET_ASM_FUNCTION_EPILOGUE
289 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
291 #undef TARGET_ASM_OUTPUT_MI_THUNK
292 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
297 #undef TARGET_ASM_FILE_START
298 #define TARGET_ASM_FILE_START sh_file_start
299 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
300 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
302 #undef TARGET_DEFAULT_TARGET_FLAGS
303 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
304 #undef TARGET_HANDLE_OPTION
305 #define TARGET_HANDLE_OPTION sh_handle_option
307 #undef TARGET_INSERT_ATTRIBUTES
308 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
310 #undef TARGET_SCHED_ADJUST_COST
311 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
316 /* The next 5 hooks have been implemented for reenabling sched1. With the
317 help of these macros we are limiting the movement of insns in sched1 to
318 reduce the register pressure. The overall idea is to keep count of SImode
319 and SFmode regs required by already scheduled insns. When these counts
320 cross some threshold values; give priority to insns that free registers.
321 The insn that frees registers is most likely to be the insn with lowest
322 LUID (original insn order); but such an insn might be there in the stalled
323 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
324 upto a max of 8 cycles so that such insns may move from Q -> R.
326 The description of the hooks are as below:
328 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
329 scheduler; it is called inside the sched_init function just after
330 find_insn_reg_weights function call. It is used to calculate the SImode
331 and SFmode weights of insns of basic blocks; much similar to what
332 find_insn_reg_weights does.
333 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
335 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
336 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
339 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
340 high; reorder the ready queue so that the insn with lowest LUID will be
343 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
344 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
346 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
347 can be returned from TARGET_SCHED_REORDER2.
349 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
351 #undef TARGET_SCHED_DFA_NEW_CYCLE
352 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
354 #undef TARGET_SCHED_INIT_GLOBAL
355 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
357 #undef TARGET_SCHED_FINISH_GLOBAL
358 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
360 #undef TARGET_SCHED_VARIABLE_ISSUE
361 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
363 #undef TARGET_SCHED_REORDER
364 #define TARGET_SCHED_REORDER sh_reorder
366 #undef TARGET_SCHED_REORDER2
367 #define TARGET_SCHED_REORDER2 sh_reorder2
369 #undef TARGET_SCHED_INIT
370 #define TARGET_SCHED_INIT sh_md_init
372 #undef TARGET_CANNOT_MODIFY_JUMPS_P
373 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
374 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
375 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
376 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
377 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
378 sh_optimize_target_register_callee_saved
380 #undef TARGET_MS_BITFIELD_LAYOUT_P
381 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
383 #undef TARGET_INIT_BUILTINS
384 #define TARGET_INIT_BUILTINS sh_init_builtins
385 #undef TARGET_EXPAND_BUILTIN
386 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
388 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
389 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
391 #undef TARGET_CANNOT_COPY_INSN_P
392 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
393 #undef TARGET_RTX_COSTS
394 #define TARGET_RTX_COSTS sh_rtx_costs
395 #undef TARGET_ADDRESS_COST
396 #define TARGET_ADDRESS_COST sh_address_cost
397 #undef TARGET_ALLOCATE_INITIAL_VALUE
398 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
400 #undef TARGET_MACHINE_DEPENDENT_REORG
401 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
404 #undef TARGET_HAVE_TLS
405 #define TARGET_HAVE_TLS true
408 #undef TARGET_PROMOTE_PROTOTYPES
409 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
410 #undef TARGET_PROMOTE_FUNCTION_ARGS
411 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
412 #undef TARGET_PROMOTE_FUNCTION_RETURN
413 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
415 #undef TARGET_STRUCT_VALUE_RTX
416 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
417 #undef TARGET_RETURN_IN_MEMORY
418 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
420 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
421 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
422 #undef TARGET_SETUP_INCOMING_VARARGS
423 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
424 #undef TARGET_STRICT_ARGUMENT_NAMING
425 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
426 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
427 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
428 #undef TARGET_MUST_PASS_IN_STACK
429 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
430 #undef TARGET_PASS_BY_REFERENCE
431 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
432 #undef TARGET_CALLEE_COPIES
433 #define TARGET_CALLEE_COPIES sh_callee_copies
434 #undef TARGET_ARG_PARTIAL_BYTES
435 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
437 #undef TARGET_BUILD_BUILTIN_VA_LIST
438 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
439 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
440 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
442 #undef TARGET_VECTOR_MODE_SUPPORTED_P
443 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
445 #undef TARGET_CHECK_PCH_TARGET_FLAGS
446 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
448 #undef TARGET_DWARF_CALLING_CONVENTION
449 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
451 /* Return regmode weight for insn. */
452 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
454 /* Return current register pressure for regmode. */
455 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
459 #undef TARGET_ENCODE_SECTION_INFO
460 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
461 #undef TARGET_STRIP_NAME_ENCODING
462 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
463 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
464 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
468 #undef TARGET_SECONDARY_RELOAD
469 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
471 struct gcc_target targetm = TARGET_INITIALIZER;
473 /* Implement TARGET_HANDLE_OPTION. */
476 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
477 int value ATTRIBUTE_UNUSED)
482 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
486 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
490 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
494 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
498 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
501 case OPT_m2a_single_only:
502 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
506 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
510 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
514 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
521 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
525 case OPT_m4_100_nofpu:
526 case OPT_m4_200_nofpu:
527 case OPT_m4_300_nofpu:
531 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
535 case OPT_m4_100_single:
536 case OPT_m4_200_single:
537 case OPT_m4_300_single:
538 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
541 case OPT_m4_single_only:
542 case OPT_m4_100_single_only:
543 case OPT_m4_200_single_only:
544 case OPT_m4_300_single_only:
545 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
549 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
554 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
558 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
561 case OPT_m4a_single_only:
562 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
566 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
569 case OPT_m5_32media_nofpu:
570 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
574 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
577 case OPT_m5_64media_nofpu:
578 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
582 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
585 case OPT_m5_compact_nofpu:
586 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
594 /* Print the operand address in x to the stream. */
597 print_operand_address (FILE *stream, rtx x)
599 switch (GET_CODE (x))
603 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
608 rtx base = XEXP (x, 0);
609 rtx index = XEXP (x, 1);
611 switch (GET_CODE (index))
614 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
615 reg_names[true_regnum (base)]);
621 int base_num = true_regnum (base);
622 int index_num = true_regnum (index);
624 fprintf (stream, "@(r0,%s)",
625 reg_names[MAX (base_num, index_num)]);
636 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
640 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
644 x = mark_constant_pool_use (x);
645 output_addr_const (stream, x);
650 /* Print operand x (an rtx) in assembler syntax to file stream
651 according to modifier code.
653 '.' print a .s if insn needs delay slot
654 ',' print LOCAL_LABEL_PREFIX
655 '@' print trap, rte or rts depending upon pragma interruptness
656 '#' output a nop if there is nothing to put in the delay slot
657 ''' print likelihood suffix (/u for unlikely).
658 '>' print branch target if -fverbose-asm
659 'O' print a constant without the #
660 'R' print the LSW of a dp value - changes if in little endian
661 'S' print the MSW of a dp value - changes if in little endian
662 'T' print the next word of a dp value - same as 'R' in big endian mode.
663 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
664 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
665 'N' print 'r63' if the operand is (const_int 0).
666 'd' print a V2SF reg as dN instead of fpN.
667 'm' print a pair `base,offset' or `base,index', for LD and ST.
668 'U' Likewise for {LD,ST}{HI,LO}.
669 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
670 'o' output an operator. */
673 print_operand (FILE *stream, rtx x, int code)
676 enum machine_mode mode;
684 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
685 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
686 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
689 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
692 trapa_attr = lookup_attribute ("trap_exit",
693 DECL_ATTRIBUTES (current_function_decl));
695 fprintf (stream, "trapa #%ld",
696 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
697 else if (sh_cfun_interrupt_handler_p ())
698 fprintf (stream, "rte");
700 fprintf (stream, "rts");
703 /* Output a nop if there's nothing in the delay slot. */
704 if (dbr_sequence_length () == 0)
705 fprintf (stream, "\n\tnop");
709 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
711 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
712 fputs ("/u", stream);
716 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
718 fputs ("\t! target: ", stream);
719 output_addr_const (stream, JUMP_LABEL (current_output_insn));
723 x = mark_constant_pool_use (x);
724 output_addr_const (stream, x);
726 /* N.B.: %R / %S / %T adjust memory addresses by four.
727 For SHMEDIA, that means they can be used to access the first and
728 second 32 bit part of a 64 bit (or larger) value that
729 might be held in floating point registers or memory.
730 While they can be used to access 64 bit parts of a larger value
731 held in general purpose registers, that won't work with memory -
732 neither for fp registers, since the frxx names are used. */
734 if (REG_P (x) || GET_CODE (x) == SUBREG)
736 regno = true_regnum (x);
737 regno += FP_REGISTER_P (regno) ? 1 : LSW;
738 fputs (reg_names[regno], (stream));
742 x = adjust_address (x, SImode, 4 * LSW);
743 print_operand_address (stream, XEXP (x, 0));
750 if (mode == VOIDmode)
752 if (GET_MODE_SIZE (mode) >= 8)
753 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
755 print_operand (stream, sub, 0);
757 output_operand_lossage ("invalid operand to %%R");
761 if (REG_P (x) || GET_CODE (x) == SUBREG)
763 regno = true_regnum (x);
764 regno += FP_REGISTER_P (regno) ? 0 : MSW;
765 fputs (reg_names[regno], (stream));
769 x = adjust_address (x, SImode, 4 * MSW);
770 print_operand_address (stream, XEXP (x, 0));
777 if (mode == VOIDmode)
779 if (GET_MODE_SIZE (mode) >= 8)
780 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
782 print_operand (stream, sub, 0);
784 output_operand_lossage ("invalid operand to %%S");
788 /* Next word of a double. */
789 switch (GET_CODE (x))
792 fputs (reg_names[REGNO (x) + 1], (stream));
795 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
796 && GET_CODE (XEXP (x, 0)) != POST_INC)
797 x = adjust_address (x, SImode, 4);
798 print_operand_address (stream, XEXP (x, 0));
805 switch (GET_CODE (x))
807 case PLUS: fputs ("add", stream); break;
808 case MINUS: fputs ("sub", stream); break;
809 case MULT: fputs ("mul", stream); break;
810 case DIV: fputs ("div", stream); break;
811 case EQ: fputs ("eq", stream); break;
812 case NE: fputs ("ne", stream); break;
813 case GT: case LT: fputs ("gt", stream); break;
814 case GE: case LE: fputs ("ge", stream); break;
815 case GTU: case LTU: fputs ("gtu", stream); break;
816 case GEU: case LEU: fputs ("geu", stream); break;
824 if (GET_CODE (x) == MEM
825 && GET_CODE (XEXP (x, 0)) == PLUS
826 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
827 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
832 if (GET_CODE (x) == MEM)
834 switch (GET_MODE (x))
836 case QImode: fputs (".b", stream); break;
837 case HImode: fputs (".w", stream); break;
838 case SImode: fputs (".l", stream); break;
839 case SFmode: fputs (".s", stream); break;
840 case DFmode: fputs (".d", stream); break;
841 default: gcc_unreachable ();
848 gcc_assert (GET_CODE (x) == MEM);
852 switch (GET_CODE (x))
856 print_operand (stream, x, 0);
857 fputs (", 0", stream);
861 print_operand (stream, XEXP (x, 0), 0);
862 fputs (", ", stream);
863 print_operand (stream, XEXP (x, 1), 0);
872 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
874 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
878 if (x == CONST0_RTX (GET_MODE (x)))
880 fprintf ((stream), "r63");
885 if (GET_CODE (x) == CONST_INT)
887 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
897 switch (GET_CODE (x))
901 rtx inner = XEXP (x, 0);
903 enum machine_mode inner_mode;
905 /* We might see SUBREGs with vector mode registers inside. */
906 if (GET_CODE (inner) == SUBREG
907 && (GET_MODE_SIZE (GET_MODE (inner))
908 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
909 && subreg_lowpart_p (inner))
910 inner = SUBREG_REG (inner);
911 if (GET_CODE (inner) == CONST_INT)
913 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
916 inner_mode = GET_MODE (inner);
917 if (GET_CODE (inner) == SUBREG
918 && (GET_MODE_SIZE (GET_MODE (inner))
919 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
920 && GET_CODE (SUBREG_REG (inner)) == REG)
922 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
923 GET_MODE (SUBREG_REG (inner)),
926 inner = SUBREG_REG (inner);
928 if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8)
930 /* Floating point register pairs are always big endian;
931 general purpose registers are 64 bit wide. */
932 regno = REGNO (inner);
933 regno = (HARD_REGNO_NREGS (regno, inner_mode)
934 - HARD_REGNO_NREGS (regno, mode))
942 /* FIXME: We need this on SHmedia32 because reload generates
943 some sign-extended HI or QI loads into DImode registers
944 but, because Pmode is SImode, the address ends up with a
945 subreg:SI of the DImode register. Maybe reload should be
946 fixed so as to apply alter_subreg to such loads? */
948 gcc_assert (trapping_target_operand (x, VOIDmode));
949 x = XEXP (XEXP (x, 2), 0);
952 gcc_assert (SUBREG_BYTE (x) == 0
953 && GET_CODE (SUBREG_REG (x)) == REG);
961 if (FP_REGISTER_P (regno)
962 && mode == V16SFmode)
963 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
964 else if (FP_REGISTER_P (REGNO (x))
966 fprintf ((stream), "fv%s", reg_names[regno] + 2);
967 else if (GET_CODE (x) == REG
969 fprintf ((stream), "fp%s", reg_names[regno] + 2);
970 else if (FP_REGISTER_P (REGNO (x))
971 && GET_MODE_SIZE (mode) > 4)
972 fprintf ((stream), "d%s", reg_names[regno] + 1);
974 fputs (reg_names[regno], (stream));
978 output_address (XEXP (x, 0));
983 && (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
984 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
985 && (GET_MODE (XEXP (x, 0)) == DImode
986 || GET_MODE (XEXP (x, 0)) == SImode)
987 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
988 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
990 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
992 bool nested_expr = false;
995 if (GET_CODE (val) == ASHIFTRT)
998 val2 = XEXP (val, 0);
1000 if (GET_CODE (val2) == CONST
1001 || GET_RTX_CLASS (GET_CODE (val2)) != RTX_OBJ)
1003 fputc ('(', stream);
1006 output_addr_const (stream, val2);
1008 fputc (')', stream);
1009 if (GET_CODE (val) == ASHIFTRT)
1011 fputs (" >> ", stream);
1012 output_addr_const (stream, XEXP (val, 1));
1013 fputc (')', stream);
1015 fputs (" & 65535)", stream);
1022 fputc ('#', stream);
1023 output_addr_const (stream, x);
1030 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1032 force_into (rtx value, rtx target)
1034 value = force_operand (value, target);
1035 if (! rtx_equal_p (value, target))
1036 emit_insn (gen_move_insn (target, value));
1039 /* Emit code to perform a block move. Choose the best method.
1041 OPERANDS[0] is the destination.
1042 OPERANDS[1] is the source.
1043 OPERANDS[2] is the size.
1044 OPERANDS[3] is the alignment safe to use. */
1047 expand_block_move (rtx *operands)
1049 int align = INTVAL (operands[3]);
1050 int constp = (GET_CODE (operands[2]) == CONST_INT);
1051 int bytes = (constp ? INTVAL (operands[2]) : 0);
1056 /* If we could use mov.l to move words and dest is word-aligned, we
1057 can use movua.l for loads and still generate a relatively short
1058 and efficient sequence. */
1059 if (TARGET_SH4A_ARCH && align < 4
1060 && MEM_ALIGN (operands[0]) >= 32
1061 && can_move_by_pieces (bytes, 32))
1063 rtx dest = copy_rtx (operands[0]);
1064 rtx src = copy_rtx (operands[1]);
1065 /* We could use different pseudos for each copied word, but
1066 since movua can only load into r0, it's kind of
1068 rtx temp = gen_reg_rtx (SImode);
1069 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1072 while (copied + 4 <= bytes)
1074 rtx to = adjust_address (dest, SImode, copied);
1075 rtx from = adjust_automodify_address (src, BLKmode,
1078 set_mem_size (from, GEN_INT (4));
1079 emit_insn (gen_movua (temp, from));
1080 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1081 emit_move_insn (to, temp);
1086 move_by_pieces (adjust_address (dest, BLKmode, copied),
1087 adjust_automodify_address (src, BLKmode,
1089 bytes - copied, align, 0);
1094 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1095 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1096 if (align < 4 || (bytes % 4 != 0))
1099 if (TARGET_HARD_SH4)
1103 else if (bytes == 12)
1105 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1106 rtx r4 = gen_rtx_REG (SImode, 4);
1107 rtx r5 = gen_rtx_REG (SImode, 5);
1109 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1110 force_into (XEXP (operands[0], 0), r4);
1111 force_into (XEXP (operands[1], 0), r5);
1112 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1115 else if (! TARGET_SMALLCODE)
1117 const char *entry_name;
1118 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1120 rtx r4 = gen_rtx_REG (SImode, 4);
1121 rtx r5 = gen_rtx_REG (SImode, 5);
1122 rtx r6 = gen_rtx_REG (SImode, 6);
1124 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1125 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1126 force_into (XEXP (operands[0], 0), r4);
1127 force_into (XEXP (operands[1], 0), r5);
1129 dwords = bytes >> 3;
1130 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1131 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1140 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1141 rtx r4 = gen_rtx_REG (SImode, 4);
1142 rtx r5 = gen_rtx_REG (SImode, 5);
1144 sprintf (entry, "__movmemSI%d", bytes);
1145 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1146 force_into (XEXP (operands[0], 0), r4);
1147 force_into (XEXP (operands[1], 0), r5);
1148 emit_insn (gen_block_move_real (func_addr_rtx));
1152 /* This is the same number of bytes as a memcpy call, but to a different
1153 less common function name, so this will occasionally use more space. */
1154 if (! TARGET_SMALLCODE)
1156 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1157 int final_switch, while_loop;
1158 rtx r4 = gen_rtx_REG (SImode, 4);
1159 rtx r5 = gen_rtx_REG (SImode, 5);
1160 rtx r6 = gen_rtx_REG (SImode, 6);
1162 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1163 force_into (XEXP (operands[0], 0), r4);
1164 force_into (XEXP (operands[1], 0), r5);
1166 /* r6 controls the size of the move. 16 is decremented from it
1167 for each 64 bytes moved. Then the negative bit left over is used
1168 as an index into a list of move instructions. e.g., a 72 byte move
1169 would be set up with size(r6) = 14, for one iteration through the
1170 big while loop, and a switch of -2 for the last part. */
1172 final_switch = 16 - ((bytes / 4) % 16);
1173 while_loop = ((bytes / 4) / 16 - 1) * 16;
1174 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1175 emit_insn (gen_block_lump_real (func_addr_rtx));
1182 /* Prepare operands for a move define_expand; specifically, one of the
1183 operands must be in a register. */
1186 prepare_move_operands (rtx operands[], enum machine_mode mode)
1188 if ((mode == SImode || mode == DImode)
1190 && ! ((mode == Pmode || mode == ptr_mode)
1191 && tls_symbolic_operand (operands[1], Pmode) != 0))
1194 if (SYMBOLIC_CONST_P (operands[1]))
1196 if (GET_CODE (operands[0]) == MEM)
1197 operands[1] = force_reg (Pmode, operands[1]);
1198 else if (TARGET_SHMEDIA
1199 && GET_CODE (operands[1]) == LABEL_REF
1200 && target_reg_operand (operands[0], mode))
1204 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
1205 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1208 else if (GET_CODE (operands[1]) == CONST
1209 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1210 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1212 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
1213 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1215 operands[1] = expand_binop (mode, add_optab, temp,
1216 XEXP (XEXP (operands[1], 0), 1),
1217 no_new_pseudos ? temp
1218 : gen_reg_rtx (Pmode),
1219 0, OPTAB_LIB_WIDEN);
1223 if (! reload_in_progress && ! reload_completed)
1225 /* Copy the source to a register if both operands aren't registers. */
1226 if (! register_operand (operands[0], mode)
1227 && ! sh_register_operand (operands[1], mode))
1228 operands[1] = copy_to_mode_reg (mode, operands[1]);
1230 if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode))
1232 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1233 except that we can't use that function because it is static. */
1234 rtx new = change_address (operands[0], mode, 0);
1235 MEM_COPY_ATTRIBUTES (new, operands[0]);
1239 /* This case can happen while generating code to move the result
1240 of a library call to the target. Reject `st r0,@(rX,rY)' because
1241 reload will fail to find a spill register for rX, since r0 is already
1242 being used for the source. */
1244 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1245 && GET_CODE (operands[0]) == MEM
1246 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1247 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
1248 operands[1] = copy_to_mode_reg (mode, operands[1]);
1251 if (mode == Pmode || mode == ptr_mode)
1254 enum tls_model tls_kind;
1258 if (GET_CODE (op1) == CONST
1259 && GET_CODE (XEXP (op1, 0)) == PLUS
1260 && tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode))
1262 opc = XEXP (XEXP (op1, 0), 1);
1263 op1 = XEXP (XEXP (op1, 0), 0);
1268 if ((tls_kind = tls_symbolic_operand (op1, Pmode)))
1270 rtx tga_op1, tga_ret, tmp, tmp2;
1274 case TLS_MODEL_GLOBAL_DYNAMIC:
1275 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1276 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1280 case TLS_MODEL_LOCAL_DYNAMIC:
1281 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1282 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1284 tmp = gen_reg_rtx (Pmode);
1285 emit_move_insn (tmp, tga_ret);
1287 if (register_operand (op0, Pmode))
1290 tmp2 = gen_reg_rtx (Pmode);
1292 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1296 case TLS_MODEL_INITIAL_EXEC:
1299 /* Don't schedule insns for getting GOT address when
1300 the first scheduling is enabled, to avoid spill
1302 if (flag_schedule_insns)
1303 emit_insn (gen_blockage ());
1304 emit_insn (gen_GOTaddr2picreg ());
1305 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode,
1307 if (flag_schedule_insns)
1308 emit_insn (gen_blockage ());
1310 tga_op1 = no_new_pseudos ? op0 : gen_reg_rtx (Pmode);
1311 tmp = gen_sym2GOTTPOFF (op1);
1312 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1316 case TLS_MODEL_LOCAL_EXEC:
1317 tmp2 = gen_reg_rtx (Pmode);
1318 emit_insn (gen_load_gbr (tmp2));
1319 tmp = gen_reg_rtx (Pmode);
1320 emit_insn (gen_symTPOFF2reg (tmp, op1));
1322 if (register_operand (op0, Pmode))
1325 op1 = gen_reg_rtx (Pmode);
1327 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1334 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1343 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1344 enum rtx_code comparison)
1347 rtx scratch = NULL_RTX;
1349 if (comparison == CODE_FOR_nothing)
1350 comparison = GET_CODE (operands[0]);
1352 scratch = operands[4];
1353 if (GET_CODE (operands[1]) == CONST_INT
1354 && GET_CODE (operands[2]) != CONST_INT)
1356 rtx tmp = operands[1];
1358 operands[1] = operands[2];
1360 comparison = swap_condition (comparison);
1362 if (GET_CODE (operands[2]) == CONST_INT)
1364 HOST_WIDE_INT val = INTVAL (operands[2]);
1365 if ((val == -1 || val == -0x81)
1366 && (comparison == GT || comparison == LE))
1368 comparison = (comparison == GT) ? GE : LT;
1369 operands[2] = gen_int_mode (val + 1, mode);
1371 else if ((val == 1 || val == 0x80)
1372 && (comparison == GE || comparison == LT))
1374 comparison = (comparison == GE) ? GT : LE;
1375 operands[2] = gen_int_mode (val - 1, mode);
1377 else if (val == 1 && (comparison == GEU || comparison == LTU))
1379 comparison = (comparison == GEU) ? NE : EQ;
1380 operands[2] = CONST0_RTX (mode);
1382 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1384 comparison = (comparison == GEU) ? GTU : LEU;
1385 operands[2] = gen_int_mode (val - 1, mode);
1387 else if (val == 0 && (comparison == GTU || comparison == LEU))
1388 comparison = (comparison == GTU) ? NE : EQ;
1389 else if (mode == SImode
1390 && ((val == 0x7fffffff
1391 && (comparison == GTU || comparison == LEU))
1392 || ((unsigned HOST_WIDE_INT) val
1393 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1394 && (comparison == GEU || comparison == LTU))))
1396 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1397 operands[2] = CONST0_RTX (mode);
1401 if (!no_new_pseudos)
1402 operands[1] = force_reg (mode, op1);
1403 /* When we are handling DImode comparisons, we want to keep constants so
1404 that we can optimize the component comparisons; however, memory loads
1405 are better issued as a whole so that they can be scheduled well.
1406 SImode equality comparisons allow I08 constants, but only when they
1407 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1408 into a register, that register might as well be r0, and we allow the
1409 constant. If it is already in a register, this is likely to be
1410 allocated to a different hard register, thus we load the constant into
1411 a register unless it is zero. */
1412 if (!REG_P (operands[2])
1413 && (GET_CODE (operands[2]) != CONST_INT
1414 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1415 && ((comparison != EQ && comparison != NE)
1416 || (REG_P (op1) && REGNO (op1) != R0_REG)
1417 || !CONST_OK_FOR_I08 (INTVAL (operands[2]))))))
1419 if (scratch && GET_MODE (scratch) == mode)
1421 emit_move_insn (scratch, operands[2]);
1422 operands[2] = scratch;
1424 else if (!no_new_pseudos)
1425 operands[2] = force_reg (mode, operands[2]);
1431 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1433 rtx (*branch_expander) (rtx) = gen_branch_true;
1436 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1439 case NE: case LT: case LE: case LTU: case LEU:
1440 comparison = reverse_condition (comparison);
1441 branch_expander = gen_branch_false;
1444 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1445 gen_rtx_fmt_ee (comparison, SImode,
1446 operands[1], operands[2])));
1447 jump = emit_jump_insn (branch_expander (operands[3]));
1448 if (probability >= 0)
1450 = gen_rtx_EXPR_LIST (REG_BR_PROB, GEN_INT (probability),
1455 /* ??? How should we distribute probabilities when more than one branch
1456 is generated. So far we only have soem ad-hoc observations:
1457 - If the operands are random, they are likely to differ in both parts.
1458 - If comparing items in a hash chain, the operands are random or equal;
1459 operation should be EQ or NE.
1460 - If items are searched in an ordered tree from the root, we can expect
1461 the highpart to be unequal about half of the time; operation should be
1462 an inequality comparison, operands non-constant, and overall probability
1463 about 50%. Likewise for quicksort.
1464 - Range checks will be often made against constants. Even if we assume for
1465 simplicity an even distribution of the non-constant operand over a
1466 sub-range here, the same probability could be generated with differently
1467 wide sub-ranges - as long as the ratio of the part of the subrange that
1468 is before the threshold to the part that comes after the threshold stays
1469 the same. Thus, we can't really tell anything here;
1470 assuming random distribution is at least simple.
1474 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1476 enum rtx_code msw_taken, msw_skip, lsw_taken;
1477 rtx skip_label = NULL_RTX;
1478 rtx op1h, op1l, op2h, op2l;
1481 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1482 rtx scratch = operands[4];
1484 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1485 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1486 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1487 op1l = gen_lowpart (SImode, operands[1]);
1488 op2l = gen_lowpart (SImode, operands[2]);
1489 msw_taken = msw_skip = lsw_taken = CODE_FOR_nothing;
1490 prob = split_branch_probability;
1491 rev_prob = REG_BR_PROB_BASE - prob;
1494 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1495 That costs 1 cycle more when the first branch can be predicted taken,
1496 but saves us mispredicts because only one branch needs prediction.
1497 It also enables generating the cmpeqdi_t-1 pattern. */
1499 if (TARGET_CMPEQDI_T)
1501 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1502 emit_jump_insn (gen_branch_true (operands[3]));
1509 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1511 msw_skip_prob = rev_prob;
1512 if (REG_BR_PROB_BASE <= 65535)
1513 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1516 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1520 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1521 / ((HOST_WIDEST_INT) prob << 32)))
1527 if (TARGET_CMPEQDI_T)
1529 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1530 emit_jump_insn (gen_branch_false (operands[3]));
1534 msw_taken_prob = prob;
1539 msw_taken = comparison;
1540 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1542 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1543 msw_skip = swap_condition (msw_taken);
1547 if (op2l == CONST0_RTX (SImode))
1548 msw_taken = comparison;
1551 msw_taken = comparison == GE ? GT : GTU;
1552 msw_skip = swap_condition (msw_taken);
1557 msw_taken = comparison;
1558 if (op2l == CONST0_RTX (SImode))
1560 msw_skip = swap_condition (msw_taken);
1564 if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1)
1565 msw_taken = comparison;
1569 if (comparison == LE)
1571 else if (op2h != CONST0_RTX (SImode))
1575 msw_skip = swap_condition (msw_taken);
1578 default: return false;
1580 num_branches = ((msw_taken != CODE_FOR_nothing)
1581 + (msw_skip != CODE_FOR_nothing)
1582 + (lsw_taken != CODE_FOR_nothing));
1583 if (comparison != EQ && comparison != NE && num_branches > 1)
1585 if (!CONSTANT_P (operands[2])
1586 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1587 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1589 msw_taken_prob = prob / 2U;
1591 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1592 lsw_taken_prob = prob;
1596 msw_taken_prob = prob;
1597 msw_skip_prob = REG_BR_PROB_BASE;
1598 /* ??? If we have a constant op2h, should we use that when
1599 calculating lsw_taken_prob? */
1600 lsw_taken_prob = prob;
1605 operands[4] = NULL_RTX;
1606 if (reload_completed
1607 && ! arith_reg_or_0_operand (op2h, SImode) && true_regnum (op1h)
1608 && (msw_taken != CODE_FOR_nothing || msw_skip != CODE_FOR_nothing))
1610 emit_move_insn (scratch, operands[2]);
1611 operands[2] = scratch;
1613 if (msw_taken != CODE_FOR_nothing)
1614 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1615 if (msw_skip != CODE_FOR_nothing)
1617 rtx taken_label = operands[3];
1619 operands[3] = skip_label = gen_label_rtx ();
1620 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1621 operands[3] = taken_label;
1625 if (lsw_taken != CODE_FOR_nothing)
1627 if (reload_completed
1628 && ! arith_reg_or_0_operand (op2l, SImode) && true_regnum (op1l))
1629 operands[4] = scratch;
1630 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1632 if (msw_skip != CODE_FOR_nothing)
1633 emit_label (skip_label);
1637 /* Prepare the operands for an scc instruction; make sure that the
1638 compare has been done. */
1640 prepare_scc_operands (enum rtx_code code)
1642 rtx t_reg = gen_rtx_REG (SImode, T_REG);
1643 enum rtx_code oldcode = code;
1644 enum machine_mode mode;
1646 /* First need a compare insn. */
1650 /* It isn't possible to handle this case. */
1667 if (code != oldcode)
1669 rtx tmp = sh_compare_op0;
1670 sh_compare_op0 = sh_compare_op1;
1671 sh_compare_op1 = tmp;
1674 mode = GET_MODE (sh_compare_op0);
1675 if (mode == VOIDmode)
1676 mode = GET_MODE (sh_compare_op1);
1678 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1679 if ((code != EQ && code != NE
1680 && (sh_compare_op1 != const0_rtx
1681 || code == GTU || code == GEU || code == LTU || code == LEU))
1682 || (mode == DImode && sh_compare_op1 != const0_rtx)
1683 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1684 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1686 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1687 (mode == SFmode ? emit_sf_insn : emit_df_insn)
1688 (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1689 gen_rtx_SET (VOIDmode, t_reg,
1690 gen_rtx_fmt_ee (code, SImode,
1691 sh_compare_op0, sh_compare_op1)),
1692 gen_rtx_USE (VOIDmode, get_fpscr_rtx ()))));
1694 emit_insn (gen_rtx_SET (VOIDmode, t_reg,
1695 gen_rtx_fmt_ee (code, SImode,
1696 sh_compare_op0, sh_compare_op1)));
1701 /* Called from the md file, set up the operands of a compare instruction. */
1704 from_compare (rtx *operands, int code)
1706 enum machine_mode mode = GET_MODE (sh_compare_op0);
1708 if (mode == VOIDmode)
1709 mode = GET_MODE (sh_compare_op1);
1712 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1714 /* Force args into regs, since we can't use constants here. */
1715 sh_compare_op0 = force_reg (mode, sh_compare_op0);
1716 if (sh_compare_op1 != const0_rtx
1717 || code == GTU || code == GEU
1718 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
1719 sh_compare_op1 = force_reg (mode, sh_compare_op1);
1721 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
1723 from_compare (operands, GT);
1724 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
1727 insn = gen_rtx_SET (VOIDmode,
1728 gen_rtx_REG (SImode, T_REG),
1729 gen_rtx_fmt_ee (code, SImode,
1730 sh_compare_op0, sh_compare_op1));
1731 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1733 insn = gen_rtx_PARALLEL (VOIDmode,
1735 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1736 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1742 /* Functions to output assembly code. */
1744 /* Return a sequence of instructions to perform DI or DF move.
1746 Since the SH cannot move a DI or DF in one instruction, we have
1747 to take care when we see overlapping source and dest registers. */
1750 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1751 enum machine_mode mode)
1753 rtx dst = operands[0];
1754 rtx src = operands[1];
1756 if (GET_CODE (dst) == MEM
1757 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
1758 return "mov.l %T1,%0\n\tmov.l %1,%0";
1760 if (register_operand (dst, mode)
1761 && register_operand (src, mode))
1763 if (REGNO (src) == MACH_REG)
1764 return "sts mach,%S0\n\tsts macl,%R0";
1766 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1767 when mov.d r1,r0 do r1->r0 then r2->r1. */
1769 if (REGNO (src) + 1 == REGNO (dst))
1770 return "mov %T1,%T0\n\tmov %1,%0";
1772 return "mov %1,%0\n\tmov %T1,%T0";
1774 else if (GET_CODE (src) == CONST_INT)
1776 if (INTVAL (src) < 0)
1777 output_asm_insn ("mov #-1,%S0", operands);
1779 output_asm_insn ("mov #0,%S0", operands);
1781 return "mov %1,%R0";
1783 else if (GET_CODE (src) == MEM)
1786 int dreg = REGNO (dst);
1787 rtx inside = XEXP (src, 0);
1789 switch (GET_CODE (inside))
1792 ptrreg = REGNO (inside);
1796 ptrreg = subreg_regno (inside);
1800 ptrreg = REGNO (XEXP (inside, 0));
1801 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1802 an offsettable address. Unfortunately, offsettable addresses use
1803 QImode to check the offset, and a QImode offsettable address
1804 requires r0 for the other operand, which is not currently
1805 supported, so we can't use the 'o' constraint.
1806 Thus we must check for and handle r0+REG addresses here.
1807 We punt for now, since this is likely very rare. */
1808 gcc_assert (GET_CODE (XEXP (inside, 1)) != REG);
1812 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1814 return "mov.l %1,%0\n\tmov.l %1,%T0";
1819 /* Work out the safe way to copy. Copy into the second half first. */
1821 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1824 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1827 /* Print an instruction which would have gone into a delay slot after
1828 another instruction, but couldn't because the other instruction expanded
1829 into a sequence where putting the slot insn at the end wouldn't work. */
1832 print_slot (rtx insn)
1834 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
1836 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1840 output_far_jump (rtx insn, rtx op)
1842 struct { rtx lab, reg, op; } this;
1843 rtx braf_base_lab = NULL_RTX;
1846 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1849 this.lab = gen_label_rtx ();
1853 && offset - get_attr_length (insn) <= 32766)
1856 jump = "mov.w %O0,%1; braf %1";
1864 jump = "mov.l %O0,%1; braf %1";
1866 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1869 jump = "mov.l %O0,%1; jmp @%1";
1871 /* If we have a scratch register available, use it. */
1872 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1873 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1875 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1876 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1877 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1878 output_asm_insn (jump, &this.lab);
1879 if (dbr_sequence_length ())
1880 print_slot (final_sequence);
1882 output_asm_insn ("nop", 0);
1886 /* Output the delay slot insn first if any. */
1887 if (dbr_sequence_length ())
1888 print_slot (final_sequence);
1890 this.reg = gen_rtx_REG (SImode, 13);
1891 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1892 Fortunately, MACL is fixed and call-clobbered, and we never
1893 need its value across jumps, so save r13 in it instead of in
1896 output_asm_insn ("lds r13, macl", 0);
1898 output_asm_insn ("mov.l r13,@-r15", 0);
1899 output_asm_insn (jump, &this.lab);
1901 output_asm_insn ("sts macl, r13", 0);
1903 output_asm_insn ("mov.l @r15+,r13", 0);
1905 if (far && flag_pic && TARGET_SH2)
1907 braf_base_lab = gen_label_rtx ();
1908 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1909 CODE_LABEL_NUMBER (braf_base_lab));
1912 output_asm_insn (".align 2", 0);
1913 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1915 if (far && flag_pic)
1918 this.lab = braf_base_lab;
1919 output_asm_insn (".long %O2-%O0", &this.lab);
1922 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1926 /* Local label counter, used for constants in the pool and inside
1927 pattern branches. */
1929 static int lf = 100;
1931 /* Output code for ordinary branches. */
1934 output_branch (int logic, rtx insn, rtx *operands)
1936 switch (get_attr_length (insn))
1939 /* This can happen if filling the delay slot has caused a forward
1940 branch to exceed its range (we could reverse it, but only
1941 when we know we won't overextend other branches; this should
1942 best be handled by relaxation).
1943 It can also happen when other condbranches hoist delay slot insn
1944 from their destination, thus leading to code size increase.
1945 But the branch will still be in the range -4092..+4098 bytes. */
1950 /* The call to print_slot will clobber the operands. */
1951 rtx op0 = operands[0];
1953 /* If the instruction in the delay slot is annulled (true), then
1954 there is no delay slot where we can put it now. The only safe
1955 place for it is after the label. final will do that by default. */
1958 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1959 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1961 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1962 ASSEMBLER_DIALECT ? "/" : ".", label);
1963 print_slot (final_sequence);
1966 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1968 output_asm_insn ("bra\t%l0", &op0);
1969 fprintf (asm_out_file, "\tnop\n");
1970 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1974 /* When relaxing, handle this like a short branch. The linker
1975 will fix it up if it still doesn't fit after relaxation. */
1977 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1979 /* These are for SH2e, in which we have to account for the
1980 extra nop because of the hardware bug in annulled branches. */
1986 gcc_assert (!final_sequence
1987 || !(INSN_ANNULLED_BRANCH_P
1988 (XVECEXP (final_sequence, 0, 0))));
1989 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
1991 ASSEMBLER_DIALECT ? "/" : ".", label);
1992 fprintf (asm_out_file, "\tnop\n");
1993 output_asm_insn ("bra\t%l0", operands);
1994 fprintf (asm_out_file, "\tnop\n");
1995 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
1999 /* When relaxing, fall through. */
2004 sprintf (buffer, "b%s%ss\t%%l0",
2006 ASSEMBLER_DIALECT ? "/" : ".");
2007 output_asm_insn (buffer, &operands[0]);
2012 /* There should be no longer branches now - that would
2013 indicate that something has destroyed the branches set
2014 up in machine_dependent_reorg. */
2019 /* Output a code sequence for INSN using TEMPLATE with OPERANDS; but before,
2020 fill in operands 9 as a label to the successor insn.
2021 We try to use jump threading where possible.
2022 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2023 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2024 follow jmp and bt, if the address is in range. */
2026 output_branchy_insn (enum rtx_code code, const char *template,
2027 rtx insn, rtx *operands)
2029 rtx next_insn = NEXT_INSN (insn);
2031 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
2033 rtx src = SET_SRC (PATTERN (next_insn));
2034 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2036 /* Following branch not taken */
2037 operands[9] = gen_label_rtx ();
2038 emit_label_after (operands[9], next_insn);
2039 INSN_ADDRESSES_NEW (operands[9],
2040 INSN_ADDRESSES (INSN_UID (next_insn))
2041 + get_attr_length (next_insn));
2046 int offset = (branch_dest (next_insn)
2047 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2048 if (offset >= -252 && offset <= 258)
2050 if (GET_CODE (src) == IF_THEN_ELSE)
2052 src = XEXP (src, 1);
2058 operands[9] = gen_label_rtx ();
2059 emit_label_after (operands[9], insn);
2060 INSN_ADDRESSES_NEW (operands[9],
2061 INSN_ADDRESSES (INSN_UID (insn))
2062 + get_attr_length (insn));
2067 output_ieee_ccmpeq (rtx insn, rtx *operands)
2069 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2073 /* Output the start of the assembler file. */
2076 sh_file_start (void)
2078 default_file_start ();
2081 /* Declare the .directive section before it is used. */
2082 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2083 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2087 /* We need to show the text section with the proper
2088 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2089 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2090 will complain. We can teach GAS specifically about the
2091 default attributes for our choice of text section, but
2092 then we would have to change GAS again if/when we change
2093 the text section name. */
2094 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2096 /* Switch to the data section so that the coffsem symbol
2097 isn't in the text section. */
2098 switch_to_section (data_section);
2100 if (TARGET_LITTLE_ENDIAN)
2101 fputs ("\t.little\n", asm_out_file);
2105 if (TARGET_SHCOMPACT)
2106 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2107 else if (TARGET_SHMEDIA)
2108 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2109 TARGET_SHMEDIA64 ? 64 : 32);
2113 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2116 unspec_caller_rtx_p (rtx pat)
2118 switch (GET_CODE (pat))
2121 return unspec_caller_rtx_p (XEXP (pat, 0));
2124 if (unspec_caller_rtx_p (XEXP (pat, 0)))
2126 return unspec_caller_rtx_p (XEXP (pat, 1));
2128 if (XINT (pat, 1) == UNSPEC_CALLER)
2137 /* Indicate that INSN cannot be duplicated. This is true for insn
2138 that generates a unique label. */
2141 sh_cannot_copy_insn_p (rtx insn)
2145 if (!reload_completed || !flag_pic)
2148 if (GET_CODE (insn) != INSN)
2150 if (asm_noperands (insn) >= 0)
2153 pat = PATTERN (insn);
2154 if (GET_CODE (pat) != SET)
2156 pat = SET_SRC (pat);
2158 if (unspec_caller_rtx_p (pat))
2164 /* Actual number of instructions used to make a shift by N. */
2165 static const char ashiftrt_insns[] =
2166 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2168 /* Left shift and logical right shift are the same. */
2169 static const char shift_insns[] =
2170 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2172 /* Individual shift amounts needed to get the above length sequences.
2173 One bit right shifts clobber the T bit, so when possible, put one bit
2174 shifts in the middle of the sequence, so the ends are eligible for
2175 branch delay slots. */
2176 static const short shift_amounts[32][5] = {
2177 {0}, {1}, {2}, {2, 1},
2178 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2179 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2180 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2181 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2182 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2183 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2184 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2186 /* Likewise, but for shift amounts < 16, up to three highmost bits
2187 might be clobbered. This is typically used when combined with some
2188 kind of sign or zero extension. */
2190 static const char ext_shift_insns[] =
2191 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2193 static const short ext_shift_amounts[32][4] = {
2194 {0}, {1}, {2}, {2, 1},
2195 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2196 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2197 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2198 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2199 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2200 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2201 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2203 /* Assuming we have a value that has been sign-extended by at least one bit,
2204 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2205 to shift it by N without data loss, and quicker than by other means? */
2206 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2208 /* This is used in length attributes in sh.md to help compute the length
2209 of arbitrary constant shift instructions. */
2212 shift_insns_rtx (rtx insn)
2214 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2215 int shift_count = INTVAL (XEXP (set_src, 1));
2216 enum rtx_code shift_code = GET_CODE (set_src);
2221 return ashiftrt_insns[shift_count];
2224 return shift_insns[shift_count];
2230 /* Return the cost of a shift. */
2240 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2242 if (GET_MODE (x) == DImode
2243 && GET_CODE (XEXP (x, 1)) == CONST_INT
2244 && INTVAL (XEXP (x, 1)) == 1)
2247 /* Everything else is invalid, because there is no pattern for it. */
2250 /* If shift by a non constant, then this will be expensive. */
2251 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2252 return SH_DYNAMIC_SHIFT_COST;
2254 value = INTVAL (XEXP (x, 1));
2256 /* Otherwise, return the true cost in instructions. */
2257 if (GET_CODE (x) == ASHIFTRT)
2259 int cost = ashiftrt_insns[value];
2260 /* If SH3, then we put the constant in a reg and use shad. */
2261 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2262 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2266 return shift_insns[value];
2269 /* Return the cost of an AND operation. */
2276 /* Anding with a register is a single cycle and instruction. */
2277 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2280 i = INTVAL (XEXP (x, 1));
2284 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2285 && (CONST_OK_FOR_I10 (INTVAL (XEXP (x, 1)))
2286 || CONST_OK_FOR_J16 (INTVAL (XEXP (x, 1)))))
2289 return 1 + rtx_cost (XEXP (x, 1), AND);
2292 /* These constants are single cycle extu.[bw] instructions. */
2293 if (i == 0xff || i == 0xffff)
2295 /* Constants that can be used in an and immediate instruction in a single
2296 cycle, but this requires r0, so make it a little more expensive. */
2297 if (CONST_OK_FOR_K08 (i))
2299 /* Constants that can be loaded with a mov immediate and an and.
2300 This case is probably unnecessary. */
2301 if (CONST_OK_FOR_I08 (i))
2303 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2304 This case is probably unnecessary. */
2308 /* Return the cost of an addition or a subtraction. */
2313 /* Adding a register is a single cycle insn. */
2314 if (GET_CODE (XEXP (x, 1)) == REG
2315 || GET_CODE (XEXP (x, 1)) == SUBREG)
2318 /* Likewise for small constants. */
2319 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2320 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2324 switch (GET_CODE (XEXP (x, 1)))
2329 return TARGET_SHMEDIA64 ? 5 : 3;
2332 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2334 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2336 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2344 /* Any other constant requires a 2 cycle pc-relative load plus an
2349 /* Return the cost of a multiply. */
2351 multcosts (rtx x ATTRIBUTE_UNUSED)
2353 if (sh_multcost >= 0)
2356 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2357 accept constants. Ideally, we would use a cost of one or two and
2358 add the cost of the operand, but disregard the latter when inside loops
2359 and loop invariant code motion is still to follow.
2360 Using a multiply first and splitting it later if it's a loss
2361 doesn't work because of different sign / zero extension semantics
2362 of multiplies vs. shifts. */
2363 return TARGET_SMALLCODE ? 2 : 3;
2367 /* We have a mul insn, so we can never take more than the mul and the
2368 read of the mac reg, but count more because of the latency and extra
2370 if (TARGET_SMALLCODE)
2375 /* If we're aiming at small code, then just count the number of
2376 insns in a multiply call sequence. */
2377 if (TARGET_SMALLCODE)
2380 /* Otherwise count all the insns in the routine we'd be calling too. */
2384 /* Compute a (partial) cost for rtx X. Return true if the complete
2385 cost has been computed, and false if subexpressions should be
2386 scanned. In either case, *TOTAL contains the cost result. */
2389 sh_rtx_costs (rtx x, int code, int outer_code, int *total)
2396 if (INTVAL (x) == 0)
2398 else if (outer_code == AND && and_operand ((x), DImode))
2400 else if ((outer_code == IOR || outer_code == XOR
2401 || outer_code == PLUS)
2402 && CONST_OK_FOR_I10 (INTVAL (x)))
2404 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2405 *total = COSTS_N_INSNS (outer_code != SET);
2406 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2407 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2408 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2409 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2411 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2414 if (CONST_OK_FOR_I08 (INTVAL (x)))
2416 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2417 && CONST_OK_FOR_K08 (INTVAL (x)))
2419 /* prepare_cmp_insn will force costly constants int registers before
2420 the cbrach[sd]i4 patterns can see them, so preserve potentially
2421 interesting ones not covered by I08 above. */
2422 else if (outer_code == COMPARE
2423 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2424 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2425 || INTVAL (x) == 0x7fffffff
2426 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2435 if (TARGET_SHMEDIA64)
2436 *total = COSTS_N_INSNS (4);
2437 else if (TARGET_SHMEDIA32)
2438 *total = COSTS_N_INSNS (2);
2445 *total = COSTS_N_INSNS (4);
2446 /* prepare_cmp_insn will force costly constants int registers before
2447 the cbrachdi4 pattern can see them, so preserve potentially
2448 interesting ones. */
2449 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2455 if (x == CONST0_RTX (GET_MODE (x)))
2457 else if (sh_1el_vec (x, VOIDmode))
2458 *total = outer_code != SET;
2459 if (sh_rep_vec (x, VOIDmode))
2460 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2461 + (outer_code != SET));
2462 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2467 *total = COSTS_N_INSNS (addsubcosts (x));
2471 *total = COSTS_N_INSNS (andcosts (x));
2475 *total = COSTS_N_INSNS (multcosts (x));
2481 *total = COSTS_N_INSNS (shiftcosts (x));
2488 *total = COSTS_N_INSNS (20);
2492 if (sh_1el_vec (x, VOIDmode))
2493 *total = outer_code != SET;
2494 if (sh_rep_vec (x, VOIDmode))
2495 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2496 + (outer_code != SET));
2497 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2510 /* Compute the cost of an address. For the SH, all valid addresses are
2511 the same cost. Use a slightly higher cost for reg + reg addressing,
2512 since it increases pressure on r0. */
2515 sh_address_cost (rtx X)
2517 return (GET_CODE (X) == PLUS
2518 && ! CONSTANT_P (XEXP (X, 1))
2519 && ! TARGET_SHMEDIA ? 1 : 0);
2522 /* Code to expand a shift. */
2525 gen_ashift (int type, int n, rtx reg)
2527 /* Negative values here come from the shift_amounts array. */
2540 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
2544 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
2546 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
2549 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
2554 /* Same for HImode */
2557 gen_ashift_hi (int type, int n, rtx reg)
2559 /* Negative values here come from the shift_amounts array. */
2573 /* We don't have HImode right shift operations because using the
2574 ordinary 32 bit shift instructions for that doesn't generate proper
2575 zero/sign extension.
2576 gen_ashift_hi is only called in contexts where we know that the
2577 sign extension works out correctly. */
2580 if (GET_CODE (reg) == SUBREG)
2582 offset = SUBREG_BYTE (reg);
2583 reg = SUBREG_REG (reg);
2585 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
2589 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
2594 /* Output RTL to split a constant shift into its component SH constant
2595 shift instructions. */
2598 gen_shifty_op (int code, rtx *operands)
2600 int value = INTVAL (operands[2]);
2603 /* Truncate the shift count in case it is out of bounds. */
2604 value = value & 0x1f;
2608 if (code == LSHIFTRT)
2610 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2611 emit_insn (gen_movt (operands[0]));
2614 else if (code == ASHIFT)
2616 /* There is a two instruction sequence for 31 bit left shifts,
2617 but it requires r0. */
2618 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
2620 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
2621 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2626 else if (value == 0)
2628 /* This can happen even when optimizing, if there were subregs before
2629 reload. Don't output a nop here, as this is never optimized away;
2630 use a no-op move instead. */
2631 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
2635 max = shift_insns[value];
2636 for (i = 0; i < max; i++)
2637 gen_ashift (code, shift_amounts[value][i], operands[0]);
2640 /* Same as above, but optimized for values where the topmost bits don't
2644 gen_shifty_hi_op (int code, rtx *operands)
2646 int value = INTVAL (operands[2]);
2648 void (*gen_fun) (int, int, rtx);
2650 /* This operation is used by and_shl for SImode values with a few
2651 high bits known to be cleared. */
2655 emit_insn (gen_nop ());
2659 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
2662 max = ext_shift_insns[value];
2663 for (i = 0; i < max; i++)
2664 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2667 /* When shifting right, emit the shifts in reverse order, so that
2668 solitary negative values come first. */
2669 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
2670 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
2673 /* Output RTL for an arithmetic right shift. */
2675 /* ??? Rewrite to use super-optimizer sequences. */
2678 expand_ashiftrt (rtx *operands)
2686 if (GET_CODE (operands[2]) != CONST_INT)
2688 rtx count = copy_to_mode_reg (SImode, operands[2]);
2689 emit_insn (gen_negsi2 (count, count));
2690 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2693 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
2694 > 1 + SH_DYNAMIC_SHIFT_COST)
2697 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
2698 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
2702 if (GET_CODE (operands[2]) != CONST_INT)
2705 value = INTVAL (operands[2]) & 31;
2709 /* If we are called from abs expansion, arrange things so that we
2710 we can use a single MT instruction that doesn't clobber the source,
2711 if LICM can hoist out the load of the constant zero. */
2712 if (currently_expanding_to_rtl)
2714 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
2716 emit_insn (gen_mov_neg_si_t (operands[0]));
2719 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
2722 else if (value >= 16 && value <= 19)
2724 wrk = gen_reg_rtx (SImode);
2725 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
2728 gen_ashift (ASHIFTRT, 1, wrk);
2729 emit_move_insn (operands[0], wrk);
2732 /* Expand a short sequence inline, longer call a magic routine. */
2733 else if (value <= 5)
2735 wrk = gen_reg_rtx (SImode);
2736 emit_move_insn (wrk, operands[1]);
2738 gen_ashift (ASHIFTRT, 1, wrk);
2739 emit_move_insn (operands[0], wrk);
2743 wrk = gen_reg_rtx (Pmode);
2745 /* Load the value into an arg reg and call a helper. */
2746 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2747 sprintf (func, "__ashiftrt_r4_%d", value);
2748 function_symbol (wrk, func, SFUNC_STATIC);
2749 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
2750 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
2755 sh_dynamicalize_shift_p (rtx count)
2757 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
2760 /* Try to find a good way to implement the combiner pattern
2761 [(set (match_operand:SI 0 "register_operand" "r")
2762 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2763 (match_operand:SI 2 "const_int_operand" "n"))
2764 (match_operand:SI 3 "const_int_operand" "n"))) .
2765 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2766 return 0 for simple right / left or left/right shift combination.
2767 return 1 for a combination of shifts with zero_extend.
2768 return 2 for a combination of shifts with an AND that needs r0.
2769 return 3 for a combination of shifts with an AND that needs an extra
2770 scratch register, when the three highmost bits of the AND mask are clear.
2771 return 4 for a combination of shifts with an AND that needs an extra
2772 scratch register, when any of the three highmost bits of the AND mask
2774 If ATTRP is set, store an initial right shift width in ATTRP[0],
2775 and the instruction length in ATTRP[1] . These values are not valid
2777 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2778 shift_amounts for the last shift value that is to be used before the
2781 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
2783 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
2784 int left = INTVAL (left_rtx), right;
2786 int cost, best_cost = 10000;
2787 int best_right = 0, best_len = 0;
2791 if (left < 0 || left > 31)
2793 if (GET_CODE (mask_rtx) == CONST_INT)
2794 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
2796 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
2797 /* Can this be expressed as a right shift / left shift pair? */
2798 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
2799 right = exact_log2 (lsb);
2800 mask2 = ~(mask + lsb - 1);
2801 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
2802 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2804 best_cost = shift_insns[right] + shift_insns[right + left];
2805 /* mask has no trailing zeroes <==> ! right */
2806 else if (! right && mask2 == ~(lsb2 - 1))
2808 int late_right = exact_log2 (lsb2);
2809 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
2811 /* Try to use zero extend. */
2812 if (mask2 == ~(lsb2 - 1))
2816 for (width = 8; width <= 16; width += 8)
2818 /* Can we zero-extend right away? */
2819 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
2822 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
2823 if (cost < best_cost)
2834 /* ??? Could try to put zero extend into initial right shift,
2835 or even shift a bit left before the right shift. */
2836 /* Determine value of first part of left shift, to get to the
2837 zero extend cut-off point. */
2838 first = width - exact_log2 (lsb2) + right;
2839 if (first >= 0 && right + left - first >= 0)
2841 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
2842 + ext_shift_insns[right + left - first];
2843 if (cost < best_cost)
2855 /* Try to use r0 AND pattern */
2856 for (i = 0; i <= 2; i++)
2860 if (! CONST_OK_FOR_K08 (mask >> i))
2862 cost = (i != 0) + 2 + ext_shift_insns[left + i];
2863 if (cost < best_cost)
2868 best_len = cost - 1;
2871 /* Try to use a scratch register to hold the AND operand. */
2872 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
2873 for (i = 0; i <= 2; i++)
2877 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
2878 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
2879 if (cost < best_cost)
2884 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
2890 attrp[0] = best_right;
2891 attrp[1] = best_len;
2896 /* This is used in length attributes of the unnamed instructions
2897 corresponding to shl_and_kind return values of 1 and 2. */
2899 shl_and_length (rtx insn)
2901 rtx set_src, left_rtx, mask_rtx;
2904 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2905 left_rtx = XEXP (XEXP (set_src, 0), 1);
2906 mask_rtx = XEXP (set_src, 1);
2907 shl_and_kind (left_rtx, mask_rtx, attributes);
2908 return attributes[1];
2911 /* This is used in length attribute of the and_shl_scratch instruction. */
2914 shl_and_scr_length (rtx insn)
2916 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2917 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
2918 rtx op = XEXP (set_src, 0);
2919 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
2920 op = XEXP (XEXP (op, 0), 0);
2921 return len + shift_insns[INTVAL (XEXP (op, 1))];
2924 /* Generate rtl for instructions for which shl_and_kind advised a particular
2925 method of generating them, i.e. returned zero. */
2928 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
2931 unsigned HOST_WIDE_INT mask;
2932 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
2933 int right, total_shift;
2934 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
2936 right = attributes[0];
2937 total_shift = INTVAL (left_rtx) + right;
2938 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
2945 int first = attributes[2];
2950 emit_insn ((mask << right) <= 0xff
2951 ? gen_zero_extendqisi2 (dest,
2952 gen_lowpart (QImode, source))
2953 : gen_zero_extendhisi2 (dest,
2954 gen_lowpart (HImode, source)));
2958 emit_insn (gen_movsi (dest, source));
2962 operands[2] = GEN_INT (right);
2963 gen_shifty_hi_op (LSHIFTRT, operands);
2967 operands[2] = GEN_INT (first);
2968 gen_shifty_hi_op (ASHIFT, operands);
2969 total_shift -= first;
2973 emit_insn (mask <= 0xff
2974 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
2975 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2976 if (total_shift > 0)
2978 operands[2] = GEN_INT (total_shift);
2979 gen_shifty_hi_op (ASHIFT, operands);
2984 shift_gen_fun = gen_shifty_op;
2986 /* If the topmost bit that matters is set, set the topmost bits
2987 that don't matter. This way, we might be able to get a shorter
2989 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
2990 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
2992 /* Don't expand fine-grained when combining, because that will
2993 make the pattern fail. */
2994 if (currently_expanding_to_rtl
2995 || reload_in_progress || reload_completed)
2999 /* Cases 3 and 4 should be handled by this split
3000 only while combining */
3001 gcc_assert (kind <= 2);
3004 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3007 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3012 operands[2] = GEN_INT (total_shift);
3013 shift_gen_fun (ASHIFT, operands);
3020 if (kind != 4 && total_shift < 16)
3022 neg = -ext_shift_amounts[total_shift][1];
3024 neg -= ext_shift_amounts[total_shift][2];
3028 emit_insn (gen_and_shl_scratch (dest, source,
3031 GEN_INT (total_shift + neg),
3033 emit_insn (gen_movsi (dest, dest));
3040 /* Try to find a good way to implement the combiner pattern
3041 [(set (match_operand:SI 0 "register_operand" "=r")
3042 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3043 (match_operand:SI 2 "const_int_operand" "n")
3044 (match_operand:SI 3 "const_int_operand" "n")
3046 (clobber (reg:SI T_REG))]
3047 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3048 return 0 for simple left / right shift combination.
3049 return 1 for left shift / 8 bit sign extend / left shift.
3050 return 2 for left shift / 16 bit sign extend / left shift.
3051 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3052 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3053 return 5 for left shift / 16 bit sign extend / right shift
3054 return 6 for < 8 bit sign extend / left shift.
3055 return 7 for < 8 bit sign extend / left shift / single right shift.
3056 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3059 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3061 int left, size, insize, ext;
3062 int cost = 0, best_cost;
3065 left = INTVAL (left_rtx);
3066 size = INTVAL (size_rtx);
3067 insize = size - left;
3068 gcc_assert (insize > 0);
3069 /* Default to left / right shift. */
3071 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3074 /* 16 bit shift / sign extend / 16 bit shift */
3075 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3076 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3077 below, by alternative 3 or something even better. */
3078 if (cost < best_cost)
3084 /* Try a plain sign extend between two shifts. */
3085 for (ext = 16; ext >= insize; ext -= 8)
3089 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3090 if (cost < best_cost)
3092 kind = ext / (unsigned) 8;
3096 /* Check if we can do a sloppy shift with a final signed shift
3097 restoring the sign. */
3098 if (EXT_SHIFT_SIGNED (size - ext))
3099 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3100 /* If not, maybe it's still cheaper to do the second shift sloppy,
3101 and do a final sign extend? */
3102 else if (size <= 16)
3103 cost = ext_shift_insns[ext - insize] + 1
3104 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3107 if (cost < best_cost)
3109 kind = ext / (unsigned) 8 + 2;
3113 /* Check if we can sign extend in r0 */
3116 cost = 3 + shift_insns[left];
3117 if (cost < best_cost)
3122 /* Try the same with a final signed shift. */
3125 cost = 3 + ext_shift_insns[left + 1] + 1;
3126 if (cost < best_cost)
3135 /* Try to use a dynamic shift. */
3136 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3137 if (cost < best_cost)
3148 /* Function to be used in the length attribute of the instructions
3149 implementing this pattern. */
3152 shl_sext_length (rtx insn)
3154 rtx set_src, left_rtx, size_rtx;
3157 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3158 left_rtx = XEXP (XEXP (set_src, 0), 1);
3159 size_rtx = XEXP (set_src, 1);
3160 shl_sext_kind (left_rtx, size_rtx, &cost);
3164 /* Generate rtl for this pattern */
3167 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3170 int left, size, insize, cost;
3173 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3174 left = INTVAL (left_rtx);
3175 size = INTVAL (size_rtx);
3176 insize = size - left;
3184 int ext = kind & 1 ? 8 : 16;
3185 int shift2 = size - ext;
3187 /* Don't expand fine-grained when combining, because that will
3188 make the pattern fail. */
3189 if (! currently_expanding_to_rtl
3190 && ! reload_in_progress && ! reload_completed)
3192 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3193 emit_insn (gen_movsi (dest, source));
3197 emit_insn (gen_movsi (dest, source));
3201 operands[2] = GEN_INT (ext - insize);
3202 gen_shifty_hi_op (ASHIFT, operands);
3205 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3206 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3211 operands[2] = GEN_INT (shift2);
3212 gen_shifty_op (ASHIFT, operands);
3219 if (EXT_SHIFT_SIGNED (shift2))
3221 operands[2] = GEN_INT (shift2 + 1);
3222 gen_shifty_op (ASHIFT, operands);
3223 operands[2] = const1_rtx;
3224 gen_shifty_op (ASHIFTRT, operands);
3227 operands[2] = GEN_INT (shift2);
3228 gen_shifty_hi_op (ASHIFT, operands);
3232 operands[2] = GEN_INT (-shift2);
3233 gen_shifty_hi_op (LSHIFTRT, operands);
3235 emit_insn (size <= 8
3236 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3237 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3244 if (! currently_expanding_to_rtl
3245 && ! reload_in_progress && ! reload_completed)
3246 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3250 operands[2] = GEN_INT (16 - insize);
3251 gen_shifty_hi_op (ASHIFT, operands);
3252 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3254 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3256 gen_ashift (ASHIFTRT, 1, dest);
3261 /* Don't expand fine-grained when combining, because that will
3262 make the pattern fail. */
3263 if (! currently_expanding_to_rtl
3264 && ! reload_in_progress && ! reload_completed)
3266 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3267 emit_insn (gen_movsi (dest, source));
3270 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3271 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3272 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3274 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3275 gen_shifty_op (ASHIFT, operands);
3277 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3285 /* Prefix a symbol_ref name with "datalabel". */
3288 gen_datalabel_ref (rtx sym)
3292 if (GET_CODE (sym) == LABEL_REF)
3293 return gen_rtx_CONST (GET_MODE (sym),
3294 gen_rtx_UNSPEC (GET_MODE (sym),
3298 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3300 str = XSTR (sym, 0);
3301 /* Share all SYMBOL_REF strings with the same value - that is important
3303 str = IDENTIFIER_POINTER (get_identifier (str));
3304 XSTR (sym, 0) = str;
3310 static alloc_pool label_ref_list_pool;
3312 typedef struct label_ref_list_d
3315 struct label_ref_list_d *next;
3316 } *label_ref_list_t;
3318 /* The SH cannot load a large constant into a register, constants have to
3319 come from a pc relative load. The reference of a pc relative load
3320 instruction must be less than 1k in front of the instruction. This
3321 means that we often have to dump a constant inside a function, and
3322 generate code to branch around it.
3324 It is important to minimize this, since the branches will slow things
3325 down and make things bigger.
3327 Worst case code looks like:
3345 We fix this by performing a scan before scheduling, which notices which
3346 instructions need to have their operands fetched from the constant table
3347 and builds the table.
3351 scan, find an instruction which needs a pcrel move. Look forward, find the
3352 last barrier which is within MAX_COUNT bytes of the requirement.
3353 If there isn't one, make one. Process all the instructions between
3354 the find and the barrier.
3356 In the above example, we can tell that L3 is within 1k of L1, so
3357 the first move can be shrunk from the 3 insn+constant sequence into
3358 just 1 insn, and the constant moved to L3 to make:
3369 Then the second move becomes the target for the shortening process. */
3373 rtx value; /* Value in table. */
3374 rtx label; /* Label of value. */
3375 label_ref_list_t wend; /* End of window. */
3376 enum machine_mode mode; /* Mode of value. */
3378 /* True if this constant is accessed as part of a post-increment
3379 sequence. Note that HImode constants are never accessed in this way. */
3380 bool part_of_sequence_p;
3383 /* The maximum number of constants that can fit into one pool, since
3384 constants in the range 0..510 are at least 2 bytes long, and in the
3385 range from there to 1018 at least 4 bytes. */
3387 #define MAX_POOL_SIZE 372
3388 static pool_node pool_vector[MAX_POOL_SIZE];
3389 static int pool_size;
3390 static rtx pool_window_label;
3391 static int pool_window_last;
3393 static int max_labelno_before_reorg;
3395 /* ??? If we need a constant in HImode which is the truncated value of a
3396 constant we need in SImode, we could combine the two entries thus saving
3397 two bytes. Is this common enough to be worth the effort of implementing
3400 /* ??? This stuff should be done at the same time that we shorten branches.
3401 As it is now, we must assume that all branches are the maximum size, and
3402 this causes us to almost always output constant pools sooner than
3405 /* Add a constant to the pool and return its label. */
3408 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3412 label_ref_list_t ref, newref;
3414 /* First see if we've already got it. */
3415 for (i = 0; i < pool_size; i++)
3417 if (x->code == pool_vector[i].value->code
3418 && mode == pool_vector[i].mode)
3420 if (x->code == CODE_LABEL)
3422 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3425 if (rtx_equal_p (x, pool_vector[i].value))
3430 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3432 new = gen_label_rtx ();
3433 LABEL_REFS (new) = pool_vector[i].label;
3434 pool_vector[i].label = lab = new;
3436 if (lab && pool_window_label)
3438 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3439 newref->label = pool_window_label;
3440 ref = pool_vector[pool_window_last].wend;
3442 pool_vector[pool_window_last].wend = newref;
3445 pool_window_label = new;
3446 pool_window_last = i;
3452 /* Need a new one. */
3453 pool_vector[pool_size].value = x;
3454 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3457 pool_vector[pool_size - 1].part_of_sequence_p = true;
3460 lab = gen_label_rtx ();
3461 pool_vector[pool_size].mode = mode;
3462 pool_vector[pool_size].label = lab;
3463 pool_vector[pool_size].wend = NULL;
3464 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3465 if (lab && pool_window_label)
3467 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3468 newref->label = pool_window_label;
3469 ref = pool_vector[pool_window_last].wend;
3471 pool_vector[pool_window_last].wend = newref;
3474 pool_window_label = lab;
3475 pool_window_last = pool_size;
3480 /* Output the literal table. START, if nonzero, is the first instruction
3481 this table is needed for, and also indicates that there is at least one
3482 casesi_worker_2 instruction; We have to emit the operand3 labels from
3483 these insns at a 4-byte aligned position. BARRIER is the barrier
3484 after which we are to place the table. */
3487 dump_table (rtx start, rtx barrier)
3493 label_ref_list_t ref;
3496 /* Do two passes, first time dump out the HI sized constants. */
3498 for (i = 0; i < pool_size; i++)
3500 pool_node *p = &pool_vector[i];
3502 if (p->mode == HImode)
3506 scan = emit_insn_after (gen_align_2 (), scan);
3509 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3510 scan = emit_label_after (lab, scan);
3511 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
3513 for (ref = p->wend; ref; ref = ref->next)
3516 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3519 else if (p->mode == DFmode)
3527 scan = emit_insn_after (gen_align_4 (), scan);
3529 for (; start != barrier; start = NEXT_INSN (start))
3530 if (GET_CODE (start) == INSN
3531 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
3533 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
3534 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
3536 scan = emit_label_after (lab, scan);
3539 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
3541 rtx align_insn = NULL_RTX;
3543 scan = emit_label_after (gen_label_rtx (), scan);
3544 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3547 for (i = 0; i < pool_size; i++)
3549 pool_node *p = &pool_vector[i];
3557 if (align_insn && !p->part_of_sequence_p)
3559 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3560 emit_label_before (lab, align_insn);
3561 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
3563 for (ref = p->wend; ref; ref = ref->next)
3566 emit_insn_before (gen_consttable_window_end (lab),
3569 delete_insn (align_insn);
3570 align_insn = NULL_RTX;
3575 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3576 scan = emit_label_after (lab, scan);
3577 scan = emit_insn_after (gen_consttable_4 (p->value,
3579 need_align = ! need_align;
3585 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
3590 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3591 scan = emit_label_after (lab, scan);
3592 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3599 if (p->mode != HImode)
3601 for (ref = p->wend; ref; ref = ref->next)
3604 scan = emit_insn_after (gen_consttable_window_end (lab),
3613 for (i = 0; i < pool_size; i++)
3615 pool_node *p = &pool_vector[i];
3626 scan = emit_label_after (gen_label_rtx (), scan);
3627 scan = emit_insn_after (gen_align_4 (), scan);
3629 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3630 scan = emit_label_after (lab, scan);
3631 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
3639 scan = emit_label_after (gen_label_rtx (), scan);
3640 scan = emit_insn_after (gen_align_4 (), scan);
3642 for (lab = p->label; lab; lab = LABEL_REFS (lab))
3643 scan = emit_label_after (lab, scan);
3644 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
3651 if (p->mode != HImode)
3653 for (ref = p->wend; ref; ref = ref->next)
3656 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
3661 scan = emit_insn_after (gen_consttable_end (), scan);
3662 scan = emit_barrier_after (scan);
3664 pool_window_label = NULL_RTX;
3665 pool_window_last = 0;
3668 /* Return nonzero if constant would be an ok source for a
3669 mov.w instead of a mov.l. */
3674 return (GET_CODE (src) == CONST_INT
3675 && INTVAL (src) >= -32768
3676 && INTVAL (src) <= 32767);
3679 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
3681 /* Nonzero if the insn is a move instruction which needs to be fixed. */
3683 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
3684 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
3685 need to fix it if the input value is CONST_OK_FOR_I08. */
3688 broken_move (rtx insn)
3690 if (GET_CODE (insn) == INSN)
3692 rtx pat = PATTERN (insn);
3693 if (GET_CODE (pat) == PARALLEL)
3694 pat = XVECEXP (pat, 0, 0);
3695 if (GET_CODE (pat) == SET
3696 /* We can load any 8-bit value if we don't care what the high
3697 order bits end up as. */
3698 && GET_MODE (SET_DEST (pat)) != QImode
3699 && (CONSTANT_P (SET_SRC (pat))
3700 /* Match mova_const. */
3701 || (GET_CODE (SET_SRC (pat)) == UNSPEC
3702 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
3703 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
3705 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
3706 && (fp_zero_operand (SET_SRC (pat))
3707 || fp_one_operand (SET_SRC (pat)))
3708 /* ??? If this is a -m4 or -m4-single compilation, in general
3709 we don't know the current setting of fpscr, so disable fldi.
3710 There is an exception if this was a register-register move
3711 before reload - and hence it was ascertained that we have
3712 single precision setting - and in a post-reload optimization
3713 we changed this to do a constant load. In that case
3714 we don't have an r0 clobber, hence we must use fldi. */
3715 && (! TARGET_SH4 || TARGET_FMOVD
3716 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
3718 && GET_CODE (SET_DEST (pat)) == REG
3719 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
3721 && GET_MODE (SET_DEST (pat)) == SImode
3722 && GET_CODE (SET_SRC (pat)) == CONST_INT
3723 && CONST_OK_FOR_I20 (INTVAL (SET_SRC (pat))))
3724 && (GET_CODE (SET_SRC (pat)) != CONST_INT
3725 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat)))))
3735 return (GET_CODE (insn) == INSN
3736 && GET_CODE (PATTERN (insn)) == SET
3737 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
3738 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
3739 /* Don't match mova_const. */
3740 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
3743 /* Fix up a mova from a switch that went out of range. */
3745 fixup_mova (rtx mova)
3747 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
3750 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
3751 INSN_CODE (mova) = -1;
3756 rtx lab = gen_label_rtx ();
3757 rtx wpat, wpat0, wpat1, wsrc, diff;
3761 worker = NEXT_INSN (worker);
3763 && GET_CODE (worker) != CODE_LABEL
3764 && GET_CODE (worker) != JUMP_INSN);
3765 } while (GET_CODE (worker) == NOTE
3766 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
3767 wpat = PATTERN (worker);
3768 wpat0 = XVECEXP (wpat, 0, 0);
3769 wpat1 = XVECEXP (wpat, 0, 1);
3770 wsrc = SET_SRC (wpat0);
3771 PATTERN (worker) = (gen_casesi_worker_2
3772 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
3773 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
3775 INSN_CODE (worker) = -1;
3776 diff = gen_rtx_MINUS (Pmode, XVECEXP (SET_SRC (PATTERN (mova)), 0, 0),
3777 gen_rtx_LABEL_REF (Pmode, lab));
3778 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, diff), UNSPEC_PIC);
3779 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
3780 INSN_CODE (mova) = -1;
3784 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
3785 *num_mova, and check if the new mova is not nested within the first one.
3786 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
3787 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
3789 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
3791 int n_addr = 0; /* Initialization to shut up spurious warning. */
3792 int f_target, n_target = 0; /* Likewise. */
3796 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
3797 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
3798 if (n_addr > n_target || n_addr + 1022 < n_target)
3800 /* Change the mova into a load.
3801 broken_move will then return true for it. */
3802 fixup_mova (new_mova);
3808 *first_mova = new_mova;
3813 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
3818 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
3819 > n_target - n_addr)
3821 fixup_mova (*first_mova);
3826 fixup_mova (new_mova);
3831 /* Find the last barrier from insn FROM which is close enough to hold the
3832 constant pool. If we can't find one, then create one near the end of
3836 find_barrier (int num_mova, rtx mova, rtx from)
3845 int leading_mova = num_mova;
3846 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
3850 /* For HImode: range is 510, add 4 because pc counts from address of
3851 second instruction after this one, subtract 2 for the jump instruction
3852 that we may need to emit before the table, subtract 2 for the instruction
3853 that fills the jump delay slot (in very rare cases, reorg will take an
3854 instruction from after the constant pool or will leave the delay slot
3855 empty). This gives 510.
3856 For SImode: range is 1020, add 4 because pc counts from address of
3857 second instruction after this one, subtract 2 in case pc is 2 byte
3858 aligned, subtract 2 for the jump instruction that we may need to emit
3859 before the table, subtract 2 for the instruction that fills the jump
3860 delay slot. This gives 1018. */
3862 /* The branch will always be shortened now that the reference address for
3863 forward branches is the successor address, thus we need no longer make
3864 adjustments to the [sh]i_limit for -O0. */
3869 while (from && count_si < si_limit && count_hi < hi_limit)
3871 int inc = get_attr_length (from);
3874 /* If this is a label that existed at the time of the compute_alignments
3875 call, determine the alignment. N.B. When find_barrier recurses for
3876 an out-of-reach mova, we might see labels at the start of previously
3877 inserted constant tables. */
3878 if (GET_CODE (from) == CODE_LABEL
3879 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
3882 new_align = 1 << label_to_alignment (from);
3883 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
3884 new_align = 1 << barrier_align (from);
3889 /* In case we are scanning a constant table because of recursion, check
3890 for explicit alignments. If the table is long, we might be forced
3891 to emit the new table in front of it; the length of the alignment
3892 might be the last straw. */
3893 else if (GET_CODE (from) == INSN
3894 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3895 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
3896 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
3897 /* When we find the end of a constant table, paste the new constant
3898 at the end. That is better than putting it in front because
3899 this way, we don't need extra alignment for adding a 4-byte-aligned
3900 mov(a) label to a 2/4 or 8/4 byte aligned table. */
3901 else if (GET_CODE (from) == INSN
3902 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
3903 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
3906 if (GET_CODE (from) == BARRIER)
3909 found_barrier = from;
3911 /* If we are at the end of the function, or in front of an alignment
3912 instruction, we need not insert an extra alignment. We prefer
3913 this kind of barrier. */
3914 if (barrier_align (from) > 2)
3915 good_barrier = from;
3918 if (broken_move (from))
3921 enum machine_mode mode;
3923 pat = PATTERN (from);
3924 if (GET_CODE (pat) == PARALLEL)
3925 pat = XVECEXP (pat, 0, 0);
3926 src = SET_SRC (pat);
3927 dst = SET_DEST (pat);
3928 mode = GET_MODE (dst);
3930 /* We must explicitly check the mode, because sometimes the
3931 front end will generate code to load unsigned constants into
3932 HImode targets without properly sign extending them. */
3934 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
3937 /* We put the short constants before the long constants, so
3938 we must count the length of short constants in the range
3939 for the long constants. */
3940 /* ??? This isn't optimal, but is easy to do. */
3945 /* We dump DF/DI constants before SF/SI ones, because
3946 the limit is the same, but the alignment requirements
3947 are higher. We may waste up to 4 additional bytes
3948 for alignment, and the DF/DI constant may have
3949 another SF/SI constant placed before it. */
3950 if (TARGET_SHCOMPACT
3952 && (mode == DFmode || mode == DImode))
3957 while (si_align > 2 && found_si + si_align - 2 > count_si)
3959 if (found_si > count_si)
3960 count_si = found_si;
3961 found_si += GET_MODE_SIZE (mode);
3963 si_limit -= GET_MODE_SIZE (mode);
3969 switch (untangle_mova (&num_mova, &mova, from))
3971 case 0: return find_barrier (0, 0, mova);
3976 = good_barrier ? good_barrier : found_barrier;
3980 if (found_si > count_si)
3981 count_si = found_si;
3983 else if (GET_CODE (from) == JUMP_INSN
3984 && (GET_CODE (PATTERN (from)) == ADDR_VEC
3985 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
3987 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
3989 && (prev_nonnote_insn (from)
3990 == XEXP (MOVA_LABELREF (mova), 0))))
3992 if (barrier_align (next_real_insn (from)) == align_jumps_log)
3994 /* We have just passed the barrier in front of the
3995 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3996 the ADDR_DIFF_VEC is accessed as data, just like our pool
3997 constants, this is a good opportunity to accommodate what
3998 we have gathered so far.
3999 If we waited any longer, we could end up at a barrier in
4000 front of code, which gives worse cache usage for separated
4001 instruction / data caches. */
4002 good_barrier = found_barrier;
4007 rtx body = PATTERN (from);
4008 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4011 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4012 else if (GET_CODE (from) == JUMP_INSN
4014 && ! TARGET_SMALLCODE)
4020 if (new_align > si_align)
4022 si_limit -= (count_si - 1) & (new_align - si_align);
4023 si_align = new_align;
4025 count_si = (count_si + new_align - 1) & -new_align;
4030 if (new_align > hi_align)
4032 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4033 hi_align = new_align;
4035 count_hi = (count_hi + new_align - 1) & -new_align;
4037 from = NEXT_INSN (from);
4044 /* Try as we might, the leading mova is out of range. Change
4045 it into a load (which will become a pcload) and retry. */
4047 return find_barrier (0, 0, mova);
4051 /* Insert the constant pool table before the mova instruction,
4052 to prevent the mova label reference from going out of range. */
4054 good_barrier = found_barrier = barrier_before_mova;
4060 if (good_barrier && next_real_insn (found_barrier))
4061 found_barrier = good_barrier;
4065 /* We didn't find a barrier in time to dump our stuff,
4066 so we'll make one. */
4067 rtx label = gen_label_rtx ();
4069 /* If we exceeded the range, then we must back up over the last
4070 instruction we looked at. Otherwise, we just need to undo the
4071 NEXT_INSN at the end of the loop. */
4072 if (count_hi > hi_limit || count_si > si_limit)
4073 from = PREV_INSN (PREV_INSN (from));
4075 from = PREV_INSN (from);
4077 /* Walk back to be just before any jump or label.
4078 Putting it before a label reduces the number of times the branch
4079 around the constant pool table will be hit. Putting it before
4080 a jump makes it more likely that the bra delay slot will be
4082 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
4083 || GET_CODE (from) == CODE_LABEL)
4084 from = PREV_INSN (from);
4086 from = emit_jump_insn_after (gen_jump (label), from);
4087 JUMP_LABEL (from) = label;
4088 LABEL_NUSES (label) = 1;
4089 found_barrier = emit_barrier_after (from);
4090 emit_label_after (label, found_barrier);
4093 return found_barrier;
4096 /* If the instruction INSN is implemented by a special function, and we can
4097 positively find the register that is used to call the sfunc, and this
4098 register is not used anywhere else in this instruction - except as the
4099 destination of a set, return this register; else, return 0. */
4101 sfunc_uses_reg (rtx insn)
4104 rtx pattern, part, reg_part, reg;
4106 if (GET_CODE (insn) != INSN)
4108 pattern = PATTERN (insn);
4109 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4112 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4114 part = XVECEXP (pattern, 0, i);
4115 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4120 reg = XEXP (reg_part, 0);
4121 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4123 part = XVECEXP (pattern, 0, i);
4124 if (part == reg_part || GET_CODE (part) == CLOBBER)
4126 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4127 && GET_CODE (SET_DEST (part)) == REG)
4128 ? SET_SRC (part) : part)))
4134 /* See if the only way in which INSN uses REG is by calling it, or by
4135 setting it while calling it. Set *SET to a SET rtx if the register
4139 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4145 reg2 = sfunc_uses_reg (insn);
4146 if (reg2 && REGNO (reg2) == REGNO (reg))
4148 pattern = single_set (insn);
4150 && GET_CODE (SET_DEST (pattern)) == REG
4151 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4155 if (GET_CODE (insn) != CALL_INSN)
4157 /* We don't use rtx_equal_p because we don't care if the mode is
4159 pattern = single_set (insn);
4161 && GET_CODE (SET_DEST (pattern)) == REG
4162 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4168 par = PATTERN (insn);
4169 if (GET_CODE (par) == PARALLEL)
4170 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4172 part = XVECEXP (par, 0, i);
4173 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4176 return reg_mentioned_p (reg, SET_SRC (pattern));
4182 pattern = PATTERN (insn);
4184 if (GET_CODE (pattern) == PARALLEL)
4188 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4189 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4191 pattern = XVECEXP (pattern, 0, 0);
4194 if (GET_CODE (pattern) == SET)
4196 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4198 /* We don't use rtx_equal_p, because we don't care if the
4199 mode is different. */
4200 if (GET_CODE (SET_DEST (pattern)) != REG
4201 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4207 pattern = SET_SRC (pattern);
4210 if (GET_CODE (pattern) != CALL
4211 || GET_CODE (XEXP (pattern, 0)) != MEM
4212 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4218 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4219 general registers. Bits 0..15 mean that the respective registers
4220 are used as inputs in the instruction. Bits 16..31 mean that the
4221 registers 0..15, respectively, are used as outputs, or are clobbered.
4222 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4224 regs_used (rtx x, int is_dest)
4232 code = GET_CODE (x);
4237 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4238 << (REGNO (x) + is_dest));
4242 rtx y = SUBREG_REG (x);
4244 if (GET_CODE (y) != REG)
4247 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4249 subreg_regno_offset (REGNO (y),
4252 GET_MODE (x)) + is_dest));
4256 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4258 /* If there was a return value, it must have been indicated with USE. */
4273 fmt = GET_RTX_FORMAT (code);
4275 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4280 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4281 used |= regs_used (XVECEXP (x, i, j), is_dest);
4283 else if (fmt[i] == 'e')
4284 used |= regs_used (XEXP (x, i), is_dest);
4289 /* Create an instruction that prevents redirection of a conditional branch
4290 to the destination of the JUMP with address ADDR.
4291 If the branch needs to be implemented as an indirect jump, try to find
4292 a scratch register for it.
4293 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4294 If any preceding insn that doesn't fit into a delay slot is good enough,
4295 pass 1. Pass 2 if a definite blocking insn is needed.
4296 -1 is used internally to avoid deep recursion.
4297 If a blocking instruction is made or recognized, return it. */
4300 gen_block_redirect (rtx jump, int addr, int need_block)
4303 rtx prev = prev_nonnote_insn (jump);
4306 /* First, check if we already have an instruction that satisfies our need. */
4307 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
4309 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4311 if (GET_CODE (PATTERN (prev)) == USE
4312 || GET_CODE (PATTERN (prev)) == CLOBBER
4313 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4315 else if ((need_block &= ~1) < 0)
4317 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4320 if (GET_CODE (PATTERN (jump)) == RETURN)
4324 /* Reorg even does nasty things with return insns that cause branches
4325 to go out of range - see find_end_label and callers. */
4326 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4328 /* We can't use JUMP_LABEL here because it might be undefined
4329 when not optimizing. */
4330 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4331 /* If the branch is out of range, try to find a scratch register for it. */
4333 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4337 /* Don't look for the stack pointer as a scratch register,
4338 it would cause trouble if an interrupt occurred. */
4339 unsigned try = 0x7fff, used;
4340 int jump_left = flag_expensive_optimizations + 1;
4342 /* It is likely that the most recent eligible instruction is wanted for
4343 the delay slot. Therefore, find out which registers it uses, and
4344 try to avoid using them. */
4346 for (scan = jump; (scan = PREV_INSN (scan)); )
4350 if (INSN_DELETED_P (scan))
4352 code = GET_CODE (scan);
4353 if (code == CODE_LABEL || code == JUMP_INSN)
4356 && GET_CODE (PATTERN (scan)) != USE
4357 && GET_CODE (PATTERN (scan)) != CLOBBER
4358 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4360 try &= ~regs_used (PATTERN (scan), 0);
4364 for (used = dead = 0, scan = JUMP_LABEL (jump);
4365 (scan = NEXT_INSN (scan)); )
4369 if (INSN_DELETED_P (scan))
4371 code = GET_CODE (scan);
4374 used |= regs_used (PATTERN (scan), 0);
4375 if (code == CALL_INSN)
4376 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4377 dead |= (used >> 16) & ~used;
4383 if (code == JUMP_INSN)
4385 if (jump_left-- && simplejump_p (scan))
4386 scan = JUMP_LABEL (scan);
4392 /* Mask out the stack pointer again, in case it was
4393 the only 'free' register we have found. */
4396 /* If the immediate destination is still in range, check for possible
4397 threading with a jump beyond the delay slot insn.
4398 Don't check if we are called recursively; the jump has been or will be
4399 checked in a different invocation then. */
4401 else if (optimize && need_block >= 0)
4403 rtx next = next_active_insn (next_active_insn (dest));
4404 if (next && GET_CODE (next) == JUMP_INSN
4405 && GET_CODE (PATTERN (next)) == SET
4406 && recog_memoized (next) == CODE_FOR_jump_compact)
4408 dest = JUMP_LABEL (next);
4410 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4412 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4418 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4420 /* It would be nice if we could convert the jump into an indirect
4421 jump / far branch right now, and thus exposing all constituent
4422 instructions to further optimization. However, reorg uses
4423 simplejump_p to determine if there is an unconditional jump where
4424 it should try to schedule instructions from the target of the
4425 branch; simplejump_p fails for indirect jumps even if they have
4427 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4428 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4430 /* ??? We would like this to have the scope of the jump, but that
4431 scope will change when a delay slot insn of an inner scope is added.
4432 Hence, after delay slot scheduling, we'll have to expect
4433 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4436 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4437 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4440 else if (need_block)
4441 /* We can't use JUMP_LABEL here because it might be undefined
4442 when not optimizing. */
4443 return emit_insn_before (gen_block_branch_redirect
4444 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4449 #define CONDJUMP_MIN -252
4450 #define CONDJUMP_MAX 262
4453 /* A label (to be placed) in front of the jump
4454 that jumps to our ultimate destination. */
4456 /* Where we are going to insert it if we cannot move the jump any farther,
4457 or the jump itself if we have picked up an existing jump. */
4459 /* The ultimate destination. */
4461 struct far_branch *prev;
4462 /* If the branch has already been created, its address;
4463 else the address of its first prospective user. */
4467 static void gen_far_branch (struct far_branch *);
4468 enum mdep_reorg_phase_e mdep_reorg_phase;
4470 gen_far_branch (struct far_branch *bp)
4472 rtx insn = bp->insert_place;
4474 rtx label = gen_label_rtx ();
4477 emit_label_after (label, insn);
4480 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4481 LABEL_NUSES (bp->far_label)++;
4484 jump = emit_jump_insn_after (gen_return (), insn);
4485 /* Emit a barrier so that reorg knows that any following instructions
4486 are not reachable via a fall-through path.
4487 But don't do this when not optimizing, since we wouldn't suppress the
4488 alignment for the barrier then, and could end up with out-of-range
4489 pc-relative loads. */
4491 emit_barrier_after (jump);
4492 emit_label_after (bp->near_label, insn);
4493 JUMP_LABEL (jump) = bp->far_label;
4494 ok = invert_jump (insn, label, 1);
4497 /* If we are branching around a jump (rather than a return), prevent
4498 reorg from using an insn from the jump target as the delay slot insn -
4499 when reorg did this, it pessimized code (we rather hide the delay slot)
4500 and it could cause branches to go out of range. */
4503 (gen_stuff_delay_slot
4504 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
4505 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
4507 /* Prevent reorg from undoing our splits. */
4508 gen_block_redirect (jump, bp->address += 2, 2);
4511 /* Fix up ADDR_DIFF_VECs. */
4513 fixup_addr_diff_vecs (rtx first)
4517 for (insn = first; insn; insn = NEXT_INSN (insn))
4519 rtx vec_lab, pat, prev, prevpat, x, braf_label;
4521 if (GET_CODE (insn) != JUMP_INSN
4522 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
4524 pat = PATTERN (insn);
4525 vec_lab = XEXP (XEXP (pat, 0), 0);
4527 /* Search the matching casesi_jump_2. */
4528 for (prev = vec_lab; ; prev = PREV_INSN (prev))
4530 if (GET_CODE (prev) != JUMP_INSN)
4532 prevpat = PATTERN (prev);
4533 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
4535 x = XVECEXP (prevpat, 0, 1);
4536 if (GET_CODE (x) != USE)
4539 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
4542 /* FIXME: This is a bug in the optimizer, but it seems harmless
4543 to just avoid panicing. */
4547 /* Emit the reference label of the braf where it belongs, right after
4548 the casesi_jump_2 (i.e. braf). */
4549 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
4550 emit_label_after (braf_label, prev);
4552 /* Fix up the ADDR_DIF_VEC to be relative
4553 to the reference address of the braf. */
4554 XEXP (XEXP (pat, 0), 0) = braf_label;
4558 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
4559 a barrier. Return the base 2 logarithm of the desired alignment. */
4561 barrier_align (rtx barrier_or_label)
4563 rtx next = next_real_insn (barrier_or_label), pat, prev;
4564 int slot, credit, jump_to_next = 0;
4569 pat = PATTERN (next);
4571 if (GET_CODE (pat) == ADDR_DIFF_VEC)
4574 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
4575 /* This is a barrier in front of a constant table. */
4578 prev = prev_real_insn (barrier_or_label);
4579 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
4581 pat = PATTERN (prev);
4582 /* If this is a very small table, we want to keep the alignment after
4583 the table to the minimum for proper code alignment. */
4584 return ((TARGET_SMALLCODE
4585 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
4586 <= (unsigned) 1 << (CACHE_LOG - 2)))
4587 ? 1 << TARGET_SHMEDIA : align_jumps_log);
4590 if (TARGET_SMALLCODE)
4593 if (! TARGET_SH2 || ! optimize)
4594 return align_jumps_log;
4596 /* When fixing up pcloads, a constant table might be inserted just before
4597 the basic block that ends with the barrier. Thus, we can't trust the
4598 instruction lengths before that. */
4599 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
4601 /* Check if there is an immediately preceding branch to the insn beyond
4602 the barrier. We must weight the cost of discarding useful information
4603 from the current cache line when executing this branch and there is
4604 an alignment, against that of fetching unneeded insn in front of the
4605 branch target when there is no alignment. */
4607 /* There are two delay_slot cases to consider. One is the simple case
4608 where the preceding branch is to the insn beyond the barrier (simple
4609 delay slot filling), and the other is where the preceding branch has
4610 a delay slot that is a duplicate of the insn after the barrier
4611 (fill_eager_delay_slots) and the branch is to the insn after the insn
4612 after the barrier. */
4614 /* PREV is presumed to be the JUMP_INSN for the barrier under
4615 investigation. Skip to the insn before it. */
4616 prev = prev_real_insn (prev);
4618 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
4619 credit >= 0 && prev && GET_CODE (prev) == INSN;
4620 prev = prev_real_insn (prev))
4623 if (GET_CODE (PATTERN (prev)) == USE
4624 || GET_CODE (PATTERN (prev)) == CLOBBER)
4626 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
4628 prev = XVECEXP (PATTERN (prev), 0, 1);
4629 if (INSN_UID (prev) == INSN_UID (next))
4631 /* Delay slot was filled with insn at jump target. */
4638 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4640 credit -= get_attr_length (prev);
4643 && GET_CODE (prev) == JUMP_INSN
4644 && JUMP_LABEL (prev))
4648 || next_real_insn (JUMP_LABEL (prev)) == next
4649 /* If relax_delay_slots() decides NEXT was redundant
4650 with some previous instruction, it will have
4651 redirected PREV's jump to the following insn. */
4652 || JUMP_LABEL (prev) == next_nonnote_insn (next)
4653 /* There is no upper bound on redundant instructions
4654 that might have been skipped, but we must not put an
4655 alignment where none had been before. */
4656 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
4658 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
4659 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
4660 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
4662 rtx pat = PATTERN (prev);
4663 if (GET_CODE (pat) == PARALLEL)
4664 pat = XVECEXP (pat, 0, 0);
4665 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
4671 return align_jumps_log;
4674 /* If we are inside a phony loop, almost any kind of label can turn up as the
4675 first one in the loop. Aligning a braf label causes incorrect switch
4676 destination addresses; we can detect braf labels because they are
4677 followed by a BARRIER.
4678 Applying loop alignment to small constant or switch tables is a waste
4679 of space, so we suppress this too. */
4681 sh_loop_align (rtx label)
4686 next = next_nonnote_insn (next);
4687 while (next && GET_CODE (next) == CODE_LABEL);
4691 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
4692 || recog_memoized (next) == CODE_FOR_consttable_2)
4695 return align_loops_log;
4698 /* Do a final pass over the function, just before delayed branch
4704 rtx first, insn, mova = NULL_RTX;
4706 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
4707 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
4709 first = get_insns ();
4710 max_labelno_before_reorg = max_label_num ();
4712 /* We must split call insns before introducing `mova's. If we're
4713 optimizing, they'll have already been split. Otherwise, make
4714 sure we don't split them too late. */
4716 split_all_insns_noflow ();
4721 /* If relaxing, generate pseudo-ops to associate function calls with
4722 the symbols they call. It does no harm to not generate these
4723 pseudo-ops. However, when we can generate them, it enables to
4724 linker to potentially relax the jsr to a bsr, and eliminate the
4725 register load and, possibly, the constant pool entry. */
4727 mdep_reorg_phase = SH_INSERT_USES_LABELS;
4730 /* Remove all REG_LABEL notes. We want to use them for our own
4731 purposes. This works because none of the remaining passes
4732 need to look at them.
4734 ??? But it may break in the future. We should use a machine
4735 dependent REG_NOTE, or some other approach entirely. */
4736 for (insn = first; insn; insn = NEXT_INSN (insn))
4742 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
4743 remove_note (insn, note);
4747 for (insn = first; insn; insn = NEXT_INSN (insn))
4749 rtx pattern, reg, link, set, scan, dies, label;
4750 int rescan = 0, foundinsn = 0;
4752 if (GET_CODE (insn) == CALL_INSN)
4754 pattern = PATTERN (insn);
4756 if (GET_CODE (pattern) == PARALLEL)
4757 pattern = XVECEXP (pattern, 0, 0);
4758 if (GET_CODE (pattern) == SET)
4759 pattern = SET_SRC (pattern);
4761 if (GET_CODE (pattern) != CALL
4762 || GET_CODE (XEXP (pattern, 0)) != MEM)
4765 reg = XEXP (XEXP (pattern, 0), 0);
4769 reg = sfunc_uses_reg (insn);
4774 if (GET_CODE (reg) != REG)
4777 /* This is a function call via REG. If the only uses of REG
4778 between the time that it is set and the time that it dies
4779 are in function calls, then we can associate all the
4780 function calls with the setting of REG. */
4782 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
4786 if (REG_NOTE_KIND (link) != 0)
4788 linked_insn = XEXP (link, 0);
4789 set = single_set (linked_insn);
4791 && rtx_equal_p (reg, SET_DEST (set))
4792 && ! INSN_DELETED_P (linked_insn))
4801 /* ??? Sometimes global register allocation will have
4802 deleted the insn pointed to by LOG_LINKS. Try
4803 scanning backward to find where the register is set. */
4804 for (scan = PREV_INSN (insn);
4805 scan && GET_CODE (scan) != CODE_LABEL;
4806 scan = PREV_INSN (scan))
4808 if (! INSN_P (scan))
4811 if (! reg_mentioned_p (reg, scan))
4814 if (noncall_uses_reg (reg, scan, &set))
4828 /* The register is set at LINK. */
4830 /* We can only optimize the function call if the register is
4831 being set to a symbol. In theory, we could sometimes
4832 optimize calls to a constant location, but the assembler
4833 and linker do not support that at present. */
4834 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
4835 && GET_CODE (SET_SRC (set)) != LABEL_REF)
4838 /* Scan forward from LINK to the place where REG dies, and
4839 make sure that the only insns which use REG are
4840 themselves function calls. */
4842 /* ??? This doesn't work for call targets that were allocated
4843 by reload, since there may not be a REG_DEAD note for the
4847 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
4851 /* Don't try to trace forward past a CODE_LABEL if we haven't
4852 seen INSN yet. Ordinarily, we will only find the setting insn
4853 in LOG_LINKS if it is in the same basic block. However,
4854 cross-jumping can insert code labels in between the load and
4855 the call, and can result in situations where a single call
4856 insn may have two targets depending on where we came from. */
4858 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
4861 if (! INSN_P (scan))
4864 /* Don't try to trace forward past a JUMP. To optimize
4865 safely, we would have to check that all the
4866 instructions at the jump destination did not use REG. */
4868 if (GET_CODE (scan) == JUMP_INSN)
4871 if (! reg_mentioned_p (reg, scan))
4874 if (noncall_uses_reg (reg, scan, &scanset))
4881 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
4883 /* There is a function call to this register other
4884 than the one we are checking. If we optimize
4885 this call, we need to rescan again below. */
4889 /* ??? We shouldn't have to worry about SCANSET here.
4890 We should just be able to check for a REG_DEAD note
4891 on a function call. However, the REG_DEAD notes are
4892 apparently not dependable around libcalls; c-torture
4893 execute/920501-2 is a test case. If SCANSET is set,
4894 then this insn sets the register, so it must have
4895 died earlier. Unfortunately, this will only handle
4896 the cases in which the register is, in fact, set in a
4899 /* ??? We shouldn't have to use FOUNDINSN here.
4900 However, the LOG_LINKS fields are apparently not
4901 entirely reliable around libcalls;
4902 newlib/libm/math/e_pow.c is a test case. Sometimes
4903 an insn will appear in LOG_LINKS even though it is
4904 not the most recent insn which sets the register. */
4908 || find_reg_note (scan, REG_DEAD, reg)))
4917 /* Either there was a branch, or some insn used REG
4918 other than as a function call address. */
4922 /* Create a code label, and put it in a REG_LABEL note on
4923 the insn which sets the register, and on each call insn
4924 which uses the register. In final_prescan_insn we look
4925 for the REG_LABEL notes, and output the appropriate label
4928 label = gen_label_rtx ();
4929 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
4931 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
4940 scan = NEXT_INSN (scan);
4942 && ((GET_CODE (scan) == CALL_INSN
4943 && reg_mentioned_p (reg, scan))
4944 || ((reg2 = sfunc_uses_reg (scan))
4945 && REGNO (reg2) == REGNO (reg))))
4947 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
4949 while (scan != dies);
4955 fixup_addr_diff_vecs (first);
4959 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
4960 shorten_branches (first);
4963 /* Scan the function looking for move instructions which have to be
4964 changed to pc-relative loads and insert the literal tables. */
4965 label_ref_list_pool = create_alloc_pool ("label references list",
4966 sizeof (struct label_ref_list_d),
4968 mdep_reorg_phase = SH_FIXUP_PCLOAD;
4969 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
4973 /* ??? basic block reordering can move a switch table dispatch
4974 below the switch table. Check if that has happened.
4975 We only have the addresses available when optimizing; but then,
4976 this check shouldn't be needed when not optimizing. */
4977 if (!untangle_mova (&num_mova, &mova, insn))
4983 else if (GET_CODE (insn) == JUMP_INSN
4984 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
4986 /* ??? loop invariant motion can also move a mova out of a
4987 loop. Since loop does this code motion anyway, maybe we
4988 should wrap UNSPEC_MOVA into a CONST, so that reload can
4991 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
4992 || (prev_nonnote_insn (insn)
4993 == XEXP (MOVA_LABELREF (mova), 0))))
5000 /* Some code might have been inserted between the mova and
5001 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5002 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5003 total += get_attr_length (scan);
5005 /* range of mova is 1020, add 4 because pc counts from address of
5006 second instruction after this one, subtract 2 in case pc is 2
5007 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5008 cancels out with alignment effects of the mova itself. */
5011 /* Change the mova into a load, and restart scanning
5012 there. broken_move will then return true for mova. */
5017 if (broken_move (insn)
5018 || (GET_CODE (insn) == INSN
5019 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5022 /* Scan ahead looking for a barrier to stick the constant table
5024 rtx barrier = find_barrier (num_mova, mova, insn);
5025 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5026 int need_aligned_label = 0;
5028 if (num_mova && ! mova_p (mova))
5030 /* find_barrier had to change the first mova into a
5031 pcload; thus, we have to start with this new pcload. */
5035 /* Now find all the moves between the points and modify them. */
5036 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5038 if (GET_CODE (scan) == CODE_LABEL)
5040 if (GET_CODE (scan) == INSN
5041 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5042 need_aligned_label = 1;
5043 if (broken_move (scan))
5045 rtx *patp = &PATTERN (scan), pat = *patp;
5049 enum machine_mode mode;
5051 if (GET_CODE (pat) == PARALLEL)
5052 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5053 src = SET_SRC (pat);
5054 dst = SET_DEST (pat);
5055 mode = GET_MODE (dst);
5057 if (mode == SImode && hi_const (src)
5058 && REGNO (dst) != FPUL_REG)
5063 while (GET_CODE (dst) == SUBREG)
5065 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5066 GET_MODE (SUBREG_REG (dst)),
5069 dst = SUBREG_REG (dst);
5071 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5073 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
5075 /* This must be an insn that clobbers r0. */
5076 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5077 XVECLEN (PATTERN (scan), 0)
5079 rtx clobber = *clobberp;
5081 gcc_assert (GET_CODE (clobber) == CLOBBER
5082 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5085 && reg_set_between_p (r0_rtx, last_float_move, scan))
5089 && GET_MODE_SIZE (mode) != 4
5090 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5092 lab = add_constant (src, mode, last_float);
5094 emit_insn_before (gen_mova (lab), scan);
5097 /* There will be a REG_UNUSED note for r0 on
5098 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5099 lest reorg:mark_target_live_regs will not
5100 consider r0 to be used, and we end up with delay
5101 slot insn in front of SCAN that clobbers r0. */
5103 = find_regno_note (last_float_move, REG_UNUSED, 0);
5105 /* If we are not optimizing, then there may not be
5108 PUT_MODE (note, REG_INC);
5110 *last_float_addr = r0_inc_rtx;
5112 last_float_move = scan;
5114 newsrc = gen_const_mem (mode,
5115 (((TARGET_SH4 && ! TARGET_FMOVD)
5116 || REGNO (dst) == FPUL_REG)
5119 last_float_addr = &XEXP (newsrc, 0);
5121 /* Remove the clobber of r0. */
5122 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5123 gen_rtx_SCRATCH (Pmode));
5125 /* This is a mova needing a label. Create it. */
5126 else if (GET_CODE (src) == UNSPEC
5127 && XINT (src, 1) == UNSPEC_MOVA
5128 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5130 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5131 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5132 newsrc = gen_rtx_UNSPEC (SImode,
5133 gen_rtvec (1, newsrc),
5138 lab = add_constant (src, mode, 0);
5139 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5140 newsrc = gen_const_mem (mode, newsrc);
5142 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5143 INSN_CODE (scan) = -1;
5146 dump_table (need_aligned_label ? insn : 0, barrier);
5150 free_alloc_pool (label_ref_list_pool);
5151 for (insn = first; insn; insn = NEXT_INSN (insn))
5152 PUT_MODE (insn, VOIDmode);
5154 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5155 INSN_ADDRESSES_FREE ();
5156 split_branches (first);
5158 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5159 also has an effect on the register that holds the address of the sfunc.
5160 Insert an extra dummy insn in front of each sfunc that pretends to
5161 use this register. */
5162 if (flag_delayed_branch)
5164 for (insn = first; insn; insn = NEXT_INSN (insn))
5166 rtx reg = sfunc_uses_reg (insn);
5170 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5174 /* fpscr is not actually a user variable, but we pretend it is for the
5175 sake of the previous optimization passes, since we want it handled like
5176 one. However, we don't have any debugging information for it, so turn
5177 it into a non-user variable now. */
5179 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5181 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5185 get_dest_uid (rtx label, int max_uid)
5187 rtx dest = next_real_insn (label);
5190 /* This can happen for an undefined label. */
5192 dest_uid = INSN_UID (dest);
5193 /* If this is a newly created branch redirection blocking instruction,
5194 we cannot index the branch_uid or insn_addresses arrays with its
5195 uid. But then, we won't need to, because the actual destination is
5196 the following branch. */
5197 while (dest_uid >= max_uid)
5199 dest = NEXT_INSN (dest);
5200 dest_uid = INSN_UID (dest);
5202 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
5207 /* Split condbranches that are out of range. Also add clobbers for
5208 scratch registers that are needed in far jumps.
5209 We do this before delay slot scheduling, so that it can take our
5210 newly created instructions into account. It also allows us to
5211 find branches with common targets more easily. */
5214 split_branches (rtx first)
5217 struct far_branch **uid_branch, *far_branch_list = 0;
5218 int max_uid = get_max_uid ();
5221 /* Find out which branches are out of range. */
5222 shorten_branches (first);
5224 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5225 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5227 for (insn = first; insn; insn = NEXT_INSN (insn))
5228 if (! INSN_P (insn))
5230 else if (INSN_DELETED_P (insn))
5232 /* Shorten_branches would split this instruction again,
5233 so transform it into a note. */
5234 SET_INSN_DELETED (insn);
5236 else if (GET_CODE (insn) == JUMP_INSN
5237 /* Don't mess with ADDR_DIFF_VEC */
5238 && (GET_CODE (PATTERN (insn)) == SET
5239 || GET_CODE (PATTERN (insn)) == RETURN))
5241 enum attr_type type = get_attr_type (insn);
5242 if (type == TYPE_CBRANCH)
5246 if (get_attr_length (insn) > 4)
5248 rtx src = SET_SRC (PATTERN (insn));
5249 rtx olabel = XEXP (XEXP (src, 1), 0);
5250 int addr = INSN_ADDRESSES (INSN_UID (insn));
5252 int dest_uid = get_dest_uid (olabel, max_uid);
5253 struct far_branch *bp = uid_branch[dest_uid];
5255 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5256 the label if the LABEL_NUSES count drops to zero. There is
5257 always a jump_optimize pass that sets these values, but it
5258 proceeds to delete unreferenced code, and then if not
5259 optimizing, to un-delete the deleted instructions, thus
5260 leaving labels with too low uses counts. */
5263 JUMP_LABEL (insn) = olabel;
5264 LABEL_NUSES (olabel)++;
5268 bp = (struct far_branch *) alloca (sizeof *bp);
5269 uid_branch[dest_uid] = bp;
5270 bp->prev = far_branch_list;
5271 far_branch_list = bp;
5273 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5274 LABEL_NUSES (bp->far_label)++;
5278 label = bp->near_label;
5279 if (! label && bp->address - addr >= CONDJUMP_MIN)
5281 rtx block = bp->insert_place;
5283 if (GET_CODE (PATTERN (block)) == RETURN)
5284 block = PREV_INSN (block);
5286 block = gen_block_redirect (block,
5288 label = emit_label_after (gen_label_rtx (),
5290 bp->near_label = label;
5292 else if (label && ! NEXT_INSN (label))
5294 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5295 bp->insert_place = insn;
5297 gen_far_branch (bp);
5301 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5303 bp->near_label = label = gen_label_rtx ();
5304 bp->insert_place = insn;
5307 ok = redirect_jump (insn, label, 1);
5312 /* get_attr_length (insn) == 2 */
5313 /* Check if we have a pattern where reorg wants to redirect
5314 the branch to a label from an unconditional branch that
5316 /* We can't use JUMP_LABEL here because it might be undefined
5317 when not optimizing. */
5318 /* A syntax error might cause beyond to be NULL_RTX. */
5320 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5324 && (GET_CODE (beyond) == JUMP_INSN
5325 || ((beyond = next_active_insn (beyond))
5326 && GET_CODE (beyond) == JUMP_INSN))
5327 && GET_CODE (PATTERN (beyond)) == SET
5328 && recog_memoized (beyond) == CODE_FOR_jump_compact
5330 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5331 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5333 gen_block_redirect (beyond,
5334 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5337 next = next_active_insn (insn);
5339 if ((GET_CODE (next) == JUMP_INSN
5340 || ((next = next_active_insn (next))
5341 && GET_CODE (next) == JUMP_INSN))
5342 && GET_CODE (PATTERN (next)) == SET
5343 && recog_memoized (next) == CODE_FOR_jump_compact
5345 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5346 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5348 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5350 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5352 int addr = INSN_ADDRESSES (INSN_UID (insn));
5355 struct far_branch *bp;
5357 if (type == TYPE_JUMP)
5359 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5360 dest_uid = get_dest_uid (far_label, max_uid);
5363 /* Parse errors can lead to labels outside
5365 if (! NEXT_INSN (far_label))
5370 JUMP_LABEL (insn) = far_label;
5371 LABEL_NUSES (far_label)++;
5373 redirect_jump (insn, NULL_RTX, 1);
5377 bp = uid_branch[dest_uid];
5380 bp = (struct far_branch *) alloca (sizeof *bp);
5381 uid_branch[dest_uid] = bp;
5382 bp->prev = far_branch_list;
5383 far_branch_list = bp;
5385 bp->far_label = far_label;
5387 LABEL_NUSES (far_label)++;
5389 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5390 if (addr - bp->address <= CONDJUMP_MAX)
5391 emit_label_after (bp->near_label, PREV_INSN (insn));
5394 gen_far_branch (bp);
5400 bp->insert_place = insn;
5402 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5404 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5407 /* Generate all pending far branches,
5408 and free our references to the far labels. */
5409 while (far_branch_list)
5411 if (far_branch_list->near_label
5412 && ! NEXT_INSN (far_branch_list->near_label))
5413 gen_far_branch (far_branch_list);
5415 && far_branch_list->far_label
5416 && ! --LABEL_NUSES (far_branch_list->far_label))
5417 delete_insn (far_branch_list->far_label);
5418 far_branch_list = far_branch_list->prev;
5421 /* Instruction length information is no longer valid due to the new
5422 instructions that have been generated. */
5423 init_insn_lengths ();
5426 /* Dump out instruction addresses, which is useful for debugging the
5427 constant pool table stuff.
5429 If relaxing, output the label and pseudo-ops used to link together
5430 calls and the instruction which set the registers. */
5432 /* ??? The addresses printed by this routine for insns are nonsense for
5433 insns which are inside of a sequence where none of the inner insns have
5434 variable length. This is because the second pass of shorten_branches
5435 does not bother to update them. */
5438 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5439 int noperands ATTRIBUTE_UNUSED)
5441 if (TARGET_DUMPISIZE)
5442 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5448 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
5453 pattern = PATTERN (insn);
5454 if (GET_CODE (pattern) == PARALLEL)
5455 pattern = XVECEXP (pattern, 0, 0);
5456 switch (GET_CODE (pattern))
5459 if (GET_CODE (SET_SRC (pattern)) != CALL
5460 && get_attr_type (insn) != TYPE_SFUNC)
5462 targetm.asm_out.internal_label
5463 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5466 /* else FALLTHROUGH */
5468 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5469 CODE_LABEL_NUMBER (XEXP (note, 0)));
5479 /* Dump out any constants accumulated in the final pass. These will
5483 output_jump_label_table (void)
5489 fprintf (asm_out_file, "\t.align 2\n");
5490 for (i = 0; i < pool_size; i++)
5492 pool_node *p = &pool_vector[i];
5494 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5495 CODE_LABEL_NUMBER (p->label));
5496 output_asm_insn (".long %O0", &p->value);
5504 /* A full frame looks like:
5508 [ if current_function_anonymous_args
5521 local-0 <- fp points here. */
5523 /* Number of bytes pushed for anonymous args, used to pass information
5524 between expand_prologue and expand_epilogue. */
5526 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
5527 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
5528 for an epilogue and a negative value means that it's for a sibcall
5529 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
5530 all the registers that are about to be restored, and hence dead. */
5533 output_stack_adjust (int size, rtx reg, int epilogue_p,
5534 HARD_REG_SET *live_regs_mask)
5536 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
5539 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
5541 /* This test is bogus, as output_stack_adjust is used to re-align the
5544 gcc_assert (!(size % align));
5547 if (CONST_OK_FOR_ADD (size))
5548 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
5549 /* Try to do it with two partial adjustments; however, we must make
5550 sure that the stack is properly aligned at all times, in case
5551 an interrupt occurs between the two partial adjustments. */
5552 else if (CONST_OK_FOR_ADD (size / 2 & -align)
5553 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
5555 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
5556 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
5562 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
5565 /* If TEMP is invalid, we could temporarily save a general
5566 register to MACL. However, there is currently no need
5567 to handle this case, so just die when we see it. */
5569 || current_function_interrupt
5570 || ! call_really_used_regs[temp] || fixed_regs[temp])
5572 if (temp < 0 && ! current_function_interrupt
5573 && (TARGET_SHMEDIA || epilogue_p >= 0))
5576 COPY_HARD_REG_SET (temps, call_used_reg_set);
5577 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
5581 if (current_function_return_rtx)
5583 enum machine_mode mode;
5584 mode = GET_MODE (current_function_return_rtx);
5585 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
5586 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
5588 for (i = 0; i < nreg; i++)
5589 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
5590 if (current_function_calls_eh_return)
5592 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
5593 for (i = 0; i <= 3; i++)
5594 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
5597 if (TARGET_SHMEDIA && epilogue_p < 0)
5598 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
5599 CLEAR_HARD_REG_BIT (temps, i);
5600 if (epilogue_p <= 0)
5602 for (i = FIRST_PARM_REG;
5603 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
5604 CLEAR_HARD_REG_BIT (temps, i);
5605 if (cfun->static_chain_decl != NULL)
5606 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
5608 temp = scavenge_reg (&temps);
5610 if (temp < 0 && live_regs_mask)
5614 COPY_HARD_REG_SET (temps, *live_regs_mask);
5615 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
5616 temp = scavenge_reg (&temps);
5620 rtx adj_reg, tmp_reg, mem;
5622 /* If we reached here, the most likely case is the (sibcall)
5623 epilogue for non SHmedia. Put a special push/pop sequence
5624 for such case as the last resort. This looks lengthy but
5625 would not be problem because it seems to be very
5628 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
5631 /* ??? There is still the slight possibility that r4 or
5632 r5 have been reserved as fixed registers or assigned
5633 as global registers, and they change during an
5634 interrupt. There are possible ways to handle this:
5636 - If we are adjusting the frame pointer (r14), we can do
5637 with a single temp register and an ordinary push / pop
5639 - Grab any call-used or call-saved registers (i.e. not
5640 fixed or globals) for the temps we need. We might
5641 also grab r14 if we are adjusting the stack pointer.
5642 If we can't find enough available registers, issue
5643 a diagnostic and die - the user must have reserved
5644 way too many registers.
5645 But since all this is rather unlikely to happen and
5646 would require extra testing, we just die if r4 / r5
5647 are not available. */
5648 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
5649 && !global_regs[4] && !global_regs[5]);
5651 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
5652 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
5653 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
5654 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
5655 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
5656 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5657 emit_move_insn (mem, tmp_reg);
5658 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
5659 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
5660 emit_move_insn (mem, tmp_reg);
5661 emit_move_insn (reg, adj_reg);
5662 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5663 emit_move_insn (adj_reg, mem);
5664 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
5665 emit_move_insn (tmp_reg, mem);
5666 /* Tell flow the insns that pop r4/r5 aren't dead. */
5667 emit_insn (gen_rtx_USE (VOIDmode, tmp_reg));
5668 emit_insn (gen_rtx_USE (VOIDmode, adj_reg));
5671 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
5673 /* If SIZE is negative, subtract the positive value.
5674 This sometimes allows a constant pool entry to be shared
5675 between prologue and epilogue code. */
5678 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
5679 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
5683 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
5684 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
5688 = (gen_rtx_EXPR_LIST
5689 (REG_FRAME_RELATED_EXPR,
5690 gen_rtx_SET (VOIDmode, reg,
5691 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
5701 RTX_FRAME_RELATED_P (x) = 1;
5705 /* Output RTL to push register RN onto the stack. */
5712 x = gen_push_fpul ();
5713 else if (rn == FPSCR_REG)
5714 x = gen_push_fpscr ();
5715 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5716 && FP_OR_XD_REGISTER_P (rn))
5718 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5720 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
5722 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5723 x = gen_push_e (gen_rtx_REG (SFmode, rn));
5725 x = gen_push (gen_rtx_REG (SImode, rn));
5729 = gen_rtx_EXPR_LIST (REG_INC,
5730 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5734 /* Output RTL to pop register RN from the stack. */
5741 x = gen_pop_fpul ();
5742 else if (rn == FPSCR_REG)
5743 x = gen_pop_fpscr ();
5744 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
5745 && FP_OR_XD_REGISTER_P (rn))
5747 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
5749 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
5751 else if (TARGET_SH2E && FP_REGISTER_P (rn))
5752 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
5754 x = gen_pop (gen_rtx_REG (SImode, rn));
5758 = gen_rtx_EXPR_LIST (REG_INC,
5759 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
5762 /* Generate code to push the regs specified in the mask. */
5765 push_regs (HARD_REG_SET *mask, int interrupt_handler)
5770 /* Push PR last; this gives better latencies after the prologue, and
5771 candidates for the return delay slot when there are no general
5772 registers pushed. */
5773 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5775 /* If this is an interrupt handler, and the SZ bit varies,
5776 and we have to push any floating point register, we need
5777 to switch to the correct precision first. */
5778 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
5779 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
5781 HARD_REG_SET unsaved;
5784 COMPL_HARD_REG_SET (unsaved, *mask);
5785 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
5789 && (i != FPSCR_REG || ! skip_fpscr)
5790 && TEST_HARD_REG_BIT (*mask, i))
5793 if (TEST_HARD_REG_BIT (*mask, PR_REG))
5797 /* Calculate how much extra space is needed to save all callee-saved
5799 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5802 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
5805 int stack_space = 0;
5806 int interrupt_handler = sh_cfun_interrupt_handler_p ();
5808 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5809 if ((! call_really_used_regs[reg] || interrupt_handler)
5810 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5811 /* Leave space to save this target register on the stack,
5812 in case target register allocation wants to use it. */
5813 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5817 /* Decide whether we should reserve space for callee-save target registers,
5818 in case target register allocation wants to use them. REGS_SAVED is
5819 the space, in bytes, that is already required for register saves.
5820 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5823 shmedia_reserve_space_for_target_registers_p (int regs_saved,
5824 HARD_REG_SET *live_regs_mask)
5828 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
5831 /* Decide how much space to reserve for callee-save target registers
5832 in case target register allocation wants to use them.
5833 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
5836 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
5838 if (shmedia_space_reserved_for_target_registers)
5839 return shmedia_target_regs_stack_space (live_regs_mask);
5844 /* Work out the registers which need to be saved, both as a mask and a
5845 count of saved words. Return the count.
5847 If doing a pragma interrupt function, then push all regs used by the
5848 function, and if we call another function (we can tell by looking at PR),
5849 make sure that all the regs it clobbers are safe too. */
5852 calc_live_regs (HARD_REG_SET *live_regs_mask)
5857 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
5858 bool nosave_low_regs;
5859 int pr_live, has_call;
5861 attrs = DECL_ATTRIBUTES (current_function_decl);
5862 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
5863 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
5864 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
5865 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
5867 CLEAR_HARD_REG_SET (*live_regs_mask);
5868 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
5869 && regs_ever_live[FPSCR_REG])
5870 target_flags &= ~MASK_FPU_SINGLE;
5871 /* If we can save a lot of saves by switching to double mode, do that. */
5872 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
5873 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
5874 if (regs_ever_live[reg] && regs_ever_live[reg+1]
5875 && (! call_really_used_regs[reg]
5876 || interrupt_handler)
5879 target_flags &= ~MASK_FPU_SINGLE;
5882 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
5883 knows how to use it. That means the pseudo originally allocated for
5884 the initial value can become the PR_MEDIA_REG hard register, as seen for
5885 execute/20010122-1.c:test9. */
5887 /* ??? this function is called from initial_elimination_offset, hence we
5888 can't use the result of sh_media_register_for_return here. */
5889 pr_live = sh_pr_n_sets ();
5892 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
5893 pr_live = (pr_initial
5894 ? (GET_CODE (pr_initial) != REG
5895 || REGNO (pr_initial) != (PR_REG))
5896 : regs_ever_live[PR_REG]);
5897 /* For Shcompact, if not optimizing, we end up with a memory reference
5898 using the return address pointer for __builtin_return_address even
5899 though there is no actual need to put the PR register on the stack. */
5900 pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
5902 /* Force PR to be live if the prologue has to call the SHmedia
5903 argument decoder or register saver. */
5904 if (TARGET_SHCOMPACT
5905 && ((current_function_args_info.call_cookie
5906 & ~ CALL_COOKIE_RET_TRAMP (1))
5907 || current_function_has_nonlocal_label))
5909 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
5910 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
5912 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
5915 ? (/* Need to save all the regs ever live. */
5916 (regs_ever_live[reg]
5917 || (call_really_used_regs[reg]
5918 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
5919 || reg == PIC_OFFSET_TABLE_REGNUM)
5921 || (TARGET_SHMEDIA && has_call
5922 && REGISTER_NATURAL_MODE (reg) == SImode
5923 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
5924 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
5925 && reg != RETURN_ADDRESS_POINTER_REGNUM
5926 && reg != T_REG && reg != GBR_REG
5927 /* Push fpscr only on targets which have FPU */
5928 && (reg != FPSCR_REG || TARGET_FPU_ANY))
5929 : (/* Only push those regs which are used and need to be saved. */
5932 && current_function_args_info.call_cookie
5933 && reg == PIC_OFFSET_TABLE_REGNUM)
5934 || (regs_ever_live[reg]
5935 && (!call_really_used_regs[reg]
5936 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
5937 || (current_function_calls_eh_return
5938 && (reg == EH_RETURN_DATA_REGNO (0)
5939 || reg == EH_RETURN_DATA_REGNO (1)
5940 || reg == EH_RETURN_DATA_REGNO (2)
5941 || reg == EH_RETURN_DATA_REGNO (3)))
5942 || ((reg == MACL_REG || reg == MACH_REG)
5943 && regs_ever_live[reg]
5944 && sh_cfun_attr_renesas_p ())
5947 SET_HARD_REG_BIT (*live_regs_mask, reg);
5948 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5950 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
5951 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
5953 if (FP_REGISTER_P (reg))
5955 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
5957 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
5958 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
5961 else if (XD_REGISTER_P (reg))
5963 /* Must switch to double mode to access these registers. */
5964 target_flags &= ~MASK_FPU_SINGLE;
5968 if (nosave_low_regs && reg == R8_REG)
5971 /* If we have a target register optimization pass after prologue / epilogue
5972 threading, we need to assume all target registers will be live even if
5974 if (flag_branch_target_load_optimize2
5975 && TARGET_SAVE_ALL_TARGET_REGS
5976 && shmedia_space_reserved_for_target_registers)
5977 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
5978 if ((! call_really_used_regs[reg] || interrupt_handler)
5979 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
5981 SET_HARD_REG_BIT (*live_regs_mask, reg);
5982 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
5984 /* If this is an interrupt handler, we don't have any call-clobbered
5985 registers we can conveniently use for target register save/restore.
5986 Make sure we save at least one general purpose register when we need
5987 to save target registers. */
5988 if (interrupt_handler
5989 && hard_reg_set_intersect_p (*live_regs_mask,
5990 reg_class_contents[TARGET_REGS])
5991 && ! hard_reg_set_intersect_p (*live_regs_mask,
5992 reg_class_contents[GENERAL_REGS]))
5994 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
5995 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6001 /* Code to generate prologue and epilogue sequences */
6003 /* PUSHED is the number of bytes that are being pushed on the
6004 stack for register saves. Return the frame size, padded
6005 appropriately so that the stack stays properly aligned. */
6006 static HOST_WIDE_INT
6007 rounded_frame_size (int pushed)
6009 HOST_WIDE_INT size = get_frame_size ();
6010 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6012 return ((size + pushed + align - 1) & -align) - pushed;
6015 /* Choose a call-clobbered target-branch register that remains
6016 unchanged along the whole function. We set it up as the return
6017 value in the prologue. */
6019 sh_media_register_for_return (void)
6024 if (! current_function_is_leaf)
6026 if (lookup_attribute ("interrupt_handler",
6027 DECL_ATTRIBUTES (current_function_decl)))
6029 if (sh_cfun_interrupt_handler_p ())
6032 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6034 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6035 if (call_really_used_regs[regno] && ! regs_ever_live[regno])
6041 /* The maximum registers we need to save are:
6042 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6043 - 32 floating point registers (for each pair, we save none,
6044 one single precision value, or a double precision value).
6045 - 8 target registers
6046 - add 1 entry for a delimiter. */
6047 #define MAX_SAVED_REGS (62+32+8)
6049 typedef struct save_entry_s
6058 /* There will be a delimiter entry with VOIDmode both at the start and the
6059 end of a filled in schedule. The end delimiter has the offset of the
6060 save with the smallest (i.e. most negative) offset. */
6061 typedef struct save_schedule_s
6063 save_entry entries[MAX_SAVED_REGS + 2];
6064 int temps[MAX_TEMPS+1];
6067 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6068 use reverse order. Returns the last entry written to (not counting
6069 the delimiter). OFFSET_BASE is a number to be added to all offset
6073 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6077 save_entry *entry = schedule->entries;
6081 if (! current_function_interrupt)
6082 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6083 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6084 && ! FUNCTION_ARG_REGNO_P (i)
6085 && i != FIRST_RET_REG
6086 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6087 && ! (current_function_calls_eh_return
6088 && (i == EH_RETURN_STACKADJ_REGNO
6089 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6090 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6091 schedule->temps[tmpx++] = i;
6093 entry->mode = VOIDmode;
6094 entry->offset = offset_base;
6096 /* We loop twice: first, we save 8-byte aligned registers in the
6097 higher addresses, that are known to be aligned. Then, we
6098 proceed to saving 32-bit registers that don't need 8-byte
6100 If this is an interrupt function, all registers that need saving
6101 need to be saved in full. moreover, we need to postpone saving
6102 target registers till we have saved some general purpose registers
6103 we can then use as scratch registers. */
6104 offset = offset_base;
6105 for (align = 1; align >= 0; align--)
6107 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6108 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6110 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6113 if (current_function_interrupt)
6115 if (TARGET_REGISTER_P (i))
6117 if (GENERAL_REGISTER_P (i))
6120 if (mode == SFmode && (i % 2) == 1
6121 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6122 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6129 /* If we're doing the aligned pass and this is not aligned,
6130 or we're doing the unaligned pass and this is aligned,
6132 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6136 if (current_function_interrupt
6137 && GENERAL_REGISTER_P (i)
6138 && tmpx < MAX_TEMPS)
6139 schedule->temps[tmpx++] = i;
6141 offset -= GET_MODE_SIZE (mode);
6144 entry->offset = offset;
6147 if (align && current_function_interrupt)
6148 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6149 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6151 offset -= GET_MODE_SIZE (DImode);
6153 entry->mode = DImode;
6154 entry->offset = offset;
6159 entry->mode = VOIDmode;
6160 entry->offset = offset;
6161 schedule->temps[tmpx] = -1;
6166 sh_expand_prologue (void)
6168 HARD_REG_SET live_regs_mask;
6171 int save_flags = target_flags;
6174 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6176 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6178 /* We have pretend args if we had an object sent partially in registers
6179 and partially on the stack, e.g. a large structure. */
6180 pretend_args = current_function_pretend_args_size;
6181 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6182 && (NPARM_REGS(SImode)
6183 > current_function_args_info.arg_count[(int) SH_ARG_INT]))
6185 output_stack_adjust (-pretend_args
6186 - current_function_args_info.stack_regs * 8,
6187 stack_pointer_rtx, 0, NULL);
6189 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
6190 /* We're going to use the PIC register to load the address of the
6191 incoming-argument decoder and/or of the return trampoline from
6192 the GOT, so make sure the PIC register is preserved and
6194 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6196 if (TARGET_SHCOMPACT
6197 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6201 /* First, make all registers with incoming arguments that will
6202 be pushed onto the stack live, so that register renaming
6203 doesn't overwrite them. */
6204 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6205 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
6206 >= NPARM_REGS (SImode) - reg)
6207 for (; reg < NPARM_REGS (SImode); reg++)
6208 emit_insn (gen_shcompact_preserve_incoming_args
6209 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6210 else if (CALL_COOKIE_INT_REG_GET
6211 (current_function_args_info.call_cookie, reg) == 1)
6212 emit_insn (gen_shcompact_preserve_incoming_args
6213 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6215 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6217 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6218 GEN_INT (current_function_args_info.call_cookie));
6219 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6220 gen_rtx_REG (SImode, R0_REG));
6222 else if (TARGET_SHMEDIA)
6224 int tr = sh_media_register_for_return ();
6228 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
6229 gen_rtx_REG (DImode, PR_MEDIA_REG));
6231 /* ??? We should suppress saving pr when we don't need it, but this
6232 is tricky because of builtin_return_address. */
6234 /* If this function only exits with sibcalls, this copy
6235 will be flagged as dead. */
6236 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
6242 /* Emit the code for SETUP_VARARGS. */
6243 if (current_function_stdarg)
6245 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6247 /* Push arg regs as if they'd been provided by caller in stack. */
6248 for (i = 0; i < NPARM_REGS(SImode); i++)
6250 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6253 if (i >= (NPARM_REGS(SImode)
6254 - current_function_args_info.arg_count[(int) SH_ARG_INT]
6258 RTX_FRAME_RELATED_P (insn) = 0;
6263 /* If we're supposed to switch stacks at function entry, do so now. */
6266 /* The argument specifies a variable holding the address of the
6267 stack the interrupt function should switch to/from at entry/exit. */
6269 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6270 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6272 emit_insn (gen_sp_switch_1 (sp_switch));
6275 d = calc_live_regs (&live_regs_mask);
6276 /* ??? Maybe we could save some switching if we can move a mode switch
6277 that already happens to be at the function start into the prologue. */
6278 if (target_flags != save_flags && ! current_function_interrupt)
6279 emit_insn (gen_toggle_sz ());
6283 int offset_base, offset;
6285 int offset_in_r0 = -1;
6287 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6288 int total_size, save_size;
6289 save_schedule schedule;
6293 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6294 && ! current_function_interrupt)
6295 r0 = gen_rtx_REG (Pmode, R0_REG);
6297 /* D is the actual number of bytes that we need for saving registers,
6298 however, in initial_elimination_offset we have committed to using
6299 an additional TREGS_SPACE amount of bytes - in order to keep both
6300 addresses to arguments supplied by the caller and local variables
6301 valid, we must keep this gap. Place it between the incoming
6302 arguments and the actually saved registers in a bid to optimize
6303 locality of reference. */
6304 total_size = d + tregs_space;
6305 total_size += rounded_frame_size (total_size);
6306 save_size = total_size - rounded_frame_size (d);
6307 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6308 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6309 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6311 /* If adjusting the stack in a single step costs nothing extra, do so.
6312 I.e. either if a single addi is enough, or we need a movi anyway,
6313 and we don't exceed the maximum offset range (the test for the
6314 latter is conservative for simplicity). */
6316 && (CONST_OK_FOR_I10 (-total_size)
6317 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6318 && total_size <= 2044)))
6319 d_rounding = total_size - save_size;
6321 offset_base = d + d_rounding;
6323 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6326 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6327 tmp_pnt = schedule.temps;
6328 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6330 enum machine_mode mode = entry->mode;
6331 unsigned int reg = entry->reg;
6332 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6335 offset = entry->offset;
6337 reg_rtx = gen_rtx_REG (mode, reg);
6339 mem_rtx = gen_frame_mem (mode,
6340 gen_rtx_PLUS (Pmode,
6344 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
6351 if (HAVE_PRE_DECREMENT
6352 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6353 || mem_rtx == NULL_RTX
6354 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6356 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6358 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
6367 offset += GET_MODE_SIZE (mode);
6371 if (mem_rtx != NULL_RTX)
6374 if (offset_in_r0 == -1)
6376 emit_move_insn (r0, GEN_INT (offset));
6377 offset_in_r0 = offset;
6379 else if (offset != offset_in_r0)
6384 GEN_INT (offset - offset_in_r0)));
6385 offset_in_r0 += offset - offset_in_r0;
6388 if (pre_dec != NULL_RTX)
6394 (Pmode, r0, stack_pointer_rtx));
6398 offset -= GET_MODE_SIZE (mode);
6399 offset_in_r0 -= GET_MODE_SIZE (mode);
6404 mem_rtx = gen_frame_mem (mode, r0);
6406 mem_rtx = gen_frame_mem (mode,
6407 gen_rtx_PLUS (Pmode,
6411 /* We must not use an r0-based address for target-branch
6412 registers or for special registers without pre-dec
6413 memory addresses, since we store their values in r0
6415 gcc_assert (!TARGET_REGISTER_P (reg)
6416 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6417 || mem_rtx == pre_dec));
6420 orig_reg_rtx = reg_rtx;
6421 if (TARGET_REGISTER_P (reg)
6422 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6423 && mem_rtx != pre_dec))
6425 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6427 emit_move_insn (tmp_reg, reg_rtx);
6429 if (REGNO (tmp_reg) == R0_REG)
6433 gcc_assert (!refers_to_regno_p
6434 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6437 if (*++tmp_pnt <= 0)
6438 tmp_pnt = schedule.temps;
6445 /* Mark as interesting for dwarf cfi generator */
6446 insn = emit_move_insn (mem_rtx, reg_rtx);
6447 RTX_FRAME_RELATED_P (insn) = 1;
6448 /* If we use an intermediate register for the save, we can't
6449 describe this exactly in cfi as a copy of the to-be-saved
6450 register into the temporary register and then the temporary
6451 register on the stack, because the temporary register can
6452 have a different natural size than the to-be-saved register.
6453 Thus, we gloss over the intermediate copy and pretend we do
6454 a direct save from the to-be-saved register. */
6455 if (REGNO (reg_rtx) != reg)
6459 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6460 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6462 REG_NOTES (insn) = note_rtx;
6465 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6467 rtx reg_rtx = gen_rtx_REG (mode, reg);
6469 rtx mem_rtx = gen_frame_mem (mode,
6470 gen_rtx_PLUS (Pmode,
6474 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6475 note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
6477 REG_NOTES (insn) = note_rtx;
6482 gcc_assert (entry->offset == d_rounding);
6485 push_regs (&live_regs_mask, current_function_interrupt);
6487 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6489 rtx insn = get_last_insn ();
6490 rtx last = emit_insn (gen_GOTaddr2picreg ());
6492 /* Mark these insns as possibly dead. Sometimes, flow2 may
6493 delete all uses of the PIC register. In this case, let it
6494 delete the initialization too. */
6497 insn = NEXT_INSN (insn);
6499 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
6503 while (insn != last);
6506 if (SHMEDIA_REGS_STACK_ADJUST ())
6508 /* This must NOT go through the PLT, otherwise mach and macl
6509 may be clobbered. */
6510 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6512 ? "__GCC_push_shmedia_regs"
6513 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6514 emit_insn (gen_shmedia_save_restore_regs_compact
6515 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6518 if (target_flags != save_flags && ! current_function_interrupt)
6520 rtx insn = emit_insn (gen_toggle_sz ());
6522 /* If we're lucky, a mode switch in the function body will
6523 overwrite fpscr, turning this insn dead. Tell flow this
6524 insn is ok to delete. */
6525 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
6530 target_flags = save_flags;
6532 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6533 stack_pointer_rtx, 0, NULL);
6535 if (frame_pointer_needed)
6536 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6538 if (TARGET_SHCOMPACT
6539 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6541 /* This must NOT go through the PLT, otherwise mach and macl
6542 may be clobbered. */
6543 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6544 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6545 emit_insn (gen_shcompact_incoming_args ());
6550 sh_expand_epilogue (bool sibcall_p)
6552 HARD_REG_SET live_regs_mask;
6556 int save_flags = target_flags;
6557 int frame_size, save_size;
6558 int fpscr_deferred = 0;
6559 int e = sibcall_p ? -1 : 1;
6561 d = calc_live_regs (&live_regs_mask);
6564 frame_size = rounded_frame_size (d);
6568 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6570 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
6571 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6572 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
6574 total_size = d + tregs_space;
6575 total_size += rounded_frame_size (total_size);
6576 save_size = total_size - frame_size;
6578 /* If adjusting the stack in a single step costs nothing extra, do so.
6579 I.e. either if a single addi is enough, or we need a movi anyway,
6580 and we don't exceed the maximum offset range (the test for the
6581 latter is conservative for simplicity). */
6583 && ! frame_pointer_needed
6584 && (CONST_OK_FOR_I10 (total_size)
6585 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
6586 && total_size <= 2044)))
6587 d_rounding = frame_size;
6589 frame_size -= d_rounding;
6592 if (frame_pointer_needed)
6594 /* We must avoid scheduling the epilogue with previous basic blocks
6595 when exception handling is enabled. See PR/18032. */
6596 if (flag_exceptions)
6597 emit_insn (gen_blockage ());
6598 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
6601 /* We must avoid moving the stack pointer adjustment past code
6602 which reads from the local frame, else an interrupt could
6603 occur after the SP adjustment and clobber data in the local
6605 emit_insn (gen_blockage ());
6606 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
6608 else if (frame_size)
6610 /* We must avoid moving the stack pointer adjustment past code
6611 which reads from the local frame, else an interrupt could
6612 occur after the SP adjustment and clobber data in the local
6614 emit_insn (gen_blockage ());
6615 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
6618 if (SHMEDIA_REGS_STACK_ADJUST ())
6620 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6622 ? "__GCC_pop_shmedia_regs"
6623 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
6624 /* This must NOT go through the PLT, otherwise mach and macl
6625 may be clobbered. */
6626 emit_insn (gen_shmedia_save_restore_regs_compact
6627 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
6630 /* Pop all the registers. */
6632 if (target_flags != save_flags && ! current_function_interrupt)
6633 emit_insn (gen_toggle_sz ());
6636 int offset_base, offset;
6637 int offset_in_r0 = -1;
6639 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
6640 save_schedule schedule;
6644 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
6645 offset_base = -entry[1].offset + d_rounding;
6646 tmp_pnt = schedule.temps;
6647 for (; entry->mode != VOIDmode; entry--)
6649 enum machine_mode mode = entry->mode;
6650 int reg = entry->reg;
6651 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
6653 offset = offset_base + entry->offset;
6654 reg_rtx = gen_rtx_REG (mode, reg);
6656 mem_rtx = gen_frame_mem (mode,
6657 gen_rtx_PLUS (Pmode,
6661 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
6667 if (HAVE_POST_INCREMENT
6668 && (offset == offset_in_r0
6669 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
6670 && mem_rtx == NULL_RTX)
6671 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6673 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
6675 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
6678 post_inc = NULL_RTX;
6687 if (mem_rtx != NULL_RTX)
6690 if (offset_in_r0 == -1)
6692 emit_move_insn (r0, GEN_INT (offset));
6693 offset_in_r0 = offset;
6695 else if (offset != offset_in_r0)
6700 GEN_INT (offset - offset_in_r0)));
6701 offset_in_r0 += offset - offset_in_r0;
6704 if (post_inc != NULL_RTX)
6710 (Pmode, r0, stack_pointer_rtx));
6716 offset_in_r0 += GET_MODE_SIZE (mode);
6719 mem_rtx = gen_frame_mem (mode, r0);
6721 mem_rtx = gen_frame_mem (mode,
6722 gen_rtx_PLUS (Pmode,
6726 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6727 || mem_rtx == post_inc);
6730 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6731 && mem_rtx != post_inc)
6733 insn = emit_move_insn (r0, mem_rtx);
6736 else if (TARGET_REGISTER_P (reg))
6738 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
6740 /* Give the scheduler a bit of freedom by using up to
6741 MAX_TEMPS registers in a round-robin fashion. */
6742 insn = emit_move_insn (tmp_reg, mem_rtx);
6745 tmp_pnt = schedule.temps;
6748 insn = emit_move_insn (reg_rtx, mem_rtx);
6749 if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
6750 /* This is dead, unless we return with a sibcall. */
6751 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
6756 gcc_assert (entry->offset + offset_base == d + d_rounding);
6758 else /* ! TARGET_SH5 */
6761 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6763 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6765 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
6767 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
6768 && hard_reg_set_intersect_p (live_regs_mask,
6769 reg_class_contents[DF_REGS]))
6771 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
6773 if (j == FIRST_FP_REG && fpscr_deferred)
6778 if (target_flags != save_flags && ! current_function_interrupt)
6779 emit_insn (gen_toggle_sz ());
6780 target_flags = save_flags;
6782 output_stack_adjust (current_function_pretend_args_size
6783 + save_size + d_rounding
6784 + current_function_args_info.stack_regs * 8,
6785 stack_pointer_rtx, e, NULL);
6787 if (current_function_calls_eh_return)
6788 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
6789 EH_RETURN_STACKADJ_RTX));
6791 /* Switch back to the normal stack if necessary. */
6792 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
6793 emit_insn (gen_sp_switch_2 ());
6795 /* Tell flow the insn that pops PR isn't dead. */
6796 /* PR_REG will never be live in SHmedia mode, and we don't need to
6797 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
6798 by the return pattern. */
6799 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
6800 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
6803 static int sh_need_epilogue_known = 0;
6806 sh_need_epilogue (void)
6808 if (! sh_need_epilogue_known)
6813 sh_expand_epilogue (0);
6814 epilogue = get_insns ();
6816 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
6818 return sh_need_epilogue_known > 0;
6821 /* Emit code to change the current function's return address to RA.
6822 TEMP is available as a scratch register, if needed. */
6825 sh_set_return_address (rtx ra, rtx tmp)
6827 HARD_REG_SET live_regs_mask;
6829 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
6832 d = calc_live_regs (&live_regs_mask);
6834 /* If pr_reg isn't life, we can set it (or the register given in
6835 sh_media_register_for_return) directly. */
6836 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
6842 int rr_regno = sh_media_register_for_return ();
6847 rr = gen_rtx_REG (DImode, rr_regno);
6850 rr = gen_rtx_REG (SImode, pr_reg);
6852 emit_insn (GEN_MOV (rr, ra));
6853 /* Tell flow the register for return isn't dead. */
6854 emit_insn (gen_rtx_USE (VOIDmode, rr));
6861 save_schedule schedule;
6864 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
6865 offset = entry[1].offset;
6866 for (; entry->mode != VOIDmode; entry--)
6867 if (entry->reg == pr_reg)
6870 /* We can't find pr register. */
6874 offset = entry->offset - offset;
6875 pr_offset = (rounded_frame_size (d) + offset
6876 + SHMEDIA_REGS_STACK_ADJUST ());
6879 pr_offset = rounded_frame_size (d);
6881 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
6882 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
6884 tmp = gen_frame_mem (Pmode, tmp);
6885 emit_insn (GEN_MOV (tmp, ra));
6888 /* Clear variables at function end. */
6891 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6892 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6894 sh_need_epilogue_known = 0;
6898 sh_builtin_saveregs (void)
6900 /* First unnamed integer register. */
6901 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
6902 /* Number of integer registers we need to save. */
6903 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
6904 /* First unnamed SFmode float reg */
6905 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
6906 /* Number of SFmode float regs to save. */
6907 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
6910 HOST_WIDE_INT alias_set;
6916 int pushregs = n_intregs;
6918 while (pushregs < NPARM_REGS (SImode) - 1
6919 && (CALL_COOKIE_INT_REG_GET
6920 (current_function_args_info.call_cookie,
6921 NPARM_REGS (SImode) - pushregs)
6924 current_function_args_info.call_cookie
6925 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
6930 if (pushregs == NPARM_REGS (SImode))
6931 current_function_args_info.call_cookie
6932 |= (CALL_COOKIE_INT_REG (0, 1)
6933 | CALL_COOKIE_STACKSEQ (pushregs - 1));
6935 current_function_args_info.call_cookie
6936 |= CALL_COOKIE_STACKSEQ (pushregs);
6938 current_function_pretend_args_size += 8 * n_intregs;
6940 if (TARGET_SHCOMPACT)
6944 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
6946 error ("__builtin_saveregs not supported by this subtarget");
6953 /* Allocate block of memory for the regs. */
6954 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
6955 Or can assign_stack_local accept a 0 SIZE argument? */
6956 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
6959 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
6960 else if (n_floatregs & 1)
6964 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6965 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
6966 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
6967 regbuf = change_address (regbuf, BLKmode, addr);
6969 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
6973 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
6974 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
6975 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
6976 emit_insn (gen_andsi3 (addr, addr, mask));
6977 regbuf = change_address (regbuf, BLKmode, addr);
6980 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
6981 alias_set = get_varargs_alias_set ();
6982 set_mem_alias_set (regbuf, alias_set);
6985 This is optimized to only save the regs that are necessary. Explicitly
6986 named args need not be saved. */
6988 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
6989 adjust_address (regbuf, BLKmode,
6990 n_floatregs * UNITS_PER_WORD),
6994 /* Return the address of the regbuf. */
6995 return XEXP (regbuf, 0);
6998 This is optimized to only save the regs that are necessary. Explicitly
6999 named args need not be saved.
7000 We explicitly build a pointer to the buffer because it halves the insn
7001 count when not optimizing (otherwise the pointer is built for each reg
7003 We emit the moves in reverse order so that we can use predecrement. */
7005 fpregs = copy_to_mode_reg (Pmode,
7006 plus_constant (XEXP (regbuf, 0),
7007 n_floatregs * UNITS_PER_WORD));
7008 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7011 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7013 emit_insn (gen_addsi3 (fpregs, fpregs,
7014 GEN_INT (-2 * UNITS_PER_WORD)));
7015 mem = change_address (regbuf, DFmode, fpregs);
7016 emit_move_insn (mem,
7017 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7019 regno = first_floatreg;
7022 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7023 mem = change_address (regbuf, SFmode, fpregs);
7024 emit_move_insn (mem,
7025 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7026 - (TARGET_LITTLE_ENDIAN != 0)));
7030 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7034 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7035 mem = change_address (regbuf, SFmode, fpregs);
7036 emit_move_insn (mem,
7037 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7040 /* Return the address of the regbuf. */
7041 return XEXP (regbuf, 0);
7044 /* Define the `__builtin_va_list' type for the ABI. */
7047 sh_build_builtin_va_list (void)
7049 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7052 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7053 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7054 return ptr_type_node;
7056 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7058 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
7060 f_next_o_limit = build_decl (FIELD_DECL,
7061 get_identifier ("__va_next_o_limit"),
7063 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
7065 f_next_fp_limit = build_decl (FIELD_DECL,
7066 get_identifier ("__va_next_fp_limit"),
7068 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
7071 DECL_FIELD_CONTEXT (f_next_o) = record;
7072 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7073 DECL_FIELD_CONTEXT (f_next_fp) = record;
7074 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7075 DECL_FIELD_CONTEXT (f_next_stack) = record;
7077 TYPE_FIELDS (record) = f_next_o;
7078 TREE_CHAIN (f_next_o) = f_next_o_limit;
7079 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7080 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7081 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7083 layout_type (record);
7088 /* Implement `va_start' for varargs and stdarg. */
7091 sh_va_start (tree valist, rtx nextarg)
7093 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7094 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7100 expand_builtin_saveregs ();
7101 std_expand_builtin_va_start (valist, nextarg);
7105 if ((! TARGET_SH2E && ! TARGET_SH4)
7106 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7108 std_expand_builtin_va_start (valist, nextarg);
7112 f_next_o = TYPE_FIELDS (va_list_type_node);
7113 f_next_o_limit = TREE_CHAIN (f_next_o);
7114 f_next_fp = TREE_CHAIN (f_next_o_limit);
7115 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7116 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7118 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7120 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7121 valist, f_next_o_limit, NULL_TREE);
7122 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7124 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7125 valist, f_next_fp_limit, NULL_TREE);
7126 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7127 valist, f_next_stack, NULL_TREE);
7129 /* Call __builtin_saveregs. */
7130 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
7131 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp, u);
7132 TREE_SIDE_EFFECTS (t) = 1;
7133 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7135 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
7140 u = fold_build2 (PLUS_EXPR, ptr_type_node, u,
7141 build_int_cst (NULL_TREE, UNITS_PER_WORD * nfp));
7142 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_limit, u);
7143 TREE_SIDE_EFFECTS (t) = 1;
7144 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7146 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o, u);
7147 TREE_SIDE_EFFECTS (t) = 1;
7148 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7150 nint = current_function_args_info.arg_count[SH_ARG_INT];
7155 u = fold_build2 (PLUS_EXPR, ptr_type_node, u,
7156 build_int_cst (NULL_TREE, UNITS_PER_WORD * nint));
7157 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_o_limit, u);
7158 TREE_SIDE_EFFECTS (t) = 1;
7159 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7161 u = make_tree (ptr_type_node, nextarg);
7162 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_stack, u);
7163 TREE_SIDE_EFFECTS (t) = 1;
7164 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7167 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7168 member, return it. */
7170 find_sole_member (tree type)
7172 tree field, member = NULL_TREE;
7174 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7176 if (TREE_CODE (field) != FIELD_DECL)
7178 if (!DECL_SIZE (field))
7180 if (integer_zerop (DECL_SIZE (field)))
7188 /* Implement `va_arg'. */
7191 sh_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
7192 tree *post_p ATTRIBUTE_UNUSED)
7194 HOST_WIDE_INT size, rsize;
7195 tree tmp, pptr_type_node;
7196 tree addr, lab_over = NULL, result = NULL;
7197 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7201 type = build_pointer_type (type);
7203 size = int_size_in_bytes (type);
7204 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7205 pptr_type_node = build_pointer_type (ptr_type_node);
7207 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7208 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7210 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7211 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7216 f_next_o = TYPE_FIELDS (va_list_type_node);
7217 f_next_o_limit = TREE_CHAIN (f_next_o);
7218 f_next_fp = TREE_CHAIN (f_next_o_limit);
7219 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7220 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7222 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7224 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7225 valist, f_next_o_limit, NULL_TREE);
7226 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7227 valist, f_next_fp, NULL_TREE);
7228 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7229 valist, f_next_fp_limit, NULL_TREE);
7230 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7231 valist, f_next_stack, NULL_TREE);
7233 /* Structures with a single member with a distinct mode are passed
7234 like their member. This is relevant if the latter has a REAL_TYPE
7235 or COMPLEX_TYPE type. */
7237 while (TREE_CODE (eff_type) == RECORD_TYPE
7238 && (member = find_sole_member (eff_type))
7239 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7240 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7241 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7243 tree field_type = TREE_TYPE (member);
7245 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7246 eff_type = field_type;
7249 gcc_assert ((TYPE_ALIGN (eff_type)
7250 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7251 || (TYPE_ALIGN (eff_type)
7252 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7259 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7260 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7261 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7266 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7269 addr = create_tmp_var (pptr_type_node, NULL);
7270 lab_false = create_artificial_label ();
7271 lab_over = create_artificial_label ();
7273 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7277 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7279 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7281 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
7282 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7283 gimplify_and_add (tmp, pre_p);
7285 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7286 gimplify_and_add (tmp, pre_p);
7287 tmp = next_fp_limit;
7288 if (size > 4 && !is_double)
7289 tmp = build2 (PLUS_EXPR, TREE_TYPE (tmp), tmp,
7290 fold_convert (TREE_TYPE (tmp), size_int (4 - size)));
7291 tmp = build2 (GE_EXPR, boolean_type_node, next_fp_tmp, tmp);
7292 cmp = build3 (COND_EXPR, void_type_node, tmp,
7293 build1 (GOTO_EXPR, void_type_node, lab_false),
7296 gimplify_and_add (cmp, pre_p);
7298 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7299 || (is_double || size == 16))
7301 tmp = fold_convert (ptr_type_node, size_int (UNITS_PER_WORD));
7302 tmp = build2 (BIT_AND_EXPR, ptr_type_node, next_fp_tmp, tmp);
7303 tmp = build2 (PLUS_EXPR, ptr_type_node, next_fp_tmp, tmp);
7304 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7306 gimplify_and_add (tmp, pre_p);
7309 gimplify_and_add (cmp, pre_p);
7311 #ifdef FUNCTION_ARG_SCmode_WART
7312 if (TYPE_MODE (eff_type) == SCmode
7313 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7315 tree subtype = TREE_TYPE (eff_type);
7319 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7320 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7323 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7324 real = get_initialized_tmp_var (real, pre_p, NULL);
7326 result = build2 (COMPLEX_EXPR, type, real, imag);
7327 result = get_initialized_tmp_var (result, pre_p, NULL);
7329 #endif /* FUNCTION_ARG_SCmode_WART */
7331 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7332 gimplify_and_add (tmp, pre_p);
7334 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7335 gimplify_and_add (tmp, pre_p);
7337 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7338 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7339 gimplify_and_add (tmp, pre_p);
7340 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, next_fp_tmp, valist);
7341 gimplify_and_add (tmp, pre_p);
7343 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, valist, next_fp_tmp);
7344 gimplify_and_add (tmp, post_p);
7345 valist = next_fp_tmp;
7349 tmp = fold_convert (ptr_type_node, size_int (rsize));
7350 tmp = build2 (PLUS_EXPR, ptr_type_node, next_o, tmp);
7351 tmp = build2 (GT_EXPR, boolean_type_node, tmp, next_o_limit);
7352 tmp = build3 (COND_EXPR, void_type_node, tmp,
7353 build1 (GOTO_EXPR, void_type_node, lab_false),
7355 gimplify_and_add (tmp, pre_p);
7357 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
7358 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7359 gimplify_and_add (tmp, pre_p);
7361 tmp = build1 (GOTO_EXPR, void_type_node, lab_over);
7362 gimplify_and_add (tmp, pre_p);
7364 tmp = build1 (LABEL_EXPR, void_type_node, lab_false);
7365 gimplify_and_add (tmp, pre_p);
7367 if (size > 4 && ! TARGET_SH4)
7369 tmp = build2 (GIMPLE_MODIFY_STMT, ptr_type_node,
7370 next_o, next_o_limit);
7371 gimplify_and_add (tmp, pre_p);
7374 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
7375 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, tmp);
7376 gimplify_and_add (tmp, pre_p);
7381 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7382 gimplify_and_add (tmp, pre_p);
7386 /* ??? In va-sh.h, there had been code to make values larger than
7387 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7389 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7392 tmp = build2 (GIMPLE_MODIFY_STMT, void_type_node, result, tmp);
7393 gimplify_and_add (tmp, pre_p);
7395 tmp = build1 (LABEL_EXPR, void_type_node, lab_over);
7396 gimplify_and_add (tmp, pre_p);
7402 result = build_va_arg_indirect_ref (result);
7408 sh_promote_prototypes (tree type)
7414 return ! sh_attr_renesas_p (type);
7417 /* Whether an argument must be passed by reference. On SHcompact, we
7418 pretend arguments wider than 32-bits that would have been passed in
7419 registers are passed by reference, so that an SHmedia trampoline
7420 loads them into the full 64-bits registers. */
7423 shcompact_byref (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7424 tree type, bool named)
7426 unsigned HOST_WIDE_INT size;
7429 size = int_size_in_bytes (type);
7431 size = GET_MODE_SIZE (mode);
7433 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7435 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7436 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7437 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7439 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7440 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7447 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7448 tree type, bool named)
7450 if (targetm.calls.must_pass_in_stack (mode, type))
7453 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7454 wants to know about pass-by-reference semantics for incoming
7459 if (TARGET_SHCOMPACT)
7461 cum->byref = shcompact_byref (cum, mode, type, named);
7462 return cum->byref != 0;
7469 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7470 tree type, bool named ATTRIBUTE_UNUSED)
7472 /* ??? How can it possibly be correct to return true only on the
7473 caller side of the equation? Is there someplace else in the
7474 sh backend that's magically producing the copies? */
7475 return (cum->outgoing
7476 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7477 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7481 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7482 tree type, bool named ATTRIBUTE_UNUSED)
7487 && PASS_IN_REG_P (*cum, mode, type)
7488 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7489 && (ROUND_REG (*cum, mode)
7491 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7492 : ROUND_ADVANCE (int_size_in_bytes (type)))
7493 > NPARM_REGS (mode)))
7494 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7496 else if (!TARGET_SHCOMPACT
7497 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7498 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7500 return words * UNITS_PER_WORD;
7504 /* Define where to put the arguments to a function.
7505 Value is zero to push the argument on the stack,
7506 or a hard register in which to store the argument.
7508 MODE is the argument's machine mode.
7509 TYPE is the data type of the argument (as a tree).
7510 This is null for libcalls where that information may
7512 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7513 the preceding args and about the function being called.
7514 NAMED is nonzero if this argument is a named parameter
7515 (otherwise it is an extra parameter matching an ellipsis).
7517 On SH the first args are normally in registers
7518 and the rest are pushed. Any arg that starts within the first
7519 NPARM_REGS words is at least partially passed in a register unless
7520 its data type forbids. */
7524 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7525 tree type, int named)
7527 if (! TARGET_SH5 && mode == VOIDmode)
7528 return GEN_INT (ca->renesas_abi ? 1 : 0);
7531 && PASS_IN_REG_P (*ca, mode, type)
7532 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
7536 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
7537 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
7539 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
7540 gen_rtx_REG (SFmode,
7542 + (ROUND_REG (*ca, mode) ^ 1)),
7544 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
7545 gen_rtx_REG (SFmode,
7547 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
7549 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
7552 /* If the alignment of a DF value causes an SF register to be
7553 skipped, we will use that skipped register for the next SF
7555 if ((TARGET_HITACHI || ca->renesas_abi)
7556 && ca->free_single_fp_reg
7558 return gen_rtx_REG (mode, ca->free_single_fp_reg);
7560 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
7561 ^ (mode == SFmode && TARGET_SH4
7562 && TARGET_LITTLE_ENDIAN != 0
7563 && ! TARGET_HITACHI && ! ca->renesas_abi);
7564 return gen_rtx_REG (mode, regno);
7570 if (mode == VOIDmode && TARGET_SHCOMPACT)
7571 return GEN_INT (ca->call_cookie);
7573 /* The following test assumes unnamed arguments are promoted to
7575 if (mode == SFmode && ca->free_single_fp_reg)
7576 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
7578 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
7579 && (named || ! ca->prototype_p)
7580 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
7582 if (! ca->prototype_p && TARGET_SHMEDIA)
7583 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
7585 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
7587 + ca->arg_count[(int) SH_ARG_FLOAT]);
7590 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
7591 && (! TARGET_SHCOMPACT
7592 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
7593 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
7596 return gen_rtx_REG (mode, (FIRST_PARM_REG
7597 + ca->arg_count[(int) SH_ARG_INT]));
7606 /* Update the data in CUM to advance over an argument
7607 of mode MODE and data type TYPE.
7608 (TYPE is null for libcalls where that information may not be
7612 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
7613 tree type, int named)
7617 else if (TARGET_SH5)
7619 tree type2 = (ca->byref && type
7622 enum machine_mode mode2 = (ca->byref && type
7625 int dwords = ((ca->byref
7628 ? int_size_in_bytes (type2)
7629 : GET_MODE_SIZE (mode2)) + 7) / 8;
7630 int numregs = MIN (dwords, NPARM_REGS (SImode)
7631 - ca->arg_count[(int) SH_ARG_INT]);
7635 ca->arg_count[(int) SH_ARG_INT] += numregs;
7636 if (TARGET_SHCOMPACT
7637 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
7640 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7642 /* N.B. We want this also for outgoing. */
7643 ca->stack_regs += numregs;
7648 ca->stack_regs += numregs;
7649 ca->byref_regs += numregs;
7653 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7657 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
7660 else if (dwords > numregs)
7662 int pushregs = numregs;
7664 if (TARGET_SHCOMPACT)
7665 ca->stack_regs += numregs;
7666 while (pushregs < NPARM_REGS (SImode) - 1
7667 && (CALL_COOKIE_INT_REG_GET
7669 NPARM_REGS (SImode) - pushregs)
7673 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7677 if (numregs == NPARM_REGS (SImode))
7679 |= CALL_COOKIE_INT_REG (0, 1)
7680 | CALL_COOKIE_STACKSEQ (numregs - 1);
7683 |= CALL_COOKIE_STACKSEQ (numregs);
7686 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
7687 && (named || ! ca->prototype_p))
7689 if (mode2 == SFmode && ca->free_single_fp_reg)
7690 ca->free_single_fp_reg = 0;
7691 else if (ca->arg_count[(int) SH_ARG_FLOAT]
7692 < NPARM_REGS (SFmode))
7695 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
7697 - ca->arg_count[(int) SH_ARG_FLOAT]);
7699 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
7701 if (TARGET_SHCOMPACT && ! ca->prototype_p)
7703 if (ca->outgoing && numregs > 0)
7707 |= (CALL_COOKIE_INT_REG
7708 (ca->arg_count[(int) SH_ARG_INT]
7709 - numregs + ((numfpregs - 2) / 2),
7710 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
7713 while (numfpregs -= 2);
7715 else if (mode2 == SFmode && (named)
7716 && (ca->arg_count[(int) SH_ARG_FLOAT]
7717 < NPARM_REGS (SFmode)))
7718 ca->free_single_fp_reg
7719 = FIRST_FP_PARM_REG - numfpregs
7720 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
7726 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
7728 /* Note that we've used the skipped register. */
7729 if (mode == SFmode && ca->free_single_fp_reg)
7731 ca->free_single_fp_reg = 0;
7734 /* When we have a DF after an SF, there's an SF register that get
7735 skipped in order to align the DF value. We note this skipped
7736 register, because the next SF value will use it, and not the
7737 SF that follows the DF. */
7739 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
7741 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
7742 + BASE_ARG_REG (mode));
7746 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
7747 || PASS_IN_REG_P (*ca, mode, type))
7748 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
7749 = (ROUND_REG (*ca, mode)
7751 ? ROUND_ADVANCE (int_size_in_bytes (type))
7752 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
7755 /* The Renesas calling convention doesn't quite fit into this scheme since
7756 the address is passed like an invisible argument, but one that is always
7757 passed in memory. */
7759 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
7761 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7763 return gen_rtx_REG (Pmode, 2);
7766 /* Worker function for TARGET_RETURN_IN_MEMORY. */
7769 sh_return_in_memory (tree type, tree fndecl)
7773 if (TYPE_MODE (type) == BLKmode)
7774 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
7776 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
7780 return (TYPE_MODE (type) == BLKmode
7781 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
7782 && TREE_CODE (type) == RECORD_TYPE));
7786 /* We actually emit the code in sh_expand_prologue. We used to use
7787 a static variable to flag that we need to emit this code, but that
7788 doesn't when inlining, when functions are deferred and then emitted
7789 later. Fortunately, we already have two flags that are part of struct
7790 function that tell if a function uses varargs or stdarg. */
7792 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
7793 enum machine_mode mode,
7795 int *pretend_arg_size,
7796 int second_time ATTRIBUTE_UNUSED)
7798 gcc_assert (current_function_stdarg);
7799 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7801 int named_parm_regs, anon_parm_regs;
7803 named_parm_regs = (ROUND_REG (*ca, mode)
7805 ? ROUND_ADVANCE (int_size_in_bytes (type))
7806 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
7807 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
7808 if (anon_parm_regs > 0)
7809 *pretend_arg_size = anon_parm_regs * 4;
7814 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
7820 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
7822 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
7826 /* Define the offset between two registers, one to be eliminated, and
7827 the other its replacement, at the start of a routine. */
7830 initial_elimination_offset (int from, int to)
7833 int regs_saved_rounding = 0;
7834 int total_saved_regs_space;
7835 int total_auto_space;
7836 int save_flags = target_flags;
7838 HARD_REG_SET live_regs_mask;
7840 shmedia_space_reserved_for_target_registers = false;
7841 regs_saved = calc_live_regs (&live_regs_mask);
7842 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
7844 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
7846 shmedia_space_reserved_for_target_registers = true;
7847 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
7850 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
7851 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7852 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
7854 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
7855 copy_flags = target_flags;
7856 target_flags = save_flags;
7858 total_saved_regs_space = regs_saved + regs_saved_rounding;
7860 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7861 return total_saved_regs_space + total_auto_space
7862 + current_function_args_info.byref_regs * 8;
7864 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7865 return total_saved_regs_space + total_auto_space
7866 + current_function_args_info.byref_regs * 8;
7868 /* Initial gap between fp and sp is 0. */
7869 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7872 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
7873 return rounded_frame_size (0);
7875 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7876 return rounded_frame_size (0);
7878 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
7879 && (to == HARD_FRAME_POINTER_REGNUM
7880 || to == STACK_POINTER_REGNUM));
7883 int n = total_saved_regs_space;
7884 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7885 save_schedule schedule;
7888 n += total_auto_space;
7890 /* If it wasn't saved, there's not much we can do. */
7891 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7894 target_flags = copy_flags;
7896 sh5_schedule_saves (&live_regs_mask, &schedule, n);
7897 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7898 if (entry->reg == pr_reg)
7900 target_flags = save_flags;
7901 return entry->offset;
7906 return total_auto_space;
7909 /* Insert any deferred function attributes from earlier pragmas. */
7911 sh_insert_attributes (tree node, tree *attributes)
7915 if (TREE_CODE (node) != FUNCTION_DECL)
7918 /* We are only interested in fields. */
7922 /* Append the attributes to the deferred attributes. */
7923 *sh_deferred_function_attributes_tail = *attributes;
7924 attrs = sh_deferred_function_attributes;
7928 /* Some attributes imply or require the interrupt attribute. */
7929 if (!lookup_attribute ("interrupt_handler", attrs)
7930 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
7932 /* If we have a trapa_handler, but no interrupt_handler attribute,
7933 insert an interrupt_handler attribute. */
7934 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
7935 /* We can't use sh_pr_interrupt here because that's not in the
7938 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
7939 /* However, for sp_switch, trap_exit and nosave_low_regs, if the
7940 interrupt attribute is missing, we ignore the attribute and warn. */
7941 else if (lookup_attribute ("sp_switch", attrs)
7942 || lookup_attribute ("trap_exit", attrs)
7943 || lookup_attribute ("nosave_low_regs", attrs))
7947 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
7949 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
7950 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
7951 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs)))
7952 warning (OPT_Wattributes,
7953 "%qs attribute only applies to interrupt functions",
7954 IDENTIFIER_POINTER (TREE_PURPOSE (attrs)));
7957 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
7959 tail = &TREE_CHAIN (*tail);
7962 attrs = *attributes;
7966 /* Install the processed list. */
7967 *attributes = attrs;
7969 /* Clear deferred attributes. */
7970 sh_deferred_function_attributes = NULL_TREE;
7971 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
7976 /* Supported attributes:
7978 interrupt_handler -- specifies this function is an interrupt handler.
7980 trapa_handler - like above, but don't save all registers.
7982 sp_switch -- specifies an alternate stack for an interrupt handler
7985 trap_exit -- use a trapa to exit an interrupt function instead of
7988 nosave_low_regs - don't save r0..r7 in an interrupt handler.
7989 This is useful on the SH3 and upwards,
7990 which has a separate set of low regs for User and Supervisor modes.
7991 This should only be used for the lowest level of interrupts. Higher levels
7992 of interrupts must save the registers in case they themselves are
7995 renesas -- use Renesas calling/layout conventions (functions and
8000 const struct attribute_spec sh_attribute_table[] =
8002 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8003 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8004 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
8005 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
8006 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
8007 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8008 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
8010 /* Symbian support adds three new attributes:
8011 dllexport - for exporting a function/variable that will live in a dll
8012 dllimport - for importing a function/variable from a dll
8014 Microsoft allows multiple declspecs in one __declspec, separating
8015 them with spaces. We do NOT support this. Instead, use __declspec
8017 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8018 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
8020 { NULL, 0, 0, false, false, false, NULL }
8023 /* Handle an "interrupt_handler" attribute; arguments as in
8024 struct attribute_spec.handler. */
8026 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8027 tree args ATTRIBUTE_UNUSED,
8028 int flags ATTRIBUTE_UNUSED,
8031 if (TREE_CODE (*node) != FUNCTION_DECL)
8033 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8034 IDENTIFIER_POINTER (name));
8035 *no_add_attrs = true;
8037 else if (TARGET_SHCOMPACT)
8039 error ("attribute interrupt_handler is not compatible with -m5-compact");
8040 *no_add_attrs = true;
8046 /* Handle an "sp_switch" attribute; arguments as in
8047 struct attribute_spec.handler. */
8049 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8050 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8052 if (TREE_CODE (*node) != FUNCTION_DECL)
8054 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8055 IDENTIFIER_POINTER (name));
8056 *no_add_attrs = true;
8058 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8060 /* The argument must be a constant string. */
8061 warning (OPT_Wattributes, "%qs attribute argument not a string constant",
8062 IDENTIFIER_POINTER (name));
8063 *no_add_attrs = true;
8069 /* Handle an "trap_exit" attribute; arguments as in
8070 struct attribute_spec.handler. */
8072 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8073 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8075 if (TREE_CODE (*node) != FUNCTION_DECL)
8077 warning (OPT_Wattributes, "%qs attribute only applies to functions",
8078 IDENTIFIER_POINTER (name));
8079 *no_add_attrs = true;
8081 /* The argument specifies a trap number to be used in a trapa instruction
8082 at function exit (instead of an rte instruction). */
8083 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8085 /* The argument must be a constant integer. */
8086 warning (OPT_Wattributes, "%qs attribute argument not an "
8087 "integer constant", IDENTIFIER_POINTER (name));
8088 *no_add_attrs = true;
8095 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8096 tree name ATTRIBUTE_UNUSED,
8097 tree args ATTRIBUTE_UNUSED,
8098 int flags ATTRIBUTE_UNUSED,
8099 bool *no_add_attrs ATTRIBUTE_UNUSED)
8104 /* True if __attribute__((renesas)) or -mrenesas. */
8106 sh_attr_renesas_p (tree td)
8113 td = TREE_TYPE (td);
8114 if (td == error_mark_node)
8116 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8120 /* True if __attribute__((renesas)) or -mrenesas, for the current
8123 sh_cfun_attr_renesas_p (void)
8125 return sh_attr_renesas_p (current_function_decl);
8129 sh_cfun_interrupt_handler_p (void)
8131 return (lookup_attribute ("interrupt_handler",
8132 DECL_ATTRIBUTES (current_function_decl))
8136 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8139 sh_check_pch_target_flags (int old_flags)
8141 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8142 | MASK_SH_E | MASK_HARD_SH4
8143 | MASK_FPU_SINGLE | MASK_SH4))
8144 return _("created and used with different architectures / ABIs");
8145 if ((old_flags ^ target_flags) & MASK_HITACHI)
8146 return _("created and used with different ABIs");
8147 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8148 return _("created and used with different endianness");
8152 /* Predicates used by the templates. */
8154 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8155 Used only in general_movsrc_operand. */
8158 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8170 /* Nonzero if OP is a floating point value with value 0.0. */
8173 fp_zero_operand (rtx op)
8177 if (GET_MODE (op) != SFmode)
8180 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8181 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8184 /* Nonzero if OP is a floating point value with value 1.0. */
8187 fp_one_operand (rtx op)
8191 if (GET_MODE (op) != SFmode)
8194 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8195 return REAL_VALUES_EQUAL (r, dconst1);
8198 /* For -m4 and -m4-single-only, mode switching is used. If we are
8199 compiling without -mfmovd, movsf_ie isn't taken into account for
8200 mode switching. We could check in machine_dependent_reorg for
8201 cases where we know we are in single precision mode, but there is
8202 interface to find that out during reload, so we must avoid
8203 choosing an fldi alternative during reload and thus failing to
8204 allocate a scratch register for the constant loading. */
8208 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8212 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8214 enum rtx_code code = GET_CODE (op);
8215 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8218 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8220 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8222 if (GET_CODE (op) != SYMBOL_REF)
8224 return SYMBOL_REF_TLS_MODEL (op);
8227 /* Return the destination address of a branch. */
8230 branch_dest (rtx branch)
8232 rtx dest = SET_SRC (PATTERN (branch));
8235 if (GET_CODE (dest) == IF_THEN_ELSE)
8236 dest = XEXP (dest, 1);
8237 dest = XEXP (dest, 0);
8238 dest_uid = INSN_UID (dest);
8239 return INSN_ADDRESSES (dest_uid);
8242 /* Return nonzero if REG is not used after INSN.
8243 We assume REG is a reload reg, and therefore does
8244 not live past labels. It may live past calls or jumps though. */
8246 reg_unused_after (rtx reg, rtx insn)
8251 /* If the reg is set by this instruction, then it is safe for our
8252 case. Disregard the case where this is a store to memory, since
8253 we are checking a register used in the store address. */
8254 set = single_set (insn);
8255 if (set && GET_CODE (SET_DEST (set)) != MEM
8256 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8259 while ((insn = NEXT_INSN (insn)))
8265 code = GET_CODE (insn);
8268 /* If this is a label that existed before reload, then the register
8269 if dead here. However, if this is a label added by reorg, then
8270 the register may still be live here. We can't tell the difference,
8271 so we just ignore labels completely. */
8272 if (code == CODE_LABEL)
8277 if (code == JUMP_INSN)
8280 /* If this is a sequence, we must handle them all at once.
8281 We could have for instance a call that sets the target register,
8282 and an insn in a delay slot that uses the register. In this case,
8283 we must return 0. */
8284 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8289 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8291 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8292 rtx set = single_set (this_insn);
8294 if (GET_CODE (this_insn) == CALL_INSN)
8296 else if (GET_CODE (this_insn) == JUMP_INSN)
8298 if (INSN_ANNULLED_BRANCH_P (this_insn))
8303 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8305 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8307 if (GET_CODE (SET_DEST (set)) != MEM)
8313 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8318 else if (code == JUMP_INSN)
8322 set = single_set (insn);
8323 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8325 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8326 return GET_CODE (SET_DEST (set)) != MEM;
8327 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8330 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8338 static GTY(()) rtx fpscr_rtx;
8340 get_fpscr_rtx (void)
8344 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
8345 REG_USERVAR_P (fpscr_rtx) = 1;
8346 mark_user_reg (fpscr_rtx);
8348 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
8349 mark_user_reg (fpscr_rtx);
8353 static GTY(()) tree fpscr_values;
8356 emit_fpu_switch (rtx scratch, int index)
8360 if (fpscr_values == NULL)
8364 t = build_index_type (integer_one_node);
8365 t = build_array_type (integer_type_node, t);
8366 t = build_decl (VAR_DECL, get_identifier ("__fpscr_values"), t);
8367 DECL_ARTIFICIAL (t) = 1;
8368 DECL_IGNORED_P (t) = 1;
8369 DECL_EXTERNAL (t) = 1;
8370 TREE_STATIC (t) = 1;
8371 TREE_PUBLIC (t) = 1;
8377 src = DECL_RTL (fpscr_values);
8380 emit_move_insn (scratch, XEXP (src, 0));
8382 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8383 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
8386 src = adjust_address (src, PSImode, index * 4);
8388 dst = get_fpscr_rtx ();
8389 emit_move_insn (dst, src);
8393 emit_sf_insn (rtx pat)
8399 emit_df_insn (rtx pat)
8405 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8407 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8411 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8413 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
8418 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
8420 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
8424 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
8426 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
8430 /* ??? gcc does flow analysis strictly after common subexpression
8431 elimination. As a result, common subexpression elimination fails
8432 when there are some intervening statements setting the same register.
8433 If we did nothing about this, this would hurt the precision switching
8434 for SH4 badly. There is some cse after reload, but it is unable to
8435 undo the extra register pressure from the unused instructions, and
8436 it cannot remove auto-increment loads.
8438 A C code example that shows this flow/cse weakness for (at least) SH
8439 and sparc (as of gcc ss-970706) is this:
8453 So we add another pass before common subexpression elimination, to
8454 remove assignments that are dead due to a following assignment in the
8455 same basic block. */
8458 mark_use (rtx x, rtx *reg_set_block)
8464 code = GET_CODE (x);
8469 int regno = REGNO (x);
8470 int nregs = (regno < FIRST_PSEUDO_REGISTER
8471 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
8475 reg_set_block[regno + nregs - 1] = 0;
8482 rtx dest = SET_DEST (x);
8484 if (GET_CODE (dest) == SUBREG)
8485 dest = SUBREG_REG (dest);
8486 if (GET_CODE (dest) != REG)
8487 mark_use (dest, reg_set_block);
8488 mark_use (SET_SRC (x), reg_set_block);
8495 const char *fmt = GET_RTX_FORMAT (code);
8497 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8500 mark_use (XEXP (x, i), reg_set_block);
8501 else if (fmt[i] == 'E')
8502 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8503 mark_use (XVECEXP (x, i, j), reg_set_block);
8510 static rtx get_free_reg (HARD_REG_SET);
8512 /* This function returns a register to use to load the address to load
8513 the fpscr from. Currently it always returns r1 or r7, but when we are
8514 able to use pseudo registers after combine, or have a better mechanism
8515 for choosing a register, it should be done here. */
8516 /* REGS_LIVE is the liveness information for the point for which we
8517 need this allocation. In some bare-bones exit blocks, r1 is live at the
8518 start. We can even have all of r0..r3 being live:
8519 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8520 INSN before which new insns are placed with will clobber the register
8521 we return. If a basic block consists only of setting the return value
8522 register to a pseudo and using that register, the return value is not
8523 live before or after this block, yet we we'll insert our insns right in
8527 get_free_reg (HARD_REG_SET regs_live)
8529 if (! TEST_HARD_REG_BIT (regs_live, 1))
8530 return gen_rtx_REG (Pmode, 1);
8532 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
8533 there shouldn't be anything but a jump before the function end. */
8534 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8535 return gen_rtx_REG (Pmode, 7);
8538 /* This function will set the fpscr from memory.
8539 MODE is the mode we are setting it to. */
8541 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8543 enum attr_fp_mode fp_mode = mode;
8544 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8545 rtx addr_reg = get_free_reg (regs_live);
8547 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8550 /* Is the given character a logical line separator for the assembler? */
8551 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8552 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
8556 sh_insn_length_adjustment (rtx insn)
8558 /* Instructions with unfilled delay slots take up an extra two bytes for
8559 the nop in the delay slot. */
8560 if (((GET_CODE (insn) == INSN
8561 && GET_CODE (PATTERN (insn)) != USE
8562 && GET_CODE (PATTERN (insn)) != CLOBBER)
8563 || GET_CODE (insn) == CALL_INSN
8564 || (GET_CODE (insn) == JUMP_INSN
8565 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8566 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
8567 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
8568 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8571 /* SH2e has a bug that prevents the use of annulled branches, so if
8572 the delay slot is not filled, we'll have to put a NOP in it. */
8573 if (sh_cpu == CPU_SH2E
8574 && GET_CODE (insn) == JUMP_INSN
8575 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
8576 && GET_CODE (PATTERN (insn)) != ADDR_VEC
8577 && get_attr_type (insn) == TYPE_CBRANCH
8578 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
8581 /* sh-dsp parallel processing insn take four bytes instead of two. */
8583 if (GET_CODE (insn) == INSN)
8586 rtx body = PATTERN (insn);
8587 const char *template;
8589 int maybe_label = 1;
8591 if (GET_CODE (body) == ASM_INPUT)
8592 template = XSTR (body, 0);
8593 else if (asm_noperands (body) >= 0)
8595 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8604 while (c == ' ' || c == '\t');
8605 /* all sh-dsp parallel-processing insns start with p.
8606 The only non-ppi sh insn starting with p is pref.
8607 The only ppi starting with pr is prnd. */
8608 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
8610 /* The repeat pseudo-insn expands two three insns, a total of
8611 six bytes in size. */
8612 else if ((c == 'r' || c == 'R')
8613 && ! strncasecmp ("epeat", template, 5))
8615 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
8617 /* If this is a label, it is obviously not a ppi insn. */
8618 if (c == ':' && maybe_label)
8623 else if (c == '\'' || c == '"')
8628 maybe_label = c != ':';
8636 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8637 isn't protected by a PIC unspec. */
8639 nonpic_symbol_mentioned_p (rtx x)
8641 register const char *fmt;
8644 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
8645 || GET_CODE (x) == PC)
8648 /* We don't want to look into the possible MEM location of a
8649 CONST_DOUBLE, since we're not going to use it, in general. */
8650 if (GET_CODE (x) == CONST_DOUBLE)
8653 if (GET_CODE (x) == UNSPEC
8654 && (XINT (x, 1) == UNSPEC_PIC
8655 || XINT (x, 1) == UNSPEC_GOT
8656 || XINT (x, 1) == UNSPEC_GOTOFF
8657 || XINT (x, 1) == UNSPEC_GOTPLT
8658 || XINT (x, 1) == UNSPEC_GOTTPOFF
8659 || XINT (x, 1) == UNSPEC_DTPOFF
8660 || XINT (x, 1) == UNSPEC_PLT))
8663 fmt = GET_RTX_FORMAT (GET_CODE (x));
8664 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8670 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8671 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
8674 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
8681 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8682 @GOTOFF in `reg'. */
8684 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
8687 if (tls_symbolic_operand (orig, Pmode))
8690 if (GET_CODE (orig) == LABEL_REF
8691 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
8694 reg = gen_reg_rtx (Pmode);
8696 emit_insn (gen_symGOTOFF2reg (reg, orig));
8699 else if (GET_CODE (orig) == SYMBOL_REF)
8702 reg = gen_reg_rtx (Pmode);
8704 emit_insn (gen_symGOT2reg (reg, orig));
8710 /* Mark the use of a constant in the literal table. If the constant
8711 has multiple labels, make it unique. */
8713 mark_constant_pool_use (rtx x)
8715 rtx insn, lab, pattern;
8720 switch (GET_CODE (x))
8730 /* Get the first label in the list of labels for the same constant
8731 and delete another labels in the list. */
8733 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
8735 if (GET_CODE (insn) != CODE_LABEL
8736 || LABEL_REFS (insn) != NEXT_INSN (insn))
8741 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
8742 INSN_DELETED_P (insn) = 1;
8744 /* Mark constants in a window. */
8745 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
8747 if (GET_CODE (insn) != INSN)
8750 pattern = PATTERN (insn);
8751 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
8754 switch (XINT (pattern, 1))
8756 case UNSPECV_CONST2:
8757 case UNSPECV_CONST4:
8758 case UNSPECV_CONST8:
8759 XVECEXP (pattern, 0, 1) = const1_rtx;
8761 case UNSPECV_WINDOW_END:
8762 if (XVECEXP (pattern, 0, 0) == x)
8765 case UNSPECV_CONST_END:
8775 /* Return true if it's possible to redirect BRANCH1 to the destination
8776 of an unconditional jump BRANCH2. We only want to do this if the
8777 resulting branch will have a short displacement. */
8779 sh_can_redirect_branch (rtx branch1, rtx branch2)
8781 if (flag_expensive_optimizations && simplejump_p (branch2))
8783 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
8787 for (distance = 0, insn = NEXT_INSN (branch1);
8788 insn && distance < 256;
8789 insn = PREV_INSN (insn))
8794 distance += get_attr_length (insn);
8796 for (distance = 0, insn = NEXT_INSN (branch1);
8797 insn && distance < 256;
8798 insn = NEXT_INSN (insn))
8803 distance += get_attr_length (insn);
8809 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8811 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
8812 unsigned int new_reg)
8814 /* Interrupt functions can only use registers that have already been
8815 saved by the prologue, even if they would normally be
8818 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
8824 /* Function to update the integer COST
8825 based on the relationship between INSN that is dependent on
8826 DEP_INSN through the dependence LINK. The default is to make no
8827 adjustment to COST. This can be used for example to specify to
8828 the scheduler that an output- or anti-dependence does not incur
8829 the same cost as a data-dependence. The return value should be
8830 the new value for COST. */
8832 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
8838 /* On SHmedia, if the dependence is an anti-dependence or
8839 output-dependence, there is no cost. */
8840 if (REG_NOTE_KIND (link) != 0)
8842 /* However, dependencies between target register loads and
8843 uses of the register in a subsequent block that are separated
8844 by a conditional branch are not modelled - we have to do with
8845 the anti-dependency between the target register load and the
8846 conditional branch that ends the current block. */
8847 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
8848 && GET_CODE (PATTERN (dep_insn)) == SET
8849 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
8850 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
8851 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
8853 int orig_cost = cost;
8854 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
8855 rtx target = ((! note
8856 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
8857 ? insn : JUMP_LABEL (insn));
8858 /* On the likely path, the branch costs 1, on the unlikely path,
8862 target = next_active_insn (target);
8863 while (target && ! flow_dependent_p (target, dep_insn)
8865 /* If two branches are executed in immediate succession, with the
8866 first branch properly predicted, this causes a stall at the
8867 second branch, hence we won't need the target for the
8868 second branch for two cycles after the launch of the first
8870 if (cost > orig_cost - 2)
8871 cost = orig_cost - 2;
8877 else if (get_attr_is_mac_media (insn)
8878 && get_attr_is_mac_media (dep_insn))
8881 else if (! reload_completed
8882 && GET_CODE (PATTERN (insn)) == SET
8883 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
8884 && GET_CODE (PATTERN (dep_insn)) == SET
8885 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
8888 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
8889 that is needed at the target. */
8890 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
8891 && ! flow_dependent_p (insn, dep_insn))
8894 else if (REG_NOTE_KIND (link) == 0)
8896 enum attr_type type;
8899 if (recog_memoized (insn) < 0
8900 || recog_memoized (dep_insn) < 0)
8903 dep_set = single_set (dep_insn);
8905 /* The latency that we specify in the scheduling description refers
8906 to the actual output, not to an auto-increment register; for that,
8907 the latency is one. */
8908 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
8910 rtx set = single_set (insn);
8913 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
8914 && (!MEM_P (SET_DEST (set))
8915 || !reg_mentioned_p (SET_DEST (dep_set),
8916 XEXP (SET_DEST (set), 0))))
8919 /* The only input for a call that is timing-critical is the
8920 function's address. */
8921 if (GET_CODE (insn) == CALL_INSN)
8923 rtx call = PATTERN (insn);
8925 if (GET_CODE (call) == PARALLEL)
8926 call = XVECEXP (call, 0 ,0);
8927 if (GET_CODE (call) == SET)
8928 call = SET_SRC (call);
8929 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
8930 /* sibcalli_thunk uses a symbol_ref in an unspec. */
8931 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
8932 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
8933 cost -= TARGET_SH4_300 ? 3 : 6;
8935 /* Likewise, the most timing critical input for an sfuncs call
8936 is the function address. However, sfuncs typically start
8937 using their arguments pretty quickly.
8938 Assume a four cycle delay for SH4 before they are needed.
8939 Cached ST40-300 calls are quicker, so assume only a one
8941 ??? Maybe we should encode the delays till input registers
8942 are needed by sfuncs into the sfunc call insn. */
8943 /* All sfunc calls are parallels with at least four components.
8944 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8945 else if (GET_CODE (PATTERN (insn)) == PARALLEL
8946 && XVECLEN (PATTERN (insn), 0) >= 4
8947 && (reg = sfunc_uses_reg (insn)))
8949 if (! reg_set_p (reg, dep_insn))
8950 cost -= TARGET_SH4_300 ? 1 : 4;
8952 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
8954 enum attr_type dep_type = get_attr_type (dep_insn);
8956 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
8958 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
8959 && (type = get_attr_type (insn)) != TYPE_CALL
8960 && type != TYPE_SFUNC)
8962 /* When the preceding instruction loads the shift amount of
8963 the following SHAD/SHLD, the latency of the load is increased
8965 if (get_attr_type (insn) == TYPE_DYN_SHIFT
8966 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
8967 && reg_overlap_mentioned_p (SET_DEST (dep_set),
8968 XEXP (SET_SRC (single_set (insn)),
8971 /* When an LS group instruction with a latency of less than
8972 3 cycles is followed by a double-precision floating-point
8973 instruction, FIPR, or FTRV, the latency of the first
8974 instruction is increased to 3 cycles. */
8976 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
8977 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
8979 /* The lsw register of a double-precision computation is ready one
8981 else if (reload_completed
8982 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
8983 && (use_pat = single_set (insn))
8984 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
8988 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
8989 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
8992 else if (TARGET_SH4_300)
8994 /* Stores need their input register two cycles later. */
8995 if (dep_set && cost >= 1
8996 && ((type = get_attr_type (insn)) == TYPE_STORE
8997 || type == TYPE_PSTORE
8998 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9000 rtx set = single_set (insn);
9002 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9003 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9006 /* But don't reduce the cost below 1 if the address depends
9007 on a side effect of dep_insn. */
9009 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9015 /* An anti-dependence penalty of two applies if the first insn is a double
9016 precision fadd / fsub / fmul. */
9017 else if (!TARGET_SH4_300
9018 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9019 && recog_memoized (dep_insn) >= 0
9020 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9021 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9022 /* A lot of alleged anti-flow dependences are fake,
9023 so check this one is real. */
9024 && flow_dependent_p (dep_insn, insn))
9030 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9031 if DEP_INSN is anti-flow dependent on INSN. */
9033 flow_dependent_p (rtx insn, rtx dep_insn)
9035 rtx tmp = PATTERN (insn);
9037 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9038 return tmp == NULL_RTX;
9041 /* A helper function for flow_dependent_p called through note_stores. */
9043 flow_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9045 rtx * pinsn = (rtx *) data;
9047 if (*pinsn && reg_referenced_p (x, *pinsn))
9051 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9052 'special function' patterns (type sfunc) that clobber pr, but that
9053 do not look like function calls to leaf_function_p. Hence we must
9054 do this extra check. */
9058 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9061 /* Return where to allocate pseudo for a given hard register initial
9064 sh_allocate_initial_value (rtx hard_reg)
9068 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9070 if (current_function_is_leaf
9071 && ! sh_pr_n_sets ()
9072 && ! (TARGET_SHCOMPACT
9073 && ((current_function_args_info.call_cookie
9074 & ~ CALL_COOKIE_RET_TRAMP (1))
9075 || current_function_has_nonlocal_label)))
9078 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9086 /* This function returns "2" to indicate dual issue for the SH4
9087 processor. To be used by the DFA pipeline description. */
9089 sh_issue_rate (void)
9091 if (TARGET_SUPERSCALAR)
9097 /* Functions for ready queue reordering for sched1. */
9099 /* Get weight for mode for a set x. */
9101 find_set_regmode_weight (rtx x, enum machine_mode mode)
9103 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9105 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9107 if (GET_CODE (SET_DEST (x)) == REG)
9109 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9119 /* Get regmode weight for insn. */
9121 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9123 short reg_weight = 0;
9126 /* Increment weight for each register born here. */
9128 reg_weight += find_set_regmode_weight (x, mode);
9129 if (GET_CODE (x) == PARALLEL)
9132 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9134 x = XVECEXP (PATTERN (insn), 0, j);
9135 reg_weight += find_set_regmode_weight (x, mode);
9138 /* Decrement weight for each register that dies here. */
9139 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9141 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9143 rtx note = XEXP (x, 0);
9144 if (GET_CODE (note) == REG && GET_MODE (note) == mode)
9151 /* Calculate regmode weights for all insns of a basic block. */
9153 find_regmode_weight (basic_block b, enum machine_mode mode)
9155 rtx insn, next_tail, head, tail;
9157 get_ebb_head_tail (b, b, &head, &tail);
9158 next_tail = NEXT_INSN (tail);
9160 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9162 /* Handle register life information. */
9167 INSN_REGMODE_WEIGHT (insn, mode) =
9168 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9169 else if (mode == SImode)
9170 INSN_REGMODE_WEIGHT (insn, mode) =
9171 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9175 /* Comparison function for ready queue sorting. */
9177 rank_for_reorder (const void *x, const void *y)
9179 rtx tmp = *(const rtx *) y;
9180 rtx tmp2 = *(const rtx *) x;
9182 /* The insn in a schedule group should be issued the first. */
9183 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9184 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9186 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9187 minimizes instruction movement, thus minimizing sched's effect on
9188 register pressure. */
9189 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9192 /* Resort the array A in which only element at index N may be out of order. */
9194 swap_reorder (rtx *a, int n)
9196 rtx insn = a[n - 1];
9199 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9207 #define SCHED_REORDER(READY, N_READY) \
9210 if ((N_READY) == 2) \
9211 swap_reorder (READY, N_READY); \
9212 else if ((N_READY) > 2) \
9213 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9217 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9220 ready_reorder (rtx *ready, int nready)
9222 SCHED_REORDER (ready, nready);
9225 /* Calculate regmode weights for all insns of all basic block. */
9227 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9228 int verbose ATTRIBUTE_UNUSED,
9233 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9234 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9236 FOR_EACH_BB_REVERSE (b)
9238 find_regmode_weight (b, SImode);
9239 find_regmode_weight (b, SFmode);
9242 CURR_REGMODE_PRESSURE (SImode) = 0;
9243 CURR_REGMODE_PRESSURE (SFmode) = 0;
9249 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9250 int verbose ATTRIBUTE_UNUSED)
9252 if (regmode_weight[0])
9254 free (regmode_weight[0]);
9255 regmode_weight[0] = NULL;
9257 if (regmode_weight[1])
9259 free (regmode_weight[1]);
9260 regmode_weight[1] = NULL;
9264 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9265 keep count of register pressures on SImode and SFmode. */
9267 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9268 int sched_verbose ATTRIBUTE_UNUSED,
9272 if (GET_CODE (PATTERN (insn)) != USE
9273 && GET_CODE (PATTERN (insn)) != CLOBBER)
9274 cached_can_issue_more = can_issue_more - 1;
9276 cached_can_issue_more = can_issue_more;
9278 if (reload_completed)
9279 return cached_can_issue_more;
9281 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9282 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9284 return cached_can_issue_more;
9288 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9289 int verbose ATTRIBUTE_UNUSED,
9290 int veclen ATTRIBUTE_UNUSED)
9292 CURR_REGMODE_PRESSURE (SImode) = 0;
9293 CURR_REGMODE_PRESSURE (SFmode) = 0;
9296 /* Some magic numbers. */
9297 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9298 functions that already have high pressure on r0. */
9299 #define R0_MAX_LIFE_REGIONS 2
9300 #define R0_MAX_LIVE_LENGTH 12
9301 /* Register Pressure thresholds for SImode and SFmode registers. */
9302 #define SIMODE_MAX_WEIGHT 5
9303 #define SFMODE_MAX_WEIGHT 10
9305 /* Return true if the pressure is high for MODE. */
9307 high_pressure (enum machine_mode mode)
9309 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9310 functions that already have high pressure on r0. */
9311 if ((REG_N_SETS (0) - REG_N_DEATHS (0)) >= R0_MAX_LIFE_REGIONS
9312 && REG_LIVE_LENGTH (0) >= R0_MAX_LIVE_LENGTH)
9316 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9318 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9321 /* Reorder ready queue if register pressure is high. */
9323 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9324 int sched_verbose ATTRIBUTE_UNUSED,
9327 int clock_var ATTRIBUTE_UNUSED)
9329 if (reload_completed)
9330 return sh_issue_rate ();
9332 if (high_pressure (SFmode) || high_pressure (SImode))
9334 ready_reorder (ready, *n_readyp);
9337 return sh_issue_rate ();
9340 /* Skip cycles if the current register pressure is high. */
9342 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9343 int sched_verbose ATTRIBUTE_UNUSED,
9344 rtx *ready ATTRIBUTE_UNUSED,
9345 int *n_readyp ATTRIBUTE_UNUSED,
9346 int clock_var ATTRIBUTE_UNUSED)
9348 if (reload_completed)
9349 return cached_can_issue_more;
9351 if (high_pressure(SFmode) || high_pressure (SImode))
9354 return cached_can_issue_more;
9357 /* Skip cycles without sorting the ready queue. This will move insn from
9358 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9359 queue by sh_reorder. */
9361 /* Generally, skipping these many cycles are sufficient for all insns to move
9366 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
9367 int sched_verbose ATTRIBUTE_UNUSED,
9368 rtx insn ATTRIBUTE_UNUSED,
9373 if (reload_completed)
9378 if ((clock_var - last_clock_var) < MAX_SKIPS)
9383 /* If this is the last cycle we are skipping, allow reordering of R. */
9384 if ((clock_var - last_clock_var) == MAX_SKIPS)
9396 /* SHmedia requires registers for branches, so we can't generate new
9397 branches past reload. */
9399 sh_cannot_modify_jumps_p (void)
9401 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
9405 sh_target_reg_class (void)
9407 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
9411 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
9418 if (! shmedia_space_reserved_for_target_registers)
9420 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
9422 if (calc_live_regs (&dummy) >= 6 * 8)
9428 sh_ms_bitfield_layout_p (tree record_type ATTRIBUTE_UNUSED)
9430 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
9434 On the SH1..SH4, the trampoline looks like
9435 2 0002 D202 mov.l l2,r2
9436 1 0000 D301 mov.l l1,r3
9439 5 0008 00000000 l1: .long area
9440 6 000c 00000000 l2: .long function
9442 SH5 (compact) uses r1 instead of r3 for the static chain. */
9445 /* Emit RTL insns to initialize the variable parts of a trampoline.
9446 FNADDR is an RTX for the address of the function's pure code.
9447 CXT is an RTX for the static chain value for the function. */
9450 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
9452 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
9454 if (TARGET_SHMEDIA64)
9459 rtx movi1 = GEN_INT (0xcc000010);
9460 rtx shori1 = GEN_INT (0xc8000010);
9463 /* The following trampoline works within a +- 128 KB range for cxt:
9464 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
9465 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
9466 gettr tr1,r1; blink tr0,r63 */
9467 /* Address rounding makes it hard to compute the exact bounds of the
9468 offset for this trampoline, but we have a rather generous offset
9469 range, so frame_offset should do fine as an upper bound. */
9470 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
9472 /* ??? could optimize this trampoline initialization
9473 by writing DImode words with two insns each. */
9474 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
9475 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
9476 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
9477 insn = gen_rtx_AND (DImode, insn, mask);
9478 /* Or in ptb/u .,tr1 pattern */
9479 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
9480 insn = force_operand (insn, NULL_RTX);
9481 insn = gen_lowpart (SImode, insn);
9482 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
9483 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
9484 insn = gen_rtx_AND (DImode, insn, mask);
9485 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
9486 insn = gen_lowpart (SImode, insn);
9487 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
9488 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
9489 insn = gen_rtx_AND (DImode, insn, mask);
9490 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9491 insn = gen_lowpart (SImode, insn);
9492 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
9493 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
9494 insn = gen_rtx_AND (DImode, insn, mask);
9495 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9496 insn = gen_lowpart (SImode, insn);
9497 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
9498 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
9499 insn = gen_rtx_AND (DImode, insn, mask);
9500 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
9501 insn = gen_lowpart (SImode, insn);
9502 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
9503 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
9504 GEN_INT (0x6bf10600));
9505 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
9506 GEN_INT (0x4415fc10));
9507 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
9508 GEN_INT (0x4401fff0));
9509 emit_insn (gen_ic_invalidate_line (tramp));
9512 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
9513 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
9515 tramp_templ = gen_datalabel_ref (tramp_templ);
9517 src = gen_const_mem (BLKmode, tramp_templ);
9518 set_mem_align (dst, 256);
9519 set_mem_align (src, 64);
9520 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
9522 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
9523 emit_move_insn (adjust_address (tramp_mem, Pmode,
9524 fixed_len + GET_MODE_SIZE (Pmode)),
9526 emit_insn (gen_ic_invalidate_line (tramp));
9529 else if (TARGET_SHMEDIA)
9531 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
9532 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
9533 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
9534 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
9535 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
9536 rotated 10 right, and higher 16 bit of every 32 selected. */
9538 = force_reg (V2HImode, (simplify_gen_subreg
9539 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
9540 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
9541 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
9543 tramp = force_reg (Pmode, tramp);
9544 fnaddr = force_reg (SImode, fnaddr);
9545 cxt = force_reg (SImode, cxt);
9546 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
9547 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
9549 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
9550 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9551 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
9552 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
9553 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
9554 gen_rtx_SUBREG (V2HImode, cxt, 0),
9556 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
9557 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
9558 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
9559 if (TARGET_LITTLE_ENDIAN)
9561 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
9562 emit_insn (gen_mextr4 (quad2, cxtload, blink));
9566 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
9567 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
9569 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
9570 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
9571 emit_insn (gen_ic_invalidate_line (tramp));
9574 else if (TARGET_SHCOMPACT)
9576 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
9579 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
9580 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
9582 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
9583 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
9585 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
9586 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
9589 if (!TARGET_INLINE_IC_INVALIDATE
9590 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
9591 emit_library_call (function_symbol (NULL, "__ic_invalidate",
9593 0, VOIDmode, 1, tramp, SImode);
9595 emit_insn (gen_ic_invalidate_line (tramp));
9599 /* FIXME: This is overly conservative. A SHcompact function that
9600 receives arguments ``by reference'' will have them stored in its
9601 own stack frame, so it must not pass pointers or references to
9602 these arguments to other functions by means of sibling calls. */
9603 /* If PIC, we cannot make sibling calls to global functions
9604 because the PLT requires r12 to be live. */
9606 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9609 && (! TARGET_SHCOMPACT
9610 || current_function_args_info.stack_regs == 0)
9611 && ! sh_cfun_interrupt_handler_p ()
9613 || (decl && ! TREE_PUBLIC (decl))
9614 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
9617 /* Machine specific built-in functions. */
9619 struct builtin_description
9621 const enum insn_code icode;
9622 const char *const name;
9626 /* describe number and signedness of arguments; arg[0] == result
9627 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
9628 /* 9: 64-bit pointer, 10: 32-bit pointer */
9629 static const char signature_args[][4] =
9631 #define SH_BLTIN_V2SI2 0
9633 #define SH_BLTIN_V4HI2 1
9635 #define SH_BLTIN_V2SI3 2
9637 #define SH_BLTIN_V4HI3 3
9639 #define SH_BLTIN_V8QI3 4
9641 #define SH_BLTIN_MAC_HISI 5
9643 #define SH_BLTIN_SH_HI 6
9645 #define SH_BLTIN_SH_SI 7
9647 #define SH_BLTIN_V4HI2V2SI 8
9649 #define SH_BLTIN_V4HI2V8QI 9
9651 #define SH_BLTIN_SISF 10
9653 #define SH_BLTIN_LDUA_L 11
9655 #define SH_BLTIN_LDUA_Q 12
9657 #define SH_BLTIN_STUA_L 13
9659 #define SH_BLTIN_STUA_Q 14
9661 #define SH_BLTIN_LDUA_L64 15
9663 #define SH_BLTIN_LDUA_Q64 16
9665 #define SH_BLTIN_STUA_L64 17
9667 #define SH_BLTIN_STUA_Q64 18
9669 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
9670 #define SH_BLTIN_2 19
9671 #define SH_BLTIN_SU 19
9673 #define SH_BLTIN_3 20
9674 #define SH_BLTIN_SUS 20
9676 #define SH_BLTIN_PSSV 21
9678 #define SH_BLTIN_XXUU 22
9679 #define SH_BLTIN_UUUU 22
9681 #define SH_BLTIN_PV 23
9684 /* mcmv: operands considered unsigned. */
9685 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
9686 /* mperm: control value considered unsigned int. */
9687 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
9688 /* mshards_q: returns signed short. */
9689 /* nsb: takes long long arg, returns unsigned char. */
9690 static const struct builtin_description bdesc[] =
9692 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
9693 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
9694 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
9695 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
9696 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
9697 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
9698 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
9699 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
9700 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
9701 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
9702 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
9703 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
9704 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
9705 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
9706 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
9707 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
9708 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
9709 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
9710 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
9711 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
9712 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
9713 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
9714 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
9715 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
9716 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
9717 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
9718 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
9719 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
9720 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
9721 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
9722 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
9723 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
9724 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
9725 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
9726 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
9727 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
9728 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
9729 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
9730 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
9731 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
9732 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
9733 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
9734 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
9735 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
9736 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
9737 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
9738 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
9739 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
9740 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
9741 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
9742 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
9743 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
9744 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
9745 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
9746 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
9747 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
9748 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
9749 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
9750 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
9751 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
9752 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
9753 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
9754 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
9755 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
9756 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
9757 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
9758 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
9759 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
9760 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
9761 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
9762 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
9763 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
9764 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
9765 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
9766 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
9767 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
9768 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
9769 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
9770 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
9771 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
9772 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
9773 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
9774 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
9775 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
9779 sh_media_init_builtins (void)
9781 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
9782 const struct builtin_description *d;
9784 memset (shared, 0, sizeof shared);
9785 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
9787 tree type, arg_type = 0;
9788 int signature = d->signature;
9791 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
9792 type = shared[signature];
9795 int has_result = signature_args[signature][0] != 0;
9797 if ((signature_args[signature][1] & 8)
9798 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
9799 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
9801 if (! TARGET_FPU_ANY
9802 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
9804 type = void_list_node;
9807 int arg = signature_args[signature][i];
9808 int opno = i - 1 + has_result;
9811 arg_type = ptr_type_node;
9813 arg_type = (*lang_hooks.types.type_for_mode)
9814 (insn_data[d->icode].operand[opno].mode,
9819 arg_type = void_type_node;
9822 type = tree_cons (NULL_TREE, arg_type, type);
9824 type = build_function_type (arg_type, type);
9825 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
9826 shared[signature] = type;
9828 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
9833 /* Implements target hook vector_mode_supported_p. */
9835 sh_vector_mode_supported_p (enum machine_mode mode)
9838 && ((mode == V2SFmode)
9839 || (mode == V4SFmode)
9840 || (mode == V16SFmode)))
9843 else if (TARGET_SHMEDIA
9844 && ((mode == V8QImode)
9845 || (mode == V2HImode)
9846 || (mode == V4HImode)
9847 || (mode == V2SImode)))
9853 /* Implements target hook dwarf_calling_convention. Return an enum
9854 of dwarf_calling_convention. */
9856 sh_dwarf_calling_convention (tree func)
9858 if (sh_attr_renesas_p (func))
9859 return DW_CC_GNU_renesas_sh;
9861 return DW_CC_normal;
9865 sh_init_builtins (void)
9868 sh_media_init_builtins ();
9871 /* Expand an expression EXP that calls a built-in function,
9872 with result going to TARGET if that's convenient
9873 (and in mode MODE if that's convenient).
9874 SUBTARGET may be used as the target for computing one of EXP's operands.
9875 IGNORE is nonzero if the value is to be ignored. */
9878 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9879 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
9881 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9882 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9883 const struct builtin_description *d = &bdesc[fcode];
9884 enum insn_code icode = d->icode;
9885 int signature = d->signature;
9886 enum machine_mode tmode = VOIDmode;
9891 if (signature_args[signature][0])
9896 tmode = insn_data[icode].operand[0].mode;
9898 || GET_MODE (target) != tmode
9899 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9900 target = gen_reg_rtx (tmode);
9906 for (i = 1; i <= 3; i++, nop++)
9909 enum machine_mode opmode, argmode;
9912 if (! signature_args[signature][i])
9914 arg = CALL_EXPR_ARG (exp, i - 1);
9915 if (arg == error_mark_node)
9917 if (signature_args[signature][i] & 8)
9920 optype = ptr_type_node;
9924 opmode = insn_data[icode].operand[nop].mode;
9925 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
9927 argmode = TYPE_MODE (TREE_TYPE (arg));
9928 if (argmode != opmode)
9929 arg = build1 (NOP_EXPR, optype, arg);
9930 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
9931 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
9932 op[nop] = copy_to_mode_reg (opmode, op[nop]);
9938 pat = (*insn_data[d->icode].genfun) (op[0]);
9941 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
9944 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
9947 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
9959 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
9961 rtx sel0 = const0_rtx;
9962 rtx sel1 = const1_rtx;
9963 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
9964 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
9966 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
9967 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
9971 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
9973 rtx sel0 = const0_rtx;
9974 rtx sel1 = const1_rtx;
9975 rtx (*fn) (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx)
9977 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
9979 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
9980 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
9983 /* Return the class of registers for which a mode change from FROM to TO
9986 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9987 enum reg_class class)
9989 /* We want to enable the use of SUBREGs as a means to
9990 VEC_SELECT a single element of a vector. */
9991 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
9992 return (reg_classes_intersect_p (GENERAL_REGS, class));
9994 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
9996 if (TARGET_LITTLE_ENDIAN)
9998 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
9999 return reg_classes_intersect_p (DF_REGS, class);
10003 if (GET_MODE_SIZE (from) < 8)
10004 return reg_classes_intersect_p (DF_HI_REGS, class);
10011 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10012 that label is used. */
10015 sh_mark_label (rtx address, int nuses)
10017 if (GOTOFF_P (address))
10019 /* Extract the label or symbol. */
10020 address = XEXP (address, 0);
10021 if (GET_CODE (address) == PLUS)
10022 address = XEXP (address, 0);
10023 address = XVECEXP (address, 0, 0);
10025 if (GET_CODE (address) == LABEL_REF
10026 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
10027 LABEL_NUSES (XEXP (address, 0)) += nuses;
10030 /* Compute extra cost of moving data between one register class
10033 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10034 uses this information. Hence, the general register <-> floating point
10035 register information here is not used for SFmode. */
10038 sh_register_move_cost (enum machine_mode mode,
10039 enum reg_class srcclass, enum reg_class dstclass)
10041 if (dstclass == T_REGS || dstclass == PR_REGS)
10044 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10047 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10048 && REGCLASS_HAS_FP_REG (srcclass)
10049 && REGCLASS_HAS_FP_REG (dstclass))
10052 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10053 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10055 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10056 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10059 if ((REGCLASS_HAS_FP_REG (dstclass)
10060 && REGCLASS_HAS_GENERAL_REG (srcclass))
10061 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10062 && REGCLASS_HAS_FP_REG (srcclass)))
10063 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
10064 * ((GET_MODE_SIZE (mode) + 7) / 8U));
10066 if ((dstclass == FPUL_REGS
10067 && REGCLASS_HAS_GENERAL_REG (srcclass))
10068 || (srcclass == FPUL_REGS
10069 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10072 if ((dstclass == FPUL_REGS
10073 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10074 || (srcclass == FPUL_REGS
10075 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10078 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10079 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10082 /* ??? ptabs faults on (value & 0x3) == 0x3 */
10084 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
10086 if (sh_gettrcost >= 0)
10087 return sh_gettrcost;
10088 else if (!TARGET_PT_FIXED)
10092 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10093 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10098 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10099 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
10100 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10102 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10105 static rtx emit_load_ptr (rtx, rtx);
10108 emit_load_ptr (rtx reg, rtx addr)
10110 rtx mem = gen_const_mem (ptr_mode, addr);
10112 if (Pmode != ptr_mode)
10113 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10114 return emit_move_insn (reg, mem);
10118 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10119 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10122 CUMULATIVE_ARGS cum;
10123 int structure_value_byref = 0;
10124 rtx this, this_value, sibcall, insns, funexp;
10125 tree funtype = TREE_TYPE (function);
10126 int simple_add = CONST_OK_FOR_ADD (delta);
10128 rtx scratch0, scratch1, scratch2;
10131 reload_completed = 1;
10132 epilogue_completed = 1;
10133 no_new_pseudos = 1;
10134 current_function_uses_only_leaf_regs = 1;
10136 emit_note (NOTE_INSN_PROLOGUE_END);
10138 /* Find the "this" pointer. We have such a wide range of ABIs for the
10139 SH that it's best to do this completely machine independently.
10140 "this" is passed as first argument, unless a structure return pointer
10141 comes first, in which case "this" comes second. */
10142 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10143 #ifndef PCC_STATIC_STRUCT_RETURN
10144 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10145 structure_value_byref = 1;
10146 #endif /* not PCC_STATIC_STRUCT_RETURN */
10147 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10149 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10151 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
10153 this = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
10155 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10156 static chain pointer (even if you can't have nested virtual functions
10157 right now, someone might implement them sometime), and the rest of the
10158 registers are used for argument passing, are callee-saved, or reserved. */
10159 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10160 -ffixed-reg has been used. */
10161 if (! call_used_regs[0] || fixed_regs[0])
10162 error ("r0 needs to be available as a call-clobbered register");
10163 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10166 if (call_used_regs[1] && ! fixed_regs[1])
10167 scratch1 = gen_rtx_REG (ptr_mode, 1);
10168 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10169 pointing where to return struct values. */
10170 if (call_used_regs[3] && ! fixed_regs[3])
10171 scratch2 = gen_rtx_REG (Pmode, 3);
10173 else if (TARGET_SHMEDIA)
10175 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
10176 if (i != REGNO (scratch0) &&
10177 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
10179 scratch1 = gen_rtx_REG (ptr_mode, i);
10182 if (scratch1 == scratch0)
10183 error ("Need a second call-clobbered general purpose register");
10184 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
10185 if (call_used_regs[i] && ! fixed_regs[i])
10187 scratch2 = gen_rtx_REG (Pmode, i);
10190 if (scratch2 == scratch0)
10191 error ("Need a call-clobbered target register");
10194 this_value = plus_constant (this, delta);
10196 && (simple_add || scratch0 != scratch1)
10197 && strict_memory_address_p (ptr_mode, this_value))
10199 emit_load_ptr (scratch0, this_value);
10204 ; /* Do nothing. */
10205 else if (simple_add)
10206 emit_move_insn (this, this_value);
10209 emit_move_insn (scratch1, GEN_INT (delta));
10210 emit_insn (gen_add2_insn (this, scratch1));
10218 emit_load_ptr (scratch0, this);
10220 offset_addr = plus_constant (scratch0, vcall_offset);
10221 if (strict_memory_address_p (ptr_mode, offset_addr))
10222 ; /* Do nothing. */
10223 else if (! TARGET_SH5 && scratch0 != scratch1)
10225 /* scratch0 != scratch1, and we have indexed loads. Get better
10226 schedule by loading the offset into r1 and using an indexed
10227 load - then the load of r1 can issue before the load from
10228 (this + delta) finishes. */
10229 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10230 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10232 else if (CONST_OK_FOR_ADD (vcall_offset))
10234 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10235 offset_addr = scratch0;
10237 else if (scratch0 != scratch1)
10239 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10240 emit_insn (gen_add2_insn (scratch0, scratch1));
10241 offset_addr = scratch0;
10244 gcc_unreachable (); /* FIXME */
10245 emit_load_ptr (scratch0, offset_addr);
10247 if (Pmode != ptr_mode)
10248 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10249 emit_insn (gen_add2_insn (this, scratch0));
10252 /* Generate a tail call to the target function. */
10253 if (! TREE_USED (function))
10255 assemble_external (function);
10256 TREE_USED (function) = 1;
10258 funexp = XEXP (DECL_RTL (function), 0);
10259 /* If the function is overridden, so is the thunk, hence we don't
10260 need GOT addressing even if this is a public symbol. */
10262 if (TARGET_SH1 && ! flag_weak)
10263 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10266 if (TARGET_SH2 && flag_pic)
10268 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10269 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10273 if (TARGET_SHMEDIA && flag_pic)
10275 funexp = gen_sym2PIC (funexp);
10276 PUT_MODE (funexp, Pmode);
10278 emit_move_insn (scratch2, funexp);
10279 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10280 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10282 sibcall = emit_call_insn (sibcall);
10283 SIBLING_CALL_P (sibcall) = 1;
10284 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this);
10287 /* Run just enough of rest_of_compilation to do scheduling and get
10288 the insns emitted. Note that use_thunk calls
10289 assemble_start_function and assemble_end_function. */
10291 insn_locators_alloc ();
10292 insns = get_insns ();
10296 /* Initialize the bitmap obstacks. */
10297 bitmap_obstack_initialize (NULL);
10298 bitmap_obstack_initialize (®_obstack);
10301 rtl_register_cfg_hooks ();
10302 init_rtl_bb_info (ENTRY_BLOCK_PTR);
10303 init_rtl_bb_info (EXIT_BLOCK_PTR);
10304 ENTRY_BLOCK_PTR->flags |= BB_RTL;
10305 EXIT_BLOCK_PTR->flags |= BB_RTL;
10306 find_basic_blocks (insns);
10308 if (flag_schedule_insns_after_reload)
10310 life_analysis (PROP_FINAL);
10312 split_all_insns (1);
10316 /* We must split jmp insn in PIC case. */
10318 split_all_insns_noflow ();
10323 if (optimize > 0 && flag_delayed_branch)
10324 dbr_schedule (insns);
10326 shorten_branches (insns);
10327 final_start_function (insns, file, 1);
10328 final (insns, file, 1);
10329 final_end_function ();
10333 /* Release all memory allocated by flow. */
10334 free_basic_block_vars ();
10336 /* Release the bitmap obstacks. */
10337 bitmap_obstack_release (®_obstack);
10338 bitmap_obstack_release (NULL);
10341 reload_completed = 0;
10342 epilogue_completed = 0;
10343 no_new_pseudos = 0;
10347 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
10351 /* If this is not an ordinary function, the name usually comes from a
10352 string literal or an sprintf buffer. Make sure we use the same
10353 string consistently, so that cse will be able to unify address loads. */
10354 if (kind != FUNCTION_ORDINARY)
10355 name = IDENTIFIER_POINTER (get_identifier (name));
10356 sym = gen_rtx_SYMBOL_REF (Pmode, name);
10357 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10361 case FUNCTION_ORDINARY:
10365 rtx reg = target ? target : gen_reg_rtx (Pmode);
10367 emit_insn (gen_symGOT2reg (reg, sym));
10373 /* ??? To allow cse to work, we use GOTOFF relocations.
10374 we could add combiner patterns to transform this into
10375 straight pc-relative calls with sym2PIC / bsrf when
10376 label load and function call are still 1:1 and in the
10377 same basic block during combine. */
10378 rtx reg = target ? target : gen_reg_rtx (Pmode);
10380 emit_insn (gen_symGOTOFF2reg (reg, sym));
10385 if (target && sym != target)
10387 emit_move_insn (target, sym);
10393 /* Find the number of a general purpose register in S. */
10395 scavenge_reg (HARD_REG_SET *s)
10398 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
10399 if (TEST_HARD_REG_BIT (*s, r))
10405 sh_get_pr_initial_val (void)
10409 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
10410 PR register on SHcompact, because it might be clobbered by the prologue.
10411 We check first if that is known to be the case. */
10412 if (TARGET_SHCOMPACT
10413 && ((current_function_args_info.call_cookie
10414 & ~ CALL_COOKIE_RET_TRAMP (1))
10415 || current_function_has_nonlocal_label))
10416 return gen_frame_mem (SImode, return_address_pointer_rtx);
10418 /* If we haven't finished rtl generation, there might be a nonlocal label
10419 that we haven't seen yet.
10420 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
10421 is set, unless it has been called before for the same register. And even
10422 then, we end in trouble if we didn't use the register in the same
10423 basic block before. So call get_hard_reg_initial_val now and wrap it
10424 in an unspec if we might need to replace it. */
10425 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
10426 combine can put the pseudo returned by get_hard_reg_initial_val into
10427 instructions that need a general purpose registers, which will fail to
10428 be recognized when the pseudo becomes allocated to PR. */
10430 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10432 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
10437 sh_expand_t_scc (enum rtx_code code, rtx target)
10439 rtx result = target;
10442 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
10443 || GET_CODE (sh_compare_op1) != CONST_INT)
10445 if (GET_CODE (result) != REG)
10446 result = gen_reg_rtx (SImode);
10447 val = INTVAL (sh_compare_op1);
10448 if ((code == EQ && val == 1) || (code == NE && val == 0))
10449 emit_insn (gen_movt (result));
10450 else if ((code == EQ && val == 0) || (code == NE && val == 1))
10452 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
10453 emit_insn (gen_subc (result, result, result));
10454 emit_insn (gen_addsi3 (result, result, const1_rtx));
10456 else if (code == EQ || code == NE)
10457 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
10460 if (result != target)
10461 emit_move_insn (target, result);
10465 /* INSN is an sfunc; return the rtx that describes the address used. */
10467 extract_sfunc_addr (rtx insn)
10469 rtx pattern, part = NULL_RTX;
10472 pattern = PATTERN (insn);
10473 len = XVECLEN (pattern, 0);
10474 for (i = 0; i < len; i++)
10476 part = XVECEXP (pattern, 0, i);
10477 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
10478 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
10479 return XEXP (part, 0);
10481 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
10482 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
10485 /* Verify that the register in use_sfunc_addr still agrees with the address
10486 used in the sfunc. This prevents fill_slots_from_thread from changing
10488 INSN is the use_sfunc_addr instruction, and REG is the register it
10491 check_use_sfunc_addr (rtx insn, rtx reg)
10493 /* Search for the sfunc. It should really come right after INSN. */
10494 while ((insn = NEXT_INSN (insn)))
10496 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
10498 if (! INSN_P (insn))
10501 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10502 insn = XVECEXP (PATTERN (insn), 0, 0);
10503 if (GET_CODE (PATTERN (insn)) != PARALLEL
10504 || get_attr_type (insn) != TYPE_SFUNC)
10506 return rtx_equal_p (extract_sfunc_addr (insn), reg);
10508 gcc_unreachable ();
10511 /* This function returns a constant rtx that represents pi / 2**15 in
10512 SFmode. it's used to scale SFmode angles, in radians, to a
10513 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10514 maps to 0x10000). */
10516 static GTY(()) rtx sh_fsca_sf2int_rtx;
10519 sh_fsca_sf2int (void)
10521 if (! sh_fsca_sf2int_rtx)
10523 REAL_VALUE_TYPE rv;
10525 real_from_string (&rv, "10430.378350470453");
10526 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
10529 return sh_fsca_sf2int_rtx;
10532 /* This function returns a constant rtx that represents pi / 2**15 in
10533 DFmode. it's used to scale DFmode angles, in radians, to a
10534 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
10535 maps to 0x10000). */
10537 static GTY(()) rtx sh_fsca_df2int_rtx;
10540 sh_fsca_df2int (void)
10542 if (! sh_fsca_df2int_rtx)
10544 REAL_VALUE_TYPE rv;
10546 real_from_string (&rv, "10430.378350470453");
10547 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
10550 return sh_fsca_df2int_rtx;
10553 /* This function returns a constant rtx that represents 2**15 / pi in
10554 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
10555 of a full circle back to a SFmode value, i.e., 0x10000 maps to
10558 static GTY(()) rtx sh_fsca_int2sf_rtx;
10561 sh_fsca_int2sf (void)
10563 if (! sh_fsca_int2sf_rtx)
10565 REAL_VALUE_TYPE rv;
10567 real_from_string (&rv, "9.587379924285257e-5");
10568 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
10571 return sh_fsca_int2sf_rtx;
10574 /* Initialize the CUMULATIVE_ARGS structure. */
10577 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
10579 rtx libname ATTRIBUTE_UNUSED,
10581 signed int n_named_args,
10582 enum machine_mode mode)
10584 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
10585 pcum->free_single_fp_reg = 0;
10586 pcum->stack_regs = 0;
10587 pcum->byref_regs = 0;
10589 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
10591 /* XXX - Should we check TARGET_HITACHI here ??? */
10592 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
10596 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
10597 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
10598 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
10599 pcum->arg_count [(int) SH_ARG_INT]
10600 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
10603 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10604 && pcum->arg_count [(int) SH_ARG_INT] == 0
10605 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
10606 ? int_size_in_bytes (TREE_TYPE (fntype))
10607 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
10608 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
10609 == FIRST_RET_REG));
10613 pcum->arg_count [(int) SH_ARG_INT] = 0;
10614 pcum->prototype_p = FALSE;
10615 if (mode != VOIDmode)
10617 pcum->call_cookie =
10618 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
10619 && GET_MODE_SIZE (mode) > 4
10620 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
10622 /* If the default ABI is the Renesas ABI then all library
10623 calls must assume that the library will be using the
10624 Renesas ABI. So if the function would return its result
10625 in memory then we must force the address of this memory
10626 block onto the stack. Ideally we would like to call
10627 targetm.calls.return_in_memory() here but we do not have
10628 the TYPE or the FNDECL available so we synthesize the
10629 contents of that function as best we can. */
10631 (TARGET_DEFAULT & MASK_HITACHI)
10632 && (mode == BLKmode
10633 || (GET_MODE_SIZE (mode) > 4
10634 && !(mode == DFmode
10635 && TARGET_FPU_DOUBLE)));
10639 pcum->call_cookie = 0;
10640 pcum->force_mem = FALSE;
10645 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
10646 not enter into CONST_DOUBLE for the replace.
10648 Note that copying is not done so X must not be shared unless all copies
10649 are to be modified.
10651 This is like replace_rtx, except that we operate on N_REPLACEMENTS
10652 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
10653 replacements[n*2+1] - and that we take mode changes into account.
10655 If a replacement is ambiguous, return NULL_RTX.
10657 If MODIFY is zero, don't modify any rtl in place,
10658 just return zero or nonzero for failure / success. */
10661 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
10666 /* The following prevents loops occurrence when we change MEM in
10667 CONST_DOUBLE onto the same CONST_DOUBLE. */
10668 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
10671 for (i = n_replacements - 1; i >= 0 ; i--)
10672 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
10673 return replacements[i*2+1];
10675 /* Allow this function to make replacements in EXPR_LISTs. */
10679 if (GET_CODE (x) == SUBREG)
10681 rtx new = replace_n_hard_rtx (SUBREG_REG (x), replacements,
10682 n_replacements, modify);
10684 if (GET_CODE (new) == CONST_INT)
10686 x = simplify_subreg (GET_MODE (x), new,
10687 GET_MODE (SUBREG_REG (x)),
10693 SUBREG_REG (x) = new;
10697 else if (GET_CODE (x) == REG)
10699 unsigned regno = REGNO (x);
10700 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
10701 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10702 rtx result = NULL_RTX;
10704 for (i = n_replacements - 1; i >= 0; i--)
10706 rtx from = replacements[i*2];
10707 rtx to = replacements[i*2+1];
10708 unsigned from_regno, from_nregs, to_regno, new_regno;
10710 if (GET_CODE (from) != REG)
10712 from_regno = REGNO (from);
10713 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
10714 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
10715 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
10717 if (regno < from_regno
10718 || regno + nregs > from_regno + nregs
10719 || GET_CODE (to) != REG
10722 to_regno = REGNO (to);
10723 if (to_regno < FIRST_PSEUDO_REGISTER)
10725 new_regno = regno + to_regno - from_regno;
10726 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
10729 result = gen_rtx_REG (GET_MODE (x), new_regno);
10731 else if (GET_MODE (x) <= GET_MODE (to))
10732 result = gen_lowpart_common (GET_MODE (x), to);
10734 result = gen_lowpart_SUBREG (GET_MODE (x), to);
10737 return result ? result : x;
10739 else if (GET_CODE (x) == ZERO_EXTEND)
10741 rtx new = replace_n_hard_rtx (XEXP (x, 0), replacements,
10742 n_replacements, modify);
10744 if (GET_CODE (new) == CONST_INT)
10746 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
10747 new, GET_MODE (XEXP (x, 0)));
10757 fmt = GET_RTX_FORMAT (GET_CODE (x));
10758 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
10764 new = replace_n_hard_rtx (XEXP (x, i), replacements,
10765 n_replacements, modify);
10771 else if (fmt[i] == 'E')
10772 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10774 new = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
10775 n_replacements, modify);
10779 XVECEXP (x, i, j) = new;
10787 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
10789 enum rtx_code code = TRUNCATE;
10791 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
10793 rtx inner = XEXP (x, 0);
10794 enum machine_mode inner_mode = GET_MODE (inner);
10796 if (inner_mode == mode)
10798 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
10800 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
10801 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
10803 code = GET_CODE (x);
10807 return gen_rtx_fmt_e (code, mode, x);
10810 /* called via for_each_rtx after reload, to clean up truncates of
10811 registers that span multiple actual hard registers. */
10813 shmedia_cleanup_truncate (rtx *p, void *n_changes)
10817 if (GET_CODE (x) != TRUNCATE)
10820 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG)
10822 enum machine_mode reg_mode = GET_MODE (reg);
10823 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
10824 subreg_lowpart_offset (DImode, reg_mode));
10825 *(int*) n_changes += 1;
10831 /* Load and store depend on the highpart of the address. However,
10832 set_attr_alternative does not give well-defined results before reload,
10833 so we must look at the rtl ourselves to see if any of the feeding
10834 registers is used in a memref. */
10836 /* Called by sh_contains_memref_p via for_each_rtx. */
10838 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
10840 return (GET_CODE (*loc) == MEM);
10843 /* Return nonzero iff INSN contains a MEM. */
10845 sh_contains_memref_p (rtx insn)
10847 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
10850 /* FNADDR is the MEM expression from a call expander. Return an address
10851 to use in an SHmedia insn pattern. */
10853 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
10857 fnaddr = XEXP (fnaddr, 0);
10858 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
10859 if (flag_pic && is_sym)
10861 if (! SYMBOL_REF_LOCAL_P (fnaddr))
10863 rtx reg = gen_reg_rtx (Pmode);
10865 /* We must not use GOTPLT for sibcalls, because PIC_REG
10866 must be restored before the PLT code gets to run. */
10868 emit_insn (gen_symGOT2reg (reg, fnaddr));
10870 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
10875 fnaddr = gen_sym2PIC (fnaddr);
10876 PUT_MODE (fnaddr, Pmode);
10879 /* If ptabs might trap, make this visible to the rest of the compiler.
10880 We generally assume that symbols pertain to valid locations, but
10881 it is possible to generate invalid symbols with asm or linker tricks.
10882 In a list of functions where each returns its successor, an invalid
10883 symbol might denote an empty list. */
10884 if (!TARGET_PT_FIXED
10885 && (!is_sym || TARGET_INVALID_SYMBOLS)
10886 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
10888 rtx tr = gen_reg_rtx (PDImode);
10890 emit_insn (gen_ptabs (tr, fnaddr));
10893 else if (! target_reg_operand (fnaddr, Pmode))
10894 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
10899 sh_secondary_reload (bool in_p, rtx x, enum reg_class class,
10900 enum machine_mode mode, secondary_reload_info *sri)
10904 if (REGCLASS_HAS_FP_REG (class)
10905 && ! TARGET_SHMEDIA
10906 && immediate_operand ((x), mode)
10907 && ! ((fp_zero_operand (x) || fp_one_operand (x))
10908 && mode == SFmode && fldi_ok ()))
10912 sri->icode = CODE_FOR_reload_insf__frn;
10915 sri->icode = CODE_FOR_reload_indf__frn;
10918 /* ??? If we knew that we are in the appropriate mode -
10919 single precision - we could use a reload pattern directly. */
10924 if (class == FPUL_REGS
10925 && ((GET_CODE (x) == REG
10926 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
10927 || REGNO (x) == T_REG))
10928 || GET_CODE (x) == PLUS))
10929 return GENERAL_REGS;
10930 if (class == FPUL_REGS && immediate_operand (x, mode))
10932 if (GET_CODE (x) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (x)))
10933 return GENERAL_REGS;
10934 sri->icode = CODE_FOR_reload_insi__i_fpul;
10937 if (class == FPSCR_REGS
10938 && ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
10939 || (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS)))
10940 return GENERAL_REGS;
10941 if (REGCLASS_HAS_FP_REG (class)
10943 && immediate_operand (x, mode)
10944 && x != CONST0_RTX (GET_MODE (x))
10945 && GET_MODE (x) != V4SFmode)
10946 return GENERAL_REGS;
10947 if ((mode == QImode || mode == HImode)
10948 && TARGET_SHMEDIA && inqhi_operand (x, mode))
10950 sri->icode = ((mode == QImode)
10951 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
10954 if (TARGET_SHMEDIA && class == GENERAL_REGS
10955 && (GET_CODE (x) == LABEL_REF || PIC_DIRECT_ADDR_P (x)))
10956 return TARGET_REGS;
10957 } /* end of input-only processing. */
10959 if (((REGCLASS_HAS_FP_REG (class)
10960 && (GET_CODE (x) == REG
10961 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
10962 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
10963 && TARGET_FMOVD))))
10964 || (REGCLASS_HAS_GENERAL_REG (class)
10965 && GET_CODE (x) == REG
10966 && FP_REGISTER_P (REGNO (x))))
10967 && ! TARGET_SHMEDIA
10968 && (mode == SFmode || mode == SImode))
10970 if ((class == FPUL_REGS
10971 || (REGCLASS_HAS_FP_REG (class)
10972 && ! TARGET_SHMEDIA && mode == SImode))
10973 && (GET_CODE (x) == MEM
10974 || (GET_CODE (x) == REG
10975 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
10976 || REGNO (x) == T_REG
10977 || system_reg_operand (x, VOIDmode)))))
10979 if (class == FPUL_REGS)
10980 return GENERAL_REGS;
10983 if ((class == TARGET_REGS
10984 || (TARGET_SHMEDIA && class == SIBCALL_REGS))
10985 && !EXTRA_CONSTRAINT_Csy (x)
10986 && (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x))))
10987 return GENERAL_REGS;
10988 if ((class == MAC_REGS || class == PR_REGS)
10989 && GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x))
10990 && class != REGNO_REG_CLASS (REGNO (x)))
10991 return GENERAL_REGS;
10992 if (class != GENERAL_REGS && GET_CODE (x) == REG
10993 && TARGET_REGISTER_P (REGNO (x)))
10994 return GENERAL_REGS;
10998 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;