1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
40 #include "diagnostic-core.h"
42 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
57 #include "alloc-pool.h"
58 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt;
85 tree sh_deferred_function_attributes;
86 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles = 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid = 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static bool sh_handle_option (struct gcc_options *, struct gcc_options *,
172 const struct cl_decoded_option *, location_t);
173 static void split_branches (rtx);
174 static int branch_dest (rtx);
175 static void force_into (rtx, rtx);
176 static void print_slot (rtx);
177 static rtx add_constant (rtx, enum machine_mode, rtx);
178 static void dump_table (rtx, rtx);
179 static int hi_const (rtx);
180 static int broken_move (rtx);
181 static int mova_p (rtx);
182 static rtx find_barrier (int, rtx, rtx);
183 static int noncall_uses_reg (rtx, rtx, rtx *);
184 static rtx gen_block_redirect (rtx, int, int);
185 static void sh_reorg (void);
186 static void sh_option_override (void);
187 static void sh_option_init_struct (struct gcc_options *);
188 static void sh_option_default_params (void);
189 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
190 static rtx frame_insn (rtx);
191 static rtx push (int);
192 static void pop (int);
193 static void push_regs (HARD_REG_SET *, int);
194 static int calc_live_regs (HARD_REG_SET *);
195 static HOST_WIDE_INT rounded_frame_size (int);
196 static bool sh_frame_pointer_required (void);
197 static rtx mark_constant_pool_use (rtx);
198 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
199 static tree sh_handle_resbank_handler_attribute (tree *, tree,
201 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
203 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
204 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
205 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
206 static void sh_print_operand (FILE *, rtx, int);
207 static void sh_print_operand_address (FILE *, rtx);
208 static bool sh_print_operand_punct_valid_p (unsigned char code);
209 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
210 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
211 static void sh_insert_attributes (tree, tree *);
212 static const char *sh_check_pch_target_flags (int);
213 static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
214 static int sh_adjust_cost (rtx, rtx, rtx, int);
215 static int sh_issue_rate (void);
216 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
217 static short find_set_regmode_weight (rtx, enum machine_mode);
218 static short find_insn_regmode_weight (rtx, enum machine_mode);
219 static void find_regmode_weight (basic_block, enum machine_mode);
220 static int find_r0_life_regions (basic_block);
221 static void sh_md_init_global (FILE *, int, int);
222 static void sh_md_finish_global (FILE *, int);
223 static int rank_for_reorder (const void *, const void *);
224 static void swap_reorder (rtx *, int);
225 static void ready_reorder (rtx *, int);
226 static short high_pressure (enum machine_mode);
227 static int sh_reorder (FILE *, int, rtx *, int *, int);
228 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
229 static void sh_md_init (FILE *, int, int);
230 static int sh_variable_issue (FILE *, int, rtx, int);
232 static bool sh_function_ok_for_sibcall (tree, tree);
234 static bool sh_cannot_modify_jumps_p (void);
235 static reg_class_t sh_target_reg_class (void);
236 static bool sh_optimize_target_register_callee_saved (bool);
237 static bool sh_ms_bitfield_layout_p (const_tree);
239 static void sh_init_builtins (void);
240 static tree sh_builtin_decl (unsigned, bool);
241 static void sh_media_init_builtins (void);
242 static tree sh_media_builtin_decl (unsigned, bool);
243 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
244 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
245 static void sh_file_start (void);
246 static int flow_dependent_p (rtx, rtx);
247 static void flow_dependent_p_1 (rtx, const_rtx, void *);
248 static int shiftcosts (rtx);
249 static int andcosts (rtx);
250 static int addsubcosts (rtx);
251 static int multcosts (rtx);
252 static bool unspec_caller_rtx_p (rtx);
253 static bool sh_cannot_copy_insn_p (rtx);
254 static bool sh_rtx_costs (rtx, int, int, int *, bool);
255 static int sh_address_cost (rtx, bool);
256 static int sh_pr_n_sets (void);
257 static rtx sh_allocate_initial_value (rtx);
258 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
259 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
261 struct secondary_reload_info *);
262 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
263 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
264 static rtx sh_delegitimize_address (rtx);
265 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
266 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
267 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
268 static int scavenge_reg (HARD_REG_SET *s);
269 struct save_schedule_s;
270 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
271 struct save_schedule_s *, int);
273 static rtx sh_struct_value_rtx (tree, int);
274 static rtx sh_function_value (const_tree, const_tree, bool);
275 static bool sh_function_value_regno_p (const unsigned int);
276 static rtx sh_libcall_value (enum machine_mode, const_rtx);
277 static bool sh_return_in_memory (const_tree, const_tree);
278 static rtx sh_builtin_saveregs (void);
279 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
280 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
281 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
282 static tree sh_build_builtin_va_list (void);
283 static void sh_va_start (tree, rtx);
284 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
285 static bool sh_promote_prototypes (const_tree);
286 static enum machine_mode sh_promote_function_mode (const_tree type,
291 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
293 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
295 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
297 static void sh_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
299 static rtx sh_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
301 static bool sh_scalar_mode_supported_p (enum machine_mode);
302 static int sh_dwarf_calling_convention (const_tree);
303 static void sh_encode_section_info (tree, rtx, int);
304 static int sh2a_function_vector_p (tree);
305 static void sh_trampoline_init (rtx, tree, rtx);
306 static rtx sh_trampoline_adjust_address (rtx);
307 static void sh_conditional_register_usage (void);
309 static const struct attribute_spec sh_attribute_table[] =
311 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
312 affects_type_identity } */
313 { "interrupt_handler", 0, 0, true, false, false,
314 sh_handle_interrupt_handler_attribute, false },
315 { "sp_switch", 1, 1, true, false, false,
316 sh_handle_sp_switch_attribute, false },
317 { "trap_exit", 1, 1, true, false, false,
318 sh_handle_trap_exit_attribute, false },
319 { "renesas", 0, 0, false, true, false,
320 sh_handle_renesas_attribute, false },
321 { "trapa_handler", 0, 0, true, false, false,
322 sh_handle_interrupt_handler_attribute, false },
323 { "nosave_low_regs", 0, 0, true, false, false,
324 sh_handle_interrupt_handler_attribute, false },
325 { "resbank", 0, 0, true, false, false,
326 sh_handle_resbank_handler_attribute, false },
327 { "function_vector", 1, 1, true, false, false,
328 sh2a_handle_function_vector_handler_attribute, false },
329 { NULL, 0, 0, false, false, false, NULL, false }
332 /* Set default optimization options. */
333 static const struct default_options sh_option_optimization_table[] =
335 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
336 { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_mdiv_, "inv:minlat", 1 },
337 { OPT_LEVELS_SIZE, OPT_mdiv_, SH_DIV_STR_FOR_SIZE, 1 },
338 { OPT_LEVELS_0_ONLY, OPT_mdiv_, "", 1 },
339 { OPT_LEVELS_SIZE, OPT_mcbranchdi, NULL, 0 },
340 /* We can't meaningfully test TARGET_SHMEDIA here, because -m
341 options haven't been parsed yet, hence we'd read only the
342 default. sh_target_reg_class will return NO_REGS if this is
343 not SHMEDIA, so it's OK to always set
344 flag_branch_target_load_optimize. */
345 { OPT_LEVELS_2_PLUS, OPT_fbranch_target_load_optimize, NULL, 1 },
346 { OPT_LEVELS_NONE, 0, NULL, 0 }
349 /* Initialize the GCC target structure. */
350 #undef TARGET_ATTRIBUTE_TABLE
351 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
353 /* The next two are used for debug info when compiling with -gdwarf. */
354 #undef TARGET_ASM_UNALIGNED_HI_OP
355 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
356 #undef TARGET_ASM_UNALIGNED_SI_OP
357 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
359 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
360 #undef TARGET_ASM_UNALIGNED_DI_OP
361 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
362 #undef TARGET_ASM_ALIGNED_DI_OP
363 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
365 #undef TARGET_OPTION_OVERRIDE
366 #define TARGET_OPTION_OVERRIDE sh_option_override
367 #undef TARGET_OPTION_OPTIMIZATION_TABLE
368 #define TARGET_OPTION_OPTIMIZATION_TABLE sh_option_optimization_table
369 #undef TARGET_OPTION_INIT_STRUCT
370 #define TARGET_OPTION_INIT_STRUCT sh_option_init_struct
371 #undef TARGET_OPTION_DEFAULT_PARAMS
372 #define TARGET_OPTION_DEFAULT_PARAMS sh_option_default_params
374 #undef TARGET_PRINT_OPERAND
375 #define TARGET_PRINT_OPERAND sh_print_operand
376 #undef TARGET_PRINT_OPERAND_ADDRESS
377 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
378 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
379 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
380 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
381 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
383 #undef TARGET_ASM_FUNCTION_EPILOGUE
384 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
386 #undef TARGET_ASM_OUTPUT_MI_THUNK
387 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
389 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
390 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
392 #undef TARGET_ASM_FILE_START
393 #define TARGET_ASM_FILE_START sh_file_start
394 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
395 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
397 #undef TARGET_DEFAULT_TARGET_FLAGS
398 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
399 #undef TARGET_HANDLE_OPTION
400 #define TARGET_HANDLE_OPTION sh_handle_option
402 #undef TARGET_REGISTER_MOVE_COST
403 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
405 #undef TARGET_INSERT_ATTRIBUTES
406 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
408 #undef TARGET_SCHED_ADJUST_COST
409 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
411 #undef TARGET_SCHED_ISSUE_RATE
412 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
414 /* The next 5 hooks have been implemented for reenabling sched1. With the
415 help of these macros we are limiting the movement of insns in sched1 to
416 reduce the register pressure. The overall idea is to keep count of SImode
417 and SFmode regs required by already scheduled insns. When these counts
418 cross some threshold values; give priority to insns that free registers.
419 The insn that frees registers is most likely to be the insn with lowest
420 LUID (original insn order); but such an insn might be there in the stalled
421 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
422 upto a max of 8 cycles so that such insns may move from Q -> R.
424 The description of the hooks are as below:
426 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
427 scheduler; it is called inside the sched_init function just after
428 find_insn_reg_weights function call. It is used to calculate the SImode
429 and SFmode weights of insns of basic blocks; much similar to what
430 find_insn_reg_weights does.
431 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
433 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
434 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
437 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
438 high; reorder the ready queue so that the insn with lowest LUID will be
441 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
442 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
444 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
445 can be returned from TARGET_SCHED_REORDER2.
447 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
449 #undef TARGET_SCHED_DFA_NEW_CYCLE
450 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
452 #undef TARGET_SCHED_INIT_GLOBAL
453 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
455 #undef TARGET_SCHED_FINISH_GLOBAL
456 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
458 #undef TARGET_SCHED_VARIABLE_ISSUE
459 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
461 #undef TARGET_SCHED_REORDER
462 #define TARGET_SCHED_REORDER sh_reorder
464 #undef TARGET_SCHED_REORDER2
465 #define TARGET_SCHED_REORDER2 sh_reorder2
467 #undef TARGET_SCHED_INIT
468 #define TARGET_SCHED_INIT sh_md_init
470 #undef TARGET_DELEGITIMIZE_ADDRESS
471 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
473 #undef TARGET_LEGITIMIZE_ADDRESS
474 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
476 #undef TARGET_CANNOT_MODIFY_JUMPS_P
477 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
478 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
479 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
480 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
481 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
482 sh_optimize_target_register_callee_saved
484 #undef TARGET_MS_BITFIELD_LAYOUT_P
485 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
487 #undef TARGET_INIT_BUILTINS
488 #define TARGET_INIT_BUILTINS sh_init_builtins
489 #undef TARGET_BUILTIN_DECL
490 #define TARGET_BUILTIN_DECL sh_builtin_decl
491 #undef TARGET_EXPAND_BUILTIN
492 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
494 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
495 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
497 #undef TARGET_CANNOT_COPY_INSN_P
498 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
499 #undef TARGET_RTX_COSTS
500 #define TARGET_RTX_COSTS sh_rtx_costs
501 #undef TARGET_ADDRESS_COST
502 #define TARGET_ADDRESS_COST sh_address_cost
503 #undef TARGET_ALLOCATE_INITIAL_VALUE
504 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
506 #undef TARGET_MACHINE_DEPENDENT_REORG
507 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
509 #undef TARGET_DWARF_REGISTER_SPAN
510 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
513 #undef TARGET_HAVE_TLS
514 #define TARGET_HAVE_TLS true
517 #undef TARGET_PROMOTE_PROTOTYPES
518 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
519 #undef TARGET_PROMOTE_FUNCTION_MODE
520 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
522 #undef TARGET_FUNCTION_VALUE
523 #define TARGET_FUNCTION_VALUE sh_function_value
524 #undef TARGET_FUNCTION_VALUE_REGNO_P
525 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
526 #undef TARGET_LIBCALL_VALUE
527 #define TARGET_LIBCALL_VALUE sh_libcall_value
528 #undef TARGET_STRUCT_VALUE_RTX
529 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
530 #undef TARGET_RETURN_IN_MEMORY
531 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
533 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
534 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
535 #undef TARGET_SETUP_INCOMING_VARARGS
536 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
537 #undef TARGET_STRICT_ARGUMENT_NAMING
538 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
539 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
540 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
541 #undef TARGET_MUST_PASS_IN_STACK
542 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
543 #undef TARGET_PASS_BY_REFERENCE
544 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
545 #undef TARGET_CALLEE_COPIES
546 #define TARGET_CALLEE_COPIES sh_callee_copies
547 #undef TARGET_ARG_PARTIAL_BYTES
548 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
549 #undef TARGET_FUNCTION_ARG
550 #define TARGET_FUNCTION_ARG sh_function_arg
551 #undef TARGET_FUNCTION_ARG_ADVANCE
552 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
554 #undef TARGET_BUILD_BUILTIN_VA_LIST
555 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
556 #undef TARGET_EXPAND_BUILTIN_VA_START
557 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
558 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
559 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
561 #undef TARGET_SCALAR_MODE_SUPPORTED_P
562 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
563 #undef TARGET_VECTOR_MODE_SUPPORTED_P
564 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
566 #undef TARGET_CHECK_PCH_TARGET_FLAGS
567 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
569 #undef TARGET_DWARF_CALLING_CONVENTION
570 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
572 #undef TARGET_FRAME_POINTER_REQUIRED
573 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
575 /* Return regmode weight for insn. */
576 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
578 /* Return current register pressure for regmode. */
579 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
581 #undef TARGET_ENCODE_SECTION_INFO
582 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
584 #undef TARGET_SECONDARY_RELOAD
585 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
587 #undef TARGET_PREFERRED_RELOAD_CLASS
588 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
590 #undef TARGET_CONDITIONAL_REGISTER_USAGE
591 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
593 #undef TARGET_LEGITIMATE_ADDRESS_P
594 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
596 #undef TARGET_TRAMPOLINE_INIT
597 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
598 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
599 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
601 /* Machine-specific symbol_ref flags. */
602 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
604 struct gcc_target targetm = TARGET_INITIALIZER;
606 /* Implement TARGET_HANDLE_OPTION. */
609 sh_handle_option (struct gcc_options *opts,
610 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
611 const struct cl_decoded_option *decoded,
612 location_t loc ATTRIBUTE_UNUSED)
614 size_t code = decoded->opt_index;
619 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH1;
623 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2;
627 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2A;
632 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
637 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
640 case OPT_m2a_single_only:
642 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
646 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH2E;
650 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH3;
654 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH3E;
661 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4;
665 case OPT_m4_100_nofpu:
666 case OPT_m4_200_nofpu:
667 case OPT_m4_300_nofpu:
672 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
676 case OPT_m4_100_single:
677 case OPT_m4_200_single:
678 case OPT_m4_300_single:
680 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
683 case OPT_m4_single_only:
684 case OPT_m4_100_single_only:
685 case OPT_m4_200_single_only:
686 case OPT_m4_300_single_only:
688 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
692 opts->x_target_flags = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4A;
698 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
703 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
706 case OPT_m4a_single_only:
708 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
713 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
716 case OPT_m5_32media_nofpu:
718 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
723 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
726 case OPT_m5_64media_nofpu:
728 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
733 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
736 case OPT_m5_compact_nofpu:
738 = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
746 /* Implement TARGET_OPTION_INIT_STRUCT. */
748 sh_option_init_struct (struct gcc_options *opts)
750 /* We can't meaningfully test TARGET_SH2E / TARGET_IEEE
751 here, so leave it to TARGET_OPTION_OVERRIDE to set
752 flag_finite_math_only. We set it to 2 here so we know if the user
753 explicitly requested this to be on or off. */
754 opts->x_flag_finite_math_only = 2;
757 /* Implement TARGET_OPTION_DEFAULT_PARAMS. */
759 sh_option_default_params (void)
761 set_default_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 2);
764 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
765 various options, and do some machine dependent initialization. */
767 sh_option_override (void)
771 SUBTARGET_OVERRIDE_OPTIONS;
772 if (optimize > 1 && !optimize_size)
773 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
774 if (flag_finite_math_only == 2)
775 flag_finite_math_only
776 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
777 if (TARGET_SH2E && !flag_finite_math_only)
778 target_flags |= MASK_IEEE;
779 sh_cpu = PROCESSOR_SH1;
780 assembler_dialect = 0;
782 sh_cpu = PROCESSOR_SH2;
784 sh_cpu = PROCESSOR_SH2E;
786 sh_cpu = PROCESSOR_SH2A;
788 sh_cpu = PROCESSOR_SH3;
790 sh_cpu = PROCESSOR_SH3E;
793 assembler_dialect = 1;
794 sh_cpu = PROCESSOR_SH4;
796 if (TARGET_SH4A_ARCH)
798 assembler_dialect = 1;
799 sh_cpu = PROCESSOR_SH4A;
803 sh_cpu = PROCESSOR_SH5;
804 target_flags |= MASK_ALIGN_DOUBLE;
805 if (TARGET_SHMEDIA_FPU)
806 target_flags |= MASK_FMOVD;
809 /* There are no delay slots on SHmedia. */
810 flag_delayed_branch = 0;
811 /* Relaxation isn't yet supported for SHmedia */
812 target_flags &= ~MASK_RELAX;
813 /* After reload, if conversion does little good but can cause
815 - find_if_block doesn't do anything for SH because we don't
816 have conditional execution patterns. (We use conditional
817 move patterns, which are handled differently, and only
819 - find_cond_trap doesn't do anything for the SH because we
820 don't have conditional traps.
821 - find_if_case_1 uses redirect_edge_and_branch_force in
822 the only path that does an optimization, and this causes
823 an ICE when branch targets are in registers.
824 - find_if_case_2 doesn't do anything for the SHmedia after
825 reload except when it can redirect a tablejump - and
826 that's rather rare. */
827 flag_if_conversion2 = 0;
828 if (! strcmp (sh_div_str, "call"))
829 sh_div_strategy = SH_DIV_CALL;
830 else if (! strcmp (sh_div_str, "call2"))
831 sh_div_strategy = SH_DIV_CALL2;
832 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
833 sh_div_strategy = SH_DIV_FP;
834 else if (! strcmp (sh_div_str, "inv"))
835 sh_div_strategy = SH_DIV_INV;
836 else if (! strcmp (sh_div_str, "inv:minlat"))
837 sh_div_strategy = SH_DIV_INV_MINLAT;
838 else if (! strcmp (sh_div_str, "inv20u"))
839 sh_div_strategy = SH_DIV_INV20U;
840 else if (! strcmp (sh_div_str, "inv20l"))
841 sh_div_strategy = SH_DIV_INV20L;
842 else if (! strcmp (sh_div_str, "inv:call2"))
843 sh_div_strategy = SH_DIV_INV_CALL2;
844 else if (! strcmp (sh_div_str, "inv:call"))
845 sh_div_strategy = SH_DIV_INV_CALL;
846 else if (! strcmp (sh_div_str, "inv:fp"))
849 sh_div_strategy = SH_DIV_INV_FP;
851 sh_div_strategy = SH_DIV_INV;
853 TARGET_CBRANCHDI4 = 0;
854 /* Assembler CFI isn't yet fully supported for SHmedia. */
855 flag_dwarf2_cfi_asm = 0;
860 /* Only the sh64-elf assembler fully supports .quad properly. */
861 targetm.asm_out.aligned_op.di = NULL;
862 targetm.asm_out.unaligned_op.di = NULL;
866 if (! strcmp (sh_div_str, "call-div1"))
867 sh_div_strategy = SH_DIV_CALL_DIV1;
868 else if (! strcmp (sh_div_str, "call-fp")
869 && (TARGET_FPU_DOUBLE
870 || (TARGET_HARD_SH4 && TARGET_SH2E)
871 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
872 sh_div_strategy = SH_DIV_CALL_FP;
873 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
874 sh_div_strategy = SH_DIV_CALL_TABLE;
876 /* Pick one that makes most sense for the target in general.
877 It is not much good to use different functions depending
878 on -Os, since then we'll end up with two different functions
879 when some of the code is compiled for size, and some for
882 /* SH4 tends to emphasize speed. */
884 sh_div_strategy = SH_DIV_CALL_TABLE;
885 /* These have their own way of doing things. */
886 else if (TARGET_SH2A)
887 sh_div_strategy = SH_DIV_INTRINSIC;
888 /* ??? Should we use the integer SHmedia function instead? */
889 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
890 sh_div_strategy = SH_DIV_CALL_FP;
891 /* SH1 .. SH3 cores often go into small-footprint systems, so
892 default to the smallest implementation available. */
893 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
894 sh_div_strategy = SH_DIV_CALL_TABLE;
896 sh_div_strategy = SH_DIV_CALL_DIV1;
899 TARGET_PRETEND_CMOVE = 0;
900 if (sh_divsi3_libfunc[0])
901 ; /* User supplied - leave it alone. */
902 else if (TARGET_DIVIDE_CALL_FP)
903 sh_divsi3_libfunc = "__sdivsi3_i4";
904 else if (TARGET_DIVIDE_CALL_TABLE)
905 sh_divsi3_libfunc = "__sdivsi3_i4i";
907 sh_divsi3_libfunc = "__sdivsi3_1";
909 sh_divsi3_libfunc = "__sdivsi3";
910 if (sh_branch_cost == -1)
912 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
914 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
915 if (! VALID_REGISTER_P (regno))
916 sh_register_names[regno][0] = '\0';
918 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
919 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
920 sh_additional_register_names[regno][0] = '\0';
922 flag_omit_frame_pointer = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
924 if ((flag_pic && ! TARGET_PREFERGOT)
925 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
926 flag_no_function_cse = 1;
928 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
930 /* Never run scheduling before reload, since that can
931 break global alloc, and generates slower code anyway due
932 to the pressure on R0. */
933 /* Enable sched1 for SH4 if the user explicitly requests.
934 When sched1 is enabled, the ready queue will be reordered by
935 the target hooks if pressure is high. We can not do this for
936 PIC, SH3 and lower as they give spill failures for R0. */
937 if (!TARGET_HARD_SH4 || flag_pic)
938 flag_schedule_insns = 0;
939 /* ??? Current exception handling places basic block boundaries
940 after call_insns. It causes the high pressure on R0 and gives
941 spill failures for R0 in reload. See PR 22553 and the thread
943 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
944 else if (flag_exceptions)
946 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
947 warning (0, "ignoring -fschedule-insns because of exception handling bug");
948 flag_schedule_insns = 0;
950 else if (flag_schedule_insns
951 && !global_options_set.x_flag_schedule_insns)
952 flag_schedule_insns = 0;
955 if ((target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) == 0)
956 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
958 /* Unwind info is not correct around the CFG unless either a frame
959 pointer is present or M_A_O_A is set. Fixing this requires rewriting
960 unwind info generation to be aware of the CFG and propagating states
962 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
963 || flag_exceptions || flag_non_call_exceptions)
964 && flag_omit_frame_pointer
965 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
967 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
968 warning (0, "unwind tables currently require either a frame pointer "
969 "or -maccumulate-outgoing-args for correctness");
970 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
973 /* Unwinding with -freorder-blocks-and-partition does not work on this
974 architecture, because it requires far jumps to label crossing between
975 hot/cold sections which are rejected on this architecture. */
976 if (flag_reorder_blocks_and_partition)
980 inform (input_location,
981 "-freorder-blocks-and-partition does not work with "
982 "exceptions on this architecture");
983 flag_reorder_blocks_and_partition = 0;
984 flag_reorder_blocks = 1;
986 else if (flag_unwind_tables)
988 inform (input_location,
989 "-freorder-blocks-and-partition does not support unwind "
990 "info on this architecture");
991 flag_reorder_blocks_and_partition = 0;
992 flag_reorder_blocks = 1;
996 if (align_loops == 0)
997 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
998 if (align_jumps == 0)
999 align_jumps = 1 << CACHE_LOG;
1000 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
1001 align_jumps = TARGET_SHMEDIA ? 4 : 2;
1003 /* Allocation boundary (in *bytes*) for the code of a function.
1004 SH1: 32 bit alignment is faster, because instructions are always
1005 fetched as a pair from a longword boundary.
1006 SH2 .. SH5 : align to cache line start. */
1007 if (align_functions == 0)
1009 = optimize_size ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
1010 /* The linker relaxation code breaks when a function contains
1011 alignments that are larger than that at the start of a
1012 compilation unit. */
1016 = align_loops > align_jumps ? align_loops : align_jumps;
1018 /* Also take possible .long constants / mova tables int account. */
1021 if (align_functions < min_align)
1022 align_functions = min_align;
1025 if (sh_fixed_range_str)
1026 sh_fix_range (sh_fixed_range_str);
1028 /* This target defaults to strict volatile bitfields. */
1029 if (flag_strict_volatile_bitfields < 0)
1030 flag_strict_volatile_bitfields = 1;
1033 /* Print the operand address in x to the stream. */
1036 sh_print_operand_address (FILE *stream, rtx x)
1038 switch (GET_CODE (x))
1042 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
1047 rtx base = XEXP (x, 0);
1048 rtx index = XEXP (x, 1);
1050 switch (GET_CODE (index))
1053 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
1054 reg_names[true_regnum (base)]);
1060 int base_num = true_regnum (base);
1061 int index_num = true_regnum (index);
1063 fprintf (stream, "@(r0,%s)",
1064 reg_names[MAX (base_num, index_num)]);
1075 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
1079 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
1083 x = mark_constant_pool_use (x);
1084 output_addr_const (stream, x);
1089 /* Print operand x (an rtx) in assembler syntax to file stream
1090 according to modifier code.
1092 '.' print a .s if insn needs delay slot
1093 ',' print LOCAL_LABEL_PREFIX
1094 '@' print trap, rte or rts depending upon pragma interruptness
1095 '#' output a nop if there is nothing to put in the delay slot
1096 ''' print likelihood suffix (/u for unlikely).
1097 '>' print branch target if -fverbose-asm
1098 'O' print a constant without the #
1099 'R' print the LSW of a dp value - changes if in little endian
1100 'S' print the MSW of a dp value - changes if in little endian
1101 'T' print the next word of a dp value - same as 'R' in big endian mode.
1102 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1103 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1104 'N' print 'r63' if the operand is (const_int 0).
1105 'd' print a V2SF reg as dN instead of fpN.
1106 'm' print a pair `base,offset' or `base,index', for LD and ST.
1107 'U' Likewise for {LD,ST}{HI,LO}.
1108 'V' print the position of a single bit set.
1109 'W' print the position of a single bit cleared.
1110 't' print a memory address which is a register.
1111 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1112 'o' output an operator. */
1115 sh_print_operand (FILE *stream, rtx x, int code)
1118 enum machine_mode mode;
1126 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1127 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1128 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1131 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1134 trapa_attr = lookup_attribute ("trap_exit",
1135 DECL_ATTRIBUTES (current_function_decl));
1137 fprintf (stream, "trapa #%ld",
1138 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1139 else if (sh_cfun_interrupt_handler_p ())
1141 if (sh_cfun_resbank_handler_p ())
1142 fprintf (stream, "resbank\n");
1143 fprintf (stream, "rte");
1146 fprintf (stream, "rts");
1149 /* Output a nop if there's nothing in the delay slot. */
1150 if (dbr_sequence_length () == 0)
1151 fprintf (stream, "\n\tnop");
1155 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1157 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1158 fputs ("/u", stream);
1162 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1164 fputs ("\t! target: ", stream);
1165 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1169 x = mark_constant_pool_use (x);
1170 output_addr_const (stream, x);
1172 /* N.B.: %R / %S / %T adjust memory addresses by four.
1173 For SHMEDIA, that means they can be used to access the first and
1174 second 32 bit part of a 64 bit (or larger) value that
1175 might be held in floating point registers or memory.
1176 While they can be used to access 64 bit parts of a larger value
1177 held in general purpose registers, that won't work with memory -
1178 neither for fp registers, since the frxx names are used. */
1180 if (REG_P (x) || GET_CODE (x) == SUBREG)
1182 regno = true_regnum (x);
1183 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1184 fputs (reg_names[regno], (stream));
1188 x = adjust_address (x, SImode, 4 * LSW);
1189 sh_print_operand_address (stream, XEXP (x, 0));
1195 mode = GET_MODE (x);
1196 if (mode == VOIDmode)
1198 if (GET_MODE_SIZE (mode) >= 8)
1199 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1201 sh_print_operand (stream, sub, 0);
1203 output_operand_lossage ("invalid operand to %%R");
1207 if (REG_P (x) || GET_CODE (x) == SUBREG)
1209 regno = true_regnum (x);
1210 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1211 fputs (reg_names[regno], (stream));
1215 x = adjust_address (x, SImode, 4 * MSW);
1216 sh_print_operand_address (stream, XEXP (x, 0));
1222 mode = GET_MODE (x);
1223 if (mode == VOIDmode)
1225 if (GET_MODE_SIZE (mode) >= 8)
1226 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1228 sh_print_operand (stream, sub, 0);
1230 output_operand_lossage ("invalid operand to %%S");
1234 /* Next word of a double. */
1235 switch (GET_CODE (x))
1238 fputs (reg_names[REGNO (x) + 1], (stream));
1241 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1242 && GET_CODE (XEXP (x, 0)) != POST_INC)
1243 x = adjust_address (x, SImode, 4);
1244 sh_print_operand_address (stream, XEXP (x, 0));
1252 gcc_assert (MEM_P (x));
1254 switch (GET_CODE (x))
1258 sh_print_operand (stream, x, 0);
1266 switch (GET_CODE (x))
1268 case PLUS: fputs ("add", stream); break;
1269 case MINUS: fputs ("sub", stream); break;
1270 case MULT: fputs ("mul", stream); break;
1271 case DIV: fputs ("div", stream); break;
1272 case EQ: fputs ("eq", stream); break;
1273 case NE: fputs ("ne", stream); break;
1274 case GT: case LT: fputs ("gt", stream); break;
1275 case GE: case LE: fputs ("ge", stream); break;
1276 case GTU: case LTU: fputs ("gtu", stream); break;
1277 case GEU: case LEU: fputs ("geu", stream); break;
1286 && GET_CODE (XEXP (x, 0)) == PLUS
1287 && (REG_P (XEXP (XEXP (x, 0), 1))
1288 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1289 fputc ('x', stream);
1295 switch (GET_MODE (x))
1297 case QImode: fputs (".b", stream); break;
1298 case HImode: fputs (".w", stream); break;
1299 case SImode: fputs (".l", stream); break;
1300 case SFmode: fputs (".s", stream); break;
1301 case DFmode: fputs (".d", stream); break;
1302 default: gcc_unreachable ();
1309 gcc_assert (MEM_P (x));
1313 switch (GET_CODE (x))
1317 sh_print_operand (stream, x, 0);
1318 fputs (", 0", stream);
1322 sh_print_operand (stream, XEXP (x, 0), 0);
1323 fputs (", ", stream);
1324 sh_print_operand (stream, XEXP (x, 1), 0);
1334 int num = exact_log2 (INTVAL (x));
1335 gcc_assert (num >= 0);
1336 fprintf (stream, "#%d", num);
1342 int num = exact_log2 (~INTVAL (x));
1343 gcc_assert (num >= 0);
1344 fprintf (stream, "#%d", num);
1349 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1351 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1355 if (x == CONST0_RTX (GET_MODE (x)))
1357 fprintf ((stream), "r63");
1360 goto default_output;
1362 if (CONST_INT_P (x))
1364 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1372 mode = GET_MODE (x);
1374 switch (GET_CODE (x))
1378 rtx inner = XEXP (x, 0);
1380 enum machine_mode inner_mode;
1382 /* We might see SUBREGs with vector mode registers inside. */
1383 if (GET_CODE (inner) == SUBREG
1384 && (GET_MODE_SIZE (GET_MODE (inner))
1385 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1386 && subreg_lowpart_p (inner))
1387 inner = SUBREG_REG (inner);
1388 if (CONST_INT_P (inner))
1390 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1391 goto default_output;
1393 inner_mode = GET_MODE (inner);
1394 if (GET_CODE (inner) == SUBREG
1395 && (GET_MODE_SIZE (GET_MODE (inner))
1396 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1397 && REG_P (SUBREG_REG (inner)))
1399 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1400 GET_MODE (SUBREG_REG (inner)),
1401 SUBREG_BYTE (inner),
1403 inner = SUBREG_REG (inner);
1405 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1407 /* Floating point register pairs are always big endian;
1408 general purpose registers are 64 bit wide. */
1409 regno = REGNO (inner);
1410 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1411 - HARD_REGNO_NREGS (regno, mode))
1419 /* FIXME: We need this on SHmedia32 because reload generates
1420 some sign-extended HI or QI loads into DImode registers
1421 but, because Pmode is SImode, the address ends up with a
1422 subreg:SI of the DImode register. Maybe reload should be
1423 fixed so as to apply alter_subreg to such loads? */
1425 gcc_assert (trapping_target_operand (x, VOIDmode));
1426 x = XEXP (XEXP (x, 2), 0);
1427 goto default_output;
1429 gcc_assert (SUBREG_BYTE (x) == 0
1430 && REG_P (SUBREG_REG (x)));
1438 if (FP_REGISTER_P (regno)
1439 && mode == V16SFmode)
1440 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1441 else if (FP_REGISTER_P (REGNO (x))
1442 && mode == V4SFmode)
1443 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1445 && mode == V2SFmode)
1446 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1447 else if (FP_REGISTER_P (REGNO (x))
1448 && GET_MODE_SIZE (mode) > 4)
1449 fprintf ((stream), "d%s", reg_names[regno] + 1);
1451 fputs (reg_names[regno], (stream));
1455 output_address (XEXP (x, 0));
1460 fputc ('#', stream);
1461 output_addr_const (stream, x);
1469 sh_print_operand_punct_valid_p (unsigned char code)
1471 return (code == '.' || code == '#' || code == '@' || code == ','
1472 || code == '$' || code == '\'' || code == '>');
1475 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1478 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1480 if (GET_CODE (x) == UNSPEC)
1482 switch (XINT (x, 1))
1484 case UNSPEC_DATALABEL:
1485 fputs ("datalabel ", file);
1486 output_addr_const (file, XVECEXP (x, 0, 0));
1489 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1490 output_addr_const (file, XVECEXP (x, 0, 0));
1493 output_addr_const (file, XVECEXP (x, 0, 0));
1494 fputs ("@GOT", file);
1497 output_addr_const (file, XVECEXP (x, 0, 0));
1498 fputs ("@GOTOFF", file);
1501 output_addr_const (file, XVECEXP (x, 0, 0));
1502 fputs ("@PLT", file);
1505 output_addr_const (file, XVECEXP (x, 0, 0));
1506 fputs ("@GOTPLT", file);
1509 output_addr_const (file, XVECEXP (x, 0, 0));
1510 fputs ("@DTPOFF", file);
1512 case UNSPEC_GOTTPOFF:
1513 output_addr_const (file, XVECEXP (x, 0, 0));
1514 fputs ("@GOTTPOFF", file);
1517 output_addr_const (file, XVECEXP (x, 0, 0));
1518 fputs ("@TPOFF", file);
1523 /* LPCS stands for Label for PIC Call Site. */
1524 targetm.asm_out.generate_internal_label (name, "LPCS",
1525 INTVAL (XVECEXP (x, 0, 0)));
1526 assemble_name (file, name);
1529 case UNSPEC_EXTRACT_S16:
1530 case UNSPEC_EXTRACT_U16:
1534 val = XVECEXP (x, 0, 0);
1535 shift = XVECEXP (x, 0, 1);
1537 if (shift != const0_rtx)
1539 if (GET_CODE (val) == CONST
1540 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
1543 output_addr_const (file, val);
1547 output_addr_const (file, val);
1548 if (shift != const0_rtx)
1550 fputs (" >> ", file);
1551 output_addr_const (file, shift);
1554 fputs (" & 65535)", file);
1558 output_addr_const (file, XVECEXP (x, 0, 0));
1560 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1563 output_addr_const (file, XVECEXP (x, 0, 1));
1567 output_addr_const (file, XVECEXP (x, 0, 1));
1569 case UNSPEC_PCREL_SYMOFF:
1570 output_addr_const (file, XVECEXP (x, 0, 0));
1572 output_addr_const (file, XVECEXP (x, 0, 1));
1573 fputs ("-.)", file);
1585 /* Encode symbol attributes of a SYMBOL_REF into its
1586 SYMBOL_REF_FLAGS. */
1588 sh_encode_section_info (tree decl, rtx rtl, int first)
1590 default_encode_section_info (decl, rtl, first);
1592 if (TREE_CODE (decl) == FUNCTION_DECL
1593 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1594 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1597 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1599 force_into (rtx value, rtx target)
1601 value = force_operand (value, target);
1602 if (! rtx_equal_p (value, target))
1603 emit_insn (gen_move_insn (target, value));
1606 /* Emit code to perform a block move. Choose the best method.
1608 OPERANDS[0] is the destination.
1609 OPERANDS[1] is the source.
1610 OPERANDS[2] is the size.
1611 OPERANDS[3] is the alignment safe to use. */
1614 expand_block_move (rtx *operands)
1616 int align = INTVAL (operands[3]);
1617 int constp = (CONST_INT_P (operands[2]));
1618 int bytes = (constp ? INTVAL (operands[2]) : 0);
1623 /* If we could use mov.l to move words and dest is word-aligned, we
1624 can use movua.l for loads and still generate a relatively short
1625 and efficient sequence. */
1626 if (TARGET_SH4A_ARCH && align < 4
1627 && MEM_ALIGN (operands[0]) >= 32
1628 && can_move_by_pieces (bytes, 32))
1630 rtx dest = copy_rtx (operands[0]);
1631 rtx src = copy_rtx (operands[1]);
1632 /* We could use different pseudos for each copied word, but
1633 since movua can only load into r0, it's kind of
1635 rtx temp = gen_reg_rtx (SImode);
1636 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1639 while (copied + 4 <= bytes)
1641 rtx to = adjust_address (dest, SImode, copied);
1642 rtx from = adjust_automodify_address (src, BLKmode,
1645 set_mem_size (from, GEN_INT (4));
1646 emit_insn (gen_movua (temp, from));
1647 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1648 emit_move_insn (to, temp);
1653 move_by_pieces (adjust_address (dest, BLKmode, copied),
1654 adjust_automodify_address (src, BLKmode,
1656 bytes - copied, align, 0);
1661 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1662 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1663 if (align < 4 || (bytes % 4 != 0))
1666 if (TARGET_HARD_SH4)
1670 else if (bytes == 12)
1672 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1673 rtx r4 = gen_rtx_REG (SImode, 4);
1674 rtx r5 = gen_rtx_REG (SImode, 5);
1676 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1677 force_into (XEXP (operands[0], 0), r4);
1678 force_into (XEXP (operands[1], 0), r5);
1679 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1682 else if (! optimize_size)
1684 const char *entry_name;
1685 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1687 rtx r4 = gen_rtx_REG (SImode, 4);
1688 rtx r5 = gen_rtx_REG (SImode, 5);
1689 rtx r6 = gen_rtx_REG (SImode, 6);
1691 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1692 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1693 force_into (XEXP (operands[0], 0), r4);
1694 force_into (XEXP (operands[1], 0), r5);
1696 dwords = bytes >> 3;
1697 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1698 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1707 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1708 rtx r4 = gen_rtx_REG (SImode, 4);
1709 rtx r5 = gen_rtx_REG (SImode, 5);
1711 sprintf (entry, "__movmemSI%d", bytes);
1712 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1713 force_into (XEXP (operands[0], 0), r4);
1714 force_into (XEXP (operands[1], 0), r5);
1715 emit_insn (gen_block_move_real (func_addr_rtx));
1719 /* This is the same number of bytes as a memcpy call, but to a different
1720 less common function name, so this will occasionally use more space. */
1721 if (! optimize_size)
1723 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1724 int final_switch, while_loop;
1725 rtx r4 = gen_rtx_REG (SImode, 4);
1726 rtx r5 = gen_rtx_REG (SImode, 5);
1727 rtx r6 = gen_rtx_REG (SImode, 6);
1729 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1730 force_into (XEXP (operands[0], 0), r4);
1731 force_into (XEXP (operands[1], 0), r5);
1733 /* r6 controls the size of the move. 16 is decremented from it
1734 for each 64 bytes moved. Then the negative bit left over is used
1735 as an index into a list of move instructions. e.g., a 72 byte move
1736 would be set up with size(r6) = 14, for one iteration through the
1737 big while loop, and a switch of -2 for the last part. */
1739 final_switch = 16 - ((bytes / 4) % 16);
1740 while_loop = ((bytes / 4) / 16 - 1) * 16;
1741 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1742 emit_insn (gen_block_lump_real (func_addr_rtx));
1749 /* Prepare operands for a move define_expand; specifically, one of the
1750 operands must be in a register. */
1753 prepare_move_operands (rtx operands[], enum machine_mode mode)
1755 if ((mode == SImode || mode == DImode)
1757 && ! ((mode == Pmode || mode == ptr_mode)
1758 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1761 if (SYMBOLIC_CONST_P (operands[1]))
1763 if (MEM_P (operands[0]))
1764 operands[1] = force_reg (Pmode, operands[1]);
1765 else if (TARGET_SHMEDIA
1766 && GET_CODE (operands[1]) == LABEL_REF
1767 && target_reg_operand (operands[0], mode))
1771 temp = (!can_create_pseudo_p ()
1773 : gen_reg_rtx (Pmode));
1774 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1777 else if (GET_CODE (operands[1]) == CONST
1778 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1779 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1781 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1782 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1784 operands[1] = expand_binop (mode, add_optab, temp,
1785 XEXP (XEXP (operands[1], 0), 1),
1786 (!can_create_pseudo_p ()
1788 : gen_reg_rtx (Pmode)),
1789 0, OPTAB_LIB_WIDEN);
1793 if (! reload_in_progress && ! reload_completed)
1795 /* Copy the source to a register if both operands aren't registers. */
1796 if (! register_operand (operands[0], mode)
1797 && ! sh_register_operand (operands[1], mode))
1798 operands[1] = copy_to_mode_reg (mode, operands[1]);
1800 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1802 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1803 except that we can't use that function because it is static. */
1804 rtx new_rtx = change_address (operands[0], mode, 0);
1805 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1806 operands[0] = new_rtx;
1809 /* This case can happen while generating code to move the result
1810 of a library call to the target. Reject `st r0,@(rX,rY)' because
1811 reload will fail to find a spill register for rX, since r0 is already
1812 being used for the source. */
1814 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1815 && MEM_P (operands[0])
1816 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1817 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1818 operands[1] = copy_to_mode_reg (mode, operands[1]);
1821 if (mode == Pmode || mode == ptr_mode)
1824 enum tls_model tls_kind;
1828 if (GET_CODE (op1) == CONST
1829 && GET_CODE (XEXP (op1, 0)) == PLUS
1830 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1833 opc = XEXP (XEXP (op1, 0), 1);
1834 op1 = XEXP (XEXP (op1, 0), 0);
1839 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1841 rtx tga_op1, tga_ret, tmp, tmp2;
1845 case TLS_MODEL_GLOBAL_DYNAMIC:
1846 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1847 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1851 case TLS_MODEL_LOCAL_DYNAMIC:
1852 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1853 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1855 tmp = gen_reg_rtx (Pmode);
1856 emit_move_insn (tmp, tga_ret);
1858 if (register_operand (op0, Pmode))
1861 tmp2 = gen_reg_rtx (Pmode);
1863 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1867 case TLS_MODEL_INITIAL_EXEC:
1870 /* Don't schedule insns for getting GOT address when
1871 the first scheduling is enabled, to avoid spill
1873 if (flag_schedule_insns)
1874 emit_insn (gen_blockage ());
1875 emit_insn (gen_GOTaddr2picreg ());
1876 emit_use (gen_rtx_REG (SImode, PIC_REG));
1877 if (flag_schedule_insns)
1878 emit_insn (gen_blockage ());
1880 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1881 tmp = gen_sym2GOTTPOFF (op1);
1882 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1886 case TLS_MODEL_LOCAL_EXEC:
1887 tmp2 = gen_reg_rtx (Pmode);
1888 emit_insn (gen_load_gbr (tmp2));
1889 tmp = gen_reg_rtx (Pmode);
1890 emit_insn (gen_symTPOFF2reg (tmp, op1));
1892 if (register_operand (op0, Pmode))
1895 op1 = gen_reg_rtx (Pmode);
1897 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1904 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1913 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1914 enum rtx_code comparison)
1917 rtx scratch = NULL_RTX;
1919 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1920 comparison = GET_CODE (operands[0]);
1922 scratch = operands[4];
1923 if (CONST_INT_P (operands[1])
1924 && !CONST_INT_P (operands[2]))
1926 rtx tmp = operands[1];
1928 operands[1] = operands[2];
1930 comparison = swap_condition (comparison);
1932 if (CONST_INT_P (operands[2]))
1934 HOST_WIDE_INT val = INTVAL (operands[2]);
1935 if ((val == -1 || val == -0x81)
1936 && (comparison == GT || comparison == LE))
1938 comparison = (comparison == GT) ? GE : LT;
1939 operands[2] = gen_int_mode (val + 1, mode);
1941 else if ((val == 1 || val == 0x80)
1942 && (comparison == GE || comparison == LT))
1944 comparison = (comparison == GE) ? GT : LE;
1945 operands[2] = gen_int_mode (val - 1, mode);
1947 else if (val == 1 && (comparison == GEU || comparison == LTU))
1949 comparison = (comparison == GEU) ? NE : EQ;
1950 operands[2] = CONST0_RTX (mode);
1952 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1954 comparison = (comparison == GEU) ? GTU : LEU;
1955 operands[2] = gen_int_mode (val - 1, mode);
1957 else if (val == 0 && (comparison == GTU || comparison == LEU))
1958 comparison = (comparison == GTU) ? NE : EQ;
1959 else if (mode == SImode
1960 && ((val == 0x7fffffff
1961 && (comparison == GTU || comparison == LEU))
1962 || ((unsigned HOST_WIDE_INT) val
1963 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1964 && (comparison == GEU || comparison == LTU))))
1966 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1967 operands[2] = CONST0_RTX (mode);
1971 if (can_create_pseudo_p ())
1972 operands[1] = force_reg (mode, op1);
1973 /* When we are handling DImode comparisons, we want to keep constants so
1974 that we can optimize the component comparisons; however, memory loads
1975 are better issued as a whole so that they can be scheduled well.
1976 SImode equality comparisons allow I08 constants, but only when they
1977 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1978 into a register, that register might as well be r0, and we allow the
1979 constant. If it is already in a register, this is likely to be
1980 allocated to a different hard register, thus we load the constant into
1981 a register unless it is zero. */
1982 if (!REG_P (operands[2])
1983 && (!CONST_INT_P (operands[2])
1984 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1985 && ((comparison != EQ && comparison != NE)
1986 || (REG_P (op1) && REGNO (op1) != R0_REG)
1987 || !satisfies_constraint_I08 (operands[2])))))
1989 if (scratch && GET_MODE (scratch) == mode)
1991 emit_move_insn (scratch, operands[2]);
1992 operands[2] = scratch;
1994 else if (can_create_pseudo_p ())
1995 operands[2] = force_reg (mode, operands[2]);
2001 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
2003 rtx (*branch_expander) (rtx) = gen_branch_true;
2006 comparison = prepare_cbranch_operands (operands, SImode, comparison);
2009 case NE: case LT: case LE: case LTU: case LEU:
2010 comparison = reverse_condition (comparison);
2011 branch_expander = gen_branch_false;
2014 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
2015 gen_rtx_fmt_ee (comparison, SImode,
2016 operands[1], operands[2])));
2017 jump = emit_jump_insn (branch_expander (operands[3]));
2018 if (probability >= 0)
2019 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
2023 /* ??? How should we distribute probabilities when more than one branch
2024 is generated. So far we only have soem ad-hoc observations:
2025 - If the operands are random, they are likely to differ in both parts.
2026 - If comparing items in a hash chain, the operands are random or equal;
2027 operation should be EQ or NE.
2028 - If items are searched in an ordered tree from the root, we can expect
2029 the highpart to be unequal about half of the time; operation should be
2030 an inequality comparison, operands non-constant, and overall probability
2031 about 50%. Likewise for quicksort.
2032 - Range checks will be often made against constants. Even if we assume for
2033 simplicity an even distribution of the non-constant operand over a
2034 sub-range here, the same probability could be generated with differently
2035 wide sub-ranges - as long as the ratio of the part of the subrange that
2036 is before the threshold to the part that comes after the threshold stays
2037 the same. Thus, we can't really tell anything here;
2038 assuming random distribution is at least simple.
2042 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
2044 enum rtx_code msw_taken, msw_skip, lsw_taken;
2045 rtx skip_label = NULL_RTX;
2046 rtx op1h, op1l, op2h, op2l;
2049 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
2050 rtx scratch = operands[4];
2052 comparison = prepare_cbranch_operands (operands, DImode, comparison);
2053 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
2054 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
2055 op1l = gen_lowpart (SImode, operands[1]);
2056 op2l = gen_lowpart (SImode, operands[2]);
2057 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
2058 prob = split_branch_probability;
2059 rev_prob = REG_BR_PROB_BASE - prob;
2062 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
2063 That costs 1 cycle more when the first branch can be predicted taken,
2064 but saves us mispredicts because only one branch needs prediction.
2065 It also enables generating the cmpeqdi_t-1 pattern. */
2067 if (TARGET_CMPEQDI_T)
2069 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
2070 emit_jump_insn (gen_branch_true (operands[3]));
2077 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
2079 msw_skip_prob = rev_prob;
2080 if (REG_BR_PROB_BASE <= 65535)
2081 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
2084 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
2088 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
2089 / ((HOST_WIDEST_INT) prob << 32)))
2095 if (TARGET_CMPEQDI_T)
2097 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
2098 emit_jump_insn (gen_branch_false (operands[3]));
2102 msw_taken_prob = prob;
2107 msw_taken = comparison;
2108 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2110 if (comparison != GTU || op2h != CONST0_RTX (SImode))
2111 msw_skip = swap_condition (msw_taken);
2115 if (op2l == CONST0_RTX (SImode))
2116 msw_taken = comparison;
2119 msw_taken = comparison == GE ? GT : GTU;
2120 msw_skip = swap_condition (msw_taken);
2125 msw_taken = comparison;
2126 if (op2l == CONST0_RTX (SImode))
2128 msw_skip = swap_condition (msw_taken);
2132 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2133 msw_taken = comparison;
2137 if (comparison == LE)
2139 else if (op2h != CONST0_RTX (SImode))
2143 msw_skip = swap_condition (msw_taken);
2146 default: return false;
2148 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
2149 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2150 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
2151 if (comparison != EQ && comparison != NE && num_branches > 1)
2153 if (!CONSTANT_P (operands[2])
2154 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
2155 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
2157 msw_taken_prob = prob / 2U;
2159 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
2160 lsw_taken_prob = prob;
2164 msw_taken_prob = prob;
2165 msw_skip_prob = REG_BR_PROB_BASE;
2166 /* ??? If we have a constant op2h, should we use that when
2167 calculating lsw_taken_prob? */
2168 lsw_taken_prob = prob;
2173 operands[4] = NULL_RTX;
2174 if (reload_completed
2175 && ! arith_reg_or_0_operand (op2h, SImode)
2176 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
2177 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
2178 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
2180 emit_move_insn (scratch, operands[2]);
2181 operands[2] = scratch;
2183 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2184 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2185 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2187 rtx taken_label = operands[3];
2189 /* Operands were possibly modified, but msw_skip doesn't expect this.
2190 Always use the original ones. */
2191 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2197 operands[3] = skip_label = gen_label_rtx ();
2198 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2199 operands[3] = taken_label;
2203 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2205 if (reload_completed
2206 && ! arith_reg_or_0_operand (op2l, SImode)
2207 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2209 emit_move_insn (scratch, operands[2]);
2210 operands[2] = scratch;
2212 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2214 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2215 emit_label (skip_label);
2219 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2222 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2224 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2226 insn = gen_rtx_PARALLEL (VOIDmode,
2228 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2229 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2235 /* Prepare the operands for an scc instruction; make sure that the
2236 compare has been done and the result is in T_REG. */
2238 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2240 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2241 enum rtx_code oldcode = code;
2242 enum machine_mode mode;
2244 /* First need a compare insn. */
2248 /* It isn't possible to handle this case. */
2265 if (code != oldcode)
2272 mode = GET_MODE (op0);
2273 if (mode == VOIDmode)
2274 mode = GET_MODE (op1);
2276 op0 = force_reg (mode, op0);
2277 if ((code != EQ && code != NE
2278 && (op1 != const0_rtx
2279 || code == GTU || code == GEU || code == LTU || code == LEU))
2280 || (mode == DImode && op1 != const0_rtx)
2281 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2282 op1 = force_reg (mode, op1);
2284 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2285 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2290 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2293 rtx target = gen_reg_rtx (SImode);
2296 gcc_assert (TARGET_SHMEDIA);
2305 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2306 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2316 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2317 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2335 rtx t2 = gen_reg_rtx (DImode);
2336 emit_insn (gen_extendsidi2 (t2, target));
2340 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2343 /* Called from the md file, set up the operands of a compare instruction. */
2346 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2348 enum rtx_code code = GET_CODE (operands[0]);
2349 enum rtx_code branch_code;
2350 rtx op0 = operands[1];
2351 rtx op1 = operands[2];
2353 bool need_ccmpeq = false;
2355 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2357 op0 = force_reg (mode, op0);
2358 op1 = force_reg (mode, op1);
2362 if (code != EQ || mode == DImode)
2364 /* Force args into regs, since we can't use constants here. */
2365 op0 = force_reg (mode, op0);
2366 if (op1 != const0_rtx || code == GTU || code == GEU)
2367 op1 = force_reg (mode, op1);
2371 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2374 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2375 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2377 tem = op0, op0 = op1, op1 = tem;
2378 code = swap_condition (code);
2381 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2384 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2389 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2390 to EQ/GT respectively. */
2391 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2408 branch_code = reverse_condition (code);
2414 insn = gen_rtx_SET (VOIDmode,
2415 gen_rtx_REG (SImode, T_REG),
2416 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2418 sh_emit_set_t_insn (insn, mode);
2420 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2422 if (branch_code == code)
2423 emit_jump_insn (gen_branch_true (operands[3]));
2425 emit_jump_insn (gen_branch_false (operands[3]));
2429 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2431 enum rtx_code code = GET_CODE (operands[1]);
2432 rtx op0 = operands[2];
2433 rtx op1 = operands[3];
2435 bool invert = false;
2438 op0 = force_reg (mode, op0);
2439 if ((code != EQ && code != NE
2440 && (op1 != const0_rtx
2441 || code == GTU || code == GEU || code == LTU || code == LEU))
2442 || (mode == DImode && op1 != const0_rtx)
2443 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2444 op1 = force_reg (mode, op1);
2446 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2448 if (code == LT || code == LE)
2450 code = swap_condition (code);
2451 tem = op0, op0 = op1, op1 = tem;
2457 lab = gen_label_rtx ();
2458 sh_emit_scc_to_t (EQ, op0, op1);
2459 emit_jump_insn (gen_branch_true (lab));
2476 sh_emit_scc_to_t (code, op0, op1);
2480 emit_insn (gen_movnegt (operands[0]));
2482 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2485 /* Functions to output assembly code. */
2487 /* Return a sequence of instructions to perform DI or DF move.
2489 Since the SH cannot move a DI or DF in one instruction, we have
2490 to take care when we see overlapping source and dest registers. */
2493 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2494 enum machine_mode mode)
2496 rtx dst = operands[0];
2497 rtx src = operands[1];
2500 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2501 return "mov.l %T1,%0\n\tmov.l %1,%0";
2503 if (register_operand (dst, mode)
2504 && register_operand (src, mode))
2506 if (REGNO (src) == MACH_REG)
2507 return "sts mach,%S0\n\tsts macl,%R0";
2509 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2510 when mov.d r1,r0 do r1->r0 then r2->r1. */
2512 if (REGNO (src) + 1 == REGNO (dst))
2513 return "mov %T1,%T0\n\tmov %1,%0";
2515 return "mov %1,%0\n\tmov %T1,%T0";
2517 else if (CONST_INT_P (src))
2519 if (INTVAL (src) < 0)
2520 output_asm_insn ("mov #-1,%S0", operands);
2522 output_asm_insn ("mov #0,%S0", operands);
2524 return "mov %1,%R0";
2526 else if (MEM_P (src))
2529 int dreg = REGNO (dst);
2530 rtx inside = XEXP (src, 0);
2532 switch (GET_CODE (inside))
2535 ptrreg = REGNO (inside);
2539 ptrreg = subreg_regno (inside);
2543 ptrreg = REGNO (XEXP (inside, 0));
2544 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2545 an offsettable address. Unfortunately, offsettable addresses use
2546 QImode to check the offset, and a QImode offsettable address
2547 requires r0 for the other operand, which is not currently
2548 supported, so we can't use the 'o' constraint.
2549 Thus we must check for and handle r0+REG addresses here.
2550 We punt for now, since this is likely very rare. */
2551 gcc_assert (!REG_P (XEXP (inside, 1)));
2555 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2557 return "mov.l %1,%0\n\tmov.l %1,%T0";
2562 /* Work out the safe way to copy. Copy into the second half first. */
2564 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2567 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2570 /* Print an instruction which would have gone into a delay slot after
2571 another instruction, but couldn't because the other instruction expanded
2572 into a sequence where putting the slot insn at the end wouldn't work. */
2575 print_slot (rtx insn)
2577 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2579 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2583 output_far_jump (rtx insn, rtx op)
2585 struct { rtx lab, reg, op; } this_jmp;
2586 rtx braf_base_lab = NULL_RTX;
2589 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2592 this_jmp.lab = gen_label_rtx ();
2596 && offset - get_attr_length (insn) <= 32766)
2599 jump = "mov.w %O0,%1; braf %1";
2607 jump = "mov.l %O0,%1; braf %1";
2609 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2612 jump = "mov.l %O0,%1; jmp @%1";
2614 /* If we have a scratch register available, use it. */
2615 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2616 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2618 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2619 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2620 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2621 output_asm_insn (jump, &this_jmp.lab);
2622 if (dbr_sequence_length ())
2623 print_slot (final_sequence);
2625 output_asm_insn ("nop", 0);
2629 /* Output the delay slot insn first if any. */
2630 if (dbr_sequence_length ())
2631 print_slot (final_sequence);
2633 this_jmp.reg = gen_rtx_REG (SImode, 13);
2634 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2635 Fortunately, MACL is fixed and call-clobbered, and we never
2636 need its value across jumps, so save r13 in it instead of in
2639 output_asm_insn ("lds r13, macl", 0);
2641 output_asm_insn ("mov.l r13,@-r15", 0);
2642 output_asm_insn (jump, &this_jmp.lab);
2644 output_asm_insn ("sts macl, r13", 0);
2646 output_asm_insn ("mov.l @r15+,r13", 0);
2648 if (far && flag_pic && TARGET_SH2)
2650 braf_base_lab = gen_label_rtx ();
2651 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2652 CODE_LABEL_NUMBER (braf_base_lab));
2655 output_asm_insn (".align 2", 0);
2656 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2658 if (far && flag_pic)
2661 this_jmp.lab = braf_base_lab;
2662 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2665 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2669 /* Local label counter, used for constants in the pool and inside
2670 pattern branches. */
2672 static int lf = 100;
2674 /* Output code for ordinary branches. */
2677 output_branch (int logic, rtx insn, rtx *operands)
2679 switch (get_attr_length (insn))
2682 /* This can happen if filling the delay slot has caused a forward
2683 branch to exceed its range (we could reverse it, but only
2684 when we know we won't overextend other branches; this should
2685 best be handled by relaxation).
2686 It can also happen when other condbranches hoist delay slot insn
2687 from their destination, thus leading to code size increase.
2688 But the branch will still be in the range -4092..+4098 bytes. */
2693 /* The call to print_slot will clobber the operands. */
2694 rtx op0 = operands[0];
2696 /* If the instruction in the delay slot is annulled (true), then
2697 there is no delay slot where we can put it now. The only safe
2698 place for it is after the label. final will do that by default. */
2701 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2702 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2704 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2705 ASSEMBLER_DIALECT ? "/" : ".", label);
2706 print_slot (final_sequence);
2709 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2711 output_asm_insn ("bra\t%l0", &op0);
2712 fprintf (asm_out_file, "\tnop\n");
2713 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2717 /* When relaxing, handle this like a short branch. The linker
2718 will fix it up if it still doesn't fit after relaxation. */
2720 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2722 /* These are for SH2e, in which we have to account for the
2723 extra nop because of the hardware bug in annulled branches. */
2729 gcc_assert (!final_sequence
2730 || !(INSN_ANNULLED_BRANCH_P
2731 (XVECEXP (final_sequence, 0, 0))));
2732 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2734 ASSEMBLER_DIALECT ? "/" : ".", label);
2735 fprintf (asm_out_file, "\tnop\n");
2736 output_asm_insn ("bra\t%l0", operands);
2737 fprintf (asm_out_file, "\tnop\n");
2738 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2742 /* When relaxing, fall through. */
2747 sprintf (buffer, "b%s%ss\t%%l0",
2749 ASSEMBLER_DIALECT ? "/" : ".");
2750 output_asm_insn (buffer, &operands[0]);
2755 /* There should be no longer branches now - that would
2756 indicate that something has destroyed the branches set
2757 up in machine_dependent_reorg. */
2762 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2763 fill in operands 9 as a label to the successor insn.
2764 We try to use jump threading where possible.
2765 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2766 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2767 follow jmp and bt, if the address is in range. */
2769 output_branchy_insn (enum rtx_code code, const char *templ,
2770 rtx insn, rtx *operands)
2772 rtx next_insn = NEXT_INSN (insn);
2774 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2776 rtx src = SET_SRC (PATTERN (next_insn));
2777 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2779 /* Following branch not taken */
2780 operands[9] = gen_label_rtx ();
2781 emit_label_after (operands[9], next_insn);
2782 INSN_ADDRESSES_NEW (operands[9],
2783 INSN_ADDRESSES (INSN_UID (next_insn))
2784 + get_attr_length (next_insn));
2789 int offset = (branch_dest (next_insn)
2790 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2791 if (offset >= -252 && offset <= 258)
2793 if (GET_CODE (src) == IF_THEN_ELSE)
2795 src = XEXP (src, 1);
2801 operands[9] = gen_label_rtx ();
2802 emit_label_after (operands[9], insn);
2803 INSN_ADDRESSES_NEW (operands[9],
2804 INSN_ADDRESSES (INSN_UID (insn))
2805 + get_attr_length (insn));
2810 output_ieee_ccmpeq (rtx insn, rtx *operands)
2812 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2816 /* Output the start of the assembler file. */
2819 sh_file_start (void)
2821 default_file_start ();
2824 /* We need to show the text section with the proper
2825 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2826 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2827 will complain. We can teach GAS specifically about the
2828 default attributes for our choice of text section, but
2829 then we would have to change GAS again if/when we change
2830 the text section name. */
2831 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2833 /* Switch to the data section so that the coffsem symbol
2834 isn't in the text section. */
2835 switch_to_section (data_section);
2837 if (TARGET_LITTLE_ENDIAN)
2838 fputs ("\t.little\n", asm_out_file);
2842 if (TARGET_SHCOMPACT)
2843 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2844 else if (TARGET_SHMEDIA)
2845 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2846 TARGET_SHMEDIA64 ? 64 : 32);
2850 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2853 unspec_caller_rtx_p (rtx pat)
2858 split_const (pat, &base, &offset);
2859 if (GET_CODE (base) == UNSPEC)
2861 if (XINT (base, 1) == UNSPEC_CALLER)
2863 for (i = 0; i < XVECLEN (base, 0); i++)
2864 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2870 /* Indicate that INSN cannot be duplicated. This is true for insn
2871 that generates a unique label. */
2874 sh_cannot_copy_insn_p (rtx insn)
2878 if (!reload_completed || !flag_pic)
2881 if (!NONJUMP_INSN_P (insn))
2883 if (asm_noperands (insn) >= 0)
2886 pat = PATTERN (insn);
2887 if (GET_CODE (pat) != SET)
2889 pat = SET_SRC (pat);
2891 if (unspec_caller_rtx_p (pat))
2897 /* Actual number of instructions used to make a shift by N. */
2898 static const char ashiftrt_insns[] =
2899 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2901 /* Left shift and logical right shift are the same. */
2902 static const char shift_insns[] =
2903 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2905 /* Individual shift amounts needed to get the above length sequences.
2906 One bit right shifts clobber the T bit, so when possible, put one bit
2907 shifts in the middle of the sequence, so the ends are eligible for
2908 branch delay slots. */
2909 static const short shift_amounts[32][5] = {
2910 {0}, {1}, {2}, {2, 1},
2911 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2912 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2913 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2914 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2915 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2916 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2917 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2919 /* Likewise, but for shift amounts < 16, up to three highmost bits
2920 might be clobbered. This is typically used when combined with some
2921 kind of sign or zero extension. */
2923 static const char ext_shift_insns[] =
2924 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2926 static const short ext_shift_amounts[32][4] = {
2927 {0}, {1}, {2}, {2, 1},
2928 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2929 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2930 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2931 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2932 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2933 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2934 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2936 /* Assuming we have a value that has been sign-extended by at least one bit,
2937 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2938 to shift it by N without data loss, and quicker than by other means? */
2939 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2941 /* This is used in length attributes in sh.md to help compute the length
2942 of arbitrary constant shift instructions. */
2945 shift_insns_rtx (rtx insn)
2947 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2948 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2949 enum rtx_code shift_code = GET_CODE (set_src);
2954 return ashiftrt_insns[shift_count];
2957 return shift_insns[shift_count];
2963 /* Return the cost of a shift. */
2973 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2975 if (GET_MODE (x) == DImode
2976 && CONST_INT_P (XEXP (x, 1))
2977 && INTVAL (XEXP (x, 1)) == 1)
2980 /* Everything else is invalid, because there is no pattern for it. */
2983 /* If shift by a non constant, then this will be expensive. */
2984 if (!CONST_INT_P (XEXP (x, 1)))
2985 return SH_DYNAMIC_SHIFT_COST;
2987 /* Otherwise, return the true cost in instructions. Cope with out of range
2988 shift counts more or less arbitrarily. */
2989 value = INTVAL (XEXP (x, 1)) & 31;
2991 if (GET_CODE (x) == ASHIFTRT)
2993 int cost = ashiftrt_insns[value];
2994 /* If SH3, then we put the constant in a reg and use shad. */
2995 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2996 cost = 1 + SH_DYNAMIC_SHIFT_COST;
3000 return shift_insns[value];
3003 /* Return the cost of an AND operation. */
3010 /* Anding with a register is a single cycle and instruction. */
3011 if (!CONST_INT_P (XEXP (x, 1)))
3014 i = INTVAL (XEXP (x, 1));
3018 if (satisfies_constraint_I10 (XEXP (x, 1))
3019 || satisfies_constraint_J16 (XEXP (x, 1)))
3022 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
3025 /* These constants are single cycle extu.[bw] instructions. */
3026 if (i == 0xff || i == 0xffff)
3028 /* Constants that can be used in an and immediate instruction in a single
3029 cycle, but this requires r0, so make it a little more expensive. */
3030 if (CONST_OK_FOR_K08 (i))
3032 /* Constants that can be loaded with a mov immediate and an and.
3033 This case is probably unnecessary. */
3034 if (CONST_OK_FOR_I08 (i))
3036 /* Any other constants requires a 2 cycle pc-relative load plus an and.
3037 This case is probably unnecessary. */
3041 /* Return the cost of an addition or a subtraction. */
3046 /* Adding a register is a single cycle insn. */
3047 if (REG_P (XEXP (x, 1))
3048 || GET_CODE (XEXP (x, 1)) == SUBREG)
3051 /* Likewise for small constants. */
3052 if (CONST_INT_P (XEXP (x, 1))
3053 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
3057 switch (GET_CODE (XEXP (x, 1)))
3062 return TARGET_SHMEDIA64 ? 5 : 3;
3065 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
3067 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
3069 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
3077 /* Any other constant requires a 2 cycle pc-relative load plus an
3082 /* Return the cost of a multiply. */
3084 multcosts (rtx x ATTRIBUTE_UNUSED)
3086 if (sh_multcost >= 0)
3089 /* ??? We have a mul insn, but it has a latency of three, and doesn't
3090 accept constants. Ideally, we would use a cost of one or two and
3091 add the cost of the operand, but disregard the latter when inside loops
3092 and loop invariant code motion is still to follow.
3093 Using a multiply first and splitting it later if it's a loss
3094 doesn't work because of different sign / zero extension semantics
3095 of multiplies vs. shifts. */
3096 return optimize_size ? 2 : 3;
3100 /* We have a mul insn, so we can never take more than the mul and the
3101 read of the mac reg, but count more because of the latency and extra
3108 /* If we're aiming at small code, then just count the number of
3109 insns in a multiply call sequence. */
3113 /* Otherwise count all the insns in the routine we'd be calling too. */
3117 /* Compute a (partial) cost for rtx X. Return true if the complete
3118 cost has been computed, and false if subexpressions should be
3119 scanned. In either case, *TOTAL contains the cost result. */
3122 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
3123 bool speed ATTRIBUTE_UNUSED)
3130 if (INTVAL (x) == 0)
3132 else if (outer_code == AND && and_operand ((x), DImode))
3134 else if ((outer_code == IOR || outer_code == XOR
3135 || outer_code == PLUS)
3136 && CONST_OK_FOR_I10 (INTVAL (x)))
3138 else if (CONST_OK_FOR_I16 (INTVAL (x)))
3139 *total = COSTS_N_INSNS (outer_code != SET);
3140 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
3141 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
3142 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
3143 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
3145 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
3148 if (CONST_OK_FOR_I08 (INTVAL (x)))
3150 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
3151 && CONST_OK_FOR_K08 (INTVAL (x)))
3153 /* prepare_cmp_insn will force costly constants int registers before
3154 the cbranch[sd]i4 patterns can see them, so preserve potentially
3155 interesting ones not covered by I08 above. */
3156 else if (outer_code == COMPARE
3157 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3158 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3159 || INTVAL (x) == 0x7fffffff
3160 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3169 if (TARGET_SHMEDIA64)
3170 *total = COSTS_N_INSNS (4);
3171 else if (TARGET_SHMEDIA32)
3172 *total = COSTS_N_INSNS (2);
3179 *total = COSTS_N_INSNS (4);
3180 /* prepare_cmp_insn will force costly constants int registers before
3181 the cbranchdi4 pattern can see them, so preserve potentially
3182 interesting ones. */
3183 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3189 if (x == CONST0_RTX (GET_MODE (x)))
3191 else if (sh_1el_vec (x, VOIDmode))
3192 *total = outer_code != SET;
3193 if (sh_rep_vec (x, VOIDmode))
3194 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3195 + (outer_code != SET));
3196 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3201 *total = COSTS_N_INSNS (addsubcosts (x));
3205 *total = COSTS_N_INSNS (andcosts (x));
3209 *total = COSTS_N_INSNS (multcosts (x));
3215 *total = COSTS_N_INSNS (shiftcosts (x));
3222 *total = COSTS_N_INSNS (20);
3226 if (sh_1el_vec (x, VOIDmode))
3227 *total = outer_code != SET;
3228 if (sh_rep_vec (x, VOIDmode))
3229 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3230 + (outer_code != SET));
3231 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3244 /* Compute the cost of an address. For the SH, all valid addresses are
3245 the same cost. Use a slightly higher cost for reg + reg addressing,
3246 since it increases pressure on r0. */
3249 sh_address_cost (rtx X,
3250 bool speed ATTRIBUTE_UNUSED)
3252 return (GET_CODE (X) == PLUS
3253 && ! CONSTANT_P (XEXP (X, 1))
3254 && ! TARGET_SHMEDIA ? 1 : 0);
3257 /* Code to expand a shift. */
3260 gen_ashift (int type, int n, rtx reg)
3262 /* Negative values here come from the shift_amounts array. */
3275 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3279 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3281 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3284 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3289 /* Same for HImode */
3292 gen_ashift_hi (int type, int n, rtx reg)
3294 /* Negative values here come from the shift_amounts array. */
3308 /* We don't have HImode right shift operations because using the
3309 ordinary 32 bit shift instructions for that doesn't generate proper
3310 zero/sign extension.
3311 gen_ashift_hi is only called in contexts where we know that the
3312 sign extension works out correctly. */
3315 if (GET_CODE (reg) == SUBREG)
3317 offset = SUBREG_BYTE (reg);
3318 reg = SUBREG_REG (reg);
3320 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3324 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3329 /* Output RTL to split a constant shift into its component SH constant
3330 shift instructions. */
3333 gen_shifty_op (int code, rtx *operands)
3335 int value = INTVAL (operands[2]);
3338 /* Truncate the shift count in case it is out of bounds. */
3343 if (code == LSHIFTRT)
3345 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3346 emit_insn (gen_movt (operands[0]));
3349 else if (code == ASHIFT)
3351 /* There is a two instruction sequence for 31 bit left shifts,
3352 but it requires r0. */
3353 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3355 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3356 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3361 else if (value == 0)
3363 /* This can happen even when optimizing, if there were subregs before
3364 reload. Don't output a nop here, as this is never optimized away;
3365 use a no-op move instead. */
3366 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3370 max = shift_insns[value];
3371 for (i = 0; i < max; i++)
3372 gen_ashift (code, shift_amounts[value][i], operands[0]);
3375 /* Same as above, but optimized for values where the topmost bits don't
3379 gen_shifty_hi_op (int code, rtx *operands)
3381 int value = INTVAL (operands[2]);
3383 void (*gen_fun) (int, int, rtx);
3385 /* This operation is used by and_shl for SImode values with a few
3386 high bits known to be cleared. */
3390 emit_insn (gen_nop ());
3394 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3397 max = ext_shift_insns[value];
3398 for (i = 0; i < max; i++)
3399 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3402 /* When shifting right, emit the shifts in reverse order, so that
3403 solitary negative values come first. */
3404 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3405 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3408 /* Output RTL for an arithmetic right shift. */
3410 /* ??? Rewrite to use super-optimizer sequences. */
3413 expand_ashiftrt (rtx *operands)
3421 if (!CONST_INT_P (operands[2]))
3423 rtx count = copy_to_mode_reg (SImode, operands[2]);
3424 emit_insn (gen_negsi2 (count, count));
3425 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3428 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3429 > 1 + SH_DYNAMIC_SHIFT_COST)
3432 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3433 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3437 if (!CONST_INT_P (operands[2]))
3440 value = INTVAL (operands[2]) & 31;
3444 /* If we are called from abs expansion, arrange things so that we
3445 we can use a single MT instruction that doesn't clobber the source,
3446 if LICM can hoist out the load of the constant zero. */
3447 if (currently_expanding_to_rtl)
3449 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3451 emit_insn (gen_mov_neg_si_t (operands[0]));
3454 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3457 else if (value >= 16 && value <= 19)
3459 wrk = gen_reg_rtx (SImode);
3460 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3463 gen_ashift (ASHIFTRT, 1, wrk);
3464 emit_move_insn (operands[0], wrk);
3467 /* Expand a short sequence inline, longer call a magic routine. */
3468 else if (value <= 5)
3470 wrk = gen_reg_rtx (SImode);
3471 emit_move_insn (wrk, operands[1]);
3473 gen_ashift (ASHIFTRT, 1, wrk);
3474 emit_move_insn (operands[0], wrk);
3478 wrk = gen_reg_rtx (Pmode);
3480 /* Load the value into an arg reg and call a helper. */
3481 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3482 sprintf (func, "__ashiftrt_r4_%d", value);
3483 function_symbol (wrk, func, SFUNC_STATIC);
3484 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3485 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3490 sh_dynamicalize_shift_p (rtx count)
3492 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3495 /* Try to find a good way to implement the combiner pattern
3496 [(set (match_operand:SI 0 "register_operand" "r")
3497 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3498 (match_operand:SI 2 "const_int_operand" "n"))
3499 (match_operand:SI 3 "const_int_operand" "n"))) .
3500 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3501 return 0 for simple right / left or left/right shift combination.
3502 return 1 for a combination of shifts with zero_extend.
3503 return 2 for a combination of shifts with an AND that needs r0.
3504 return 3 for a combination of shifts with an AND that needs an extra
3505 scratch register, when the three highmost bits of the AND mask are clear.
3506 return 4 for a combination of shifts with an AND that needs an extra
3507 scratch register, when any of the three highmost bits of the AND mask
3509 If ATTRP is set, store an initial right shift width in ATTRP[0],
3510 and the instruction length in ATTRP[1] . These values are not valid
3512 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3513 shift_amounts for the last shift value that is to be used before the
3516 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3518 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3519 int left = INTVAL (left_rtx), right;
3521 int cost, best_cost = 10000;
3522 int best_right = 0, best_len = 0;
3526 if (left < 0 || left > 31)
3528 if (CONST_INT_P (mask_rtx))
3529 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3531 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3532 /* Can this be expressed as a right shift / left shift pair? */
3533 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3534 right = exact_log2 (lsb);
3535 mask2 = ~(mask + lsb - 1);
3536 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3537 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3539 best_cost = shift_insns[right] + shift_insns[right + left];
3540 /* mask has no trailing zeroes <==> ! right */
3541 else if (! right && mask2 == ~(lsb2 - 1))
3543 int late_right = exact_log2 (lsb2);
3544 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3546 /* Try to use zero extend. */
3547 if (mask2 == ~(lsb2 - 1))
3551 for (width = 8; width <= 16; width += 8)
3553 /* Can we zero-extend right away? */
3554 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3557 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3558 if (cost < best_cost)
3569 /* ??? Could try to put zero extend into initial right shift,
3570 or even shift a bit left before the right shift. */
3571 /* Determine value of first part of left shift, to get to the
3572 zero extend cut-off point. */
3573 first = width - exact_log2 (lsb2) + right;
3574 if (first >= 0 && right + left - first >= 0)
3576 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3577 + ext_shift_insns[right + left - first];
3578 if (cost < best_cost)
3590 /* Try to use r0 AND pattern */
3591 for (i = 0; i <= 2; i++)
3595 if (! CONST_OK_FOR_K08 (mask >> i))
3597 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3598 if (cost < best_cost)
3603 best_len = cost - 1;
3606 /* Try to use a scratch register to hold the AND operand. */
3607 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3608 for (i = 0; i <= 2; i++)
3612 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3613 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3614 if (cost < best_cost)
3619 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3625 attrp[0] = best_right;
3626 attrp[1] = best_len;
3631 /* This is used in length attributes of the unnamed instructions
3632 corresponding to shl_and_kind return values of 1 and 2. */
3634 shl_and_length (rtx insn)
3636 rtx set_src, left_rtx, mask_rtx;
3639 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3640 left_rtx = XEXP (XEXP (set_src, 0), 1);
3641 mask_rtx = XEXP (set_src, 1);
3642 shl_and_kind (left_rtx, mask_rtx, attributes);
3643 return attributes[1];
3646 /* This is used in length attribute of the and_shl_scratch instruction. */
3649 shl_and_scr_length (rtx insn)
3651 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3652 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3653 rtx op = XEXP (set_src, 0);
3654 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3655 op = XEXP (XEXP (op, 0), 0);
3656 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3659 /* Generate rtl for instructions for which shl_and_kind advised a particular
3660 method of generating them, i.e. returned zero. */
3663 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3666 unsigned HOST_WIDE_INT mask;
3667 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3668 int right, total_shift;
3669 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3671 right = attributes[0];
3672 total_shift = INTVAL (left_rtx) + right;
3673 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3680 int first = attributes[2];
3685 emit_insn ((mask << right) <= 0xff
3686 ? gen_zero_extendqisi2 (dest,
3687 gen_lowpart (QImode, source))
3688 : gen_zero_extendhisi2 (dest,
3689 gen_lowpart (HImode, source)));
3693 emit_insn (gen_movsi (dest, source));
3697 operands[2] = GEN_INT (right);
3698 gen_shifty_hi_op (LSHIFTRT, operands);
3702 operands[2] = GEN_INT (first);
3703 gen_shifty_hi_op (ASHIFT, operands);
3704 total_shift -= first;
3708 emit_insn (mask <= 0xff
3709 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3710 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3711 if (total_shift > 0)
3713 operands[2] = GEN_INT (total_shift);
3714 gen_shifty_hi_op (ASHIFT, operands);
3719 shift_gen_fun = gen_shifty_op;
3721 /* If the topmost bit that matters is set, set the topmost bits
3722 that don't matter. This way, we might be able to get a shorter
3724 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3725 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3727 /* Don't expand fine-grained when combining, because that will
3728 make the pattern fail. */
3729 if (currently_expanding_to_rtl
3730 || reload_in_progress || reload_completed)
3734 /* Cases 3 and 4 should be handled by this split
3735 only while combining */
3736 gcc_assert (kind <= 2);
3739 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3742 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3747 operands[2] = GEN_INT (total_shift);
3748 shift_gen_fun (ASHIFT, operands);
3755 if (kind != 4 && total_shift < 16)
3757 neg = -ext_shift_amounts[total_shift][1];
3759 neg -= ext_shift_amounts[total_shift][2];
3763 emit_insn (gen_and_shl_scratch (dest, source,
3766 GEN_INT (total_shift + neg),
3768 emit_insn (gen_movsi (dest, dest));
3775 /* Try to find a good way to implement the combiner pattern
3776 [(set (match_operand:SI 0 "register_operand" "=r")
3777 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3778 (match_operand:SI 2 "const_int_operand" "n")
3779 (match_operand:SI 3 "const_int_operand" "n")
3781 (clobber (reg:SI T_REG))]
3782 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3783 return 0 for simple left / right shift combination.
3784 return 1 for left shift / 8 bit sign extend / left shift.
3785 return 2 for left shift / 16 bit sign extend / left shift.
3786 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3787 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3788 return 5 for left shift / 16 bit sign extend / right shift
3789 return 6 for < 8 bit sign extend / left shift.
3790 return 7 for < 8 bit sign extend / left shift / single right shift.
3791 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3794 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3796 int left, size, insize, ext;
3797 int cost = 0, best_cost;
3800 left = INTVAL (left_rtx);
3801 size = INTVAL (size_rtx);
3802 insize = size - left;
3803 gcc_assert (insize > 0);
3804 /* Default to left / right shift. */
3806 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3809 /* 16 bit shift / sign extend / 16 bit shift */
3810 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3811 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3812 below, by alternative 3 or something even better. */
3813 if (cost < best_cost)
3819 /* Try a plain sign extend between two shifts. */
3820 for (ext = 16; ext >= insize; ext -= 8)
3824 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3825 if (cost < best_cost)
3827 kind = ext / (unsigned) 8;
3831 /* Check if we can do a sloppy shift with a final signed shift
3832 restoring the sign. */
3833 if (EXT_SHIFT_SIGNED (size - ext))
3834 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3835 /* If not, maybe it's still cheaper to do the second shift sloppy,
3836 and do a final sign extend? */
3837 else if (size <= 16)
3838 cost = ext_shift_insns[ext - insize] + 1
3839 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3842 if (cost < best_cost)
3844 kind = ext / (unsigned) 8 + 2;
3848 /* Check if we can sign extend in r0 */
3851 cost = 3 + shift_insns[left];
3852 if (cost < best_cost)
3857 /* Try the same with a final signed shift. */
3860 cost = 3 + ext_shift_insns[left + 1] + 1;
3861 if (cost < best_cost)
3870 /* Try to use a dynamic shift. */
3871 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3872 if (cost < best_cost)
3883 /* Function to be used in the length attribute of the instructions
3884 implementing this pattern. */
3887 shl_sext_length (rtx insn)
3889 rtx set_src, left_rtx, size_rtx;
3892 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3893 left_rtx = XEXP (XEXP (set_src, 0), 1);
3894 size_rtx = XEXP (set_src, 1);
3895 shl_sext_kind (left_rtx, size_rtx, &cost);
3899 /* Generate rtl for this pattern */
3902 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3905 int left, size, insize, cost;
3908 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3909 left = INTVAL (left_rtx);
3910 size = INTVAL (size_rtx);
3911 insize = size - left;
3919 int ext = kind & 1 ? 8 : 16;
3920 int shift2 = size - ext;
3922 /* Don't expand fine-grained when combining, because that will
3923 make the pattern fail. */
3924 if (! currently_expanding_to_rtl
3925 && ! reload_in_progress && ! reload_completed)
3927 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3928 emit_insn (gen_movsi (dest, source));
3932 emit_insn (gen_movsi (dest, source));
3936 operands[2] = GEN_INT (ext - insize);
3937 gen_shifty_hi_op (ASHIFT, operands);
3940 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3941 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3946 operands[2] = GEN_INT (shift2);
3947 gen_shifty_op (ASHIFT, operands);
3954 if (EXT_SHIFT_SIGNED (shift2))
3956 operands[2] = GEN_INT (shift2 + 1);
3957 gen_shifty_op (ASHIFT, operands);
3958 operands[2] = const1_rtx;
3959 gen_shifty_op (ASHIFTRT, operands);
3962 operands[2] = GEN_INT (shift2);
3963 gen_shifty_hi_op (ASHIFT, operands);
3967 operands[2] = GEN_INT (-shift2);
3968 gen_shifty_hi_op (LSHIFTRT, operands);
3970 emit_insn (size <= 8
3971 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3972 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3979 if (! currently_expanding_to_rtl
3980 && ! reload_in_progress && ! reload_completed)
3981 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3985 operands[2] = GEN_INT (16 - insize);
3986 gen_shifty_hi_op (ASHIFT, operands);
3987 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3989 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3991 gen_ashift (ASHIFTRT, 1, dest);
3996 /* Don't expand fine-grained when combining, because that will
3997 make the pattern fail. */
3998 if (! currently_expanding_to_rtl
3999 && ! reload_in_progress && ! reload_completed)
4001 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4002 emit_insn (gen_movsi (dest, source));
4005 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
4006 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
4007 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
4009 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
4010 gen_shifty_op (ASHIFT, operands);
4012 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
4020 /* Prefix a symbol_ref name with "datalabel". */
4023 gen_datalabel_ref (rtx sym)
4027 if (GET_CODE (sym) == LABEL_REF)
4028 return gen_rtx_CONST (GET_MODE (sym),
4029 gen_rtx_UNSPEC (GET_MODE (sym),
4033 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
4035 str = XSTR (sym, 0);
4036 /* Share all SYMBOL_REF strings with the same value - that is important
4038 str = IDENTIFIER_POINTER (get_identifier (str));
4039 XSTR (sym, 0) = str;
4045 static alloc_pool label_ref_list_pool;
4047 typedef struct label_ref_list_d
4050 struct label_ref_list_d *next;
4051 } *label_ref_list_t;
4053 /* The SH cannot load a large constant into a register, constants have to
4054 come from a pc relative load. The reference of a pc relative load
4055 instruction must be less than 1k in front of the instruction. This
4056 means that we often have to dump a constant inside a function, and
4057 generate code to branch around it.
4059 It is important to minimize this, since the branches will slow things
4060 down and make things bigger.
4062 Worst case code looks like:
4080 We fix this by performing a scan before scheduling, which notices which
4081 instructions need to have their operands fetched from the constant table
4082 and builds the table.
4086 scan, find an instruction which needs a pcrel move. Look forward, find the
4087 last barrier which is within MAX_COUNT bytes of the requirement.
4088 If there isn't one, make one. Process all the instructions between
4089 the find and the barrier.
4091 In the above example, we can tell that L3 is within 1k of L1, so
4092 the first move can be shrunk from the 3 insn+constant sequence into
4093 just 1 insn, and the constant moved to L3 to make:
4104 Then the second move becomes the target for the shortening process. */
4108 rtx value; /* Value in table. */
4109 rtx label; /* Label of value. */
4110 label_ref_list_t wend; /* End of window. */
4111 enum machine_mode mode; /* Mode of value. */
4113 /* True if this constant is accessed as part of a post-increment
4114 sequence. Note that HImode constants are never accessed in this way. */
4115 bool part_of_sequence_p;
4118 /* The maximum number of constants that can fit into one pool, since
4119 constants in the range 0..510 are at least 2 bytes long, and in the
4120 range from there to 1018 at least 4 bytes. */
4122 #define MAX_POOL_SIZE 372
4123 static pool_node pool_vector[MAX_POOL_SIZE];
4124 static int pool_size;
4125 static rtx pool_window_label;
4126 static int pool_window_last;
4128 static int max_labelno_before_reorg;
4130 /* ??? If we need a constant in HImode which is the truncated value of a
4131 constant we need in SImode, we could combine the two entries thus saving
4132 two bytes. Is this common enough to be worth the effort of implementing
4135 /* ??? This stuff should be done at the same time that we shorten branches.
4136 As it is now, we must assume that all branches are the maximum size, and
4137 this causes us to almost always output constant pools sooner than
4140 /* Add a constant to the pool and return its label. */
4143 add_constant (rtx x, enum machine_mode mode, rtx last_value)
4147 label_ref_list_t ref, newref;
4149 /* First see if we've already got it. */
4150 for (i = 0; i < pool_size; i++)
4152 if (x->code == pool_vector[i].value->code
4153 && mode == pool_vector[i].mode)
4155 if (x->code == CODE_LABEL)
4157 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4160 if (rtx_equal_p (x, pool_vector[i].value))
4165 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4167 new_rtx = gen_label_rtx ();
4168 LABEL_REFS (new_rtx) = pool_vector[i].label;
4169 pool_vector[i].label = lab = new_rtx;
4171 if (lab && pool_window_label)
4173 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4174 newref->label = pool_window_label;
4175 ref = pool_vector[pool_window_last].wend;
4177 pool_vector[pool_window_last].wend = newref;
4180 pool_window_label = new_rtx;
4181 pool_window_last = i;
4187 /* Need a new one. */
4188 pool_vector[pool_size].value = x;
4189 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4192 pool_vector[pool_size - 1].part_of_sequence_p = true;
4195 lab = gen_label_rtx ();
4196 pool_vector[pool_size].mode = mode;
4197 pool_vector[pool_size].label = lab;
4198 pool_vector[pool_size].wend = NULL;
4199 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4200 if (lab && pool_window_label)
4202 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4203 newref->label = pool_window_label;
4204 ref = pool_vector[pool_window_last].wend;
4206 pool_vector[pool_window_last].wend = newref;
4209 pool_window_label = lab;
4210 pool_window_last = pool_size;
4215 /* Output the literal table. START, if nonzero, is the first instruction
4216 this table is needed for, and also indicates that there is at least one
4217 casesi_worker_2 instruction; We have to emit the operand3 labels from
4218 these insns at a 4-byte aligned position. BARRIER is the barrier
4219 after which we are to place the table. */
4222 dump_table (rtx start, rtx barrier)
4228 label_ref_list_t ref;
4231 /* Do two passes, first time dump out the HI sized constants. */
4233 for (i = 0; i < pool_size; i++)
4235 pool_node *p = &pool_vector[i];
4237 if (p->mode == HImode)
4241 scan = emit_insn_after (gen_align_2 (), scan);
4244 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4245 scan = emit_label_after (lab, scan);
4246 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4248 for (ref = p->wend; ref; ref = ref->next)
4251 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4254 else if (p->mode == DFmode)
4262 scan = emit_insn_after (gen_align_4 (), scan);
4264 for (; start != barrier; start = NEXT_INSN (start))
4265 if (NONJUMP_INSN_P (start)
4266 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4268 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4269 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4271 scan = emit_label_after (lab, scan);
4274 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4276 rtx align_insn = NULL_RTX;
4278 scan = emit_label_after (gen_label_rtx (), scan);
4279 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4282 for (i = 0; i < pool_size; i++)
4284 pool_node *p = &pool_vector[i];
4292 if (align_insn && !p->part_of_sequence_p)
4294 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4295 emit_label_before (lab, align_insn);
4296 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4298 for (ref = p->wend; ref; ref = ref->next)
4301 emit_insn_before (gen_consttable_window_end (lab),
4304 delete_insn (align_insn);
4305 align_insn = NULL_RTX;
4310 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4311 scan = emit_label_after (lab, scan);
4312 scan = emit_insn_after (gen_consttable_4 (p->value,
4314 need_align = ! need_align;
4320 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4325 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4326 scan = emit_label_after (lab, scan);
4327 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4334 if (p->mode != HImode)
4336 for (ref = p->wend; ref; ref = ref->next)
4339 scan = emit_insn_after (gen_consttable_window_end (lab),
4348 for (i = 0; i < pool_size; i++)
4350 pool_node *p = &pool_vector[i];
4361 scan = emit_label_after (gen_label_rtx (), scan);
4362 scan = emit_insn_after (gen_align_4 (), scan);
4364 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4365 scan = emit_label_after (lab, scan);
4366 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4374 scan = emit_label_after (gen_label_rtx (), scan);
4375 scan = emit_insn_after (gen_align_4 (), scan);
4377 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4378 scan = emit_label_after (lab, scan);
4379 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4386 if (p->mode != HImode)
4388 for (ref = p->wend; ref; ref = ref->next)
4391 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4396 scan = emit_insn_after (gen_consttable_end (), scan);
4397 scan = emit_barrier_after (scan);
4399 pool_window_label = NULL_RTX;
4400 pool_window_last = 0;
4403 /* Return nonzero if constant would be an ok source for a
4404 mov.w instead of a mov.l. */
4409 return (CONST_INT_P (src)
4410 && INTVAL (src) >= -32768
4411 && INTVAL (src) <= 32767);
4414 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4416 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4418 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4419 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4420 need to fix it if the input value is CONST_OK_FOR_I08. */
4423 broken_move (rtx insn)
4425 if (NONJUMP_INSN_P (insn))
4427 rtx pat = PATTERN (insn);
4428 if (GET_CODE (pat) == PARALLEL)
4429 pat = XVECEXP (pat, 0, 0);
4430 if (GET_CODE (pat) == SET
4431 /* We can load any 8-bit value if we don't care what the high
4432 order bits end up as. */
4433 && GET_MODE (SET_DEST (pat)) != QImode
4434 && (CONSTANT_P (SET_SRC (pat))
4435 /* Match mova_const. */
4436 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4437 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4438 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4440 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4441 && (fp_zero_operand (SET_SRC (pat))
4442 || fp_one_operand (SET_SRC (pat)))
4443 /* In general we don't know the current setting of fpscr, so disable fldi.
4444 There is an exception if this was a register-register move
4445 before reload - and hence it was ascertained that we have
4446 single precision setting - and in a post-reload optimization
4447 we changed this to do a constant load. In that case
4448 we don't have an r0 clobber, hence we must use fldi. */
4450 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4452 && REG_P (SET_DEST (pat))
4453 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4455 && GET_MODE (SET_DEST (pat)) == SImode
4456 && (satisfies_constraint_I20 (SET_SRC (pat))
4457 || satisfies_constraint_I28 (SET_SRC (pat))))
4458 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4468 return (NONJUMP_INSN_P (insn)
4469 && GET_CODE (PATTERN (insn)) == SET
4470 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4471 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4472 /* Don't match mova_const. */
4473 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4476 /* Fix up a mova from a switch that went out of range. */
4478 fixup_mova (rtx mova)
4480 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4483 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4484 INSN_CODE (mova) = -1;
4489 rtx lab = gen_label_rtx ();
4490 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4494 worker = NEXT_INSN (worker);
4496 && !LABEL_P (worker)
4497 && !JUMP_P (worker));
4498 } while (NOTE_P (worker)
4499 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4500 wpat = PATTERN (worker);
4501 wpat0 = XVECEXP (wpat, 0, 0);
4502 wpat1 = XVECEXP (wpat, 0, 1);
4503 wsrc = SET_SRC (wpat0);
4504 PATTERN (worker) = (gen_casesi_worker_2
4505 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4506 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4508 INSN_CODE (worker) = -1;
4509 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4510 base = gen_rtx_LABEL_REF (Pmode, lab);
4511 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4512 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4513 INSN_CODE (mova) = -1;
4517 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4518 *num_mova, and check if the new mova is not nested within the first one.
4519 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4520 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4522 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4524 int n_addr = 0; /* Initialization to shut up spurious warning. */
4525 int f_target, n_target = 0; /* Likewise. */
4529 /* If NEW_MOVA has no address yet, it will be handled later. */
4530 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4533 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4534 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4535 if (n_addr > n_target || n_addr + 1022 < n_target)
4537 /* Change the mova into a load.
4538 broken_move will then return true for it. */
4539 fixup_mova (new_mova);
4545 *first_mova = new_mova;
4550 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4555 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4556 > n_target - n_addr)
4558 fixup_mova (*first_mova);
4563 fixup_mova (new_mova);
4568 /* Find the last barrier from insn FROM which is close enough to hold the
4569 constant pool. If we can't find one, then create one near the end of
4573 find_barrier (int num_mova, rtx mova, rtx from)
4582 int leading_mova = num_mova;
4583 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4587 rtx last_got = NULL_RTX;
4588 rtx last_symoff = NULL_RTX;
4590 /* For HImode: range is 510, add 4 because pc counts from address of
4591 second instruction after this one, subtract 2 for the jump instruction
4592 that we may need to emit before the table, subtract 2 for the instruction
4593 that fills the jump delay slot (in very rare cases, reorg will take an
4594 instruction from after the constant pool or will leave the delay slot
4595 empty). This gives 510.
4596 For SImode: range is 1020, add 4 because pc counts from address of
4597 second instruction after this one, subtract 2 in case pc is 2 byte
4598 aligned, subtract 2 for the jump instruction that we may need to emit
4599 before the table, subtract 2 for the instruction that fills the jump
4600 delay slot. This gives 1018. */
4602 /* The branch will always be shortened now that the reference address for
4603 forward branches is the successor address, thus we need no longer make
4604 adjustments to the [sh]i_limit for -O0. */
4609 while (from && count_si < si_limit && count_hi < hi_limit)
4611 int inc = get_attr_length (from);
4614 /* If this is a label that existed at the time of the compute_alignments
4615 call, determine the alignment. N.B. When find_barrier recurses for
4616 an out-of-reach mova, we might see labels at the start of previously
4617 inserted constant tables. */
4619 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4622 new_align = 1 << label_to_alignment (from);
4623 else if (BARRIER_P (prev_nonnote_insn (from)))
4624 new_align = 1 << barrier_align (from);
4629 /* In case we are scanning a constant table because of recursion, check
4630 for explicit alignments. If the table is long, we might be forced
4631 to emit the new table in front of it; the length of the alignment
4632 might be the last straw. */
4633 else if (NONJUMP_INSN_P (from)
4634 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4635 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4636 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4637 /* When we find the end of a constant table, paste the new constant
4638 at the end. That is better than putting it in front because
4639 this way, we don't need extra alignment for adding a 4-byte-aligned
4640 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4641 else if (NONJUMP_INSN_P (from)
4642 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4643 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4646 if (BARRIER_P (from))
4650 found_barrier = from;
4652 /* If we are at the end of the function, or in front of an alignment
4653 instruction, we need not insert an extra alignment. We prefer
4654 this kind of barrier. */
4655 if (barrier_align (from) > 2)
4656 good_barrier = from;
4658 /* If we are at the end of a hot/cold block, dump the constants
4660 next = NEXT_INSN (from);
4663 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4667 if (broken_move (from))
4670 enum machine_mode mode;
4672 pat = PATTERN (from);
4673 if (GET_CODE (pat) == PARALLEL)
4674 pat = XVECEXP (pat, 0, 0);
4675 src = SET_SRC (pat);
4676 dst = SET_DEST (pat);
4677 mode = GET_MODE (dst);
4679 /* GOT pcrelat setting comes in pair of
4682 instructions. (plus add r0,r12).
4683 Remember if we see one without the other. */
4684 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4685 last_got = last_got ? NULL_RTX : from;
4686 else if (PIC_ADDR_P (src))
4687 last_got = last_got ? NULL_RTX : from;
4689 /* We must explicitly check the mode, because sometimes the
4690 front end will generate code to load unsigned constants into
4691 HImode targets without properly sign extending them. */
4693 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4696 /* We put the short constants before the long constants, so
4697 we must count the length of short constants in the range
4698 for the long constants. */
4699 /* ??? This isn't optimal, but is easy to do. */
4704 /* We dump DF/DI constants before SF/SI ones, because
4705 the limit is the same, but the alignment requirements
4706 are higher. We may waste up to 4 additional bytes
4707 for alignment, and the DF/DI constant may have
4708 another SF/SI constant placed before it. */
4709 if (TARGET_SHCOMPACT
4711 && (mode == DFmode || mode == DImode))
4716 while (si_align > 2 && found_si + si_align - 2 > count_si)
4718 if (found_si > count_si)
4719 count_si = found_si;
4720 found_si += GET_MODE_SIZE (mode);
4722 si_limit -= GET_MODE_SIZE (mode);
4728 switch (untangle_mova (&num_mova, &mova, from))
4733 rtx src = SET_SRC (PATTERN (from));
4734 if (GET_CODE (src) == CONST
4735 && GET_CODE (XEXP (src, 0)) == UNSPEC
4736 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4740 case 0: return find_barrier (0, 0, mova);
4745 = good_barrier ? good_barrier : found_barrier;
4749 if (found_si > count_si)
4750 count_si = found_si;
4752 else if (JUMP_TABLE_DATA_P (from))
4754 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4756 && (prev_nonnote_insn (from)
4757 == XEXP (MOVA_LABELREF (mova), 0))))
4759 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4761 /* We have just passed the barrier in front of the
4762 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4763 the ADDR_DIFF_VEC is accessed as data, just like our pool
4764 constants, this is a good opportunity to accommodate what
4765 we have gathered so far.
4766 If we waited any longer, we could end up at a barrier in
4767 front of code, which gives worse cache usage for separated
4768 instruction / data caches. */
4769 good_barrier = found_barrier;
4774 rtx body = PATTERN (from);
4775 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4778 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4779 else if (JUMP_P (from)
4784 /* There is a possibility that a bf is transformed into a bf/s by the
4785 delay slot scheduler. */
4786 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4787 && get_attr_type (from) == TYPE_CBRANCH
4788 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4794 if (new_align > si_align)
4796 si_limit -= (count_si - 1) & (new_align - si_align);
4797 si_align = new_align;
4799 count_si = (count_si + new_align - 1) & -new_align;
4804 if (new_align > hi_align)
4806 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4807 hi_align = new_align;
4809 count_hi = (count_hi + new_align - 1) & -new_align;
4811 from = NEXT_INSN (from);
4818 /* Try as we might, the leading mova is out of range. Change
4819 it into a load (which will become a pcload) and retry. */
4821 return find_barrier (0, 0, mova);
4825 /* Insert the constant pool table before the mova instruction,
4826 to prevent the mova label reference from going out of range. */
4828 good_barrier = found_barrier = barrier_before_mova;
4834 if (good_barrier && next_real_insn (found_barrier))
4835 found_barrier = good_barrier;
4839 /* We didn't find a barrier in time to dump our stuff,
4840 so we'll make one. */
4841 rtx label = gen_label_rtx ();
4843 /* Don't emit a constant table in the middle of insns for
4844 casesi_worker_2. This is a bit overkill but is enough
4845 because casesi_worker_2 wouldn't appear so frequently. */
4849 /* If we exceeded the range, then we must back up over the last
4850 instruction we looked at. Otherwise, we just need to undo the
4851 NEXT_INSN at the end of the loop. */
4852 if (PREV_INSN (from) != orig
4853 && (count_hi > hi_limit || count_si > si_limit))
4854 from = PREV_INSN (PREV_INSN (from));
4856 from = PREV_INSN (from);
4858 /* Don't emit a constant table int the middle of global pointer setting,
4859 since that that would move the addressing base GOT into another table.
4860 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4861 in the pool anyway, so just move up the whole constant pool. */
4863 from = PREV_INSN (last_got);
4865 /* Don't insert the constant pool table at the position which
4866 may be the landing pad. */
4869 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4870 from = PREV_INSN (from);
4872 /* Walk back to be just before any jump or label.
4873 Putting it before a label reduces the number of times the branch
4874 around the constant pool table will be hit. Putting it before
4875 a jump makes it more likely that the bra delay slot will be
4877 while (NOTE_P (from) || JUMP_P (from)
4879 from = PREV_INSN (from);
4881 /* Make sure we do not split between a call and its corresponding
4882 CALL_ARG_LOCATION note. */
4885 rtx next = NEXT_INSN (from);
4886 if (next && NOTE_P (next)
4887 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
4891 from = emit_jump_insn_after (gen_jump (label), from);
4892 JUMP_LABEL (from) = label;
4893 LABEL_NUSES (label) = 1;
4894 found_barrier = emit_barrier_after (from);
4895 emit_label_after (label, found_barrier);
4898 return found_barrier;
4901 /* If the instruction INSN is implemented by a special function, and we can
4902 positively find the register that is used to call the sfunc, and this
4903 register is not used anywhere else in this instruction - except as the
4904 destination of a set, return this register; else, return 0. */
4906 sfunc_uses_reg (rtx insn)
4909 rtx pattern, part, reg_part, reg;
4911 if (!NONJUMP_INSN_P (insn))
4913 pattern = PATTERN (insn);
4914 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4917 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4919 part = XVECEXP (pattern, 0, i);
4920 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4925 reg = XEXP (reg_part, 0);
4926 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4928 part = XVECEXP (pattern, 0, i);
4929 if (part == reg_part || GET_CODE (part) == CLOBBER)
4931 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4932 && REG_P (SET_DEST (part)))
4933 ? SET_SRC (part) : part)))
4939 /* See if the only way in which INSN uses REG is by calling it, or by
4940 setting it while calling it. Set *SET to a SET rtx if the register
4944 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4950 reg2 = sfunc_uses_reg (insn);
4951 if (reg2 && REGNO (reg2) == REGNO (reg))
4953 pattern = single_set (insn);
4955 && REG_P (SET_DEST (pattern))
4956 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4962 /* We don't use rtx_equal_p because we don't care if the mode is
4964 pattern = single_set (insn);
4966 && REG_P (SET_DEST (pattern))
4967 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4973 par = PATTERN (insn);
4974 if (GET_CODE (par) == PARALLEL)
4975 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4977 part = XVECEXP (par, 0, i);
4978 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4981 return reg_mentioned_p (reg, SET_SRC (pattern));
4987 pattern = PATTERN (insn);
4989 if (GET_CODE (pattern) == PARALLEL)
4993 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4994 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4996 pattern = XVECEXP (pattern, 0, 0);
4999 if (GET_CODE (pattern) == SET)
5001 if (reg_mentioned_p (reg, SET_DEST (pattern)))
5003 /* We don't use rtx_equal_p, because we don't care if the
5004 mode is different. */
5005 if (!REG_P (SET_DEST (pattern))
5006 || REGNO (reg) != REGNO (SET_DEST (pattern)))
5012 pattern = SET_SRC (pattern);
5015 if (GET_CODE (pattern) != CALL
5016 || !MEM_P (XEXP (pattern, 0))
5017 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
5023 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5024 general registers. Bits 0..15 mean that the respective registers
5025 are used as inputs in the instruction. Bits 16..31 mean that the
5026 registers 0..15, respectively, are used as outputs, or are clobbered.
5027 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5029 regs_used (rtx x, int is_dest)
5037 code = GET_CODE (x);
5042 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
5043 << (REGNO (x) + is_dest));
5047 rtx y = SUBREG_REG (x);
5052 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
5054 subreg_regno_offset (REGNO (y),
5057 GET_MODE (x)) + is_dest));
5061 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
5063 /* If there was a return value, it must have been indicated with USE. */
5078 fmt = GET_RTX_FORMAT (code);
5080 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5085 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5086 used |= regs_used (XVECEXP (x, i, j), is_dest);
5088 else if (fmt[i] == 'e')
5089 used |= regs_used (XEXP (x, i), is_dest);
5094 /* Create an instruction that prevents redirection of a conditional branch
5095 to the destination of the JUMP with address ADDR.
5096 If the branch needs to be implemented as an indirect jump, try to find
5097 a scratch register for it.
5098 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5099 If any preceding insn that doesn't fit into a delay slot is good enough,
5100 pass 1. Pass 2 if a definite blocking insn is needed.
5101 -1 is used internally to avoid deep recursion.
5102 If a blocking instruction is made or recognized, return it. */
5105 gen_block_redirect (rtx jump, int addr, int need_block)
5108 rtx prev = prev_nonnote_insn (jump);
5111 /* First, check if we already have an instruction that satisfies our need. */
5112 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
5114 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
5116 if (GET_CODE (PATTERN (prev)) == USE
5117 || GET_CODE (PATTERN (prev)) == CLOBBER
5118 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5120 else if ((need_block &= ~1) < 0)
5122 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
5125 if (GET_CODE (PATTERN (jump)) == RETURN)
5129 /* Reorg even does nasty things with return insns that cause branches
5130 to go out of range - see find_end_label and callers. */
5131 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
5133 /* We can't use JUMP_LABEL here because it might be undefined
5134 when not optimizing. */
5135 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
5136 /* If the branch is out of range, try to find a scratch register for it. */
5138 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5142 /* Don't look for the stack pointer as a scratch register,
5143 it would cause trouble if an interrupt occurred. */
5144 unsigned attempt = 0x7fff, used;
5145 int jump_left = flag_expensive_optimizations + 1;
5147 /* It is likely that the most recent eligible instruction is wanted for
5148 the delay slot. Therefore, find out which registers it uses, and
5149 try to avoid using them. */
5151 for (scan = jump; (scan = PREV_INSN (scan)); )
5155 if (INSN_DELETED_P (scan))
5157 code = GET_CODE (scan);
5158 if (code == CODE_LABEL || code == JUMP_INSN)
5161 && GET_CODE (PATTERN (scan)) != USE
5162 && GET_CODE (PATTERN (scan)) != CLOBBER
5163 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5165 attempt &= ~regs_used (PATTERN (scan), 0);
5169 for (used = dead = 0, scan = JUMP_LABEL (jump);
5170 (scan = NEXT_INSN (scan)); )
5174 if (INSN_DELETED_P (scan))
5176 code = GET_CODE (scan);
5179 used |= regs_used (PATTERN (scan), 0);
5180 if (code == CALL_INSN)
5181 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5182 dead |= (used >> 16) & ~used;
5188 if (code == JUMP_INSN)
5190 if (jump_left-- && simplejump_p (scan))
5191 scan = JUMP_LABEL (scan);
5197 /* Mask out the stack pointer again, in case it was
5198 the only 'free' register we have found. */
5201 /* If the immediate destination is still in range, check for possible
5202 threading with a jump beyond the delay slot insn.
5203 Don't check if we are called recursively; the jump has been or will be
5204 checked in a different invocation then. */
5206 else if (optimize && need_block >= 0)
5208 rtx next = next_active_insn (next_active_insn (dest));
5209 if (next && JUMP_P (next)
5210 && GET_CODE (PATTERN (next)) == SET
5211 && recog_memoized (next) == CODE_FOR_jump_compact)
5213 dest = JUMP_LABEL (next);
5215 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5217 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5223 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5225 /* It would be nice if we could convert the jump into an indirect
5226 jump / far branch right now, and thus exposing all constituent
5227 instructions to further optimization. However, reorg uses
5228 simplejump_p to determine if there is an unconditional jump where
5229 it should try to schedule instructions from the target of the
5230 branch; simplejump_p fails for indirect jumps even if they have
5232 rtx insn = emit_insn_before (gen_indirect_jump_scratch
5233 (reg, GEN_INT (unspec_bbr_uid++)),
5235 /* ??? We would like this to have the scope of the jump, but that
5236 scope will change when a delay slot insn of an inner scope is added.
5237 Hence, after delay slot scheduling, we'll have to expect
5238 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5241 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
5242 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5245 else if (need_block)
5246 /* We can't use JUMP_LABEL here because it might be undefined
5247 when not optimizing. */
5248 return emit_insn_before (gen_block_branch_redirect
5249 (GEN_INT (unspec_bbr_uid++)),
5254 #define CONDJUMP_MIN -252
5255 #define CONDJUMP_MAX 262
5258 /* A label (to be placed) in front of the jump
5259 that jumps to our ultimate destination. */
5261 /* Where we are going to insert it if we cannot move the jump any farther,
5262 or the jump itself if we have picked up an existing jump. */
5264 /* The ultimate destination. */
5266 struct far_branch *prev;
5267 /* If the branch has already been created, its address;
5268 else the address of its first prospective user. */
5272 static void gen_far_branch (struct far_branch *);
5273 enum mdep_reorg_phase_e mdep_reorg_phase;
5275 gen_far_branch (struct far_branch *bp)
5277 rtx insn = bp->insert_place;
5279 rtx label = gen_label_rtx ();
5282 emit_label_after (label, insn);
5285 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5286 LABEL_NUSES (bp->far_label)++;
5289 jump = emit_jump_insn_after (gen_return (), insn);
5290 /* Emit a barrier so that reorg knows that any following instructions
5291 are not reachable via a fall-through path.
5292 But don't do this when not optimizing, since we wouldn't suppress the
5293 alignment for the barrier then, and could end up with out-of-range
5294 pc-relative loads. */
5296 emit_barrier_after (jump);
5297 emit_label_after (bp->near_label, insn);
5298 JUMP_LABEL (jump) = bp->far_label;
5299 ok = invert_jump (insn, label, 1);
5302 /* If we are branching around a jump (rather than a return), prevent
5303 reorg from using an insn from the jump target as the delay slot insn -
5304 when reorg did this, it pessimized code (we rather hide the delay slot)
5305 and it could cause branches to go out of range. */
5308 (gen_stuff_delay_slot
5309 (GEN_INT (unspec_bbr_uid++),
5310 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5312 /* Prevent reorg from undoing our splits. */
5313 gen_block_redirect (jump, bp->address += 2, 2);
5316 /* Fix up ADDR_DIFF_VECs. */
5318 fixup_addr_diff_vecs (rtx first)
5322 for (insn = first; insn; insn = NEXT_INSN (insn))
5324 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5327 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5329 pat = PATTERN (insn);
5330 vec_lab = XEXP (XEXP (pat, 0), 0);
5332 /* Search the matching casesi_jump_2. */
5333 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5337 prevpat = PATTERN (prev);
5338 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5340 x = XVECEXP (prevpat, 0, 1);
5341 if (GET_CODE (x) != USE)
5344 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5347 /* FIXME: This is a bug in the optimizer, but it seems harmless
5348 to just avoid panicing. */
5352 /* Emit the reference label of the braf where it belongs, right after
5353 the casesi_jump_2 (i.e. braf). */
5354 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5355 emit_label_after (braf_label, prev);
5357 /* Fix up the ADDR_DIF_VEC to be relative
5358 to the reference address of the braf. */
5359 XEXP (XEXP (pat, 0), 0) = braf_label;
5363 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5364 a barrier. Return the base 2 logarithm of the desired alignment. */
5366 barrier_align (rtx barrier_or_label)
5368 rtx next = next_real_insn (barrier_or_label), pat, prev;
5369 int slot, credit, jump_to_next = 0;
5374 pat = PATTERN (next);
5376 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5379 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5380 /* This is a barrier in front of a constant table. */
5383 prev = prev_real_insn (barrier_or_label);
5384 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5386 pat = PATTERN (prev);
5387 /* If this is a very small table, we want to keep the alignment after
5388 the table to the minimum for proper code alignment. */
5389 return ((optimize_size
5390 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5391 <= (unsigned) 1 << (CACHE_LOG - 2)))
5392 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5398 if (! TARGET_SH2 || ! optimize)
5399 return align_jumps_log;
5401 /* When fixing up pcloads, a constant table might be inserted just before
5402 the basic block that ends with the barrier. Thus, we can't trust the
5403 instruction lengths before that. */
5404 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5406 /* Check if there is an immediately preceding branch to the insn beyond
5407 the barrier. We must weight the cost of discarding useful information
5408 from the current cache line when executing this branch and there is
5409 an alignment, against that of fetching unneeded insn in front of the
5410 branch target when there is no alignment. */
5412 /* There are two delay_slot cases to consider. One is the simple case
5413 where the preceding branch is to the insn beyond the barrier (simple
5414 delay slot filling), and the other is where the preceding branch has
5415 a delay slot that is a duplicate of the insn after the barrier
5416 (fill_eager_delay_slots) and the branch is to the insn after the insn
5417 after the barrier. */
5419 /* PREV is presumed to be the JUMP_INSN for the barrier under
5420 investigation. Skip to the insn before it. */
5421 prev = prev_real_insn (prev);
5423 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5424 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5425 prev = prev_real_insn (prev))
5428 if (GET_CODE (PATTERN (prev)) == USE
5429 || GET_CODE (PATTERN (prev)) == CLOBBER)
5431 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5433 prev = XVECEXP (PATTERN (prev), 0, 1);
5434 if (INSN_UID (prev) == INSN_UID (next))
5436 /* Delay slot was filled with insn at jump target. */
5443 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5445 credit -= get_attr_length (prev);
5449 && JUMP_LABEL (prev))
5453 || next_real_insn (JUMP_LABEL (prev)) == next
5454 /* If relax_delay_slots() decides NEXT was redundant
5455 with some previous instruction, it will have
5456 redirected PREV's jump to the following insn. */
5457 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5458 /* There is no upper bound on redundant instructions
5459 that might have been skipped, but we must not put an
5460 alignment where none had been before. */
5461 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5463 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5464 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5465 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5467 rtx pat = PATTERN (prev);
5468 if (GET_CODE (pat) == PARALLEL)
5469 pat = XVECEXP (pat, 0, 0);
5470 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5476 return align_jumps_log;
5479 /* If we are inside a phony loop, almost any kind of label can turn up as the
5480 first one in the loop. Aligning a braf label causes incorrect switch
5481 destination addresses; we can detect braf labels because they are
5482 followed by a BARRIER.
5483 Applying loop alignment to small constant or switch tables is a waste
5484 of space, so we suppress this too. */
5486 sh_loop_align (rtx label)
5491 next = next_nonnote_insn (next);
5492 while (next && LABEL_P (next));
5496 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5497 || recog_memoized (next) == CODE_FOR_consttable_2)
5500 return align_loops_log;
5503 /* Do a final pass over the function, just before delayed branch
5509 rtx first, insn, mova = NULL_RTX;
5511 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5512 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5514 first = get_insns ();
5515 max_labelno_before_reorg = max_label_num ();
5517 /* We must split call insns before introducing `mova's. If we're
5518 optimizing, they'll have already been split. Otherwise, make
5519 sure we don't split them too late. */
5521 split_all_insns_noflow ();
5526 /* If relaxing, generate pseudo-ops to associate function calls with
5527 the symbols they call. It does no harm to not generate these
5528 pseudo-ops. However, when we can generate them, it enables to
5529 linker to potentially relax the jsr to a bsr, and eliminate the
5530 register load and, possibly, the constant pool entry. */
5532 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5535 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5536 own purposes. This works because none of the remaining passes
5537 need to look at them.
5539 ??? But it may break in the future. We should use a machine
5540 dependent REG_NOTE, or some other approach entirely. */
5541 for (insn = first; insn; insn = NEXT_INSN (insn))
5547 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5549 remove_note (insn, note);
5553 for (insn = first; insn; insn = NEXT_INSN (insn))
5555 rtx pattern, reg, link, set, scan, dies, label;
5556 int rescan = 0, foundinsn = 0;
5560 pattern = PATTERN (insn);
5562 if (GET_CODE (pattern) == PARALLEL)
5563 pattern = XVECEXP (pattern, 0, 0);
5564 if (GET_CODE (pattern) == SET)
5565 pattern = SET_SRC (pattern);
5567 if (GET_CODE (pattern) != CALL
5568 || !MEM_P (XEXP (pattern, 0)))
5571 reg = XEXP (XEXP (pattern, 0), 0);
5575 reg = sfunc_uses_reg (insn);
5583 /* Try scanning backward to find where the register is set. */
5585 for (scan = PREV_INSN (insn);
5586 scan && !LABEL_P (scan);
5587 scan = PREV_INSN (scan))
5589 if (! INSN_P (scan))
5592 if (! reg_mentioned_p (reg, scan))
5595 if (noncall_uses_reg (reg, scan, &set))
5608 /* The register is set at LINK. */
5610 /* We can only optimize the function call if the register is
5611 being set to a symbol. In theory, we could sometimes
5612 optimize calls to a constant location, but the assembler
5613 and linker do not support that at present. */
5614 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5615 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5618 /* Scan forward from LINK to the place where REG dies, and
5619 make sure that the only insns which use REG are
5620 themselves function calls. */
5622 /* ??? This doesn't work for call targets that were allocated
5623 by reload, since there may not be a REG_DEAD note for the
5627 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5631 /* Don't try to trace forward past a CODE_LABEL if we haven't
5632 seen INSN yet. Ordinarily, we will only find the setting insn
5633 if it is in the same basic block. However,
5634 cross-jumping can insert code labels in between the load and
5635 the call, and can result in situations where a single call
5636 insn may have two targets depending on where we came from. */
5638 if (LABEL_P (scan) && ! foundinsn)
5641 if (! INSN_P (scan))
5644 /* Don't try to trace forward past a JUMP. To optimize
5645 safely, we would have to check that all the
5646 instructions at the jump destination did not use REG. */
5651 if (! reg_mentioned_p (reg, scan))
5654 if (noncall_uses_reg (reg, scan, &scanset))
5661 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5663 /* There is a function call to this register other
5664 than the one we are checking. If we optimize
5665 this call, we need to rescan again below. */
5669 /* ??? We shouldn't have to worry about SCANSET here.
5670 We should just be able to check for a REG_DEAD note
5671 on a function call. However, the REG_DEAD notes are
5672 apparently not dependable around libcalls; c-torture
5673 execute/920501-2 is a test case. If SCANSET is set,
5674 then this insn sets the register, so it must have
5675 died earlier. Unfortunately, this will only handle
5676 the cases in which the register is, in fact, set in a
5679 /* ??? We shouldn't have to use FOUNDINSN here.
5680 This dates back to when we used LOG_LINKS to find
5681 the most recent insn which sets the register. */
5685 || find_reg_note (scan, REG_DEAD, reg)))
5694 /* Either there was a branch, or some insn used REG
5695 other than as a function call address. */
5699 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5700 on the insn which sets the register, and on each call insn
5701 which uses the register. In final_prescan_insn we look for
5702 the REG_LABEL_OPERAND notes, and output the appropriate label
5705 label = gen_label_rtx ();
5706 add_reg_note (link, REG_LABEL_OPERAND, label);
5707 add_reg_note (insn, REG_LABEL_OPERAND, label);
5715 scan = NEXT_INSN (scan);
5718 && reg_mentioned_p (reg, scan))
5719 || ((reg2 = sfunc_uses_reg (scan))
5720 && REGNO (reg2) == REGNO (reg))))
5721 add_reg_note (scan, REG_LABEL_OPERAND, label);
5723 while (scan != dies);
5729 fixup_addr_diff_vecs (first);
5733 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5734 shorten_branches (first);
5737 /* Scan the function looking for move instructions which have to be
5738 changed to pc-relative loads and insert the literal tables. */
5739 label_ref_list_pool = create_alloc_pool ("label references list",
5740 sizeof (struct label_ref_list_d),
5742 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5743 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5747 /* ??? basic block reordering can move a switch table dispatch
5748 below the switch table. Check if that has happened.
5749 We only have the addresses available when optimizing; but then,
5750 this check shouldn't be needed when not optimizing. */
5751 if (!untangle_mova (&num_mova, &mova, insn))
5757 else if (JUMP_P (insn)
5758 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5760 /* ??? loop invariant motion can also move a mova out of a
5761 loop. Since loop does this code motion anyway, maybe we
5762 should wrap UNSPEC_MOVA into a CONST, so that reload can
5765 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5766 || (prev_nonnote_insn (insn)
5767 == XEXP (MOVA_LABELREF (mova), 0))))
5774 /* Some code might have been inserted between the mova and
5775 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5776 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5777 total += get_attr_length (scan);
5779 /* range of mova is 1020, add 4 because pc counts from address of
5780 second instruction after this one, subtract 2 in case pc is 2
5781 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5782 cancels out with alignment effects of the mova itself. */
5785 /* Change the mova into a load, and restart scanning
5786 there. broken_move will then return true for mova. */
5791 if (broken_move (insn)
5792 || (NONJUMP_INSN_P (insn)
5793 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5796 /* Scan ahead looking for a barrier to stick the constant table
5798 rtx barrier = find_barrier (num_mova, mova, insn);
5799 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5800 int need_aligned_label = 0;
5802 if (num_mova && ! mova_p (mova))
5804 /* find_barrier had to change the first mova into a
5805 pcload; thus, we have to start with this new pcload. */
5809 /* Now find all the moves between the points and modify them. */
5810 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5814 if (NONJUMP_INSN_P (scan)
5815 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5816 need_aligned_label = 1;
5817 if (broken_move (scan))
5819 rtx *patp = &PATTERN (scan), pat = *patp;
5823 enum machine_mode mode;
5825 if (GET_CODE (pat) == PARALLEL)
5826 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5827 src = SET_SRC (pat);
5828 dst = SET_DEST (pat);
5829 mode = GET_MODE (dst);
5831 if (mode == SImode && hi_const (src)
5832 && REGNO (dst) != FPUL_REG)
5837 while (GET_CODE (dst) == SUBREG)
5839 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5840 GET_MODE (SUBREG_REG (dst)),
5843 dst = SUBREG_REG (dst);
5845 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5847 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5849 /* This must be an insn that clobbers r0. */
5850 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5851 XVECLEN (PATTERN (scan), 0)
5853 rtx clobber = *clobberp;
5855 gcc_assert (GET_CODE (clobber) == CLOBBER
5856 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5859 && reg_set_between_p (r0_rtx, last_float_move, scan))
5863 && GET_MODE_SIZE (mode) != 4
5864 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5866 lab = add_constant (src, mode, last_float);
5868 emit_insn_before (gen_mova (lab), scan);
5871 /* There will be a REG_UNUSED note for r0 on
5872 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5873 lest reorg:mark_target_live_regs will not
5874 consider r0 to be used, and we end up with delay
5875 slot insn in front of SCAN that clobbers r0. */
5877 = find_regno_note (last_float_move, REG_UNUSED, 0);
5879 /* If we are not optimizing, then there may not be
5882 PUT_REG_NOTE_KIND (note, REG_INC);
5884 *last_float_addr = r0_inc_rtx;
5886 last_float_move = scan;
5888 newsrc = gen_const_mem (mode,
5889 (((TARGET_SH4 && ! TARGET_FMOVD)
5890 || REGNO (dst) == FPUL_REG)
5893 last_float_addr = &XEXP (newsrc, 0);
5895 /* Remove the clobber of r0. */
5896 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5897 gen_rtx_SCRATCH (Pmode));
5899 /* This is a mova needing a label. Create it. */
5900 else if (GET_CODE (src) == UNSPEC
5901 && XINT (src, 1) == UNSPEC_MOVA
5902 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5904 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5905 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5906 newsrc = gen_rtx_UNSPEC (SImode,
5907 gen_rtvec (1, newsrc),
5912 lab = add_constant (src, mode, 0);
5913 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5914 newsrc = gen_const_mem (mode, newsrc);
5916 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5917 INSN_CODE (scan) = -1;
5920 dump_table (need_aligned_label ? insn : 0, barrier);
5924 free_alloc_pool (label_ref_list_pool);
5925 for (insn = first; insn; insn = NEXT_INSN (insn))
5926 PUT_MODE (insn, VOIDmode);
5928 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5929 INSN_ADDRESSES_FREE ();
5930 split_branches (first);
5932 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5933 also has an effect on the register that holds the address of the sfunc.
5934 Insert an extra dummy insn in front of each sfunc that pretends to
5935 use this register. */
5936 if (flag_delayed_branch)
5938 for (insn = first; insn; insn = NEXT_INSN (insn))
5940 rtx reg = sfunc_uses_reg (insn);
5944 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5948 /* fpscr is not actually a user variable, but we pretend it is for the
5949 sake of the previous optimization passes, since we want it handled like
5950 one. However, we don't have any debugging information for it, so turn
5951 it into a non-user variable now. */
5953 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5955 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5959 get_dest_uid (rtx label, int max_uid)
5961 rtx dest = next_real_insn (label);
5964 /* This can happen for an undefined label. */
5966 dest_uid = INSN_UID (dest);
5967 /* If this is a newly created branch redirection blocking instruction,
5968 we cannot index the branch_uid or insn_addresses arrays with its
5969 uid. But then, we won't need to, because the actual destination is
5970 the following branch. */
5971 while (dest_uid >= max_uid)
5973 dest = NEXT_INSN (dest);
5974 dest_uid = INSN_UID (dest);
5976 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5981 /* Split condbranches that are out of range. Also add clobbers for
5982 scratch registers that are needed in far jumps.
5983 We do this before delay slot scheduling, so that it can take our
5984 newly created instructions into account. It also allows us to
5985 find branches with common targets more easily. */
5988 split_branches (rtx first)
5991 struct far_branch **uid_branch, *far_branch_list = 0;
5992 int max_uid = get_max_uid ();
5995 /* Find out which branches are out of range. */
5996 shorten_branches (first);
5998 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5999 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
6001 for (insn = first; insn; insn = NEXT_INSN (insn))
6002 if (! INSN_P (insn))
6004 else if (INSN_DELETED_P (insn))
6006 /* Shorten_branches would split this instruction again,
6007 so transform it into a note. */
6008 SET_INSN_DELETED (insn);
6010 else if (JUMP_P (insn)
6011 /* Don't mess with ADDR_DIFF_VEC */
6012 && (GET_CODE (PATTERN (insn)) == SET
6013 || GET_CODE (PATTERN (insn)) == RETURN))
6015 enum attr_type type = get_attr_type (insn);
6016 if (type == TYPE_CBRANCH)
6020 if (get_attr_length (insn) > 4)
6022 rtx src = SET_SRC (PATTERN (insn));
6023 rtx olabel = XEXP (XEXP (src, 1), 0);
6024 int addr = INSN_ADDRESSES (INSN_UID (insn));
6026 int dest_uid = get_dest_uid (olabel, max_uid);
6027 struct far_branch *bp = uid_branch[dest_uid];
6029 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6030 the label if the LABEL_NUSES count drops to zero. There is
6031 always a jump_optimize pass that sets these values, but it
6032 proceeds to delete unreferenced code, and then if not
6033 optimizing, to un-delete the deleted instructions, thus
6034 leaving labels with too low uses counts. */
6037 JUMP_LABEL (insn) = olabel;
6038 LABEL_NUSES (olabel)++;
6042 bp = (struct far_branch *) alloca (sizeof *bp);
6043 uid_branch[dest_uid] = bp;
6044 bp->prev = far_branch_list;
6045 far_branch_list = bp;
6047 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
6048 LABEL_NUSES (bp->far_label)++;
6052 label = bp->near_label;
6053 if (! label && bp->address - addr >= CONDJUMP_MIN)
6055 rtx block = bp->insert_place;
6057 if (GET_CODE (PATTERN (block)) == RETURN)
6058 block = PREV_INSN (block);
6060 block = gen_block_redirect (block,
6062 label = emit_label_after (gen_label_rtx (),
6064 bp->near_label = label;
6066 else if (label && ! NEXT_INSN (label))
6068 if (addr + 2 - bp->address <= CONDJUMP_MAX)
6069 bp->insert_place = insn;
6071 gen_far_branch (bp);
6075 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
6077 bp->near_label = label = gen_label_rtx ();
6078 bp->insert_place = insn;
6081 ok = redirect_jump (insn, label, 0);
6086 /* get_attr_length (insn) == 2 */
6087 /* Check if we have a pattern where reorg wants to redirect
6088 the branch to a label from an unconditional branch that
6090 /* We can't use JUMP_LABEL here because it might be undefined
6091 when not optimizing. */
6092 /* A syntax error might cause beyond to be NULL_RTX. */
6094 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
6099 || ((beyond = next_active_insn (beyond))
6100 && JUMP_P (beyond)))
6101 && GET_CODE (PATTERN (beyond)) == SET
6102 && recog_memoized (beyond) == CODE_FOR_jump_compact
6104 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
6105 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6107 gen_block_redirect (beyond,
6108 INSN_ADDRESSES (INSN_UID (beyond)), 1);
6111 next = next_active_insn (insn);
6115 || ((next = next_active_insn (next))
6117 && GET_CODE (PATTERN (next)) == SET
6118 && recog_memoized (next) == CODE_FOR_jump_compact
6120 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
6121 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6123 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
6125 else if (type == TYPE_JUMP || type == TYPE_RETURN)
6127 int addr = INSN_ADDRESSES (INSN_UID (insn));
6130 struct far_branch *bp;
6132 if (type == TYPE_JUMP)
6134 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
6135 dest_uid = get_dest_uid (far_label, max_uid);
6138 /* Parse errors can lead to labels outside
6140 if (! NEXT_INSN (far_label))
6145 JUMP_LABEL (insn) = far_label;
6146 LABEL_NUSES (far_label)++;
6148 redirect_jump (insn, NULL_RTX, 1);
6152 bp = uid_branch[dest_uid];
6155 bp = (struct far_branch *) alloca (sizeof *bp);
6156 uid_branch[dest_uid] = bp;
6157 bp->prev = far_branch_list;
6158 far_branch_list = bp;
6160 bp->far_label = far_label;
6162 LABEL_NUSES (far_label)++;
6164 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6165 if (addr - bp->address <= CONDJUMP_MAX)
6166 emit_label_after (bp->near_label, PREV_INSN (insn));
6169 gen_far_branch (bp);
6175 bp->insert_place = insn;
6177 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6179 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6182 /* Generate all pending far branches,
6183 and free our references to the far labels. */
6184 while (far_branch_list)
6186 if (far_branch_list->near_label
6187 && ! NEXT_INSN (far_branch_list->near_label))
6188 gen_far_branch (far_branch_list);
6190 && far_branch_list->far_label
6191 && ! --LABEL_NUSES (far_branch_list->far_label))
6192 delete_insn (far_branch_list->far_label);
6193 far_branch_list = far_branch_list->prev;
6196 /* Instruction length information is no longer valid due to the new
6197 instructions that have been generated. */
6198 init_insn_lengths ();
6201 /* Dump out instruction addresses, which is useful for debugging the
6202 constant pool table stuff.
6204 If relaxing, output the label and pseudo-ops used to link together
6205 calls and the instruction which set the registers. */
6207 /* ??? The addresses printed by this routine for insns are nonsense for
6208 insns which are inside of a sequence where none of the inner insns have
6209 variable length. This is because the second pass of shorten_branches
6210 does not bother to update them. */
6213 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6214 int noperands ATTRIBUTE_UNUSED)
6216 if (TARGET_DUMPISIZE)
6217 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6223 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
6228 pattern = PATTERN (insn);
6229 if (GET_CODE (pattern) == PARALLEL)
6230 pattern = XVECEXP (pattern, 0, 0);
6231 switch (GET_CODE (pattern))
6234 if (GET_CODE (SET_SRC (pattern)) != CALL
6235 && get_attr_type (insn) != TYPE_SFUNC)
6237 targetm.asm_out.internal_label
6238 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6241 /* else FALLTHROUGH */
6243 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6244 CODE_LABEL_NUMBER (XEXP (note, 0)));
6254 /* Dump out any constants accumulated in the final pass. These will
6258 output_jump_label_table (void)
6264 fprintf (asm_out_file, "\t.align 2\n");
6265 for (i = 0; i < pool_size; i++)
6267 pool_node *p = &pool_vector[i];
6269 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6270 CODE_LABEL_NUMBER (p->label));
6271 output_asm_insn (".long %O0", &p->value);
6279 /* A full frame looks like:
6283 [ if current_function_anonymous_args
6296 local-0 <- fp points here. */
6298 /* Number of bytes pushed for anonymous args, used to pass information
6299 between expand_prologue and expand_epilogue. */
6301 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6302 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6303 for an epilogue and a negative value means that it's for a sibcall
6304 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6305 all the registers that are about to be restored, and hence dead. */
6308 output_stack_adjust (int size, rtx reg, int epilogue_p,
6309 HARD_REG_SET *live_regs_mask, bool frame_p)
6311 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6314 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6316 /* This test is bogus, as output_stack_adjust is used to re-align the
6319 gcc_assert (!(size % align));
6322 if (CONST_OK_FOR_ADD (size))
6323 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6324 /* Try to do it with two partial adjustments; however, we must make
6325 sure that the stack is properly aligned at all times, in case
6326 an interrupt occurs between the two partial adjustments. */
6327 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6328 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6330 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6331 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6337 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6340 /* If TEMP is invalid, we could temporarily save a general
6341 register to MACL. However, there is currently no need
6342 to handle this case, so just die when we see it. */
6344 || current_function_interrupt
6345 || ! call_really_used_regs[temp] || fixed_regs[temp])
6347 if (temp < 0 && ! current_function_interrupt
6348 && (TARGET_SHMEDIA || epilogue_p >= 0))
6351 COPY_HARD_REG_SET (temps, call_used_reg_set);
6352 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6356 if (crtl->return_rtx)
6358 enum machine_mode mode;
6359 mode = GET_MODE (crtl->return_rtx);
6360 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6361 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6363 for (i = 0; i < nreg; i++)
6364 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6365 if (crtl->calls_eh_return)
6367 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6368 for (i = 0; i <= 3; i++)
6369 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6372 if (TARGET_SHMEDIA && epilogue_p < 0)
6373 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6374 CLEAR_HARD_REG_BIT (temps, i);
6375 if (epilogue_p <= 0)
6377 for (i = FIRST_PARM_REG;
6378 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6379 CLEAR_HARD_REG_BIT (temps, i);
6380 if (cfun->static_chain_decl != NULL)
6381 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6383 temp = scavenge_reg (&temps);
6385 if (temp < 0 && live_regs_mask)
6389 COPY_HARD_REG_SET (temps, *live_regs_mask);
6390 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6391 temp = scavenge_reg (&temps);
6395 rtx adj_reg, tmp_reg, mem;
6397 /* If we reached here, the most likely case is the (sibcall)
6398 epilogue for non SHmedia. Put a special push/pop sequence
6399 for such case as the last resort. This looks lengthy but
6400 would not be problem because it seems to be very
6403 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6406 /* ??? There is still the slight possibility that r4 or
6407 r5 have been reserved as fixed registers or assigned
6408 as global registers, and they change during an
6409 interrupt. There are possible ways to handle this:
6411 - If we are adjusting the frame pointer (r14), we can do
6412 with a single temp register and an ordinary push / pop
6414 - Grab any call-used or call-saved registers (i.e. not
6415 fixed or globals) for the temps we need. We might
6416 also grab r14 if we are adjusting the stack pointer.
6417 If we can't find enough available registers, issue
6418 a diagnostic and die - the user must have reserved
6419 way too many registers.
6420 But since all this is rather unlikely to happen and
6421 would require extra testing, we just die if r4 / r5
6422 are not available. */
6423 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6424 && !global_regs[4] && !global_regs[5]);
6426 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6427 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6428 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6429 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6430 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6431 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6432 emit_move_insn (mem, tmp_reg);
6433 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6434 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6435 emit_move_insn (mem, tmp_reg);
6436 emit_move_insn (reg, adj_reg);
6437 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6438 emit_move_insn (adj_reg, mem);
6439 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6440 emit_move_insn (tmp_reg, mem);
6441 /* Tell flow the insns that pop r4/r5 aren't dead. */
6446 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6448 /* If SIZE is negative, subtract the positive value.
6449 This sometimes allows a constant pool entry to be shared
6450 between prologue and epilogue code. */
6453 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6454 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6458 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6459 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6462 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6463 gen_rtx_SET (VOIDmode, reg,
6464 gen_rtx_PLUS (SImode, reg,
6474 RTX_FRAME_RELATED_P (x) = 1;
6478 /* Output RTL to push register RN onto the stack. */
6485 x = gen_push_fpul ();
6486 else if (rn == FPSCR_REG)
6487 x = gen_push_fpscr ();
6488 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6489 && FP_OR_XD_REGISTER_P (rn))
6491 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6493 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6495 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6496 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6498 x = gen_push (gen_rtx_REG (SImode, rn));
6501 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6505 /* Output RTL to pop register RN from the stack. */
6512 x = gen_pop_fpul ();
6513 else if (rn == FPSCR_REG)
6514 x = gen_pop_fpscr ();
6515 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6516 && FP_OR_XD_REGISTER_P (rn))
6518 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6520 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6522 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6523 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6525 x = gen_pop (gen_rtx_REG (SImode, rn));
6528 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6531 /* Generate code to push the regs specified in the mask. */
6534 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6536 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6539 /* Push PR last; this gives better latencies after the prologue, and
6540 candidates for the return delay slot when there are no general
6541 registers pushed. */
6542 for (; i < FIRST_PSEUDO_REGISTER; i++)
6544 /* If this is an interrupt handler, and the SZ bit varies,
6545 and we have to push any floating point register, we need
6546 to switch to the correct precision first. */
6547 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6548 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6550 HARD_REG_SET unsaved;
6553 COMPL_HARD_REG_SET (unsaved, *mask);
6554 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6558 && (i != FPSCR_REG || ! skip_fpscr)
6559 && TEST_HARD_REG_BIT (*mask, i))
6561 /* If the ISR has RESBANK attribute assigned, don't push any of
6562 the following registers - R0-R14, MACH, MACL and GBR. */
6563 if (! (sh_cfun_resbank_handler_p ()
6564 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6572 /* Push banked registers last to improve delay slot opportunities. */
6573 if (interrupt_handler)
6575 bool use_movml = false;
6579 unsigned int count = 0;
6581 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6582 if (TEST_HARD_REG_BIT (*mask, i))
6587 /* Use movml when all banked registers are pushed. */
6588 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6594 rtx x, mem, reg, set;
6595 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6597 /* We must avoid scheduling multiple store insn with another
6599 emit_insn (gen_blockage ());
6600 x = gen_movml_push_banked (sp_reg);
6602 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6604 mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4));
6605 reg = gen_rtx_REG (SImode, i);
6606 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg));
6609 set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32));
6610 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6611 emit_insn (gen_blockage ());
6614 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6615 if (TEST_HARD_REG_BIT (*mask, i))
6619 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6620 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6624 /* Calculate how much extra space is needed to save all callee-saved
6626 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6629 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6632 int stack_space = 0;
6633 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6635 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6636 if ((! call_really_used_regs[reg] || interrupt_handler)
6637 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6638 /* Leave space to save this target register on the stack,
6639 in case target register allocation wants to use it. */
6640 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6644 /* Decide whether we should reserve space for callee-save target registers,
6645 in case target register allocation wants to use them. REGS_SAVED is
6646 the space, in bytes, that is already required for register saves.
6647 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6650 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6651 HARD_REG_SET *live_regs_mask)
6655 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6658 /* Decide how much space to reserve for callee-save target registers
6659 in case target register allocation wants to use them.
6660 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6663 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6665 if (shmedia_space_reserved_for_target_registers)
6666 return shmedia_target_regs_stack_space (live_regs_mask);
6671 /* Work out the registers which need to be saved, both as a mask and a
6672 count of saved words. Return the count.
6674 If doing a pragma interrupt function, then push all regs used by the
6675 function, and if we call another function (we can tell by looking at PR),
6676 make sure that all the regs it clobbers are safe too. */
6679 calc_live_regs (HARD_REG_SET *live_regs_mask)
6684 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6685 bool nosave_low_regs;
6686 int pr_live, has_call;
6688 attrs = DECL_ATTRIBUTES (current_function_decl);
6689 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6690 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6691 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6692 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6694 CLEAR_HARD_REG_SET (*live_regs_mask);
6695 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6696 && df_regs_ever_live_p (FPSCR_REG))
6697 target_flags &= ~MASK_FPU_SINGLE;
6698 /* If we can save a lot of saves by switching to double mode, do that. */
6699 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6700 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6701 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6702 && (! call_really_used_regs[reg]
6703 || interrupt_handler)
6706 target_flags &= ~MASK_FPU_SINGLE;
6709 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6710 knows how to use it. That means the pseudo originally allocated for
6711 the initial value can become the PR_MEDIA_REG hard register, as seen for
6712 execute/20010122-1.c:test9. */
6714 /* ??? this function is called from initial_elimination_offset, hence we
6715 can't use the result of sh_media_register_for_return here. */
6716 pr_live = sh_pr_n_sets ();
6719 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6720 pr_live = (pr_initial
6721 ? (!REG_P (pr_initial)
6722 || REGNO (pr_initial) != (PR_REG))
6723 : df_regs_ever_live_p (PR_REG));
6724 /* For Shcompact, if not optimizing, we end up with a memory reference
6725 using the return address pointer for __builtin_return_address even
6726 though there is no actual need to put the PR register on the stack. */
6727 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6729 /* Force PR to be live if the prologue has to call the SHmedia
6730 argument decoder or register saver. */
6731 if (TARGET_SHCOMPACT
6732 && ((crtl->args.info.call_cookie
6733 & ~ CALL_COOKIE_RET_TRAMP (1))
6734 || crtl->saves_all_registers))
6736 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6737 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6739 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6742 ? (/* Need to save all the regs ever live. */
6743 (df_regs_ever_live_p (reg)
6744 || (call_really_used_regs[reg]
6745 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6746 || reg == PIC_OFFSET_TABLE_REGNUM)
6748 || (TARGET_SHMEDIA && has_call
6749 && REGISTER_NATURAL_MODE (reg) == SImode
6750 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6751 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6752 && reg != RETURN_ADDRESS_POINTER_REGNUM
6753 && reg != T_REG && reg != GBR_REG
6754 /* Push fpscr only on targets which have FPU */
6755 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6756 : (/* Only push those regs which are used and need to be saved. */
6759 && crtl->args.info.call_cookie
6760 && reg == PIC_OFFSET_TABLE_REGNUM)
6761 || (df_regs_ever_live_p (reg)
6762 && ((!call_really_used_regs[reg]
6763 && !(reg != PIC_OFFSET_TABLE_REGNUM
6764 && fixed_regs[reg] && call_used_regs[reg]))
6765 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6766 || (crtl->calls_eh_return
6767 && (reg == EH_RETURN_DATA_REGNO (0)
6768 || reg == EH_RETURN_DATA_REGNO (1)
6769 || reg == EH_RETURN_DATA_REGNO (2)
6770 || reg == EH_RETURN_DATA_REGNO (3)))
6771 || ((reg == MACL_REG || reg == MACH_REG)
6772 && df_regs_ever_live_p (reg)
6773 && sh_cfun_attr_renesas_p ())
6776 SET_HARD_REG_BIT (*live_regs_mask, reg);
6777 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6779 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6780 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6782 if (FP_REGISTER_P (reg))
6784 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6786 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6787 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6790 else if (XD_REGISTER_P (reg))
6792 /* Must switch to double mode to access these registers. */
6793 target_flags &= ~MASK_FPU_SINGLE;
6797 if (nosave_low_regs && reg == R8_REG)
6800 /* If we have a target register optimization pass after prologue / epilogue
6801 threading, we need to assume all target registers will be live even if
6803 if (flag_branch_target_load_optimize2
6804 && TARGET_SAVE_ALL_TARGET_REGS
6805 && shmedia_space_reserved_for_target_registers)
6806 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6807 if ((! call_really_used_regs[reg] || interrupt_handler)
6808 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6810 SET_HARD_REG_BIT (*live_regs_mask, reg);
6811 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6813 /* If this is an interrupt handler, we don't have any call-clobbered
6814 registers we can conveniently use for target register save/restore.
6815 Make sure we save at least one general purpose register when we need
6816 to save target registers. */
6817 if (interrupt_handler
6818 && hard_reg_set_intersect_p (*live_regs_mask,
6819 reg_class_contents[TARGET_REGS])
6820 && ! hard_reg_set_intersect_p (*live_regs_mask,
6821 reg_class_contents[GENERAL_REGS]))
6823 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6824 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6830 /* Code to generate prologue and epilogue sequences */
6832 /* PUSHED is the number of bytes that are being pushed on the
6833 stack for register saves. Return the frame size, padded
6834 appropriately so that the stack stays properly aligned. */
6835 static HOST_WIDE_INT
6836 rounded_frame_size (int pushed)
6838 HOST_WIDE_INT size = get_frame_size ();
6839 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6841 if (ACCUMULATE_OUTGOING_ARGS)
6842 size += crtl->outgoing_args_size;
6844 return ((size + pushed + align - 1) & -align) - pushed;
6847 /* Choose a call-clobbered target-branch register that remains
6848 unchanged along the whole function. We set it up as the return
6849 value in the prologue. */
6851 sh_media_register_for_return (void)
6856 if (! current_function_is_leaf)
6858 if (lookup_attribute ("interrupt_handler",
6859 DECL_ATTRIBUTES (current_function_decl)))
6861 if (sh_cfun_interrupt_handler_p ())
6864 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6866 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6867 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6873 /* The maximum registers we need to save are:
6874 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6875 - 32 floating point registers (for each pair, we save none,
6876 one single precision value, or a double precision value).
6877 - 8 target registers
6878 - add 1 entry for a delimiter. */
6879 #define MAX_SAVED_REGS (62+32+8)
6881 typedef struct save_entry_s
6890 /* There will be a delimiter entry with VOIDmode both at the start and the
6891 end of a filled in schedule. The end delimiter has the offset of the
6892 save with the smallest (i.e. most negative) offset. */
6893 typedef struct save_schedule_s
6895 save_entry entries[MAX_SAVED_REGS + 2];
6896 int temps[MAX_TEMPS+1];
6899 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6900 use reverse order. Returns the last entry written to (not counting
6901 the delimiter). OFFSET_BASE is a number to be added to all offset
6905 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6909 save_entry *entry = schedule->entries;
6913 if (! current_function_interrupt)
6914 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6915 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6916 && ! FUNCTION_ARG_REGNO_P (i)
6917 && i != FIRST_RET_REG
6918 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6919 && ! (crtl->calls_eh_return
6920 && (i == EH_RETURN_STACKADJ_REGNO
6921 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6922 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6923 schedule->temps[tmpx++] = i;
6925 entry->mode = VOIDmode;
6926 entry->offset = offset_base;
6928 /* We loop twice: first, we save 8-byte aligned registers in the
6929 higher addresses, that are known to be aligned. Then, we
6930 proceed to saving 32-bit registers that don't need 8-byte
6932 If this is an interrupt function, all registers that need saving
6933 need to be saved in full. moreover, we need to postpone saving
6934 target registers till we have saved some general purpose registers
6935 we can then use as scratch registers. */
6936 offset = offset_base;
6937 for (align = 1; align >= 0; align--)
6939 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6940 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6942 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6945 if (current_function_interrupt)
6947 if (TARGET_REGISTER_P (i))
6949 if (GENERAL_REGISTER_P (i))
6952 if (mode == SFmode && (i % 2) == 1
6953 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6954 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6961 /* If we're doing the aligned pass and this is not aligned,
6962 or we're doing the unaligned pass and this is aligned,
6964 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6968 if (current_function_interrupt
6969 && GENERAL_REGISTER_P (i)
6970 && tmpx < MAX_TEMPS)
6971 schedule->temps[tmpx++] = i;
6973 offset -= GET_MODE_SIZE (mode);
6976 entry->offset = offset;
6979 if (align && current_function_interrupt)
6980 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6981 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6983 offset -= GET_MODE_SIZE (DImode);
6985 entry->mode = DImode;
6986 entry->offset = offset;
6991 entry->mode = VOIDmode;
6992 entry->offset = offset;
6993 schedule->temps[tmpx] = -1;
6998 sh_expand_prologue (void)
7000 HARD_REG_SET live_regs_mask;
7003 int save_flags = target_flags;
7007 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
7009 current_function_interrupt = sh_cfun_interrupt_handler_p ();
7011 /* We have pretend args if we had an object sent partially in registers
7012 and partially on the stack, e.g. a large structure. */
7013 pretend_args = crtl->args.pretend_args_size;
7014 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
7015 && (NPARM_REGS(SImode)
7016 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
7019 output_stack_adjust (-pretend_args
7020 - crtl->args.info.stack_regs * 8,
7021 stack_pointer_rtx, 0, NULL, true);
7022 stack_usage = pretend_args + crtl->args.info.stack_regs * 8;
7024 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
7025 /* We're going to use the PIC register to load the address of the
7026 incoming-argument decoder and/or of the return trampoline from
7027 the GOT, so make sure the PIC register is preserved and
7029 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7031 if (TARGET_SHCOMPACT
7032 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7036 /* First, make all registers with incoming arguments that will
7037 be pushed onto the stack live, so that register renaming
7038 doesn't overwrite them. */
7039 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
7040 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
7041 >= NPARM_REGS (SImode) - reg)
7042 for (; reg < NPARM_REGS (SImode); reg++)
7043 emit_insn (gen_shcompact_preserve_incoming_args
7044 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
7045 else if (CALL_COOKIE_INT_REG_GET
7046 (crtl->args.info.call_cookie, reg) == 1)
7047 emit_insn (gen_shcompact_preserve_incoming_args
7048 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
7050 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
7052 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
7053 GEN_INT (crtl->args.info.call_cookie));
7054 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
7055 gen_rtx_REG (SImode, R0_REG));
7057 else if (TARGET_SHMEDIA)
7059 int tr = sh_media_register_for_return ();
7062 emit_move_insn (gen_rtx_REG (DImode, tr),
7063 gen_rtx_REG (DImode, PR_MEDIA_REG));
7066 /* Emit the code for SETUP_VARARGS. */
7069 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7071 /* Push arg regs as if they'd been provided by caller in stack. */
7072 for (i = 0; i < NPARM_REGS(SImode); i++)
7074 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
7076 if (i >= (NPARM_REGS(SImode)
7077 - crtl->args.info.arg_count[(int) SH_ARG_INT]
7081 stack_usage += GET_MODE_SIZE (SImode);
7086 /* If we're supposed to switch stacks at function entry, do so now. */
7090 /* The argument specifies a variable holding the address of the
7091 stack the interrupt function should switch to/from at entry/exit. */
7092 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
7094 = ggc_strdup (TREE_STRING_POINTER (arg));
7095 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
7097 lab = add_constant (sp_switch, SImode, 0);
7098 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
7099 newsrc = gen_const_mem (SImode, newsrc);
7101 emit_insn (gen_sp_switch_1 (newsrc));
7104 d = calc_live_regs (&live_regs_mask);
7105 /* ??? Maybe we could save some switching if we can move a mode switch
7106 that already happens to be at the function start into the prologue. */
7107 if (target_flags != save_flags && ! current_function_interrupt)
7108 emit_insn (gen_toggle_sz ());
7112 int offset_base, offset;
7114 int offset_in_r0 = -1;
7116 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7117 int total_size, save_size;
7118 save_schedule schedule;
7122 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
7123 && ! current_function_interrupt)
7124 r0 = gen_rtx_REG (Pmode, R0_REG);
7126 /* D is the actual number of bytes that we need for saving registers,
7127 however, in initial_elimination_offset we have committed to using
7128 an additional TREGS_SPACE amount of bytes - in order to keep both
7129 addresses to arguments supplied by the caller and local variables
7130 valid, we must keep this gap. Place it between the incoming
7131 arguments and the actually saved registers in a bid to optimize
7132 locality of reference. */
7133 total_size = d + tregs_space;
7134 total_size += rounded_frame_size (total_size);
7135 save_size = total_size - rounded_frame_size (d);
7136 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
7137 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7138 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
7140 /* If adjusting the stack in a single step costs nothing extra, do so.
7141 I.e. either if a single addi is enough, or we need a movi anyway,
7142 and we don't exceed the maximum offset range (the test for the
7143 latter is conservative for simplicity). */
7145 && (CONST_OK_FOR_I10 (-total_size)
7146 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
7147 && total_size <= 2044)))
7148 d_rounding = total_size - save_size;
7150 offset_base = d + d_rounding;
7152 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
7154 stack_usage += save_size + d_rounding;
7156 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
7157 tmp_pnt = schedule.temps;
7158 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7160 enum machine_mode mode = (enum machine_mode) entry->mode;
7161 unsigned int reg = entry->reg;
7162 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
7165 offset = entry->offset;
7167 reg_rtx = gen_rtx_REG (mode, reg);
7169 mem_rtx = gen_frame_mem (mode,
7170 gen_rtx_PLUS (Pmode,
7174 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7180 if (HAVE_PRE_DECREMENT
7181 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
7182 || mem_rtx == NULL_RTX
7183 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7185 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
7187 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
7192 offset += GET_MODE_SIZE (mode);
7196 if (mem_rtx != NULL_RTX)
7199 if (offset_in_r0 == -1)
7201 emit_move_insn (r0, GEN_INT (offset));
7202 offset_in_r0 = offset;
7204 else if (offset != offset_in_r0)
7209 GEN_INT (offset - offset_in_r0)));
7210 offset_in_r0 += offset - offset_in_r0;
7213 if (pre_dec != NULL_RTX)
7219 (Pmode, r0, stack_pointer_rtx));
7223 offset -= GET_MODE_SIZE (mode);
7224 offset_in_r0 -= GET_MODE_SIZE (mode);
7229 mem_rtx = gen_frame_mem (mode, r0);
7231 mem_rtx = gen_frame_mem (mode,
7232 gen_rtx_PLUS (Pmode,
7236 /* We must not use an r0-based address for target-branch
7237 registers or for special registers without pre-dec
7238 memory addresses, since we store their values in r0
7240 gcc_assert (!TARGET_REGISTER_P (reg)
7241 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7242 || mem_rtx == pre_dec));
7245 orig_reg_rtx = reg_rtx;
7246 if (TARGET_REGISTER_P (reg)
7247 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7248 && mem_rtx != pre_dec))
7250 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
7252 emit_move_insn (tmp_reg, reg_rtx);
7254 if (REGNO (tmp_reg) == R0_REG)
7258 gcc_assert (!refers_to_regno_p
7259 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
7262 if (*++tmp_pnt <= 0)
7263 tmp_pnt = schedule.temps;
7270 /* Mark as interesting for dwarf cfi generator */
7271 insn = emit_move_insn (mem_rtx, reg_rtx);
7272 RTX_FRAME_RELATED_P (insn) = 1;
7273 /* If we use an intermediate register for the save, we can't
7274 describe this exactly in cfi as a copy of the to-be-saved
7275 register into the temporary register and then the temporary
7276 register on the stack, because the temporary register can
7277 have a different natural size than the to-be-saved register.
7278 Thus, we gloss over the intermediate copy and pretend we do
7279 a direct save from the to-be-saved register. */
7280 if (REGNO (reg_rtx) != reg)
7284 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
7285 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7288 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
7290 rtx reg_rtx = gen_rtx_REG (mode, reg);
7292 rtx mem_rtx = gen_frame_mem (mode,
7293 gen_rtx_PLUS (Pmode,
7297 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
7298 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7303 gcc_assert (entry->offset == d_rounding);
7307 push_regs (&live_regs_mask, current_function_interrupt);
7311 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7312 emit_insn (gen_GOTaddr2picreg ());
7314 if (SHMEDIA_REGS_STACK_ADJUST ())
7316 /* This must NOT go through the PLT, otherwise mach and macl
7317 may be clobbered. */
7318 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7320 ? "__GCC_push_shmedia_regs"
7321 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7322 emit_insn (gen_shmedia_save_restore_regs_compact
7323 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7326 if (target_flags != save_flags && ! current_function_interrupt)
7327 emit_insn (gen_toggle_sz ());
7329 target_flags = save_flags;
7331 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7332 stack_pointer_rtx, 0, NULL, true);
7333 stack_usage += rounded_frame_size (d) - d_rounding;
7335 if (frame_pointer_needed)
7336 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7338 if (TARGET_SHCOMPACT
7339 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7341 /* This must NOT go through the PLT, otherwise mach and macl
7342 may be clobbered. */
7343 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7344 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7345 emit_insn (gen_shcompact_incoming_args ());
7348 if (flag_stack_usage)
7349 current_function_static_stack_size = stack_usage;
7353 sh_expand_epilogue (bool sibcall_p)
7355 HARD_REG_SET live_regs_mask;
7359 int save_flags = target_flags;
7360 int frame_size, save_size;
7361 int fpscr_deferred = 0;
7362 int e = sibcall_p ? -1 : 1;
7364 d = calc_live_regs (&live_regs_mask);
7367 frame_size = rounded_frame_size (d);
7371 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7373 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7374 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7375 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7377 total_size = d + tregs_space;
7378 total_size += rounded_frame_size (total_size);
7379 save_size = total_size - frame_size;
7381 /* If adjusting the stack in a single step costs nothing extra, do so.
7382 I.e. either if a single addi is enough, or we need a movi anyway,
7383 and we don't exceed the maximum offset range (the test for the
7384 latter is conservative for simplicity). */
7386 && ! frame_pointer_needed
7387 && (CONST_OK_FOR_I10 (total_size)
7388 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7389 && total_size <= 2044)))
7390 d_rounding = frame_size;
7392 frame_size -= d_rounding;
7395 if (frame_pointer_needed)
7397 /* We must avoid scheduling the epilogue with previous basic blocks.
7398 See PR/18032 and PR/40313. */
7399 emit_insn (gen_blockage ());
7400 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7401 &live_regs_mask, false);
7403 /* We must avoid moving the stack pointer adjustment past code
7404 which reads from the local frame, else an interrupt could
7405 occur after the SP adjustment and clobber data in the local
7407 emit_insn (gen_blockage ());
7408 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7410 else if (frame_size)
7412 /* We must avoid moving the stack pointer adjustment past code
7413 which reads from the local frame, else an interrupt could
7414 occur after the SP adjustment and clobber data in the local
7416 emit_insn (gen_blockage ());
7417 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7418 &live_regs_mask, false);
7421 if (SHMEDIA_REGS_STACK_ADJUST ())
7423 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7425 ? "__GCC_pop_shmedia_regs"
7426 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7427 /* This must NOT go through the PLT, otherwise mach and macl
7428 may be clobbered. */
7429 emit_insn (gen_shmedia_save_restore_regs_compact
7430 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7433 /* Pop all the registers. */
7435 if (target_flags != save_flags && ! current_function_interrupt)
7436 emit_insn (gen_toggle_sz ());
7439 int offset_base, offset;
7440 int offset_in_r0 = -1;
7442 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7443 save_schedule schedule;
7447 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7448 offset_base = -entry[1].offset + d_rounding;
7449 tmp_pnt = schedule.temps;
7450 for (; entry->mode != VOIDmode; entry--)
7452 enum machine_mode mode = (enum machine_mode) entry->mode;
7453 int reg = entry->reg;
7454 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX;
7456 offset = offset_base + entry->offset;
7457 reg_rtx = gen_rtx_REG (mode, reg);
7459 mem_rtx = gen_frame_mem (mode,
7460 gen_rtx_PLUS (Pmode,
7464 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7467 if (HAVE_POST_INCREMENT
7468 && (offset == offset_in_r0
7469 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7470 && mem_rtx == NULL_RTX)
7471 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7473 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7475 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7476 post_inc = NULL_RTX;
7481 if (mem_rtx != NULL_RTX)
7484 if (offset_in_r0 == -1)
7486 emit_move_insn (r0, GEN_INT (offset));
7487 offset_in_r0 = offset;
7489 else if (offset != offset_in_r0)
7494 GEN_INT (offset - offset_in_r0)));
7495 offset_in_r0 += offset - offset_in_r0;
7498 if (post_inc != NULL_RTX)
7504 (Pmode, r0, stack_pointer_rtx));
7510 offset_in_r0 += GET_MODE_SIZE (mode);
7513 mem_rtx = gen_frame_mem (mode, r0);
7515 mem_rtx = gen_frame_mem (mode,
7516 gen_rtx_PLUS (Pmode,
7520 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7521 || mem_rtx == post_inc);
7524 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7525 && mem_rtx != post_inc)
7527 emit_move_insn (r0, mem_rtx);
7530 else if (TARGET_REGISTER_P (reg))
7532 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7534 /* Give the scheduler a bit of freedom by using up to
7535 MAX_TEMPS registers in a round-robin fashion. */
7536 emit_move_insn (tmp_reg, mem_rtx);
7539 tmp_pnt = schedule.temps;
7542 emit_move_insn (reg_rtx, mem_rtx);
7545 gcc_assert (entry->offset + offset_base == d + d_rounding);
7547 else /* ! TARGET_SH5 */
7552 /* For an ISR with RESBANK attribute assigned, don't pop PR
7554 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7555 && !sh_cfun_resbank_handler_p ())
7557 if (!frame_pointer_needed)
7558 emit_insn (gen_blockage ());
7562 /* Banked registers are popped first to avoid being scheduled in the
7563 delay slot. RTE switches banks before the ds instruction. */
7564 if (current_function_interrupt)
7566 bool use_movml = false;
7570 unsigned int count = 0;
7572 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7573 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7578 /* Use movml when all banked register are poped. */
7579 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7585 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7587 /* We must avoid scheduling multiple load insn with another
7589 emit_insn (gen_blockage ());
7590 emit_insn (gen_movml_pop_banked (sp_reg));
7591 emit_insn (gen_blockage ());
7594 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7595 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7598 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7601 last_reg = FIRST_PSEUDO_REGISTER;
7603 for (i = 0; i < last_reg; i++)
7605 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7607 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7608 && hard_reg_set_intersect_p (live_regs_mask,
7609 reg_class_contents[DF_REGS]))
7611 /* For an ISR with RESBANK attribute assigned, don't pop
7612 following registers, R0-R14, MACH, MACL and GBR. */
7613 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7614 && ! (sh_cfun_resbank_handler_p ()
7615 && ((j >= FIRST_GENERAL_REG
7616 && j < LAST_GENERAL_REG)
7622 if (j == FIRST_FP_REG && fpscr_deferred)
7626 if (target_flags != save_flags && ! current_function_interrupt)
7627 emit_insn (gen_toggle_sz ());
7628 target_flags = save_flags;
7630 output_stack_adjust (crtl->args.pretend_args_size
7631 + save_size + d_rounding
7632 + crtl->args.info.stack_regs * 8,
7633 stack_pointer_rtx, e, NULL, false);
7635 if (crtl->calls_eh_return)
7636 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7637 EH_RETURN_STACKADJ_RTX));
7639 /* Switch back to the normal stack if necessary. */
7640 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7641 emit_insn (gen_sp_switch_2 ());
7643 /* Tell flow the insn that pops PR isn't dead. */
7644 /* PR_REG will never be live in SHmedia mode, and we don't need to
7645 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7646 by the return pattern. */
7647 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7648 emit_use (gen_rtx_REG (SImode, PR_REG));
7651 static int sh_need_epilogue_known = 0;
7654 sh_need_epilogue (void)
7656 if (! sh_need_epilogue_known)
7661 sh_expand_epilogue (0);
7662 epilogue = get_insns ();
7664 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7666 return sh_need_epilogue_known > 0;
7669 /* Emit code to change the current function's return address to RA.
7670 TEMP is available as a scratch register, if needed. */
7673 sh_set_return_address (rtx ra, rtx tmp)
7675 HARD_REG_SET live_regs_mask;
7677 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7680 d = calc_live_regs (&live_regs_mask);
7682 /* If pr_reg isn't life, we can set it (or the register given in
7683 sh_media_register_for_return) directly. */
7684 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7690 int rr_regno = sh_media_register_for_return ();
7695 rr = gen_rtx_REG (DImode, rr_regno);
7698 rr = gen_rtx_REG (SImode, pr_reg);
7700 emit_insn (GEN_MOV (rr, ra));
7701 /* Tell flow the register for return isn't dead. */
7709 save_schedule schedule;
7712 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7713 offset = entry[1].offset;
7714 for (; entry->mode != VOIDmode; entry--)
7715 if (entry->reg == pr_reg)
7718 /* We can't find pr register. */
7722 offset = entry->offset - offset;
7723 pr_offset = (rounded_frame_size (d) + offset
7724 + SHMEDIA_REGS_STACK_ADJUST ());
7727 pr_offset = rounded_frame_size (d);
7729 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7731 if (frame_pointer_needed)
7732 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7734 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7736 tmp = gen_frame_mem (Pmode, tmp);
7737 emit_insn (GEN_MOV (tmp, ra));
7738 /* Tell this store isn't dead. */
7742 /* Clear variables at function end. */
7745 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7746 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7748 sh_need_epilogue_known = 0;
7752 sh_builtin_saveregs (void)
7754 /* First unnamed integer register. */
7755 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7756 /* Number of integer registers we need to save. */
7757 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7758 /* First unnamed SFmode float reg */
7759 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7760 /* Number of SFmode float regs to save. */
7761 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7764 alias_set_type alias_set;
7770 int pushregs = n_intregs;
7772 while (pushregs < NPARM_REGS (SImode) - 1
7773 && (CALL_COOKIE_INT_REG_GET
7774 (crtl->args.info.call_cookie,
7775 NPARM_REGS (SImode) - pushregs)
7778 crtl->args.info.call_cookie
7779 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7784 if (pushregs == NPARM_REGS (SImode))
7785 crtl->args.info.call_cookie
7786 |= (CALL_COOKIE_INT_REG (0, 1)
7787 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7789 crtl->args.info.call_cookie
7790 |= CALL_COOKIE_STACKSEQ (pushregs);
7792 crtl->args.pretend_args_size += 8 * n_intregs;
7794 if (TARGET_SHCOMPACT)
7798 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7800 error ("__builtin_saveregs not supported by this subtarget");
7807 /* Allocate block of memory for the regs. */
7808 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7809 Or can assign_stack_local accept a 0 SIZE argument? */
7810 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7813 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7814 else if (n_floatregs & 1)
7818 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7819 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7820 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7821 regbuf = change_address (regbuf, BLKmode, addr);
7823 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7827 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7828 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7829 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7830 emit_insn (gen_andsi3 (addr, addr, mask));
7831 regbuf = change_address (regbuf, BLKmode, addr);
7834 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7835 alias_set = get_varargs_alias_set ();
7836 set_mem_alias_set (regbuf, alias_set);
7839 This is optimized to only save the regs that are necessary. Explicitly
7840 named args need not be saved. */
7842 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7843 adjust_address (regbuf, BLKmode,
7844 n_floatregs * UNITS_PER_WORD),
7848 /* Return the address of the regbuf. */
7849 return XEXP (regbuf, 0);
7852 This is optimized to only save the regs that are necessary. Explicitly
7853 named args need not be saved.
7854 We explicitly build a pointer to the buffer because it halves the insn
7855 count when not optimizing (otherwise the pointer is built for each reg
7857 We emit the moves in reverse order so that we can use predecrement. */
7859 fpregs = copy_to_mode_reg (Pmode,
7860 plus_constant (XEXP (regbuf, 0),
7861 n_floatregs * UNITS_PER_WORD));
7862 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7865 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7867 emit_insn (gen_addsi3 (fpregs, fpregs,
7868 GEN_INT (-2 * UNITS_PER_WORD)));
7869 mem = change_address (regbuf, DFmode, fpregs);
7870 emit_move_insn (mem,
7871 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7873 regno = first_floatreg;
7876 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7877 mem = change_address (regbuf, SFmode, fpregs);
7878 emit_move_insn (mem,
7879 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7880 - (TARGET_LITTLE_ENDIAN != 0)));
7884 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7888 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7889 mem = change_address (regbuf, SFmode, fpregs);
7890 emit_move_insn (mem,
7891 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7894 /* Return the address of the regbuf. */
7895 return XEXP (regbuf, 0);
7898 /* Define the `__builtin_va_list' type for the ABI. */
7901 sh_build_builtin_va_list (void)
7903 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7904 tree record, type_decl;
7906 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7907 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7908 return ptr_type_node;
7910 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7911 type_decl = build_decl (BUILTINS_LOCATION,
7912 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7914 f_next_o = build_decl (BUILTINS_LOCATION,
7915 FIELD_DECL, get_identifier ("__va_next_o"),
7917 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7919 get_identifier ("__va_next_o_limit"),
7921 f_next_fp = build_decl (BUILTINS_LOCATION,
7922 FIELD_DECL, get_identifier ("__va_next_fp"),
7924 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7926 get_identifier ("__va_next_fp_limit"),
7928 f_next_stack = build_decl (BUILTINS_LOCATION,
7929 FIELD_DECL, get_identifier ("__va_next_stack"),
7932 DECL_FIELD_CONTEXT (f_next_o) = record;
7933 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7934 DECL_FIELD_CONTEXT (f_next_fp) = record;
7935 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7936 DECL_FIELD_CONTEXT (f_next_stack) = record;
7938 TYPE_STUB_DECL (record) = type_decl;
7939 TYPE_NAME (record) = type_decl;
7940 TYPE_FIELDS (record) = f_next_o;
7941 DECL_CHAIN (f_next_o) = f_next_o_limit;
7942 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7943 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7944 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7946 layout_type (record);
7951 /* Implement `va_start' for varargs and stdarg. */
7954 sh_va_start (tree valist, rtx nextarg)
7956 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7957 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7963 expand_builtin_saveregs ();
7964 std_expand_builtin_va_start (valist, nextarg);
7968 if ((! TARGET_SH2E && ! TARGET_SH4)
7969 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7971 std_expand_builtin_va_start (valist, nextarg);
7975 f_next_o = TYPE_FIELDS (va_list_type_node);
7976 f_next_o_limit = DECL_CHAIN (f_next_o);
7977 f_next_fp = DECL_CHAIN (f_next_o_limit);
7978 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7979 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7981 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7983 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7984 valist, f_next_o_limit, NULL_TREE);
7985 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7987 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7988 valist, f_next_fp_limit, NULL_TREE);
7989 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7990 valist, f_next_stack, NULL_TREE);
7992 /* Call __builtin_saveregs. */
7993 u = make_tree (sizetype, expand_builtin_saveregs ());
7994 u = fold_convert (ptr_type_node, u);
7995 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7996 TREE_SIDE_EFFECTS (t) = 1;
7997 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7999 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
8004 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
8005 size_int (UNITS_PER_WORD * nfp));
8006 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
8007 TREE_SIDE_EFFECTS (t) = 1;
8008 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8010 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
8011 TREE_SIDE_EFFECTS (t) = 1;
8012 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8014 nint = crtl->args.info.arg_count[SH_ARG_INT];
8019 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
8020 size_int (UNITS_PER_WORD * nint));
8021 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
8022 TREE_SIDE_EFFECTS (t) = 1;
8023 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8025 u = make_tree (ptr_type_node, nextarg);
8026 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
8027 TREE_SIDE_EFFECTS (t) = 1;
8028 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8031 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
8032 member, return it. */
8034 find_sole_member (tree type)
8036 tree field, member = NULL_TREE;
8038 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8040 if (TREE_CODE (field) != FIELD_DECL)
8042 if (!DECL_SIZE (field))
8044 if (integer_zerop (DECL_SIZE (field)))
8052 /* Implement `va_arg'. */
8055 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
8056 gimple_seq *post_p ATTRIBUTE_UNUSED)
8058 HOST_WIDE_INT size, rsize;
8059 tree tmp, pptr_type_node;
8060 tree addr, lab_over = NULL, result = NULL;
8061 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
8065 type = build_pointer_type (type);
8067 size = int_size_in_bytes (type);
8068 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
8069 pptr_type_node = build_pointer_type (ptr_type_node);
8071 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
8072 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
8074 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
8075 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
8080 f_next_o = TYPE_FIELDS (va_list_type_node);
8081 f_next_o_limit = DECL_CHAIN (f_next_o);
8082 f_next_fp = DECL_CHAIN (f_next_o_limit);
8083 f_next_fp_limit = DECL_CHAIN (f_next_fp);
8084 f_next_stack = DECL_CHAIN (f_next_fp_limit);
8086 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
8088 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
8089 valist, f_next_o_limit, NULL_TREE);
8090 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
8091 valist, f_next_fp, NULL_TREE);
8092 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
8093 valist, f_next_fp_limit, NULL_TREE);
8094 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
8095 valist, f_next_stack, NULL_TREE);
8097 /* Structures with a single member with a distinct mode are passed
8098 like their member. This is relevant if the latter has a REAL_TYPE
8099 or COMPLEX_TYPE type. */
8101 while (TREE_CODE (eff_type) == RECORD_TYPE
8102 && (member = find_sole_member (eff_type))
8103 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
8104 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
8105 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
8107 tree field_type = TREE_TYPE (member);
8109 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
8110 eff_type = field_type;
8113 gcc_assert ((TYPE_ALIGN (eff_type)
8114 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
8115 || (TYPE_ALIGN (eff_type)
8116 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
8121 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8123 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
8124 || (TREE_CODE (eff_type) == COMPLEX_TYPE
8125 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
8130 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
8133 addr = create_tmp_var (pptr_type_node, NULL);
8134 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8135 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8137 valist = build_simple_mem_ref (addr);
8141 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
8143 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
8145 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
8146 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8148 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
8149 tmp = next_fp_limit;
8150 if (size > 4 && !is_double)
8151 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
8152 unshare_expr (tmp), size_int (4 - size));
8153 tmp = build2 (GE_EXPR, boolean_type_node,
8154 unshare_expr (next_fp_tmp), unshare_expr (tmp));
8155 cmp = build3 (COND_EXPR, void_type_node, tmp,
8156 build1 (GOTO_EXPR, void_type_node,
8157 unshare_expr (lab_false)), NULL_TREE);
8159 gimplify_and_add (cmp, pre_p);
8161 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
8162 || (is_double || size == 16))
8164 tmp = fold_convert (sizetype, next_fp_tmp);
8165 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
8166 size_int (UNITS_PER_WORD));
8167 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
8168 unshare_expr (next_fp_tmp), tmp);
8169 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
8172 gimplify_and_add (cmp, pre_p);
8174 #ifdef FUNCTION_ARG_SCmode_WART
8175 if (TYPE_MODE (eff_type) == SCmode
8176 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
8178 tree subtype = TREE_TYPE (eff_type);
8182 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8183 imag = get_initialized_tmp_var (imag, pre_p, NULL);
8186 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8187 real = get_initialized_tmp_var (real, pre_p, NULL);
8189 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
8190 if (type != eff_type)
8191 result = build1 (VIEW_CONVERT_EXPR, type, result);
8192 result = get_initialized_tmp_var (result, pre_p, NULL);
8194 #endif /* FUNCTION_ARG_SCmode_WART */
8196 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8197 gimplify_and_add (tmp, pre_p);
8199 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8200 gimplify_and_add (tmp, pre_p);
8202 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8203 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8204 gimplify_assign (unshare_expr (next_fp_tmp),
8205 unshare_expr (valist), pre_p);
8207 gimplify_assign (unshare_expr (valist),
8208 unshare_expr (next_fp_tmp), post_p);
8209 valist = next_fp_tmp;
8213 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
8214 unshare_expr (next_o), size_int (rsize));
8215 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
8216 unshare_expr (next_o_limit));
8217 tmp = build3 (COND_EXPR, void_type_node, tmp,
8218 build1 (GOTO_EXPR, void_type_node,
8219 unshare_expr (lab_false)),
8221 gimplify_and_add (tmp, pre_p);
8223 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
8224 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8226 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8227 gimplify_and_add (tmp, pre_p);
8229 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8230 gimplify_and_add (tmp, pre_p);
8232 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8233 gimplify_assign (unshare_expr (next_o),
8234 unshare_expr (next_o_limit), pre_p);
8236 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8237 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8242 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8243 gimplify_and_add (tmp, pre_p);
8247 /* ??? In va-sh.h, there had been code to make values larger than
8248 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8250 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
8253 gimplify_assign (result, tmp, pre_p);
8254 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
8255 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8256 gimplify_and_add (tmp, pre_p);
8262 result = build_va_arg_indirect_ref (result);
8267 /* 64 bit floating points memory transfers are paired single precision loads
8268 or store. So DWARF information needs fixing in little endian (unless
8269 PR=SZ=1 in FPSCR). */
8271 sh_dwarf_register_span (rtx reg)
8273 unsigned regno = REGNO (reg);
8275 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8279 gen_rtx_PARALLEL (VOIDmode,
8281 gen_rtx_REG (SFmode,
8282 DBX_REGISTER_NUMBER (regno+1)),
8283 gen_rtx_REG (SFmode,
8284 DBX_REGISTER_NUMBER (regno))));
8287 static enum machine_mode
8288 sh_promote_function_mode (const_tree type, enum machine_mode mode,
8289 int *punsignedp, const_tree funtype,
8292 if (sh_promote_prototypes (funtype))
8293 return promote_mode (type, mode, punsignedp);
8295 return default_promote_function_mode (type, mode, punsignedp, funtype,
8300 sh_promote_prototypes (const_tree type)
8306 return ! sh_attr_renesas_p (type);
8309 /* Whether an argument must be passed by reference. On SHcompact, we
8310 pretend arguments wider than 32-bits that would have been passed in
8311 registers are passed by reference, so that an SHmedia trampoline
8312 loads them into the full 64-bits registers. */
8315 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8316 const_tree type, bool named)
8318 unsigned HOST_WIDE_INT size;
8321 size = int_size_in_bytes (type);
8323 size = GET_MODE_SIZE (mode);
8325 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8327 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8328 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8329 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8331 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8332 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8339 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8340 const_tree type, bool named)
8342 if (targetm.calls.must_pass_in_stack (mode, type))
8345 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8346 wants to know about pass-by-reference semantics for incoming
8351 if (TARGET_SHCOMPACT)
8353 cum->byref = shcompact_byref (cum, mode, type, named);
8354 return cum->byref != 0;
8361 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8362 const_tree type, bool named ATTRIBUTE_UNUSED)
8364 /* ??? How can it possibly be correct to return true only on the
8365 caller side of the equation? Is there someplace else in the
8366 sh backend that's magically producing the copies? */
8367 return (cum->outgoing
8368 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8369 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8373 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8374 tree type, bool named ATTRIBUTE_UNUSED)
8379 && PASS_IN_REG_P (*cum, mode, type)
8380 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8381 && (ROUND_REG (*cum, mode)
8383 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8384 : ROUND_ADVANCE (int_size_in_bytes (type)))
8385 > NPARM_REGS (mode)))
8386 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8388 else if (!TARGET_SHCOMPACT
8389 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8390 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8392 return words * UNITS_PER_WORD;
8396 /* Define where to put the arguments to a function.
8397 Value is zero to push the argument on the stack,
8398 or a hard register in which to store the argument.
8400 MODE is the argument's machine mode.
8401 TYPE is the data type of the argument (as a tree).
8402 This is null for libcalls where that information may
8404 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8405 the preceding args and about the function being called.
8406 NAMED is nonzero if this argument is a named parameter
8407 (otherwise it is an extra parameter matching an ellipsis).
8409 On SH the first args are normally in registers
8410 and the rest are pushed. Any arg that starts within the first
8411 NPARM_REGS words is at least partially passed in a register unless
8412 its data type forbids. */
8415 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8416 const_tree type, bool named)
8418 if (! TARGET_SH5 && mode == VOIDmode)
8419 return GEN_INT (ca->renesas_abi ? 1 : 0);
8422 && PASS_IN_REG_P (*ca, mode, type)
8423 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8427 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8428 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8430 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8431 gen_rtx_REG (SFmode,
8433 + (ROUND_REG (*ca, mode) ^ 1)),
8435 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8436 gen_rtx_REG (SFmode,
8438 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8440 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8443 /* If the alignment of a DF value causes an SF register to be
8444 skipped, we will use that skipped register for the next SF
8446 if ((TARGET_HITACHI || ca->renesas_abi)
8447 && ca->free_single_fp_reg
8449 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8451 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8452 ^ (mode == SFmode && TARGET_SH4
8453 && TARGET_LITTLE_ENDIAN != 0
8454 && ! TARGET_HITACHI && ! ca->renesas_abi);
8455 return gen_rtx_REG (mode, regno);
8461 if (mode == VOIDmode && TARGET_SHCOMPACT)
8462 return GEN_INT (ca->call_cookie);
8464 /* The following test assumes unnamed arguments are promoted to
8466 if (mode == SFmode && ca->free_single_fp_reg)
8467 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8469 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8470 && (named || ! ca->prototype_p)
8471 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8473 if (! ca->prototype_p && TARGET_SHMEDIA)
8474 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8476 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8478 + ca->arg_count[(int) SH_ARG_FLOAT]);
8481 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8482 && (! TARGET_SHCOMPACT
8483 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8484 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8487 return gen_rtx_REG (mode, (FIRST_PARM_REG
8488 + ca->arg_count[(int) SH_ARG_INT]));
8497 /* Update the data in CUM to advance over an argument
8498 of mode MODE and data type TYPE.
8499 (TYPE is null for libcalls where that information may not be
8503 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8504 const_tree type, bool named)
8508 else if (TARGET_SH5)
8510 const_tree type2 = (ca->byref && type
8513 enum machine_mode mode2 = (ca->byref && type
8516 int dwords = ((ca->byref
8519 ? int_size_in_bytes (type2)
8520 : GET_MODE_SIZE (mode2)) + 7) / 8;
8521 int numregs = MIN (dwords, NPARM_REGS (SImode)
8522 - ca->arg_count[(int) SH_ARG_INT]);
8526 ca->arg_count[(int) SH_ARG_INT] += numregs;
8527 if (TARGET_SHCOMPACT
8528 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8531 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8533 /* N.B. We want this also for outgoing. */
8534 ca->stack_regs += numregs;
8539 ca->stack_regs += numregs;
8540 ca->byref_regs += numregs;
8544 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8548 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8551 else if (dwords > numregs)
8553 int pushregs = numregs;
8555 if (TARGET_SHCOMPACT)
8556 ca->stack_regs += numregs;
8557 while (pushregs < NPARM_REGS (SImode) - 1
8558 && (CALL_COOKIE_INT_REG_GET
8560 NPARM_REGS (SImode) - pushregs)
8564 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8568 if (numregs == NPARM_REGS (SImode))
8570 |= CALL_COOKIE_INT_REG (0, 1)
8571 | CALL_COOKIE_STACKSEQ (numregs - 1);
8574 |= CALL_COOKIE_STACKSEQ (numregs);
8577 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8578 && (named || ! ca->prototype_p))
8580 if (mode2 == SFmode && ca->free_single_fp_reg)
8581 ca->free_single_fp_reg = 0;
8582 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8583 < NPARM_REGS (SFmode))
8586 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8588 - ca->arg_count[(int) SH_ARG_FLOAT]);
8590 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8592 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8594 if (ca->outgoing && numregs > 0)
8598 |= (CALL_COOKIE_INT_REG
8599 (ca->arg_count[(int) SH_ARG_INT]
8600 - numregs + ((numfpregs - 2) / 2),
8601 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8604 while (numfpregs -= 2);
8606 else if (mode2 == SFmode && (named)
8607 && (ca->arg_count[(int) SH_ARG_FLOAT]
8608 < NPARM_REGS (SFmode)))
8609 ca->free_single_fp_reg
8610 = FIRST_FP_PARM_REG - numfpregs
8611 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8617 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8619 /* Note that we've used the skipped register. */
8620 if (mode == SFmode && ca->free_single_fp_reg)
8622 ca->free_single_fp_reg = 0;
8625 /* When we have a DF after an SF, there's an SF register that get
8626 skipped in order to align the DF value. We note this skipped
8627 register, because the next SF value will use it, and not the
8628 SF that follows the DF. */
8630 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8632 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8633 + BASE_ARG_REG (mode));
8637 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8638 || PASS_IN_REG_P (*ca, mode, type))
8639 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8640 = (ROUND_REG (*ca, mode)
8642 ? ROUND_ADVANCE (int_size_in_bytes (type))
8643 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8646 /* The Renesas calling convention doesn't quite fit into this scheme since
8647 the address is passed like an invisible argument, but one that is always
8648 passed in memory. */
8650 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8652 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8654 return gen_rtx_REG (Pmode, 2);
8657 /* Worker function for TARGET_FUNCTION_VALUE.
8659 For the SH, this is like LIBCALL_VALUE, except that we must change the
8660 mode like PROMOTE_MODE does.
8661 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8662 tested here has to be kept in sync with the one in explow.c:promote_mode.
8666 sh_function_value (const_tree valtype,
8667 const_tree fn_decl_or_type,
8668 bool outgoing ATTRIBUTE_UNUSED)
8671 && !DECL_P (fn_decl_or_type))
8672 fn_decl_or_type = NULL;
8674 return gen_rtx_REG (
8675 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8676 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8677 && (TREE_CODE (valtype) == INTEGER_TYPE
8678 || TREE_CODE (valtype) == ENUMERAL_TYPE
8679 || TREE_CODE (valtype) == BOOLEAN_TYPE
8680 || TREE_CODE (valtype) == REAL_TYPE
8681 || TREE_CODE (valtype) == OFFSET_TYPE))
8682 && sh_promote_prototypes (fn_decl_or_type)
8683 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8684 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8687 /* Worker function for TARGET_LIBCALL_VALUE. */
8690 sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8692 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8695 /* Return true if N is a possible register number of function value. */
8698 sh_function_value_regno_p (const unsigned int regno)
8700 return ((regno) == FIRST_RET_REG
8701 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8702 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8705 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8708 sh_return_in_memory (const_tree type, const_tree fndecl)
8712 if (TYPE_MODE (type) == BLKmode)
8713 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8715 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8719 return (TYPE_MODE (type) == BLKmode
8720 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8721 && TREE_CODE (type) == RECORD_TYPE));
8725 /* We actually emit the code in sh_expand_prologue. We used to use
8726 a static variable to flag that we need to emit this code, but that
8727 doesn't when inlining, when functions are deferred and then emitted
8728 later. Fortunately, we already have two flags that are part of struct
8729 function that tell if a function uses varargs or stdarg. */
8731 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8732 enum machine_mode mode,
8734 int *pretend_arg_size,
8735 int second_time ATTRIBUTE_UNUSED)
8737 gcc_assert (cfun->stdarg);
8738 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8740 int named_parm_regs, anon_parm_regs;
8742 named_parm_regs = (ROUND_REG (*ca, mode)
8744 ? ROUND_ADVANCE (int_size_in_bytes (type))
8745 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8746 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8747 if (anon_parm_regs > 0)
8748 *pretend_arg_size = anon_parm_regs * 4;
8753 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8759 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8761 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8765 /* Define the offset between two registers, one to be eliminated, and
8766 the other its replacement, at the start of a routine. */
8769 initial_elimination_offset (int from, int to)
8772 int regs_saved_rounding = 0;
8773 int total_saved_regs_space;
8774 int total_auto_space;
8775 int save_flags = target_flags;
8777 HARD_REG_SET live_regs_mask;
8779 shmedia_space_reserved_for_target_registers = false;
8780 regs_saved = calc_live_regs (&live_regs_mask);
8781 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8783 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8785 shmedia_space_reserved_for_target_registers = true;
8786 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8789 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8790 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8791 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8793 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8794 copy_flags = target_flags;
8795 target_flags = save_flags;
8797 total_saved_regs_space = regs_saved + regs_saved_rounding;
8799 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8800 return total_saved_regs_space + total_auto_space
8801 + crtl->args.info.byref_regs * 8;
8803 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8804 return total_saved_regs_space + total_auto_space
8805 + crtl->args.info.byref_regs * 8;
8807 /* Initial gap between fp and sp is 0. */
8808 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8811 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8812 return rounded_frame_size (0);
8814 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8815 return rounded_frame_size (0);
8817 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8818 && (to == HARD_FRAME_POINTER_REGNUM
8819 || to == STACK_POINTER_REGNUM));
8822 int n = total_saved_regs_space;
8823 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8824 save_schedule schedule;
8827 n += total_auto_space;
8829 /* If it wasn't saved, there's not much we can do. */
8830 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8833 target_flags = copy_flags;
8835 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8836 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8837 if (entry->reg == pr_reg)
8839 target_flags = save_flags;
8840 return entry->offset;
8845 return total_auto_space;
8848 /* Parse the -mfixed-range= option string. */
8850 sh_fix_range (const char *const_str)
8853 char *str, *dash, *comma;
8855 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8856 REG2 are either register names or register numbers. The effect
8857 of this option is to mark the registers in the range from REG1 to
8858 REG2 as ``fixed'' so they won't be used by the compiler. */
8860 i = strlen (const_str);
8861 str = (char *) alloca (i + 1);
8862 memcpy (str, const_str, i + 1);
8866 dash = strchr (str, '-');
8869 warning (0, "value of -mfixed-range must have form REG1-REG2");
8873 comma = strchr (dash + 1, ',');
8877 first = decode_reg_name (str);
8880 warning (0, "unknown register name: %s", str);
8884 last = decode_reg_name (dash + 1);
8887 warning (0, "unknown register name: %s", dash + 1);
8895 warning (0, "%s-%s is an empty range", str, dash + 1);
8899 for (i = first; i <= last; ++i)
8900 fixed_regs[i] = call_used_regs[i] = 1;
8910 /* Insert any deferred function attributes from earlier pragmas. */
8912 sh_insert_attributes (tree node, tree *attributes)
8916 if (TREE_CODE (node) != FUNCTION_DECL)
8919 /* We are only interested in fields. */
8923 /* Append the attributes to the deferred attributes. */
8924 *sh_deferred_function_attributes_tail = *attributes;
8925 attrs = sh_deferred_function_attributes;
8929 /* Some attributes imply or require the interrupt attribute. */
8930 if (!lookup_attribute ("interrupt_handler", attrs)
8931 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8933 /* If we have a trapa_handler, but no interrupt_handler attribute,
8934 insert an interrupt_handler attribute. */
8935 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8936 /* We can't use sh_pr_interrupt here because that's not in the
8939 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8940 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8941 if the interrupt attribute is missing, we ignore the attribute
8943 else if (lookup_attribute ("sp_switch", attrs)
8944 || lookup_attribute ("trap_exit", attrs)
8945 || lookup_attribute ("nosave_low_regs", attrs)
8946 || lookup_attribute ("resbank", attrs))
8950 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8952 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8953 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8954 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8955 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8956 warning (OPT_Wattributes,
8957 "%qE attribute only applies to interrupt functions",
8958 TREE_PURPOSE (attrs));
8961 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8963 tail = &TREE_CHAIN (*tail);
8966 attrs = *attributes;
8970 /* Install the processed list. */
8971 *attributes = attrs;
8973 /* Clear deferred attributes. */
8974 sh_deferred_function_attributes = NULL_TREE;
8975 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8980 /* Supported attributes:
8982 interrupt_handler -- specifies this function is an interrupt handler.
8984 trapa_handler - like above, but don't save all registers.
8986 sp_switch -- specifies an alternate stack for an interrupt handler
8989 trap_exit -- use a trapa to exit an interrupt function instead of
8992 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8993 This is useful on the SH3 and upwards,
8994 which has a separate set of low regs for User and Supervisor modes.
8995 This should only be used for the lowest level of interrupts. Higher levels
8996 of interrupts must save the registers in case they themselves are
8999 renesas -- use Renesas calling/layout conventions (functions and
9002 resbank -- In case of an ISR, use a register bank to save registers
9003 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
9006 /* Handle a 'resbank' attribute. */
9008 sh_handle_resbank_handler_attribute (tree * node, tree name,
9009 tree args ATTRIBUTE_UNUSED,
9010 int flags ATTRIBUTE_UNUSED,
9011 bool * no_add_attrs)
9015 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
9017 *no_add_attrs = true;
9019 if (TREE_CODE (*node) != FUNCTION_DECL)
9021 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9023 *no_add_attrs = true;
9029 /* Handle an "interrupt_handler" attribute; arguments as in
9030 struct attribute_spec.handler. */
9032 sh_handle_interrupt_handler_attribute (tree *node, tree name,
9033 tree args ATTRIBUTE_UNUSED,
9034 int flags ATTRIBUTE_UNUSED,
9037 if (TREE_CODE (*node) != FUNCTION_DECL)
9039 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9041 *no_add_attrs = true;
9043 else if (TARGET_SHCOMPACT)
9045 error ("attribute interrupt_handler is not compatible with -m5-compact");
9046 *no_add_attrs = true;
9052 /* Handle an 'function_vector' attribute; arguments as in
9053 struct attribute_spec.handler. */
9055 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
9056 tree args ATTRIBUTE_UNUSED,
9057 int flags ATTRIBUTE_UNUSED,
9058 bool * no_add_attrs)
9062 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
9064 *no_add_attrs = true;
9066 else if (TREE_CODE (*node) != FUNCTION_DECL)
9068 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9070 *no_add_attrs = true;
9072 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9074 /* The argument must be a constant integer. */
9075 warning (OPT_Wattributes,
9076 "%qE attribute argument not an integer constant",
9078 *no_add_attrs = true;
9080 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
9082 /* The argument value must be between 0 to 255. */
9083 warning (OPT_Wattributes,
9084 "%qE attribute argument should be between 0 to 255",
9086 *no_add_attrs = true;
9091 /* Returns 1 if current function has been assigned the attribute
9092 'function_vector'. */
9094 sh2a_is_function_vector_call (rtx x)
9096 if (GET_CODE (x) == SYMBOL_REF
9097 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9099 tree tr = SYMBOL_REF_DECL (x);
9101 if (sh2a_function_vector_p (tr))
9108 /* Returns the function vector number, if the attribute
9109 'function_vector' is assigned, otherwise returns zero. */
9111 sh2a_get_function_vector_number (rtx x)
9116 if ((GET_CODE (x) == SYMBOL_REF)
9117 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
9119 t = SYMBOL_REF_DECL (x);
9121 if (TREE_CODE (t) != FUNCTION_DECL)
9124 list = SH_ATTRIBUTES (t);
9127 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9129 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
9133 list = TREE_CHAIN (list);
9142 /* Handle an "sp_switch" attribute; arguments as in
9143 struct attribute_spec.handler. */
9145 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
9146 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9148 if (TREE_CODE (*node) != FUNCTION_DECL)
9150 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9152 *no_add_attrs = true;
9154 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
9156 /* The argument must be a constant string. */
9157 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
9159 *no_add_attrs = true;
9165 /* Handle an "trap_exit" attribute; arguments as in
9166 struct attribute_spec.handler. */
9168 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
9169 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9171 if (TREE_CODE (*node) != FUNCTION_DECL)
9173 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9175 *no_add_attrs = true;
9177 /* The argument specifies a trap number to be used in a trapa instruction
9178 at function exit (instead of an rte instruction). */
9179 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9181 /* The argument must be a constant integer. */
9182 warning (OPT_Wattributes, "%qE attribute argument not an "
9183 "integer constant", name);
9184 *no_add_attrs = true;
9191 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
9192 tree name ATTRIBUTE_UNUSED,
9193 tree args ATTRIBUTE_UNUSED,
9194 int flags ATTRIBUTE_UNUSED,
9195 bool *no_add_attrs ATTRIBUTE_UNUSED)
9200 /* True if __attribute__((renesas)) or -mrenesas. */
9202 sh_attr_renesas_p (const_tree td)
9209 td = TREE_TYPE (td);
9210 if (td == error_mark_node)
9212 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
9216 /* True if __attribute__((renesas)) or -mrenesas, for the current
9219 sh_cfun_attr_renesas_p (void)
9221 return sh_attr_renesas_p (current_function_decl);
9225 sh_cfun_interrupt_handler_p (void)
9227 return (lookup_attribute ("interrupt_handler",
9228 DECL_ATTRIBUTES (current_function_decl))
9232 /* Returns 1 if FUNC has been assigned the attribute
9233 "function_vector". */
9235 sh2a_function_vector_p (tree func)
9238 if (TREE_CODE (func) != FUNCTION_DECL)
9241 list = SH_ATTRIBUTES (func);
9244 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9247 list = TREE_CHAIN (list);
9252 /* Returns TRUE if given tree has the "resbank" attribute. */
9255 sh_cfun_resbank_handler_p (void)
9257 return ((lookup_attribute ("resbank",
9258 DECL_ATTRIBUTES (current_function_decl))
9260 && (lookup_attribute ("interrupt_handler",
9261 DECL_ATTRIBUTES (current_function_decl))
9262 != NULL_TREE) && TARGET_SH2A);
9265 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9268 sh_check_pch_target_flags (int old_flags)
9270 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9271 | MASK_SH_E | MASK_HARD_SH4
9272 | MASK_FPU_SINGLE | MASK_SH4))
9273 return _("created and used with different architectures / ABIs");
9274 if ((old_flags ^ target_flags) & MASK_HITACHI)
9275 return _("created and used with different ABIs");
9276 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9277 return _("created and used with different endianness");
9281 /* Predicates used by the templates. */
9283 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9284 Used only in general_movsrc_operand. */
9287 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9299 /* Nonzero if OP is a floating point value with value 0.0. */
9302 fp_zero_operand (rtx op)
9306 if (GET_MODE (op) != SFmode)
9309 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9310 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
9313 /* Nonzero if OP is a floating point value with value 1.0. */
9316 fp_one_operand (rtx op)
9320 if (GET_MODE (op) != SFmode)
9323 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9324 return REAL_VALUES_EQUAL (r, dconst1);
9327 /* In general mode switching is used. If we are
9328 compiling without -mfmovd, movsf_ie isn't taken into account for
9329 mode switching. We could check in machine_dependent_reorg for
9330 cases where we know we are in single precision mode, but there is
9331 interface to find that out during reload, so we must avoid
9332 choosing an fldi alternative during reload and thus failing to
9333 allocate a scratch register for the constant loading. */
9341 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9343 enum rtx_code code = GET_CODE (op);
9344 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
9347 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9349 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9351 if (GET_CODE (op) != SYMBOL_REF)
9352 return TLS_MODEL_NONE;
9353 return SYMBOL_REF_TLS_MODEL (op);
9356 /* Return the destination address of a branch. */
9359 branch_dest (rtx branch)
9361 rtx dest = SET_SRC (PATTERN (branch));
9364 if (GET_CODE (dest) == IF_THEN_ELSE)
9365 dest = XEXP (dest, 1);
9366 dest = XEXP (dest, 0);
9367 dest_uid = INSN_UID (dest);
9368 return INSN_ADDRESSES (dest_uid);
9371 /* Return nonzero if REG is not used after INSN.
9372 We assume REG is a reload reg, and therefore does
9373 not live past labels. It may live past calls or jumps though. */
9375 reg_unused_after (rtx reg, rtx insn)
9380 /* If the reg is set by this instruction, then it is safe for our
9381 case. Disregard the case where this is a store to memory, since
9382 we are checking a register used in the store address. */
9383 set = single_set (insn);
9384 if (set && !MEM_P (SET_DEST (set))
9385 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9388 while ((insn = NEXT_INSN (insn)))
9394 code = GET_CODE (insn);
9397 /* If this is a label that existed before reload, then the register
9398 if dead here. However, if this is a label added by reorg, then
9399 the register may still be live here. We can't tell the difference,
9400 so we just ignore labels completely. */
9401 if (code == CODE_LABEL)
9406 if (code == JUMP_INSN)
9409 /* If this is a sequence, we must handle them all at once.
9410 We could have for instance a call that sets the target register,
9411 and an insn in a delay slot that uses the register. In this case,
9412 we must return 0. */
9413 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9418 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9420 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9421 rtx set = single_set (this_insn);
9423 if (CALL_P (this_insn))
9425 else if (JUMP_P (this_insn))
9427 if (INSN_ANNULLED_BRANCH_P (this_insn))
9432 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9434 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9436 if (!MEM_P (SET_DEST (set)))
9442 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9447 else if (code == JUMP_INSN)
9451 set = single_set (insn);
9452 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9454 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9455 return !MEM_P (SET_DEST (set));
9456 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9459 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9467 static GTY(()) rtx fpscr_rtx;
9469 get_fpscr_rtx (void)
9473 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9474 REG_USERVAR_P (fpscr_rtx) = 1;
9475 mark_user_reg (fpscr_rtx);
9477 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9478 mark_user_reg (fpscr_rtx);
9482 static GTY(()) tree fpscr_values;
9485 emit_fpu_switch (rtx scratch, int index)
9489 if (fpscr_values == NULL)
9493 t = build_index_type (integer_one_node);
9494 t = build_array_type (integer_type_node, t);
9495 t = build_decl (BUILTINS_LOCATION,
9496 VAR_DECL, get_identifier ("__fpscr_values"), t);
9497 DECL_ARTIFICIAL (t) = 1;
9498 DECL_IGNORED_P (t) = 1;
9499 DECL_EXTERNAL (t) = 1;
9500 TREE_STATIC (t) = 1;
9501 TREE_PUBLIC (t) = 1;
9507 src = DECL_RTL (fpscr_values);
9508 if (!can_create_pseudo_p ())
9510 emit_move_insn (scratch, XEXP (src, 0));
9512 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9513 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9516 src = adjust_address (src, PSImode, index * 4);
9518 dst = get_fpscr_rtx ();
9519 emit_move_insn (dst, src);
9523 emit_sf_insn (rtx pat)
9529 emit_df_insn (rtx pat)
9535 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9537 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9541 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9543 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9548 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9550 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9554 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9556 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9560 static rtx get_free_reg (HARD_REG_SET);
9562 /* This function returns a register to use to load the address to load
9563 the fpscr from. Currently it always returns r1 or r7, but when we are
9564 able to use pseudo registers after combine, or have a better mechanism
9565 for choosing a register, it should be done here. */
9566 /* REGS_LIVE is the liveness information for the point for which we
9567 need this allocation. In some bare-bones exit blocks, r1 is live at the
9568 start. We can even have all of r0..r3 being live:
9569 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9570 INSN before which new insns are placed with will clobber the register
9571 we return. If a basic block consists only of setting the return value
9572 register to a pseudo and using that register, the return value is not
9573 live before or after this block, yet we we'll insert our insns right in
9577 get_free_reg (HARD_REG_SET regs_live)
9579 if (! TEST_HARD_REG_BIT (regs_live, 1))
9580 return gen_rtx_REG (Pmode, 1);
9582 /* Hard reg 1 is live; since this is a small register classes target,
9583 there shouldn't be anything but a jump before the function end. */
9584 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9585 return gen_rtx_REG (Pmode, 7);
9588 /* This function will set the fpscr from memory.
9589 MODE is the mode we are setting it to. */
9591 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9593 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9594 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9597 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9598 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9601 /* Is the given character a logical line separator for the assembler? */
9602 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9603 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9607 sh_insn_length_adjustment (rtx insn)
9609 /* Instructions with unfilled delay slots take up an extra two bytes for
9610 the nop in the delay slot. */
9611 if (((NONJUMP_INSN_P (insn)
9612 && GET_CODE (PATTERN (insn)) != USE
9613 && GET_CODE (PATTERN (insn)) != CLOBBER)
9615 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9616 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9617 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9620 /* SH2e has a bug that prevents the use of annulled branches, so if
9621 the delay slot is not filled, we'll have to put a NOP in it. */
9622 if (sh_cpu_attr == CPU_SH2E
9623 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
9624 && get_attr_type (insn) == TYPE_CBRANCH
9625 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9628 /* sh-dsp parallel processing insn take four bytes instead of two. */
9630 if (NONJUMP_INSN_P (insn))
9633 rtx body = PATTERN (insn);
9636 int maybe_label = 1;
9638 if (GET_CODE (body) == ASM_INPUT)
9639 templ = XSTR (body, 0);
9640 else if (asm_noperands (body) >= 0)
9642 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9651 while (c == ' ' || c == '\t');
9652 /* all sh-dsp parallel-processing insns start with p.
9653 The only non-ppi sh insn starting with p is pref.
9654 The only ppi starting with pr is prnd. */
9655 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9657 /* The repeat pseudo-insn expands two three insns, a total of
9658 six bytes in size. */
9659 else if ((c == 'r' || c == 'R')
9660 && ! strncasecmp ("epeat", templ, 5))
9662 while (c && c != '\n'
9663 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9665 /* If this is a label, it is obviously not a ppi insn. */
9666 if (c == ':' && maybe_label)
9671 else if (c == '\'' || c == '"')
9676 maybe_label = c != ':';
9684 /* Return TRUE for a valid displacement for the REG+disp addressing
9687 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9688 into the FRx registers. We implement this by setting the maximum offset
9689 to zero when the value is SFmode. This also restricts loading of SFmode
9690 values into the integer registers, but that can't be helped. */
9692 /* The SH allows a displacement in a QI or HI amode, but only when the
9693 other operand is R0. GCC doesn't handle this very well, so we forgot
9696 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9697 DI can be any number 0..60. */
9700 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9702 if (CONST_INT_P (op))
9708 /* Check if this the address of an unaligned load / store. */
9709 if (mode == VOIDmode)
9710 return CONST_OK_FOR_I06 (INTVAL (op));
9712 size = GET_MODE_SIZE (mode);
9713 return (!(INTVAL (op) & (size - 1))
9714 && INTVAL (op) >= -512 * size
9715 && INTVAL (op) < 512 * size);
9720 if (GET_MODE_SIZE (mode) == 1
9721 && (unsigned) INTVAL (op) < 4096)
9725 if ((GET_MODE_SIZE (mode) == 4
9726 && (unsigned) INTVAL (op) < 64
9727 && !(INTVAL (op) & 3)
9728 && !(TARGET_SH2E && mode == SFmode))
9729 || (GET_MODE_SIZE (mode) == 4
9730 && (unsigned) INTVAL (op) < 16383
9731 && !(INTVAL (op) & 3) && TARGET_SH2A))
9734 if ((GET_MODE_SIZE (mode) == 8
9735 && (unsigned) INTVAL (op) < 60
9736 && !(INTVAL (op) & 3)
9737 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9738 || ((GET_MODE_SIZE (mode)==8)
9739 && (unsigned) INTVAL (op) < 8192
9740 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9741 && (TARGET_SH2A && mode == DFmode)))
9748 /* Recognize an RTL expression that is a valid memory address for
9750 The MODE argument is the machine mode for the MEM expression
9751 that wants to use this address.
9759 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9761 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9763 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9765 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9767 else if (GET_CODE (x) == PLUS
9768 && (mode != PSImode || reload_completed))
9770 rtx xop0 = XEXP (x, 0);
9771 rtx xop1 = XEXP (x, 1);
9773 if (GET_MODE_SIZE (mode) <= 8
9774 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9775 && sh_legitimate_index_p (mode, xop1))
9778 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9779 || ((xop0 == stack_pointer_rtx
9780 || xop0 == hard_frame_pointer_rtx)
9781 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9782 || ((xop1 == stack_pointer_rtx
9783 || xop1 == hard_frame_pointer_rtx)
9784 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9785 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9786 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9787 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9788 && TARGET_FMOVD && mode == DFmode)))
9790 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9791 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9793 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9794 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9802 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9803 isn't protected by a PIC unspec. */
9805 nonpic_symbol_mentioned_p (rtx x)
9807 register const char *fmt;
9810 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9811 || GET_CODE (x) == PC)
9814 /* We don't want to look into the possible MEM location of a
9815 CONST_DOUBLE, since we're not going to use it, in general. */
9816 if (GET_CODE (x) == CONST_DOUBLE)
9819 if (GET_CODE (x) == UNSPEC
9820 && (XINT (x, 1) == UNSPEC_PIC
9821 || XINT (x, 1) == UNSPEC_GOT
9822 || XINT (x, 1) == UNSPEC_GOTOFF
9823 || XINT (x, 1) == UNSPEC_GOTPLT
9824 || XINT (x, 1) == UNSPEC_GOTTPOFF
9825 || XINT (x, 1) == UNSPEC_DTPOFF
9826 || XINT (x, 1) == UNSPEC_TPOFF
9827 || XINT (x, 1) == UNSPEC_PLT
9828 || XINT (x, 1) == UNSPEC_SYMOFF
9829 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9832 fmt = GET_RTX_FORMAT (GET_CODE (x));
9833 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9839 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9840 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9843 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9850 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9851 @GOTOFF in `reg'. */
9853 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9856 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9859 if (GET_CODE (orig) == LABEL_REF
9860 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9863 reg = gen_reg_rtx (Pmode);
9865 emit_insn (gen_symGOTOFF2reg (reg, orig));
9868 else if (GET_CODE (orig) == SYMBOL_REF)
9871 reg = gen_reg_rtx (Pmode);
9873 emit_insn (gen_symGOT2reg (reg, orig));
9879 /* Try machine-dependent ways of modifying an illegitimate address
9880 to be legitimate. If we find one, return the new, valid address.
9881 Otherwise, return X.
9883 For the SH, if X is almost suitable for indexing, but the offset is
9884 out of range, convert it into a normal form so that CSE has a chance
9885 of reducing the number of address registers used. */
9888 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9891 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9893 if (GET_CODE (x) == PLUS
9894 && (GET_MODE_SIZE (mode) == 4
9895 || GET_MODE_SIZE (mode) == 8)
9896 && CONST_INT_P (XEXP (x, 1))
9897 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9899 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9900 && ! (TARGET_SH2E && mode == SFmode))
9902 rtx index_rtx = XEXP (x, 1);
9903 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9906 /* On rare occasions, we might get an unaligned pointer
9907 that is indexed in a way to give an aligned address.
9908 Therefore, keep the lower two bits in offset_base. */
9909 /* Instead of offset_base 128..131 use 124..127, so that
9910 simple add suffices. */
9912 offset_base = ((offset + 4) & ~60) - 4;
9914 offset_base = offset & ~60;
9916 /* Sometimes the normal form does not suit DImode. We
9917 could avoid that by using smaller ranges, but that
9918 would give less optimized code when SImode is
9920 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9922 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9923 GEN_INT (offset_base), NULL_RTX, 0,
9926 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9933 /* Attempt to replace *P, which is an address that needs reloading, with
9934 a valid memory address for an operand of mode MODE.
9935 Like for sh_legitimize_address, for the SH we try to get a normal form
9936 of the address. That will allow inheritance of the address reloads. */
9939 sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9942 enum reload_type type = (enum reload_type) itype;
9944 if (GET_CODE (*p) == PLUS
9945 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9946 && CONST_INT_P (XEXP (*p, 1))
9947 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
9949 && ! (TARGET_SH4 && mode == DFmode)
9950 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9951 && (ALLOW_INDEXED_ADDRESS
9952 || XEXP (*p, 0) == stack_pointer_rtx
9953 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9955 rtx index_rtx = XEXP (*p, 1);
9956 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9959 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9961 push_reload (*p, NULL_RTX, p, NULL,
9962 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9965 if (TARGET_SH2E && mode == SFmode)
9968 push_reload (*p, NULL_RTX, p, NULL,
9969 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9972 /* Instead of offset_base 128..131 use 124..127, so that
9973 simple add suffices. */
9975 offset_base = ((offset + 4) & ~60) - 4;
9977 offset_base = offset & ~60;
9978 /* Sometimes the normal form does not suit DImode. We could avoid
9979 that by using smaller ranges, but that would give less optimized
9980 code when SImode is prevalent. */
9981 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9983 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9984 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9985 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9986 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9990 /* We must re-recognize what we created before. */
9991 else if (GET_CODE (*p) == PLUS
9992 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9993 && GET_CODE (XEXP (*p, 0)) == PLUS
9994 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9995 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9996 && CONST_INT_P (XEXP (*p, 1))
9998 && ! (TARGET_SH2E && mode == SFmode))
10000 /* Because this address is so complex, we know it must have
10001 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10002 it is already unshared, and needs no further unsharing. */
10003 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
10004 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
10014 /* In the name of slightly smaller debug output, and to cater to
10015 general assembler lossage, recognize various UNSPEC sequences
10016 and turn them back into a direct symbol reference. */
10019 sh_delegitimize_address (rtx orig_x)
10023 orig_x = delegitimize_mem_from_attrs (orig_x);
10028 if (GET_CODE (x) == CONST)
10031 if (GET_CODE (y) == UNSPEC)
10033 if (XINT (y, 1) == UNSPEC_GOT
10034 || XINT (y, 1) == UNSPEC_GOTOFF
10035 || XINT (y, 1) == UNSPEC_SYMOFF)
10036 return XVECEXP (y, 0, 0);
10037 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
10039 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
10041 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
10043 if (GET_CODE (symplt) == UNSPEC
10044 && XINT (symplt, 1) == UNSPEC_PLT)
10045 return XVECEXP (symplt, 0, 0);
10048 else if (TARGET_SHMEDIA
10049 && (XINT (y, 1) == UNSPEC_EXTRACT_S16
10050 || XINT (y, 1) == UNSPEC_EXTRACT_U16))
10052 rtx offset = XVECEXP (y, 0, 1);
10054 x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset);
10055 if (MEM_P (orig_x))
10056 x = replace_equiv_address_nv (orig_x, x);
10065 /* Mark the use of a constant in the literal table. If the constant
10066 has multiple labels, make it unique. */
10068 mark_constant_pool_use (rtx x)
10070 rtx insn, lab, pattern;
10075 switch (GET_CODE (x))
10085 /* Get the first label in the list of labels for the same constant
10086 and delete another labels in the list. */
10088 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
10090 if (!LABEL_P (insn)
10091 || LABEL_REFS (insn) != NEXT_INSN (insn))
10096 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
10097 INSN_DELETED_P (insn) = 1;
10099 /* Mark constants in a window. */
10100 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
10102 if (!NONJUMP_INSN_P (insn))
10105 pattern = PATTERN (insn);
10106 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
10109 switch (XINT (pattern, 1))
10111 case UNSPECV_CONST2:
10112 case UNSPECV_CONST4:
10113 case UNSPECV_CONST8:
10114 XVECEXP (pattern, 0, 1) = const1_rtx;
10116 case UNSPECV_WINDOW_END:
10117 if (XVECEXP (pattern, 0, 0) == x)
10120 case UNSPECV_CONST_END:
10130 /* Return true if it's possible to redirect BRANCH1 to the destination
10131 of an unconditional jump BRANCH2. We only want to do this if the
10132 resulting branch will have a short displacement. */
10134 sh_can_redirect_branch (rtx branch1, rtx branch2)
10136 if (flag_expensive_optimizations && simplejump_p (branch2))
10138 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
10142 for (distance = 0, insn = NEXT_INSN (branch1);
10143 insn && distance < 256;
10144 insn = PREV_INSN (insn))
10149 distance += get_attr_length (insn);
10151 for (distance = 0, insn = NEXT_INSN (branch1);
10152 insn && distance < 256;
10153 insn = NEXT_INSN (insn))
10158 distance += get_attr_length (insn);
10164 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10166 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
10167 unsigned int new_reg)
10169 /* Interrupt functions can only use registers that have already been
10170 saved by the prologue, even if they would normally be
10173 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
10179 /* Function to update the integer COST
10180 based on the relationship between INSN that is dependent on
10181 DEP_INSN through the dependence LINK. The default is to make no
10182 adjustment to COST. This can be used for example to specify to
10183 the scheduler that an output- or anti-dependence does not incur
10184 the same cost as a data-dependence. The return value should be
10185 the new value for COST. */
10187 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
10191 if (TARGET_SHMEDIA)
10193 /* On SHmedia, if the dependence is an anti-dependence or
10194 output-dependence, there is no cost. */
10195 if (REG_NOTE_KIND (link) != 0)
10197 /* However, dependencies between target register loads and
10198 uses of the register in a subsequent block that are separated
10199 by a conditional branch are not modelled - we have to do with
10200 the anti-dependency between the target register load and the
10201 conditional branch that ends the current block. */
10202 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
10203 && GET_CODE (PATTERN (dep_insn)) == SET
10204 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
10205 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
10206 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
10208 int orig_cost = cost;
10209 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
10210 rtx target = ((! note
10211 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
10212 ? insn : JUMP_LABEL (insn));
10213 /* On the likely path, the branch costs 1, on the unlikely path,
10217 target = next_active_insn (target);
10218 while (target && ! flow_dependent_p (target, dep_insn)
10220 /* If two branches are executed in immediate succession, with the
10221 first branch properly predicted, this causes a stall at the
10222 second branch, hence we won't need the target for the
10223 second branch for two cycles after the launch of the first
10225 if (cost > orig_cost - 2)
10226 cost = orig_cost - 2;
10232 else if (get_attr_is_mac_media (insn)
10233 && get_attr_is_mac_media (dep_insn))
10236 else if (! reload_completed
10237 && GET_CODE (PATTERN (insn)) == SET
10238 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
10239 && GET_CODE (PATTERN (dep_insn)) == SET
10240 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
10243 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10244 that is needed at the target. */
10245 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
10246 && ! flow_dependent_p (insn, dep_insn))
10249 else if (REG_NOTE_KIND (link) == 0)
10251 enum attr_type type;
10254 if (recog_memoized (insn) < 0
10255 || recog_memoized (dep_insn) < 0)
10258 dep_set = single_set (dep_insn);
10260 /* The latency that we specify in the scheduling description refers
10261 to the actual output, not to an auto-increment register; for that,
10262 the latency is one. */
10263 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
10265 rtx set = single_set (insn);
10268 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
10269 && (!MEM_P (SET_DEST (set))
10270 || !reg_mentioned_p (SET_DEST (dep_set),
10271 XEXP (SET_DEST (set), 0))))
10274 /* The only input for a call that is timing-critical is the
10275 function's address. */
10278 rtx call = PATTERN (insn);
10280 if (GET_CODE (call) == PARALLEL)
10281 call = XVECEXP (call, 0 ,0);
10282 if (GET_CODE (call) == SET)
10283 call = SET_SRC (call);
10284 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
10285 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10286 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
10287 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
10288 cost -= TARGET_SH4_300 ? 3 : 6;
10290 /* Likewise, the most timing critical input for an sfuncs call
10291 is the function address. However, sfuncs typically start
10292 using their arguments pretty quickly.
10293 Assume a four cycle delay for SH4 before they are needed.
10294 Cached ST40-300 calls are quicker, so assume only a one
10296 ??? Maybe we should encode the delays till input registers
10297 are needed by sfuncs into the sfunc call insn. */
10298 /* All sfunc calls are parallels with at least four components.
10299 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10300 else if (GET_CODE (PATTERN (insn)) == PARALLEL
10301 && XVECLEN (PATTERN (insn), 0) >= 4
10302 && (reg = sfunc_uses_reg (insn)))
10304 if (! reg_set_p (reg, dep_insn))
10305 cost -= TARGET_SH4_300 ? 1 : 4;
10307 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
10309 enum attr_type dep_type = get_attr_type (dep_insn);
10311 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
10313 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
10314 && (type = get_attr_type (insn)) != TYPE_CALL
10315 && type != TYPE_SFUNC)
10317 /* When the preceding instruction loads the shift amount of
10318 the following SHAD/SHLD, the latency of the load is increased
10320 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10321 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
10322 && reg_overlap_mentioned_p (SET_DEST (dep_set),
10323 XEXP (SET_SRC (single_set (insn)),
10326 /* When an LS group instruction with a latency of less than
10327 3 cycles is followed by a double-precision floating-point
10328 instruction, FIPR, or FTRV, the latency of the first
10329 instruction is increased to 3 cycles. */
10331 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10332 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10334 /* The lsw register of a double-precision computation is ready one
10336 else if (reload_completed
10337 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10338 && (use_pat = single_set (insn))
10339 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10340 SET_SRC (use_pat)))
10343 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10344 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10347 else if (TARGET_SH4_300)
10349 /* Stores need their input register two cycles later. */
10350 if (dep_set && cost >= 1
10351 && ((type = get_attr_type (insn)) == TYPE_STORE
10352 || type == TYPE_PSTORE
10353 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10355 rtx set = single_set (insn);
10357 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10358 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10361 /* But don't reduce the cost below 1 if the address depends
10362 on a side effect of dep_insn. */
10364 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10370 /* An anti-dependence penalty of two applies if the first insn is a double
10371 precision fadd / fsub / fmul. */
10372 else if (!TARGET_SH4_300
10373 && REG_NOTE_KIND (link) == REG_DEP_ANTI
10374 && recog_memoized (dep_insn) >= 0
10375 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10376 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
10377 /* A lot of alleged anti-flow dependences are fake,
10378 so check this one is real. */
10379 && flow_dependent_p (dep_insn, insn))
10385 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10386 if DEP_INSN is anti-flow dependent on INSN. */
10388 flow_dependent_p (rtx insn, rtx dep_insn)
10390 rtx tmp = PATTERN (insn);
10392 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10393 return tmp == NULL_RTX;
10396 /* A helper function for flow_dependent_p called through note_stores. */
10398 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10400 rtx * pinsn = (rtx *) data;
10402 if (*pinsn && reg_referenced_p (x, *pinsn))
10406 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10407 'special function' patterns (type sfunc) that clobber pr, but that
10408 do not look like function calls to leaf_function_p. Hence we must
10409 do this extra check. */
10411 sh_pr_n_sets (void)
10413 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10416 /* Return where to allocate pseudo for a given hard register initial
10419 sh_allocate_initial_value (rtx hard_reg)
10423 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10425 if (current_function_is_leaf
10426 && ! sh_pr_n_sets ()
10427 && ! (TARGET_SHCOMPACT
10428 && ((crtl->args.info.call_cookie
10429 & ~ CALL_COOKIE_RET_TRAMP (1))
10430 || crtl->saves_all_registers)))
10433 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
10441 /* This function returns "2" to indicate dual issue for the SH4
10442 processor. To be used by the DFA pipeline description. */
10444 sh_issue_rate (void)
10446 if (TARGET_SUPERSCALAR)
10452 /* Functions for ready queue reordering for sched1. */
10454 /* Get weight for mode for a set x. */
10456 find_set_regmode_weight (rtx x, enum machine_mode mode)
10458 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10460 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10462 if (REG_P (SET_DEST (x)))
10464 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10474 /* Get regmode weight for insn. */
10476 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
10478 short reg_weight = 0;
10481 /* Increment weight for each register born here. */
10482 x = PATTERN (insn);
10483 reg_weight += find_set_regmode_weight (x, mode);
10484 if (GET_CODE (x) == PARALLEL)
10487 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10489 x = XVECEXP (PATTERN (insn), 0, j);
10490 reg_weight += find_set_regmode_weight (x, mode);
10493 /* Decrement weight for each register that dies here. */
10494 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10496 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10498 rtx note = XEXP (x, 0);
10499 if (REG_P (note) && GET_MODE (note) == mode)
10506 /* Calculate regmode weights for all insns of a basic block. */
10508 find_regmode_weight (basic_block b, enum machine_mode mode)
10510 rtx insn, next_tail, head, tail;
10512 get_ebb_head_tail (b, b, &head, &tail);
10513 next_tail = NEXT_INSN (tail);
10515 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10517 /* Handle register life information. */
10518 if (!INSN_P (insn))
10521 if (mode == SFmode)
10522 INSN_REGMODE_WEIGHT (insn, mode) =
10523 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10524 else if (mode == SImode)
10525 INSN_REGMODE_WEIGHT (insn, mode) =
10526 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10530 /* Comparison function for ready queue sorting. */
10532 rank_for_reorder (const void *x, const void *y)
10534 rtx tmp = *(const rtx *) y;
10535 rtx tmp2 = *(const rtx *) x;
10537 /* The insn in a schedule group should be issued the first. */
10538 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10539 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10541 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10542 minimizes instruction movement, thus minimizing sched's effect on
10543 register pressure. */
10544 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10547 /* Resort the array A in which only element at index N may be out of order. */
10549 swap_reorder (rtx *a, int n)
10551 rtx insn = a[n - 1];
10554 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10562 #define SCHED_REORDER(READY, N_READY) \
10565 if ((N_READY) == 2) \
10566 swap_reorder (READY, N_READY); \
10567 else if ((N_READY) > 2) \
10568 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10572 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10575 ready_reorder (rtx *ready, int nready)
10577 SCHED_REORDER (ready, nready);
10580 /* Count life regions of r0 for a block. */
10582 find_r0_life_regions (basic_block b)
10591 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10602 insn = BB_HEAD (b);
10604 r0_reg = gen_rtx_REG (SImode, R0_REG);
10609 if (find_regno_note (insn, REG_DEAD, R0_REG))
10615 && (pset = single_set (insn))
10616 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10617 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10625 insn = NEXT_INSN (insn);
10627 return set - death;
10630 /* Calculate regmode weights for all insns of all basic block. */
10632 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10633 int verbose ATTRIBUTE_UNUSED,
10638 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10639 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10640 r0_life_regions = 0;
10642 FOR_EACH_BB_REVERSE (b)
10644 find_regmode_weight (b, SImode);
10645 find_regmode_weight (b, SFmode);
10646 if (!reload_completed)
10647 r0_life_regions += find_r0_life_regions (b);
10650 CURR_REGMODE_PRESSURE (SImode) = 0;
10651 CURR_REGMODE_PRESSURE (SFmode) = 0;
10657 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10658 int verbose ATTRIBUTE_UNUSED)
10660 if (regmode_weight[0])
10662 free (regmode_weight[0]);
10663 regmode_weight[0] = NULL;
10665 if (regmode_weight[1])
10667 free (regmode_weight[1]);
10668 regmode_weight[1] = NULL;
10672 /* The scalar modes supported differs from the default version in TImode
10673 for 32-bit SHMEDIA. */
10675 sh_scalar_mode_supported_p (enum machine_mode mode)
10677 if (TARGET_SHMEDIA32 && mode == TImode)
10680 return default_scalar_mode_supported_p (mode);
10683 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10684 keep count of register pressures on SImode and SFmode. */
10686 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10687 int sched_verbose ATTRIBUTE_UNUSED,
10689 int can_issue_more)
10691 if (GET_CODE (PATTERN (insn)) != USE
10692 && GET_CODE (PATTERN (insn)) != CLOBBER)
10693 cached_can_issue_more = can_issue_more - 1;
10695 cached_can_issue_more = can_issue_more;
10697 if (reload_completed)
10698 return cached_can_issue_more;
10700 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10701 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10703 return cached_can_issue_more;
10707 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10708 int verbose ATTRIBUTE_UNUSED,
10709 int veclen ATTRIBUTE_UNUSED)
10711 CURR_REGMODE_PRESSURE (SImode) = 0;
10712 CURR_REGMODE_PRESSURE (SFmode) = 0;
10715 /* Some magic numbers. */
10716 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10717 functions that already have high pressure on r0. */
10718 #define R0_MAX_LIFE_REGIONS 2
10719 /* Register Pressure thresholds for SImode and SFmode registers. */
10720 #define SIMODE_MAX_WEIGHT 5
10721 #define SFMODE_MAX_WEIGHT 10
10723 /* Return true if the pressure is high for MODE. */
10725 high_pressure (enum machine_mode mode)
10727 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10728 functions that already have high pressure on r0. */
10729 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10732 if (mode == SFmode)
10733 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10735 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10738 /* Reorder ready queue if register pressure is high. */
10740 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10741 int sched_verbose ATTRIBUTE_UNUSED,
10744 int clock_var ATTRIBUTE_UNUSED)
10746 if (reload_completed)
10747 return sh_issue_rate ();
10749 if (high_pressure (SFmode) || high_pressure (SImode))
10751 ready_reorder (ready, *n_readyp);
10754 return sh_issue_rate ();
10757 /* Skip cycles if the current register pressure is high. */
10759 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10760 int sched_verbose ATTRIBUTE_UNUSED,
10761 rtx *ready ATTRIBUTE_UNUSED,
10762 int *n_readyp ATTRIBUTE_UNUSED,
10763 int clock_var ATTRIBUTE_UNUSED)
10765 if (reload_completed)
10766 return cached_can_issue_more;
10768 if (high_pressure(SFmode) || high_pressure (SImode))
10771 return cached_can_issue_more;
10774 /* Skip cycles without sorting the ready queue. This will move insn from
10775 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10776 queue by sh_reorder. */
10778 /* Generally, skipping these many cycles are sufficient for all insns to move
10780 #define MAX_SKIPS 8
10783 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10784 int sched_verbose ATTRIBUTE_UNUSED,
10785 rtx insn ATTRIBUTE_UNUSED,
10786 int last_clock_var,
10790 if (reload_completed)
10795 if ((clock_var - last_clock_var) < MAX_SKIPS)
10800 /* If this is the last cycle we are skipping, allow reordering of R. */
10801 if ((clock_var - last_clock_var) == MAX_SKIPS)
10813 /* SHmedia requires registers for branches, so we can't generate new
10814 branches past reload. */
10816 sh_cannot_modify_jumps_p (void)
10818 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10822 sh_target_reg_class (void)
10824 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10828 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10830 HARD_REG_SET dummy;
10835 if (! shmedia_space_reserved_for_target_registers)
10837 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10839 if (calc_live_regs (&dummy) >= 6 * 8)
10845 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10847 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10851 On the SH1..SH4, the trampoline looks like
10852 2 0002 D202 mov.l l2,r2
10853 1 0000 D301 mov.l l1,r3
10854 3 0004 422B jmp @r2
10856 5 0008 00000000 l1: .long area
10857 6 000c 00000000 l2: .long function
10859 SH5 (compact) uses r1 instead of r3 for the static chain. */
10862 /* Emit RTL insns to initialize the variable parts of a trampoline.
10863 FNADDR is an RTX for the address of the function's pure code.
10864 CXT is an RTX for the static chain value for the function. */
10867 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10869 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10870 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10872 if (TARGET_SHMEDIA64)
10877 rtx movi1 = GEN_INT (0xcc000010);
10878 rtx shori1 = GEN_INT (0xc8000010);
10881 /* The following trampoline works within a +- 128 KB range for cxt:
10882 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10883 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10884 gettr tr1,r1; blink tr0,r63 */
10885 /* Address rounding makes it hard to compute the exact bounds of the
10886 offset for this trampoline, but we have a rather generous offset
10887 range, so frame_offset should do fine as an upper bound. */
10888 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10890 /* ??? could optimize this trampoline initialization
10891 by writing DImode words with two insns each. */
10892 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10893 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10894 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10895 insn = gen_rtx_AND (DImode, insn, mask);
10896 /* Or in ptb/u .,tr1 pattern */
10897 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10898 insn = force_operand (insn, NULL_RTX);
10899 insn = gen_lowpart (SImode, insn);
10900 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10901 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10902 insn = gen_rtx_AND (DImode, insn, mask);
10903 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10904 insn = gen_lowpart (SImode, insn);
10905 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10906 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10907 insn = gen_rtx_AND (DImode, insn, mask);
10908 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10909 insn = gen_lowpart (SImode, insn);
10910 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10911 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10912 insn = gen_rtx_AND (DImode, insn, mask);
10913 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10914 insn = gen_lowpart (SImode, insn);
10915 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10916 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10917 insn = gen_rtx_AND (DImode, insn, mask);
10918 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10919 insn = gen_lowpart (SImode, insn);
10920 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10921 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10922 GEN_INT (0x6bf10600));
10923 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10924 GEN_INT (0x4415fc10));
10925 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10926 GEN_INT (0x4401fff0));
10927 emit_insn (gen_ic_invalidate_line (tramp));
10930 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10931 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10933 tramp_templ = gen_datalabel_ref (tramp_templ);
10935 src = gen_const_mem (BLKmode, tramp_templ);
10936 set_mem_align (dst, 256);
10937 set_mem_align (src, 64);
10938 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10940 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10941 emit_move_insn (adjust_address (tramp_mem, Pmode,
10942 fixed_len + GET_MODE_SIZE (Pmode)),
10944 emit_insn (gen_ic_invalidate_line (tramp));
10947 else if (TARGET_SHMEDIA)
10949 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10950 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10951 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10952 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10953 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10954 rotated 10 right, and higher 16 bit of every 32 selected. */
10956 = force_reg (V2HImode, (simplify_gen_subreg
10957 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10958 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10959 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10961 fnaddr = force_reg (SImode, fnaddr);
10962 cxt = force_reg (SImode, cxt);
10963 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10964 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10966 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10967 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10968 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10969 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10970 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10971 gen_rtx_SUBREG (V2HImode, cxt, 0),
10973 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10974 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10975 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10976 if (TARGET_LITTLE_ENDIAN)
10978 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10979 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10983 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10984 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10986 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10987 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10988 emit_insn (gen_ic_invalidate_line (tramp));
10991 else if (TARGET_SHCOMPACT)
10993 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10996 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10997 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10999 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
11000 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
11002 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
11003 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
11004 if (TARGET_HARVARD)
11006 if (!TARGET_INLINE_IC_INVALIDATE
11007 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
11008 emit_library_call (function_symbol (NULL, "__ic_invalidate",
11009 FUNCTION_ORDINARY),
11010 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
11012 emit_insn (gen_ic_invalidate_line (tramp));
11016 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
11019 sh_trampoline_adjust_address (rtx tramp)
11021 if (TARGET_SHMEDIA)
11022 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
11023 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
11027 /* FIXME: This is overly conservative. A SHcompact function that
11028 receives arguments ``by reference'' will have them stored in its
11029 own stack frame, so it must not pass pointers or references to
11030 these arguments to other functions by means of sibling calls. */
11031 /* If PIC, we cannot make sibling calls to global functions
11032 because the PLT requires r12 to be live. */
11034 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11037 && (! TARGET_SHCOMPACT
11038 || crtl->args.info.stack_regs == 0)
11039 && ! sh_cfun_interrupt_handler_p ()
11041 || (decl && ! TREE_PUBLIC (decl))
11042 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
11045 /* Machine specific built-in functions. */
11047 struct builtin_description
11049 const enum insn_code icode;
11050 const char *const name;
11055 /* describe number and signedness of arguments; arg[0] == result
11056 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
11057 /* 9: 64-bit pointer, 10: 32-bit pointer */
11058 static const char signature_args[][4] =
11060 #define SH_BLTIN_V2SI2 0
11062 #define SH_BLTIN_V4HI2 1
11064 #define SH_BLTIN_V2SI3 2
11066 #define SH_BLTIN_V4HI3 3
11068 #define SH_BLTIN_V8QI3 4
11070 #define SH_BLTIN_MAC_HISI 5
11072 #define SH_BLTIN_SH_HI 6
11074 #define SH_BLTIN_SH_SI 7
11076 #define SH_BLTIN_V4HI2V2SI 8
11078 #define SH_BLTIN_V4HI2V8QI 9
11080 #define SH_BLTIN_SISF 10
11082 #define SH_BLTIN_LDUA_L 11
11084 #define SH_BLTIN_LDUA_Q 12
11086 #define SH_BLTIN_STUA_L 13
11088 #define SH_BLTIN_STUA_Q 14
11090 #define SH_BLTIN_LDUA_L64 15
11092 #define SH_BLTIN_LDUA_Q64 16
11094 #define SH_BLTIN_STUA_L64 17
11096 #define SH_BLTIN_STUA_Q64 18
11098 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
11099 #define SH_BLTIN_2 19
11100 #define SH_BLTIN_SU 19
11102 #define SH_BLTIN_3 20
11103 #define SH_BLTIN_SUS 20
11105 #define SH_BLTIN_PSSV 21
11107 #define SH_BLTIN_XXUU 22
11108 #define SH_BLTIN_UUUU 22
11110 #define SH_BLTIN_PV 23
11113 /* mcmv: operands considered unsigned. */
11114 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
11115 /* mperm: control value considered unsigned int. */
11116 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
11117 /* mshards_q: returns signed short. */
11118 /* nsb: takes long long arg, returns unsigned char. */
11119 static struct builtin_description bdesc[] =
11121 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
11122 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
11123 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
11124 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
11125 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
11126 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
11127 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
11128 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
11129 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
11130 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
11131 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
11132 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
11133 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
11134 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
11135 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
11136 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
11137 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
11138 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
11139 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
11140 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
11141 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
11142 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
11143 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
11144 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
11145 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
11146 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
11147 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
11148 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
11149 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
11150 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
11151 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
11152 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
11153 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
11154 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
11155 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
11156 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
11157 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
11158 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
11159 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
11160 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
11161 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
11162 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
11163 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
11164 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
11165 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
11166 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
11167 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
11168 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
11169 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
11170 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
11171 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
11172 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
11173 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
11174 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
11175 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
11176 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
11177 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
11178 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
11179 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
11180 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
11181 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
11182 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
11183 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
11184 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
11185 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
11186 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
11187 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
11188 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
11189 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
11190 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
11191 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
11192 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
11193 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
11194 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
11195 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
11196 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
11197 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
11198 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
11199 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
11200 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
11201 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
11202 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
11203 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
11204 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
11208 sh_media_init_builtins (void)
11210 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
11211 struct builtin_description *d;
11213 memset (shared, 0, sizeof shared);
11214 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
11216 tree type, arg_type = 0;
11217 int signature = d->signature;
11220 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
11221 type = shared[signature];
11224 int has_result = signature_args[signature][0] != 0;
11226 if ((signature_args[signature][1] & 8)
11227 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
11228 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
11230 if (! TARGET_FPU_ANY
11231 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
11233 type = void_list_node;
11236 int arg = signature_args[signature][i];
11237 int opno = i - 1 + has_result;
11240 arg_type = ptr_type_node;
11242 arg_type = (*lang_hooks.types.type_for_mode)
11243 (insn_data[d->icode].operand[opno].mode,
11248 arg_type = void_type_node;
11251 type = tree_cons (NULL_TREE, arg_type, type);
11253 type = build_function_type (arg_type, type);
11254 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
11255 shared[signature] = type;
11258 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
11263 /* Returns the shmedia builtin decl for CODE. */
11266 sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11268 if (code >= ARRAY_SIZE (bdesc))
11269 return error_mark_node;
11271 return bdesc[code].fndecl;
11274 /* Implements target hook vector_mode_supported_p. */
11276 sh_vector_mode_supported_p (enum machine_mode mode)
11279 && ((mode == V2SFmode)
11280 || (mode == V4SFmode)
11281 || (mode == V16SFmode)))
11284 else if (TARGET_SHMEDIA
11285 && ((mode == V8QImode)
11286 || (mode == V2HImode)
11287 || (mode == V4HImode)
11288 || (mode == V2SImode)))
11295 sh_frame_pointer_required (void)
11297 /* If needed override this in other tm.h files to cope with various OS
11298 lossage requiring a frame pointer. */
11299 if (SUBTARGET_FRAME_POINTER_REQUIRED)
11308 /* Implements target hook dwarf_calling_convention. Return an enum
11309 of dwarf_calling_convention. */
11311 sh_dwarf_calling_convention (const_tree func)
11313 if (sh_attr_renesas_p (func))
11314 return DW_CC_GNU_renesas_sh;
11316 return DW_CC_normal;
11320 sh_init_builtins (void)
11322 if (TARGET_SHMEDIA)
11323 sh_media_init_builtins ();
11326 /* Returns the sh builtin decl for CODE. */
11329 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11331 if (TARGET_SHMEDIA)
11332 return sh_media_builtin_decl (code, initialize_p);
11334 return error_mark_node;
11337 /* Expand an expression EXP that calls a built-in function,
11338 with result going to TARGET if that's convenient
11339 (and in mode MODE if that's convenient).
11340 SUBTARGET may be used as the target for computing one of EXP's operands.
11341 IGNORE is nonzero if the value is to be ignored. */
11344 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11345 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
11347 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11348 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11349 const struct builtin_description *d = &bdesc[fcode];
11350 enum insn_code icode = d->icode;
11351 int signature = d->signature;
11352 enum machine_mode tmode = VOIDmode;
11357 if (signature_args[signature][0])
11362 tmode = insn_data[icode].operand[0].mode;
11364 || GET_MODE (target) != tmode
11365 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11366 target = gen_reg_rtx (tmode);
11367 op[nop++] = target;
11372 for (i = 1; i <= 3; i++, nop++)
11375 enum machine_mode opmode, argmode;
11378 if (! signature_args[signature][i])
11380 arg = CALL_EXPR_ARG (exp, i - 1);
11381 if (arg == error_mark_node)
11383 if (signature_args[signature][i] & 8)
11386 optype = ptr_type_node;
11390 opmode = insn_data[icode].operand[nop].mode;
11391 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11393 argmode = TYPE_MODE (TREE_TYPE (arg));
11394 if (argmode != opmode)
11395 arg = build1 (NOP_EXPR, optype, arg);
11396 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
11397 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11398 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11404 pat = (*insn_data[d->icode].genfun) (op[0]);
11407 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11410 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11413 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11416 gcc_unreachable ();
11425 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
11427 rtx sel0 = const0_rtx;
11428 rtx sel1 = const1_rtx;
11429 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
11430 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11432 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11433 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11437 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
11439 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11441 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11442 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
11445 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11446 We can allow any mode in any general register. The special registers
11447 only allow SImode. Don't allow any mode in the PR.
11449 We cannot hold DCmode values in the XD registers because alter_reg
11450 handles subregs of them incorrectly. We could work around this by
11451 spacing the XD registers like the DR registers, but this would require
11452 additional memory in every compilation to hold larger register vectors.
11453 We could hold SFmode / SCmode values in XD registers, but that
11454 would require a tertiary reload when reloading from / to memory,
11455 and a secondary reload to reload from / to general regs; that
11456 seems to be a loosing proposition.
11458 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11459 it won't be ferried through GP registers first. */
11462 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11464 if (SPECIAL_REGISTER_P (regno))
11465 return mode == SImode;
11467 if (regno == FPUL_REG)
11468 return (mode == SImode || mode == SFmode);
11470 if (FP_REGISTER_P (regno) && mode == SFmode)
11473 if (mode == V2SFmode)
11475 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11476 || GENERAL_REGISTER_P (regno)))
11482 if (mode == V4SFmode)
11484 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11485 || GENERAL_REGISTER_P (regno))
11491 if (mode == V16SFmode)
11493 if (TARGET_SHMEDIA)
11495 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11501 return regno == FIRST_XD_REG;
11504 if (FP_REGISTER_P (regno))
11508 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11509 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11512 && (mode == DFmode || mode == DImode
11513 || mode == V2SFmode || mode == TImode)))
11514 && ((regno - FIRST_FP_REG) & 1) == 0)
11515 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11516 && ((regno - FIRST_FP_REG) & 3) == 0))
11522 if (XD_REGISTER_P (regno))
11523 return mode == DFmode;
11525 if (TARGET_REGISTER_P (regno))
11526 return (mode == DImode || mode == SImode || mode == PDImode);
11528 if (regno == PR_REG)
11529 return mode == SImode;
11531 if (regno == FPSCR_REG)
11532 return mode == PSImode;
11534 /* FIXME. This works around PR target/37633 for -O0. */
11535 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11537 unsigned int n = GET_MODE_SIZE (mode) / 8;
11539 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11540 && regno <= FIRST_GENERAL_REG + 14)
11547 /* Return the class of registers for which a mode change from FROM to TO
11550 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
11551 enum reg_class rclass)
11553 /* We want to enable the use of SUBREGs as a means to
11554 VEC_SELECT a single element of a vector. */
11555 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
11556 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
11558 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11560 if (TARGET_LITTLE_ENDIAN)
11562 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
11563 return reg_classes_intersect_p (DF_REGS, rclass);
11567 if (GET_MODE_SIZE (from) < 8)
11568 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11574 /* Return true if registers in machine mode MODE will likely be
11575 allocated to registers in small register classes. */
11578 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11580 return (! TARGET_SHMEDIA);
11583 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11584 that label is used. */
11587 sh_mark_label (rtx address, int nuses)
11589 if (GOTOFF_P (address))
11591 /* Extract the label or symbol. */
11592 address = XEXP (address, 0);
11593 if (GET_CODE (address) == PLUS)
11594 address = XEXP (address, 0);
11595 address = XVECEXP (address, 0, 0);
11597 if (GET_CODE (address) == LABEL_REF
11598 && LABEL_P (XEXP (address, 0)))
11599 LABEL_NUSES (XEXP (address, 0)) += nuses;
11602 /* Compute extra cost of moving data between one register class
11605 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11606 uses this information. Hence, the general register <-> floating point
11607 register information here is not used for SFmode. */
11610 sh_register_move_cost (enum machine_mode mode,
11611 reg_class_t srcclass, reg_class_t dstclass)
11613 if (dstclass == T_REGS || dstclass == PR_REGS)
11616 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11619 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11620 && REGCLASS_HAS_FP_REG (srcclass)
11621 && REGCLASS_HAS_FP_REG (dstclass))
11624 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11625 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11627 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11628 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11631 if ((REGCLASS_HAS_FP_REG (dstclass)
11632 && REGCLASS_HAS_GENERAL_REG (srcclass))
11633 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11634 && REGCLASS_HAS_FP_REG (srcclass)))
11635 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11636 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11638 if ((dstclass == FPUL_REGS
11639 && REGCLASS_HAS_GENERAL_REG (srcclass))
11640 || (srcclass == FPUL_REGS
11641 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11644 if ((dstclass == FPUL_REGS
11645 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11646 || (srcclass == FPUL_REGS
11647 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11650 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11651 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11654 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11656 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11658 if (sh_gettrcost >= 0)
11659 return sh_gettrcost;
11660 else if (!TARGET_PT_FIXED)
11664 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11665 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11670 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11671 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11672 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11674 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11677 static rtx emit_load_ptr (rtx, rtx);
11680 emit_load_ptr (rtx reg, rtx addr)
11682 rtx mem = gen_const_mem (ptr_mode, addr);
11684 if (Pmode != ptr_mode)
11685 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11686 return emit_move_insn (reg, mem);
11690 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11691 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11694 CUMULATIVE_ARGS cum;
11695 int structure_value_byref = 0;
11696 rtx this_rtx, this_value, sibcall, insns, funexp;
11697 tree funtype = TREE_TYPE (function);
11698 int simple_add = CONST_OK_FOR_ADD (delta);
11700 rtx scratch0, scratch1, scratch2;
11703 reload_completed = 1;
11704 epilogue_completed = 1;
11705 current_function_uses_only_leaf_regs = 1;
11707 emit_note (NOTE_INSN_PROLOGUE_END);
11709 /* Find the "this" pointer. We have such a wide range of ABIs for the
11710 SH that it's best to do this completely machine independently.
11711 "this" is passed as first argument, unless a structure return pointer
11712 comes first, in which case "this" comes second. */
11713 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11714 #ifndef PCC_STATIC_STRUCT_RETURN
11715 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11716 structure_value_byref = 1;
11717 #endif /* not PCC_STATIC_STRUCT_RETURN */
11718 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11720 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11722 sh_function_arg_advance (&cum, Pmode, ptype, true);
11724 this_rtx = sh_function_arg (&cum, Pmode, ptr_type_node, true);
11726 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11727 static chain pointer (even if you can't have nested virtual functions
11728 right now, someone might implement them sometime), and the rest of the
11729 registers are used for argument passing, are callee-saved, or reserved. */
11730 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11731 -ffixed-reg has been used. */
11732 if (! call_used_regs[0] || fixed_regs[0])
11733 error ("r0 needs to be available as a call-clobbered register");
11734 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11737 if (call_used_regs[1] && ! fixed_regs[1])
11738 scratch1 = gen_rtx_REG (ptr_mode, 1);
11739 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11740 pointing where to return struct values. */
11741 if (call_used_regs[3] && ! fixed_regs[3])
11742 scratch2 = gen_rtx_REG (Pmode, 3);
11744 else if (TARGET_SHMEDIA)
11746 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11747 if (i != REGNO (scratch0) &&
11748 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11750 scratch1 = gen_rtx_REG (ptr_mode, i);
11753 if (scratch1 == scratch0)
11754 error ("need a second call-clobbered general purpose register");
11755 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11756 if (call_used_regs[i] && ! fixed_regs[i])
11758 scratch2 = gen_rtx_REG (Pmode, i);
11761 if (scratch2 == scratch0)
11762 error ("need a call-clobbered target register");
11765 this_value = plus_constant (this_rtx, delta);
11767 && (simple_add || scratch0 != scratch1)
11768 && strict_memory_address_p (ptr_mode, this_value))
11770 emit_load_ptr (scratch0, this_value);
11775 ; /* Do nothing. */
11776 else if (simple_add)
11777 emit_move_insn (this_rtx, this_value);
11780 emit_move_insn (scratch1, GEN_INT (delta));
11781 emit_insn (gen_add2_insn (this_rtx, scratch1));
11789 emit_load_ptr (scratch0, this_rtx);
11791 offset_addr = plus_constant (scratch0, vcall_offset);
11792 if (strict_memory_address_p (ptr_mode, offset_addr))
11793 ; /* Do nothing. */
11794 else if (! TARGET_SH5 && scratch0 != scratch1)
11796 /* scratch0 != scratch1, and we have indexed loads. Get better
11797 schedule by loading the offset into r1 and using an indexed
11798 load - then the load of r1 can issue before the load from
11799 (this_rtx + delta) finishes. */
11800 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11801 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11803 else if (CONST_OK_FOR_ADD (vcall_offset))
11805 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11806 offset_addr = scratch0;
11808 else if (scratch0 != scratch1)
11810 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11811 emit_insn (gen_add2_insn (scratch0, scratch1));
11812 offset_addr = scratch0;
11815 gcc_unreachable (); /* FIXME */
11816 emit_load_ptr (scratch0, offset_addr);
11818 if (Pmode != ptr_mode)
11819 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11820 emit_insn (gen_add2_insn (this_rtx, scratch0));
11823 /* Generate a tail call to the target function. */
11824 if (! TREE_USED (function))
11826 assemble_external (function);
11827 TREE_USED (function) = 1;
11829 funexp = XEXP (DECL_RTL (function), 0);
11830 /* If the function is overridden, so is the thunk, hence we don't
11831 need GOT addressing even if this is a public symbol. */
11833 if (TARGET_SH1 && ! flag_weak)
11834 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11837 if (TARGET_SH2 && flag_pic)
11839 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11840 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11844 if (TARGET_SHMEDIA && flag_pic)
11846 funexp = gen_sym2PIC (funexp);
11847 PUT_MODE (funexp, Pmode);
11849 emit_move_insn (scratch2, funexp);
11850 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11851 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11853 sibcall = emit_call_insn (sibcall);
11854 SIBLING_CALL_P (sibcall) = 1;
11855 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11858 /* Run just enough of rest_of_compilation to do scheduling and get
11859 the insns emitted. Note that use_thunk calls
11860 assemble_start_function and assemble_end_function. */
11862 insn_locators_alloc ();
11863 insns = get_insns ();
11869 split_all_insns_noflow ();
11874 if (optimize > 0 && flag_delayed_branch)
11875 dbr_schedule (insns);
11877 shorten_branches (insns);
11878 final_start_function (insns, file, 1);
11879 final (insns, file, 1);
11880 final_end_function ();
11882 reload_completed = 0;
11883 epilogue_completed = 0;
11887 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11891 /* If this is not an ordinary function, the name usually comes from a
11892 string literal or an sprintf buffer. Make sure we use the same
11893 string consistently, so that cse will be able to unify address loads. */
11894 if (kind != FUNCTION_ORDINARY)
11895 name = IDENTIFIER_POINTER (get_identifier (name));
11896 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11897 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11901 case FUNCTION_ORDINARY:
11905 rtx reg = target ? target : gen_reg_rtx (Pmode);
11907 emit_insn (gen_symGOT2reg (reg, sym));
11913 /* ??? To allow cse to work, we use GOTOFF relocations.
11914 we could add combiner patterns to transform this into
11915 straight pc-relative calls with sym2PIC / bsrf when
11916 label load and function call are still 1:1 and in the
11917 same basic block during combine. */
11918 rtx reg = target ? target : gen_reg_rtx (Pmode);
11920 emit_insn (gen_symGOTOFF2reg (reg, sym));
11925 if (target && sym != target)
11927 emit_move_insn (target, sym);
11933 /* Find the number of a general purpose register in S. */
11935 scavenge_reg (HARD_REG_SET *s)
11938 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11939 if (TEST_HARD_REG_BIT (*s, r))
11945 sh_get_pr_initial_val (void)
11949 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11950 PR register on SHcompact, because it might be clobbered by the prologue.
11951 We check first if that is known to be the case. */
11952 if (TARGET_SHCOMPACT
11953 && ((crtl->args.info.call_cookie
11954 & ~ CALL_COOKIE_RET_TRAMP (1))
11955 || crtl->saves_all_registers))
11956 return gen_frame_mem (SImode, return_address_pointer_rtx);
11958 /* If we haven't finished rtl generation, there might be a nonlocal label
11959 that we haven't seen yet.
11960 ??? get_hard_reg_initial_val fails if it is called after register
11961 allocation has started, unless it has been called before for the
11962 same register. And even then, we end in trouble if we didn't use
11963 the register in the same basic block before. So call
11964 get_hard_reg_initial_val now and wrap it in an unspec if we might
11965 need to replace it. */
11966 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11967 combine can put the pseudo returned by get_hard_reg_initial_val into
11968 instructions that need a general purpose registers, which will fail to
11969 be recognized when the pseudo becomes allocated to PR. */
11971 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11973 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11978 sh_expand_t_scc (rtx operands[])
11980 enum rtx_code code = GET_CODE (operands[1]);
11981 rtx target = operands[0];
11982 rtx op0 = operands[2];
11983 rtx op1 = operands[3];
11984 rtx result = target;
11987 if (!REG_P (op0) || REGNO (op0) != T_REG
11988 || !CONST_INT_P (op1))
11990 if (!REG_P (result))
11991 result = gen_reg_rtx (SImode);
11992 val = INTVAL (op1);
11993 if ((code == EQ && val == 1) || (code == NE && val == 0))
11994 emit_insn (gen_movt (result));
11995 else if (TARGET_SH2A && ((code == EQ && val == 0)
11996 || (code == NE && val == 1)))
11997 emit_insn (gen_xorsi3_movrt (result));
11998 else if ((code == EQ && val == 0) || (code == NE && val == 1))
12000 emit_clobber (result);
12001 emit_insn (gen_subc (result, result, result));
12002 emit_insn (gen_addsi3 (result, result, const1_rtx));
12004 else if (code == EQ || code == NE)
12005 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
12008 if (result != target)
12009 emit_move_insn (target, result);
12013 /* INSN is an sfunc; return the rtx that describes the address used. */
12015 extract_sfunc_addr (rtx insn)
12017 rtx pattern, part = NULL_RTX;
12020 pattern = PATTERN (insn);
12021 len = XVECLEN (pattern, 0);
12022 for (i = 0; i < len; i++)
12024 part = XVECEXP (pattern, 0, i);
12025 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
12026 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
12027 return XEXP (part, 0);
12029 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
12030 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
12033 /* Verify that the register in use_sfunc_addr still agrees with the address
12034 used in the sfunc. This prevents fill_slots_from_thread from changing
12036 INSN is the use_sfunc_addr instruction, and REG is the register it
12039 check_use_sfunc_addr (rtx insn, rtx reg)
12041 /* Search for the sfunc. It should really come right after INSN. */
12042 while ((insn = NEXT_INSN (insn)))
12044 if (LABEL_P (insn) || JUMP_P (insn))
12046 if (! INSN_P (insn))
12049 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
12050 insn = XVECEXP (PATTERN (insn), 0, 0);
12051 if (GET_CODE (PATTERN (insn)) != PARALLEL
12052 || get_attr_type (insn) != TYPE_SFUNC)
12054 return rtx_equal_p (extract_sfunc_addr (insn), reg);
12056 gcc_unreachable ();
12059 /* This function returns a constant rtx that represents pi / 2**15 in
12060 SFmode. it's used to scale SFmode angles, in radians, to a
12061 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
12062 maps to 0x10000). */
12064 static GTY(()) rtx sh_fsca_sf2int_rtx;
12067 sh_fsca_sf2int (void)
12069 if (! sh_fsca_sf2int_rtx)
12071 REAL_VALUE_TYPE rv;
12073 real_from_string (&rv, "10430.378350470453");
12074 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
12077 return sh_fsca_sf2int_rtx;
12080 /* This function returns a constant rtx that represents pi / 2**15 in
12081 DFmode. it's used to scale DFmode angles, in radians, to a
12082 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
12083 maps to 0x10000). */
12085 static GTY(()) rtx sh_fsca_df2int_rtx;
12088 sh_fsca_df2int (void)
12090 if (! sh_fsca_df2int_rtx)
12092 REAL_VALUE_TYPE rv;
12094 real_from_string (&rv, "10430.378350470453");
12095 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
12098 return sh_fsca_df2int_rtx;
12101 /* This function returns a constant rtx that represents 2**15 / pi in
12102 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
12103 of a full circle back to a SFmode value, i.e., 0x10000 maps to
12106 static GTY(()) rtx sh_fsca_int2sf_rtx;
12109 sh_fsca_int2sf (void)
12111 if (! sh_fsca_int2sf_rtx)
12113 REAL_VALUE_TYPE rv;
12115 real_from_string (&rv, "9.587379924285257e-5");
12116 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
12119 return sh_fsca_int2sf_rtx;
12122 /* Initialize the CUMULATIVE_ARGS structure. */
12125 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
12127 rtx libname ATTRIBUTE_UNUSED,
12129 signed int n_named_args,
12130 enum machine_mode mode)
12132 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
12133 pcum->free_single_fp_reg = 0;
12134 pcum->stack_regs = 0;
12135 pcum->byref_regs = 0;
12137 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
12139 /* XXX - Should we check TARGET_HITACHI here ??? */
12140 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
12144 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
12145 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
12146 pcum->prototype_p = prototype_p (fntype);
12147 pcum->arg_count [(int) SH_ARG_INT]
12148 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
12151 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12152 && pcum->arg_count [(int) SH_ARG_INT] == 0
12153 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
12154 ? int_size_in_bytes (TREE_TYPE (fntype))
12155 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
12156 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
12157 == FIRST_RET_REG));
12161 pcum->arg_count [(int) SH_ARG_INT] = 0;
12162 pcum->prototype_p = FALSE;
12163 if (mode != VOIDmode)
12165 pcum->call_cookie =
12166 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12167 && GET_MODE_SIZE (mode) > 4
12168 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
12170 /* If the default ABI is the Renesas ABI then all library
12171 calls must assume that the library will be using the
12172 Renesas ABI. So if the function would return its result
12173 in memory then we must force the address of this memory
12174 block onto the stack. Ideally we would like to call
12175 targetm.calls.return_in_memory() here but we do not have
12176 the TYPE or the FNDECL available so we synthesize the
12177 contents of that function as best we can. */
12179 (TARGET_DEFAULT & MASK_HITACHI)
12180 && (mode == BLKmode
12181 || (GET_MODE_SIZE (mode) > 4
12182 && !(mode == DFmode
12183 && TARGET_FPU_DOUBLE)));
12187 pcum->call_cookie = 0;
12188 pcum->force_mem = FALSE;
12193 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12194 not enter into CONST_DOUBLE for the replace.
12196 Note that copying is not done so X must not be shared unless all copies
12197 are to be modified.
12199 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12200 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12201 replacements[n*2+1] - and that we take mode changes into account.
12203 If a replacement is ambiguous, return NULL_RTX.
12205 If MODIFY is zero, don't modify any rtl in place,
12206 just return zero or nonzero for failure / success. */
12209 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
12214 /* The following prevents loops occurrence when we change MEM in
12215 CONST_DOUBLE onto the same CONST_DOUBLE. */
12216 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
12219 for (i = n_replacements - 1; i >= 0 ; i--)
12220 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
12221 return replacements[i*2+1];
12223 /* Allow this function to make replacements in EXPR_LISTs. */
12227 if (GET_CODE (x) == SUBREG)
12229 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
12230 n_replacements, modify);
12232 if (CONST_INT_P (new_rtx))
12234 x = simplify_subreg (GET_MODE (x), new_rtx,
12235 GET_MODE (SUBREG_REG (x)),
12241 SUBREG_REG (x) = new_rtx;
12245 else if (REG_P (x))
12247 unsigned regno = REGNO (x);
12248 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
12249 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12250 rtx result = NULL_RTX;
12252 for (i = n_replacements - 1; i >= 0; i--)
12254 rtx from = replacements[i*2];
12255 rtx to = replacements[i*2+1];
12256 unsigned from_regno, from_nregs, to_regno, new_regno;
12260 from_regno = REGNO (from);
12261 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
12262 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
12263 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
12265 if (regno < from_regno
12266 || regno + nregs > from_regno + nregs
12270 to_regno = REGNO (to);
12271 if (to_regno < FIRST_PSEUDO_REGISTER)
12273 new_regno = regno + to_regno - from_regno;
12274 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
12277 result = gen_rtx_REG (GET_MODE (x), new_regno);
12279 else if (GET_MODE (x) <= GET_MODE (to))
12280 result = gen_lowpart_common (GET_MODE (x), to);
12282 result = gen_lowpart_SUBREG (GET_MODE (x), to);
12285 return result ? result : x;
12287 else if (GET_CODE (x) == ZERO_EXTEND)
12289 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
12290 n_replacements, modify);
12292 if (CONST_INT_P (new_rtx))
12294 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
12295 new_rtx, GET_MODE (XEXP (x, 0)));
12300 XEXP (x, 0) = new_rtx;
12305 fmt = GET_RTX_FORMAT (GET_CODE (x));
12306 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
12312 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
12313 n_replacements, modify);
12317 XEXP (x, i) = new_rtx;
12319 else if (fmt[i] == 'E')
12320 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12322 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
12323 n_replacements, modify);
12327 XVECEXP (x, i, j) = new_rtx;
12335 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12337 enum rtx_code code = TRUNCATE;
12339 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12341 rtx inner = XEXP (x, 0);
12342 enum machine_mode inner_mode = GET_MODE (inner);
12344 if (inner_mode == mode)
12346 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12348 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12349 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12351 code = GET_CODE (x);
12355 return gen_rtx_fmt_e (code, mode, x);
12358 /* called via for_each_rtx after reload, to clean up truncates of
12359 registers that span multiple actual hard registers. */
12361 shmedia_cleanup_truncate (rtx *p, void *n_changes)
12365 if (GET_CODE (x) != TRUNCATE)
12368 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
12370 enum machine_mode reg_mode = GET_MODE (reg);
12371 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12372 subreg_lowpart_offset (DImode, reg_mode));
12373 *(int*) n_changes += 1;
12379 /* Load and store depend on the highpart of the address. However,
12380 set_attr_alternative does not give well-defined results before reload,
12381 so we must look at the rtl ourselves to see if any of the feeding
12382 registers is used in a memref. */
12384 /* Called by sh_contains_memref_p via for_each_rtx. */
12386 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12388 return (MEM_P (*loc));
12391 /* Return nonzero iff INSN contains a MEM. */
12393 sh_contains_memref_p (rtx insn)
12395 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12398 /* Return nonzero iff INSN loads a banked register. */
12400 sh_loads_bankedreg_p (rtx insn)
12402 if (GET_CODE (PATTERN (insn)) == SET)
12404 rtx op = SET_DEST (PATTERN(insn));
12405 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12412 /* FNADDR is the MEM expression from a call expander. Return an address
12413 to use in an SHmedia insn pattern. */
12415 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12419 fnaddr = XEXP (fnaddr, 0);
12420 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12421 if (flag_pic && is_sym)
12423 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12425 rtx reg = gen_reg_rtx (Pmode);
12427 /* We must not use GOTPLT for sibcalls, because PIC_REG
12428 must be restored before the PLT code gets to run. */
12430 emit_insn (gen_symGOT2reg (reg, fnaddr));
12432 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12437 fnaddr = gen_sym2PIC (fnaddr);
12438 PUT_MODE (fnaddr, Pmode);
12441 /* If ptabs might trap, make this visible to the rest of the compiler.
12442 We generally assume that symbols pertain to valid locations, but
12443 it is possible to generate invalid symbols with asm or linker tricks.
12444 In a list of functions where each returns its successor, an invalid
12445 symbol might denote an empty list. */
12446 if (!TARGET_PT_FIXED
12447 && (!is_sym || TARGET_INVALID_SYMBOLS)
12448 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12450 rtx tr = gen_reg_rtx (PDImode);
12452 emit_insn (gen_ptabs (tr, fnaddr));
12455 else if (! target_reg_operand (fnaddr, Pmode))
12456 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12460 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12463 sh_preferred_reload_class (rtx x, reg_class_t rclass)
12465 if (rclass == NO_REGS
12467 && (CONST_DOUBLE_P (x)
12468 || GET_CODE (x) == SYMBOL_REF
12469 || PIC_ADDR_P (x)))
12470 return GENERAL_REGS;
12475 /* Implement TARGET_SECONDARY_RELOAD. */
12478 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12479 enum machine_mode mode, secondary_reload_info *sri)
12481 enum reg_class rclass = (enum reg_class) rclass_i;
12485 if (REGCLASS_HAS_FP_REG (rclass)
12486 && ! TARGET_SHMEDIA
12487 && immediate_operand ((x), mode)
12488 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12489 && mode == SFmode && fldi_ok ()))
12493 sri->icode = CODE_FOR_reload_insf__frn;
12496 sri->icode = CODE_FOR_reload_indf__frn;
12499 /* ??? If we knew that we are in the appropriate mode -
12500 single precision - we could use a reload pattern directly. */
12505 if (rclass == FPUL_REGS
12507 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12508 || REGNO (x) == T_REG))
12509 || GET_CODE (x) == PLUS))
12510 return GENERAL_REGS;
12511 if (rclass == FPUL_REGS && immediate_operand (x, mode))
12513 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
12514 return GENERAL_REGS;
12515 else if (mode == SFmode)
12517 sri->icode = CODE_FOR_reload_insi__i_fpul;
12520 if (rclass == FPSCR_REGS
12521 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12522 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
12523 return GENERAL_REGS;
12524 if (REGCLASS_HAS_FP_REG (rclass)
12526 && immediate_operand (x, mode)
12527 && x != CONST0_RTX (GET_MODE (x))
12528 && GET_MODE (x) != V4SFmode)
12529 return GENERAL_REGS;
12530 if ((mode == QImode || mode == HImode)
12531 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12533 sri->icode = ((mode == QImode)
12534 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12537 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
12538 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
12539 return TARGET_REGS;
12540 } /* end of input-only processing. */
12542 if (((REGCLASS_HAS_FP_REG (rclass)
12544 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12545 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12546 && TARGET_FMOVD))))
12547 || (REGCLASS_HAS_GENERAL_REG (rclass)
12549 && FP_REGISTER_P (REGNO (x))))
12550 && ! TARGET_SHMEDIA
12551 && (mode == SFmode || mode == SImode))
12553 if ((rclass == FPUL_REGS
12554 || (REGCLASS_HAS_FP_REG (rclass)
12555 && ! TARGET_SHMEDIA && mode == SImode))
12558 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12559 || REGNO (x) == T_REG
12560 || system_reg_operand (x, VOIDmode)))))
12562 if (rclass == FPUL_REGS)
12563 return GENERAL_REGS;
12566 if ((rclass == TARGET_REGS
12567 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
12568 && !satisfies_constraint_Csy (x)
12569 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
12570 return GENERAL_REGS;
12571 if ((rclass == MAC_REGS || rclass == PR_REGS)
12572 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
12573 && rclass != REGNO_REG_CLASS (REGNO (x)))
12574 return GENERAL_REGS;
12575 if (rclass != GENERAL_REGS && REG_P (x)
12576 && TARGET_REGISTER_P (REGNO (x)))
12577 return GENERAL_REGS;
12582 sh_conditional_register_usage (void)
12585 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
12586 if (! VALID_REGISTER_P (regno))
12587 fixed_regs[regno] = call_used_regs[regno] = 1;
12588 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12591 call_used_regs[FIRST_GENERAL_REG + 8]
12592 = call_used_regs[FIRST_GENERAL_REG + 9] = 1;
12593 call_really_used_regs[FIRST_GENERAL_REG + 8]
12594 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;
12596 if (TARGET_SHMEDIA)
12598 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;
12599 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);
12600 regno_reg_class[FIRST_FP_REG] = FP_REGS;
12604 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12605 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12607 /* Renesas saves and restores mac registers on call. */
12608 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
12610 call_really_used_regs[MACH_REG] = 0;
12611 call_really_used_regs[MACL_REG] = 0;
12613 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);
12614 regno <= LAST_FP_REG; regno += 2)
12615 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);
12616 if (TARGET_SHMEDIA)
12618 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)
12619 if (! fixed_regs[regno] && call_really_used_regs[regno])
12620 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12623 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
12624 if (! fixed_regs[regno] && call_really_used_regs[regno])
12625 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12629 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;