1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
40 #include "diagnostic-core.h"
42 #include "integrate.h"
46 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 #include "sched-int.h"
57 #include "alloc-pool.h"
58 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt;
85 tree sh_deferred_function_attributes;
86 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles = 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid = 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static void split_branches (rtx);
172 static int branch_dest (rtx);
173 static void force_into (rtx, rtx);
174 static void print_slot (rtx);
175 static rtx add_constant (rtx, enum machine_mode, rtx);
176 static void dump_table (rtx, rtx);
177 static int hi_const (rtx);
178 static int broken_move (rtx);
179 static int mova_p (rtx);
180 static rtx find_barrier (int, rtx, rtx);
181 static int noncall_uses_reg (rtx, rtx, rtx *);
182 static rtx gen_block_redirect (rtx, int, int);
183 static void sh_reorg (void);
184 static void sh_option_override (void);
185 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
186 static rtx frame_insn (rtx);
187 static rtx push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET *, int);
190 static int calc_live_regs (HARD_REG_SET *);
191 static HOST_WIDE_INT rounded_frame_size (int);
192 static bool sh_frame_pointer_required (void);
193 static rtx mark_constant_pool_use (rtx);
194 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_resbank_handler_attribute (tree *, tree,
197 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
199 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
202 static void sh_print_operand (FILE *, rtx, int);
203 static void sh_print_operand_address (FILE *, rtx);
204 static bool sh_print_operand_punct_valid_p (unsigned char code);
205 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
206 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
207 static void sh_insert_attributes (tree, tree *);
208 static const char *sh_check_pch_target_flags (int);
209 static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
210 static int sh_adjust_cost (rtx, rtx, rtx, int);
211 static int sh_issue_rate (void);
212 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
213 static short find_set_regmode_weight (rtx, enum machine_mode);
214 static short find_insn_regmode_weight (rtx, enum machine_mode);
215 static void find_regmode_weight (basic_block, enum machine_mode);
216 static int find_r0_life_regions (basic_block);
217 static void sh_md_init_global (FILE *, int, int);
218 static void sh_md_finish_global (FILE *, int);
219 static int rank_for_reorder (const void *, const void *);
220 static void swap_reorder (rtx *, int);
221 static void ready_reorder (rtx *, int);
222 static short high_pressure (enum machine_mode);
223 static int sh_reorder (FILE *, int, rtx *, int *, int);
224 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
225 static void sh_md_init (FILE *, int, int);
226 static int sh_variable_issue (FILE *, int, rtx, int);
228 static bool sh_function_ok_for_sibcall (tree, tree);
230 static bool sh_cannot_modify_jumps_p (void);
231 static reg_class_t sh_target_reg_class (void);
232 static bool sh_optimize_target_register_callee_saved (bool);
233 static bool sh_ms_bitfield_layout_p (const_tree);
235 static void sh_init_builtins (void);
236 static tree sh_builtin_decl (unsigned, bool);
237 static void sh_media_init_builtins (void);
238 static tree sh_media_builtin_decl (unsigned, bool);
239 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
240 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
241 static void sh_file_start (void);
242 static int flow_dependent_p (rtx, rtx);
243 static void flow_dependent_p_1 (rtx, const_rtx, void *);
244 static int shiftcosts (rtx);
245 static int and_xor_ior_costs (rtx, int);
246 static int addsubcosts (rtx);
247 static int multcosts (rtx);
248 static bool unspec_caller_rtx_p (rtx);
249 static bool sh_cannot_copy_insn_p (rtx);
250 static bool sh_rtx_costs (rtx, int, int, int, int *, bool);
251 static int sh_address_cost (rtx, bool);
252 static int sh_pr_n_sets (void);
253 static rtx sh_allocate_initial_value (rtx);
254 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
255 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
257 struct secondary_reload_info *);
258 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
259 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
260 static rtx sh_delegitimize_address (rtx);
261 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
262 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
263 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
264 static int scavenge_reg (HARD_REG_SET *s);
265 struct save_schedule_s;
266 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
267 struct save_schedule_s *, int);
269 static rtx sh_struct_value_rtx (tree, int);
270 static rtx sh_function_value (const_tree, const_tree, bool);
271 static bool sh_function_value_regno_p (const unsigned int);
272 static rtx sh_libcall_value (enum machine_mode, const_rtx);
273 static bool sh_return_in_memory (const_tree, const_tree);
274 static rtx sh_builtin_saveregs (void);
275 static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode, tree, int *, int);
276 static bool sh_strict_argument_naming (cumulative_args_t);
277 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
278 static tree sh_build_builtin_va_list (void);
279 static void sh_va_start (tree, rtx);
280 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
281 static bool sh_promote_prototypes (const_tree);
282 static enum machine_mode sh_promote_function_mode (const_tree type,
287 static bool sh_pass_by_reference (cumulative_args_t, enum machine_mode,
289 static bool sh_callee_copies (cumulative_args_t, enum machine_mode,
291 static int sh_arg_partial_bytes (cumulative_args_t, enum machine_mode,
293 static void sh_function_arg_advance (cumulative_args_t, enum machine_mode,
295 static rtx sh_function_arg (cumulative_args_t, enum machine_mode,
297 static bool sh_scalar_mode_supported_p (enum machine_mode);
298 static int sh_dwarf_calling_convention (const_tree);
299 static void sh_encode_section_info (tree, rtx, int);
300 static int sh2a_function_vector_p (tree);
301 static void sh_trampoline_init (rtx, tree, rtx);
302 static rtx sh_trampoline_adjust_address (rtx);
303 static void sh_conditional_register_usage (void);
304 static bool sh_legitimate_constant_p (enum machine_mode, rtx);
306 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
308 static const struct attribute_spec sh_attribute_table[] =
310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
311 affects_type_identity } */
312 { "interrupt_handler", 0, 0, true, false, false,
313 sh_handle_interrupt_handler_attribute, false },
314 { "sp_switch", 1, 1, true, false, false,
315 sh_handle_sp_switch_attribute, false },
316 { "trap_exit", 1, 1, true, false, false,
317 sh_handle_trap_exit_attribute, false },
318 { "renesas", 0, 0, false, true, false,
319 sh_handle_renesas_attribute, false },
320 { "trapa_handler", 0, 0, true, false, false,
321 sh_handle_interrupt_handler_attribute, false },
322 { "nosave_low_regs", 0, 0, true, false, false,
323 sh_handle_interrupt_handler_attribute, false },
324 { "resbank", 0, 0, true, false, false,
325 sh_handle_resbank_handler_attribute, false },
326 { "function_vector", 1, 1, true, false, false,
327 sh2a_handle_function_vector_handler_attribute, false },
328 { NULL, 0, 0, false, false, false, NULL, false }
331 /* Initialize the GCC target structure. */
332 #undef TARGET_ATTRIBUTE_TABLE
333 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
335 /* The next two are used for debug info when compiling with -gdwarf. */
336 #undef TARGET_ASM_UNALIGNED_HI_OP
337 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
338 #undef TARGET_ASM_UNALIGNED_SI_OP
339 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
341 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
342 #undef TARGET_ASM_UNALIGNED_DI_OP
343 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
344 #undef TARGET_ASM_ALIGNED_DI_OP
345 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
347 #undef TARGET_OPTION_OVERRIDE
348 #define TARGET_OPTION_OVERRIDE sh_option_override
350 #undef TARGET_PRINT_OPERAND
351 #define TARGET_PRINT_OPERAND sh_print_operand
352 #undef TARGET_PRINT_OPERAND_ADDRESS
353 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
354 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
355 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
356 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
357 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
359 #undef TARGET_ASM_FUNCTION_EPILOGUE
360 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
362 #undef TARGET_ASM_OUTPUT_MI_THUNK
363 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
365 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
366 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
368 #undef TARGET_ASM_FILE_START
369 #define TARGET_ASM_FILE_START sh_file_start
370 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
371 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
373 #undef TARGET_REGISTER_MOVE_COST
374 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
376 #undef TARGET_INSERT_ATTRIBUTES
377 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
379 #undef TARGET_SCHED_ADJUST_COST
380 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
382 #undef TARGET_SCHED_ISSUE_RATE
383 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
385 /* The next 5 hooks have been implemented for reenabling sched1. With the
386 help of these macros we are limiting the movement of insns in sched1 to
387 reduce the register pressure. The overall idea is to keep count of SImode
388 and SFmode regs required by already scheduled insns. When these counts
389 cross some threshold values; give priority to insns that free registers.
390 The insn that frees registers is most likely to be the insn with lowest
391 LUID (original insn order); but such an insn might be there in the stalled
392 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
393 upto a max of 8 cycles so that such insns may move from Q -> R.
395 The description of the hooks are as below:
397 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
398 scheduler; it is called inside the sched_init function just after
399 find_insn_reg_weights function call. It is used to calculate the SImode
400 and SFmode weights of insns of basic blocks; much similar to what
401 find_insn_reg_weights does.
402 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
404 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
405 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
408 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
409 high; reorder the ready queue so that the insn with lowest LUID will be
412 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
413 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
415 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
416 can be returned from TARGET_SCHED_REORDER2.
418 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
420 #undef TARGET_SCHED_DFA_NEW_CYCLE
421 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
423 #undef TARGET_SCHED_INIT_GLOBAL
424 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
426 #undef TARGET_SCHED_FINISH_GLOBAL
427 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
429 #undef TARGET_SCHED_VARIABLE_ISSUE
430 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
432 #undef TARGET_SCHED_REORDER
433 #define TARGET_SCHED_REORDER sh_reorder
435 #undef TARGET_SCHED_REORDER2
436 #define TARGET_SCHED_REORDER2 sh_reorder2
438 #undef TARGET_SCHED_INIT
439 #define TARGET_SCHED_INIT sh_md_init
441 #undef TARGET_DELEGITIMIZE_ADDRESS
442 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
444 #undef TARGET_LEGITIMIZE_ADDRESS
445 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
447 #undef TARGET_CANNOT_MODIFY_JUMPS_P
448 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
449 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
450 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
451 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
452 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
453 sh_optimize_target_register_callee_saved
455 #undef TARGET_MS_BITFIELD_LAYOUT_P
456 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
458 #undef TARGET_INIT_BUILTINS
459 #define TARGET_INIT_BUILTINS sh_init_builtins
460 #undef TARGET_BUILTIN_DECL
461 #define TARGET_BUILTIN_DECL sh_builtin_decl
462 #undef TARGET_EXPAND_BUILTIN
463 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
465 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
466 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
468 #undef TARGET_CANNOT_COPY_INSN_P
469 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
470 #undef TARGET_RTX_COSTS
471 #define TARGET_RTX_COSTS sh_rtx_costs
472 #undef TARGET_ADDRESS_COST
473 #define TARGET_ADDRESS_COST sh_address_cost
474 #undef TARGET_ALLOCATE_INITIAL_VALUE
475 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
477 #undef TARGET_MACHINE_DEPENDENT_REORG
478 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
480 #undef TARGET_DWARF_REGISTER_SPAN
481 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
484 #undef TARGET_HAVE_TLS
485 #define TARGET_HAVE_TLS true
488 #undef TARGET_PROMOTE_PROTOTYPES
489 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
490 #undef TARGET_PROMOTE_FUNCTION_MODE
491 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
493 #undef TARGET_FUNCTION_VALUE
494 #define TARGET_FUNCTION_VALUE sh_function_value
495 #undef TARGET_FUNCTION_VALUE_REGNO_P
496 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
497 #undef TARGET_LIBCALL_VALUE
498 #define TARGET_LIBCALL_VALUE sh_libcall_value
499 #undef TARGET_STRUCT_VALUE_RTX
500 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
501 #undef TARGET_RETURN_IN_MEMORY
502 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
504 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
505 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
506 #undef TARGET_SETUP_INCOMING_VARARGS
507 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
508 #undef TARGET_STRICT_ARGUMENT_NAMING
509 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
510 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
511 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
512 #undef TARGET_MUST_PASS_IN_STACK
513 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
514 #undef TARGET_PASS_BY_REFERENCE
515 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
516 #undef TARGET_CALLEE_COPIES
517 #define TARGET_CALLEE_COPIES sh_callee_copies
518 #undef TARGET_ARG_PARTIAL_BYTES
519 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
520 #undef TARGET_FUNCTION_ARG
521 #define TARGET_FUNCTION_ARG sh_function_arg
522 #undef TARGET_FUNCTION_ARG_ADVANCE
523 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
525 #undef TARGET_BUILD_BUILTIN_VA_LIST
526 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
527 #undef TARGET_EXPAND_BUILTIN_VA_START
528 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
529 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
530 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
532 #undef TARGET_SCALAR_MODE_SUPPORTED_P
533 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
534 #undef TARGET_VECTOR_MODE_SUPPORTED_P
535 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
537 #undef TARGET_CHECK_PCH_TARGET_FLAGS
538 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
540 #undef TARGET_DWARF_CALLING_CONVENTION
541 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
543 #undef TARGET_FRAME_POINTER_REQUIRED
544 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
546 /* Return regmode weight for insn. */
547 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
549 /* Return current register pressure for regmode. */
550 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
552 #undef TARGET_ENCODE_SECTION_INFO
553 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
555 #undef TARGET_SECONDARY_RELOAD
556 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
558 #undef TARGET_PREFERRED_RELOAD_CLASS
559 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
561 #undef TARGET_CONDITIONAL_REGISTER_USAGE
562 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
564 #undef TARGET_LEGITIMATE_ADDRESS_P
565 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
567 #undef TARGET_TRAMPOLINE_INIT
568 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
569 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
570 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
572 #undef TARGET_LEGITIMATE_CONSTANT_P
573 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
575 /* Machine-specific symbol_ref flags. */
576 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
578 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
579 is used by optabs.c atomic op expansion code as well as in sync.md. */
580 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
581 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
583 struct gcc_target targetm = TARGET_INITIALIZER;
585 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
586 various options, and do some machine dependent initialization. */
588 sh_option_override (void)
592 SUBTARGET_OVERRIDE_OPTIONS;
593 if (optimize > 1 && !optimize_size)
594 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
595 if (flag_finite_math_only == 2)
596 flag_finite_math_only
597 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
598 if (TARGET_SH2E && !flag_finite_math_only)
599 target_flags |= MASK_IEEE;
600 sh_cpu = PROCESSOR_SH1;
601 assembler_dialect = 0;
603 sh_cpu = PROCESSOR_SH2;
605 sh_cpu = PROCESSOR_SH2E;
607 sh_cpu = PROCESSOR_SH2A;
609 sh_cpu = PROCESSOR_SH3;
611 sh_cpu = PROCESSOR_SH3E;
614 assembler_dialect = 1;
615 sh_cpu = PROCESSOR_SH4;
617 if (TARGET_SH4A_ARCH)
619 assembler_dialect = 1;
620 sh_cpu = PROCESSOR_SH4A;
624 sh_cpu = PROCESSOR_SH5;
625 target_flags |= MASK_ALIGN_DOUBLE;
626 if (TARGET_SHMEDIA_FPU)
627 target_flags |= MASK_FMOVD;
630 /* There are no delay slots on SHmedia. */
631 flag_delayed_branch = 0;
632 /* Relaxation isn't yet supported for SHmedia */
633 target_flags &= ~MASK_RELAX;
634 /* After reload, if conversion does little good but can cause
636 - find_if_block doesn't do anything for SH because we don't
637 have conditional execution patterns. (We use conditional
638 move patterns, which are handled differently, and only
640 - find_cond_trap doesn't do anything for the SH because we
641 don't have conditional traps.
642 - find_if_case_1 uses redirect_edge_and_branch_force in
643 the only path that does an optimization, and this causes
644 an ICE when branch targets are in registers.
645 - find_if_case_2 doesn't do anything for the SHmedia after
646 reload except when it can redirect a tablejump - and
647 that's rather rare. */
648 flag_if_conversion2 = 0;
649 if (! strcmp (sh_div_str, "call"))
650 sh_div_strategy = SH_DIV_CALL;
651 else if (! strcmp (sh_div_str, "call2"))
652 sh_div_strategy = SH_DIV_CALL2;
653 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
654 sh_div_strategy = SH_DIV_FP;
655 else if (! strcmp (sh_div_str, "inv"))
656 sh_div_strategy = SH_DIV_INV;
657 else if (! strcmp (sh_div_str, "inv:minlat"))
658 sh_div_strategy = SH_DIV_INV_MINLAT;
659 else if (! strcmp (sh_div_str, "inv20u"))
660 sh_div_strategy = SH_DIV_INV20U;
661 else if (! strcmp (sh_div_str, "inv20l"))
662 sh_div_strategy = SH_DIV_INV20L;
663 else if (! strcmp (sh_div_str, "inv:call2"))
664 sh_div_strategy = SH_DIV_INV_CALL2;
665 else if (! strcmp (sh_div_str, "inv:call"))
666 sh_div_strategy = SH_DIV_INV_CALL;
667 else if (! strcmp (sh_div_str, "inv:fp"))
670 sh_div_strategy = SH_DIV_INV_FP;
672 sh_div_strategy = SH_DIV_INV;
674 TARGET_CBRANCHDI4 = 0;
675 /* Assembler CFI isn't yet fully supported for SHmedia. */
676 flag_dwarf2_cfi_asm = 0;
681 /* Only the sh64-elf assembler fully supports .quad properly. */
682 targetm.asm_out.aligned_op.di = NULL;
683 targetm.asm_out.unaligned_op.di = NULL;
687 if (! strcmp (sh_div_str, "call-div1"))
688 sh_div_strategy = SH_DIV_CALL_DIV1;
689 else if (! strcmp (sh_div_str, "call-fp")
690 && (TARGET_FPU_DOUBLE
691 || (TARGET_HARD_SH4 && TARGET_SH2E)
692 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
693 sh_div_strategy = SH_DIV_CALL_FP;
694 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
695 sh_div_strategy = SH_DIV_CALL_TABLE;
697 /* Pick one that makes most sense for the target in general.
698 It is not much good to use different functions depending
699 on -Os, since then we'll end up with two different functions
700 when some of the code is compiled for size, and some for
703 /* SH4 tends to emphasize speed. */
705 sh_div_strategy = SH_DIV_CALL_TABLE;
706 /* These have their own way of doing things. */
707 else if (TARGET_SH2A)
708 sh_div_strategy = SH_DIV_INTRINSIC;
709 /* ??? Should we use the integer SHmedia function instead? */
710 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
711 sh_div_strategy = SH_DIV_CALL_FP;
712 /* SH1 .. SH3 cores often go into small-footprint systems, so
713 default to the smallest implementation available. */
714 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
715 sh_div_strategy = SH_DIV_CALL_TABLE;
717 sh_div_strategy = SH_DIV_CALL_DIV1;
720 TARGET_PRETEND_CMOVE = 0;
721 if (sh_divsi3_libfunc[0])
722 ; /* User supplied - leave it alone. */
723 else if (TARGET_DIVIDE_CALL_FP)
724 sh_divsi3_libfunc = "__sdivsi3_i4";
725 else if (TARGET_DIVIDE_CALL_TABLE)
726 sh_divsi3_libfunc = "__sdivsi3_i4i";
728 sh_divsi3_libfunc = "__sdivsi3_1";
730 sh_divsi3_libfunc = "__sdivsi3";
731 if (sh_branch_cost == -1)
735 /* The SH1 does not have delay slots, hence we get a pipeline stall
736 at every branch. The SH4 is superscalar, so the single delay slot
737 is not sufficient to keep both pipelines filled. */
738 if (! TARGET_SH2 || TARGET_HARD_SH4)
742 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
743 if (! VALID_REGISTER_P (regno))
744 sh_register_names[regno][0] = '\0';
746 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
747 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
748 sh_additional_register_names[regno][0] = '\0';
750 flag_omit_frame_pointer = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
752 if ((flag_pic && ! TARGET_PREFERGOT)
753 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
754 flag_no_function_cse = 1;
756 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
758 /* Never run scheduling before reload, since that can
759 break global alloc, and generates slower code anyway due
760 to the pressure on R0. */
761 /* Enable sched1 for SH4 if the user explicitly requests.
762 When sched1 is enabled, the ready queue will be reordered by
763 the target hooks if pressure is high. We can not do this for
764 PIC, SH3 and lower as they give spill failures for R0. */
765 if (!TARGET_HARD_SH4 || flag_pic)
766 flag_schedule_insns = 0;
767 /* ??? Current exception handling places basic block boundaries
768 after call_insns. It causes the high pressure on R0 and gives
769 spill failures for R0 in reload. See PR 22553 and the thread
771 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
772 else if (flag_exceptions)
774 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
775 warning (0, "ignoring -fschedule-insns because of exception handling bug");
776 flag_schedule_insns = 0;
778 else if (flag_schedule_insns
779 && !global_options_set.x_flag_schedule_insns)
780 flag_schedule_insns = 0;
783 if ((target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) == 0)
784 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
786 /* Unwind info is not correct around the CFG unless either a frame
787 pointer is present or M_A_O_A is set. Fixing this requires rewriting
788 unwind info generation to be aware of the CFG and propagating states
790 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
791 || flag_exceptions || flag_non_call_exceptions)
792 && flag_omit_frame_pointer
793 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
795 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
796 warning (0, "unwind tables currently require either a frame pointer "
797 "or -maccumulate-outgoing-args for correctness");
798 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
801 /* Unwinding with -freorder-blocks-and-partition does not work on this
802 architecture, because it requires far jumps to label crossing between
803 hot/cold sections which are rejected on this architecture. */
804 if (flag_reorder_blocks_and_partition)
808 inform (input_location,
809 "-freorder-blocks-and-partition does not work with "
810 "exceptions on this architecture");
811 flag_reorder_blocks_and_partition = 0;
812 flag_reorder_blocks = 1;
814 else if (flag_unwind_tables)
816 inform (input_location,
817 "-freorder-blocks-and-partition does not support unwind "
818 "info on this architecture");
819 flag_reorder_blocks_and_partition = 0;
820 flag_reorder_blocks = 1;
824 if (align_loops == 0)
825 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
826 if (align_jumps == 0)
827 align_jumps = 1 << CACHE_LOG;
828 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
829 align_jumps = TARGET_SHMEDIA ? 4 : 2;
831 /* Allocation boundary (in *bytes*) for the code of a function.
832 SH1: 32 bit alignment is faster, because instructions are always
833 fetched as a pair from a longword boundary.
834 SH2 .. SH5 : align to cache line start. */
835 if (align_functions == 0)
837 = optimize_size ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
838 /* The linker relaxation code breaks when a function contains
839 alignments that are larger than that at the start of a
844 = align_loops > align_jumps ? align_loops : align_jumps;
846 /* Also take possible .long constants / mova tables int account. */
849 if (align_functions < min_align)
850 align_functions = min_align;
853 if (sh_fixed_range_str)
854 sh_fix_range (sh_fixed_range_str);
856 /* This target defaults to strict volatile bitfields. */
857 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
858 flag_strict_volatile_bitfields = 1;
861 /* Print the operand address in x to the stream. */
864 sh_print_operand_address (FILE *stream, rtx x)
866 switch (GET_CODE (x))
870 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
875 rtx base = XEXP (x, 0);
876 rtx index = XEXP (x, 1);
878 switch (GET_CODE (index))
881 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
882 reg_names[true_regnum (base)]);
888 int base_num = true_regnum (base);
889 int index_num = true_regnum (index);
891 fprintf (stream, "@(r0,%s)",
892 reg_names[MAX (base_num, index_num)]);
903 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
907 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
911 x = mark_constant_pool_use (x);
912 output_addr_const (stream, x);
917 /* Print operand x (an rtx) in assembler syntax to file stream
918 according to modifier code.
920 '.' print a .s if insn needs delay slot
921 ',' print LOCAL_LABEL_PREFIX
922 '@' print trap, rte or rts depending upon pragma interruptness
923 '#' output a nop if there is nothing to put in the delay slot
924 ''' print likelihood suffix (/u for unlikely).
925 '>' print branch target if -fverbose-asm
926 'O' print a constant without the #
927 'R' print the LSW of a dp value - changes if in little endian
928 'S' print the MSW of a dp value - changes if in little endian
929 'T' print the next word of a dp value - same as 'R' in big endian mode.
930 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
931 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
932 'N' print 'r63' if the operand is (const_int 0).
933 'd' print a V2SF reg as dN instead of fpN.
934 'm' print a pair `base,offset' or `base,index', for LD and ST.
935 'U' Likewise for {LD,ST}{HI,LO}.
936 'V' print the position of a single bit set.
937 'W' print the position of a single bit cleared.
938 't' print a memory address which is a register.
939 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
940 'o' output an operator. */
943 sh_print_operand (FILE *stream, rtx x, int code)
946 enum machine_mode mode;
954 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
955 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
956 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
959 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
962 trapa_attr = lookup_attribute ("trap_exit",
963 DECL_ATTRIBUTES (current_function_decl));
965 fprintf (stream, "trapa #%ld",
966 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
967 else if (sh_cfun_interrupt_handler_p ())
969 if (sh_cfun_resbank_handler_p ())
970 fprintf (stream, "resbank\n");
971 fprintf (stream, "rte");
974 fprintf (stream, "rts");
977 /* Output a nop if there's nothing in the delay slot. */
978 if (dbr_sequence_length () == 0)
979 fprintf (stream, "\n\tnop");
983 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
985 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
986 fputs ("/u", stream);
990 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
992 fputs ("\t! target: ", stream);
993 output_addr_const (stream, JUMP_LABEL (current_output_insn));
997 x = mark_constant_pool_use (x);
998 output_addr_const (stream, x);
1000 /* N.B.: %R / %S / %T adjust memory addresses by four.
1001 For SHMEDIA, that means they can be used to access the first and
1002 second 32 bit part of a 64 bit (or larger) value that
1003 might be held in floating point registers or memory.
1004 While they can be used to access 64 bit parts of a larger value
1005 held in general purpose registers, that won't work with memory -
1006 neither for fp registers, since the frxx names are used. */
1008 if (REG_P (x) || GET_CODE (x) == SUBREG)
1010 regno = true_regnum (x);
1011 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1012 fputs (reg_names[regno], (stream));
1016 x = adjust_address (x, SImode, 4 * LSW);
1017 sh_print_operand_address (stream, XEXP (x, 0));
1023 mode = GET_MODE (x);
1024 if (mode == VOIDmode)
1026 if (GET_MODE_SIZE (mode) >= 8)
1027 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1029 sh_print_operand (stream, sub, 0);
1031 output_operand_lossage ("invalid operand to %%R");
1035 if (REG_P (x) || GET_CODE (x) == SUBREG)
1037 regno = true_regnum (x);
1038 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1039 fputs (reg_names[regno], (stream));
1043 x = adjust_address (x, SImode, 4 * MSW);
1044 sh_print_operand_address (stream, XEXP (x, 0));
1050 mode = GET_MODE (x);
1051 if (mode == VOIDmode)
1053 if (GET_MODE_SIZE (mode) >= 8)
1054 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1056 sh_print_operand (stream, sub, 0);
1058 output_operand_lossage ("invalid operand to %%S");
1062 /* Next word of a double. */
1063 switch (GET_CODE (x))
1066 fputs (reg_names[REGNO (x) + 1], (stream));
1069 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1070 && GET_CODE (XEXP (x, 0)) != POST_INC)
1071 x = adjust_address (x, SImode, 4);
1072 sh_print_operand_address (stream, XEXP (x, 0));
1080 gcc_assert (MEM_P (x));
1082 switch (GET_CODE (x))
1086 sh_print_operand (stream, x, 0);
1094 switch (GET_CODE (x))
1096 case PLUS: fputs ("add", stream); break;
1097 case MINUS: fputs ("sub", stream); break;
1098 case MULT: fputs ("mul", stream); break;
1099 case DIV: fputs ("div", stream); break;
1100 case EQ: fputs ("eq", stream); break;
1101 case NE: fputs ("ne", stream); break;
1102 case GT: case LT: fputs ("gt", stream); break;
1103 case GE: case LE: fputs ("ge", stream); break;
1104 case GTU: case LTU: fputs ("gtu", stream); break;
1105 case GEU: case LEU: fputs ("geu", stream); break;
1114 && GET_CODE (XEXP (x, 0)) == PLUS
1115 && (REG_P (XEXP (XEXP (x, 0), 1))
1116 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1117 fputc ('x', stream);
1123 switch (GET_MODE (x))
1125 case QImode: fputs (".b", stream); break;
1126 case HImode: fputs (".w", stream); break;
1127 case SImode: fputs (".l", stream); break;
1128 case SFmode: fputs (".s", stream); break;
1129 case DFmode: fputs (".d", stream); break;
1130 default: gcc_unreachable ();
1137 gcc_assert (MEM_P (x));
1141 switch (GET_CODE (x))
1145 sh_print_operand (stream, x, 0);
1146 fputs (", 0", stream);
1150 sh_print_operand (stream, XEXP (x, 0), 0);
1151 fputs (", ", stream);
1152 sh_print_operand (stream, XEXP (x, 1), 0);
1162 int num = exact_log2 (INTVAL (x));
1163 gcc_assert (num >= 0);
1164 fprintf (stream, "#%d", num);
1170 int num = exact_log2 (~INTVAL (x));
1171 gcc_assert (num >= 0);
1172 fprintf (stream, "#%d", num);
1177 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1179 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1183 if (x == CONST0_RTX (GET_MODE (x)))
1185 fprintf ((stream), "r63");
1188 goto default_output;
1190 if (CONST_INT_P (x))
1192 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1200 mode = GET_MODE (x);
1202 switch (GET_CODE (x))
1206 rtx inner = XEXP (x, 0);
1208 enum machine_mode inner_mode;
1210 /* We might see SUBREGs with vector mode registers inside. */
1211 if (GET_CODE (inner) == SUBREG
1212 && (GET_MODE_SIZE (GET_MODE (inner))
1213 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1214 && subreg_lowpart_p (inner))
1215 inner = SUBREG_REG (inner);
1216 if (CONST_INT_P (inner))
1218 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1219 goto default_output;
1221 inner_mode = GET_MODE (inner);
1222 if (GET_CODE (inner) == SUBREG
1223 && (GET_MODE_SIZE (GET_MODE (inner))
1224 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1225 && REG_P (SUBREG_REG (inner)))
1227 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1228 GET_MODE (SUBREG_REG (inner)),
1229 SUBREG_BYTE (inner),
1231 inner = SUBREG_REG (inner);
1233 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1235 /* Floating point register pairs are always big endian;
1236 general purpose registers are 64 bit wide. */
1237 regno = REGNO (inner);
1238 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1239 - HARD_REGNO_NREGS (regno, mode))
1247 /* FIXME: We need this on SHmedia32 because reload generates
1248 some sign-extended HI or QI loads into DImode registers
1249 but, because Pmode is SImode, the address ends up with a
1250 subreg:SI of the DImode register. Maybe reload should be
1251 fixed so as to apply alter_subreg to such loads? */
1253 gcc_assert (trapping_target_operand (x, VOIDmode));
1254 x = XEXP (XEXP (x, 2), 0);
1255 goto default_output;
1257 gcc_assert (SUBREG_BYTE (x) == 0
1258 && REG_P (SUBREG_REG (x)));
1266 if (FP_REGISTER_P (regno)
1267 && mode == V16SFmode)
1268 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1269 else if (FP_REGISTER_P (REGNO (x))
1270 && mode == V4SFmode)
1271 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1273 && mode == V2SFmode)
1274 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1275 else if (FP_REGISTER_P (REGNO (x))
1276 && GET_MODE_SIZE (mode) > 4)
1277 fprintf ((stream), "d%s", reg_names[regno] + 1);
1279 fputs (reg_names[regno], (stream));
1283 output_address (XEXP (x, 0));
1288 fputc ('#', stream);
1289 output_addr_const (stream, x);
1297 sh_print_operand_punct_valid_p (unsigned char code)
1299 return (code == '.' || code == '#' || code == '@' || code == ','
1300 || code == '$' || code == '\'' || code == '>');
1303 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1306 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1308 if (GET_CODE (x) == UNSPEC)
1310 switch (XINT (x, 1))
1312 case UNSPEC_DATALABEL:
1313 fputs ("datalabel ", file);
1314 output_addr_const (file, XVECEXP (x, 0, 0));
1317 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1318 output_addr_const (file, XVECEXP (x, 0, 0));
1321 output_addr_const (file, XVECEXP (x, 0, 0));
1322 fputs ("@GOT", file);
1325 output_addr_const (file, XVECEXP (x, 0, 0));
1326 fputs ("@GOTOFF", file);
1329 output_addr_const (file, XVECEXP (x, 0, 0));
1330 fputs ("@PLT", file);
1333 output_addr_const (file, XVECEXP (x, 0, 0));
1334 fputs ("@GOTPLT", file);
1337 output_addr_const (file, XVECEXP (x, 0, 0));
1338 fputs ("@DTPOFF", file);
1340 case UNSPEC_GOTTPOFF:
1341 output_addr_const (file, XVECEXP (x, 0, 0));
1342 fputs ("@GOTTPOFF", file);
1345 output_addr_const (file, XVECEXP (x, 0, 0));
1346 fputs ("@TPOFF", file);
1351 /* LPCS stands for Label for PIC Call Site. */
1352 targetm.asm_out.generate_internal_label (name, "LPCS",
1353 INTVAL (XVECEXP (x, 0, 0)));
1354 assemble_name (file, name);
1357 case UNSPEC_EXTRACT_S16:
1358 case UNSPEC_EXTRACT_U16:
1362 val = XVECEXP (x, 0, 0);
1363 shift = XVECEXP (x, 0, 1);
1365 if (shift != const0_rtx)
1367 if (GET_CODE (val) == CONST
1368 || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ)
1371 output_addr_const (file, val);
1375 output_addr_const (file, val);
1376 if (shift != const0_rtx)
1378 fputs (" >> ", file);
1379 output_addr_const (file, shift);
1382 fputs (" & 65535)", file);
1386 output_addr_const (file, XVECEXP (x, 0, 0));
1388 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1391 output_addr_const (file, XVECEXP (x, 0, 1));
1395 output_addr_const (file, XVECEXP (x, 0, 1));
1397 case UNSPEC_PCREL_SYMOFF:
1398 output_addr_const (file, XVECEXP (x, 0, 0));
1400 output_addr_const (file, XVECEXP (x, 0, 1));
1401 fputs ("-.)", file);
1413 /* Encode symbol attributes of a SYMBOL_REF into its
1414 SYMBOL_REF_FLAGS. */
1416 sh_encode_section_info (tree decl, rtx rtl, int first)
1418 default_encode_section_info (decl, rtl, first);
1420 if (TREE_CODE (decl) == FUNCTION_DECL
1421 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1422 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1425 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1427 force_into (rtx value, rtx target)
1429 value = force_operand (value, target);
1430 if (! rtx_equal_p (value, target))
1431 emit_insn (gen_move_insn (target, value));
1434 /* Emit code to perform a block move. Choose the best method.
1436 OPERANDS[0] is the destination.
1437 OPERANDS[1] is the source.
1438 OPERANDS[2] is the size.
1439 OPERANDS[3] is the alignment safe to use. */
1442 expand_block_move (rtx *operands)
1444 int align = INTVAL (operands[3]);
1445 int constp = (CONST_INT_P (operands[2]));
1446 int bytes = (constp ? INTVAL (operands[2]) : 0);
1451 /* If we could use mov.l to move words and dest is word-aligned, we
1452 can use movua.l for loads and still generate a relatively short
1453 and efficient sequence. */
1454 if (TARGET_SH4A_ARCH && align < 4
1455 && MEM_ALIGN (operands[0]) >= 32
1456 && can_move_by_pieces (bytes, 32))
1458 rtx dest = copy_rtx (operands[0]);
1459 rtx src = copy_rtx (operands[1]);
1460 /* We could use different pseudos for each copied word, but
1461 since movua can only load into r0, it's kind of
1463 rtx temp = gen_reg_rtx (SImode);
1464 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1467 while (copied + 4 <= bytes)
1469 rtx to = adjust_address (dest, SImode, copied);
1470 rtx from = adjust_automodify_address (src, BLKmode,
1473 set_mem_size (from, 4);
1474 emit_insn (gen_movua (temp, from));
1475 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1476 emit_move_insn (to, temp);
1481 move_by_pieces (adjust_address (dest, BLKmode, copied),
1482 adjust_automodify_address (src, BLKmode,
1484 bytes - copied, align, 0);
1489 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1490 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1491 if (align < 4 || (bytes % 4 != 0))
1494 if (TARGET_HARD_SH4)
1498 else if (bytes == 12)
1500 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1501 rtx r4 = gen_rtx_REG (SImode, 4);
1502 rtx r5 = gen_rtx_REG (SImode, 5);
1504 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1505 force_into (XEXP (operands[0], 0), r4);
1506 force_into (XEXP (operands[1], 0), r5);
1507 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1510 else if (! optimize_size)
1512 const char *entry_name;
1513 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1515 rtx r4 = gen_rtx_REG (SImode, 4);
1516 rtx r5 = gen_rtx_REG (SImode, 5);
1517 rtx r6 = gen_rtx_REG (SImode, 6);
1519 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1520 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1521 force_into (XEXP (operands[0], 0), r4);
1522 force_into (XEXP (operands[1], 0), r5);
1524 dwords = bytes >> 3;
1525 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1526 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1535 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1536 rtx r4 = gen_rtx_REG (SImode, 4);
1537 rtx r5 = gen_rtx_REG (SImode, 5);
1539 sprintf (entry, "__movmemSI%d", bytes);
1540 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1541 force_into (XEXP (operands[0], 0), r4);
1542 force_into (XEXP (operands[1], 0), r5);
1543 emit_insn (gen_block_move_real (func_addr_rtx));
1547 /* This is the same number of bytes as a memcpy call, but to a different
1548 less common function name, so this will occasionally use more space. */
1549 if (! optimize_size)
1551 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1552 int final_switch, while_loop;
1553 rtx r4 = gen_rtx_REG (SImode, 4);
1554 rtx r5 = gen_rtx_REG (SImode, 5);
1555 rtx r6 = gen_rtx_REG (SImode, 6);
1557 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1558 force_into (XEXP (operands[0], 0), r4);
1559 force_into (XEXP (operands[1], 0), r5);
1561 /* r6 controls the size of the move. 16 is decremented from it
1562 for each 64 bytes moved. Then the negative bit left over is used
1563 as an index into a list of move instructions. e.g., a 72 byte move
1564 would be set up with size(r6) = 14, for one iteration through the
1565 big while loop, and a switch of -2 for the last part. */
1567 final_switch = 16 - ((bytes / 4) % 16);
1568 while_loop = ((bytes / 4) / 16 - 1) * 16;
1569 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1570 emit_insn (gen_block_lump_real (func_addr_rtx));
1577 /* Prepare operands for a move define_expand; specifically, one of the
1578 operands must be in a register. */
1581 prepare_move_operands (rtx operands[], enum machine_mode mode)
1583 if ((mode == SImode || mode == DImode)
1585 && ! ((mode == Pmode || mode == ptr_mode)
1586 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1589 if (SYMBOLIC_CONST_P (operands[1]))
1591 if (MEM_P (operands[0]))
1592 operands[1] = force_reg (Pmode, operands[1]);
1593 else if (TARGET_SHMEDIA
1594 && GET_CODE (operands[1]) == LABEL_REF
1595 && target_reg_operand (operands[0], mode))
1599 temp = (!can_create_pseudo_p ()
1601 : gen_reg_rtx (Pmode));
1602 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1605 else if (GET_CODE (operands[1]) == CONST
1606 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1607 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1609 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1610 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1612 operands[1] = expand_binop (mode, add_optab, temp,
1613 XEXP (XEXP (operands[1], 0), 1),
1614 (!can_create_pseudo_p ()
1616 : gen_reg_rtx (Pmode)),
1617 0, OPTAB_LIB_WIDEN);
1621 if (! reload_in_progress && ! reload_completed)
1623 /* Copy the source to a register if both operands aren't registers. */
1624 if (! register_operand (operands[0], mode)
1625 && ! sh_register_operand (operands[1], mode))
1626 operands[1] = copy_to_mode_reg (mode, operands[1]);
1628 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1630 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1631 except that we can't use that function because it is static. */
1632 rtx new_rtx = change_address (operands[0], mode, 0);
1633 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1634 operands[0] = new_rtx;
1637 /* This case can happen while generating code to move the result
1638 of a library call to the target. Reject `st r0,@(rX,rY)' because
1639 reload will fail to find a spill register for rX, since r0 is already
1640 being used for the source. */
1642 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1643 && MEM_P (operands[0])
1644 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1645 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1646 operands[1] = copy_to_mode_reg (mode, operands[1]);
1649 if (mode == Pmode || mode == ptr_mode)
1652 enum tls_model tls_kind;
1656 if (GET_CODE (op1) == CONST
1657 && GET_CODE (XEXP (op1, 0)) == PLUS
1658 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1661 opc = XEXP (XEXP (op1, 0), 1);
1662 op1 = XEXP (XEXP (op1, 0), 0);
1667 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1669 rtx tga_op1, tga_ret, tmp, tmp2;
1672 && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC
1673 || tls_kind == TLS_MODEL_LOCAL_DYNAMIC
1674 || tls_kind == TLS_MODEL_INITIAL_EXEC))
1676 /* Don't schedule insns for getting GOT address when
1677 the first scheduling is enabled, to avoid spill
1679 if (flag_schedule_insns)
1680 emit_insn (gen_blockage ());
1681 emit_insn (gen_GOTaddr2picreg ());
1682 emit_use (gen_rtx_REG (SImode, PIC_REG));
1683 if (flag_schedule_insns)
1684 emit_insn (gen_blockage ());
1689 case TLS_MODEL_GLOBAL_DYNAMIC:
1690 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1691 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1692 tmp = gen_reg_rtx (Pmode);
1693 emit_move_insn (tmp, tga_ret);
1697 case TLS_MODEL_LOCAL_DYNAMIC:
1698 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1699 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1701 tmp = gen_reg_rtx (Pmode);
1702 emit_move_insn (tmp, tga_ret);
1704 if (register_operand (op0, Pmode))
1707 tmp2 = gen_reg_rtx (Pmode);
1709 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1713 case TLS_MODEL_INITIAL_EXEC:
1714 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1715 tmp = gen_sym2GOTTPOFF (op1);
1716 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1720 case TLS_MODEL_LOCAL_EXEC:
1721 tmp2 = gen_reg_rtx (Pmode);
1722 emit_insn (gen_load_gbr (tmp2));
1723 tmp = gen_reg_rtx (Pmode);
1724 emit_insn (gen_symTPOFF2reg (tmp, op1));
1726 if (register_operand (op0, Pmode))
1729 op1 = gen_reg_rtx (Pmode);
1731 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1738 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1747 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1748 enum rtx_code comparison)
1751 rtx scratch = NULL_RTX;
1753 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1754 comparison = GET_CODE (operands[0]);
1756 scratch = operands[4];
1757 if (CONST_INT_P (operands[1])
1758 && !CONST_INT_P (operands[2]))
1760 rtx tmp = operands[1];
1762 operands[1] = operands[2];
1764 comparison = swap_condition (comparison);
1766 if (CONST_INT_P (operands[2]))
1768 HOST_WIDE_INT val = INTVAL (operands[2]);
1769 if ((val == -1 || val == -0x81)
1770 && (comparison == GT || comparison == LE))
1772 comparison = (comparison == GT) ? GE : LT;
1773 operands[2] = gen_int_mode (val + 1, mode);
1775 else if ((val == 1 || val == 0x80)
1776 && (comparison == GE || comparison == LT))
1778 comparison = (comparison == GE) ? GT : LE;
1779 operands[2] = gen_int_mode (val - 1, mode);
1781 else if (val == 1 && (comparison == GEU || comparison == LTU))
1783 comparison = (comparison == GEU) ? NE : EQ;
1784 operands[2] = CONST0_RTX (mode);
1786 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1788 comparison = (comparison == GEU) ? GTU : LEU;
1789 operands[2] = gen_int_mode (val - 1, mode);
1791 else if (val == 0 && (comparison == GTU || comparison == LEU))
1792 comparison = (comparison == GTU) ? NE : EQ;
1793 else if (mode == SImode
1794 && ((val == 0x7fffffff
1795 && (comparison == GTU || comparison == LEU))
1796 || ((unsigned HOST_WIDE_INT) val
1797 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1798 && (comparison == GEU || comparison == LTU))))
1800 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1801 operands[2] = CONST0_RTX (mode);
1805 if (can_create_pseudo_p ())
1806 operands[1] = force_reg (mode, op1);
1807 /* When we are handling DImode comparisons, we want to keep constants so
1808 that we can optimize the component comparisons; however, memory loads
1809 are better issued as a whole so that they can be scheduled well.
1810 SImode equality comparisons allow I08 constants, but only when they
1811 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1812 into a register, that register might as well be r0, and we allow the
1813 constant. If it is already in a register, this is likely to be
1814 allocated to a different hard register, thus we load the constant into
1815 a register unless it is zero. */
1816 if (!REG_P (operands[2])
1817 && (!CONST_INT_P (operands[2])
1818 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1819 && ((comparison != EQ && comparison != NE)
1820 || (REG_P (op1) && REGNO (op1) != R0_REG)
1821 || !satisfies_constraint_I08 (operands[2])))))
1823 if (scratch && GET_MODE (scratch) == mode)
1825 emit_move_insn (scratch, operands[2]);
1826 operands[2] = scratch;
1828 else if (can_create_pseudo_p ())
1829 operands[2] = force_reg (mode, operands[2]);
1835 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1837 rtx (*branch_expander) (rtx) = gen_branch_true;
1840 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1843 case NE: case LT: case LE: case LTU: case LEU:
1844 comparison = reverse_condition (comparison);
1845 branch_expander = gen_branch_false;
1848 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1849 gen_rtx_fmt_ee (comparison, SImode,
1850 operands[1], operands[2])));
1851 jump = emit_jump_insn (branch_expander (operands[3]));
1852 if (probability >= 0)
1853 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1857 /* ??? How should we distribute probabilities when more than one branch
1858 is generated. So far we only have some ad-hoc observations:
1859 - If the operands are random, they are likely to differ in both parts.
1860 - If comparing items in a hash chain, the operands are random or equal;
1861 operation should be EQ or NE.
1862 - If items are searched in an ordered tree from the root, we can expect
1863 the highpart to be unequal about half of the time; operation should be
1864 an inequality comparison, operands non-constant, and overall probability
1865 about 50%. Likewise for quicksort.
1866 - Range checks will be often made against constants. Even if we assume for
1867 simplicity an even distribution of the non-constant operand over a
1868 sub-range here, the same probability could be generated with differently
1869 wide sub-ranges - as long as the ratio of the part of the subrange that
1870 is before the threshold to the part that comes after the threshold stays
1871 the same. Thus, we can't really tell anything here;
1872 assuming random distribution is at least simple.
1876 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1878 enum rtx_code msw_taken, msw_skip, lsw_taken;
1879 rtx skip_label = NULL_RTX;
1880 rtx op1h, op1l, op2h, op2l;
1883 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1884 rtx scratch = operands[4];
1886 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1887 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1888 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1889 op1l = gen_lowpart (SImode, operands[1]);
1890 op2l = gen_lowpart (SImode, operands[2]);
1891 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1892 prob = split_branch_probability;
1893 rev_prob = REG_BR_PROB_BASE - prob;
1896 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1897 That costs 1 cycle more when the first branch can be predicted taken,
1898 but saves us mispredicts because only one branch needs prediction.
1899 It also enables generating the cmpeqdi_t-1 pattern. */
1901 if (TARGET_CMPEQDI_T)
1903 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1904 emit_jump_insn (gen_branch_true (operands[3]));
1911 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1913 msw_skip_prob = rev_prob;
1914 if (REG_BR_PROB_BASE <= 65535)
1915 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1918 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1922 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1923 / ((HOST_WIDEST_INT) prob << 32)))
1929 if (TARGET_CMPEQDI_T)
1931 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1932 emit_jump_insn (gen_branch_false (operands[3]));
1936 msw_taken_prob = prob;
1941 msw_taken = comparison;
1942 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1944 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1945 msw_skip = swap_condition (msw_taken);
1949 if (op2l == CONST0_RTX (SImode))
1950 msw_taken = comparison;
1953 msw_taken = comparison == GE ? GT : GTU;
1954 msw_skip = swap_condition (msw_taken);
1959 msw_taken = comparison;
1960 if (op2l == CONST0_RTX (SImode))
1962 msw_skip = swap_condition (msw_taken);
1966 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1967 msw_taken = comparison;
1971 if (comparison == LE)
1973 else if (op2h != CONST0_RTX (SImode))
1977 msw_skip = swap_condition (LTU);
1980 msw_skip = swap_condition (msw_taken);
1983 default: return false;
1985 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1986 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1987 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1988 if (comparison != EQ && comparison != NE && num_branches > 1)
1990 if (!CONSTANT_P (operands[2])
1991 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1992 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1994 msw_taken_prob = prob / 2U;
1996 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1997 lsw_taken_prob = prob;
2001 msw_taken_prob = prob;
2002 msw_skip_prob = REG_BR_PROB_BASE;
2003 /* ??? If we have a constant op2h, should we use that when
2004 calculating lsw_taken_prob? */
2005 lsw_taken_prob = prob;
2010 operands[4] = NULL_RTX;
2011 if (reload_completed
2012 && ! arith_reg_or_0_operand (op2h, SImode)
2013 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
2014 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
2015 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
2017 emit_move_insn (scratch, operands[2]);
2018 operands[2] = scratch;
2020 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2021 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2022 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2024 rtx taken_label = operands[3];
2026 /* Operands were possibly modified, but msw_skip doesn't expect this.
2027 Always use the original ones. */
2028 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2032 if (reload_completed
2033 && ! arith_reg_or_0_operand (op2h, SImode)
2034 && (true_regnum (op1h) || (comparison != EQ && comparison != NE)))
2036 emit_move_insn (scratch, operands[2]);
2037 operands[2] = scratch;
2041 operands[3] = skip_label = gen_label_rtx ();
2042 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2043 operands[3] = taken_label;
2047 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2049 if (reload_completed
2050 && ! arith_reg_or_0_operand (op2l, SImode)
2051 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2053 emit_move_insn (scratch, operands[2]);
2054 operands[2] = scratch;
2056 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2058 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2059 emit_label (skip_label);
2063 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2066 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2068 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2070 insn = gen_rtx_PARALLEL (VOIDmode,
2072 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2073 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2079 /* Prepare the operands for an scc instruction; make sure that the
2080 compare has been done and the result is in T_REG. */
2082 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2084 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2085 enum rtx_code oldcode = code;
2086 enum machine_mode mode;
2088 /* First need a compare insn. */
2092 /* It isn't possible to handle this case. */
2109 if (code != oldcode)
2116 mode = GET_MODE (op0);
2117 if (mode == VOIDmode)
2118 mode = GET_MODE (op1);
2120 op0 = force_reg (mode, op0);
2121 if ((code != EQ && code != NE
2122 && (op1 != const0_rtx
2123 || code == GTU || code == GEU || code == LTU || code == LEU))
2124 || (mode == DImode && op1 != const0_rtx)
2125 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2126 op1 = force_reg (mode, op1);
2128 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2129 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2134 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2137 rtx target = gen_reg_rtx (SImode);
2140 gcc_assert (TARGET_SHMEDIA);
2149 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2150 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2160 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2161 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2179 rtx t2 = gen_reg_rtx (DImode);
2180 emit_insn (gen_extendsidi2 (t2, target));
2184 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2187 /* Called from the md file, set up the operands of a compare instruction. */
2190 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2192 enum rtx_code code = GET_CODE (operands[0]);
2193 enum rtx_code branch_code;
2194 rtx op0 = operands[1];
2195 rtx op1 = operands[2];
2197 bool need_ccmpeq = false;
2199 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2201 op0 = force_reg (mode, op0);
2202 op1 = force_reg (mode, op1);
2206 if (code != EQ || mode == DImode)
2208 /* Force args into regs, since we can't use constants here. */
2209 op0 = force_reg (mode, op0);
2210 if (op1 != const0_rtx || code == GTU || code == GEU)
2211 op1 = force_reg (mode, op1);
2215 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2218 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2219 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2221 tem = op0, op0 = op1, op1 = tem;
2222 code = swap_condition (code);
2225 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2228 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2233 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2234 to EQ/GT respectively. */
2235 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2252 branch_code = reverse_condition (code);
2258 insn = gen_rtx_SET (VOIDmode,
2259 gen_rtx_REG (SImode, T_REG),
2260 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2262 sh_emit_set_t_insn (insn, mode);
2264 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2266 if (branch_code == code)
2267 emit_jump_insn (gen_branch_true (operands[3]));
2269 emit_jump_insn (gen_branch_false (operands[3]));
2273 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2275 enum rtx_code code = GET_CODE (operands[1]);
2276 rtx op0 = operands[2];
2277 rtx op1 = operands[3];
2279 bool invert = false;
2282 op0 = force_reg (mode, op0);
2283 if ((code != EQ && code != NE
2284 && (op1 != const0_rtx
2285 || code == GTU || code == GEU || code == LTU || code == LEU))
2286 || (mode == DImode && op1 != const0_rtx)
2287 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2288 op1 = force_reg (mode, op1);
2290 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2292 if (code == LT || code == LE)
2294 code = swap_condition (code);
2295 tem = op0, op0 = op1, op1 = tem;
2301 lab = gen_label_rtx ();
2302 sh_emit_scc_to_t (EQ, op0, op1);
2303 emit_jump_insn (gen_branch_true (lab));
2320 sh_emit_scc_to_t (code, op0, op1);
2324 emit_insn (gen_movnegt (operands[0]));
2326 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2329 /* Functions to output assembly code. */
2331 /* Return a sequence of instructions to perform DI or DF move.
2333 Since the SH cannot move a DI or DF in one instruction, we have
2334 to take care when we see overlapping source and dest registers. */
2337 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2338 enum machine_mode mode)
2340 rtx dst = operands[0];
2341 rtx src = operands[1];
2344 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2345 return "mov.l %T1,%0\n\tmov.l %1,%0";
2347 if (register_operand (dst, mode)
2348 && register_operand (src, mode))
2350 if (REGNO (src) == MACH_REG)
2351 return "sts mach,%S0\n\tsts macl,%R0";
2353 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2354 when mov.d r1,r0 do r1->r0 then r2->r1. */
2356 if (REGNO (src) + 1 == REGNO (dst))
2357 return "mov %T1,%T0\n\tmov %1,%0";
2359 return "mov %1,%0\n\tmov %T1,%T0";
2361 else if (CONST_INT_P (src))
2363 if (INTVAL (src) < 0)
2364 output_asm_insn ("mov #-1,%S0", operands);
2366 output_asm_insn ("mov #0,%S0", operands);
2368 return "mov %1,%R0";
2370 else if (MEM_P (src))
2373 int dreg = REGNO (dst);
2374 rtx inside = XEXP (src, 0);
2376 switch (GET_CODE (inside))
2379 ptrreg = REGNO (inside);
2383 ptrreg = subreg_regno (inside);
2387 ptrreg = REGNO (XEXP (inside, 0));
2388 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2389 an offsettable address. Unfortunately, offsettable addresses use
2390 QImode to check the offset, and a QImode offsettable address
2391 requires r0 for the other operand, which is not currently
2392 supported, so we can't use the 'o' constraint.
2393 Thus we must check for and handle r0+REG addresses here.
2394 We punt for now, since this is likely very rare. */
2395 gcc_assert (!REG_P (XEXP (inside, 1)));
2399 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2401 return "mov.l %1,%0\n\tmov.l %1,%T0";
2406 /* Work out the safe way to copy. Copy into the second half first. */
2408 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2411 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2414 /* Print an instruction which would have gone into a delay slot after
2415 another instruction, but couldn't because the other instruction expanded
2416 into a sequence where putting the slot insn at the end wouldn't work. */
2419 print_slot (rtx insn)
2421 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2423 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2427 output_far_jump (rtx insn, rtx op)
2429 struct { rtx lab, reg, op; } this_jmp;
2430 rtx braf_base_lab = NULL_RTX;
2433 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2436 this_jmp.lab = gen_label_rtx ();
2440 && offset - get_attr_length (insn) <= 32766)
2443 jump = "mov.w %O0,%1; braf %1";
2451 jump = "mov.l %O0,%1; braf %1";
2453 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2456 jump = "mov.l %O0,%1; jmp @%1";
2458 /* If we have a scratch register available, use it. */
2459 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2460 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2462 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2463 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2464 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2465 output_asm_insn (jump, &this_jmp.lab);
2466 if (dbr_sequence_length ())
2467 print_slot (final_sequence);
2469 output_asm_insn ("nop", 0);
2473 /* Output the delay slot insn first if any. */
2474 if (dbr_sequence_length ())
2475 print_slot (final_sequence);
2477 this_jmp.reg = gen_rtx_REG (SImode, 13);
2478 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2479 Fortunately, MACL is fixed and call-clobbered, and we never
2480 need its value across jumps, so save r13 in it instead of in
2483 output_asm_insn ("lds r13, macl", 0);
2485 output_asm_insn ("mov.l r13,@-r15", 0);
2486 output_asm_insn (jump, &this_jmp.lab);
2488 output_asm_insn ("sts macl, r13", 0);
2490 output_asm_insn ("mov.l @r15+,r13", 0);
2492 if (far && flag_pic && TARGET_SH2)
2494 braf_base_lab = gen_label_rtx ();
2495 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2496 CODE_LABEL_NUMBER (braf_base_lab));
2499 output_asm_insn (".align 2", 0);
2500 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2502 if (far && flag_pic)
2505 this_jmp.lab = braf_base_lab;
2506 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2509 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2513 /* Local label counter, used for constants in the pool and inside
2514 pattern branches. */
2516 static int lf = 100;
2518 /* Output code for ordinary branches. */
2521 output_branch (int logic, rtx insn, rtx *operands)
2523 switch (get_attr_length (insn))
2526 /* This can happen if filling the delay slot has caused a forward
2527 branch to exceed its range (we could reverse it, but only
2528 when we know we won't overextend other branches; this should
2529 best be handled by relaxation).
2530 It can also happen when other condbranches hoist delay slot insn
2531 from their destination, thus leading to code size increase.
2532 But the branch will still be in the range -4092..+4098 bytes. */
2537 /* The call to print_slot will clobber the operands. */
2538 rtx op0 = operands[0];
2540 /* If the instruction in the delay slot is annulled (true), then
2541 there is no delay slot where we can put it now. The only safe
2542 place for it is after the label. final will do that by default. */
2545 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2546 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2548 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2549 ASSEMBLER_DIALECT ? "/" : ".", label);
2550 print_slot (final_sequence);
2553 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2555 output_asm_insn ("bra\t%l0", &op0);
2556 fprintf (asm_out_file, "\tnop\n");
2557 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2561 /* When relaxing, handle this like a short branch. The linker
2562 will fix it up if it still doesn't fit after relaxation. */
2564 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2566 /* These are for SH2e, in which we have to account for the
2567 extra nop because of the hardware bug in annulled branches. */
2573 gcc_assert (!final_sequence
2574 || !(INSN_ANNULLED_BRANCH_P
2575 (XVECEXP (final_sequence, 0, 0))));
2576 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2578 ASSEMBLER_DIALECT ? "/" : ".", label);
2579 fprintf (asm_out_file, "\tnop\n");
2580 output_asm_insn ("bra\t%l0", operands);
2581 fprintf (asm_out_file, "\tnop\n");
2582 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2586 /* When relaxing, fall through. */
2591 sprintf (buffer, "b%s%ss\t%%l0",
2593 ASSEMBLER_DIALECT ? "/" : ".");
2594 output_asm_insn (buffer, &operands[0]);
2599 /* There should be no longer branches now - that would
2600 indicate that something has destroyed the branches set
2601 up in machine_dependent_reorg. */
2606 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2607 fill in operands 9 as a label to the successor insn.
2608 We try to use jump threading where possible.
2609 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2610 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2611 follow jmp and bt, if the address is in range. */
2613 output_branchy_insn (enum rtx_code code, const char *templ,
2614 rtx insn, rtx *operands)
2616 rtx next_insn = NEXT_INSN (insn);
2618 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2620 rtx src = SET_SRC (PATTERN (next_insn));
2621 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2623 /* Following branch not taken */
2624 operands[9] = gen_label_rtx ();
2625 emit_label_after (operands[9], next_insn);
2626 INSN_ADDRESSES_NEW (operands[9],
2627 INSN_ADDRESSES (INSN_UID (next_insn))
2628 + get_attr_length (next_insn));
2633 int offset = (branch_dest (next_insn)
2634 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2635 if (offset >= -252 && offset <= 258)
2637 if (GET_CODE (src) == IF_THEN_ELSE)
2639 src = XEXP (src, 1);
2645 operands[9] = gen_label_rtx ();
2646 emit_label_after (operands[9], insn);
2647 INSN_ADDRESSES_NEW (operands[9],
2648 INSN_ADDRESSES (INSN_UID (insn))
2649 + get_attr_length (insn));
2654 output_ieee_ccmpeq (rtx insn, rtx *operands)
2656 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2660 /* Output the start of the assembler file. */
2663 sh_file_start (void)
2665 default_file_start ();
2668 /* We need to show the text section with the proper
2669 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2670 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2671 will complain. We can teach GAS specifically about the
2672 default attributes for our choice of text section, but
2673 then we would have to change GAS again if/when we change
2674 the text section name. */
2675 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2677 /* Switch to the data section so that the coffsem symbol
2678 isn't in the text section. */
2679 switch_to_section (data_section);
2681 if (TARGET_LITTLE_ENDIAN)
2682 fputs ("\t.little\n", asm_out_file);
2686 if (TARGET_SHCOMPACT)
2687 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2688 else if (TARGET_SHMEDIA)
2689 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2690 TARGET_SHMEDIA64 ? 64 : 32);
2694 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2697 unspec_caller_rtx_p (rtx pat)
2702 split_const (pat, &base, &offset);
2703 if (GET_CODE (base) == UNSPEC)
2705 if (XINT (base, 1) == UNSPEC_CALLER)
2707 for (i = 0; i < XVECLEN (base, 0); i++)
2708 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2714 /* Indicate that INSN cannot be duplicated. This is true for insn
2715 that generates a unique label. */
2718 sh_cannot_copy_insn_p (rtx insn)
2722 if (!reload_completed || !flag_pic)
2725 if (!NONJUMP_INSN_P (insn))
2727 if (asm_noperands (insn) >= 0)
2730 pat = PATTERN (insn);
2731 if (GET_CODE (pat) != SET)
2733 pat = SET_SRC (pat);
2735 if (unspec_caller_rtx_p (pat))
2741 /* Actual number of instructions used to make a shift by N. */
2742 static const char ashiftrt_insns[] =
2743 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2745 /* Left shift and logical right shift are the same. */
2746 static const char shift_insns[] =
2747 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2749 /* Individual shift amounts needed to get the above length sequences.
2750 One bit right shifts clobber the T bit, so when possible, put one bit
2751 shifts in the middle of the sequence, so the ends are eligible for
2752 branch delay slots. */
2753 static const short shift_amounts[32][5] = {
2754 {0}, {1}, {2}, {2, 1},
2755 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2756 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2757 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2758 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2759 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2760 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2761 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2763 /* Likewise, but for shift amounts < 16, up to three highmost bits
2764 might be clobbered. This is typically used when combined with some
2765 kind of sign or zero extension. */
2767 static const char ext_shift_insns[] =
2768 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2770 static const short ext_shift_amounts[32][4] = {
2771 {0}, {1}, {2}, {2, 1},
2772 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2773 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2774 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2775 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2776 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2777 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2778 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2780 /* Assuming we have a value that has been sign-extended by at least one bit,
2781 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2782 to shift it by N without data loss, and quicker than by other means? */
2783 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2785 /* This is used in length attributes in sh.md to help compute the length
2786 of arbitrary constant shift instructions. */
2789 shift_insns_rtx (rtx insn)
2791 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2792 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2793 enum rtx_code shift_code = GET_CODE (set_src);
2798 return ashiftrt_insns[shift_count];
2801 return shift_insns[shift_count];
2807 /* Return the cost of a shift. */
2817 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2819 if (GET_MODE (x) == DImode
2820 && CONST_INT_P (XEXP (x, 1))
2821 && INTVAL (XEXP (x, 1)) == 1)
2824 /* Everything else is invalid, because there is no pattern for it. */
2827 /* If shift by a non constant, then this will be expensive. */
2828 if (!CONST_INT_P (XEXP (x, 1)))
2829 return SH_DYNAMIC_SHIFT_COST;
2831 /* Otherwise, return the true cost in instructions. Cope with out of range
2832 shift counts more or less arbitrarily. */
2833 value = INTVAL (XEXP (x, 1)) & 31;
2835 if (GET_CODE (x) == ASHIFTRT)
2837 int cost = ashiftrt_insns[value];
2838 /* If SH3, then we put the constant in a reg and use shad. */
2839 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2840 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2844 return shift_insns[value];
2847 /* Return the cost of an AND/XOR/IOR operation. */
2850 and_xor_ior_costs (rtx x, int code)
2854 /* A logical operation with two registers is a single cycle
2856 if (!CONST_INT_P (XEXP (x, 1)))
2859 i = INTVAL (XEXP (x, 1));
2863 if (satisfies_constraint_I10 (XEXP (x, 1))
2864 || satisfies_constraint_J16 (XEXP (x, 1)))
2867 return 1 + rtx_cost (XEXP (x, 1), AND, 1, !optimize_size);
2870 /* These constants are single cycle extu.[bw] instructions. */
2871 if ((i == 0xff || i == 0xffff) && code == AND)
2873 /* Constants that can be used in an instruction as an immediate are
2874 a single cycle, but this requires r0, so make it a little more
2876 if (CONST_OK_FOR_K08 (i))
2878 /* Constants that can be loaded with a mov immediate need one more cycle.
2879 This case is probably unnecessary. */
2880 if (CONST_OK_FOR_I08 (i))
2882 /* Any other constant requires an additional 2 cycle pc-relative load.
2883 This case is probably unnecessary. */
2887 /* Return the cost of an addition or a subtraction. */
2892 /* Adding a register is a single cycle insn. */
2893 if (REG_P (XEXP (x, 1))
2894 || GET_CODE (XEXP (x, 1)) == SUBREG)
2897 /* Likewise for small constants. */
2898 if (CONST_INT_P (XEXP (x, 1))
2899 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2903 switch (GET_CODE (XEXP (x, 1)))
2908 return TARGET_SHMEDIA64 ? 5 : 3;
2911 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2913 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2915 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2923 /* Any other constant requires a 2 cycle pc-relative load plus an
2928 /* Return the cost of a multiply. */
2930 multcosts (rtx x ATTRIBUTE_UNUSED)
2932 if (sh_multcost >= 0)
2935 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2936 accept constants. Ideally, we would use a cost of one or two and
2937 add the cost of the operand, but disregard the latter when inside loops
2938 and loop invariant code motion is still to follow.
2939 Using a multiply first and splitting it later if it's a loss
2940 doesn't work because of different sign / zero extension semantics
2941 of multiplies vs. shifts. */
2942 return optimize_size ? 2 : 3;
2946 /* We have a mul insn, so we can never take more than the mul and the
2947 read of the mac reg, but count more because of the latency and extra
2954 /* If we're aiming at small code, then just count the number of
2955 insns in a multiply call sequence. */
2959 /* Otherwise count all the insns in the routine we'd be calling too. */
2963 /* Compute a (partial) cost for rtx X. Return true if the complete
2964 cost has been computed, and false if subexpressions should be
2965 scanned. In either case, *TOTAL contains the cost result. */
2968 sh_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2969 int *total, bool speed ATTRIBUTE_UNUSED)
2976 if (INTVAL (x) == 0)
2978 else if (outer_code == AND && and_operand ((x), DImode))
2980 else if ((outer_code == IOR || outer_code == XOR
2981 || outer_code == PLUS)
2982 && CONST_OK_FOR_I10 (INTVAL (x)))
2984 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2985 *total = COSTS_N_INSNS (outer_code != SET);
2986 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2987 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2988 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2989 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2991 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2994 if (CONST_OK_FOR_I08 (INTVAL (x)))
2996 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2997 && CONST_OK_FOR_K08 (INTVAL (x)))
2999 /* prepare_cmp_insn will force costly constants int registers before
3000 the cbranch[sd]i4 patterns can see them, so preserve potentially
3001 interesting ones not covered by I08 above. */
3002 else if (outer_code == COMPARE
3003 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3004 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3005 || INTVAL (x) == 0x7fffffff
3006 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3013 /* An and with a constant compared against zero is
3014 most likely going to be a TST #imm, R0 instruction.
3015 Notice that this does not catch the zero_extract variants from
3017 if (GET_CODE (XEXP (x, 0)) == AND
3018 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 0)
3029 if (TARGET_SHMEDIA64)
3030 *total = COSTS_N_INSNS (4);
3031 else if (TARGET_SHMEDIA32)
3032 *total = COSTS_N_INSNS (2);
3039 *total = COSTS_N_INSNS (4);
3040 /* prepare_cmp_insn will force costly constants int registers before
3041 the cbranchdi4 pattern can see them, so preserve potentially
3042 interesting ones. */
3043 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3049 if (x == CONST0_RTX (GET_MODE (x)))
3051 else if (sh_1el_vec (x, VOIDmode))
3052 *total = outer_code != SET;
3053 if (sh_rep_vec (x, VOIDmode))
3054 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3055 + (outer_code != SET));
3056 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3061 *total = COSTS_N_INSNS (addsubcosts (x));
3067 *total = COSTS_N_INSNS (and_xor_ior_costs (x, code));
3071 *total = COSTS_N_INSNS (multcosts (x));
3077 *total = COSTS_N_INSNS (shiftcosts (x));
3084 *total = COSTS_N_INSNS (20);
3088 if (sh_1el_vec (x, VOIDmode))
3089 *total = outer_code != SET;
3090 if (sh_rep_vec (x, VOIDmode))
3091 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3092 + (outer_code != SET));
3093 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3106 /* Compute the cost of an address. For the SH, all valid addresses are
3107 the same cost. Use a slightly higher cost for reg + reg addressing,
3108 since it increases pressure on r0. */
3111 sh_address_cost (rtx X,
3112 bool speed ATTRIBUTE_UNUSED)
3114 return (GET_CODE (X) == PLUS
3115 && ! CONSTANT_P (XEXP (X, 1))
3116 && ! TARGET_SHMEDIA ? 1 : 0);
3119 /* Code to expand a shift. */
3122 gen_ashift (int type, int n, rtx reg)
3124 /* Negative values here come from the shift_amounts array. */
3137 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3141 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3143 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3146 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3151 /* Same for HImode */
3154 gen_ashift_hi (int type, int n, rtx reg)
3156 /* Negative values here come from the shift_amounts array. */
3170 /* We don't have HImode right shift operations because using the
3171 ordinary 32 bit shift instructions for that doesn't generate proper
3172 zero/sign extension.
3173 gen_ashift_hi is only called in contexts where we know that the
3174 sign extension works out correctly. */
3177 if (GET_CODE (reg) == SUBREG)
3179 offset = SUBREG_BYTE (reg);
3180 reg = SUBREG_REG (reg);
3182 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3186 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3191 /* Output RTL to split a constant shift into its component SH constant
3192 shift instructions. */
3195 gen_shifty_op (int code, rtx *operands)
3197 int value = INTVAL (operands[2]);
3200 /* Truncate the shift count in case it is out of bounds. */
3205 if (code == LSHIFTRT)
3207 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3208 emit_insn (gen_movt (operands[0]));
3211 else if (code == ASHIFT)
3213 /* There is a two instruction sequence for 31 bit left shifts,
3214 but it requires r0. */
3215 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3217 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3218 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3223 else if (value == 0)
3225 /* This can happen even when optimizing, if there were subregs before
3226 reload. Don't output a nop here, as this is never optimized away;
3227 use a no-op move instead. */
3228 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3232 max = shift_insns[value];
3233 for (i = 0; i < max; i++)
3234 gen_ashift (code, shift_amounts[value][i], operands[0]);
3237 /* Same as above, but optimized for values where the topmost bits don't
3241 gen_shifty_hi_op (int code, rtx *operands)
3243 int value = INTVAL (operands[2]);
3245 void (*gen_fun) (int, int, rtx);
3247 /* This operation is used by and_shl for SImode values with a few
3248 high bits known to be cleared. */
3252 emit_insn (gen_nop ());
3256 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3259 max = ext_shift_insns[value];
3260 for (i = 0; i < max; i++)
3261 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3264 /* When shifting right, emit the shifts in reverse order, so that
3265 solitary negative values come first. */
3266 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3267 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3270 /* Output RTL for an arithmetic right shift. */
3272 /* ??? Rewrite to use super-optimizer sequences. */
3275 expand_ashiftrt (rtx *operands)
3281 if (TARGET_SH3 || TARGET_SH2A)
3283 if (!CONST_INT_P (operands[2]))
3285 rtx count = copy_to_mode_reg (SImode, operands[2]);
3286 emit_insn (gen_negsi2 (count, count));
3287 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3290 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3291 > 1 + SH_DYNAMIC_SHIFT_COST)
3294 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3295 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3299 if (!CONST_INT_P (operands[2]))
3302 value = INTVAL (operands[2]) & 31;
3306 /* If we are called from abs expansion, arrange things so that we
3307 we can use a single MT instruction that doesn't clobber the source,
3308 if LICM can hoist out the load of the constant zero. */
3309 if (currently_expanding_to_rtl)
3311 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3313 emit_insn (gen_mov_neg_si_t (operands[0]));
3316 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3319 else if (value >= 16 && value <= 19)
3321 wrk = gen_reg_rtx (SImode);
3322 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3325 gen_ashift (ASHIFTRT, 1, wrk);
3326 emit_move_insn (operands[0], wrk);
3329 /* Expand a short sequence inline, longer call a magic routine. */
3330 else if (value <= 5)
3332 wrk = gen_reg_rtx (SImode);
3333 emit_move_insn (wrk, operands[1]);
3335 gen_ashift (ASHIFTRT, 1, wrk);
3336 emit_move_insn (operands[0], wrk);
3340 wrk = gen_reg_rtx (Pmode);
3342 /* Load the value into an arg reg and call a helper. */
3343 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3344 sprintf (func, "__ashiftrt_r4_%d", value);
3345 function_symbol (wrk, func, SFUNC_STATIC);
3346 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3347 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3352 sh_dynamicalize_shift_p (rtx count)
3354 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3357 /* Try to find a good way to implement the combiner pattern
3358 [(set (match_operand:SI 0 "register_operand" "r")
3359 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3360 (match_operand:SI 2 "const_int_operand" "n"))
3361 (match_operand:SI 3 "const_int_operand" "n"))) .
3362 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3363 return 0 for simple right / left or left/right shift combination.
3364 return 1 for a combination of shifts with zero_extend.
3365 return 2 for a combination of shifts with an AND that needs r0.
3366 return 3 for a combination of shifts with an AND that needs an extra
3367 scratch register, when the three highmost bits of the AND mask are clear.
3368 return 4 for a combination of shifts with an AND that needs an extra
3369 scratch register, when any of the three highmost bits of the AND mask
3371 If ATTRP is set, store an initial right shift width in ATTRP[0],
3372 and the instruction length in ATTRP[1] . These values are not valid
3374 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3375 shift_amounts for the last shift value that is to be used before the
3378 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3380 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3381 int left = INTVAL (left_rtx), right;
3383 int cost, best_cost = 10000;
3384 int best_right = 0, best_len = 0;
3388 if (left < 0 || left > 31)
3390 if (CONST_INT_P (mask_rtx))
3391 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3393 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3394 /* Can this be expressed as a right shift / left shift pair? */
3395 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3396 right = exact_log2 (lsb);
3397 mask2 = ~(mask + lsb - 1);
3398 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3399 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3401 best_cost = shift_insns[right] + shift_insns[right + left];
3402 /* mask has no trailing zeroes <==> ! right */
3403 else if (! right && mask2 == ~(lsb2 - 1))
3405 int late_right = exact_log2 (lsb2);
3406 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3408 /* Try to use zero extend. */
3409 if (mask2 == ~(lsb2 - 1))
3413 for (width = 8; width <= 16; width += 8)
3415 /* Can we zero-extend right away? */
3416 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3419 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3420 if (cost < best_cost)
3431 /* ??? Could try to put zero extend into initial right shift,
3432 or even shift a bit left before the right shift. */
3433 /* Determine value of first part of left shift, to get to the
3434 zero extend cut-off point. */
3435 first = width - exact_log2 (lsb2) + right;
3436 if (first >= 0 && right + left - first >= 0)
3438 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3439 + ext_shift_insns[right + left - first];
3440 if (cost < best_cost)
3452 /* Try to use r0 AND pattern */
3453 for (i = 0; i <= 2; i++)
3457 if (! CONST_OK_FOR_K08 (mask >> i))
3459 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3460 if (cost < best_cost)
3465 best_len = cost - 1;
3468 /* Try to use a scratch register to hold the AND operand. */
3469 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3470 for (i = 0; i <= 2; i++)
3474 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3475 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3476 if (cost < best_cost)
3481 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3487 attrp[0] = best_right;
3488 attrp[1] = best_len;
3493 /* This is used in length attributes of the unnamed instructions
3494 corresponding to shl_and_kind return values of 1 and 2. */
3496 shl_and_length (rtx insn)
3498 rtx set_src, left_rtx, mask_rtx;
3501 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3502 left_rtx = XEXP (XEXP (set_src, 0), 1);
3503 mask_rtx = XEXP (set_src, 1);
3504 shl_and_kind (left_rtx, mask_rtx, attributes);
3505 return attributes[1];
3508 /* This is used in length attribute of the and_shl_scratch instruction. */
3511 shl_and_scr_length (rtx insn)
3513 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3514 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3515 rtx op = XEXP (set_src, 0);
3516 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3517 op = XEXP (XEXP (op, 0), 0);
3518 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3521 /* Generate rtl for instructions for which shl_and_kind advised a particular
3522 method of generating them, i.e. returned zero. */
3525 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3528 unsigned HOST_WIDE_INT mask;
3529 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3530 int right, total_shift;
3531 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3533 right = attributes[0];
3534 total_shift = INTVAL (left_rtx) + right;
3535 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3542 int first = attributes[2];
3547 emit_insn ((mask << right) <= 0xff
3548 ? gen_zero_extendqisi2 (dest,
3549 gen_lowpart (QImode, source))
3550 : gen_zero_extendhisi2 (dest,
3551 gen_lowpart (HImode, source)));
3555 emit_insn (gen_movsi (dest, source));
3559 operands[2] = GEN_INT (right);
3560 gen_shifty_hi_op (LSHIFTRT, operands);
3564 operands[2] = GEN_INT (first);
3565 gen_shifty_hi_op (ASHIFT, operands);
3566 total_shift -= first;
3570 emit_insn (mask <= 0xff
3571 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3572 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3573 if (total_shift > 0)
3575 operands[2] = GEN_INT (total_shift);
3576 gen_shifty_hi_op (ASHIFT, operands);
3581 shift_gen_fun = gen_shifty_op;
3583 /* If the topmost bit that matters is set, set the topmost bits
3584 that don't matter. This way, we might be able to get a shorter
3586 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3587 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3589 /* Don't expand fine-grained when combining, because that will
3590 make the pattern fail. */
3591 if (currently_expanding_to_rtl
3592 || reload_in_progress || reload_completed)
3596 /* Cases 3 and 4 should be handled by this split
3597 only while combining */
3598 gcc_assert (kind <= 2);
3601 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3604 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3609 operands[2] = GEN_INT (total_shift);
3610 shift_gen_fun (ASHIFT, operands);
3617 if (kind != 4 && total_shift < 16)
3619 neg = -ext_shift_amounts[total_shift][1];
3621 neg -= ext_shift_amounts[total_shift][2];
3625 emit_insn (gen_and_shl_scratch (dest, source,
3628 GEN_INT (total_shift + neg),
3630 emit_insn (gen_movsi (dest, dest));
3637 /* Try to find a good way to implement the combiner pattern
3638 [(set (match_operand:SI 0 "register_operand" "=r")
3639 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3640 (match_operand:SI 2 "const_int_operand" "n")
3641 (match_operand:SI 3 "const_int_operand" "n")
3643 (clobber (reg:SI T_REG))]
3644 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3645 return 0 for simple left / right shift combination.
3646 return 1 for left shift / 8 bit sign extend / left shift.
3647 return 2 for left shift / 16 bit sign extend / left shift.
3648 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3649 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3650 return 5 for left shift / 16 bit sign extend / right shift
3651 return 6 for < 8 bit sign extend / left shift.
3652 return 7 for < 8 bit sign extend / left shift / single right shift.
3653 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3656 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3658 int left, size, insize, ext;
3659 int cost = 0, best_cost;
3662 left = INTVAL (left_rtx);
3663 size = INTVAL (size_rtx);
3664 insize = size - left;
3665 gcc_assert (insize > 0);
3666 /* Default to left / right shift. */
3668 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3671 /* 16 bit shift / sign extend / 16 bit shift */
3672 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3673 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3674 below, by alternative 3 or something even better. */
3675 if (cost < best_cost)
3681 /* Try a plain sign extend between two shifts. */
3682 for (ext = 16; ext >= insize; ext -= 8)
3686 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3687 if (cost < best_cost)
3689 kind = ext / (unsigned) 8;
3693 /* Check if we can do a sloppy shift with a final signed shift
3694 restoring the sign. */
3695 if (EXT_SHIFT_SIGNED (size - ext))
3696 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3697 /* If not, maybe it's still cheaper to do the second shift sloppy,
3698 and do a final sign extend? */
3699 else if (size <= 16)
3700 cost = ext_shift_insns[ext - insize] + 1
3701 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3704 if (cost < best_cost)
3706 kind = ext / (unsigned) 8 + 2;
3710 /* Check if we can sign extend in r0 */
3713 cost = 3 + shift_insns[left];
3714 if (cost < best_cost)
3719 /* Try the same with a final signed shift. */
3722 cost = 3 + ext_shift_insns[left + 1] + 1;
3723 if (cost < best_cost)
3730 if (TARGET_SH3 || TARGET_SH2A)
3732 /* Try to use a dynamic shift. */
3733 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3734 if (cost < best_cost)
3745 /* Function to be used in the length attribute of the instructions
3746 implementing this pattern. */
3749 shl_sext_length (rtx insn)
3751 rtx set_src, left_rtx, size_rtx;
3754 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3755 left_rtx = XEXP (XEXP (set_src, 0), 1);
3756 size_rtx = XEXP (set_src, 1);
3757 shl_sext_kind (left_rtx, size_rtx, &cost);
3761 /* Generate rtl for this pattern */
3764 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3767 int left, size, insize, cost;
3770 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3771 left = INTVAL (left_rtx);
3772 size = INTVAL (size_rtx);
3773 insize = size - left;
3781 int ext = kind & 1 ? 8 : 16;
3782 int shift2 = size - ext;
3784 /* Don't expand fine-grained when combining, because that will
3785 make the pattern fail. */
3786 if (! currently_expanding_to_rtl
3787 && ! reload_in_progress && ! reload_completed)
3789 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3790 emit_insn (gen_movsi (dest, source));
3794 emit_insn (gen_movsi (dest, source));
3798 operands[2] = GEN_INT (ext - insize);
3799 gen_shifty_hi_op (ASHIFT, operands);
3802 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3803 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3808 operands[2] = GEN_INT (shift2);
3809 gen_shifty_op (ASHIFT, operands);
3816 if (EXT_SHIFT_SIGNED (shift2))
3818 operands[2] = GEN_INT (shift2 + 1);
3819 gen_shifty_op (ASHIFT, operands);
3820 operands[2] = const1_rtx;
3821 gen_shifty_op (ASHIFTRT, operands);
3824 operands[2] = GEN_INT (shift2);
3825 gen_shifty_hi_op (ASHIFT, operands);
3829 operands[2] = GEN_INT (-shift2);
3830 gen_shifty_hi_op (LSHIFTRT, operands);
3832 emit_insn (size <= 8
3833 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3834 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3841 if (! currently_expanding_to_rtl
3842 && ! reload_in_progress && ! reload_completed)
3843 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3847 operands[2] = GEN_INT (16 - insize);
3848 gen_shifty_hi_op (ASHIFT, operands);
3849 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3851 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3853 gen_ashift (ASHIFTRT, 1, dest);
3858 /* Don't expand fine-grained when combining, because that will
3859 make the pattern fail. */
3860 if (! currently_expanding_to_rtl
3861 && ! reload_in_progress && ! reload_completed)
3863 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3864 emit_insn (gen_movsi (dest, source));
3867 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3868 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3869 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3871 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3872 gen_shifty_op (ASHIFT, operands);
3874 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3882 /* Prefix a symbol_ref name with "datalabel". */
3885 gen_datalabel_ref (rtx sym)
3889 if (GET_CODE (sym) == LABEL_REF)
3890 return gen_rtx_CONST (GET_MODE (sym),
3891 gen_rtx_UNSPEC (GET_MODE (sym),
3895 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3897 str = XSTR (sym, 0);
3898 /* Share all SYMBOL_REF strings with the same value - that is important
3900 str = IDENTIFIER_POINTER (get_identifier (str));
3901 XSTR (sym, 0) = str;
3907 static alloc_pool label_ref_list_pool;
3909 typedef struct label_ref_list_d
3912 struct label_ref_list_d *next;
3913 } *label_ref_list_t;
3915 /* The SH cannot load a large constant into a register, constants have to
3916 come from a pc relative load. The reference of a pc relative load
3917 instruction must be less than 1k in front of the instruction. This
3918 means that we often have to dump a constant inside a function, and
3919 generate code to branch around it.
3921 It is important to minimize this, since the branches will slow things
3922 down and make things bigger.
3924 Worst case code looks like:
3942 We fix this by performing a scan before scheduling, which notices which
3943 instructions need to have their operands fetched from the constant table
3944 and builds the table.
3948 scan, find an instruction which needs a pcrel move. Look forward, find the
3949 last barrier which is within MAX_COUNT bytes of the requirement.
3950 If there isn't one, make one. Process all the instructions between
3951 the find and the barrier.
3953 In the above example, we can tell that L3 is within 1k of L1, so
3954 the first move can be shrunk from the 3 insn+constant sequence into
3955 just 1 insn, and the constant moved to L3 to make:
3966 Then the second move becomes the target for the shortening process. */
3970 rtx value; /* Value in table. */
3971 rtx label; /* Label of value. */
3972 label_ref_list_t wend; /* End of window. */
3973 enum machine_mode mode; /* Mode of value. */
3975 /* True if this constant is accessed as part of a post-increment
3976 sequence. Note that HImode constants are never accessed in this way. */
3977 bool part_of_sequence_p;
3980 /* The maximum number of constants that can fit into one pool, since
3981 constants in the range 0..510 are at least 2 bytes long, and in the
3982 range from there to 1018 at least 4 bytes. */
3984 #define MAX_POOL_SIZE 372
3985 static pool_node pool_vector[MAX_POOL_SIZE];
3986 static int pool_size;
3987 static rtx pool_window_label;
3988 static int pool_window_last;
3990 static int max_labelno_before_reorg;
3992 /* ??? If we need a constant in HImode which is the truncated value of a
3993 constant we need in SImode, we could combine the two entries thus saving
3994 two bytes. Is this common enough to be worth the effort of implementing
3997 /* ??? This stuff should be done at the same time that we shorten branches.
3998 As it is now, we must assume that all branches are the maximum size, and
3999 this causes us to almost always output constant pools sooner than
4002 /* Add a constant to the pool and return its label. */
4005 add_constant (rtx x, enum machine_mode mode, rtx last_value)
4009 label_ref_list_t ref, newref;
4011 /* First see if we've already got it. */
4012 for (i = 0; i < pool_size; i++)
4014 if (x->code == pool_vector[i].value->code
4015 && mode == pool_vector[i].mode)
4017 if (x->code == CODE_LABEL)
4019 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4022 if (rtx_equal_p (x, pool_vector[i].value))
4027 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4029 new_rtx = gen_label_rtx ();
4030 LABEL_REFS (new_rtx) = pool_vector[i].label;
4031 pool_vector[i].label = lab = new_rtx;
4033 if (lab && pool_window_label)
4035 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4036 newref->label = pool_window_label;
4037 ref = pool_vector[pool_window_last].wend;
4039 pool_vector[pool_window_last].wend = newref;
4042 pool_window_label = new_rtx;
4043 pool_window_last = i;
4049 /* Need a new one. */
4050 pool_vector[pool_size].value = x;
4051 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4054 pool_vector[pool_size - 1].part_of_sequence_p = true;
4057 lab = gen_label_rtx ();
4058 pool_vector[pool_size].mode = mode;
4059 pool_vector[pool_size].label = lab;
4060 pool_vector[pool_size].wend = NULL;
4061 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4062 if (lab && pool_window_label)
4064 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4065 newref->label = pool_window_label;
4066 ref = pool_vector[pool_window_last].wend;
4068 pool_vector[pool_window_last].wend = newref;
4071 pool_window_label = lab;
4072 pool_window_last = pool_size;
4077 /* Output the literal table. START, if nonzero, is the first instruction
4078 this table is needed for, and also indicates that there is at least one
4079 casesi_worker_2 instruction; We have to emit the operand3 labels from
4080 these insns at a 4-byte aligned position. BARRIER is the barrier
4081 after which we are to place the table. */
4084 dump_table (rtx start, rtx barrier)
4090 label_ref_list_t ref;
4093 /* Do two passes, first time dump out the HI sized constants. */
4095 for (i = 0; i < pool_size; i++)
4097 pool_node *p = &pool_vector[i];
4099 if (p->mode == HImode)
4103 scan = emit_insn_after (gen_align_2 (), scan);
4106 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4107 scan = emit_label_after (lab, scan);
4108 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4110 for (ref = p->wend; ref; ref = ref->next)
4113 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4116 else if (p->mode == DFmode)
4124 scan = emit_insn_after (gen_align_4 (), scan);
4126 for (; start != barrier; start = NEXT_INSN (start))
4127 if (NONJUMP_INSN_P (start)
4128 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4130 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4131 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4133 scan = emit_label_after (lab, scan);
4136 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4138 rtx align_insn = NULL_RTX;
4140 scan = emit_label_after (gen_label_rtx (), scan);
4141 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4144 for (i = 0; i < pool_size; i++)
4146 pool_node *p = &pool_vector[i];
4154 if (align_insn && !p->part_of_sequence_p)
4156 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4157 emit_label_before (lab, align_insn);
4158 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4160 for (ref = p->wend; ref; ref = ref->next)
4163 emit_insn_before (gen_consttable_window_end (lab),
4166 delete_insn (align_insn);
4167 align_insn = NULL_RTX;
4172 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4173 scan = emit_label_after (lab, scan);
4174 scan = emit_insn_after (gen_consttable_4 (p->value,
4176 need_align = ! need_align;
4182 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4187 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4188 scan = emit_label_after (lab, scan);
4189 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4196 if (p->mode != HImode)
4198 for (ref = p->wend; ref; ref = ref->next)
4201 scan = emit_insn_after (gen_consttable_window_end (lab),
4210 for (i = 0; i < pool_size; i++)
4212 pool_node *p = &pool_vector[i];
4223 scan = emit_label_after (gen_label_rtx (), scan);
4224 scan = emit_insn_after (gen_align_4 (), scan);
4226 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4227 scan = emit_label_after (lab, scan);
4228 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4236 scan = emit_label_after (gen_label_rtx (), scan);
4237 scan = emit_insn_after (gen_align_4 (), scan);
4239 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4240 scan = emit_label_after (lab, scan);
4241 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4248 if (p->mode != HImode)
4250 for (ref = p->wend; ref; ref = ref->next)
4253 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4258 scan = emit_insn_after (gen_consttable_end (), scan);
4259 scan = emit_barrier_after (scan);
4261 pool_window_label = NULL_RTX;
4262 pool_window_last = 0;
4265 /* Return nonzero if constant would be an ok source for a
4266 mov.w instead of a mov.l. */
4271 return (CONST_INT_P (src)
4272 && INTVAL (src) >= -32768
4273 && INTVAL (src) <= 32767);
4276 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4278 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4280 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4281 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4282 need to fix it if the input value is CONST_OK_FOR_I08. */
4285 broken_move (rtx insn)
4287 if (NONJUMP_INSN_P (insn))
4289 rtx pat = PATTERN (insn);
4290 if (GET_CODE (pat) == PARALLEL)
4291 pat = XVECEXP (pat, 0, 0);
4292 if (GET_CODE (pat) == SET
4293 /* We can load any 8-bit value if we don't care what the high
4294 order bits end up as. */
4295 && GET_MODE (SET_DEST (pat)) != QImode
4296 && (CONSTANT_P (SET_SRC (pat))
4297 /* Match mova_const. */
4298 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4299 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4300 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4302 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4303 && (fp_zero_operand (SET_SRC (pat))
4304 || fp_one_operand (SET_SRC (pat)))
4305 /* In general we don't know the current setting of fpscr, so disable fldi.
4306 There is an exception if this was a register-register move
4307 before reload - and hence it was ascertained that we have
4308 single precision setting - and in a post-reload optimization
4309 we changed this to do a constant load. In that case
4310 we don't have an r0 clobber, hence we must use fldi. */
4312 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4314 && REG_P (SET_DEST (pat))
4315 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4317 && GET_MODE (SET_DEST (pat)) == SImode
4318 && (satisfies_constraint_I20 (SET_SRC (pat))
4319 || satisfies_constraint_I28 (SET_SRC (pat))))
4320 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4330 return (NONJUMP_INSN_P (insn)
4331 && GET_CODE (PATTERN (insn)) == SET
4332 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4333 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4334 /* Don't match mova_const. */
4335 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4338 /* Fix up a mova from a switch that went out of range. */
4340 fixup_mova (rtx mova)
4342 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4345 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4346 INSN_CODE (mova) = -1;
4351 rtx lab = gen_label_rtx ();
4352 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4356 worker = NEXT_INSN (worker);
4358 && !LABEL_P (worker)
4359 && !JUMP_P (worker));
4360 } while (NOTE_P (worker)
4361 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4362 wpat = PATTERN (worker);
4363 wpat0 = XVECEXP (wpat, 0, 0);
4364 wpat1 = XVECEXP (wpat, 0, 1);
4365 wsrc = SET_SRC (wpat0);
4366 PATTERN (worker) = (gen_casesi_worker_2
4367 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4368 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4370 INSN_CODE (worker) = -1;
4371 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4372 base = gen_rtx_LABEL_REF (Pmode, lab);
4373 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4374 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4375 INSN_CODE (mova) = -1;
4379 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4380 *num_mova, and check if the new mova is not nested within the first one.
4381 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4382 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4384 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4386 int n_addr = 0; /* Initialization to shut up spurious warning. */
4387 int f_target, n_target = 0; /* Likewise. */
4391 /* If NEW_MOVA has no address yet, it will be handled later. */
4392 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4395 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4396 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4397 if (n_addr > n_target || n_addr + 1022 < n_target)
4399 /* Change the mova into a load.
4400 broken_move will then return true for it. */
4401 fixup_mova (new_mova);
4407 *first_mova = new_mova;
4412 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4417 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4418 > n_target - n_addr)
4420 fixup_mova (*first_mova);
4425 fixup_mova (new_mova);
4430 /* Find the last barrier from insn FROM which is close enough to hold the
4431 constant pool. If we can't find one, then create one near the end of
4435 find_barrier (int num_mova, rtx mova, rtx from)
4444 int leading_mova = num_mova;
4445 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4449 rtx last_got = NULL_RTX;
4450 rtx last_symoff = NULL_RTX;
4452 /* For HImode: range is 510, add 4 because pc counts from address of
4453 second instruction after this one, subtract 2 for the jump instruction
4454 that we may need to emit before the table, subtract 2 for the instruction
4455 that fills the jump delay slot (in very rare cases, reorg will take an
4456 instruction from after the constant pool or will leave the delay slot
4457 empty). This gives 510.
4458 For SImode: range is 1020, add 4 because pc counts from address of
4459 second instruction after this one, subtract 2 in case pc is 2 byte
4460 aligned, subtract 2 for the jump instruction that we may need to emit
4461 before the table, subtract 2 for the instruction that fills the jump
4462 delay slot. This gives 1018. */
4464 /* The branch will always be shortened now that the reference address for
4465 forward branches is the successor address, thus we need no longer make
4466 adjustments to the [sh]i_limit for -O0. */
4471 while (from && count_si < si_limit && count_hi < hi_limit)
4473 int inc = get_attr_length (from);
4476 /* If this is a label that existed at the time of the compute_alignments
4477 call, determine the alignment. N.B. When find_barrier recurses for
4478 an out-of-reach mova, we might see labels at the start of previously
4479 inserted constant tables. */
4481 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4484 new_align = 1 << label_to_alignment (from);
4485 else if (BARRIER_P (prev_nonnote_insn (from)))
4486 new_align = 1 << barrier_align (from);
4491 /* In case we are scanning a constant table because of recursion, check
4492 for explicit alignments. If the table is long, we might be forced
4493 to emit the new table in front of it; the length of the alignment
4494 might be the last straw. */
4495 else if (NONJUMP_INSN_P (from)
4496 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4497 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4498 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4499 /* When we find the end of a constant table, paste the new constant
4500 at the end. That is better than putting it in front because
4501 this way, we don't need extra alignment for adding a 4-byte-aligned
4502 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4503 else if (NONJUMP_INSN_P (from)
4504 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4505 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4508 if (BARRIER_P (from))
4512 found_barrier = from;
4514 /* If we are at the end of the function, or in front of an alignment
4515 instruction, we need not insert an extra alignment. We prefer
4516 this kind of barrier. */
4517 if (barrier_align (from) > 2)
4518 good_barrier = from;
4520 /* If we are at the end of a hot/cold block, dump the constants
4522 next = NEXT_INSN (from);
4525 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4529 if (broken_move (from))
4532 enum machine_mode mode;
4534 pat = PATTERN (from);
4535 if (GET_CODE (pat) == PARALLEL)
4536 pat = XVECEXP (pat, 0, 0);
4537 src = SET_SRC (pat);
4538 dst = SET_DEST (pat);
4539 mode = GET_MODE (dst);
4541 /* GOT pcrelat setting comes in pair of
4544 instructions. (plus add r0,r12).
4545 Remember if we see one without the other. */
4546 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4547 last_got = last_got ? NULL_RTX : from;
4548 else if (PIC_ADDR_P (src))
4549 last_got = last_got ? NULL_RTX : from;
4551 /* We must explicitly check the mode, because sometimes the
4552 front end will generate code to load unsigned constants into
4553 HImode targets without properly sign extending them. */
4555 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4558 /* We put the short constants before the long constants, so
4559 we must count the length of short constants in the range
4560 for the long constants. */
4561 /* ??? This isn't optimal, but is easy to do. */
4566 /* We dump DF/DI constants before SF/SI ones, because
4567 the limit is the same, but the alignment requirements
4568 are higher. We may waste up to 4 additional bytes
4569 for alignment, and the DF/DI constant may have
4570 another SF/SI constant placed before it. */
4571 if (TARGET_SHCOMPACT
4573 && (mode == DFmode || mode == DImode))
4578 while (si_align > 2 && found_si + si_align - 2 > count_si)
4580 if (found_si > count_si)
4581 count_si = found_si;
4582 found_si += GET_MODE_SIZE (mode);
4584 si_limit -= GET_MODE_SIZE (mode);
4590 switch (untangle_mova (&num_mova, &mova, from))
4595 rtx src = SET_SRC (PATTERN (from));
4596 if (GET_CODE (src) == CONST
4597 && GET_CODE (XEXP (src, 0)) == UNSPEC
4598 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4602 case 0: return find_barrier (0, 0, mova);
4607 = good_barrier ? good_barrier : found_barrier;
4611 if (found_si > count_si)
4612 count_si = found_si;
4614 else if (JUMP_TABLE_DATA_P (from))
4616 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4618 && (prev_nonnote_insn (from)
4619 == XEXP (MOVA_LABELREF (mova), 0))))
4621 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4623 /* We have just passed the barrier in front of the
4624 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4625 the ADDR_DIFF_VEC is accessed as data, just like our pool
4626 constants, this is a good opportunity to accommodate what
4627 we have gathered so far.
4628 If we waited any longer, we could end up at a barrier in
4629 front of code, which gives worse cache usage for separated
4630 instruction / data caches. */
4631 good_barrier = found_barrier;
4636 rtx body = PATTERN (from);
4637 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4640 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4641 else if (JUMP_P (from)
4646 /* There is a possibility that a bf is transformed into a bf/s by the
4647 delay slot scheduler. */
4648 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4649 && get_attr_type (from) == TYPE_CBRANCH
4650 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4656 if (new_align > si_align)
4658 si_limit -= (count_si - 1) & (new_align - si_align);
4659 si_align = new_align;
4661 count_si = (count_si + new_align - 1) & -new_align;
4666 if (new_align > hi_align)
4668 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4669 hi_align = new_align;
4671 count_hi = (count_hi + new_align - 1) & -new_align;
4673 from = NEXT_INSN (from);
4680 /* Try as we might, the leading mova is out of range. Change
4681 it into a load (which will become a pcload) and retry. */
4683 return find_barrier (0, 0, mova);
4687 /* Insert the constant pool table before the mova instruction,
4688 to prevent the mova label reference from going out of range. */
4690 good_barrier = found_barrier = barrier_before_mova;
4696 if (good_barrier && next_real_insn (found_barrier))
4697 found_barrier = good_barrier;
4701 /* We didn't find a barrier in time to dump our stuff,
4702 so we'll make one. */
4703 rtx label = gen_label_rtx ();
4705 /* Don't emit a constant table in the middle of insns for
4706 casesi_worker_2. This is a bit overkill but is enough
4707 because casesi_worker_2 wouldn't appear so frequently. */
4711 /* If we exceeded the range, then we must back up over the last
4712 instruction we looked at. Otherwise, we just need to undo the
4713 NEXT_INSN at the end of the loop. */
4714 if (PREV_INSN (from) != orig
4715 && (count_hi > hi_limit || count_si > si_limit))
4716 from = PREV_INSN (PREV_INSN (from));
4718 from = PREV_INSN (from);
4720 /* Don't emit a constant table int the middle of global pointer setting,
4721 since that that would move the addressing base GOT into another table.
4722 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4723 in the pool anyway, so just move up the whole constant pool. */
4725 from = PREV_INSN (last_got);
4727 /* Don't insert the constant pool table at the position which
4728 may be the landing pad. */
4731 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4732 from = PREV_INSN (from);
4734 /* Walk back to be just before any jump or label.
4735 Putting it before a label reduces the number of times the branch
4736 around the constant pool table will be hit. Putting it before
4737 a jump makes it more likely that the bra delay slot will be
4739 while (NOTE_P (from) || JUMP_P (from)
4741 from = PREV_INSN (from);
4743 /* Make sure we do not split between a call and its corresponding
4744 CALL_ARG_LOCATION note. */
4747 rtx next = NEXT_INSN (from);
4748 if (next && NOTE_P (next)
4749 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
4753 from = emit_jump_insn_after (gen_jump (label), from);
4754 JUMP_LABEL (from) = label;
4755 LABEL_NUSES (label) = 1;
4756 found_barrier = emit_barrier_after (from);
4757 emit_label_after (label, found_barrier);
4760 return found_barrier;
4763 /* If the instruction INSN is implemented by a special function, and we can
4764 positively find the register that is used to call the sfunc, and this
4765 register is not used anywhere else in this instruction - except as the
4766 destination of a set, return this register; else, return 0. */
4768 sfunc_uses_reg (rtx insn)
4771 rtx pattern, part, reg_part, reg;
4773 if (!NONJUMP_INSN_P (insn))
4775 pattern = PATTERN (insn);
4776 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4779 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4781 part = XVECEXP (pattern, 0, i);
4782 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4787 reg = XEXP (reg_part, 0);
4788 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4790 part = XVECEXP (pattern, 0, i);
4791 if (part == reg_part || GET_CODE (part) == CLOBBER)
4793 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4794 && REG_P (SET_DEST (part)))
4795 ? SET_SRC (part) : part)))
4801 /* See if the only way in which INSN uses REG is by calling it, or by
4802 setting it while calling it. Set *SET to a SET rtx if the register
4806 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4812 reg2 = sfunc_uses_reg (insn);
4813 if (reg2 && REGNO (reg2) == REGNO (reg))
4815 pattern = single_set (insn);
4817 && REG_P (SET_DEST (pattern))
4818 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4824 /* We don't use rtx_equal_p because we don't care if the mode is
4826 pattern = single_set (insn);
4828 && REG_P (SET_DEST (pattern))
4829 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4835 par = PATTERN (insn);
4836 if (GET_CODE (par) == PARALLEL)
4837 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4839 part = XVECEXP (par, 0, i);
4840 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4843 return reg_mentioned_p (reg, SET_SRC (pattern));
4849 pattern = PATTERN (insn);
4851 if (GET_CODE (pattern) == PARALLEL)
4855 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4856 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4858 pattern = XVECEXP (pattern, 0, 0);
4861 if (GET_CODE (pattern) == SET)
4863 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4865 /* We don't use rtx_equal_p, because we don't care if the
4866 mode is different. */
4867 if (!REG_P (SET_DEST (pattern))
4868 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4874 pattern = SET_SRC (pattern);
4877 if (GET_CODE (pattern) != CALL
4878 || !MEM_P (XEXP (pattern, 0))
4879 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4885 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4886 general registers. Bits 0..15 mean that the respective registers
4887 are used as inputs in the instruction. Bits 16..31 mean that the
4888 registers 0..15, respectively, are used as outputs, or are clobbered.
4889 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4891 regs_used (rtx x, int is_dest)
4899 code = GET_CODE (x);
4904 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4905 << (REGNO (x) + is_dest));
4909 rtx y = SUBREG_REG (x);
4914 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4916 subreg_regno_offset (REGNO (y),
4919 GET_MODE (x)) + is_dest));
4923 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4925 /* If there was a return value, it must have been indicated with USE. */
4940 fmt = GET_RTX_FORMAT (code);
4942 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4947 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4948 used |= regs_used (XVECEXP (x, i, j), is_dest);
4950 else if (fmt[i] == 'e')
4951 used |= regs_used (XEXP (x, i), is_dest);
4956 /* Create an instruction that prevents redirection of a conditional branch
4957 to the destination of the JUMP with address ADDR.
4958 If the branch needs to be implemented as an indirect jump, try to find
4959 a scratch register for it.
4960 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4961 If any preceding insn that doesn't fit into a delay slot is good enough,
4962 pass 1. Pass 2 if a definite blocking insn is needed.
4963 -1 is used internally to avoid deep recursion.
4964 If a blocking instruction is made or recognized, return it. */
4967 gen_block_redirect (rtx jump, int addr, int need_block)
4970 rtx prev = prev_nonnote_insn (jump);
4973 /* First, check if we already have an instruction that satisfies our need. */
4974 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4976 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4978 if (GET_CODE (PATTERN (prev)) == USE
4979 || GET_CODE (PATTERN (prev)) == CLOBBER
4980 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4982 else if ((need_block &= ~1) < 0)
4984 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4987 if (GET_CODE (PATTERN (jump)) == RETURN)
4991 /* Reorg even does nasty things with return insns that cause branches
4992 to go out of range - see find_end_label and callers. */
4993 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4995 /* We can't use JUMP_LABEL here because it might be undefined
4996 when not optimizing. */
4997 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4998 /* If the branch is out of range, try to find a scratch register for it. */
5000 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5004 /* Don't look for the stack pointer as a scratch register,
5005 it would cause trouble if an interrupt occurred. */
5006 unsigned attempt = 0x7fff, used;
5007 int jump_left = flag_expensive_optimizations + 1;
5009 /* It is likely that the most recent eligible instruction is wanted for
5010 the delay slot. Therefore, find out which registers it uses, and
5011 try to avoid using them. */
5013 for (scan = jump; (scan = PREV_INSN (scan)); )
5017 if (INSN_DELETED_P (scan))
5019 code = GET_CODE (scan);
5020 if (code == CODE_LABEL || code == JUMP_INSN)
5023 && GET_CODE (PATTERN (scan)) != USE
5024 && GET_CODE (PATTERN (scan)) != CLOBBER
5025 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5027 attempt &= ~regs_used (PATTERN (scan), 0);
5031 for (used = dead = 0, scan = JUMP_LABEL (jump);
5032 (scan = NEXT_INSN (scan)); )
5036 if (INSN_DELETED_P (scan))
5038 code = GET_CODE (scan);
5041 used |= regs_used (PATTERN (scan), 0);
5042 if (code == CALL_INSN)
5043 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5044 dead |= (used >> 16) & ~used;
5050 if (code == JUMP_INSN)
5052 if (jump_left-- && simplejump_p (scan))
5053 scan = JUMP_LABEL (scan);
5059 /* Mask out the stack pointer again, in case it was
5060 the only 'free' register we have found. */
5063 /* If the immediate destination is still in range, check for possible
5064 threading with a jump beyond the delay slot insn.
5065 Don't check if we are called recursively; the jump has been or will be
5066 checked in a different invocation then. */
5068 else if (optimize && need_block >= 0)
5070 rtx next = next_active_insn (next_active_insn (dest));
5071 if (next && JUMP_P (next)
5072 && GET_CODE (PATTERN (next)) == SET
5073 && recog_memoized (next) == CODE_FOR_jump_compact)
5075 dest = JUMP_LABEL (next);
5077 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5079 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5085 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5087 /* It would be nice if we could convert the jump into an indirect
5088 jump / far branch right now, and thus exposing all constituent
5089 instructions to further optimization. However, reorg uses
5090 simplejump_p to determine if there is an unconditional jump where
5091 it should try to schedule instructions from the target of the
5092 branch; simplejump_p fails for indirect jumps even if they have
5094 rtx insn = emit_insn_before (gen_indirect_jump_scratch
5095 (reg, GEN_INT (unspec_bbr_uid++)),
5097 /* ??? We would like this to have the scope of the jump, but that
5098 scope will change when a delay slot insn of an inner scope is added.
5099 Hence, after delay slot scheduling, we'll have to expect
5100 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5103 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
5104 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5107 else if (need_block)
5108 /* We can't use JUMP_LABEL here because it might be undefined
5109 when not optimizing. */
5110 return emit_insn_before (gen_block_branch_redirect
5111 (GEN_INT (unspec_bbr_uid++)),
5116 #define CONDJUMP_MIN -252
5117 #define CONDJUMP_MAX 262
5120 /* A label (to be placed) in front of the jump
5121 that jumps to our ultimate destination. */
5123 /* Where we are going to insert it if we cannot move the jump any farther,
5124 or the jump itself if we have picked up an existing jump. */
5126 /* The ultimate destination. */
5128 struct far_branch *prev;
5129 /* If the branch has already been created, its address;
5130 else the address of its first prospective user. */
5134 static void gen_far_branch (struct far_branch *);
5135 enum mdep_reorg_phase_e mdep_reorg_phase;
5137 gen_far_branch (struct far_branch *bp)
5139 rtx insn = bp->insert_place;
5141 rtx label = gen_label_rtx ();
5144 emit_label_after (label, insn);
5147 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5148 LABEL_NUSES (bp->far_label)++;
5151 jump = emit_jump_insn_after (gen_return (), insn);
5152 /* Emit a barrier so that reorg knows that any following instructions
5153 are not reachable via a fall-through path.
5154 But don't do this when not optimizing, since we wouldn't suppress the
5155 alignment for the barrier then, and could end up with out-of-range
5156 pc-relative loads. */
5158 emit_barrier_after (jump);
5159 emit_label_after (bp->near_label, insn);
5160 JUMP_LABEL (jump) = bp->far_label;
5161 ok = invert_jump (insn, label, 1);
5164 /* If we are branching around a jump (rather than a return), prevent
5165 reorg from using an insn from the jump target as the delay slot insn -
5166 when reorg did this, it pessimized code (we rather hide the delay slot)
5167 and it could cause branches to go out of range. */
5170 (gen_stuff_delay_slot
5171 (GEN_INT (unspec_bbr_uid++),
5172 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5174 /* Prevent reorg from undoing our splits. */
5175 gen_block_redirect (jump, bp->address += 2, 2);
5178 /* Fix up ADDR_DIFF_VECs. */
5180 fixup_addr_diff_vecs (rtx first)
5184 for (insn = first; insn; insn = NEXT_INSN (insn))
5186 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5189 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5191 pat = PATTERN (insn);
5192 vec_lab = XEXP (XEXP (pat, 0), 0);
5194 /* Search the matching casesi_jump_2. */
5195 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5199 prevpat = PATTERN (prev);
5200 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5202 x = XVECEXP (prevpat, 0, 1);
5203 if (GET_CODE (x) != USE)
5206 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5209 /* FIXME: This is a bug in the optimizer, but it seems harmless
5210 to just avoid panicing. */
5214 /* Emit the reference label of the braf where it belongs, right after
5215 the casesi_jump_2 (i.e. braf). */
5216 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5217 emit_label_after (braf_label, prev);
5219 /* Fix up the ADDR_DIF_VEC to be relative
5220 to the reference address of the braf. */
5221 XEXP (XEXP (pat, 0), 0) = braf_label;
5225 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5226 a barrier. Return the base 2 logarithm of the desired alignment. */
5228 barrier_align (rtx barrier_or_label)
5230 rtx next = next_real_insn (barrier_or_label), pat, prev;
5231 int slot, credit, jump_to_next = 0;
5236 pat = PATTERN (next);
5238 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5241 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5242 /* This is a barrier in front of a constant table. */
5245 prev = prev_real_insn (barrier_or_label);
5246 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5248 pat = PATTERN (prev);
5249 /* If this is a very small table, we want to keep the alignment after
5250 the table to the minimum for proper code alignment. */
5251 return ((optimize_size
5252 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5253 <= (unsigned) 1 << (CACHE_LOG - 2)))
5254 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5260 if (! TARGET_SH2 || ! optimize)
5261 return align_jumps_log;
5263 /* When fixing up pcloads, a constant table might be inserted just before
5264 the basic block that ends with the barrier. Thus, we can't trust the
5265 instruction lengths before that. */
5266 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5268 /* Check if there is an immediately preceding branch to the insn beyond
5269 the barrier. We must weight the cost of discarding useful information
5270 from the current cache line when executing this branch and there is
5271 an alignment, against that of fetching unneeded insn in front of the
5272 branch target when there is no alignment. */
5274 /* There are two delay_slot cases to consider. One is the simple case
5275 where the preceding branch is to the insn beyond the barrier (simple
5276 delay slot filling), and the other is where the preceding branch has
5277 a delay slot that is a duplicate of the insn after the barrier
5278 (fill_eager_delay_slots) and the branch is to the insn after the insn
5279 after the barrier. */
5281 /* PREV is presumed to be the JUMP_INSN for the barrier under
5282 investigation. Skip to the insn before it. */
5283 prev = prev_real_insn (prev);
5285 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5286 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5287 prev = prev_real_insn (prev))
5290 if (GET_CODE (PATTERN (prev)) == USE
5291 || GET_CODE (PATTERN (prev)) == CLOBBER)
5293 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5295 prev = XVECEXP (PATTERN (prev), 0, 1);
5296 if (INSN_UID (prev) == INSN_UID (next))
5298 /* Delay slot was filled with insn at jump target. */
5305 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5307 credit -= get_attr_length (prev);
5309 if (prev && jump_to_label_p (prev))
5313 || next_real_insn (JUMP_LABEL (prev)) == next
5314 /* If relax_delay_slots() decides NEXT was redundant
5315 with some previous instruction, it will have
5316 redirected PREV's jump to the following insn. */
5317 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5318 /* There is no upper bound on redundant instructions
5319 that might have been skipped, but we must not put an
5320 alignment where none had been before. */
5321 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5323 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5324 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5325 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5327 rtx pat = PATTERN (prev);
5328 if (GET_CODE (pat) == PARALLEL)
5329 pat = XVECEXP (pat, 0, 0);
5330 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5336 return align_jumps_log;
5339 /* If we are inside a phony loop, almost any kind of label can turn up as the
5340 first one in the loop. Aligning a braf label causes incorrect switch
5341 destination addresses; we can detect braf labels because they are
5342 followed by a BARRIER.
5343 Applying loop alignment to small constant or switch tables is a waste
5344 of space, so we suppress this too. */
5346 sh_loop_align (rtx label)
5351 next = next_nonnote_insn (next);
5352 while (next && LABEL_P (next));
5356 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5357 || recog_memoized (next) == CODE_FOR_consttable_2)
5360 return align_loops_log;
5363 /* Do a final pass over the function, just before delayed branch
5369 rtx first, insn, mova = NULL_RTX;
5371 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5372 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5374 first = get_insns ();
5375 max_labelno_before_reorg = max_label_num ();
5377 /* We must split call insns before introducing `mova's. If we're
5378 optimizing, they'll have already been split. Otherwise, make
5379 sure we don't split them too late. */
5381 split_all_insns_noflow ();
5386 /* If relaxing, generate pseudo-ops to associate function calls with
5387 the symbols they call. It does no harm to not generate these
5388 pseudo-ops. However, when we can generate them, it enables the
5389 linker to potentially relax the jsr to a bsr, and eliminate the
5390 register load and, possibly, the constant pool entry. */
5392 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5395 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5396 own purposes. This works because none of the remaining passes
5397 need to look at them.
5399 ??? But it may break in the future. We should use a machine
5400 dependent REG_NOTE, or some other approach entirely. */
5401 for (insn = first; insn; insn = NEXT_INSN (insn))
5407 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5409 remove_note (insn, note);
5413 for (insn = first; insn; insn = NEXT_INSN (insn))
5415 rtx pattern, reg, link, set, scan, dies, label;
5416 int rescan = 0, foundinsn = 0;
5420 pattern = PATTERN (insn);
5422 if (GET_CODE (pattern) == PARALLEL)
5423 pattern = XVECEXP (pattern, 0, 0);
5424 if (GET_CODE (pattern) == SET)
5425 pattern = SET_SRC (pattern);
5427 if (GET_CODE (pattern) != CALL
5428 || !MEM_P (XEXP (pattern, 0)))
5431 reg = XEXP (XEXP (pattern, 0), 0);
5435 reg = sfunc_uses_reg (insn);
5443 /* Try scanning backward to find where the register is set. */
5445 for (scan = PREV_INSN (insn);
5446 scan && !LABEL_P (scan);
5447 scan = PREV_INSN (scan))
5449 if (! INSN_P (scan))
5452 if (! reg_mentioned_p (reg, scan))
5455 if (noncall_uses_reg (reg, scan, &set))
5468 /* The register is set at LINK. */
5470 /* We can only optimize the function call if the register is
5471 being set to a symbol. In theory, we could sometimes
5472 optimize calls to a constant location, but the assembler
5473 and linker do not support that at present. */
5474 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5475 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5478 /* Scan forward from LINK to the place where REG dies, and
5479 make sure that the only insns which use REG are
5480 themselves function calls. */
5482 /* ??? This doesn't work for call targets that were allocated
5483 by reload, since there may not be a REG_DEAD note for the
5487 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5491 /* Don't try to trace forward past a CODE_LABEL if we haven't
5492 seen INSN yet. Ordinarily, we will only find the setting insn
5493 if it is in the same basic block. However,
5494 cross-jumping can insert code labels in between the load and
5495 the call, and can result in situations where a single call
5496 insn may have two targets depending on where we came from. */
5498 if (LABEL_P (scan) && ! foundinsn)
5501 if (! INSN_P (scan))
5504 /* Don't try to trace forward past a JUMP. To optimize
5505 safely, we would have to check that all the
5506 instructions at the jump destination did not use REG. */
5511 if (! reg_mentioned_p (reg, scan))
5514 if (noncall_uses_reg (reg, scan, &scanset))
5521 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5523 /* There is a function call to this register other
5524 than the one we are checking. If we optimize
5525 this call, we need to rescan again below. */
5529 /* ??? We shouldn't have to worry about SCANSET here.
5530 We should just be able to check for a REG_DEAD note
5531 on a function call. However, the REG_DEAD notes are
5532 apparently not dependable around libcalls; c-torture
5533 execute/920501-2 is a test case. If SCANSET is set,
5534 then this insn sets the register, so it must have
5535 died earlier. Unfortunately, this will only handle
5536 the cases in which the register is, in fact, set in a
5539 /* ??? We shouldn't have to use FOUNDINSN here.
5540 This dates back to when we used LOG_LINKS to find
5541 the most recent insn which sets the register. */
5545 || find_reg_note (scan, REG_DEAD, reg)))
5554 /* Either there was a branch, or some insn used REG
5555 other than as a function call address. */
5559 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5560 on the insn which sets the register, and on each call insn
5561 which uses the register. In final_prescan_insn we look for
5562 the REG_LABEL_OPERAND notes, and output the appropriate label
5565 label = gen_label_rtx ();
5566 add_reg_note (link, REG_LABEL_OPERAND, label);
5567 add_reg_note (insn, REG_LABEL_OPERAND, label);
5575 scan = NEXT_INSN (scan);
5578 && reg_mentioned_p (reg, scan))
5579 || ((reg2 = sfunc_uses_reg (scan))
5580 && REGNO (reg2) == REGNO (reg))))
5581 add_reg_note (scan, REG_LABEL_OPERAND, label);
5583 while (scan != dies);
5589 fixup_addr_diff_vecs (first);
5593 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5594 shorten_branches (first);
5597 /* Scan the function looking for move instructions which have to be
5598 changed to pc-relative loads and insert the literal tables. */
5599 label_ref_list_pool = create_alloc_pool ("label references list",
5600 sizeof (struct label_ref_list_d),
5602 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5603 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5607 /* ??? basic block reordering can move a switch table dispatch
5608 below the switch table. Check if that has happened.
5609 We only have the addresses available when optimizing; but then,
5610 this check shouldn't be needed when not optimizing. */
5611 if (!untangle_mova (&num_mova, &mova, insn))
5617 else if (JUMP_P (insn)
5618 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5620 /* ??? loop invariant motion can also move a mova out of a
5621 loop. Since loop does this code motion anyway, maybe we
5622 should wrap UNSPEC_MOVA into a CONST, so that reload can
5625 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5626 || (prev_nonnote_insn (insn)
5627 == XEXP (MOVA_LABELREF (mova), 0))))
5634 /* Some code might have been inserted between the mova and
5635 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5636 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5637 total += get_attr_length (scan);
5639 /* range of mova is 1020, add 4 because pc counts from address of
5640 second instruction after this one, subtract 2 in case pc is 2
5641 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5642 cancels out with alignment effects of the mova itself. */
5645 /* Change the mova into a load, and restart scanning
5646 there. broken_move will then return true for mova. */
5651 if (broken_move (insn)
5652 || (NONJUMP_INSN_P (insn)
5653 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5656 /* Scan ahead looking for a barrier to stick the constant table
5658 rtx barrier = find_barrier (num_mova, mova, insn);
5659 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5660 int need_aligned_label = 0;
5662 if (num_mova && ! mova_p (mova))
5664 /* find_barrier had to change the first mova into a
5665 pcload; thus, we have to start with this new pcload. */
5669 /* Now find all the moves between the points and modify them. */
5670 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5674 if (NONJUMP_INSN_P (scan)
5675 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5676 need_aligned_label = 1;
5677 if (broken_move (scan))
5679 rtx *patp = &PATTERN (scan), pat = *patp;
5683 enum machine_mode mode;
5685 if (GET_CODE (pat) == PARALLEL)
5686 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5687 src = SET_SRC (pat);
5688 dst = SET_DEST (pat);
5689 mode = GET_MODE (dst);
5691 if (mode == SImode && hi_const (src)
5692 && REGNO (dst) != FPUL_REG)
5697 while (GET_CODE (dst) == SUBREG)
5699 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5700 GET_MODE (SUBREG_REG (dst)),
5703 dst = SUBREG_REG (dst);
5705 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5707 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5709 /* This must be an insn that clobbers r0. */
5710 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5711 XVECLEN (PATTERN (scan), 0)
5713 rtx clobber = *clobberp;
5715 gcc_assert (GET_CODE (clobber) == CLOBBER
5716 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5719 && reg_set_between_p (r0_rtx, last_float_move, scan))
5723 && GET_MODE_SIZE (mode) != 4
5724 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5726 lab = add_constant (src, mode, last_float);
5728 emit_insn_before (gen_mova (lab), scan);
5731 /* There will be a REG_UNUSED note for r0 on
5732 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5733 lest reorg:mark_target_live_regs will not
5734 consider r0 to be used, and we end up with delay
5735 slot insn in front of SCAN that clobbers r0. */
5737 = find_regno_note (last_float_move, REG_UNUSED, 0);
5739 /* If we are not optimizing, then there may not be
5742 PUT_REG_NOTE_KIND (note, REG_INC);
5744 *last_float_addr = r0_inc_rtx;
5746 last_float_move = scan;
5748 newsrc = gen_const_mem (mode,
5749 (((TARGET_SH4 && ! TARGET_FMOVD)
5750 || REGNO (dst) == FPUL_REG)
5753 last_float_addr = &XEXP (newsrc, 0);
5755 /* Remove the clobber of r0. */
5756 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5757 gen_rtx_SCRATCH (Pmode));
5759 /* This is a mova needing a label. Create it. */
5760 else if (GET_CODE (src) == UNSPEC
5761 && XINT (src, 1) == UNSPEC_MOVA
5762 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5764 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5765 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5766 newsrc = gen_rtx_UNSPEC (SImode,
5767 gen_rtvec (1, newsrc),
5772 lab = add_constant (src, mode, 0);
5773 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5774 newsrc = gen_const_mem (mode, newsrc);
5776 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5777 INSN_CODE (scan) = -1;
5780 dump_table (need_aligned_label ? insn : 0, barrier);
5784 free_alloc_pool (label_ref_list_pool);
5785 for (insn = first; insn; insn = NEXT_INSN (insn))
5786 PUT_MODE (insn, VOIDmode);
5788 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5789 INSN_ADDRESSES_FREE ();
5790 split_branches (first);
5792 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5793 also has an effect on the register that holds the address of the sfunc.
5794 Insert an extra dummy insn in front of each sfunc that pretends to
5795 use this register. */
5796 if (flag_delayed_branch)
5798 for (insn = first; insn; insn = NEXT_INSN (insn))
5800 rtx reg = sfunc_uses_reg (insn);
5804 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5808 /* fpscr is not actually a user variable, but we pretend it is for the
5809 sake of the previous optimization passes, since we want it handled like
5810 one. However, we don't have any debugging information for it, so turn
5811 it into a non-user variable now. */
5813 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5815 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5819 get_dest_uid (rtx label, int max_uid)
5821 rtx dest = next_real_insn (label);
5824 /* This can happen for an undefined label. */
5826 dest_uid = INSN_UID (dest);
5827 /* If this is a newly created branch redirection blocking instruction,
5828 we cannot index the branch_uid or insn_addresses arrays with its
5829 uid. But then, we won't need to, because the actual destination is
5830 the following branch. */
5831 while (dest_uid >= max_uid)
5833 dest = NEXT_INSN (dest);
5834 dest_uid = INSN_UID (dest);
5836 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5841 /* Split condbranches that are out of range. Also add clobbers for
5842 scratch registers that are needed in far jumps.
5843 We do this before delay slot scheduling, so that it can take our
5844 newly created instructions into account. It also allows us to
5845 find branches with common targets more easily. */
5848 split_branches (rtx first)
5851 struct far_branch **uid_branch, *far_branch_list = 0;
5852 int max_uid = get_max_uid ();
5855 /* Find out which branches are out of range. */
5856 shorten_branches (first);
5858 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5859 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5861 for (insn = first; insn; insn = NEXT_INSN (insn))
5862 if (! INSN_P (insn))
5864 else if (INSN_DELETED_P (insn))
5866 /* Shorten_branches would split this instruction again,
5867 so transform it into a note. */
5868 SET_INSN_DELETED (insn);
5870 else if (JUMP_P (insn)
5871 /* Don't mess with ADDR_DIFF_VEC */
5872 && (GET_CODE (PATTERN (insn)) == SET
5873 || GET_CODE (PATTERN (insn)) == RETURN))
5875 enum attr_type type = get_attr_type (insn);
5876 if (type == TYPE_CBRANCH)
5880 if (get_attr_length (insn) > 4)
5882 rtx src = SET_SRC (PATTERN (insn));
5883 rtx olabel = XEXP (XEXP (src, 1), 0);
5884 int addr = INSN_ADDRESSES (INSN_UID (insn));
5886 int dest_uid = get_dest_uid (olabel, max_uid);
5887 struct far_branch *bp = uid_branch[dest_uid];
5889 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5890 the label if the LABEL_NUSES count drops to zero. There is
5891 always a jump_optimize pass that sets these values, but it
5892 proceeds to delete unreferenced code, and then if not
5893 optimizing, to un-delete the deleted instructions, thus
5894 leaving labels with too low uses counts. */
5897 JUMP_LABEL (insn) = olabel;
5898 LABEL_NUSES (olabel)++;
5902 bp = (struct far_branch *) alloca (sizeof *bp);
5903 uid_branch[dest_uid] = bp;
5904 bp->prev = far_branch_list;
5905 far_branch_list = bp;
5907 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5908 LABEL_NUSES (bp->far_label)++;
5912 label = bp->near_label;
5913 if (! label && bp->address - addr >= CONDJUMP_MIN)
5915 rtx block = bp->insert_place;
5917 if (GET_CODE (PATTERN (block)) == RETURN)
5918 block = PREV_INSN (block);
5920 block = gen_block_redirect (block,
5922 label = emit_label_after (gen_label_rtx (),
5924 bp->near_label = label;
5926 else if (label && ! NEXT_INSN (label))
5928 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5929 bp->insert_place = insn;
5931 gen_far_branch (bp);
5935 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5937 bp->near_label = label = gen_label_rtx ();
5938 bp->insert_place = insn;
5941 ok = redirect_jump (insn, label, 0);
5946 /* get_attr_length (insn) == 2 */
5947 /* Check if we have a pattern where reorg wants to redirect
5948 the branch to a label from an unconditional branch that
5950 /* We can't use JUMP_LABEL here because it might be undefined
5951 when not optimizing. */
5952 /* A syntax error might cause beyond to be NULL_RTX. */
5954 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5959 || ((beyond = next_active_insn (beyond))
5960 && JUMP_P (beyond)))
5961 && GET_CODE (PATTERN (beyond)) == SET
5962 && recog_memoized (beyond) == CODE_FOR_jump_compact
5964 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5965 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5967 gen_block_redirect (beyond,
5968 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5971 next = next_active_insn (insn);
5975 || ((next = next_active_insn (next))
5977 && GET_CODE (PATTERN (next)) == SET
5978 && recog_memoized (next) == CODE_FOR_jump_compact
5980 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5981 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5983 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5985 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5987 int addr = INSN_ADDRESSES (INSN_UID (insn));
5990 struct far_branch *bp;
5992 if (type == TYPE_JUMP)
5994 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5995 dest_uid = get_dest_uid (far_label, max_uid);
5998 /* Parse errors can lead to labels outside
6000 if (! NEXT_INSN (far_label))
6005 JUMP_LABEL (insn) = far_label;
6006 LABEL_NUSES (far_label)++;
6008 redirect_jump (insn, ret_rtx, 1);
6012 bp = uid_branch[dest_uid];
6015 bp = (struct far_branch *) alloca (sizeof *bp);
6016 uid_branch[dest_uid] = bp;
6017 bp->prev = far_branch_list;
6018 far_branch_list = bp;
6020 bp->far_label = far_label;
6022 LABEL_NUSES (far_label)++;
6024 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6025 if (addr - bp->address <= CONDJUMP_MAX)
6026 emit_label_after (bp->near_label, PREV_INSN (insn));
6029 gen_far_branch (bp);
6035 bp->insert_place = insn;
6037 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6039 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6042 /* Generate all pending far branches,
6043 and free our references to the far labels. */
6044 while (far_branch_list)
6046 if (far_branch_list->near_label
6047 && ! NEXT_INSN (far_branch_list->near_label))
6048 gen_far_branch (far_branch_list);
6050 && far_branch_list->far_label
6051 && ! --LABEL_NUSES (far_branch_list->far_label))
6052 delete_insn (far_branch_list->far_label);
6053 far_branch_list = far_branch_list->prev;
6056 /* Instruction length information is no longer valid due to the new
6057 instructions that have been generated. */
6058 init_insn_lengths ();
6061 /* Dump out instruction addresses, which is useful for debugging the
6062 constant pool table stuff.
6064 If relaxing, output the label and pseudo-ops used to link together
6065 calls and the instruction which set the registers. */
6067 /* ??? The addresses printed by this routine for insns are nonsense for
6068 insns which are inside of a sequence where none of the inner insns have
6069 variable length. This is because the second pass of shorten_branches
6070 does not bother to update them. */
6073 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6074 int noperands ATTRIBUTE_UNUSED)
6076 if (TARGET_DUMPISIZE)
6077 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6083 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
6088 pattern = PATTERN (insn);
6089 if (GET_CODE (pattern) == PARALLEL)
6090 pattern = XVECEXP (pattern, 0, 0);
6091 switch (GET_CODE (pattern))
6094 if (GET_CODE (SET_SRC (pattern)) != CALL
6095 && get_attr_type (insn) != TYPE_SFUNC)
6097 targetm.asm_out.internal_label
6098 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6101 /* else FALLTHROUGH */
6103 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6104 CODE_LABEL_NUMBER (XEXP (note, 0)));
6114 /* Dump out any constants accumulated in the final pass. These will
6118 output_jump_label_table (void)
6124 fprintf (asm_out_file, "\t.align 2\n");
6125 for (i = 0; i < pool_size; i++)
6127 pool_node *p = &pool_vector[i];
6129 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6130 CODE_LABEL_NUMBER (p->label));
6131 output_asm_insn (".long %O0", &p->value);
6139 /* A full frame looks like:
6143 [ if current_function_anonymous_args
6156 local-0 <- fp points here. */
6158 /* Number of bytes pushed for anonymous args, used to pass information
6159 between expand_prologue and expand_epilogue. */
6161 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6162 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6163 for an epilogue and a negative value means that it's for a sibcall
6164 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6165 all the registers that are about to be restored, and hence dead. */
6168 output_stack_adjust (int size, rtx reg, int epilogue_p,
6169 HARD_REG_SET *live_regs_mask, bool frame_p)
6171 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6174 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6176 /* This test is bogus, as output_stack_adjust is used to re-align the
6179 gcc_assert (!(size % align));
6182 if (CONST_OK_FOR_ADD (size))
6183 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6184 /* Try to do it with two partial adjustments; however, we must make
6185 sure that the stack is properly aligned at all times, in case
6186 an interrupt occurs between the two partial adjustments. */
6187 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6188 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6190 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6191 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6197 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6200 /* If TEMP is invalid, we could temporarily save a general
6201 register to MACL. However, there is currently no need
6202 to handle this case, so just die when we see it. */
6204 || current_function_interrupt
6205 || ! call_really_used_regs[temp] || fixed_regs[temp])
6207 if (temp < 0 && ! current_function_interrupt
6208 && (TARGET_SHMEDIA || epilogue_p >= 0))
6211 COPY_HARD_REG_SET (temps, call_used_reg_set);
6212 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6216 if (crtl->return_rtx)
6218 enum machine_mode mode;
6219 mode = GET_MODE (crtl->return_rtx);
6220 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6221 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6223 for (i = 0; i < nreg; i++)
6224 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6225 if (crtl->calls_eh_return)
6227 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6228 for (i = 0; i <= 3; i++)
6229 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6232 if (TARGET_SHMEDIA && epilogue_p < 0)
6233 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6234 CLEAR_HARD_REG_BIT (temps, i);
6235 if (epilogue_p <= 0)
6237 for (i = FIRST_PARM_REG;
6238 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6239 CLEAR_HARD_REG_BIT (temps, i);
6240 if (cfun->static_chain_decl != NULL)
6241 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6243 temp = scavenge_reg (&temps);
6245 if (temp < 0 && live_regs_mask)
6249 COPY_HARD_REG_SET (temps, *live_regs_mask);
6250 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6251 temp = scavenge_reg (&temps);
6255 rtx adj_reg, tmp_reg, mem;
6257 /* If we reached here, the most likely case is the (sibcall)
6258 epilogue for non SHmedia. Put a special push/pop sequence
6259 for such case as the last resort. This looks lengthy but
6260 would not be problem because it seems to be very
6263 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6266 /* ??? There is still the slight possibility that r4 or
6267 r5 have been reserved as fixed registers or assigned
6268 as global registers, and they change during an
6269 interrupt. There are possible ways to handle this:
6271 - If we are adjusting the frame pointer (r14), we can do
6272 with a single temp register and an ordinary push / pop
6274 - Grab any call-used or call-saved registers (i.e. not
6275 fixed or globals) for the temps we need. We might
6276 also grab r14 if we are adjusting the stack pointer.
6277 If we can't find enough available registers, issue
6278 a diagnostic and die - the user must have reserved
6279 way too many registers.
6280 But since all this is rather unlikely to happen and
6281 would require extra testing, we just die if r4 / r5
6282 are not available. */
6283 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6284 && !global_regs[4] && !global_regs[5]);
6286 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6287 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6288 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6289 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6290 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6291 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6292 emit_move_insn (mem, tmp_reg);
6293 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6294 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6295 emit_move_insn (mem, tmp_reg);
6296 emit_move_insn (reg, adj_reg);
6297 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6298 emit_move_insn (adj_reg, mem);
6299 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6300 emit_move_insn (tmp_reg, mem);
6301 /* Tell flow the insns that pop r4/r5 aren't dead. */
6306 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6308 /* If SIZE is negative, subtract the positive value.
6309 This sometimes allows a constant pool entry to be shared
6310 between prologue and epilogue code. */
6313 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6314 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6318 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6319 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6322 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6323 gen_rtx_SET (VOIDmode, reg,
6324 gen_rtx_PLUS (SImode, reg,
6334 RTX_FRAME_RELATED_P (x) = 1;
6338 /* Output RTL to push register RN onto the stack. */
6345 x = gen_push_fpul ();
6346 else if (rn == FPSCR_REG)
6347 x = gen_push_fpscr ();
6348 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6349 && FP_OR_XD_REGISTER_P (rn))
6351 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6353 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6355 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6356 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6358 x = gen_push (gen_rtx_REG (SImode, rn));
6361 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6365 /* Output RTL to pop register RN from the stack. */
6372 x = gen_pop_fpul ();
6373 else if (rn == FPSCR_REG)
6374 x = gen_pop_fpscr ();
6375 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6376 && FP_OR_XD_REGISTER_P (rn))
6378 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6380 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6382 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6383 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6385 x = gen_pop (gen_rtx_REG (SImode, rn));
6388 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6391 /* Generate code to push the regs specified in the mask. */
6394 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6396 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6399 /* Push PR last; this gives better latencies after the prologue, and
6400 candidates for the return delay slot when there are no general
6401 registers pushed. */
6402 for (; i < FIRST_PSEUDO_REGISTER; i++)
6404 /* If this is an interrupt handler, and the SZ bit varies,
6405 and we have to push any floating point register, we need
6406 to switch to the correct precision first. */
6407 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6408 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6410 HARD_REG_SET unsaved;
6413 COMPL_HARD_REG_SET (unsaved, *mask);
6414 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6418 && (i != FPSCR_REG || ! skip_fpscr)
6419 && TEST_HARD_REG_BIT (*mask, i))
6421 /* If the ISR has RESBANK attribute assigned, don't push any of
6422 the following registers - R0-R14, MACH, MACL and GBR. */
6423 if (! (sh_cfun_resbank_handler_p ()
6424 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6432 /* Push banked registers last to improve delay slot opportunities. */
6433 if (interrupt_handler)
6435 bool use_movml = false;
6439 unsigned int count = 0;
6441 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6442 if (TEST_HARD_REG_BIT (*mask, i))
6447 /* Use movml when all banked registers are pushed. */
6448 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6454 rtx x, mem, reg, set;
6455 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6457 /* We must avoid scheduling multiple store insn with another
6459 emit_insn (gen_blockage ());
6460 x = gen_movml_push_banked (sp_reg);
6462 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6464 mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4));
6465 reg = gen_rtx_REG (SImode, i);
6466 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg));
6469 set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32));
6470 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6471 emit_insn (gen_blockage ());
6474 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6475 if (TEST_HARD_REG_BIT (*mask, i))
6479 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6480 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6484 /* Calculate how much extra space is needed to save all callee-saved
6486 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6489 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6492 int stack_space = 0;
6493 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6495 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6496 if ((! call_really_used_regs[reg] || interrupt_handler)
6497 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6498 /* Leave space to save this target register on the stack,
6499 in case target register allocation wants to use it. */
6500 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6504 /* Decide whether we should reserve space for callee-save target registers,
6505 in case target register allocation wants to use them. REGS_SAVED is
6506 the space, in bytes, that is already required for register saves.
6507 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6510 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6511 HARD_REG_SET *live_regs_mask)
6515 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6518 /* Decide how much space to reserve for callee-save target registers
6519 in case target register allocation wants to use them.
6520 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6523 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6525 if (shmedia_space_reserved_for_target_registers)
6526 return shmedia_target_regs_stack_space (live_regs_mask);
6531 /* Work out the registers which need to be saved, both as a mask and a
6532 count of saved words. Return the count.
6534 If doing a pragma interrupt function, then push all regs used by the
6535 function, and if we call another function (we can tell by looking at PR),
6536 make sure that all the regs it clobbers are safe too. */
6539 calc_live_regs (HARD_REG_SET *live_regs_mask)
6544 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6545 bool nosave_low_regs;
6546 int pr_live, has_call;
6548 attrs = DECL_ATTRIBUTES (current_function_decl);
6549 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6550 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6551 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6552 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6554 CLEAR_HARD_REG_SET (*live_regs_mask);
6555 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6556 && df_regs_ever_live_p (FPSCR_REG))
6557 target_flags &= ~MASK_FPU_SINGLE;
6558 /* If we can save a lot of saves by switching to double mode, do that. */
6559 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6560 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6561 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6562 && (! call_really_used_regs[reg]
6563 || interrupt_handler)
6566 target_flags &= ~MASK_FPU_SINGLE;
6569 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6570 knows how to use it. That means the pseudo originally allocated for
6571 the initial value can become the PR_MEDIA_REG hard register, as seen for
6572 execute/20010122-1.c:test9. */
6574 /* ??? this function is called from initial_elimination_offset, hence we
6575 can't use the result of sh_media_register_for_return here. */
6576 pr_live = sh_pr_n_sets ();
6579 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6580 pr_live = (pr_initial
6581 ? (!REG_P (pr_initial)
6582 || REGNO (pr_initial) != (PR_REG))
6583 : df_regs_ever_live_p (PR_REG));
6584 /* For Shcompact, if not optimizing, we end up with a memory reference
6585 using the return address pointer for __builtin_return_address even
6586 though there is no actual need to put the PR register on the stack. */
6587 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6589 /* Force PR to be live if the prologue has to call the SHmedia
6590 argument decoder or register saver. */
6591 if (TARGET_SHCOMPACT
6592 && ((crtl->args.info.call_cookie
6593 & ~ CALL_COOKIE_RET_TRAMP (1))
6594 || crtl->saves_all_registers))
6596 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6597 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6599 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6602 ? (/* Need to save all the regs ever live. */
6603 (df_regs_ever_live_p (reg)
6604 || (call_really_used_regs[reg]
6605 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6606 || reg == PIC_OFFSET_TABLE_REGNUM)
6608 || (TARGET_SHMEDIA && has_call
6609 && REGISTER_NATURAL_MODE (reg) == SImode
6610 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6611 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6612 && reg != RETURN_ADDRESS_POINTER_REGNUM
6613 && reg != T_REG && reg != GBR_REG
6614 /* Push fpscr only on targets which have FPU */
6615 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6616 : (/* Only push those regs which are used and need to be saved. */
6619 && crtl->args.info.call_cookie
6620 && reg == PIC_OFFSET_TABLE_REGNUM)
6621 || (df_regs_ever_live_p (reg)
6622 && ((!call_really_used_regs[reg]
6623 && !(reg != PIC_OFFSET_TABLE_REGNUM
6624 && fixed_regs[reg] && call_used_regs[reg]))
6625 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6626 || (crtl->calls_eh_return
6627 && (reg == EH_RETURN_DATA_REGNO (0)
6628 || reg == EH_RETURN_DATA_REGNO (1)
6629 || reg == EH_RETURN_DATA_REGNO (2)
6630 || reg == EH_RETURN_DATA_REGNO (3)))
6631 || ((reg == MACL_REG || reg == MACH_REG)
6632 && df_regs_ever_live_p (reg)
6633 && sh_cfun_attr_renesas_p ())
6636 SET_HARD_REG_BIT (*live_regs_mask, reg);
6637 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6639 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6640 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6642 if (FP_REGISTER_P (reg))
6644 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6646 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6647 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6650 else if (XD_REGISTER_P (reg))
6652 /* Must switch to double mode to access these registers. */
6653 target_flags &= ~MASK_FPU_SINGLE;
6657 if (nosave_low_regs && reg == R8_REG)
6660 /* If we have a target register optimization pass after prologue / epilogue
6661 threading, we need to assume all target registers will be live even if
6663 if (flag_branch_target_load_optimize2
6664 && TARGET_SAVE_ALL_TARGET_REGS
6665 && shmedia_space_reserved_for_target_registers)
6666 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6667 if ((! call_really_used_regs[reg] || interrupt_handler)
6668 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6670 SET_HARD_REG_BIT (*live_regs_mask, reg);
6671 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6673 /* If this is an interrupt handler, we don't have any call-clobbered
6674 registers we can conveniently use for target register save/restore.
6675 Make sure we save at least one general purpose register when we need
6676 to save target registers. */
6677 if (interrupt_handler
6678 && hard_reg_set_intersect_p (*live_regs_mask,
6679 reg_class_contents[TARGET_REGS])
6680 && ! hard_reg_set_intersect_p (*live_regs_mask,
6681 reg_class_contents[GENERAL_REGS]))
6683 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6684 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6690 /* Code to generate prologue and epilogue sequences */
6692 /* PUSHED is the number of bytes that are being pushed on the
6693 stack for register saves. Return the frame size, padded
6694 appropriately so that the stack stays properly aligned. */
6695 static HOST_WIDE_INT
6696 rounded_frame_size (int pushed)
6698 HOST_WIDE_INT size = get_frame_size ();
6699 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6701 if (ACCUMULATE_OUTGOING_ARGS)
6702 size += crtl->outgoing_args_size;
6704 return ((size + pushed + align - 1) & -align) - pushed;
6707 /* Choose a call-clobbered target-branch register that remains
6708 unchanged along the whole function. We set it up as the return
6709 value in the prologue. */
6711 sh_media_register_for_return (void)
6716 if (! current_function_is_leaf)
6718 if (lookup_attribute ("interrupt_handler",
6719 DECL_ATTRIBUTES (current_function_decl)))
6721 if (sh_cfun_interrupt_handler_p ())
6724 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6726 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6727 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6733 /* The maximum registers we need to save are:
6734 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6735 - 32 floating point registers (for each pair, we save none,
6736 one single precision value, or a double precision value).
6737 - 8 target registers
6738 - add 1 entry for a delimiter. */
6739 #define MAX_SAVED_REGS (62+32+8)
6741 typedef struct save_entry_s
6750 /* There will be a delimiter entry with VOIDmode both at the start and the
6751 end of a filled in schedule. The end delimiter has the offset of the
6752 save with the smallest (i.e. most negative) offset. */
6753 typedef struct save_schedule_s
6755 save_entry entries[MAX_SAVED_REGS + 2];
6756 int temps[MAX_TEMPS+1];
6759 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6760 use reverse order. Returns the last entry written to (not counting
6761 the delimiter). OFFSET_BASE is a number to be added to all offset
6765 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6769 save_entry *entry = schedule->entries;
6773 if (! current_function_interrupt)
6774 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6775 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6776 && ! FUNCTION_ARG_REGNO_P (i)
6777 && i != FIRST_RET_REG
6778 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6779 && ! (crtl->calls_eh_return
6780 && (i == EH_RETURN_STACKADJ_REGNO
6781 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6782 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6783 schedule->temps[tmpx++] = i;
6785 entry->mode = VOIDmode;
6786 entry->offset = offset_base;
6788 /* We loop twice: first, we save 8-byte aligned registers in the
6789 higher addresses, that are known to be aligned. Then, we
6790 proceed to saving 32-bit registers that don't need 8-byte
6792 If this is an interrupt function, all registers that need saving
6793 need to be saved in full. moreover, we need to postpone saving
6794 target registers till we have saved some general purpose registers
6795 we can then use as scratch registers. */
6796 offset = offset_base;
6797 for (align = 1; align >= 0; align--)
6799 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6800 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6802 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6805 if (current_function_interrupt)
6807 if (TARGET_REGISTER_P (i))
6809 if (GENERAL_REGISTER_P (i))
6812 if (mode == SFmode && (i % 2) == 1
6813 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6814 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6821 /* If we're doing the aligned pass and this is not aligned,
6822 or we're doing the unaligned pass and this is aligned,
6824 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6828 if (current_function_interrupt
6829 && GENERAL_REGISTER_P (i)
6830 && tmpx < MAX_TEMPS)
6831 schedule->temps[tmpx++] = i;
6833 offset -= GET_MODE_SIZE (mode);
6836 entry->offset = offset;
6839 if (align && current_function_interrupt)
6840 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6841 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6843 offset -= GET_MODE_SIZE (DImode);
6845 entry->mode = DImode;
6846 entry->offset = offset;
6851 entry->mode = VOIDmode;
6852 entry->offset = offset;
6853 schedule->temps[tmpx] = -1;
6858 sh_expand_prologue (void)
6860 HARD_REG_SET live_regs_mask;
6863 int save_flags = target_flags;
6867 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6869 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6871 /* We have pretend args if we had an object sent partially in registers
6872 and partially on the stack, e.g. a large structure. */
6873 pretend_args = crtl->args.pretend_args_size;
6874 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6875 && (NPARM_REGS(SImode)
6876 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6879 output_stack_adjust (-pretend_args
6880 - crtl->args.info.stack_regs * 8,
6881 stack_pointer_rtx, 0, NULL, true);
6882 stack_usage = pretend_args + crtl->args.info.stack_regs * 8;
6884 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6885 /* We're going to use the PIC register to load the address of the
6886 incoming-argument decoder and/or of the return trampoline from
6887 the GOT, so make sure the PIC register is preserved and
6889 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6891 if (TARGET_SHCOMPACT
6892 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6896 /* First, make all registers with incoming arguments that will
6897 be pushed onto the stack live, so that register renaming
6898 doesn't overwrite them. */
6899 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6900 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6901 >= NPARM_REGS (SImode) - reg)
6902 for (; reg < NPARM_REGS (SImode); reg++)
6903 emit_insn (gen_shcompact_preserve_incoming_args
6904 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6905 else if (CALL_COOKIE_INT_REG_GET
6906 (crtl->args.info.call_cookie, reg) == 1)
6907 emit_insn (gen_shcompact_preserve_incoming_args
6908 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6910 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6912 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6913 GEN_INT (crtl->args.info.call_cookie));
6914 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6915 gen_rtx_REG (SImode, R0_REG));
6917 else if (TARGET_SHMEDIA)
6919 int tr = sh_media_register_for_return ();
6922 emit_move_insn (gen_rtx_REG (DImode, tr),
6923 gen_rtx_REG (DImode, PR_MEDIA_REG));
6926 /* Emit the code for SETUP_VARARGS. */
6929 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6931 /* Push arg regs as if they'd been provided by caller in stack. */
6932 for (i = 0; i < NPARM_REGS(SImode); i++)
6934 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6936 if (i >= (NPARM_REGS(SImode)
6937 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6941 stack_usage += GET_MODE_SIZE (SImode);
6946 /* If we're supposed to switch stacks at function entry, do so now. */
6950 /* The argument specifies a variable holding the address of the
6951 stack the interrupt function should switch to/from at entry/exit. */
6952 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6954 = ggc_strdup (TREE_STRING_POINTER (arg));
6955 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6957 lab = add_constant (sp_switch, SImode, 0);
6958 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6959 newsrc = gen_const_mem (SImode, newsrc);
6961 emit_insn (gen_sp_switch_1 (newsrc));
6964 d = calc_live_regs (&live_regs_mask);
6965 /* ??? Maybe we could save some switching if we can move a mode switch
6966 that already happens to be at the function start into the prologue. */
6967 if (target_flags != save_flags && ! current_function_interrupt)
6968 emit_insn (gen_toggle_sz ());
6972 int offset_base, offset;
6974 int offset_in_r0 = -1;
6976 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6977 int total_size, save_size;
6978 save_schedule schedule;
6982 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6983 && ! current_function_interrupt)
6984 r0 = gen_rtx_REG (Pmode, R0_REG);
6986 /* D is the actual number of bytes that we need for saving registers,
6987 however, in initial_elimination_offset we have committed to using
6988 an additional TREGS_SPACE amount of bytes - in order to keep both
6989 addresses to arguments supplied by the caller and local variables
6990 valid, we must keep this gap. Place it between the incoming
6991 arguments and the actually saved registers in a bid to optimize
6992 locality of reference. */
6993 total_size = d + tregs_space;
6994 total_size += rounded_frame_size (total_size);
6995 save_size = total_size - rounded_frame_size (d);
6996 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6997 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6998 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
7000 /* If adjusting the stack in a single step costs nothing extra, do so.
7001 I.e. either if a single addi is enough, or we need a movi anyway,
7002 and we don't exceed the maximum offset range (the test for the
7003 latter is conservative for simplicity). */
7005 && (CONST_OK_FOR_I10 (-total_size)
7006 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
7007 && total_size <= 2044)))
7008 d_rounding = total_size - save_size;
7010 offset_base = d + d_rounding;
7012 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
7014 stack_usage += save_size + d_rounding;
7016 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
7017 tmp_pnt = schedule.temps;
7018 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
7020 enum machine_mode mode = (enum machine_mode) entry->mode;
7021 unsigned int reg = entry->reg;
7022 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
7025 offset = entry->offset;
7027 reg_rtx = gen_rtx_REG (mode, reg);
7029 mem_rtx = gen_frame_mem (mode,
7030 gen_rtx_PLUS (Pmode,
7034 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7040 if (HAVE_PRE_DECREMENT
7041 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
7042 || mem_rtx == NULL_RTX
7043 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7045 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
7047 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
7052 offset += GET_MODE_SIZE (mode);
7056 if (mem_rtx != NULL_RTX)
7059 if (offset_in_r0 == -1)
7061 emit_move_insn (r0, GEN_INT (offset));
7062 offset_in_r0 = offset;
7064 else if (offset != offset_in_r0)
7069 GEN_INT (offset - offset_in_r0)));
7070 offset_in_r0 += offset - offset_in_r0;
7073 if (pre_dec != NULL_RTX)
7079 (Pmode, r0, stack_pointer_rtx));
7083 offset -= GET_MODE_SIZE (mode);
7084 offset_in_r0 -= GET_MODE_SIZE (mode);
7089 mem_rtx = gen_frame_mem (mode, r0);
7091 mem_rtx = gen_frame_mem (mode,
7092 gen_rtx_PLUS (Pmode,
7096 /* We must not use an r0-based address for target-branch
7097 registers or for special registers without pre-dec
7098 memory addresses, since we store their values in r0
7100 gcc_assert (!TARGET_REGISTER_P (reg)
7101 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7102 || mem_rtx == pre_dec));
7105 orig_reg_rtx = reg_rtx;
7106 if (TARGET_REGISTER_P (reg)
7107 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7108 && mem_rtx != pre_dec))
7110 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
7112 emit_move_insn (tmp_reg, reg_rtx);
7114 if (REGNO (tmp_reg) == R0_REG)
7118 gcc_assert (!refers_to_regno_p
7119 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
7122 if (*++tmp_pnt <= 0)
7123 tmp_pnt = schedule.temps;
7130 /* Mark as interesting for dwarf cfi generator */
7131 insn = emit_move_insn (mem_rtx, reg_rtx);
7132 RTX_FRAME_RELATED_P (insn) = 1;
7133 /* If we use an intermediate register for the save, we can't
7134 describe this exactly in cfi as a copy of the to-be-saved
7135 register into the temporary register and then the temporary
7136 register on the stack, because the temporary register can
7137 have a different natural size than the to-be-saved register.
7138 Thus, we gloss over the intermediate copy and pretend we do
7139 a direct save from the to-be-saved register. */
7140 if (REGNO (reg_rtx) != reg)
7144 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
7145 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7148 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
7150 rtx reg_rtx = gen_rtx_REG (mode, reg);
7152 rtx mem_rtx = gen_frame_mem (mode,
7153 gen_rtx_PLUS (Pmode,
7157 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
7158 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7163 gcc_assert (entry->offset == d_rounding);
7167 push_regs (&live_regs_mask, current_function_interrupt);
7171 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7172 emit_insn (gen_GOTaddr2picreg ());
7174 if (SHMEDIA_REGS_STACK_ADJUST ())
7176 /* This must NOT go through the PLT, otherwise mach and macl
7177 may be clobbered. */
7178 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7180 ? "__GCC_push_shmedia_regs"
7181 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7182 emit_insn (gen_shmedia_save_restore_regs_compact
7183 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7186 if (target_flags != save_flags && ! current_function_interrupt)
7187 emit_insn (gen_toggle_sz ());
7189 target_flags = save_flags;
7191 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7192 stack_pointer_rtx, 0, NULL, true);
7193 stack_usage += rounded_frame_size (d) - d_rounding;
7195 if (frame_pointer_needed)
7196 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7198 if (TARGET_SHCOMPACT
7199 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7201 /* This must NOT go through the PLT, otherwise mach and macl
7202 may be clobbered. */
7203 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7204 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7205 emit_insn (gen_shcompact_incoming_args ());
7208 if (flag_stack_usage_info)
7209 current_function_static_stack_size = stack_usage;
7213 sh_expand_epilogue (bool sibcall_p)
7215 HARD_REG_SET live_regs_mask;
7219 int save_flags = target_flags;
7220 int frame_size, save_size;
7221 int fpscr_deferred = 0;
7222 int e = sibcall_p ? -1 : 1;
7224 d = calc_live_regs (&live_regs_mask);
7227 frame_size = rounded_frame_size (d);
7231 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7233 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7234 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7235 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7237 total_size = d + tregs_space;
7238 total_size += rounded_frame_size (total_size);
7239 save_size = total_size - frame_size;
7241 /* If adjusting the stack in a single step costs nothing extra, do so.
7242 I.e. either if a single addi is enough, or we need a movi anyway,
7243 and we don't exceed the maximum offset range (the test for the
7244 latter is conservative for simplicity). */
7246 && ! frame_pointer_needed
7247 && (CONST_OK_FOR_I10 (total_size)
7248 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7249 && total_size <= 2044)))
7250 d_rounding = frame_size;
7252 frame_size -= d_rounding;
7255 if (frame_pointer_needed)
7257 /* We must avoid scheduling the epilogue with previous basic blocks.
7258 See PR/18032 and PR/40313. */
7259 emit_insn (gen_blockage ());
7260 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7261 &live_regs_mask, false);
7263 /* We must avoid moving the stack pointer adjustment past code
7264 which reads from the local frame, else an interrupt could
7265 occur after the SP adjustment and clobber data in the local
7267 emit_insn (gen_blockage ());
7268 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7270 else if (frame_size)
7272 /* We must avoid moving the stack pointer adjustment past code
7273 which reads from the local frame, else an interrupt could
7274 occur after the SP adjustment and clobber data in the local
7276 emit_insn (gen_blockage ());
7277 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7278 &live_regs_mask, false);
7281 if (SHMEDIA_REGS_STACK_ADJUST ())
7283 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7285 ? "__GCC_pop_shmedia_regs"
7286 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7287 /* This must NOT go through the PLT, otherwise mach and macl
7288 may be clobbered. */
7289 emit_insn (gen_shmedia_save_restore_regs_compact
7290 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7293 /* Pop all the registers. */
7295 if (target_flags != save_flags && ! current_function_interrupt)
7296 emit_insn (gen_toggle_sz ());
7299 int offset_base, offset;
7300 int offset_in_r0 = -1;
7302 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7303 save_schedule schedule;
7307 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7308 offset_base = -entry[1].offset + d_rounding;
7309 tmp_pnt = schedule.temps;
7310 for (; entry->mode != VOIDmode; entry--)
7312 enum machine_mode mode = (enum machine_mode) entry->mode;
7313 int reg = entry->reg;
7314 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX;
7316 offset = offset_base + entry->offset;
7317 reg_rtx = gen_rtx_REG (mode, reg);
7319 mem_rtx = gen_frame_mem (mode,
7320 gen_rtx_PLUS (Pmode,
7324 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7327 if (HAVE_POST_INCREMENT
7328 && (offset == offset_in_r0
7329 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7330 && mem_rtx == NULL_RTX)
7331 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7333 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7335 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7336 post_inc = NULL_RTX;
7341 if (mem_rtx != NULL_RTX)
7344 if (offset_in_r0 == -1)
7346 emit_move_insn (r0, GEN_INT (offset));
7347 offset_in_r0 = offset;
7349 else if (offset != offset_in_r0)
7354 GEN_INT (offset - offset_in_r0)));
7355 offset_in_r0 += offset - offset_in_r0;
7358 if (post_inc != NULL_RTX)
7364 (Pmode, r0, stack_pointer_rtx));
7370 offset_in_r0 += GET_MODE_SIZE (mode);
7373 mem_rtx = gen_frame_mem (mode, r0);
7375 mem_rtx = gen_frame_mem (mode,
7376 gen_rtx_PLUS (Pmode,
7380 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7381 || mem_rtx == post_inc);
7384 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7385 && mem_rtx != post_inc)
7387 emit_move_insn (r0, mem_rtx);
7390 else if (TARGET_REGISTER_P (reg))
7392 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7394 /* Give the scheduler a bit of freedom by using up to
7395 MAX_TEMPS registers in a round-robin fashion. */
7396 emit_move_insn (tmp_reg, mem_rtx);
7399 tmp_pnt = schedule.temps;
7402 emit_move_insn (reg_rtx, mem_rtx);
7405 gcc_assert (entry->offset + offset_base == d + d_rounding);
7407 else /* ! TARGET_SH5 */
7412 /* For an ISR with RESBANK attribute assigned, don't pop PR
7414 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7415 && !sh_cfun_resbank_handler_p ())
7417 if (!frame_pointer_needed)
7418 emit_insn (gen_blockage ());
7422 /* Banked registers are popped first to avoid being scheduled in the
7423 delay slot. RTE switches banks before the ds instruction. */
7424 if (current_function_interrupt)
7426 bool use_movml = false;
7430 unsigned int count = 0;
7432 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7433 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7438 /* Use movml when all banked register are poped. */
7439 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7445 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7447 /* We must avoid scheduling multiple load insn with another
7449 emit_insn (gen_blockage ());
7450 emit_insn (gen_movml_pop_banked (sp_reg));
7451 emit_insn (gen_blockage ());
7454 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7455 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7458 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7461 last_reg = FIRST_PSEUDO_REGISTER;
7463 for (i = 0; i < last_reg; i++)
7465 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7467 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7468 && hard_reg_set_intersect_p (live_regs_mask,
7469 reg_class_contents[DF_REGS]))
7471 /* For an ISR with RESBANK attribute assigned, don't pop
7472 following registers, R0-R14, MACH, MACL and GBR. */
7473 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7474 && ! (sh_cfun_resbank_handler_p ()
7475 && ((j >= FIRST_GENERAL_REG
7476 && j < LAST_GENERAL_REG)
7482 if (j == FIRST_FP_REG && fpscr_deferred)
7486 if (target_flags != save_flags && ! current_function_interrupt)
7487 emit_insn (gen_toggle_sz ());
7488 target_flags = save_flags;
7490 output_stack_adjust (crtl->args.pretend_args_size
7491 + save_size + d_rounding
7492 + crtl->args.info.stack_regs * 8,
7493 stack_pointer_rtx, e, NULL, false);
7495 if (crtl->calls_eh_return)
7496 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7497 EH_RETURN_STACKADJ_RTX));
7499 /* Switch back to the normal stack if necessary. */
7500 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7501 emit_insn (gen_sp_switch_2 ());
7503 /* Tell flow the insn that pops PR isn't dead. */
7504 /* PR_REG will never be live in SHmedia mode, and we don't need to
7505 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7506 by the return pattern. */
7507 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7508 emit_use (gen_rtx_REG (SImode, PR_REG));
7511 static int sh_need_epilogue_known = 0;
7514 sh_need_epilogue (void)
7516 if (! sh_need_epilogue_known)
7521 sh_expand_epilogue (0);
7522 epilogue = get_insns ();
7524 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7526 return sh_need_epilogue_known > 0;
7529 /* Emit code to change the current function's return address to RA.
7530 TEMP is available as a scratch register, if needed. */
7533 sh_set_return_address (rtx ra, rtx tmp)
7535 HARD_REG_SET live_regs_mask;
7537 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7540 d = calc_live_regs (&live_regs_mask);
7542 /* If pr_reg isn't life, we can set it (or the register given in
7543 sh_media_register_for_return) directly. */
7544 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7550 int rr_regno = sh_media_register_for_return ();
7555 rr = gen_rtx_REG (DImode, rr_regno);
7558 rr = gen_rtx_REG (SImode, pr_reg);
7560 emit_insn (GEN_MOV (rr, ra));
7561 /* Tell flow the register for return isn't dead. */
7569 save_schedule schedule;
7572 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7573 offset = entry[1].offset;
7574 for (; entry->mode != VOIDmode; entry--)
7575 if (entry->reg == pr_reg)
7578 /* We can't find pr register. */
7582 offset = entry->offset - offset;
7583 pr_offset = (rounded_frame_size (d) + offset
7584 + SHMEDIA_REGS_STACK_ADJUST ());
7587 pr_offset = rounded_frame_size (d);
7589 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7591 if (frame_pointer_needed)
7592 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7594 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7596 tmp = gen_frame_mem (Pmode, tmp);
7597 emit_insn (GEN_MOV (tmp, ra));
7598 /* Tell this store isn't dead. */
7602 /* Clear variables at function end. */
7605 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7606 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7608 sh_need_epilogue_known = 0;
7612 sh_builtin_saveregs (void)
7614 /* First unnamed integer register. */
7615 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7616 /* Number of integer registers we need to save. */
7617 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7618 /* First unnamed SFmode float reg */
7619 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7620 /* Number of SFmode float regs to save. */
7621 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7624 alias_set_type alias_set;
7630 int pushregs = n_intregs;
7632 while (pushregs < NPARM_REGS (SImode) - 1
7633 && (CALL_COOKIE_INT_REG_GET
7634 (crtl->args.info.call_cookie,
7635 NPARM_REGS (SImode) - pushregs)
7638 crtl->args.info.call_cookie
7639 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7644 if (pushregs == NPARM_REGS (SImode))
7645 crtl->args.info.call_cookie
7646 |= (CALL_COOKIE_INT_REG (0, 1)
7647 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7649 crtl->args.info.call_cookie
7650 |= CALL_COOKIE_STACKSEQ (pushregs);
7652 crtl->args.pretend_args_size += 8 * n_intregs;
7654 if (TARGET_SHCOMPACT)
7658 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7660 error ("__builtin_saveregs not supported by this subtarget");
7667 /* Allocate block of memory for the regs. */
7668 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7669 Or can assign_stack_local accept a 0 SIZE argument? */
7670 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7673 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7674 else if (n_floatregs & 1)
7678 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7679 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7680 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7681 regbuf = change_address (regbuf, BLKmode, addr);
7683 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7687 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7688 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7689 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7690 emit_insn (gen_andsi3 (addr, addr, mask));
7691 regbuf = change_address (regbuf, BLKmode, addr);
7694 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7695 alias_set = get_varargs_alias_set ();
7696 set_mem_alias_set (regbuf, alias_set);
7699 This is optimized to only save the regs that are necessary. Explicitly
7700 named args need not be saved. */
7702 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7703 adjust_address (regbuf, BLKmode,
7704 n_floatregs * UNITS_PER_WORD),
7708 /* Return the address of the regbuf. */
7709 return XEXP (regbuf, 0);
7712 This is optimized to only save the regs that are necessary. Explicitly
7713 named args need not be saved.
7714 We explicitly build a pointer to the buffer because it halves the insn
7715 count when not optimizing (otherwise the pointer is built for each reg
7717 We emit the moves in reverse order so that we can use predecrement. */
7719 fpregs = copy_to_mode_reg (Pmode,
7720 plus_constant (XEXP (regbuf, 0),
7721 n_floatregs * UNITS_PER_WORD));
7722 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7725 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7727 emit_insn (gen_addsi3 (fpregs, fpregs,
7728 GEN_INT (-2 * UNITS_PER_WORD)));
7729 mem = change_address (regbuf, DFmode, fpregs);
7730 emit_move_insn (mem,
7731 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7733 regno = first_floatreg;
7736 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7737 mem = change_address (regbuf, SFmode, fpregs);
7738 emit_move_insn (mem,
7739 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7740 - (TARGET_LITTLE_ENDIAN != 0)));
7744 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7748 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7749 mem = change_address (regbuf, SFmode, fpregs);
7750 emit_move_insn (mem,
7751 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7754 /* Return the address of the regbuf. */
7755 return XEXP (regbuf, 0);
7758 /* Define the `__builtin_va_list' type for the ABI. */
7761 sh_build_builtin_va_list (void)
7763 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7764 tree record, type_decl;
7766 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7767 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7768 return ptr_type_node;
7770 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7771 type_decl = build_decl (BUILTINS_LOCATION,
7772 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7774 f_next_o = build_decl (BUILTINS_LOCATION,
7775 FIELD_DECL, get_identifier ("__va_next_o"),
7777 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7779 get_identifier ("__va_next_o_limit"),
7781 f_next_fp = build_decl (BUILTINS_LOCATION,
7782 FIELD_DECL, get_identifier ("__va_next_fp"),
7784 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7786 get_identifier ("__va_next_fp_limit"),
7788 f_next_stack = build_decl (BUILTINS_LOCATION,
7789 FIELD_DECL, get_identifier ("__va_next_stack"),
7792 DECL_FIELD_CONTEXT (f_next_o) = record;
7793 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7794 DECL_FIELD_CONTEXT (f_next_fp) = record;
7795 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7796 DECL_FIELD_CONTEXT (f_next_stack) = record;
7798 TYPE_STUB_DECL (record) = type_decl;
7799 TYPE_NAME (record) = type_decl;
7800 TYPE_FIELDS (record) = f_next_o;
7801 DECL_CHAIN (f_next_o) = f_next_o_limit;
7802 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7803 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7804 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7806 layout_type (record);
7811 /* Implement `va_start' for varargs and stdarg. */
7814 sh_va_start (tree valist, rtx nextarg)
7816 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7817 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7823 expand_builtin_saveregs ();
7824 std_expand_builtin_va_start (valist, nextarg);
7828 if ((! TARGET_SH2E && ! TARGET_SH4)
7829 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7831 std_expand_builtin_va_start (valist, nextarg);
7835 f_next_o = TYPE_FIELDS (va_list_type_node);
7836 f_next_o_limit = DECL_CHAIN (f_next_o);
7837 f_next_fp = DECL_CHAIN (f_next_o_limit);
7838 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7839 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7841 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7843 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7844 valist, f_next_o_limit, NULL_TREE);
7845 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7847 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7848 valist, f_next_fp_limit, NULL_TREE);
7849 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7850 valist, f_next_stack, NULL_TREE);
7852 /* Call __builtin_saveregs. */
7853 u = make_tree (sizetype, expand_builtin_saveregs ());
7854 u = fold_convert (ptr_type_node, u);
7855 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7856 TREE_SIDE_EFFECTS (t) = 1;
7857 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7859 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7864 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp);
7865 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7866 TREE_SIDE_EFFECTS (t) = 1;
7867 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7869 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7870 TREE_SIDE_EFFECTS (t) = 1;
7871 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7873 nint = crtl->args.info.arg_count[SH_ARG_INT];
7878 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint);
7879 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7880 TREE_SIDE_EFFECTS (t) = 1;
7881 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7883 u = make_tree (ptr_type_node, nextarg);
7884 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7885 TREE_SIDE_EFFECTS (t) = 1;
7886 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7889 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7890 member, return it. */
7892 find_sole_member (tree type)
7894 tree field, member = NULL_TREE;
7896 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
7898 if (TREE_CODE (field) != FIELD_DECL)
7900 if (!DECL_SIZE (field))
7902 if (integer_zerop (DECL_SIZE (field)))
7910 /* Implement `va_arg'. */
7913 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7914 gimple_seq *post_p ATTRIBUTE_UNUSED)
7916 HOST_WIDE_INT size, rsize;
7917 tree tmp, pptr_type_node;
7918 tree addr, lab_over = NULL, result = NULL;
7922 if (!VOID_TYPE_P (type))
7923 pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7925 pass_by_ref = false;
7928 type = build_pointer_type (type);
7930 size = int_size_in_bytes (type);
7931 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7932 pptr_type_node = build_pointer_type (ptr_type_node);
7934 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7935 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7937 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7938 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7943 f_next_o = TYPE_FIELDS (va_list_type_node);
7944 f_next_o_limit = DECL_CHAIN (f_next_o);
7945 f_next_fp = DECL_CHAIN (f_next_o_limit);
7946 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7947 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7949 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7951 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7952 valist, f_next_o_limit, NULL_TREE);
7953 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7954 valist, f_next_fp, NULL_TREE);
7955 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7956 valist, f_next_fp_limit, NULL_TREE);
7957 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7958 valist, f_next_stack, NULL_TREE);
7960 /* Structures with a single member with a distinct mode are passed
7961 like their member. This is relevant if the latter has a REAL_TYPE
7962 or COMPLEX_TYPE type. */
7964 while (TREE_CODE (eff_type) == RECORD_TYPE
7965 && (member = find_sole_member (eff_type))
7966 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7967 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7968 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7970 tree field_type = TREE_TYPE (member);
7972 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7973 eff_type = field_type;
7976 gcc_assert ((TYPE_ALIGN (eff_type)
7977 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7978 || (TYPE_ALIGN (eff_type)
7979 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7984 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7986 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7987 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7988 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7993 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7996 addr = create_tmp_var (pptr_type_node, NULL);
7997 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7998 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8000 valist = build_simple_mem_ref (addr);
8004 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
8006 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
8008 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
8009 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8011 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
8012 tmp = next_fp_limit;
8013 if (size > 4 && !is_double)
8014 tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size);
8015 tmp = build2 (GE_EXPR, boolean_type_node,
8016 unshare_expr (next_fp_tmp), unshare_expr (tmp));
8017 cmp = build3 (COND_EXPR, void_type_node, tmp,
8018 build1 (GOTO_EXPR, void_type_node,
8019 unshare_expr (lab_false)), NULL_TREE);
8021 gimplify_and_add (cmp, pre_p);
8023 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
8024 || (is_double || size == 16))
8026 tmp = fold_convert (sizetype, next_fp_tmp);
8027 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
8028 size_int (UNITS_PER_WORD));
8029 tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp);
8030 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
8033 gimplify_and_add (cmp, pre_p);
8035 #ifdef FUNCTION_ARG_SCmode_WART
8036 if (TYPE_MODE (eff_type) == SCmode
8037 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
8039 tree subtype = TREE_TYPE (eff_type);
8043 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8044 imag = get_initialized_tmp_var (imag, pre_p, NULL);
8047 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
8048 real = get_initialized_tmp_var (real, pre_p, NULL);
8050 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
8051 if (type != eff_type)
8052 result = build1 (VIEW_CONVERT_EXPR, type, result);
8053 result = get_initialized_tmp_var (result, pre_p, NULL);
8055 #endif /* FUNCTION_ARG_SCmode_WART */
8057 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8058 gimplify_and_add (tmp, pre_p);
8060 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8061 gimplify_and_add (tmp, pre_p);
8063 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8064 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8065 gimplify_assign (unshare_expr (next_fp_tmp),
8066 unshare_expr (valist), pre_p);
8068 gimplify_assign (unshare_expr (valist),
8069 unshare_expr (next_fp_tmp), post_p);
8070 valist = next_fp_tmp;
8074 tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize);
8075 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
8076 unshare_expr (next_o_limit));
8077 tmp = build3 (COND_EXPR, void_type_node, tmp,
8078 build1 (GOTO_EXPR, void_type_node,
8079 unshare_expr (lab_false)),
8081 gimplify_and_add (tmp, pre_p);
8083 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
8084 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8086 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
8087 gimplify_and_add (tmp, pre_p);
8089 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
8090 gimplify_and_add (tmp, pre_p);
8092 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
8093 gimplify_assign (unshare_expr (next_o),
8094 unshare_expr (next_o_limit), pre_p);
8096 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
8097 gimplify_assign (unshare_expr (addr), tmp, pre_p);
8102 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8103 gimplify_and_add (tmp, pre_p);
8107 /* ??? In va-sh.h, there had been code to make values larger than
8108 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8110 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
8113 gimplify_assign (result, tmp, pre_p);
8114 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
8115 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
8116 gimplify_and_add (tmp, pre_p);
8122 result = build_va_arg_indirect_ref (result);
8127 /* 64 bit floating points memory transfers are paired single precision loads
8128 or store. So DWARF information needs fixing in little endian (unless
8129 PR=SZ=1 in FPSCR). */
8131 sh_dwarf_register_span (rtx reg)
8133 unsigned regno = REGNO (reg);
8135 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8139 gen_rtx_PARALLEL (VOIDmode,
8141 gen_rtx_REG (SFmode,
8142 DBX_REGISTER_NUMBER (regno+1)),
8143 gen_rtx_REG (SFmode,
8144 DBX_REGISTER_NUMBER (regno))));
8147 static enum machine_mode
8148 sh_promote_function_mode (const_tree type, enum machine_mode mode,
8149 int *punsignedp, const_tree funtype,
8152 if (sh_promote_prototypes (funtype))
8153 return promote_mode (type, mode, punsignedp);
8155 return default_promote_function_mode (type, mode, punsignedp, funtype,
8160 sh_promote_prototypes (const_tree type)
8166 return ! sh_attr_renesas_p (type);
8169 /* Whether an argument must be passed by reference. On SHcompact, we
8170 pretend arguments wider than 32-bits that would have been passed in
8171 registers are passed by reference, so that an SHmedia trampoline
8172 loads them into the full 64-bits registers. */
8175 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8176 const_tree type, bool named)
8178 unsigned HOST_WIDE_INT size;
8181 size = int_size_in_bytes (type);
8183 size = GET_MODE_SIZE (mode);
8185 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8187 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8188 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8189 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8191 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8192 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8199 sh_pass_by_reference (cumulative_args_t cum_v, enum machine_mode mode,
8200 const_tree type, bool named)
8202 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8204 if (targetm.calls.must_pass_in_stack (mode, type))
8207 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8208 wants to know about pass-by-reference semantics for incoming
8213 if (TARGET_SHCOMPACT)
8215 cum->byref = shcompact_byref (cum, mode, type, named);
8216 return cum->byref != 0;
8223 sh_callee_copies (cumulative_args_t cum, enum machine_mode mode,
8224 const_tree type, bool named ATTRIBUTE_UNUSED)
8226 /* ??? How can it possibly be correct to return true only on the
8227 caller side of the equation? Is there someplace else in the
8228 sh backend that's magically producing the copies? */
8229 return (get_cumulative_args (cum)->outgoing
8230 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8231 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8235 sh_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8236 tree type, bool named ATTRIBUTE_UNUSED)
8238 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8242 && PASS_IN_REG_P (*cum, mode, type)
8243 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8244 && (ROUND_REG (*cum, mode)
8246 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8247 : ROUND_ADVANCE (int_size_in_bytes (type)))
8248 > NPARM_REGS (mode)))
8249 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8251 else if (!TARGET_SHCOMPACT
8252 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8253 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8255 return words * UNITS_PER_WORD;
8259 /* Define where to put the arguments to a function.
8260 Value is zero to push the argument on the stack,
8261 or a hard register in which to store the argument.
8263 MODE is the argument's machine mode.
8264 TYPE is the data type of the argument (as a tree).
8265 This is null for libcalls where that information may
8267 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8268 the preceding args and about the function being called.
8269 NAMED is nonzero if this argument is a named parameter
8270 (otherwise it is an extra parameter matching an ellipsis).
8272 On SH the first args are normally in registers
8273 and the rest are pushed. Any arg that starts within the first
8274 NPARM_REGS words is at least partially passed in a register unless
8275 its data type forbids. */
8278 sh_function_arg (cumulative_args_t ca_v, enum machine_mode mode,
8279 const_tree type, bool named)
8281 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8283 if (! TARGET_SH5 && mode == VOIDmode)
8284 return GEN_INT (ca->renesas_abi ? 1 : 0);
8287 && PASS_IN_REG_P (*ca, mode, type)
8288 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8292 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8293 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8295 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8296 gen_rtx_REG (SFmode,
8298 + (ROUND_REG (*ca, mode) ^ 1)),
8300 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8301 gen_rtx_REG (SFmode,
8303 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8305 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8308 /* If the alignment of a DF value causes an SF register to be
8309 skipped, we will use that skipped register for the next SF
8311 if ((TARGET_HITACHI || ca->renesas_abi)
8312 && ca->free_single_fp_reg
8314 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8316 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8317 ^ (mode == SFmode && TARGET_SH4
8318 && TARGET_LITTLE_ENDIAN != 0
8319 && ! TARGET_HITACHI && ! ca->renesas_abi);
8320 return gen_rtx_REG (mode, regno);
8326 if (mode == VOIDmode && TARGET_SHCOMPACT)
8327 return GEN_INT (ca->call_cookie);
8329 /* The following test assumes unnamed arguments are promoted to
8331 if (mode == SFmode && ca->free_single_fp_reg)
8332 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8334 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8335 && (named || ! ca->prototype_p)
8336 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8338 if (! ca->prototype_p && TARGET_SHMEDIA)
8339 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8341 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8343 + ca->arg_count[(int) SH_ARG_FLOAT]);
8346 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8347 && (! TARGET_SHCOMPACT
8348 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8349 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8352 return gen_rtx_REG (mode, (FIRST_PARM_REG
8353 + ca->arg_count[(int) SH_ARG_INT]));
8362 /* Update the data in CUM to advance over an argument
8363 of mode MODE and data type TYPE.
8364 (TYPE is null for libcalls where that information may not be
8368 sh_function_arg_advance (cumulative_args_t ca_v, enum machine_mode mode,
8369 const_tree type, bool named)
8371 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8375 else if (TARGET_SH5)
8377 const_tree type2 = (ca->byref && type
8380 enum machine_mode mode2 = (ca->byref && type
8383 int dwords = ((ca->byref
8386 ? int_size_in_bytes (type2)
8387 : GET_MODE_SIZE (mode2)) + 7) / 8;
8388 int numregs = MIN (dwords, NPARM_REGS (SImode)
8389 - ca->arg_count[(int) SH_ARG_INT]);
8393 ca->arg_count[(int) SH_ARG_INT] += numregs;
8394 if (TARGET_SHCOMPACT
8395 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8398 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8400 /* N.B. We want this also for outgoing. */
8401 ca->stack_regs += numregs;
8406 ca->stack_regs += numregs;
8407 ca->byref_regs += numregs;
8411 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8415 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8418 else if (dwords > numregs)
8420 int pushregs = numregs;
8422 if (TARGET_SHCOMPACT)
8423 ca->stack_regs += numregs;
8424 while (pushregs < NPARM_REGS (SImode) - 1
8425 && (CALL_COOKIE_INT_REG_GET
8427 NPARM_REGS (SImode) - pushregs)
8431 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8435 if (numregs == NPARM_REGS (SImode))
8437 |= CALL_COOKIE_INT_REG (0, 1)
8438 | CALL_COOKIE_STACKSEQ (numregs - 1);
8441 |= CALL_COOKIE_STACKSEQ (numregs);
8444 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8445 && (named || ! ca->prototype_p))
8447 if (mode2 == SFmode && ca->free_single_fp_reg)
8448 ca->free_single_fp_reg = 0;
8449 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8450 < NPARM_REGS (SFmode))
8453 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8455 - ca->arg_count[(int) SH_ARG_FLOAT]);
8457 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8459 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8461 if (ca->outgoing && numregs > 0)
8465 |= (CALL_COOKIE_INT_REG
8466 (ca->arg_count[(int) SH_ARG_INT]
8467 - numregs + ((numfpregs - 2) / 2),
8468 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8471 while (numfpregs -= 2);
8473 else if (mode2 == SFmode && (named)
8474 && (ca->arg_count[(int) SH_ARG_FLOAT]
8475 < NPARM_REGS (SFmode)))
8476 ca->free_single_fp_reg
8477 = FIRST_FP_PARM_REG - numfpregs
8478 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8484 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8486 /* Note that we've used the skipped register. */
8487 if (mode == SFmode && ca->free_single_fp_reg)
8489 ca->free_single_fp_reg = 0;
8492 /* When we have a DF after an SF, there's an SF register that get
8493 skipped in order to align the DF value. We note this skipped
8494 register, because the next SF value will use it, and not the
8495 SF that follows the DF. */
8497 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8499 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8500 + BASE_ARG_REG (mode));
8504 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8505 || PASS_IN_REG_P (*ca, mode, type))
8506 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8507 = (ROUND_REG (*ca, mode)
8509 ? ROUND_ADVANCE (int_size_in_bytes (type))
8510 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8513 /* The Renesas calling convention doesn't quite fit into this scheme since
8514 the address is passed like an invisible argument, but one that is always
8515 passed in memory. */
8517 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8519 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8521 return gen_rtx_REG (Pmode, 2);
8524 /* Worker function for TARGET_FUNCTION_VALUE.
8526 For the SH, this is like LIBCALL_VALUE, except that we must change the
8527 mode like PROMOTE_MODE does.
8528 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8529 tested here has to be kept in sync with the one in explow.c:promote_mode.
8533 sh_function_value (const_tree valtype,
8534 const_tree fn_decl_or_type,
8535 bool outgoing ATTRIBUTE_UNUSED)
8538 && !DECL_P (fn_decl_or_type))
8539 fn_decl_or_type = NULL;
8541 return gen_rtx_REG (
8542 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8543 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8544 && (TREE_CODE (valtype) == INTEGER_TYPE
8545 || TREE_CODE (valtype) == ENUMERAL_TYPE
8546 || TREE_CODE (valtype) == BOOLEAN_TYPE
8547 || TREE_CODE (valtype) == REAL_TYPE
8548 || TREE_CODE (valtype) == OFFSET_TYPE))
8549 && sh_promote_prototypes (fn_decl_or_type)
8550 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8551 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8554 /* Worker function for TARGET_LIBCALL_VALUE. */
8557 sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8559 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8562 /* Return true if N is a possible register number of function value. */
8565 sh_function_value_regno_p (const unsigned int regno)
8567 return ((regno) == FIRST_RET_REG
8568 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8569 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8572 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8575 sh_return_in_memory (const_tree type, const_tree fndecl)
8579 if (TYPE_MODE (type) == BLKmode)
8580 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8582 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8586 return (TYPE_MODE (type) == BLKmode
8587 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8588 && TREE_CODE (type) == RECORD_TYPE));
8592 /* We actually emit the code in sh_expand_prologue. We used to use
8593 a static variable to flag that we need to emit this code, but that
8594 doesn't when inlining, when functions are deferred and then emitted
8595 later. Fortunately, we already have two flags that are part of struct
8596 function that tell if a function uses varargs or stdarg. */
8598 sh_setup_incoming_varargs (cumulative_args_t ca,
8599 enum machine_mode mode,
8601 int *pretend_arg_size,
8602 int second_time ATTRIBUTE_UNUSED)
8604 gcc_assert (cfun->stdarg);
8605 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8607 int named_parm_regs, anon_parm_regs;
8609 named_parm_regs = (ROUND_REG (*get_cumulative_args (ca), mode)
8611 ? ROUND_ADVANCE (int_size_in_bytes (type))
8612 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8613 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8614 if (anon_parm_regs > 0)
8615 *pretend_arg_size = anon_parm_regs * 4;
8620 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
8626 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
8628 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8630 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8634 /* Define the offset between two registers, one to be eliminated, and
8635 the other its replacement, at the start of a routine. */
8638 initial_elimination_offset (int from, int to)
8641 int regs_saved_rounding = 0;
8642 int total_saved_regs_space;
8643 int total_auto_space;
8644 int save_flags = target_flags;
8646 HARD_REG_SET live_regs_mask;
8648 shmedia_space_reserved_for_target_registers = false;
8649 regs_saved = calc_live_regs (&live_regs_mask);
8650 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8652 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8654 shmedia_space_reserved_for_target_registers = true;
8655 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8658 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8659 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8660 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8662 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8663 copy_flags = target_flags;
8664 target_flags = save_flags;
8666 total_saved_regs_space = regs_saved + regs_saved_rounding;
8668 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8669 return total_saved_regs_space + total_auto_space
8670 + crtl->args.info.byref_regs * 8;
8672 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8673 return total_saved_regs_space + total_auto_space
8674 + crtl->args.info.byref_regs * 8;
8676 /* Initial gap between fp and sp is 0. */
8677 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8680 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8681 return rounded_frame_size (0);
8683 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8684 return rounded_frame_size (0);
8686 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8687 && (to == HARD_FRAME_POINTER_REGNUM
8688 || to == STACK_POINTER_REGNUM));
8691 int n = total_saved_regs_space;
8692 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8693 save_schedule schedule;
8696 n += total_auto_space;
8698 /* If it wasn't saved, there's not much we can do. */
8699 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8702 target_flags = copy_flags;
8704 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8705 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8706 if (entry->reg == pr_reg)
8708 target_flags = save_flags;
8709 return entry->offset;
8714 return total_auto_space;
8717 /* Parse the -mfixed-range= option string. */
8719 sh_fix_range (const char *const_str)
8722 char *str, *dash, *comma;
8724 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8725 REG2 are either register names or register numbers. The effect
8726 of this option is to mark the registers in the range from REG1 to
8727 REG2 as ``fixed'' so they won't be used by the compiler. */
8729 i = strlen (const_str);
8730 str = (char *) alloca (i + 1);
8731 memcpy (str, const_str, i + 1);
8735 dash = strchr (str, '-');
8738 warning (0, "value of -mfixed-range must have form REG1-REG2");
8742 comma = strchr (dash + 1, ',');
8746 first = decode_reg_name (str);
8749 warning (0, "unknown register name: %s", str);
8753 last = decode_reg_name (dash + 1);
8756 warning (0, "unknown register name: %s", dash + 1);
8764 warning (0, "%s-%s is an empty range", str, dash + 1);
8768 for (i = first; i <= last; ++i)
8769 fixed_regs[i] = call_used_regs[i] = 1;
8779 /* Insert any deferred function attributes from earlier pragmas. */
8781 sh_insert_attributes (tree node, tree *attributes)
8785 if (TREE_CODE (node) != FUNCTION_DECL)
8788 /* We are only interested in fields. */
8792 /* Append the attributes to the deferred attributes. */
8793 *sh_deferred_function_attributes_tail = *attributes;
8794 attrs = sh_deferred_function_attributes;
8798 /* Some attributes imply or require the interrupt attribute. */
8799 if (!lookup_attribute ("interrupt_handler", attrs)
8800 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8802 /* If we have a trapa_handler, but no interrupt_handler attribute,
8803 insert an interrupt_handler attribute. */
8804 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8805 /* We can't use sh_pr_interrupt here because that's not in the
8808 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8809 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8810 if the interrupt attribute is missing, we ignore the attribute
8812 else if (lookup_attribute ("sp_switch", attrs)
8813 || lookup_attribute ("trap_exit", attrs)
8814 || lookup_attribute ("nosave_low_regs", attrs)
8815 || lookup_attribute ("resbank", attrs))
8819 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8821 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8822 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8823 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8824 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8825 warning (OPT_Wattributes,
8826 "%qE attribute only applies to interrupt functions",
8827 TREE_PURPOSE (attrs));
8830 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8832 tail = &TREE_CHAIN (*tail);
8835 attrs = *attributes;
8839 /* Install the processed list. */
8840 *attributes = attrs;
8842 /* Clear deferred attributes. */
8843 sh_deferred_function_attributes = NULL_TREE;
8844 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8849 /* Supported attributes:
8851 interrupt_handler -- specifies this function is an interrupt handler.
8853 trapa_handler - like above, but don't save all registers.
8855 sp_switch -- specifies an alternate stack for an interrupt handler
8858 trap_exit -- use a trapa to exit an interrupt function instead of
8861 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8862 This is useful on the SH3 and upwards,
8863 which has a separate set of low regs for User and Supervisor modes.
8864 This should only be used for the lowest level of interrupts. Higher levels
8865 of interrupts must save the registers in case they themselves are
8868 renesas -- use Renesas calling/layout conventions (functions and
8871 resbank -- In case of an ISR, use a register bank to save registers
8872 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8875 /* Handle a 'resbank' attribute. */
8877 sh_handle_resbank_handler_attribute (tree * node, tree name,
8878 tree args ATTRIBUTE_UNUSED,
8879 int flags ATTRIBUTE_UNUSED,
8880 bool * no_add_attrs)
8884 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8886 *no_add_attrs = true;
8888 if (TREE_CODE (*node) != FUNCTION_DECL)
8890 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8892 *no_add_attrs = true;
8898 /* Handle an "interrupt_handler" attribute; arguments as in
8899 struct attribute_spec.handler. */
8901 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8902 tree args ATTRIBUTE_UNUSED,
8903 int flags ATTRIBUTE_UNUSED,
8906 if (TREE_CODE (*node) != FUNCTION_DECL)
8908 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8910 *no_add_attrs = true;
8912 else if (TARGET_SHCOMPACT)
8914 error ("attribute interrupt_handler is not compatible with -m5-compact");
8915 *no_add_attrs = true;
8921 /* Handle an 'function_vector' attribute; arguments as in
8922 struct attribute_spec.handler. */
8924 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8925 tree args ATTRIBUTE_UNUSED,
8926 int flags ATTRIBUTE_UNUSED,
8927 bool * no_add_attrs)
8931 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8933 *no_add_attrs = true;
8935 else if (TREE_CODE (*node) != FUNCTION_DECL)
8937 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8939 *no_add_attrs = true;
8941 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8943 /* The argument must be a constant integer. */
8944 warning (OPT_Wattributes,
8945 "%qE attribute argument not an integer constant",
8947 *no_add_attrs = true;
8949 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8951 /* The argument value must be between 0 to 255. */
8952 warning (OPT_Wattributes,
8953 "%qE attribute argument should be between 0 to 255",
8955 *no_add_attrs = true;
8960 /* Returns 1 if current function has been assigned the attribute
8961 'function_vector'. */
8963 sh2a_is_function_vector_call (rtx x)
8965 if (GET_CODE (x) == SYMBOL_REF
8966 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8968 tree tr = SYMBOL_REF_DECL (x);
8970 if (sh2a_function_vector_p (tr))
8977 /* Returns the function vector number, if the attribute
8978 'function_vector' is assigned, otherwise returns zero. */
8980 sh2a_get_function_vector_number (rtx x)
8985 if ((GET_CODE (x) == SYMBOL_REF)
8986 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8988 t = SYMBOL_REF_DECL (x);
8990 if (TREE_CODE (t) != FUNCTION_DECL)
8993 list = SH_ATTRIBUTES (t);
8996 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8998 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
9002 list = TREE_CHAIN (list);
9011 /* Handle an "sp_switch" attribute; arguments as in
9012 struct attribute_spec.handler. */
9014 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
9015 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9017 if (TREE_CODE (*node) != FUNCTION_DECL)
9019 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9021 *no_add_attrs = true;
9023 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
9025 /* The argument must be a constant string. */
9026 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
9028 *no_add_attrs = true;
9034 /* Handle an "trap_exit" attribute; arguments as in
9035 struct attribute_spec.handler. */
9037 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
9038 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
9040 if (TREE_CODE (*node) != FUNCTION_DECL)
9042 warning (OPT_Wattributes, "%qE attribute only applies to functions",
9044 *no_add_attrs = true;
9046 /* The argument specifies a trap number to be used in a trapa instruction
9047 at function exit (instead of an rte instruction). */
9048 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
9050 /* The argument must be a constant integer. */
9051 warning (OPT_Wattributes, "%qE attribute argument not an "
9052 "integer constant", name);
9053 *no_add_attrs = true;
9060 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
9061 tree name ATTRIBUTE_UNUSED,
9062 tree args ATTRIBUTE_UNUSED,
9063 int flags ATTRIBUTE_UNUSED,
9064 bool *no_add_attrs ATTRIBUTE_UNUSED)
9069 /* True if __attribute__((renesas)) or -mrenesas. */
9071 sh_attr_renesas_p (const_tree td)
9078 td = TREE_TYPE (td);
9079 if (td == error_mark_node)
9081 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
9085 /* True if __attribute__((renesas)) or -mrenesas, for the current
9088 sh_cfun_attr_renesas_p (void)
9090 return sh_attr_renesas_p (current_function_decl);
9094 sh_cfun_interrupt_handler_p (void)
9096 return (lookup_attribute ("interrupt_handler",
9097 DECL_ATTRIBUTES (current_function_decl))
9101 /* Returns 1 if FUNC has been assigned the attribute
9102 "function_vector". */
9104 sh2a_function_vector_p (tree func)
9107 if (TREE_CODE (func) != FUNCTION_DECL)
9110 list = SH_ATTRIBUTES (func);
9113 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
9116 list = TREE_CHAIN (list);
9121 /* Returns TRUE if given tree has the "resbank" attribute. */
9124 sh_cfun_resbank_handler_p (void)
9126 return ((lookup_attribute ("resbank",
9127 DECL_ATTRIBUTES (current_function_decl))
9129 && (lookup_attribute ("interrupt_handler",
9130 DECL_ATTRIBUTES (current_function_decl))
9131 != NULL_TREE) && TARGET_SH2A);
9134 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9137 sh_check_pch_target_flags (int old_flags)
9139 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9140 | MASK_SH_E | MASK_HARD_SH4
9141 | MASK_FPU_SINGLE | MASK_SH4))
9142 return _("created and used with different architectures / ABIs");
9143 if ((old_flags ^ target_flags) & MASK_HITACHI)
9144 return _("created and used with different ABIs");
9145 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9146 return _("created and used with different endianness");
9150 /* Predicates used by the templates. */
9152 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9153 Used only in general_movsrc_operand. */
9156 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9168 /* Nonzero if OP is a floating point value with value 0.0. */
9171 fp_zero_operand (rtx op)
9175 if (GET_MODE (op) != SFmode)
9178 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9179 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
9182 /* Nonzero if OP is a floating point value with value 1.0. */
9185 fp_one_operand (rtx op)
9189 if (GET_MODE (op) != SFmode)
9192 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9193 return REAL_VALUES_EQUAL (r, dconst1);
9196 /* In general mode switching is used. If we are
9197 compiling without -mfmovd, movsf_ie isn't taken into account for
9198 mode switching. We could check in machine_dependent_reorg for
9199 cases where we know we are in single precision mode, but there is
9200 interface to find that out during reload, so we must avoid
9201 choosing an fldi alternative during reload and thus failing to
9202 allocate a scratch register for the constant loading. */
9209 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9211 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9213 if (GET_CODE (op) != SYMBOL_REF)
9214 return TLS_MODEL_NONE;
9215 return SYMBOL_REF_TLS_MODEL (op);
9218 /* Return the destination address of a branch. */
9221 branch_dest (rtx branch)
9223 rtx dest = SET_SRC (PATTERN (branch));
9226 if (GET_CODE (dest) == IF_THEN_ELSE)
9227 dest = XEXP (dest, 1);
9228 dest = XEXP (dest, 0);
9229 dest_uid = INSN_UID (dest);
9230 return INSN_ADDRESSES (dest_uid);
9233 /* Return nonzero if REG is not used after INSN.
9234 We assume REG is a reload reg, and therefore does
9235 not live past labels. It may live past calls or jumps though. */
9237 reg_unused_after (rtx reg, rtx insn)
9242 /* If the reg is set by this instruction, then it is safe for our
9243 case. Disregard the case where this is a store to memory, since
9244 we are checking a register used in the store address. */
9245 set = single_set (insn);
9246 if (set && !MEM_P (SET_DEST (set))
9247 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9250 while ((insn = NEXT_INSN (insn)))
9256 code = GET_CODE (insn);
9259 /* If this is a label that existed before reload, then the register
9260 is dead here. However, if this is a label added by reorg, then
9261 the register may still be live here. We can't tell the difference,
9262 so we just ignore labels completely. */
9263 if (code == CODE_LABEL)
9268 if (code == JUMP_INSN)
9271 /* If this is a sequence, we must handle them all at once.
9272 We could have for instance a call that sets the target register,
9273 and an insn in a delay slot that uses the register. In this case,
9274 we must return 0. */
9275 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9280 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9282 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9283 rtx set = single_set (this_insn);
9285 if (CALL_P (this_insn))
9287 else if (JUMP_P (this_insn))
9289 if (INSN_ANNULLED_BRANCH_P (this_insn))
9294 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9296 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9298 if (!MEM_P (SET_DEST (set)))
9304 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9309 else if (code == JUMP_INSN)
9313 set = single_set (insn);
9314 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9316 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9317 return !MEM_P (SET_DEST (set));
9318 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9321 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9329 static GTY(()) rtx fpscr_rtx;
9331 get_fpscr_rtx (void)
9335 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9336 REG_USERVAR_P (fpscr_rtx) = 1;
9337 mark_user_reg (fpscr_rtx);
9339 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9340 mark_user_reg (fpscr_rtx);
9344 static GTY(()) tree fpscr_values;
9347 emit_fpu_switch (rtx scratch, int index)
9351 if (fpscr_values == NULL)
9355 t = build_index_type (integer_one_node);
9356 t = build_array_type (integer_type_node, t);
9357 t = build_decl (BUILTINS_LOCATION,
9358 VAR_DECL, get_identifier ("__fpscr_values"), t);
9359 DECL_ARTIFICIAL (t) = 1;
9360 DECL_IGNORED_P (t) = 1;
9361 DECL_EXTERNAL (t) = 1;
9362 TREE_STATIC (t) = 1;
9363 TREE_PUBLIC (t) = 1;
9369 src = DECL_RTL (fpscr_values);
9370 if (!can_create_pseudo_p ())
9372 emit_move_insn (scratch, XEXP (src, 0));
9374 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9375 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9378 src = adjust_address (src, PSImode, index * 4);
9380 dst = get_fpscr_rtx ();
9381 emit_move_insn (dst, src);
9385 emit_sf_insn (rtx pat)
9391 emit_df_insn (rtx pat)
9397 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9399 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9403 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9405 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9410 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9412 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9416 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9418 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9422 static rtx get_free_reg (HARD_REG_SET);
9424 /* This function returns a register to use to load the address to load
9425 the fpscr from. Currently it always returns r1 or r7, but when we are
9426 able to use pseudo registers after combine, or have a better mechanism
9427 for choosing a register, it should be done here. */
9428 /* REGS_LIVE is the liveness information for the point for which we
9429 need this allocation. In some bare-bones exit blocks, r1 is live at the
9430 start. We can even have all of r0..r3 being live:
9431 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9432 INSN before which new insns are placed with will clobber the register
9433 we return. If a basic block consists only of setting the return value
9434 register to a pseudo and using that register, the return value is not
9435 live before or after this block, yet we we'll insert our insns right in
9439 get_free_reg (HARD_REG_SET regs_live)
9441 if (! TEST_HARD_REG_BIT (regs_live, 1))
9442 return gen_rtx_REG (Pmode, 1);
9444 /* Hard reg 1 is live; since this is a small register classes target,
9445 there shouldn't be anything but a jump before the function end. */
9446 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9447 return gen_rtx_REG (Pmode, 7);
9450 /* This function will set the fpscr from memory.
9451 MODE is the mode we are setting it to. */
9453 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9455 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9456 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9459 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9460 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9463 /* Is the given character a logical line separator for the assembler? */
9464 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9465 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9469 sh_insn_length_adjustment (rtx insn)
9471 /* Instructions with unfilled delay slots take up an extra two bytes for
9472 the nop in the delay slot. */
9473 if (((NONJUMP_INSN_P (insn)
9474 && GET_CODE (PATTERN (insn)) != USE
9475 && GET_CODE (PATTERN (insn)) != CLOBBER)
9477 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9478 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9479 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9482 /* SH2e has a bug that prevents the use of annulled branches, so if
9483 the delay slot is not filled, we'll have to put a NOP in it. */
9484 if (sh_cpu_attr == CPU_SH2E
9485 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
9486 && get_attr_type (insn) == TYPE_CBRANCH
9487 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9490 /* sh-dsp parallel processing insn take four bytes instead of two. */
9492 if (NONJUMP_INSN_P (insn))
9495 rtx body = PATTERN (insn);
9498 int maybe_label = 1;
9500 if (GET_CODE (body) == ASM_INPUT)
9501 templ = XSTR (body, 0);
9502 else if (asm_noperands (body) >= 0)
9504 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9513 while (c == ' ' || c == '\t');
9514 /* all sh-dsp parallel-processing insns start with p.
9515 The only non-ppi sh insn starting with p is pref.
9516 The only ppi starting with pr is prnd. */
9517 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9519 /* The repeat pseudo-insn expands two three insns, a total of
9520 six bytes in size. */
9521 else if ((c == 'r' || c == 'R')
9522 && ! strncasecmp ("epeat", templ, 5))
9524 while (c && c != '\n'
9525 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9527 /* If this is a label, it is obviously not a ppi insn. */
9528 if (c == ':' && maybe_label)
9533 else if (c == '\'' || c == '"')
9538 maybe_label = c != ':';
9546 /* Return TRUE for a valid displacement for the REG+disp addressing
9549 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9550 into the FRx registers. We implement this by setting the maximum offset
9551 to zero when the value is SFmode. This also restricts loading of SFmode
9552 values into the integer registers, but that can't be helped. */
9554 /* The SH allows a displacement in a QI or HI amode, but only when the
9555 other operand is R0. GCC doesn't handle this very well, so we forgot
9558 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9559 DI can be any number 0..60. */
9562 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9564 if (CONST_INT_P (op))
9570 /* Check if this is the address of an unaligned load / store. */
9571 if (mode == VOIDmode)
9572 return CONST_OK_FOR_I06 (INTVAL (op));
9574 size = GET_MODE_SIZE (mode);
9575 return (!(INTVAL (op) & (size - 1))
9576 && INTVAL (op) >= -512 * size
9577 && INTVAL (op) < 512 * size);
9582 if (GET_MODE_SIZE (mode) == 1
9583 && (unsigned) INTVAL (op) < 4096)
9587 if ((GET_MODE_SIZE (mode) == 4
9588 && (unsigned) INTVAL (op) < 64
9589 && !(INTVAL (op) & 3)
9590 && !(TARGET_SH2E && mode == SFmode))
9591 || (GET_MODE_SIZE (mode) == 4
9592 && (unsigned) INTVAL (op) < 16383
9593 && !(INTVAL (op) & 3) && TARGET_SH2A))
9596 if ((GET_MODE_SIZE (mode) == 8
9597 && (unsigned) INTVAL (op) < 60
9598 && !(INTVAL (op) & 3)
9599 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9600 || ((GET_MODE_SIZE (mode)==8)
9601 && (unsigned) INTVAL (op) < 8192
9602 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9603 && (TARGET_SH2A && mode == DFmode)))
9610 /* Recognize an RTL expression that is a valid memory address for
9612 The MODE argument is the machine mode for the MEM expression
9613 that wants to use this address.
9621 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9623 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9625 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9627 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9629 else if (GET_CODE (x) == PLUS
9630 && (mode != PSImode || reload_completed))
9632 rtx xop0 = XEXP (x, 0);
9633 rtx xop1 = XEXP (x, 1);
9635 if (GET_MODE_SIZE (mode) <= 8
9636 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9637 && sh_legitimate_index_p (mode, xop1))
9640 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9641 || ((xop0 == stack_pointer_rtx
9642 || xop0 == hard_frame_pointer_rtx)
9643 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9644 || ((xop1 == stack_pointer_rtx
9645 || xop1 == hard_frame_pointer_rtx)
9646 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9647 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9648 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9649 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9650 && TARGET_FMOVD && mode == DFmode)))
9652 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9653 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9655 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9656 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9664 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9665 isn't protected by a PIC unspec. */
9667 nonpic_symbol_mentioned_p (rtx x)
9669 register const char *fmt;
9672 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9673 || GET_CODE (x) == PC)
9676 /* We don't want to look into the possible MEM location of a
9677 CONST_DOUBLE, since we're not going to use it, in general. */
9678 if (GET_CODE (x) == CONST_DOUBLE)
9681 if (GET_CODE (x) == UNSPEC
9682 && (XINT (x, 1) == UNSPEC_PIC
9683 || XINT (x, 1) == UNSPEC_GOT
9684 || XINT (x, 1) == UNSPEC_GOTOFF
9685 || XINT (x, 1) == UNSPEC_GOTPLT
9686 || XINT (x, 1) == UNSPEC_GOTTPOFF
9687 || XINT (x, 1) == UNSPEC_DTPOFF
9688 || XINT (x, 1) == UNSPEC_TPOFF
9689 || XINT (x, 1) == UNSPEC_PLT
9690 || XINT (x, 1) == UNSPEC_SYMOFF
9691 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9694 fmt = GET_RTX_FORMAT (GET_CODE (x));
9695 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9701 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9702 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9705 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9712 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9713 @GOTOFF in `reg'. */
9715 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9718 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9721 if (GET_CODE (orig) == LABEL_REF
9722 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9725 reg = gen_reg_rtx (Pmode);
9727 emit_insn (gen_symGOTOFF2reg (reg, orig));
9730 else if (GET_CODE (orig) == SYMBOL_REF)
9733 reg = gen_reg_rtx (Pmode);
9735 emit_insn (gen_symGOT2reg (reg, orig));
9741 /* Try machine-dependent ways of modifying an illegitimate address
9742 to be legitimate. If we find one, return the new, valid address.
9743 Otherwise, return X.
9745 For the SH, if X is almost suitable for indexing, but the offset is
9746 out of range, convert it into a normal form so that CSE has a chance
9747 of reducing the number of address registers used. */
9750 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9753 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9755 if (GET_CODE (x) == PLUS
9756 && (GET_MODE_SIZE (mode) == 4
9757 || GET_MODE_SIZE (mode) == 8)
9758 && CONST_INT_P (XEXP (x, 1))
9759 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9761 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9762 && ! (TARGET_SH2E && mode == SFmode))
9764 rtx index_rtx = XEXP (x, 1);
9765 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9768 /* On rare occasions, we might get an unaligned pointer
9769 that is indexed in a way to give an aligned address.
9770 Therefore, keep the lower two bits in offset_base. */
9771 /* Instead of offset_base 128..131 use 124..127, so that
9772 simple add suffices. */
9774 offset_base = ((offset + 4) & ~60) - 4;
9776 offset_base = offset & ~60;
9778 /* Sometimes the normal form does not suit DImode. We
9779 could avoid that by using smaller ranges, but that
9780 would give less optimized code when SImode is
9782 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9784 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9785 GEN_INT (offset_base), NULL_RTX, 0,
9788 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9795 /* Attempt to replace *P, which is an address that needs reloading, with
9796 a valid memory address for an operand of mode MODE.
9797 Like for sh_legitimize_address, for the SH we try to get a normal form
9798 of the address. That will allow inheritance of the address reloads. */
9801 sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9804 enum reload_type type = (enum reload_type) itype;
9806 if (GET_CODE (*p) == PLUS
9807 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9808 && CONST_INT_P (XEXP (*p, 1))
9809 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
9811 && ! (TARGET_SH4 && mode == DFmode)
9812 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9813 && (ALLOW_INDEXED_ADDRESS
9814 || XEXP (*p, 0) == stack_pointer_rtx
9815 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9817 rtx index_rtx = XEXP (*p, 1);
9818 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9821 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9823 push_reload (*p, NULL_RTX, p, NULL,
9824 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9827 if (TARGET_SH2E && mode == SFmode)
9830 push_reload (*p, NULL_RTX, p, NULL,
9831 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9834 /* Instead of offset_base 128..131 use 124..127, so that
9835 simple add suffices. */
9837 offset_base = ((offset + 4) & ~60) - 4;
9839 offset_base = offset & ~60;
9840 /* Sometimes the normal form does not suit DImode. We could avoid
9841 that by using smaller ranges, but that would give less optimized
9842 code when SImode is prevalent. */
9843 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9845 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9846 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9847 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9848 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9852 /* We must re-recognize what we created before. */
9853 else if (GET_CODE (*p) == PLUS
9854 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9855 && GET_CODE (XEXP (*p, 0)) == PLUS
9856 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9857 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9858 && CONST_INT_P (XEXP (*p, 1))
9860 && ! (TARGET_SH2E && mode == SFmode))
9862 /* Because this address is so complex, we know it must have
9863 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9864 it is already unshared, and needs no further unsharing. */
9865 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9866 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9876 /* In the name of slightly smaller debug output, and to cater to
9877 general assembler lossage, recognize various UNSPEC sequences
9878 and turn them back into a direct symbol reference. */
9881 sh_delegitimize_address (rtx orig_x)
9885 orig_x = delegitimize_mem_from_attrs (orig_x);
9890 if (GET_CODE (x) == CONST)
9893 if (GET_CODE (y) == UNSPEC)
9895 if (XINT (y, 1) == UNSPEC_GOT
9896 || XINT (y, 1) == UNSPEC_GOTOFF
9897 || XINT (y, 1) == UNSPEC_SYMOFF)
9898 return XVECEXP (y, 0, 0);
9899 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
9901 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
9903 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
9905 if (GET_CODE (symplt) == UNSPEC
9906 && XINT (symplt, 1) == UNSPEC_PLT)
9907 return XVECEXP (symplt, 0, 0);
9910 else if (TARGET_SHMEDIA
9911 && (XINT (y, 1) == UNSPEC_EXTRACT_S16
9912 || XINT (y, 1) == UNSPEC_EXTRACT_U16))
9914 rtx offset = XVECEXP (y, 0, 1);
9916 x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset);
9918 x = replace_equiv_address_nv (orig_x, x);
9927 /* Mark the use of a constant in the literal table. If the constant
9928 has multiple labels, make it unique. */
9930 mark_constant_pool_use (rtx x)
9932 rtx insn, lab, pattern;
9937 switch (GET_CODE (x))
9947 /* Get the first label in the list of labels for the same constant
9948 and delete another labels in the list. */
9950 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9953 || LABEL_REFS (insn) != NEXT_INSN (insn))
9958 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9959 INSN_DELETED_P (insn) = 1;
9961 /* Mark constants in a window. */
9962 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9964 if (!NONJUMP_INSN_P (insn))
9967 pattern = PATTERN (insn);
9968 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9971 switch (XINT (pattern, 1))
9973 case UNSPECV_CONST2:
9974 case UNSPECV_CONST4:
9975 case UNSPECV_CONST8:
9976 XVECEXP (pattern, 0, 1) = const1_rtx;
9978 case UNSPECV_WINDOW_END:
9979 if (XVECEXP (pattern, 0, 0) == x)
9982 case UNSPECV_CONST_END:
9992 /* Return true if it's possible to redirect BRANCH1 to the destination
9993 of an unconditional jump BRANCH2. We only want to do this if the
9994 resulting branch will have a short displacement. */
9996 sh_can_redirect_branch (rtx branch1, rtx branch2)
9998 if (flag_expensive_optimizations && simplejump_p (branch2))
10000 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
10004 for (distance = 0, insn = NEXT_INSN (branch1);
10005 insn && distance < 256;
10006 insn = PREV_INSN (insn))
10011 distance += get_attr_length (insn);
10013 for (distance = 0, insn = NEXT_INSN (branch1);
10014 insn && distance < 256;
10015 insn = NEXT_INSN (insn))
10020 distance += get_attr_length (insn);
10026 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10028 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
10029 unsigned int new_reg)
10031 /* Interrupt functions can only use registers that have already been
10032 saved by the prologue, even if they would normally be
10035 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
10041 /* Function to update the integer COST
10042 based on the relationship between INSN that is dependent on
10043 DEP_INSN through the dependence LINK. The default is to make no
10044 adjustment to COST. This can be used for example to specify to
10045 the scheduler that an output- or anti-dependence does not incur
10046 the same cost as a data-dependence. The return value should be
10047 the new value for COST. */
10049 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
10053 if (TARGET_SHMEDIA)
10055 /* On SHmedia, if the dependence is an anti-dependence or
10056 output-dependence, there is no cost. */
10057 if (REG_NOTE_KIND (link) != 0)
10059 /* However, dependencies between target register loads and
10060 uses of the register in a subsequent block that are separated
10061 by a conditional branch are not modelled - we have to do with
10062 the anti-dependency between the target register load and the
10063 conditional branch that ends the current block. */
10064 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
10065 && GET_CODE (PATTERN (dep_insn)) == SET
10066 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
10067 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
10068 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
10070 int orig_cost = cost;
10071 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
10072 rtx target = ((! note
10073 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
10074 ? insn : JUMP_LABEL (insn));
10075 /* On the likely path, the branch costs 1, on the unlikely path,
10079 target = next_active_insn (target);
10080 while (target && ! flow_dependent_p (target, dep_insn)
10082 /* If two branches are executed in immediate succession, with the
10083 first branch properly predicted, this causes a stall at the
10084 second branch, hence we won't need the target for the
10085 second branch for two cycles after the launch of the first
10087 if (cost > orig_cost - 2)
10088 cost = orig_cost - 2;
10094 else if (get_attr_is_mac_media (insn)
10095 && get_attr_is_mac_media (dep_insn))
10098 else if (! reload_completed
10099 && GET_CODE (PATTERN (insn)) == SET
10100 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
10101 && GET_CODE (PATTERN (dep_insn)) == SET
10102 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
10105 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10106 that is needed at the target. */
10107 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
10108 && ! flow_dependent_p (insn, dep_insn))
10111 else if (REG_NOTE_KIND (link) == 0)
10113 enum attr_type type;
10116 if (recog_memoized (insn) < 0
10117 || recog_memoized (dep_insn) < 0)
10120 dep_set = single_set (dep_insn);
10122 /* The latency that we specify in the scheduling description refers
10123 to the actual output, not to an auto-increment register; for that,
10124 the latency is one. */
10125 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
10127 rtx set = single_set (insn);
10130 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
10131 && (!MEM_P (SET_DEST (set))
10132 || !reg_mentioned_p (SET_DEST (dep_set),
10133 XEXP (SET_DEST (set), 0))))
10136 /* The only input for a call that is timing-critical is the
10137 function's address. */
10140 rtx call = PATTERN (insn);
10142 if (GET_CODE (call) == PARALLEL)
10143 call = XVECEXP (call, 0 ,0);
10144 if (GET_CODE (call) == SET)
10145 call = SET_SRC (call);
10146 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
10147 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10148 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
10149 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
10150 cost -= TARGET_SH4_300 ? 3 : 6;
10152 /* Likewise, the most timing critical input for an sfuncs call
10153 is the function address. However, sfuncs typically start
10154 using their arguments pretty quickly.
10155 Assume a four cycle delay for SH4 before they are needed.
10156 Cached ST40-300 calls are quicker, so assume only a one
10158 ??? Maybe we should encode the delays till input registers
10159 are needed by sfuncs into the sfunc call insn. */
10160 /* All sfunc calls are parallels with at least four components.
10161 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10162 else if (GET_CODE (PATTERN (insn)) == PARALLEL
10163 && XVECLEN (PATTERN (insn), 0) >= 4
10164 && (reg = sfunc_uses_reg (insn)))
10166 if (! reg_set_p (reg, dep_insn))
10167 cost -= TARGET_SH4_300 ? 1 : 4;
10169 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
10171 enum attr_type dep_type = get_attr_type (dep_insn);
10173 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
10175 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
10176 && (type = get_attr_type (insn)) != TYPE_CALL
10177 && type != TYPE_SFUNC)
10179 /* When the preceding instruction loads the shift amount of
10180 the following SHAD/SHLD, the latency of the load is increased
10182 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10183 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
10184 && reg_overlap_mentioned_p (SET_DEST (dep_set),
10185 XEXP (SET_SRC (single_set (insn)),
10188 /* When an LS group instruction with a latency of less than
10189 3 cycles is followed by a double-precision floating-point
10190 instruction, FIPR, or FTRV, the latency of the first
10191 instruction is increased to 3 cycles. */
10193 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10194 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10196 /* The lsw register of a double-precision computation is ready one
10198 else if (reload_completed
10199 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10200 && (use_pat = single_set (insn))
10201 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10202 SET_SRC (use_pat)))
10205 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10206 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10209 else if (TARGET_SH4_300)
10211 /* Stores need their input register two cycles later. */
10212 if (dep_set && cost >= 1
10213 && ((type = get_attr_type (insn)) == TYPE_STORE
10214 || type == TYPE_PSTORE
10215 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10217 rtx set = single_set (insn);
10219 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10220 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10223 /* But don't reduce the cost below 1 if the address depends
10224 on a side effect of dep_insn. */
10226 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10232 /* An anti-dependence penalty of two applies if the first insn is a double
10233 precision fadd / fsub / fmul. */
10234 else if (!TARGET_SH4_300
10235 && REG_NOTE_KIND (link) == REG_DEP_ANTI
10236 && recog_memoized (dep_insn) >= 0
10237 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10238 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
10239 /* A lot of alleged anti-flow dependences are fake,
10240 so check this one is real. */
10241 && flow_dependent_p (dep_insn, insn))
10247 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10248 if DEP_INSN is anti-flow dependent on INSN. */
10250 flow_dependent_p (rtx insn, rtx dep_insn)
10252 rtx tmp = PATTERN (insn);
10254 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10255 return tmp == NULL_RTX;
10258 /* A helper function for flow_dependent_p called through note_stores. */
10260 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10262 rtx * pinsn = (rtx *) data;
10264 if (*pinsn && reg_referenced_p (x, *pinsn))
10268 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10269 'special function' patterns (type sfunc) that clobber pr, but that
10270 do not look like function calls to leaf_function_p. Hence we must
10271 do this extra check. */
10273 sh_pr_n_sets (void)
10275 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10278 /* Return where to allocate pseudo for a given hard register initial
10281 sh_allocate_initial_value (rtx hard_reg)
10285 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10287 if (current_function_is_leaf
10288 && ! sh_pr_n_sets ()
10289 && ! (TARGET_SHCOMPACT
10290 && ((crtl->args.info.call_cookie
10291 & ~ CALL_COOKIE_RET_TRAMP (1))
10292 || crtl->saves_all_registers)))
10295 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
10303 /* This function returns "2" to indicate dual issue for the SH4
10304 processor. To be used by the DFA pipeline description. */
10306 sh_issue_rate (void)
10308 if (TARGET_SUPERSCALAR)
10314 /* Functions for ready queue reordering for sched1. */
10316 /* Get weight for mode for a set x. */
10318 find_set_regmode_weight (rtx x, enum machine_mode mode)
10320 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10322 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10324 if (REG_P (SET_DEST (x)))
10326 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10336 /* Get regmode weight for insn. */
10338 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
10340 short reg_weight = 0;
10343 /* Increment weight for each register born here. */
10344 x = PATTERN (insn);
10345 reg_weight += find_set_regmode_weight (x, mode);
10346 if (GET_CODE (x) == PARALLEL)
10349 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10351 x = XVECEXP (PATTERN (insn), 0, j);
10352 reg_weight += find_set_regmode_weight (x, mode);
10355 /* Decrement weight for each register that dies here. */
10356 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10358 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10360 rtx note = XEXP (x, 0);
10361 if (REG_P (note) && GET_MODE (note) == mode)
10368 /* Calculate regmode weights for all insns of a basic block. */
10370 find_regmode_weight (basic_block b, enum machine_mode mode)
10372 rtx insn, next_tail, head, tail;
10374 get_ebb_head_tail (b, b, &head, &tail);
10375 next_tail = NEXT_INSN (tail);
10377 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10379 /* Handle register life information. */
10380 if (!INSN_P (insn))
10383 if (mode == SFmode)
10384 INSN_REGMODE_WEIGHT (insn, mode) =
10385 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10386 else if (mode == SImode)
10387 INSN_REGMODE_WEIGHT (insn, mode) =
10388 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10392 /* Comparison function for ready queue sorting. */
10394 rank_for_reorder (const void *x, const void *y)
10396 rtx tmp = *(const rtx *) y;
10397 rtx tmp2 = *(const rtx *) x;
10399 /* The insn in a schedule group should be issued the first. */
10400 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10401 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10403 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10404 minimizes instruction movement, thus minimizing sched's effect on
10405 register pressure. */
10406 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10409 /* Resort the array A in which only element at index N may be out of order. */
10411 swap_reorder (rtx *a, int n)
10413 rtx insn = a[n - 1];
10416 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10424 #define SCHED_REORDER(READY, N_READY) \
10427 if ((N_READY) == 2) \
10428 swap_reorder (READY, N_READY); \
10429 else if ((N_READY) > 2) \
10430 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10434 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10437 ready_reorder (rtx *ready, int nready)
10439 SCHED_REORDER (ready, nready);
10442 /* Count life regions of r0 for a block. */
10444 find_r0_life_regions (basic_block b)
10453 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10464 insn = BB_HEAD (b);
10466 r0_reg = gen_rtx_REG (SImode, R0_REG);
10471 if (find_regno_note (insn, REG_DEAD, R0_REG))
10477 && (pset = single_set (insn))
10478 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10479 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10487 insn = NEXT_INSN (insn);
10489 return set - death;
10492 /* Calculate regmode weights for all insns of all basic block. */
10494 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10495 int verbose ATTRIBUTE_UNUSED,
10500 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10501 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10502 r0_life_regions = 0;
10504 FOR_EACH_BB_REVERSE (b)
10506 find_regmode_weight (b, SImode);
10507 find_regmode_weight (b, SFmode);
10508 if (!reload_completed)
10509 r0_life_regions += find_r0_life_regions (b);
10512 CURR_REGMODE_PRESSURE (SImode) = 0;
10513 CURR_REGMODE_PRESSURE (SFmode) = 0;
10519 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10520 int verbose ATTRIBUTE_UNUSED)
10522 if (regmode_weight[0])
10524 free (regmode_weight[0]);
10525 regmode_weight[0] = NULL;
10527 if (regmode_weight[1])
10529 free (regmode_weight[1]);
10530 regmode_weight[1] = NULL;
10534 /* The scalar modes supported differs from the default version in TImode
10535 for 32-bit SHMEDIA. */
10537 sh_scalar_mode_supported_p (enum machine_mode mode)
10539 if (TARGET_SHMEDIA32 && mode == TImode)
10542 return default_scalar_mode_supported_p (mode);
10545 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10546 keep count of register pressures on SImode and SFmode. */
10548 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10549 int sched_verbose ATTRIBUTE_UNUSED,
10551 int can_issue_more)
10553 if (GET_CODE (PATTERN (insn)) != USE
10554 && GET_CODE (PATTERN (insn)) != CLOBBER)
10555 cached_can_issue_more = can_issue_more - 1;
10557 cached_can_issue_more = can_issue_more;
10559 if (reload_completed)
10560 return cached_can_issue_more;
10562 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10563 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10565 return cached_can_issue_more;
10569 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10570 int verbose ATTRIBUTE_UNUSED,
10571 int veclen ATTRIBUTE_UNUSED)
10573 CURR_REGMODE_PRESSURE (SImode) = 0;
10574 CURR_REGMODE_PRESSURE (SFmode) = 0;
10577 /* Some magic numbers. */
10578 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10579 functions that already have high pressure on r0. */
10580 #define R0_MAX_LIFE_REGIONS 2
10581 /* Register Pressure thresholds for SImode and SFmode registers. */
10582 #define SIMODE_MAX_WEIGHT 5
10583 #define SFMODE_MAX_WEIGHT 10
10585 /* Return true if the pressure is high for MODE. */
10587 high_pressure (enum machine_mode mode)
10589 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10590 functions that already have high pressure on r0. */
10591 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10594 if (mode == SFmode)
10595 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10597 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10600 /* Reorder ready queue if register pressure is high. */
10602 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10603 int sched_verbose ATTRIBUTE_UNUSED,
10606 int clock_var ATTRIBUTE_UNUSED)
10608 if (reload_completed)
10609 return sh_issue_rate ();
10611 if (high_pressure (SFmode) || high_pressure (SImode))
10613 ready_reorder (ready, *n_readyp);
10616 return sh_issue_rate ();
10619 /* Skip cycles if the current register pressure is high. */
10621 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10622 int sched_verbose ATTRIBUTE_UNUSED,
10623 rtx *ready ATTRIBUTE_UNUSED,
10624 int *n_readyp ATTRIBUTE_UNUSED,
10625 int clock_var ATTRIBUTE_UNUSED)
10627 if (reload_completed)
10628 return cached_can_issue_more;
10630 if (high_pressure(SFmode) || high_pressure (SImode))
10633 return cached_can_issue_more;
10636 /* Skip cycles without sorting the ready queue. This will move insn from
10637 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10638 queue by sh_reorder. */
10640 /* Generally, skipping these many cycles are sufficient for all insns to move
10642 #define MAX_SKIPS 8
10645 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10646 int sched_verbose ATTRIBUTE_UNUSED,
10647 rtx insn ATTRIBUTE_UNUSED,
10648 int last_clock_var,
10652 if (reload_completed)
10657 if ((clock_var - last_clock_var) < MAX_SKIPS)
10662 /* If this is the last cycle we are skipping, allow reordering of R. */
10663 if ((clock_var - last_clock_var) == MAX_SKIPS)
10675 /* SHmedia requires registers for branches, so we can't generate new
10676 branches past reload. */
10678 sh_cannot_modify_jumps_p (void)
10680 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10684 sh_target_reg_class (void)
10686 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10690 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10692 HARD_REG_SET dummy;
10697 if (! shmedia_space_reserved_for_target_registers)
10699 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10701 if (calc_live_regs (&dummy) >= 6 * 8)
10707 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10709 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10713 On the SH1..SH4, the trampoline looks like
10714 2 0002 D202 mov.l l2,r2
10715 1 0000 D301 mov.l l1,r3
10716 3 0004 422B jmp @r2
10718 5 0008 00000000 l1: .long area
10719 6 000c 00000000 l2: .long function
10721 SH5 (compact) uses r1 instead of r3 for the static chain. */
10724 /* Emit RTL insns to initialize the variable parts of a trampoline.
10725 FNADDR is an RTX for the address of the function's pure code.
10726 CXT is an RTX for the static chain value for the function. */
10729 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10731 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10732 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10734 if (TARGET_SHMEDIA64)
10739 rtx movi1 = GEN_INT (0xcc000010);
10740 rtx shori1 = GEN_INT (0xc8000010);
10743 /* The following trampoline works within a +- 128 KB range for cxt:
10744 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10745 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10746 gettr tr1,r1; blink tr0,r63 */
10747 /* Address rounding makes it hard to compute the exact bounds of the
10748 offset for this trampoline, but we have a rather generous offset
10749 range, so frame_offset should do fine as an upper bound. */
10750 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10752 /* ??? could optimize this trampoline initialization
10753 by writing DImode words with two insns each. */
10754 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10755 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10756 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10757 insn = gen_rtx_AND (DImode, insn, mask);
10758 /* Or in ptb/u .,tr1 pattern */
10759 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10760 insn = force_operand (insn, NULL_RTX);
10761 insn = gen_lowpart (SImode, insn);
10762 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10763 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10764 insn = gen_rtx_AND (DImode, insn, mask);
10765 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10766 insn = gen_lowpart (SImode, insn);
10767 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10768 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10769 insn = gen_rtx_AND (DImode, insn, mask);
10770 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10771 insn = gen_lowpart (SImode, insn);
10772 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10773 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10774 insn = gen_rtx_AND (DImode, insn, mask);
10775 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10776 insn = gen_lowpart (SImode, insn);
10777 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10778 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10779 insn = gen_rtx_AND (DImode, insn, mask);
10780 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10781 insn = gen_lowpart (SImode, insn);
10782 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10783 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10784 GEN_INT (0x6bf10600));
10785 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10786 GEN_INT (0x4415fc10));
10787 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10788 GEN_INT (0x4401fff0));
10789 emit_insn (gen_ic_invalidate_line (tramp));
10792 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10793 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10795 tramp_templ = gen_datalabel_ref (tramp_templ);
10797 src = gen_const_mem (BLKmode, tramp_templ);
10798 set_mem_align (dst, 256);
10799 set_mem_align (src, 64);
10800 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10802 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10803 emit_move_insn (adjust_address (tramp_mem, Pmode,
10804 fixed_len + GET_MODE_SIZE (Pmode)),
10806 emit_insn (gen_ic_invalidate_line (tramp));
10809 else if (TARGET_SHMEDIA)
10811 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10812 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10813 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10814 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10815 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10816 rotated 10 right, and higher 16 bit of every 32 selected. */
10818 = force_reg (V2HImode, (simplify_gen_subreg
10819 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10820 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10821 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10823 fnaddr = force_reg (SImode, fnaddr);
10824 cxt = force_reg (SImode, cxt);
10825 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10826 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10828 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10829 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10830 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10831 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10832 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10833 gen_rtx_SUBREG (V2HImode, cxt, 0),
10835 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10836 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10837 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10838 if (TARGET_LITTLE_ENDIAN)
10840 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10841 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10845 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10846 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10848 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10849 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10850 emit_insn (gen_ic_invalidate_line (tramp));
10853 else if (TARGET_SHCOMPACT)
10855 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10858 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10859 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10861 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10862 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10864 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10865 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10866 if (TARGET_HARVARD)
10868 if (!TARGET_INLINE_IC_INVALIDATE
10869 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10870 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10871 FUNCTION_ORDINARY),
10872 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10874 emit_insn (gen_ic_invalidate_line (tramp));
10878 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10881 sh_trampoline_adjust_address (rtx tramp)
10883 if (TARGET_SHMEDIA)
10884 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
10885 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
10889 /* FIXME: This is overly conservative. A SHcompact function that
10890 receives arguments ``by reference'' will have them stored in its
10891 own stack frame, so it must not pass pointers or references to
10892 these arguments to other functions by means of sibling calls. */
10893 /* If PIC, we cannot make sibling calls to global functions
10894 because the PLT requires r12 to be live. */
10896 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10899 && (! TARGET_SHCOMPACT
10900 || crtl->args.info.stack_regs == 0)
10901 && ! sh_cfun_interrupt_handler_p ()
10903 || (decl && ! TREE_PUBLIC (decl))
10904 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10907 /* Machine specific built-in functions. */
10909 struct builtin_description
10911 const enum insn_code icode;
10912 const char *const name;
10917 /* describe number and signedness of arguments; arg[0] == result
10918 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10919 /* 9: 64-bit pointer, 10: 32-bit pointer */
10920 static const char signature_args[][4] =
10922 #define SH_BLTIN_V2SI2 0
10924 #define SH_BLTIN_V4HI2 1
10926 #define SH_BLTIN_V2SI3 2
10928 #define SH_BLTIN_V4HI3 3
10930 #define SH_BLTIN_V8QI3 4
10932 #define SH_BLTIN_MAC_HISI 5
10934 #define SH_BLTIN_SH_HI 6
10936 #define SH_BLTIN_SH_SI 7
10938 #define SH_BLTIN_V4HI2V2SI 8
10940 #define SH_BLTIN_V4HI2V8QI 9
10942 #define SH_BLTIN_SISF 10
10944 #define SH_BLTIN_LDUA_L 11
10946 #define SH_BLTIN_LDUA_Q 12
10948 #define SH_BLTIN_STUA_L 13
10950 #define SH_BLTIN_STUA_Q 14
10952 #define SH_BLTIN_LDUA_L64 15
10954 #define SH_BLTIN_LDUA_Q64 16
10956 #define SH_BLTIN_STUA_L64 17
10958 #define SH_BLTIN_STUA_Q64 18
10960 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10961 #define SH_BLTIN_2 19
10962 #define SH_BLTIN_SU 19
10964 #define SH_BLTIN_3 20
10965 #define SH_BLTIN_SUS 20
10967 #define SH_BLTIN_PSSV 21
10969 #define SH_BLTIN_XXUU 22
10970 #define SH_BLTIN_UUUU 22
10972 #define SH_BLTIN_PV 23
10975 /* mcmv: operands considered unsigned. */
10976 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10977 /* mperm: control value considered unsigned int. */
10978 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10979 /* mshards_q: returns signed short. */
10980 /* nsb: takes long long arg, returns unsigned char. */
10981 static struct builtin_description bdesc[] =
10983 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
10984 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
10985 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
10986 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
10987 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
10988 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
10989 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
10990 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
10991 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
10992 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
10993 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
10994 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
10995 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
10996 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
10997 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
10998 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
10999 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
11000 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
11001 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
11002 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
11003 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
11004 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
11005 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
11006 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
11007 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
11008 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
11009 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
11010 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
11011 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
11012 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
11013 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
11014 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
11015 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
11016 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
11017 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
11018 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
11019 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
11020 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
11021 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
11022 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
11023 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
11024 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
11025 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
11026 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
11027 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
11028 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
11029 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
11030 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
11031 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
11032 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
11033 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
11034 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
11035 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
11036 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
11037 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
11038 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
11039 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
11040 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
11041 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
11042 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
11043 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
11044 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
11045 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
11046 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
11047 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
11048 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
11049 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
11050 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
11051 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
11052 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
11053 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
11054 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
11055 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
11056 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
11057 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
11058 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
11059 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
11060 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
11061 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
11062 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
11063 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
11064 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
11065 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
11066 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
11070 sh_media_init_builtins (void)
11072 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
11073 struct builtin_description *d;
11075 memset (shared, 0, sizeof shared);
11076 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
11078 tree type, arg_type = 0;
11079 int signature = d->signature;
11082 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
11083 type = shared[signature];
11086 int has_result = signature_args[signature][0] != 0;
11089 if ((signature_args[signature][1] & 8)
11090 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
11091 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
11093 if (! TARGET_FPU_ANY
11094 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
11096 for (i = 0; i < (int) ARRAY_SIZE (args); i++)
11097 args[i] = NULL_TREE;
11100 int arg = signature_args[signature][i];
11101 int opno = i - 1 + has_result;
11104 arg_type = ptr_type_node;
11106 arg_type = (*lang_hooks.types.type_for_mode)
11107 (insn_data[d->icode].operand[opno].mode,
11112 arg_type = void_type_node;
11115 args[i-1] = arg_type;
11117 type = build_function_type_list (arg_type, args[0], args[1],
11118 args[2], NULL_TREE);
11119 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
11120 shared[signature] = type;
11123 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
11128 /* Returns the shmedia builtin decl for CODE. */
11131 sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11133 if (code >= ARRAY_SIZE (bdesc))
11134 return error_mark_node;
11136 return bdesc[code].fndecl;
11139 /* Implements target hook vector_mode_supported_p. */
11141 sh_vector_mode_supported_p (enum machine_mode mode)
11144 && ((mode == V2SFmode)
11145 || (mode == V4SFmode)
11146 || (mode == V16SFmode)))
11149 else if (TARGET_SHMEDIA
11150 && ((mode == V8QImode)
11151 || (mode == V2HImode)
11152 || (mode == V4HImode)
11153 || (mode == V2SImode)))
11160 sh_frame_pointer_required (void)
11162 /* If needed override this in other tm.h files to cope with various OS
11163 lossage requiring a frame pointer. */
11164 if (SUBTARGET_FRAME_POINTER_REQUIRED)
11173 /* Implements target hook dwarf_calling_convention. Return an enum
11174 of dwarf_calling_convention. */
11176 sh_dwarf_calling_convention (const_tree func)
11178 if (sh_attr_renesas_p (func))
11179 return DW_CC_GNU_renesas_sh;
11181 return DW_CC_normal;
11185 sh_init_builtins (void)
11187 if (TARGET_SHMEDIA)
11188 sh_media_init_builtins ();
11191 /* Returns the sh builtin decl for CODE. */
11194 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11196 if (TARGET_SHMEDIA)
11197 return sh_media_builtin_decl (code, initialize_p);
11199 return error_mark_node;
11202 /* Expand an expression EXP that calls a built-in function,
11203 with result going to TARGET if that's convenient
11204 (and in mode MODE if that's convenient).
11205 SUBTARGET may be used as the target for computing one of EXP's operands.
11206 IGNORE is nonzero if the value is to be ignored. */
11209 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11210 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
11212 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11213 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11214 const struct builtin_description *d = &bdesc[fcode];
11215 enum insn_code icode = d->icode;
11216 int signature = d->signature;
11217 enum machine_mode tmode = VOIDmode;
11222 if (signature_args[signature][0])
11227 tmode = insn_data[icode].operand[0].mode;
11229 || GET_MODE (target) != tmode
11230 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11231 target = gen_reg_rtx (tmode);
11232 op[nop++] = target;
11237 for (i = 1; i <= 3; i++, nop++)
11240 enum machine_mode opmode, argmode;
11243 if (! signature_args[signature][i])
11245 arg = CALL_EXPR_ARG (exp, i - 1);
11246 if (arg == error_mark_node)
11248 if (signature_args[signature][i] & 8)
11251 optype = ptr_type_node;
11255 opmode = insn_data[icode].operand[nop].mode;
11256 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11258 argmode = TYPE_MODE (TREE_TYPE (arg));
11259 if (argmode != opmode)
11260 arg = build1 (NOP_EXPR, optype, arg);
11261 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
11262 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11263 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11269 pat = (*insn_data[d->icode].genfun) (op[0]);
11272 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11275 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11278 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11281 gcc_unreachable ();
11290 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
11292 rtx sel0 = const0_rtx;
11293 rtx sel1 = const1_rtx;
11294 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
11295 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11297 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11298 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11302 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
11304 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11306 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11307 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
11310 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11311 We can allow any mode in any general register. The special registers
11312 only allow SImode. Don't allow any mode in the PR.
11314 We cannot hold DCmode values in the XD registers because alter_reg
11315 handles subregs of them incorrectly. We could work around this by
11316 spacing the XD registers like the DR registers, but this would require
11317 additional memory in every compilation to hold larger register vectors.
11318 We could hold SFmode / SCmode values in XD registers, but that
11319 would require a tertiary reload when reloading from / to memory,
11320 and a secondary reload to reload from / to general regs; that
11321 seems to be a loosing proposition.
11323 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11324 it won't be ferried through GP registers first. */
11327 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11329 if (SPECIAL_REGISTER_P (regno))
11330 return mode == SImode;
11332 if (regno == FPUL_REG)
11333 return (mode == SImode || mode == SFmode);
11335 if (FP_REGISTER_P (regno) && mode == SFmode)
11338 if (mode == V2SFmode)
11340 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11341 || GENERAL_REGISTER_P (regno)))
11347 if (mode == V4SFmode)
11349 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11350 || GENERAL_REGISTER_P (regno))
11356 if (mode == V16SFmode)
11358 if (TARGET_SHMEDIA)
11360 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11366 return regno == FIRST_XD_REG;
11369 if (FP_REGISTER_P (regno))
11373 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11374 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11377 && (mode == DFmode || mode == DImode
11378 || mode == V2SFmode || mode == TImode)))
11379 && ((regno - FIRST_FP_REG) & 1) == 0)
11380 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11381 && ((regno - FIRST_FP_REG) & 3) == 0))
11387 if (XD_REGISTER_P (regno))
11388 return mode == DFmode;
11390 if (TARGET_REGISTER_P (regno))
11391 return (mode == DImode || mode == SImode || mode == PDImode);
11393 if (regno == PR_REG)
11394 return mode == SImode;
11396 if (regno == FPSCR_REG)
11397 return mode == PSImode;
11399 /* FIXME. This works around PR target/37633 for -O0. */
11400 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11402 unsigned int n = GET_MODE_SIZE (mode) / 8;
11404 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11405 && regno <= FIRST_GENERAL_REG + 14)
11412 /* Return the class of registers for which a mode change from FROM to TO
11415 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
11416 enum reg_class rclass)
11418 /* We want to enable the use of SUBREGs as a means to
11419 VEC_SELECT a single element of a vector. */
11420 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
11421 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
11423 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11425 if (TARGET_LITTLE_ENDIAN)
11427 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
11428 return reg_classes_intersect_p (DF_REGS, rclass);
11432 if (GET_MODE_SIZE (from) < 8)
11433 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11439 /* Return true if registers in machine mode MODE will likely be
11440 allocated to registers in small register classes. */
11443 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11445 return (! TARGET_SHMEDIA);
11448 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11449 that label is used. */
11452 sh_mark_label (rtx address, int nuses)
11454 if (GOTOFF_P (address))
11456 /* Extract the label or symbol. */
11457 address = XEXP (address, 0);
11458 if (GET_CODE (address) == PLUS)
11459 address = XEXP (address, 0);
11460 address = XVECEXP (address, 0, 0);
11462 if (GET_CODE (address) == LABEL_REF
11463 && LABEL_P (XEXP (address, 0)))
11464 LABEL_NUSES (XEXP (address, 0)) += nuses;
11467 /* Compute extra cost of moving data between one register class
11470 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11471 uses this information. Hence, the general register <-> floating point
11472 register information here is not used for SFmode. */
11475 sh_register_move_cost (enum machine_mode mode,
11476 reg_class_t srcclass, reg_class_t dstclass)
11478 if (dstclass == T_REGS || dstclass == PR_REGS)
11481 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11484 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11485 && REGCLASS_HAS_FP_REG (srcclass)
11486 && REGCLASS_HAS_FP_REG (dstclass))
11489 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11490 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11492 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11493 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11496 if ((REGCLASS_HAS_FP_REG (dstclass)
11497 && REGCLASS_HAS_GENERAL_REG (srcclass))
11498 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11499 && REGCLASS_HAS_FP_REG (srcclass)))
11500 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11501 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11503 if ((dstclass == FPUL_REGS
11504 && REGCLASS_HAS_GENERAL_REG (srcclass))
11505 || (srcclass == FPUL_REGS
11506 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11509 if ((dstclass == FPUL_REGS
11510 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11511 || (srcclass == FPUL_REGS
11512 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11515 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11516 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11519 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11521 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11523 if (sh_gettrcost >= 0)
11524 return sh_gettrcost;
11525 else if (!TARGET_PT_FIXED)
11529 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11530 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11535 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11536 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11537 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11539 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11542 static rtx emit_load_ptr (rtx, rtx);
11545 emit_load_ptr (rtx reg, rtx addr)
11547 rtx mem = gen_const_mem (ptr_mode, addr);
11549 if (Pmode != ptr_mode)
11550 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11551 return emit_move_insn (reg, mem);
11555 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11556 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11559 CUMULATIVE_ARGS cum;
11560 int structure_value_byref = 0;
11561 rtx this_rtx, this_value, sibcall, insns, funexp;
11562 tree funtype = TREE_TYPE (function);
11563 int simple_add = CONST_OK_FOR_ADD (delta);
11565 rtx scratch0, scratch1, scratch2;
11568 reload_completed = 1;
11569 epilogue_completed = 1;
11570 current_function_uses_only_leaf_regs = 1;
11572 emit_note (NOTE_INSN_PROLOGUE_END);
11574 /* Find the "this" pointer. We have such a wide range of ABIs for the
11575 SH that it's best to do this completely machine independently.
11576 "this" is passed as first argument, unless a structure return pointer
11577 comes first, in which case "this" comes second. */
11578 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11579 #ifndef PCC_STATIC_STRUCT_RETURN
11580 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11581 structure_value_byref = 1;
11582 #endif /* not PCC_STATIC_STRUCT_RETURN */
11583 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11585 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11587 sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true);
11590 = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true);
11592 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11593 static chain pointer (even if you can't have nested virtual functions
11594 right now, someone might implement them sometime), and the rest of the
11595 registers are used for argument passing, are callee-saved, or reserved. */
11596 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11597 -ffixed-reg has been used. */
11598 if (! call_used_regs[0] || fixed_regs[0])
11599 error ("r0 needs to be available as a call-clobbered register");
11600 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11603 if (call_used_regs[1] && ! fixed_regs[1])
11604 scratch1 = gen_rtx_REG (ptr_mode, 1);
11605 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11606 pointing where to return struct values. */
11607 if (call_used_regs[3] && ! fixed_regs[3])
11608 scratch2 = gen_rtx_REG (Pmode, 3);
11610 else if (TARGET_SHMEDIA)
11612 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11613 if (i != REGNO (scratch0) &&
11614 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11616 scratch1 = gen_rtx_REG (ptr_mode, i);
11619 if (scratch1 == scratch0)
11620 error ("need a second call-clobbered general purpose register");
11621 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11622 if (call_used_regs[i] && ! fixed_regs[i])
11624 scratch2 = gen_rtx_REG (Pmode, i);
11627 if (scratch2 == scratch0)
11628 error ("need a call-clobbered target register");
11631 this_value = plus_constant (this_rtx, delta);
11633 && (simple_add || scratch0 != scratch1)
11634 && strict_memory_address_p (ptr_mode, this_value))
11636 emit_load_ptr (scratch0, this_value);
11641 ; /* Do nothing. */
11642 else if (simple_add)
11643 emit_move_insn (this_rtx, this_value);
11646 emit_move_insn (scratch1, GEN_INT (delta));
11647 emit_insn (gen_add2_insn (this_rtx, scratch1));
11655 emit_load_ptr (scratch0, this_rtx);
11657 offset_addr = plus_constant (scratch0, vcall_offset);
11658 if (strict_memory_address_p (ptr_mode, offset_addr))
11659 ; /* Do nothing. */
11660 else if (! TARGET_SH5 && scratch0 != scratch1)
11662 /* scratch0 != scratch1, and we have indexed loads. Get better
11663 schedule by loading the offset into r1 and using an indexed
11664 load - then the load of r1 can issue before the load from
11665 (this_rtx + delta) finishes. */
11666 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11667 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11669 else if (CONST_OK_FOR_ADD (vcall_offset))
11671 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11672 offset_addr = scratch0;
11674 else if (scratch0 != scratch1)
11676 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11677 emit_insn (gen_add2_insn (scratch0, scratch1));
11678 offset_addr = scratch0;
11681 gcc_unreachable (); /* FIXME */
11682 emit_load_ptr (scratch0, offset_addr);
11684 if (Pmode != ptr_mode)
11685 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11686 emit_insn (gen_add2_insn (this_rtx, scratch0));
11689 /* Generate a tail call to the target function. */
11690 if (! TREE_USED (function))
11692 assemble_external (function);
11693 TREE_USED (function) = 1;
11695 funexp = XEXP (DECL_RTL (function), 0);
11696 /* If the function is overridden, so is the thunk, hence we don't
11697 need GOT addressing even if this is a public symbol. */
11699 if (TARGET_SH1 && ! flag_weak)
11700 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11703 if (TARGET_SH2 && flag_pic)
11705 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11706 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11710 if (TARGET_SHMEDIA && flag_pic)
11712 funexp = gen_sym2PIC (funexp);
11713 PUT_MODE (funexp, Pmode);
11715 emit_move_insn (scratch2, funexp);
11716 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11717 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11719 sibcall = emit_call_insn (sibcall);
11720 SIBLING_CALL_P (sibcall) = 1;
11721 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11724 /* Run just enough of rest_of_compilation to do scheduling and get
11725 the insns emitted. Note that use_thunk calls
11726 assemble_start_function and assemble_end_function. */
11728 insn_locators_alloc ();
11729 insns = get_insns ();
11735 split_all_insns_noflow ();
11739 shorten_branches (insns);
11740 final_start_function (insns, file, 1);
11741 final (insns, file, 1);
11742 final_end_function ();
11744 reload_completed = 0;
11745 epilogue_completed = 0;
11749 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11753 /* If this is not an ordinary function, the name usually comes from a
11754 string literal or an sprintf buffer. Make sure we use the same
11755 string consistently, so that cse will be able to unify address loads. */
11756 if (kind != FUNCTION_ORDINARY)
11757 name = IDENTIFIER_POINTER (get_identifier (name));
11758 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11759 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11763 case FUNCTION_ORDINARY:
11767 rtx reg = target ? target : gen_reg_rtx (Pmode);
11769 emit_insn (gen_symGOT2reg (reg, sym));
11775 /* ??? To allow cse to work, we use GOTOFF relocations.
11776 we could add combiner patterns to transform this into
11777 straight pc-relative calls with sym2PIC / bsrf when
11778 label load and function call are still 1:1 and in the
11779 same basic block during combine. */
11780 rtx reg = target ? target : gen_reg_rtx (Pmode);
11782 emit_insn (gen_symGOTOFF2reg (reg, sym));
11787 if (target && sym != target)
11789 emit_move_insn (target, sym);
11795 /* Find the number of a general purpose register in S. */
11797 scavenge_reg (HARD_REG_SET *s)
11800 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11801 if (TEST_HARD_REG_BIT (*s, r))
11807 sh_get_pr_initial_val (void)
11811 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11812 PR register on SHcompact, because it might be clobbered by the prologue.
11813 We check first if that is known to be the case. */
11814 if (TARGET_SHCOMPACT
11815 && ((crtl->args.info.call_cookie
11816 & ~ CALL_COOKIE_RET_TRAMP (1))
11817 || crtl->saves_all_registers))
11818 return gen_frame_mem (SImode, return_address_pointer_rtx);
11820 /* If we haven't finished rtl generation, there might be a nonlocal label
11821 that we haven't seen yet.
11822 ??? get_hard_reg_initial_val fails if it is called after register
11823 allocation has started, unless it has been called before for the
11824 same register. And even then, we end in trouble if we didn't use
11825 the register in the same basic block before. So call
11826 get_hard_reg_initial_val now and wrap it in an unspec if we might
11827 need to replace it. */
11828 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11829 combine can put the pseudo returned by get_hard_reg_initial_val into
11830 instructions that need a general purpose registers, which will fail to
11831 be recognized when the pseudo becomes allocated to PR. */
11833 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11835 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11840 sh_expand_t_scc (rtx operands[])
11842 enum rtx_code code = GET_CODE (operands[1]);
11843 rtx target = operands[0];
11844 rtx op0 = operands[2];
11845 rtx op1 = operands[3];
11846 rtx result = target;
11849 if (!REG_P (op0) || REGNO (op0) != T_REG
11850 || !CONST_INT_P (op1))
11852 if (!REG_P (result))
11853 result = gen_reg_rtx (SImode);
11854 val = INTVAL (op1);
11855 if ((code == EQ && val == 1) || (code == NE && val == 0))
11856 emit_insn (gen_movt (result));
11857 else if (TARGET_SH2A && ((code == EQ && val == 0)
11858 || (code == NE && val == 1)))
11859 emit_insn (gen_xorsi3_movrt (result));
11860 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11862 emit_clobber (result);
11863 emit_insn (gen_subc (result, result, result));
11864 emit_insn (gen_addsi3 (result, result, const1_rtx));
11866 else if (code == EQ || code == NE)
11867 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11870 if (result != target)
11871 emit_move_insn (target, result);
11875 /* INSN is an sfunc; return the rtx that describes the address used. */
11877 extract_sfunc_addr (rtx insn)
11879 rtx pattern, part = NULL_RTX;
11882 pattern = PATTERN (insn);
11883 len = XVECLEN (pattern, 0);
11884 for (i = 0; i < len; i++)
11886 part = XVECEXP (pattern, 0, i);
11887 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11888 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11889 return XEXP (part, 0);
11891 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11892 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11895 /* Verify that the register in use_sfunc_addr still agrees with the address
11896 used in the sfunc. This prevents fill_slots_from_thread from changing
11898 INSN is the use_sfunc_addr instruction, and REG is the register it
11901 check_use_sfunc_addr (rtx insn, rtx reg)
11903 /* Search for the sfunc. It should really come right after INSN. */
11904 while ((insn = NEXT_INSN (insn)))
11906 if (LABEL_P (insn) || JUMP_P (insn))
11908 if (! INSN_P (insn))
11911 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11912 insn = XVECEXP (PATTERN (insn), 0, 0);
11913 if (GET_CODE (PATTERN (insn)) != PARALLEL
11914 || get_attr_type (insn) != TYPE_SFUNC)
11916 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11918 gcc_unreachable ();
11921 /* This function returns a constant rtx that represents pi / 2**15 in
11922 SFmode. it's used to scale SFmode angles, in radians, to a
11923 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11924 maps to 0x10000). */
11926 static GTY(()) rtx sh_fsca_sf2int_rtx;
11929 sh_fsca_sf2int (void)
11931 if (! sh_fsca_sf2int_rtx)
11933 REAL_VALUE_TYPE rv;
11935 real_from_string (&rv, "10430.378350470453");
11936 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11939 return sh_fsca_sf2int_rtx;
11942 /* This function returns a constant rtx that represents pi / 2**15 in
11943 DFmode. it's used to scale DFmode angles, in radians, to a
11944 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11945 maps to 0x10000). */
11947 static GTY(()) rtx sh_fsca_df2int_rtx;
11950 sh_fsca_df2int (void)
11952 if (! sh_fsca_df2int_rtx)
11954 REAL_VALUE_TYPE rv;
11956 real_from_string (&rv, "10430.378350470453");
11957 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11960 return sh_fsca_df2int_rtx;
11963 /* This function returns a constant rtx that represents 2**15 / pi in
11964 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11965 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11968 static GTY(()) rtx sh_fsca_int2sf_rtx;
11971 sh_fsca_int2sf (void)
11973 if (! sh_fsca_int2sf_rtx)
11975 REAL_VALUE_TYPE rv;
11977 real_from_string (&rv, "9.587379924285257e-5");
11978 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11981 return sh_fsca_int2sf_rtx;
11984 /* Initialize the CUMULATIVE_ARGS structure. */
11987 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11989 rtx libname ATTRIBUTE_UNUSED,
11991 signed int n_named_args,
11992 enum machine_mode mode)
11994 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11995 pcum->free_single_fp_reg = 0;
11996 pcum->stack_regs = 0;
11997 pcum->byref_regs = 0;
11999 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
12001 /* XXX - Should we check TARGET_HITACHI here ??? */
12002 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
12006 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
12007 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
12008 pcum->prototype_p = prototype_p (fntype);
12009 pcum->arg_count [(int) SH_ARG_INT]
12010 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
12013 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12014 && pcum->arg_count [(int) SH_ARG_INT] == 0
12015 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
12016 ? int_size_in_bytes (TREE_TYPE (fntype))
12017 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
12018 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
12019 == FIRST_RET_REG));
12023 pcum->arg_count [(int) SH_ARG_INT] = 0;
12024 pcum->prototype_p = FALSE;
12025 if (mode != VOIDmode)
12027 pcum->call_cookie =
12028 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12029 && GET_MODE_SIZE (mode) > 4
12030 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
12032 /* If the default ABI is the Renesas ABI then all library
12033 calls must assume that the library will be using the
12034 Renesas ABI. So if the function would return its result
12035 in memory then we must force the address of this memory
12036 block onto the stack. Ideally we would like to call
12037 targetm.calls.return_in_memory() here but we do not have
12038 the TYPE or the FNDECL available so we synthesize the
12039 contents of that function as best we can. */
12041 (TARGET_DEFAULT & MASK_HITACHI)
12042 && (mode == BLKmode
12043 || (GET_MODE_SIZE (mode) > 4
12044 && !(mode == DFmode
12045 && TARGET_FPU_DOUBLE)));
12049 pcum->call_cookie = 0;
12050 pcum->force_mem = FALSE;
12055 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12056 not enter into CONST_DOUBLE for the replace.
12058 Note that copying is not done so X must not be shared unless all copies
12059 are to be modified.
12061 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12062 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12063 replacements[n*2+1] - and that we take mode changes into account.
12065 If a replacement is ambiguous, return NULL_RTX.
12067 If MODIFY is zero, don't modify any rtl in place,
12068 just return zero or nonzero for failure / success. */
12071 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
12076 /* The following prevents loops occurrence when we change MEM in
12077 CONST_DOUBLE onto the same CONST_DOUBLE. */
12078 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
12081 for (i = n_replacements - 1; i >= 0 ; i--)
12082 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
12083 return replacements[i*2+1];
12085 /* Allow this function to make replacements in EXPR_LISTs. */
12089 if (GET_CODE (x) == SUBREG)
12091 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
12092 n_replacements, modify);
12094 if (CONST_INT_P (new_rtx))
12096 x = simplify_subreg (GET_MODE (x), new_rtx,
12097 GET_MODE (SUBREG_REG (x)),
12103 SUBREG_REG (x) = new_rtx;
12107 else if (REG_P (x))
12109 unsigned regno = REGNO (x);
12110 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
12111 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12112 rtx result = NULL_RTX;
12114 for (i = n_replacements - 1; i >= 0; i--)
12116 rtx from = replacements[i*2];
12117 rtx to = replacements[i*2+1];
12118 unsigned from_regno, from_nregs, to_regno, new_regno;
12122 from_regno = REGNO (from);
12123 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
12124 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
12125 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
12127 if (regno < from_regno
12128 || regno + nregs > from_regno + nregs
12132 to_regno = REGNO (to);
12133 if (to_regno < FIRST_PSEUDO_REGISTER)
12135 new_regno = regno + to_regno - from_regno;
12136 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
12139 result = gen_rtx_REG (GET_MODE (x), new_regno);
12141 else if (GET_MODE (x) <= GET_MODE (to))
12142 result = gen_lowpart_common (GET_MODE (x), to);
12144 result = gen_lowpart_SUBREG (GET_MODE (x), to);
12147 return result ? result : x;
12149 else if (GET_CODE (x) == ZERO_EXTEND)
12151 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
12152 n_replacements, modify);
12154 if (CONST_INT_P (new_rtx))
12156 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
12157 new_rtx, GET_MODE (XEXP (x, 0)));
12162 XEXP (x, 0) = new_rtx;
12167 fmt = GET_RTX_FORMAT (GET_CODE (x));
12168 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
12174 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
12175 n_replacements, modify);
12179 XEXP (x, i) = new_rtx;
12181 else if (fmt[i] == 'E')
12182 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12184 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
12185 n_replacements, modify);
12189 XVECEXP (x, i, j) = new_rtx;
12197 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12199 enum rtx_code code = TRUNCATE;
12201 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12203 rtx inner = XEXP (x, 0);
12204 enum machine_mode inner_mode = GET_MODE (inner);
12206 if (inner_mode == mode)
12208 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12210 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12211 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12213 code = GET_CODE (x);
12217 return gen_rtx_fmt_e (code, mode, x);
12220 /* called via for_each_rtx after reload, to clean up truncates of
12221 registers that span multiple actual hard registers. */
12223 shmedia_cleanup_truncate (rtx *p, void *n_changes)
12227 if (GET_CODE (x) != TRUNCATE)
12230 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
12232 enum machine_mode reg_mode = GET_MODE (reg);
12233 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12234 subreg_lowpart_offset (DImode, reg_mode));
12235 *(int*) n_changes += 1;
12241 /* Load and store depend on the highpart of the address. However,
12242 set_attr_alternative does not give well-defined results before reload,
12243 so we must look at the rtl ourselves to see if any of the feeding
12244 registers is used in a memref. */
12246 /* Called by sh_contains_memref_p via for_each_rtx. */
12248 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12250 return (MEM_P (*loc));
12253 /* Return nonzero iff INSN contains a MEM. */
12255 sh_contains_memref_p (rtx insn)
12257 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12260 /* Return nonzero iff INSN loads a banked register. */
12262 sh_loads_bankedreg_p (rtx insn)
12264 if (GET_CODE (PATTERN (insn)) == SET)
12266 rtx op = SET_DEST (PATTERN(insn));
12267 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12274 /* FNADDR is the MEM expression from a call expander. Return an address
12275 to use in an SHmedia insn pattern. */
12277 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12281 fnaddr = XEXP (fnaddr, 0);
12282 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12283 if (flag_pic && is_sym)
12285 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12287 rtx reg = gen_reg_rtx (Pmode);
12289 /* We must not use GOTPLT for sibcalls, because PIC_REG
12290 must be restored before the PLT code gets to run. */
12292 emit_insn (gen_symGOT2reg (reg, fnaddr));
12294 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12299 fnaddr = gen_sym2PIC (fnaddr);
12300 PUT_MODE (fnaddr, Pmode);
12303 /* If ptabs might trap, make this visible to the rest of the compiler.
12304 We generally assume that symbols pertain to valid locations, but
12305 it is possible to generate invalid symbols with asm or linker tricks.
12306 In a list of functions where each returns its successor, an invalid
12307 symbol might denote an empty list. */
12308 if (!TARGET_PT_FIXED
12309 && (!is_sym || TARGET_INVALID_SYMBOLS)
12310 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12312 rtx tr = gen_reg_rtx (PDImode);
12314 emit_insn (gen_ptabs (tr, fnaddr));
12317 else if (! target_reg_operand (fnaddr, Pmode))
12318 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12322 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12325 sh_preferred_reload_class (rtx x, reg_class_t rclass)
12327 if (rclass == NO_REGS
12329 && (CONST_DOUBLE_P (x)
12330 || GET_CODE (x) == SYMBOL_REF
12331 || PIC_ADDR_P (x)))
12332 return GENERAL_REGS;
12337 /* Implement TARGET_SECONDARY_RELOAD. */
12340 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
12341 enum machine_mode mode, secondary_reload_info *sri)
12343 enum reg_class rclass = (enum reg_class) rclass_i;
12347 if (REGCLASS_HAS_FP_REG (rclass)
12348 && ! TARGET_SHMEDIA
12349 && immediate_operand ((x), mode)
12350 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12351 && mode == SFmode && fldi_ok ()))
12355 sri->icode = CODE_FOR_reload_insf__frn;
12358 sri->icode = CODE_FOR_reload_indf__frn;
12361 /* ??? If we knew that we are in the appropriate mode -
12362 single precision - we could use a reload pattern directly. */
12367 if (rclass == FPUL_REGS
12369 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12370 || REGNO (x) == T_REG))
12371 || GET_CODE (x) == PLUS))
12372 return GENERAL_REGS;
12373 if (rclass == FPUL_REGS && immediate_operand (x, mode))
12375 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
12376 return GENERAL_REGS;
12377 else if (mode == SFmode)
12379 sri->icode = CODE_FOR_reload_insi__i_fpul;
12382 if (rclass == FPSCR_REGS
12383 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12384 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
12385 return GENERAL_REGS;
12386 if (REGCLASS_HAS_FP_REG (rclass)
12388 && immediate_operand (x, mode)
12389 && x != CONST0_RTX (GET_MODE (x))
12390 && GET_MODE (x) != V4SFmode)
12391 return GENERAL_REGS;
12392 if ((mode == QImode || mode == HImode)
12393 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12395 sri->icode = ((mode == QImode)
12396 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12399 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
12400 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
12401 return TARGET_REGS;
12402 } /* end of input-only processing. */
12404 if (((REGCLASS_HAS_FP_REG (rclass)
12406 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12407 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12408 && TARGET_FMOVD))))
12409 || (REGCLASS_HAS_GENERAL_REG (rclass)
12411 && FP_REGISTER_P (REGNO (x))))
12412 && ! TARGET_SHMEDIA
12413 && (mode == SFmode || mode == SImode))
12415 if ((rclass == FPUL_REGS
12416 || (REGCLASS_HAS_FP_REG (rclass)
12417 && ! TARGET_SHMEDIA && mode == SImode))
12420 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12421 || REGNO (x) == T_REG
12422 || system_reg_operand (x, VOIDmode)))))
12424 if (rclass == FPUL_REGS)
12425 return GENERAL_REGS;
12428 if ((rclass == TARGET_REGS
12429 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
12430 && !satisfies_constraint_Csy (x)
12431 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
12432 return GENERAL_REGS;
12433 if ((rclass == MAC_REGS || rclass == PR_REGS)
12434 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
12435 && rclass != REGNO_REG_CLASS (REGNO (x)))
12436 return GENERAL_REGS;
12437 if (rclass != GENERAL_REGS && REG_P (x)
12438 && TARGET_REGISTER_P (REGNO (x)))
12439 return GENERAL_REGS;
12441 /* If here fall back to loading FPUL register through general registers.
12442 This case can happen when movsi_ie insn is picked initially to
12443 load/store the FPUL register from/to another register, and then the
12444 other register is allocated on the stack. */
12445 if (rclass == FPUL_REGS && true_regnum (x) == -1)
12446 return GENERAL_REGS;
12452 sh_conditional_register_usage (void)
12455 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
12456 if (! VALID_REGISTER_P (regno))
12457 fixed_regs[regno] = call_used_regs[regno] = 1;
12458 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
12461 call_used_regs[FIRST_GENERAL_REG + 8]
12462 = call_used_regs[FIRST_GENERAL_REG + 9] = 1;
12463 call_really_used_regs[FIRST_GENERAL_REG + 8]
12464 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1;
12466 if (TARGET_SHMEDIA)
12468 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS;
12469 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]);
12470 regno_reg_class[FIRST_FP_REG] = FP_REGS;
12474 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12475 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
12477 /* Renesas saves and restores mac registers on call. */
12478 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
12480 call_really_used_regs[MACH_REG] = 0;
12481 call_really_used_regs[MACL_REG] = 0;
12483 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0);
12484 regno <= LAST_FP_REG; regno += 2)
12485 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno);
12486 if (TARGET_SHMEDIA)
12488 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)
12489 if (! fixed_regs[regno] && call_really_used_regs[regno])
12490 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12493 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
12494 if (! fixed_regs[regno] && call_really_used_regs[regno])
12495 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
12498 /* Implement TARGET_LEGITIMATE_CONSTANT_P
12500 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
12503 sh_legitimate_constant_p (enum machine_mode mode, rtx x)
12505 return (TARGET_SHMEDIA
12506 ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
12507 || x == CONST0_RTX (mode)
12508 || !TARGET_SHMEDIA_FPU
12509 || TARGET_SHMEDIA64)
12510 : (GET_CODE (x) != CONST_DOUBLE
12511 || mode == DFmode || mode == SFmode
12512 || mode == DImode || GET_MODE (x) == VOIDmode));
12515 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
12518 sh_init_sync_libfuncs (void)
12520 init_sync_libfuncs (UNITS_PER_WORD);