1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Contributed by Steve Chamberlain (sac@cygnus.com).
22 Improved by Jim Wilson (wilson@cygnus.com). */
31 #include "insn-flags.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
38 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
39 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
41 /* ??? The pragma interrupt support will not work for SH3. */
42 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
43 output code for the next function appropriate for an interrupt handler. */
46 /* This is set by #pragma trapa, and is similar to the above, except that
47 the compiler doesn't emit code to preserve all registers. */
48 static int pragma_trapa;
50 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
51 which has a separate set of low regs for User and Supervisor modes.
52 This should only be used for the lowest level of interrupts. Higher levels
53 of interrupts must save the registers in case they themselves are
55 int pragma_nosave_low_regs;
57 /* This is used for communication between SETUP_INCOMING_VARARGS and
58 sh_expand_prologue. */
59 int current_function_anonymous_args;
61 /* Global variables from toplev.c and final.c that are used within, but
62 not declared in any header file. */
63 extern char *version_string;
64 extern int *insn_addresses;
66 /* Global variables for machine-dependent things. */
68 /* Which cpu are we scheduling for. */
69 enum processor_type sh_cpu;
71 /* Saved operands from the last compare to use when we generate an scc
77 /* Provides the class number of the smallest class containing
80 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
82 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
83 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
84 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
85 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
86 GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
87 MAC_REGS, MAC_REGS, FPUL_REGS, GENERAL_REGS,
88 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
89 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
90 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
91 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
94 /* Provide reg_class from a letter such as appears in the machine
97 enum reg_class reg_class_from_letter[] =
99 /* a */ NO_REGS, /* b */ NO_REGS, /* c */ NO_REGS, /* d */ NO_REGS,
100 /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
101 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
102 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
103 /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
104 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
105 /* y */ FPUL_REGS, /* z */ R0_REGS
108 /* Print the operand address in x to the stream. */
111 print_operand_address (stream, x)
115 switch (GET_CODE (x))
118 fprintf (stream, "@%s", reg_names[REGNO (x)]);
123 rtx base = XEXP (x, 0);
124 rtx index = XEXP (x, 1);
126 switch (GET_CODE (index))
129 fprintf (stream, "@(%d,%s)", INTVAL (index),
130 reg_names[REGNO (base)]);
134 fprintf (stream, "@(r0,%s)",
135 reg_names[MAX (REGNO (base), REGNO (index))]);
146 fprintf (stream, "@-%s", reg_names[REGNO (XEXP (x, 0))]);
150 fprintf (stream, "@%s+", reg_names[REGNO (XEXP (x, 0))]);
154 output_addr_const (stream, x);
159 /* Print operand x (an rtx) in assembler syntax to file stream
160 according to modifier code.
162 '.' print a .s if insn needs delay slot
163 '@' print rte or rts depending upon pragma interruptness
164 '#' output a nop if there is nothing to put in the delay slot
165 'O' print a constant without the #
166 'R' print the LSW of a dp value - changes if in little endian
167 'S' print the MSW of a dp value - changes if in little endian
168 'T' print the next word of a dp value - same as 'R' in big endian mode. */
171 print_operand (stream, x, code)
180 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
181 fprintf (stream, ".s");
184 if (pragma_interrupt)
185 fprintf (stream, "rte");
187 fprintf (stream, "rts");
190 /* Output a nop if there's nothing in the delay slot. */
191 if (dbr_sequence_length () == 0)
192 fprintf (stream, "\n\tnop");
195 output_addr_const (stream, x);
198 fputs (reg_names[REGNO (x) + LSW], (stream));
201 fputs (reg_names[REGNO (x) + MSW], (stream));
204 /* Next word of a double. */
205 switch (GET_CODE (x))
208 fputs (reg_names[REGNO (x) + 1], (stream));
211 print_operand_address (stream,
212 XEXP (adj_offsettable_operand (x, 4), 0));
217 switch (GET_CODE (x))
220 fputs (reg_names[REGNO (x)], (stream));
223 output_address (XEXP (x, 0));
227 output_addr_const (stream, x);
234 /* Emit code to perform a block move. Choose the best method.
236 OPERANDS[0] is the destination.
237 OPERANDS[1] is the source.
238 OPERANDS[2] is the size.
239 OPERANDS[3] is the alignment safe to use. */
242 expand_block_move (operands)
245 int align = INTVAL (operands[3]);
246 int constp = (GET_CODE (operands[2]) == CONST_INT);
247 int bytes = (constp ? INTVAL (operands[2]) : 0);
249 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
250 alignment, or if it isn't a multiple of 4 bytes, then fail. */
251 if (! constp || align < 4 || (bytes % 4 != 0))
259 rtx r4 = gen_rtx (REG, SImode, 4);
260 rtx r5 = gen_rtx (REG, SImode, 5);
262 sprintf (entry, "__movstrSI%d", bytes);
263 entry_name = get_identifier (entry);
266 = copy_to_mode_reg (Pmode,
267 gen_rtx (SYMBOL_REF, Pmode,
268 IDENTIFIER_POINTER (entry_name)));
269 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
270 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
271 emit_insn (gen_block_move_real (func_addr_rtx));
275 /* This is the same number of bytes as a memcpy call, but to a different
276 less common function name, so this will occasionally use more space. */
277 if (! TARGET_SMALLCODE)
281 int final_switch, while_loop;
282 rtx r4 = gen_rtx (REG, SImode, 4);
283 rtx r5 = gen_rtx (REG, SImode, 5);
284 rtx r6 = gen_rtx (REG, SImode, 6);
286 entry_name = get_identifier ("__movstr");
288 = copy_to_mode_reg (Pmode,
289 gen_rtx (SYMBOL_REF, Pmode,
290 IDENTIFIER_POINTER (entry_name)));
291 emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
292 emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
294 /* r6 controls the size of the move. 16 is decremented from it
295 for each 64 bytes moved. Then the negative bit left over is used
296 as an index into a list of move instructions. e.g., a 72 byte move
297 would be set up with size(r6) = 14, for one iteration through the
298 big while loop, and a switch of -2 for the last part. */
300 final_switch = 16 - ((bytes / 4) % 16);
301 while_loop = ((bytes / 4) / 16 - 1) * 16;
302 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
303 emit_insn (gen_block_lump_real (func_addr_rtx));
310 /* Prepare operands for a move define_expand; specifically, one of the
311 operands must be in a register. */
314 prepare_move_operands (operands, mode)
316 enum machine_mode mode;
318 if (! reload_in_progress && ! reload_completed)
320 /* Copy the source to a register if both operands aren't registers. */
321 if (! register_operand (operands[0], mode)
322 && ! register_operand (operands[1], mode))
323 operands[1] = copy_to_mode_reg (mode, operands[1]);
325 /* This case can happen while generating code to move the result
326 of a library call to the target. Reject `st r0,@(rX,rY)' because
327 reload will fail to find a spill register for rX, since r0 is already
328 being used for the source. */
329 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
330 && GET_CODE (operands[0]) == MEM
331 && GET_CODE (XEXP (operands[0], 0)) == PLUS
332 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
333 operands[1] = copy_to_mode_reg (mode, operands[1]);
339 /* Prepare the operands for an scc instruction; make sure that the
340 compare has been done. */
342 prepare_scc_operands (code)
345 rtx t_reg = gen_rtx (REG, SImode, T_REG);
346 enum rtx_code oldcode = code;
347 enum machine_mode mode;
349 /* First need a compare insn. */
353 /* It isn't possible to handle this case. */
370 rtx tmp = sh_compare_op0;
371 sh_compare_op0 = sh_compare_op1;
372 sh_compare_op1 = tmp;
375 mode = GET_MODE (sh_compare_op0);
376 if (mode == VOIDmode)
377 mode = GET_MODE (sh_compare_op1);
379 sh_compare_op0 = force_reg (mode, sh_compare_op0);
380 if (code != EQ && code != NE
381 && (sh_compare_op1 != const0_rtx
382 || code == GTU || code == GEU || code == LTU || code == LEU))
383 sh_compare_op1 = force_reg (mode, sh_compare_op1);
385 /* ??? This should be `mode' not `SImode' in the compare, but that would
386 require fixing the branch patterns too. */
387 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
388 gen_rtx (code, SImode, sh_compare_op0,
394 /* Called from the md file, set up the operands of a compare instruction. */
397 from_compare (operands, code)
401 if (code != EQ && code != NE)
403 enum machine_mode mode = GET_MODE (sh_compare_op0);
404 if (mode == VOIDmode)
405 mode = GET_MODE (sh_compare_op1);
407 /* Force args into regs, since we can't use constants here. */
408 sh_compare_op0 = force_reg (mode, sh_compare_op0);
409 if (sh_compare_op1 != const0_rtx
410 || code == GTU || code == GEU || code == LTU || code == LEU)
411 sh_compare_op1 = force_reg (mode, sh_compare_op1);
413 operands[1] = sh_compare_op0;
414 operands[2] = sh_compare_op1;
417 /* Functions to output assembly code. */
419 /* Return a sequence of instructions to perform DI or DF move.
421 Since the SH cannot move a DI or DF in one instruction, we have
422 to take care when we see overlapping source and dest registers. */
425 output_movedouble (insn, operands, mode)
428 enum machine_mode mode;
430 rtx dst = operands[0];
431 rtx src = operands[1];
433 if (GET_CODE (dst) == MEM
434 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
435 return "mov.l %T1,%0\n\tmov.l %1,%0";
437 if (register_operand (dst, mode)
438 && register_operand (src, mode))
440 if (REGNO (src) == MACH_REG)
441 return "sts mach,%S0\n\tsts macl,%R0";
443 /* When mov.d r1,r2 do r2->r3 then r1->r2;
444 when mov.d r1,r0 do r1->r0 then r2->r1. */
446 if (REGNO (src) + 1 == REGNO (dst))
447 return "mov %T1,%T0\n\tmov %1,%0";
449 return "mov %1,%0\n\tmov %T1,%T0";
451 else if (GET_CODE (src) == CONST_INT)
453 if (INTVAL (src) < 0)
454 output_asm_insn ("mov #-1,%S0", operands);
456 output_asm_insn ("mov #0,%S0", operands);
460 else if (GET_CODE (src) == MEM)
463 int dreg = REGNO (dst);
464 rtx inside = XEXP (src, 0);
466 if (GET_CODE (inside) == REG)
467 ptrreg = REGNO (inside);
468 else if (GET_CODE (inside) == SUBREG)
469 ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
470 else if (GET_CODE (inside) == PLUS)
472 ptrreg = REGNO (XEXP (inside, 0));
473 /* ??? A r0+REG address shouldn't be possible here, because it isn't
474 an offsettable address. Unfortunately, offsettable addresses use
475 QImode to check the offset, and a QImode offsettable address
476 requires r0 for the other operand, which is not currently
477 supported, so we can't use the 'o' constraint.
478 Thus we must check for and handle r0+REG addresses here.
479 We punt for now, since this is likely very rare. */
480 if (GET_CODE (XEXP (inside, 1)) == REG)
483 else if (GET_CODE (inside) == LABEL_REF)
484 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
485 else if (GET_CODE (inside) == POST_INC)
486 return "mov.l %1,%0\n\tmov.l %1,%T0";
490 /* Work out the safe way to copy. Copy into the second half first. */
492 return "mov.l %T1,%T0\n\tmov.l %1,%0";
495 return "mov.l %1,%0\n\tmov.l %T1,%T0";
498 /* Print an instruction which would have gone into a delay slot after
499 another instruction, but couldn't because the other instruction expanded
500 into a sequence where putting the slot insn at the end wouldn't work. */
506 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
508 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
511 /* We can't tell if we need a register as a scratch for the jump
512 until after branch shortening, and then it's too late to allocate a
513 register the 'proper' way. These instruction sequences are rare
514 anyway, so to avoid always using a reg up from our limited set, we'll
515 grab one when we need one on output. */
517 /* ??? Should fix compiler so that using a clobber scratch in jump
518 instructions works, and then this will be unnecessary. */
521 output_far_jump (insn, op)
525 rtx thislab = gen_label_rtx ();
527 /* Output the delay slot insn first if any. */
528 if (dbr_sequence_length ())
529 print_slot (final_sequence);
531 output_asm_insn ("mov.l r13,@-r15", 0);
532 output_asm_insn ("mov.l %O0,r13", &thislab);
533 output_asm_insn ("jmp @r13", 0);
534 output_asm_insn ("mov.l @r15+,r13", 0);
535 output_asm_insn (".align 2", 0);
536 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (thislab));
537 output_asm_insn (".long %O0", &op);
541 /* Local label counter, used for constants in the pool and inside
546 /* Output code for ordinary branches. */
549 output_branch (logic, insn, operands)
555 int length = get_attr_length (insn);
558 /* Undo the effects of ADJUST_INSN_LENGTH, so that we get the real
559 length. If NEXT_INSN (PREV_INSN (insn)) != insn, then the insn
560 is inside a sequence, and ADJUST_INSN_LENGTH was not called on
562 if (PREV_INSN (insn) == NULL
563 || NEXT_INSN (PREV_INSN (insn)) == insn)
565 adjusted_length = length;
566 ADJUST_INSN_LENGTH (insn, adjusted_length);
567 length -= (adjusted_length - length);
573 /* A branch with an unfilled delay slot. */
575 /* Simple branch in range -252..+258 bytes */
576 return logic ? "bt%. %l0" : "bf%. %l0";
579 /* A branch with an unfilled delay slot. */
581 /* Branch in range -4092..+4098 bytes. */
583 /* The call to print_slot will clobber the operands. */
584 rtx op0 = operands[0];
586 /* If the instruction in the delay slot is annulled (true), then
587 there is no delay slot where we can put it now. The only safe
588 place for it is after the label. */
592 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
593 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
595 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
596 print_slot (final_sequence);
599 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
601 output_asm_insn ("bra %l0", &op0);
602 fprintf (asm_out_file, "\tnop\n");
603 fprintf (asm_out_file, "LF%d:\n", label);
606 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
607 print_slot (final_sequence);
612 /* A branch with an unfilled delay slot. */
614 /* Branches a long way away. */
616 /* The call to print_slot will clobber the operands. */
617 rtx op0 = operands[0];
619 /* If the instruction in the delay slot is annulled (true), then
620 there is no delay slot where we can put it now. The only safe
621 place for it is after the label. */
625 fprintf (asm_out_file, "\tb%c%s\tLF%d\n", logic ? 'f' : 't',
626 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
628 if (! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
629 print_slot (final_sequence);
632 fprintf (asm_out_file, "\tb%c\tLF%d\n", logic ? 'f' : 't', label);
634 output_far_jump (insn, op0);
635 fprintf (asm_out_file, "LF%d:\n", label);
638 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
639 print_slot (final_sequence);
647 /* Output to FILE the start of the assembler file. */
650 output_file_start (file)
655 output_file_directive (file, main_input_filename);
657 /* Switch to the data section so that the coffsem symbol and the
658 gcc2_compiled. symbol aren't in the text section. */
661 if (TARGET_LITTLE_ENDIAN)
662 fprintf (file, "\t.little\n");
665 /* Actual number of instructions used to make a shift by N. */
666 static char ashiftrt_insns[] =
667 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
669 /* Left shift and logical right shift are the same. */
670 static char shift_insns[] =
671 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
673 /* Individual shift amounts needed to get the above length sequences.
674 One bit right shifts clobber the T bit, so when possible, put one bit
675 shifts in the middle of the sequence, so the ends are eligible for
676 branch delay slots. */
677 static short shift_amounts[32][5] = {
678 {0}, {1}, {2}, {2, 1},
679 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
680 {8}, {8, 1}, {8, 2}, {8, 1, 2},
681 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
682 {16}, {16, 1}, {16, 2}, {16, 1, 2},
683 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
684 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
685 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
687 /* Likewise, but for shift amounts < 16, up to three highmost bits
688 might be clobbered. This is typically used when combined with some
689 kind of sign or zero extension. */
691 static char ext_shift_insns[] =
692 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
694 static short ext_shift_amounts[32][4] = {
695 {0}, {1}, {2}, {2, 1},
696 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
697 {8}, {8, 1}, {8, 2}, {8, 1, 2},
698 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
699 {16}, {16, 1}, {16, 2}, {16, 1, 2},
700 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
701 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
702 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
704 /* Assuming we have a value that has been sign-extended by at least one bit,
705 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
706 to shift it by N without data loss, and quicker than by other means? */
707 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
709 /* This is used in length attributes in sh.md to help compute the length
710 of arbitrary constant shift instructions. */
713 shift_insns_rtx (insn)
716 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
717 int shift_count = INTVAL (XEXP (set_src, 1));
718 enum rtx_code shift_code = GET_CODE (set_src);
723 return ashiftrt_insns[shift_count];
726 return shift_insns[shift_count];
732 /* Return the cost of a shift. */
738 int value = INTVAL (XEXP (x, 1));
740 /* If shift by a non constant, then this will be expensive. */
741 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
745 /* If not an sh3 then we don't even have an instruction for it. */
749 /* Otherwise, return the true cost in instructions. */
750 if (GET_CODE (x) == ASHIFTRT)
752 int cost = ashiftrt_insns[value];
753 /* If SH3, then we put the constant in a reg and use shad. */
754 if (TARGET_SH3 && cost > 3)
759 return shift_insns[value];
762 /* Return the cost of an AND operation. */
770 /* Anding with a register is a single cycle and instruction. */
771 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
774 i = INTVAL (XEXP (x, 1));
775 /* These constants are single cycle extu.[bw] instructions. */
776 if (i == 0xff || i == 0xffff)
778 /* Constants that can be used in an and immediate instruction is a single
779 cycle, but this requires r0, so make it a little more expensive. */
780 if (CONST_OK_FOR_L (i))
782 /* Constants that can be loaded with a mov immediate and an and.
783 This case is probably unnecessary. */
784 if (CONST_OK_FOR_I (i))
786 /* Any other constants requires a 2 cycle pc-relative load plus an and.
787 This case is probably unnecessary. */
791 /* Return the cost of a multiply. */
798 /* We have a mul insn, so we can never take more than the mul and the
799 read of the mac reg, but count more because of the latency and extra
801 if (TARGET_SMALLCODE)
806 /* If we're aiming at small code, then just count the number of
807 insns in a multiply call sequence. */
808 if (TARGET_SMALLCODE)
811 /* Otherwise count all the insns in the routine we'd be calling too. */
815 /* Code to expand a shift. */
818 gen_ashift (type, n, reg)
823 /* Negative values here come from the shift_amounts array. */
836 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
840 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
842 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
845 emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
850 /* Same for HImode */
853 gen_ashift_hi (type, n, reg)
858 /* Negative values here come from the shift_amounts array. */
871 emit_insn (gen_ashrhi3_k (reg, reg, GEN_INT (n)));
875 emit_insn (gen_lshrhi3_m (reg, reg, GEN_INT (n)));
877 emit_insn (gen_lshrhi3_k (reg, reg, GEN_INT (n)));
880 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
885 /* Output RTL to split a constant shift into its component SH constant
886 shift instructions. */
889 gen_shifty_op (code, operands)
893 int value = INTVAL (operands[2]);
896 /* Truncate the shift count in case it is out of bounds. */
897 value = value & 0x1f;
901 if (code == LSHIFTRT)
903 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
904 emit_insn (gen_movt (operands[0]));
907 else if (code == ASHIFT)
909 /* There is a two instruction sequence for 31 bit left shifts,
910 but it requires r0. */
911 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
913 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
914 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
921 /* This can happen when not optimizing. We must output something here
922 to prevent the compiler from aborting in final.c after the try_split
924 emit_insn (gen_nop ());
928 max = shift_insns[value];
929 for (i = 0; i < max; i++)
930 gen_ashift (code, shift_amounts[value][i], operands[0]);
933 /* Same as above, but optimized for values where the topmost bits don't
937 gen_shifty_hi_op (code, operands)
941 int value = INTVAL (operands[2]);
945 /* This operation is used by and_shl for SImode values with a few
946 high bits known to be cleared. */
950 emit_insn (gen_nop ());
954 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
957 max = ext_shift_insns[value];
958 for (i = 0; i < max; i++)
959 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
962 /* When shifting right, emit the shifts in reverse order, so that
963 solitary negative values come first. */
964 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
965 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
968 /* Output RTL for an arithmetic right shift. */
970 /* ??? Rewrite to use super-optimizer sequences. */
973 expand_ashiftrt (operands)
983 if (GET_CODE (operands[2]) != CONST_INT)
985 rtx count = copy_to_mode_reg (SImode, operands[2]);
986 emit_insn (gen_negsi2 (count, count));
987 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
990 else if (ashiftrt_insns[INTVAL (operands[2])] > 3)
992 rtx count = force_reg (SImode, GEN_INT (- INTVAL (operands[2])));
993 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
997 if (GET_CODE (operands[2]) != CONST_INT)
1000 value = INTVAL (operands[2]);
1004 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1007 else if (value >= 16 && value <= 19)
1009 wrk = gen_reg_rtx (SImode);
1010 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1013 gen_ashift (ASHIFTRT, 1, wrk);
1014 emit_move_insn (operands[0], wrk);
1017 /* Expand a short sequence inline, longer call a magic routine. */
1018 else if (value <= 5)
1020 wrk = gen_reg_rtx (SImode);
1021 emit_move_insn (wrk, operands[1]);
1023 gen_ashift (ASHIFTRT, 1, wrk);
1024 emit_move_insn (operands[0], wrk);
1028 wrk = gen_reg_rtx (Pmode);
1030 /* Load the value into an arg reg and call a helper. */
1031 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
1032 sprintf (func, "__ashiftrt_r4_%d", value);
1033 func_name = get_identifier (func);
1034 emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
1035 IDENTIFIER_POINTER (func_name)));
1036 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1037 emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
1041 /* Try to find a good way to implement the combiner pattern
1042 [(set (match_operand:SI 0 "register_operand" "r")
1043 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1044 (match_operand:SI 2 "const_int_operand" "n"))
1045 (match_operand:SI 3 "const_int_operand" "n"))) .
1046 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1047 return 0 for simple right / left or left/right shift combination.
1048 return 1 for a combination of shifts with zero_extend.
1049 return 2 for a combination of shifts with an AND that needs r0.
1050 return 3 for a combination of shifts with an AND that needs an extra
1051 scratch register, when the three highmost bits of the AND mask are clear.
1052 return 4 for a combination of shifts with an AND that needs an extra
1053 scratch register, when any of the three highmost bits of the AND mask
1055 If ATTRP is set, store an initial right shift width in ATTRP[0],
1056 and the instruction length in ATTRP[1] . These values are not valid
1058 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1059 shift_amounts for the last shift value that is to be used before the
1062 shl_and_kind (left_rtx, mask_rtx, attrp)
1063 rtx left_rtx, mask_rtx;
1066 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1067 int left = INTVAL (left_rtx), right;
1069 int cost, best_cost = 10000;
1070 int best_right = 0, best_len = 0;
1074 if (left < 0 || left > 31)
1076 if (GET_CODE (mask_rtx) == CONST_INT)
1077 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1079 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1080 /* Can this be expressed as a right shift / left shift pair ? */
1081 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1082 right = exact_log2 (lsb);
1083 mask2 = ~(mask + lsb - 1);
1084 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1085 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1087 best_cost = shift_insns[right] + shift_insns[right + left];
1088 /* mask has no trailing zeroes <==> ! right */
1089 else if (! right && mask2 == ~(lsb2 - 1))
1091 int late_right = exact_log2 (lsb2);
1092 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1094 /* Try to use zero extend */
1095 if (mask2 == ~(lsb2 - 1))
1099 for (width = 8; width <= 16; width += 8)
1101 /* Can we zero-extend right away? */
1102 if (lsb2 == (HOST_WIDE_INT)1 << width)
1105 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1106 if (cost < best_cost)
1117 /* ??? Could try to put zero extend into initial right shift,
1118 or even shift a bit left before the right shift. */
1119 /* Determine value of first part of left shift, to get to the
1120 zero extend cut-off point. */
1121 first = width - exact_log2 (lsb2) + right;
1122 if (first >= 0 && right + left - first >= 0)
1124 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1125 + ext_shift_insns[right + left - first];
1126 if (cost < best_cost)
1138 /* Try to use r0 AND pattern */
1139 for (i = 0; i <= 2; i++)
1143 if (! CONST_OK_FOR_L (mask >> i))
1145 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1146 if (cost < best_cost)
1151 best_len = cost - 1;
1154 /* Try to use a scratch register to hold the AND operand. */
1155 can_ext = ((mask << left) & 0xe0000000) == 0;
1156 for (i = 0; i <= 2; i++)
1160 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1161 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1162 if (cost < best_cost)
1167 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1173 attrp[0] = best_right;
1174 attrp[1] = best_len;
1179 /* This is used in length attributes of the unnamed instructions
1180 corresponding to shl_and_kind return values of 1 and 2. */
1182 shl_and_length (insn)
1185 rtx set_src, left_rtx, mask_rtx;
1188 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1189 left_rtx = XEXP (XEXP (set_src, 0), 1);
1190 mask_rtx = XEXP (set_src, 1);
1191 shl_and_kind (left_rtx, mask_rtx, attributes);
1192 return attributes[1];
1195 /* This is used in length attribute of the and_shl_scratch instruction. */
1198 shl_and_scr_length (insn)
1201 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1202 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1203 rtx op = XEXP (set_src, 0);
1204 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1205 op = XEXP (XEXP (op, 0), 0);
1206 return len + shift_insns[INTVAL (XEXP (op, 1))];
1209 /* Generating rtl? */
1210 extern int rtx_equal_function_value_matters;
1212 /* Generate rtl for instructions for which shl_and_kind advised a particular
1213 method of generating them, i.e. returned zero. */
1216 gen_shl_and (dest, left_rtx, mask_rtx, source)
1217 rtx dest, left_rtx, mask_rtx, source;
1220 unsigned HOST_WIDE_INT mask;
1221 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1222 int right, total_shift;
1223 int (*shift_gen_fun) PROTO((int, rtx*)) = gen_shifty_hi_op;
1225 right = attributes[0];
1226 total_shift = INTVAL (left_rtx) + right;
1227 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1234 int first = attributes[2];
1239 emit_insn ((mask << right) == 0xff
1240 ? gen_zero_extendqisi2(dest,
1241 gen_lowpart (QImode, source))
1242 : gen_zero_extendhisi2(dest,
1243 gen_lowpart (HImode, source)));
1247 emit_insn (gen_movsi (dest, source));
1251 operands[2] = GEN_INT (right);
1252 gen_shifty_hi_op (LSHIFTRT, operands);
1256 operands[2] = GEN_INT (first);
1257 gen_shifty_hi_op (ASHIFT, operands);
1258 total_shift -= first;
1262 emit_insn (mask == 0xff
1263 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1264 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1265 if (total_shift > 0)
1267 operands[2] = GEN_INT (total_shift);
1268 gen_shifty_hi_op (ASHIFT, operands);
1273 shift_gen_fun = gen_shifty_op;
1276 /* If the topmost bit that matters is set, set the topmost bits
1277 that don't matter. This way, we might be able to get a shorter
1279 if (mask & ((HOST_WIDE_INT)1 << 31 - total_shift))
1280 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1281 /* Don't expand fine-grained when combining, because that will
1282 make the pattern fail. */
1283 if (rtx_equal_function_value_matters
1284 || reload_in_progress || reload_completed)
1290 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1293 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1298 operands[2] = GEN_INT (total_shift);
1299 shift_gen_fun (ASHIFT, operands);
1306 if (kind != 4 && total_shift < 16)
1308 neg = -ext_shift_amounts[total_shift][1];
1310 neg -= ext_shift_amounts[total_shift][2];
1314 emit_insn (gen_and_shl_scratch (dest, source,
1317 GEN_INT (total_shift + neg),
1319 emit_insn (gen_movsi (dest, dest));
1326 /* Try to find a good way to implement the combiner pattern
1327 [(set (match_operand:SI 0 "register_operand" "=r")
1328 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1329 (match_operand:SI 2 "const_int_operand" "n")
1330 (match_operand:SI 3 "const_int_operand" "n")
1332 (clobber (reg:SI 18))]
1333 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1334 return 0 for simple left / right shift combination.
1335 return 1 for left shift / 8 bit sign extend / left shift.
1336 return 2 for left shift / 16 bit sign extend / left shift.
1337 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1338 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1339 return 5 for left shift / 16 bit sign extend / right shift
1340 return 6 for < 8 bit sign extend / left shift.
1341 return 7 for < 8 bit sign extend / left shift / single right shift.
1342 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1345 shl_sext_kind (left_rtx, size_rtx, costp)
1346 rtx left_rtx, size_rtx;
1349 int left, size, insize, ext;
1350 int cost, best_cost;
1353 left = INTVAL (left_rtx);
1354 size = INTVAL (size_rtx);
1355 insize = size - left;
1358 /* Default to left / right shift. */
1360 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
1363 /* 16 bit shift / sign extend / 16 bit shift */
1364 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
1365 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1366 below, by alternative 3 or something even better. */
1367 if (cost < best_cost)
1373 /* Try a plain sign extend between two shifts. */
1374 for (ext = 16; ext >= insize; ext -= 8)
1378 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
1379 if (cost < best_cost)
1385 /* Check if we can do a sloppy shift with a final signed shift
1386 restoring the sign. */
1387 if (EXT_SHIFT_SIGNED (size - ext))
1388 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
1389 /* If not, maybe it's still cheaper to do the second shift sloppy,
1390 and do a final sign extend? */
1391 else if (size <= 16)
1392 cost = ext_shift_insns[ext - insize] + 1
1393 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
1396 if (cost < best_cost)
1398 kind = ext / 8U + 2;
1402 /* Check if we can sign extend in r0 */
1405 cost = 3 + shift_insns[left];
1406 if (cost < best_cost)
1411 /* Try the same with a final signed shift. */
1414 cost = 3 + ext_shift_insns[left + 1] + 1;
1415 if (cost < best_cost)
1424 /* Try to use a dynamic shift. */
1425 cost = shift_insns[32 - insize] + 3;
1426 if (cost < best_cost)
1437 /* Function to be used in the length attribute of the instructions
1438 implementing this pattern. */
1441 shl_sext_length (insn)
1444 rtx set_src, left_rtx, size_rtx;
1447 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1448 left_rtx = XEXP (XEXP (set_src, 0), 1);
1449 size_rtx = XEXP (set_src, 1);
1450 shl_sext_kind (left_rtx, size_rtx, &cost);
1454 /* Generate rtl for this pattern */
1457 gen_shl_sext (dest, left_rtx, size_rtx, source)
1458 rtx dest, left_rtx, size_rtx, source;
1461 int left, size, insize, cost;
1464 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
1465 left = INTVAL (left_rtx);
1466 size = INTVAL (size_rtx);
1467 insize = size - left;
1475 int ext = kind & 1 ? 8 : 16;
1476 int shift2 = size - ext;
1478 /* Don't expand fine-grained when combining, because that will
1479 make the pattern fail. */
1480 if (! rtx_equal_function_value_matters
1481 && ! reload_in_progress && ! reload_completed)
1483 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1484 emit_insn (gen_movsi (dest, source));
1488 emit_insn (gen_movsi (dest, source));
1492 operands[2] = GEN_INT (ext - insize);
1493 gen_shifty_hi_op (ASHIFT, operands);
1496 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
1497 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
1502 operands[2] = GEN_INT (shift2);
1503 gen_shifty_op (ASHIFT, operands);
1510 if (EXT_SHIFT_SIGNED (shift2))
1512 operands[2] = GEN_INT (shift2 + 1);
1513 gen_shifty_op (ASHIFT, operands);
1514 operands[2] = GEN_INT (1);
1515 gen_shifty_op (ASHIFTRT, operands);
1518 operands[2] = GEN_INT (shift2);
1519 gen_shifty_hi_op (ASHIFT, operands);
1523 operands[2] = GEN_INT (-shift2);
1524 gen_shifty_hi_op (LSHIFTRT, operands);
1526 emit_insn (size <= 8
1527 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
1528 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
1535 emit_insn (gen_shl_sext_ext (dest, source, GEN_INT (16 - insize),
1537 /* Don't use gen_ashrsi3 because it generates new pseudos. */
1539 gen_ashift (ASHIFTRT, 1, dest);
1544 /* Don't expand fine-grained when combining, because that will
1545 make the pattern fail. */
1546 if (! rtx_equal_function_value_matters
1547 && ! reload_in_progress && ! reload_completed)
1549 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
1550 emit_insn (gen_movsi (dest, source));
1553 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
1554 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
1555 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
1557 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
1558 gen_shifty_op (ASHIFT, operands);
1560 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
1568 /* The SH cannot load a large constant into a register, constants have to
1569 come from a pc relative load. The reference of a pc relative load
1570 instruction must be less than 1k infront of the instruction. This
1571 means that we often have to dump a constant inside a function, and
1572 generate code to branch around it.
1574 It is important to minimize this, since the branches will slow things
1575 down and make things bigger.
1577 Worst case code looks like:
1595 We fix this by performing a scan before scheduling, which notices which
1596 instructions need to have their operands fetched from the constant table
1597 and builds the table.
1601 scan, find an instruction which needs a pcrel move. Look forward, find the
1602 last barrier which is within MAX_COUNT bytes of the requirement.
1603 If there isn't one, make one. Process all the instructions between
1604 the find and the barrier.
1606 In the above example, we can tell that L3 is within 1k of L1, so
1607 the first move can be shrunk from the 3 insn+constant sequence into
1608 just 1 insn, and the constant moved to L3 to make:
1619 Then the second move becomes the target for the shortening process. */
1623 rtx value; /* Value in table. */
1624 rtx label; /* Label of value. */
1625 enum machine_mode mode; /* Mode of value. */
1628 /* The maximum number of constants that can fit into one pool, since
1629 the pc relative range is 0...1020 bytes and constants are at least 4
1632 #define MAX_POOL_SIZE (1020/4)
1633 static pool_node pool_vector[MAX_POOL_SIZE];
1634 static int pool_size;
1636 /* ??? If we need a constant in HImode which is the truncated value of a
1637 constant we need in SImode, we could combine the two entries thus saving
1638 two bytes. Is this common enough to be worth the effort of implementing
1641 /* ??? This stuff should be done at the same time that we shorten branches.
1642 As it is now, we must assume that all branches are the maximum size, and
1643 this causes us to almost always output constant pools sooner than
1646 /* Add a constant to the pool and return its label. */
1649 add_constant (x, mode)
1651 enum machine_mode mode;
1656 /* First see if we've already got it. */
1657 for (i = 0; i < pool_size; i++)
1659 if (x->code == pool_vector[i].value->code
1660 && mode == pool_vector[i].mode)
1662 if (x->code == CODE_LABEL)
1664 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
1667 if (rtx_equal_p (x, pool_vector[i].value))
1668 return pool_vector[i].label;
1672 /* Need a new one. */
1673 pool_vector[pool_size].value = x;
1674 lab = gen_label_rtx ();
1675 pool_vector[pool_size].mode = mode;
1676 pool_vector[pool_size].label = lab;
1681 /* Output the literal table. */
1690 /* Do two passes, first time dump out the HI sized constants. */
1692 for (i = 0; i < pool_size; i++)
1694 pool_node *p = &pool_vector[i];
1696 if (p->mode == HImode)
1700 scan = emit_insn_after (gen_align_2 (), scan);
1703 scan = emit_label_after (p->label, scan);
1704 scan = emit_insn_after (gen_consttable_2 (p->value), scan);
1710 for (i = 0; i < pool_size; i++)
1712 pool_node *p = &pool_vector[i];
1723 scan = emit_label_after (gen_label_rtx (), scan);
1724 scan = emit_insn_after (gen_align_4 (), scan);
1726 scan = emit_label_after (p->label, scan);
1727 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
1734 scan = emit_label_after (gen_label_rtx (), scan);
1735 scan = emit_insn_after (gen_align_4 (), scan);
1737 scan = emit_label_after (p->label, scan);
1738 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
1746 scan = emit_insn_after (gen_consttable_end (), scan);
1747 scan = emit_barrier_after (scan);
1751 /* Return non-zero if constant would be an ok source for a
1752 mov.w instead of a mov.l. */
1758 return (GET_CODE (src) == CONST_INT
1759 && INTVAL (src) >= -32768
1760 && INTVAL (src) <= 32767);
1763 /* Non-zero if the insn is a move instruction which needs to be fixed. */
1765 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
1766 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
1767 need to fix it if the input value is CONST_OK_FOR_I. */
1773 if (GET_CODE (insn) == INSN)
1775 rtx pat = PATTERN (insn);
1776 if (GET_CODE (pat) == PARALLEL)
1777 pat = XVECEXP (pat, 0, 0);
1778 if (GET_CODE (pat) == SET
1779 /* We can load any 8 bit value if we don't care what the high
1780 order bits end up as. */
1781 && GET_MODE (SET_DEST (pat)) != QImode
1782 && CONSTANT_P (SET_SRC (pat))
1783 && ! (GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
1784 && (fp_zero_operand (SET_SRC (pat))
1785 || fp_one_operand (SET_SRC (pat)))
1786 && GET_CODE (SET_DEST (pat)) == REG
1787 && REGNO (SET_DEST (pat)) >= FIRST_FP_REG
1788 && REGNO (SET_DEST (pat)) <= LAST_FP_REG)
1789 && (GET_CODE (SET_SRC (pat)) != CONST_INT
1790 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
1797 /* Find the last barrier from insn FROM which is close enough to hold the
1798 constant pool. If we can't find one, then create one near the end of
1801 /* ??? It would be good to put constant pool tables between a case jump and
1802 the jump table. This fails for two reasons. First, there is no
1803 barrier after the case jump. This is a bug in the casesi pattern.
1804 Second, inserting the table here may break the mova instruction that
1805 loads the jump table address, by moving the jump table too far away.
1806 We fix that problem by never outputting the constant pool between a mova
1817 rtx found_barrier = 0;
1822 /* For HImode: range is 510, add 4 because pc counts from address of
1823 second instruction after this one, subtract 2 for the jump instruction
1824 that we may need to emit before the table, subtract 2 for the instruction
1825 that fills the jump delay slot (in very rare cases, reorg will take an
1826 instruction from after the constant pool or will leave the delay slot
1827 empty). This gives 510.
1828 For SImode: range is 1020, add 4 because pc counts from address of
1829 second instruction after this one, subtract 2 in case pc is 2 byte
1830 aligned, subtract 2 for the jump instruction that we may need to emit
1831 before the table, subtract 2 for the instruction that fills the jump
1832 delay slot. This gives 1018. */
1834 /* If not optimizing, then it is possible that the jump instruction we add
1835 won't be shortened, and thus will have a length of 14 instead of 2.
1836 We must adjust the limits downwards to account for this, giving a limit
1837 of 1008 for SImode and 500 for HImode. */
1850 /* If not optimizing for space, then the constant pool will be
1851 aligned to a 4 to 16 byte boundary. We must make room for that
1852 alignment that by reducing the limits.
1853 ??? It would be better to not align the constant pool, but
1854 ASM_OUTPUT_ALIGN_CODE does not make any provision for basing the
1855 alignment on the instruction. */
1857 if (! TARGET_SMALLCODE)
1859 if (TARGET_SH3 || TARGET_SH3E)
1871 while (from && count_si < si_limit && count_hi < hi_limit)
1873 int inc = get_attr_length (from);
1875 if (GET_CODE (from) == BARRIER)
1876 found_barrier = from;
1878 if (broken_move (from))
1880 rtx pat = PATTERN (from);
1881 rtx src = SET_SRC (pat);
1882 rtx dst = SET_DEST (pat);
1883 enum machine_mode mode = GET_MODE (dst);
1885 /* We must explicitly check the mode, because sometimes the
1886 front end will generate code to load unsigned constants into
1887 HImode targets without properly sign extending them. */
1888 if (mode == HImode || (mode == SImode && hi_const (src)))
1891 /* We put the short constants before the long constants, so
1892 we must count the length of short constants in the range
1893 for the long constants. */
1894 /* ??? This isn't optimal, but is easy to do. */
1902 if (GET_CODE (from) == INSN
1903 && GET_CODE (PATTERN (from)) == SET
1904 && GET_CODE (SET_SRC (PATTERN (from))) == UNSPEC
1905 && XINT (SET_SRC (PATTERN (from)), 1) == 1)
1907 else if (GET_CODE (from) == JUMP_INSN
1908 && (GET_CODE (PATTERN (from)) == ADDR_VEC
1909 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
1916 from = NEXT_INSN (from);
1919 /* Insert the constant pool table before the mova instruction, to prevent
1920 the mova label reference from going out of range. */
1924 if (! found_barrier)
1926 /* We didn't find a barrier in time to dump our stuff,
1927 so we'll make one. */
1928 rtx label = gen_label_rtx ();
1930 /* If we exceeded the range, then we must back up over the last
1931 instruction we looked at. Otherwise, we just need to undo the
1932 NEXT_INSN at the end of the loop. */
1933 if (count_hi > hi_limit || count_si > si_limit)
1934 from = PREV_INSN (PREV_INSN (from));
1936 from = PREV_INSN (from);
1938 /* Walk back to be just before any jump or label.
1939 Putting it before a label reduces the number of times the branch
1940 around the constant pool table will be hit. Putting it before
1941 a jump makes it more likely that the bra delay slot will be
1943 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
1944 || GET_CODE (from) == CODE_LABEL)
1945 from = PREV_INSN (from);
1947 from = emit_jump_insn_after (gen_jump (label), from);
1948 JUMP_LABEL (from) = label;
1949 LABEL_NUSES (label) = 1;
1950 found_barrier = emit_barrier_after (from);
1951 emit_label_after (label, found_barrier);
1954 return found_barrier;
1957 /* If the instruction INSN is implemented by a special function, and we can
1958 positively find the register that is used to call the sfunc, and this
1959 register is not used anywhere else in this instruction - except as the
1960 destination of a set, return this register; else, return 0. */
1962 sfunc_uses_reg (insn)
1966 rtx pattern, part, reg_part, reg;
1968 if (GET_CODE (insn) != INSN)
1970 pattern = PATTERN (insn);
1971 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
1974 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
1976 part = XVECEXP (pattern, 0, i);
1977 if (GET_CODE (part) == USE)
1982 reg = XEXP (reg_part, 0);
1983 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
1985 part = XVECEXP (pattern, 0, i);
1986 if (part == reg_part)
1988 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
1989 && GET_CODE (SET_DEST (part)) == REG)
1990 ? SET_SRC (part) : part)))
1996 /* See if the only way in which INSN uses REG is by calling it, or by
1997 setting it while calling it. Set *SET to a SET rtx if the register
2001 noncall_uses_reg (reg, insn, set)
2010 reg2 = sfunc_uses_reg (insn);
2011 if (reg2 && REGNO (reg2) == REGNO (reg))
2013 pattern = single_set (insn);
2015 && GET_CODE (SET_DEST (pattern)) == REG
2016 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2020 if (GET_CODE (insn) != CALL_INSN)
2022 /* We don't use rtx_equal_p because we don't care if the mode is
2024 pattern = single_set (insn);
2026 && GET_CODE (SET_DEST (pattern)) == REG
2027 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2033 par = PATTERN (insn);
2034 if (GET_CODE (par) == PARALLEL)
2035 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2037 part = XVECEXP (par, 0, i);
2038 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2041 return reg_mentioned_p (reg, SET_SRC (pattern));
2047 pattern = PATTERN (insn);
2049 if (GET_CODE (pattern) == PARALLEL)
2053 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2054 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2056 pattern = XVECEXP (pattern, 0, 0);
2059 if (GET_CODE (pattern) == SET)
2061 if (reg_mentioned_p (reg, SET_DEST (pattern)))
2063 /* We don't use rtx_equal_p, because we don't care if the
2064 mode is different. */
2065 if (GET_CODE (SET_DEST (pattern)) != REG
2066 || REGNO (reg) != REGNO (SET_DEST (pattern)))
2072 pattern = SET_SRC (pattern);
2075 if (GET_CODE (pattern) != CALL
2076 || GET_CODE (XEXP (pattern, 0)) != MEM
2077 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
2083 /* Exported to toplev.c.
2085 Do a final pass over the function, just before delayed branch
2089 machine_dependent_reorg (first)
2094 /* If relaxing, generate pseudo-ops to associate function calls with
2095 the symbols they call. It does no harm to not generate these
2096 pseudo-ops. However, when we can generate them, it enables to
2097 linker to potentially relax the jsr to a bsr, and eliminate the
2098 register load and, possibly, the constant pool entry. */
2102 /* Remove all REG_LABEL notes. We want to use them for our own
2103 purposes. This works because none of the remaining passes
2104 need to look at them.
2106 ??? But it may break in the future. We should use a machine
2107 dependent REG_NOTE, or some other approach entirely. */
2108 for (insn = first; insn; insn = NEXT_INSN (insn))
2110 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2114 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
2115 remove_note (insn, note);
2119 for (insn = first; insn; insn = NEXT_INSN (insn))
2121 rtx pattern, reg, link, set, scan, dies, label;
2122 int rescan = 0, foundinsn = 0;
2124 if (GET_CODE (insn) == CALL_INSN)
2126 pattern = PATTERN (insn);
2128 if (GET_CODE (pattern) == PARALLEL)
2129 pattern = XVECEXP (pattern, 0, 0);
2130 if (GET_CODE (pattern) == SET)
2131 pattern = SET_SRC (pattern);
2133 if (GET_CODE (pattern) != CALL
2134 || GET_CODE (XEXP (pattern, 0)) != MEM)
2137 reg = XEXP (XEXP (pattern, 0), 0);
2141 reg = sfunc_uses_reg (insn);
2146 if (GET_CODE (reg) != REG)
2149 /* This is a function call via REG. If the only uses of REG
2150 between the time that it is set and the time that it dies
2151 are in function calls, then we can associate all the
2152 function calls with the setting of REG. */
2154 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2156 if (REG_NOTE_KIND (link) != 0)
2158 set = single_set (XEXP (link, 0));
2159 if (set && rtx_equal_p (reg, SET_DEST (set)))
2161 link = XEXP (link, 0);
2168 /* ??? Sometimes global register allocation will have
2169 deleted the insn pointed to by LOG_LINKS. Try
2170 scanning backward to find where the register is set. */
2171 for (scan = PREV_INSN (insn);
2172 scan && GET_CODE (scan) != CODE_LABEL;
2173 scan = PREV_INSN (scan))
2175 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2178 if (! reg_mentioned_p (reg, scan))
2181 if (noncall_uses_reg (reg, scan, &set))
2195 /* The register is set at LINK. */
2197 /* We can only optimize the function call if the register is
2198 being set to a symbol. In theory, we could sometimes
2199 optimize calls to a constant location, but the assembler
2200 and linker do not support that at present. */
2201 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
2202 && GET_CODE (SET_SRC (set)) != LABEL_REF)
2205 /* Scan forward from LINK to the place where REG dies, and
2206 make sure that the only insns which use REG are
2207 themselves function calls. */
2209 /* ??? This doesn't work for call targets that were allocated
2210 by reload, since there may not be a REG_DEAD note for the
2214 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
2218 /* Don't try to trace forward past a CODE_LABEL if we haven't
2219 seen INSN yet. Ordinarily, we will only find the setting insn
2220 in LOG_LINKS if it is in the same basic block. However,
2221 cross-jumping can insert code labels in between the load and
2222 the call, and can result in situations where a single call
2223 insn may have two targets depending on where we came from. */
2225 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
2228 if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
2231 /* Don't try to trace forward past a JUMP. To optimize
2232 safely, we would have to check that all the
2233 instructions at the jump destination did not use REG. */
2235 if (GET_CODE (scan) == JUMP_INSN)
2238 if (! reg_mentioned_p (reg, scan))
2241 if (noncall_uses_reg (reg, scan, &scanset))
2248 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
2250 /* There is a function call to this register other
2251 than the one we are checking. If we optimize
2252 this call, we need to rescan again below. */
2256 /* ??? We shouldn't have to worry about SCANSET here.
2257 We should just be able to check for a REG_DEAD note
2258 on a function call. However, the REG_DEAD notes are
2259 apparently not dependable around libcalls; c-torture
2260 execute/920501-2 is a test case. If SCANSET is set,
2261 then this insn sets the register, so it must have
2262 died earlier. Unfortunately, this will only handle
2263 the cases in which the register is, in fact, set in a
2266 /* ??? We shouldn't have to use FOUNDINSN here.
2267 However, the LOG_LINKS fields are apparently not
2268 entirely reliable around libcalls;
2269 newlib/libm/math/e_pow.c is a test case. Sometimes
2270 an insn will appear in LOG_LINKS even though it is
2271 not the most recent insn which sets the register. */
2275 || find_reg_note (scan, REG_DEAD, reg)))
2284 /* Either there was a branch, or some insn used REG
2285 other than as a function call address. */
2289 /* Create a code label, and put it in a REG_LABEL note on
2290 the insn which sets the register, and on each call insn
2291 which uses the register. In final_prescan_insn we look
2292 for the REG_LABEL notes, and output the appropriate label
2295 label = gen_label_rtx ();
2296 REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2298 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
2307 scan = NEXT_INSN (scan);
2309 && ((GET_CODE (scan) == CALL_INSN
2310 && reg_mentioned_p (reg, scan))
2311 || ((reg2 = sfunc_uses_reg (scan))
2312 && REGNO (reg2) == REGNO (reg))))
2313 REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
2314 label, REG_NOTES (scan));
2316 while (scan != dies);
2321 /* Scan the function looking for move instructions which have to be
2322 changed to pc-relative loads and insert the literal tables. */
2324 for (insn = first; insn; insn = NEXT_INSN (insn))
2326 if (broken_move (insn))
2329 /* Scan ahead looking for a barrier to stick the constant table
2331 rtx barrier = find_barrier (insn);
2333 /* Now find all the moves between the points and modify them. */
2334 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
2336 if (broken_move (scan))
2338 rtx *patp = &PATTERN (scan), pat = *patp;
2343 enum machine_mode mode;
2345 if (GET_CODE (pat) == PARALLEL)
2346 patp = &XVECEXP (pat, 0, 0), pat = *patp;
2347 src = SET_SRC (pat);
2348 dst = SET_DEST (pat);
2349 mode = GET_MODE (dst);
2351 if (mode == SImode && hi_const (src))
2356 while (GET_CODE (dst) == SUBREG)
2358 offset += SUBREG_WORD (dst);
2359 dst = SUBREG_REG (dst);
2361 dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
2364 lab = add_constant (src, mode);
2365 newsrc = gen_rtx (MEM, mode,
2366 gen_rtx (LABEL_REF, VOIDmode, lab));
2367 RTX_UNCHANGING_P (newsrc) = 1;
2368 *patp = gen_rtx (SET, VOIDmode, dst, newsrc);
2369 INSN_CODE (scan) = -1;
2372 dump_table (barrier);
2377 /* Dump out instruction addresses, which is useful for debugging the
2378 constant pool table stuff.
2380 If relaxing, output the label and pseudo-ops used to link together
2381 calls and the instruction which set the registers. */
2383 /* ??? This is unnecessary, and probably should be deleted. This makes
2384 the insn_addresses declaration above unnecessary. */
2386 /* ??? The addresses printed by this routine for insns are nonsense for
2387 insns which are inside of a sequence where none of the inner insns have
2388 variable length. This is because the second pass of shorten_branches
2389 does not bother to update them. */
2392 final_prescan_insn (insn, opvec, noperands)
2397 if (TARGET_DUMPISIZE)
2398 fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
2404 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
2409 pattern = PATTERN (insn);
2410 if (GET_CODE (pattern) == PARALLEL)
2411 pattern = XVECEXP (pattern, 0, 0);
2412 if (GET_CODE (pattern) == CALL
2413 || (GET_CODE (pattern) == SET
2414 && (GET_CODE (SET_SRC (pattern)) == CALL
2415 || get_attr_type (insn) == TYPE_SFUNC)))
2416 fprintf (asm_out_file, "\t.uses L%d\n",
2417 CODE_LABEL_NUMBER (XEXP (note, 0)));
2418 else if (GET_CODE (pattern) == SET)
2419 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2420 CODE_LABEL_NUMBER (XEXP (note, 0)));
2427 /* Dump out any constants accumulated in the final pass. These will
2428 will only be labels. */
2431 output_jump_label_table ()
2437 fprintf (asm_out_file, "\t.align 2\n");
2438 for (i = 0; i < pool_size; i++)
2440 pool_node *p = &pool_vector[i];
2442 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2443 CODE_LABEL_NUMBER (p->label));
2444 output_asm_insn (".long %O0", &p->value);
2452 /* A full frame looks like:
2456 [ if current_function_anonymous_args
2469 local-0 <- fp points here. */
2471 /* Number of bytes pushed for anonymous args, used to pass information
2472 between expand_prologue and expand_epilogue. */
2474 static int extra_push;
2476 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
2477 to be adjusted, and TEMP, if nonnegative, holds the register number
2478 of a general register that we may clobber. */
2481 output_stack_adjust (size, reg, temp)
2488 rtx val = GEN_INT (size);
2491 if (! CONST_OK_FOR_I (size))
2493 if (CONST_OK_FOR_I (size / 2) && CONST_OK_FOR_I (size - size / 2))
2495 val = GEN_INT (size / 2);
2496 emit_insn (gen_addsi3 (reg, reg, val));
2497 val = GEN_INT (size - size / 2);
2503 /* If TEMP is invalid, we could temporarily save a general
2504 register to MACL. However, there is currently no need
2505 to handle this case, so just abort when we see it. */
2508 reg = gen_rtx (REG, SImode, temp);
2509 emit_insn (gen_movsi (reg, val));
2514 insn = gen_addsi3 (reg, reg, val);
2519 /* Output RTL to push register RN onto the stack. */
2526 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
2528 x = emit_insn (gen_push_e (gen_rtx (REG, SFmode, rn)));
2530 x = emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
2532 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
2533 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
2536 /* Output RTL to pop register RN from the stack. */
2543 if ((rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
2545 x = emit_insn (gen_pop_e (gen_rtx (REG, SFmode, rn)));
2547 x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
2549 REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
2550 gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
2553 /* Generate code to push the regs specified in the mask, and return
2554 the number of bytes the insns take. */
2557 push_regs (mask, mask2)
2562 for (i = 0; i < 32; i++)
2563 if (mask & (1 << i))
2565 for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
2566 if (mask2 & (1 << (i - 32)))
2570 /* Work out the registers which need to be saved, both as a mask and a
2573 If doing a pragma interrupt function, then push all regs used by the
2574 function, and if we call another function (we can tell by looking at PR),
2575 make sure that all the regs it clobbers are safe too. */
2578 calc_live_regs (count_ptr, live_regs_mask2)
2580 int *live_regs_mask2;
2583 int live_regs_mask = 0;
2586 *live_regs_mask2 = 0;
2587 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
2589 if (pragma_interrupt && ! pragma_trapa)
2591 /* Need to save all the regs ever live. */
2592 if ((regs_ever_live[reg]
2593 || (call_used_regs[reg]
2594 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
2595 && regs_ever_live[PR_REG]))
2596 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
2597 && reg != RETURN_ADDRESS_POINTER_REGNUM
2598 && reg != T_REG && reg != GBR_REG)
2601 *live_regs_mask2 |= 1 << (reg - 32);
2603 live_regs_mask |= 1 << reg;
2609 /* Only push those regs which are used and need to be saved. */
2610 if (regs_ever_live[reg] && ! call_used_regs[reg])
2613 *live_regs_mask2 |= 1 << (reg - 32);
2615 live_regs_mask |= (1 << reg);
2622 return live_regs_mask;
2625 /* Code to generate prologue and epilogue sequences */
2628 sh_expand_prologue ()
2632 int live_regs_mask2;
2633 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
2635 /* We have pretend args if we had an object sent partially in registers
2636 and partially on the stack, e.g. a large structure. */
2637 output_stack_adjust (-current_function_pretend_args_size,
2638 stack_pointer_rtx, 3);
2642 /* This is set by SETUP_VARARGS to indicate that this is a varargs
2643 routine. Clear it here so that the next function isn't affected. */
2644 if (current_function_anonymous_args)
2646 current_function_anonymous_args = 0;
2648 /* This is not used by the SH3E calling convention */
2651 /* Push arg regs as if they'd been provided by caller in stack. */
2652 for (i = 0; i < NPARM_REGS(SImode); i++)
2654 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
2655 if (i > (NPARM_REGS(SImode)
2656 - current_function_args_info.arg_count[(int) SH_ARG_INT]
2657 - current_function_varargs))
2665 push_regs (live_regs_mask, live_regs_mask2);
2667 output_stack_adjust (-get_frame_size (), stack_pointer_rtx, 3);
2669 if (frame_pointer_needed)
2670 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2674 sh_expand_epilogue ()
2679 int live_regs_mask2;
2680 live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
2682 if (frame_pointer_needed)
2684 /* We deliberately make the add dependent on the frame_pointer,
2685 to ensure that instruction scheduling won't move the stack pointer
2686 adjust before instructions reading from the frame. This can fail
2687 if there is an interrupt which then writes to the stack. */
2688 output_stack_adjust (get_frame_size (), frame_pointer_rtx, 7);
2689 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2692 output_stack_adjust (get_frame_size (), stack_pointer_rtx, 7);
2694 /* Pop all the registers. */
2696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2698 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
2699 if (j < 32 && (live_regs_mask & (1 << j)))
2701 else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
2705 output_stack_adjust (extra_push + current_function_pretend_args_size,
2706 stack_pointer_rtx, 7);
2709 /* Clear variables at function end. */
2712 function_epilogue (stream, size)
2716 pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
2720 sh_builtin_saveregs (arglist)
2723 tree fntype = TREE_TYPE (current_function_decl);
2724 /* First unnamed integer register. */
2725 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
2726 /* Number of integer registers we need to save. */
2727 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
2728 /* First unnamed SFmode float reg */
2729 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
2730 /* Number of SFmode float regs to save. */
2731 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
2732 int ptrsize = GET_MODE_SIZE (Pmode);
2733 rtx valist, regbuf, fpregs;
2736 /* Allocate block of memory for the regs. */
2737 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
2738 Or can assign_stack_local accept a 0 SIZE argument? */
2739 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
2741 regbuf = assign_stack_local (BLKmode, bufsize, 0);
2742 MEM_IN_STRUCT_P (regbuf) = 1;
2745 This is optimized to only save the regs that are necessary. Explicitly
2746 named args need not be saved. */
2748 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
2749 gen_rtx (MEM, BLKmode,
2750 plus_constant (XEXP (regbuf, 0),
2751 n_floatregs * UNITS_PER_WORD)),
2752 n_intregs, n_intregs * UNITS_PER_WORD);
2755 This is optimized to only save the regs that are necessary. Explicitly
2756 named args need not be saved.
2757 We explicitly build a pointer to the buffer because it halves the insn
2758 count when not optimizing (otherwise the pointer is built for each reg
2761 fpregs = gen_reg_rtx (Pmode);
2762 emit_move_insn (fpregs, XEXP (regbuf, 0));
2763 for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno ++)
2764 emit_move_insn (gen_rtx (MEM, SFmode,
2765 plus_constant (fpregs,
2766 GET_MODE_SIZE (SFmode)
2767 * (regno - first_floatreg))),
2768 gen_rtx (REG, SFmode,
2769 BASE_ARG_REG (SFmode) + regno));
2771 /* Return the address of the regbuf. */
2772 return XEXP (regbuf, 0);
2775 /* Define the offset between two registers, one to be eliminated, and
2776 the other its replacement, at the start of a routine. */
2779 initial_elimination_offset (from, to)
2784 int total_saved_regs_space;
2785 int total_auto_space = get_frame_size ();
2787 int live_regs_mask, live_regs_mask2;
2788 live_regs_mask = calc_live_regs (®s_saved, &live_regs_mask2);
2790 total_saved_regs_space = (regs_saved) * 4;
2792 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2793 return total_saved_regs_space + total_auto_space;
2795 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2796 return total_saved_regs_space + total_auto_space;
2798 /* Initial gap between fp and sp is 0. */
2799 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2802 if (from == RETURN_ADDRESS_POINTER_REGNUM
2803 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
2806 for (i = PR_REG+1; i < 32; i++)
2807 if (live_regs_mask & (1 << i))
2809 for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
2810 if (live_regs_mask2 & (1 << (i - 32)))
2812 return n + total_auto_space;
2818 /* Handle machine specific pragmas to be semi-compatible with Hitachi
2822 handle_pragma (file, t)
2827 register char *pname;
2829 if (TREE_CODE (t) != IDENTIFIER_NODE)
2832 pname = IDENTIFIER_POINTER (t);
2833 if (strcmp (pname, "interrupt") == 0)
2834 pragma_interrupt = retval = 1;
2835 else if (strcmp (pname, "trapa") == 0)
2836 pragma_interrupt = pragma_trapa = retval = 1;
2837 else if (strcmp (pname, "nosave_low_regs") == 0)
2838 pragma_nosave_low_regs = retval = 1;
2843 /* Predicates used by the templates. */
2845 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
2846 Used only in general_movsrc_operand. */
2849 system_reg_operand (op, mode)
2851 enum machine_mode mode;
2863 /* Returns 1 if OP can be source of a simple move operation.
2864 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
2865 invalid as are subregs of system registers. */
2868 general_movsrc_operand (op, mode)
2870 enum machine_mode mode;
2872 if (GET_CODE (op) == MEM)
2874 rtx inside = XEXP (op, 0);
2875 if (GET_CODE (inside) == CONST)
2876 inside = XEXP (inside, 0);
2878 if (GET_CODE (inside) == LABEL_REF)
2881 if (GET_CODE (inside) == PLUS
2882 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
2883 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
2886 /* Only post inc allowed. */
2887 if (GET_CODE (inside) == PRE_DEC)
2891 if ((mode == QImode || mode == HImode)
2892 && (GET_CODE (op) == SUBREG
2893 && GET_CODE (XEXP (op, 0)) == REG
2894 && system_reg_operand (XEXP (op, 0), mode)))
2897 return general_operand (op, mode);
2900 /* Returns 1 if OP can be a destination of a move.
2901 Same as general_operand, but no preinc allowed. */
2904 general_movdst_operand (op, mode)
2906 enum machine_mode mode;
2908 /* Only pre dec allowed. */
2909 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
2912 return general_operand (op, mode);
2915 /* Returns 1 if OP is a normal arithmetic register. */
2918 arith_reg_operand (op, mode)
2920 enum machine_mode mode;
2922 if (register_operand (op, mode))
2926 if (GET_CODE (op) == REG)
2928 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
2929 regno = REGNO (SUBREG_REG (op));
2933 return (regno != T_REG && regno != PR_REG && regno != FPUL_REG
2934 && regno != MACH_REG && regno != MACL_REG);
2939 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
2942 arith_operand (op, mode)
2944 enum machine_mode mode;
2946 if (arith_reg_operand (op, mode))
2949 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
2955 /* Returns 1 if OP is a valid source operand for a compare insn. */
2958 arith_reg_or_0_operand (op, mode)
2960 enum machine_mode mode;
2962 if (arith_reg_operand (op, mode))
2965 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
2971 /* Returns 1 if OP is a valid source operand for a logical operation. */
2974 logical_operand (op, mode)
2976 enum machine_mode mode;
2978 if (arith_reg_operand (op, mode))
2981 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
2987 /* Nonzero if OP is a floating point value with value 0.0. */
2990 fp_zero_operand (op)
2995 if (GET_MODE (op) != SFmode)
2998 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2999 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
3002 /* Nonzero if OP is a floating point value with value 1.0. */
3010 if (GET_MODE (op) != SFmode)
3013 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3014 return REAL_VALUES_EQUAL (r, dconst1);
3017 /* Return non-zero if REG is not used after INSN.
3018 We assume REG is a reload reg, and therefore does
3019 not live past labels. It may live past calls or jumps though. */
3021 reg_unused_after (reg, insn)
3028 /* If the reg is set by this instruction, then it is safe for our
3029 case. Disregard the case where this is a store to memory, since
3030 we are checking a register used in the store address. */
3031 set = single_set (insn);
3032 if (set && GET_CODE (SET_DEST (set)) != MEM
3033 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3036 while (insn = NEXT_INSN (insn))
3038 code = GET_CODE (insn);
3041 /* If this is a label that existed before reload, then the register
3042 if dead here. However, if this is a label added by reorg, then
3043 the register may still be live here. We can't tell the difference,
3044 so we just ignore labels completely. */
3045 if (code == CODE_LABEL)
3050 if (code == JUMP_INSN)
3053 /* If this is a sequence, we must handle them all at once.
3054 We could have for instance a call that sets the target register,
3055 and a insn in a delay slot that uses the register. In this case,
3056 we must return 0. */
3057 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3062 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
3064 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
3065 rtx set = single_set (this_insn);
3067 if (GET_CODE (this_insn) == CALL_INSN)
3069 else if (GET_CODE (this_insn) == JUMP_INSN)
3071 if (INSN_ANNULLED_BRANCH_P (this_insn))
3076 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
3078 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3080 if (GET_CODE (SET_DEST (set)) != MEM)
3086 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
3091 else if (code == JUMP_INSN)
3094 else if (GET_RTX_CLASS (code) == 'i')
3096 rtx set = single_set (insn);
3098 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
3100 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3101 return GET_CODE (SET_DEST (set)) != MEM;
3102 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3106 if (code == CALL_INSN && call_used_regs[REGNO (reg)])