1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
27 #include "insn-config.h"
35 #include "hard-reg-set.h"
37 #include "insn-attr.h"
40 #include "integrate.h"
41 #include "elf/dwarf2.h"
44 #include "target-def.h"
46 #include "langhooks.h"
47 #include "basic-block.h"
49 #include "cfglayout.h"
51 #include "sched-int.h"
56 #include "alloc-pool.h"
57 #include "tm-constrs.h"
60 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
62 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
63 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
65 /* These are some macros to abstract register modes. */
66 #define CONST_OK_FOR_ADD(size) \
67 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
68 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
69 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
70 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
72 /* Used to simplify the logic below. Find the attributes wherever
74 #define SH_ATTRIBUTES(decl) \
75 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
76 : DECL_ATTRIBUTES (decl) \
77 ? (DECL_ATTRIBUTES (decl)) \
78 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
80 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
81 int current_function_interrupt;
83 tree sh_deferred_function_attributes;
84 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
86 /* Global variables for machine-dependent things. */
88 /* Which cpu are we scheduling for. */
89 enum processor_type sh_cpu;
91 /* Definitions used in ready queue reordering for first scheduling pass. */
93 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
94 static short *regmode_weight[2];
96 /* Total SFmode and SImode weights of scheduled insns. */
97 static int curr_regmode_pressure[2];
99 /* Number of r0 life regions. */
100 static int r0_life_regions;
102 /* If true, skip cycles for Q -> R movement. */
103 static int skip_cycles = 0;
105 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
106 and returned from sh_reorder2. */
107 static short cached_can_issue_more;
109 /* Provides the class number of the smallest class containing
112 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
114 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
147 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
148 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
149 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
150 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
151 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
152 GENERAL_REGS, GENERAL_REGS,
155 char sh_register_names[FIRST_PSEUDO_REGISTER] \
156 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
158 char sh_additional_register_names[ADDREGNAMES_SIZE] \
159 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
160 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
162 int assembler_dialect;
164 static bool shmedia_space_reserved_for_target_registers;
166 static bool sh_handle_option (size_t, const char *, int);
167 static void split_branches (rtx);
168 static int branch_dest (rtx);
169 static void force_into (rtx, rtx);
170 static void print_slot (rtx);
171 static rtx add_constant (rtx, enum machine_mode, rtx);
172 static void dump_table (rtx, rtx);
173 static int hi_const (rtx);
174 static int broken_move (rtx);
175 static int mova_p (rtx);
176 static rtx find_barrier (int, rtx, rtx);
177 static int noncall_uses_reg (rtx, rtx, rtx *);
178 static rtx gen_block_redirect (rtx, int, int);
179 static void sh_reorg (void);
180 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
181 static rtx frame_insn (rtx);
182 static rtx push (int);
183 static void pop (int);
184 static void push_regs (HARD_REG_SET *, int);
185 static int calc_live_regs (HARD_REG_SET *);
186 static HOST_WIDE_INT rounded_frame_size (int);
187 static rtx mark_constant_pool_use (rtx);
188 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
189 static tree sh_handle_resbank_handler_attribute (tree *, tree,
191 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
193 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
194 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
196 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
197 static void sh_insert_attributes (tree, tree *);
198 static const char *sh_check_pch_target_flags (int);
199 static int sh_adjust_cost (rtx, rtx, rtx, int);
200 static int sh_issue_rate (void);
201 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
202 static short find_set_regmode_weight (rtx, enum machine_mode);
203 static short find_insn_regmode_weight (rtx, enum machine_mode);
204 static void find_regmode_weight (basic_block, enum machine_mode);
205 static int find_r0_life_regions (basic_block);
206 static void sh_md_init_global (FILE *, int, int);
207 static void sh_md_finish_global (FILE *, int);
208 static int rank_for_reorder (const void *, const void *);
209 static void swap_reorder (rtx *, int);
210 static void ready_reorder (rtx *, int);
211 static short high_pressure (enum machine_mode);
212 static int sh_reorder (FILE *, int, rtx *, int *, int);
213 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
214 static void sh_md_init (FILE *, int, int);
215 static int sh_variable_issue (FILE *, int, rtx, int);
217 static bool sh_function_ok_for_sibcall (tree, tree);
219 static bool sh_cannot_modify_jumps_p (void);
220 static enum reg_class sh_target_reg_class (void);
221 static bool sh_optimize_target_register_callee_saved (bool);
222 static bool sh_ms_bitfield_layout_p (const_tree);
224 static void sh_init_builtins (void);
225 static void sh_media_init_builtins (void);
226 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
227 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
228 static void sh_file_start (void);
229 static int flow_dependent_p (rtx, rtx);
230 static void flow_dependent_p_1 (rtx, const_rtx, void *);
231 static int shiftcosts (rtx);
232 static int andcosts (rtx);
233 static int addsubcosts (rtx);
234 static int multcosts (rtx);
235 static bool unspec_caller_rtx_p (rtx);
236 static bool sh_cannot_copy_insn_p (rtx);
237 static bool sh_rtx_costs (rtx, int, int, int *, bool);
238 static int sh_address_cost (rtx, bool);
239 static int sh_pr_n_sets (void);
240 static rtx sh_allocate_initial_value (rtx);
241 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
242 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
243 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
244 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
245 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
246 static int scavenge_reg (HARD_REG_SET *s);
247 struct save_schedule_s;
248 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
249 struct save_schedule_s *, int);
251 static rtx sh_struct_value_rtx (tree, int);
252 static bool sh_return_in_memory (const_tree, const_tree);
253 static rtx sh_builtin_saveregs (void);
254 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
255 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
256 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
257 static tree sh_build_builtin_va_list (void);
258 static void sh_va_start (tree, rtx);
259 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
260 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
262 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
264 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
266 static bool sh_scalar_mode_supported_p (enum machine_mode);
267 static int sh_dwarf_calling_convention (const_tree);
268 static void sh_encode_section_info (tree, rtx, int);
269 static int sh2a_function_vector_p (tree);
271 static const struct attribute_spec sh_attribute_table[] =
273 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
274 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
275 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
276 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
277 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
278 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
279 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
280 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
281 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
283 /* Symbian support adds three new attributes:
284 dllexport - for exporting a function/variable that will live in a dll
285 dllimport - for importing a function/variable from a dll
287 Microsoft allows multiple declspecs in one __declspec, separating
288 them with spaces. We do NOT support this. Instead, use __declspec
290 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
291 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
293 { NULL, 0, 0, false, false, false, NULL }
296 /* Initialize the GCC target structure. */
297 #undef TARGET_ATTRIBUTE_TABLE
298 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
300 /* The next two are used for debug info when compiling with -gdwarf. */
301 #undef TARGET_ASM_UNALIGNED_HI_OP
302 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
303 #undef TARGET_ASM_UNALIGNED_SI_OP
304 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
306 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
307 #undef TARGET_ASM_UNALIGNED_DI_OP
308 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
309 #undef TARGET_ASM_ALIGNED_DI_OP
310 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
312 #undef TARGET_ASM_FUNCTION_EPILOGUE
313 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
315 #undef TARGET_ASM_OUTPUT_MI_THUNK
316 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
318 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
319 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
321 #undef TARGET_ASM_FILE_START
322 #define TARGET_ASM_FILE_START sh_file_start
323 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
324 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
326 #undef TARGET_DEFAULT_TARGET_FLAGS
327 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
328 #undef TARGET_HANDLE_OPTION
329 #define TARGET_HANDLE_OPTION sh_handle_option
331 #undef TARGET_INSERT_ATTRIBUTES
332 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
334 #undef TARGET_SCHED_ADJUST_COST
335 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
337 #undef TARGET_SCHED_ISSUE_RATE
338 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
340 /* The next 5 hooks have been implemented for reenabling sched1. With the
341 help of these macros we are limiting the movement of insns in sched1 to
342 reduce the register pressure. The overall idea is to keep count of SImode
343 and SFmode regs required by already scheduled insns. When these counts
344 cross some threshold values; give priority to insns that free registers.
345 The insn that frees registers is most likely to be the insn with lowest
346 LUID (original insn order); but such an insn might be there in the stalled
347 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
348 upto a max of 8 cycles so that such insns may move from Q -> R.
350 The description of the hooks are as below:
352 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
353 scheduler; it is called inside the sched_init function just after
354 find_insn_reg_weights function call. It is used to calculate the SImode
355 and SFmode weights of insns of basic blocks; much similar to what
356 find_insn_reg_weights does.
357 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
359 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
360 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
363 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
364 high; reorder the ready queue so that the insn with lowest LUID will be
367 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
368 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
370 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
371 can be returned from TARGET_SCHED_REORDER2.
373 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
375 #undef TARGET_SCHED_DFA_NEW_CYCLE
376 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
378 #undef TARGET_SCHED_INIT_GLOBAL
379 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
381 #undef TARGET_SCHED_FINISH_GLOBAL
382 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
384 #undef TARGET_SCHED_VARIABLE_ISSUE
385 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
387 #undef TARGET_SCHED_REORDER
388 #define TARGET_SCHED_REORDER sh_reorder
390 #undef TARGET_SCHED_REORDER2
391 #define TARGET_SCHED_REORDER2 sh_reorder2
393 #undef TARGET_SCHED_INIT
394 #define TARGET_SCHED_INIT sh_md_init
396 #undef TARGET_LEGITIMIZE_ADDRESS
397 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
399 #undef TARGET_CANNOT_MODIFY_JUMPS_P
400 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
401 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
402 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
403 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
404 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
405 sh_optimize_target_register_callee_saved
407 #undef TARGET_MS_BITFIELD_LAYOUT_P
408 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
410 #undef TARGET_INIT_BUILTINS
411 #define TARGET_INIT_BUILTINS sh_init_builtins
412 #undef TARGET_EXPAND_BUILTIN
413 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
415 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
416 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
418 #undef TARGET_CANNOT_COPY_INSN_P
419 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
420 #undef TARGET_RTX_COSTS
421 #define TARGET_RTX_COSTS sh_rtx_costs
422 #undef TARGET_ADDRESS_COST
423 #define TARGET_ADDRESS_COST sh_address_cost
424 #undef TARGET_ALLOCATE_INITIAL_VALUE
425 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
427 #undef TARGET_MACHINE_DEPENDENT_REORG
428 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
430 #undef TARGET_DWARF_REGISTER_SPAN
431 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
434 #undef TARGET_HAVE_TLS
435 #define TARGET_HAVE_TLS true
438 #undef TARGET_PROMOTE_PROTOTYPES
439 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
440 #undef TARGET_PROMOTE_FUNCTION_ARGS
441 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
442 #undef TARGET_PROMOTE_FUNCTION_RETURN
443 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
445 #undef TARGET_STRUCT_VALUE_RTX
446 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
447 #undef TARGET_RETURN_IN_MEMORY
448 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
450 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
451 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
452 #undef TARGET_SETUP_INCOMING_VARARGS
453 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
454 #undef TARGET_STRICT_ARGUMENT_NAMING
455 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
456 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
457 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
458 #undef TARGET_MUST_PASS_IN_STACK
459 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
460 #undef TARGET_PASS_BY_REFERENCE
461 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
462 #undef TARGET_CALLEE_COPIES
463 #define TARGET_CALLEE_COPIES sh_callee_copies
464 #undef TARGET_ARG_PARTIAL_BYTES
465 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
467 #undef TARGET_BUILD_BUILTIN_VA_LIST
468 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
469 #undef TARGET_EXPAND_BUILTIN_VA_START
470 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
471 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
472 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
474 #undef TARGET_SCALAR_MODE_SUPPORTED_P
475 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
476 #undef TARGET_VECTOR_MODE_SUPPORTED_P
477 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
479 #undef TARGET_CHECK_PCH_TARGET_FLAGS
480 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
482 #undef TARGET_DWARF_CALLING_CONVENTION
483 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
485 /* Return regmode weight for insn. */
486 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
488 /* Return current register pressure for regmode. */
489 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
491 #undef TARGET_ENCODE_SECTION_INFO
492 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
496 #undef TARGET_ENCODE_SECTION_INFO
497 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
498 #undef TARGET_STRIP_NAME_ENCODING
499 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
500 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
501 #define TARGET_CXX_IMPORT_EXPORT_CLASS symbian_import_export_class
505 #undef TARGET_SECONDARY_RELOAD
506 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
508 #undef TARGET_LEGITIMATE_ADDRESS_P
509 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
511 /* Machine-specific symbol_ref flags. */
512 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
514 struct gcc_target targetm = TARGET_INITIALIZER;
516 /* Implement TARGET_HANDLE_OPTION. */
519 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
520 int value ATTRIBUTE_UNUSED)
525 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
529 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
533 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
537 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
541 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
544 case OPT_m2a_single_only:
545 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
549 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
553 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
557 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
564 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
568 case OPT_m4_100_nofpu:
569 case OPT_m4_200_nofpu:
570 case OPT_m4_300_nofpu:
574 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
578 case OPT_m4_100_single:
579 case OPT_m4_200_single:
580 case OPT_m4_300_single:
581 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
584 case OPT_m4_single_only:
585 case OPT_m4_100_single_only:
586 case OPT_m4_200_single_only:
587 case OPT_m4_300_single_only:
588 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
592 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
597 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
601 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
604 case OPT_m4a_single_only:
605 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
609 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
612 case OPT_m5_32media_nofpu:
613 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
617 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
620 case OPT_m5_64media_nofpu:
621 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
625 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
628 case OPT_m5_compact_nofpu:
629 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
637 /* Set default optimization options. */
639 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
643 flag_omit_frame_pointer = 2;
645 sh_div_str = "inv:minlat";
649 target_flags |= MASK_SMALLCODE;
650 sh_div_str = SH_DIV_STR_FOR_SIZE ;
653 TARGET_CBRANCHDI4 = 1;
654 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
655 haven't been parsed yet, hence we'd read only the default.
656 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
657 it's OK to always set flag_branch_target_load_optimize. */
660 flag_branch_target_load_optimize = 1;
662 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
664 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
665 here, so leave it to OVERRIDE_OPTIONS to set
666 flag_finite_math_only. We set it to 2 here so we know if the user
667 explicitly requested this to be on or off. */
668 flag_finite_math_only = 2;
669 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
670 the user explicitly requested this to be on or off. */
671 if (flag_schedule_insns > 0)
672 flag_schedule_insns = 2;
674 set_param_value ("simultaneous-prefetches", 2);
677 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
678 options, and do some machine dependent initialization. */
680 sh_override_options (void)
684 SUBTARGET_OVERRIDE_OPTIONS;
685 if (flag_finite_math_only == 2)
686 flag_finite_math_only
687 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
688 if (TARGET_SH2E && !flag_finite_math_only)
689 target_flags |= MASK_IEEE;
690 sh_cpu = PROCESSOR_SH1;
691 assembler_dialect = 0;
693 sh_cpu = PROCESSOR_SH2;
695 sh_cpu = PROCESSOR_SH2E;
698 sh_cpu = PROCESSOR_SH2A;
699 if (TARGET_SH2A_DOUBLE)
700 target_flags |= MASK_FMOVD;
703 sh_cpu = PROCESSOR_SH3;
705 sh_cpu = PROCESSOR_SH3E;
708 assembler_dialect = 1;
709 sh_cpu = PROCESSOR_SH4;
711 if (TARGET_SH4A_ARCH)
713 assembler_dialect = 1;
714 sh_cpu = PROCESSOR_SH4A;
718 sh_cpu = PROCESSOR_SH5;
719 target_flags |= MASK_ALIGN_DOUBLE;
720 if (TARGET_SHMEDIA_FPU)
721 target_flags |= MASK_FMOVD;
724 /* There are no delay slots on SHmedia. */
725 flag_delayed_branch = 0;
726 /* Relaxation isn't yet supported for SHmedia */
727 target_flags &= ~MASK_RELAX;
728 /* After reload, if conversion does little good but can cause
730 - find_if_block doesn't do anything for SH because we don't
731 have conditional execution patterns. (We use conditional
732 move patterns, which are handled differently, and only
734 - find_cond_trap doesn't do anything for the SH because we
735 don't have conditional traps.
736 - find_if_case_1 uses redirect_edge_and_branch_force in
737 the only path that does an optimization, and this causes
738 an ICE when branch targets are in registers.
739 - find_if_case_2 doesn't do anything for the SHmedia after
740 reload except when it can redirect a tablejump - and
741 that's rather rare. */
742 flag_if_conversion2 = 0;
743 if (! strcmp (sh_div_str, "call"))
744 sh_div_strategy = SH_DIV_CALL;
745 else if (! strcmp (sh_div_str, "call2"))
746 sh_div_strategy = SH_DIV_CALL2;
747 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
748 sh_div_strategy = SH_DIV_FP;
749 else if (! strcmp (sh_div_str, "inv"))
750 sh_div_strategy = SH_DIV_INV;
751 else if (! strcmp (sh_div_str, "inv:minlat"))
752 sh_div_strategy = SH_DIV_INV_MINLAT;
753 else if (! strcmp (sh_div_str, "inv20u"))
754 sh_div_strategy = SH_DIV_INV20U;
755 else if (! strcmp (sh_div_str, "inv20l"))
756 sh_div_strategy = SH_DIV_INV20L;
757 else if (! strcmp (sh_div_str, "inv:call2"))
758 sh_div_strategy = SH_DIV_INV_CALL2;
759 else if (! strcmp (sh_div_str, "inv:call"))
760 sh_div_strategy = SH_DIV_INV_CALL;
761 else if (! strcmp (sh_div_str, "inv:fp"))
764 sh_div_strategy = SH_DIV_INV_FP;
766 sh_div_strategy = SH_DIV_INV;
768 TARGET_CBRANCHDI4 = 0;
769 /* Assembler CFI isn't yet fully supported for SHmedia. */
770 flag_dwarf2_cfi_asm = 0;
775 /* Only the sh64-elf assembler fully supports .quad properly. */
776 targetm.asm_out.aligned_op.di = NULL;
777 targetm.asm_out.unaligned_op.di = NULL;
781 if (! strcmp (sh_div_str, "call-div1"))
782 sh_div_strategy = SH_DIV_CALL_DIV1;
783 else if (! strcmp (sh_div_str, "call-fp")
784 && (TARGET_FPU_DOUBLE
785 || (TARGET_HARD_SH4 && TARGET_SH2E)
786 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
787 sh_div_strategy = SH_DIV_CALL_FP;
788 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
789 sh_div_strategy = SH_DIV_CALL_TABLE;
791 /* Pick one that makes most sense for the target in general.
792 It is not much good to use different functions depending
793 on -Os, since then we'll end up with two different functions
794 when some of the code is compiled for size, and some for
797 /* SH4 tends to emphasize speed. */
799 sh_div_strategy = SH_DIV_CALL_TABLE;
800 /* These have their own way of doing things. */
801 else if (TARGET_SH2A)
802 sh_div_strategy = SH_DIV_INTRINSIC;
803 /* ??? Should we use the integer SHmedia function instead? */
804 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
805 sh_div_strategy = SH_DIV_CALL_FP;
806 /* SH1 .. SH3 cores often go into small-footprint systems, so
807 default to the smallest implementation available. */
808 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
809 sh_div_strategy = SH_DIV_CALL_TABLE;
811 sh_div_strategy = SH_DIV_CALL_DIV1;
814 TARGET_PRETEND_CMOVE = 0;
815 if (sh_divsi3_libfunc[0])
816 ; /* User supplied - leave it alone. */
817 else if (TARGET_DIVIDE_CALL_FP)
818 sh_divsi3_libfunc = "__sdivsi3_i4";
819 else if (TARGET_DIVIDE_CALL_TABLE)
820 sh_divsi3_libfunc = "__sdivsi3_i4i";
822 sh_divsi3_libfunc = "__sdivsi3_1";
824 sh_divsi3_libfunc = "__sdivsi3";
825 if (sh_branch_cost == -1)
827 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
829 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
830 if (! VALID_REGISTER_P (regno))
831 sh_register_names[regno][0] = '\0';
833 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
834 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
835 sh_additional_register_names[regno][0] = '\0';
837 if (flag_omit_frame_pointer == 2)
839 /* The debugging information is sufficient,
840 but gdb doesn't implement this yet */
842 flag_omit_frame_pointer
843 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
845 flag_omit_frame_pointer = 0;
848 if ((flag_pic && ! TARGET_PREFERGOT)
849 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
850 flag_no_function_cse = 1;
852 if (SMALL_REGISTER_CLASSES)
854 /* Never run scheduling before reload, since that can
855 break global alloc, and generates slower code anyway due
856 to the pressure on R0. */
857 /* Enable sched1 for SH4 if the user explicitly requests.
858 When sched1 is enabled, the ready queue will be reordered by
859 the target hooks if pressure is high. We can not do this for
860 PIC, SH3 and lower as they give spill failures for R0. */
861 if (!TARGET_HARD_SH4 || flag_pic)
862 flag_schedule_insns = 0;
863 /* ??? Current exception handling places basic block boundaries
864 after call_insns. It causes the high pressure on R0 and gives
865 spill failures for R0 in reload. See PR 22553 and the thread
867 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
868 else if (flag_exceptions)
870 if (flag_schedule_insns == 1)
871 warning (0, "ignoring -fschedule-insns because of exception handling bug");
872 flag_schedule_insns = 0;
874 else if (flag_schedule_insns == 2)
875 flag_schedule_insns = 0;
878 if (align_loops == 0)
879 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
880 if (align_jumps == 0)
881 align_jumps = 1 << CACHE_LOG;
882 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
883 align_jumps = TARGET_SHMEDIA ? 4 : 2;
885 /* Allocation boundary (in *bytes*) for the code of a function.
886 SH1: 32 bit alignment is faster, because instructions are always
887 fetched as a pair from a longword boundary.
888 SH2 .. SH5 : align to cache line start. */
889 if (align_functions == 0)
891 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
892 /* The linker relaxation code breaks when a function contains
893 alignments that are larger than that at the start of a
898 = align_loops > align_jumps ? align_loops : align_jumps;
900 /* Also take possible .long constants / mova tables int account. */
903 if (align_functions < min_align)
904 align_functions = min_align;
907 if (sh_fixed_range_str)
908 sh_fix_range (sh_fixed_range_str);
911 /* Print the operand address in x to the stream. */
914 print_operand_address (FILE *stream, rtx x)
916 switch (GET_CODE (x))
920 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
925 rtx base = XEXP (x, 0);
926 rtx index = XEXP (x, 1);
928 switch (GET_CODE (index))
931 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
932 reg_names[true_regnum (base)]);
938 int base_num = true_regnum (base);
939 int index_num = true_regnum (index);
941 fprintf (stream, "@(r0,%s)",
942 reg_names[MAX (base_num, index_num)]);
953 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
957 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
961 x = mark_constant_pool_use (x);
962 output_addr_const (stream, x);
967 /* Print operand x (an rtx) in assembler syntax to file stream
968 according to modifier code.
970 '.' print a .s if insn needs delay slot
971 ',' print LOCAL_LABEL_PREFIX
972 '@' print trap, rte or rts depending upon pragma interruptness
973 '#' output a nop if there is nothing to put in the delay slot
974 ''' print likelihood suffix (/u for unlikely).
975 '>' print branch target if -fverbose-asm
976 'O' print a constant without the #
977 'R' print the LSW of a dp value - changes if in little endian
978 'S' print the MSW of a dp value - changes if in little endian
979 'T' print the next word of a dp value - same as 'R' in big endian mode.
980 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
981 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
982 'N' print 'r63' if the operand is (const_int 0).
983 'd' print a V2SF reg as dN instead of fpN.
984 'm' print a pair `base,offset' or `base,index', for LD and ST.
985 'U' Likewise for {LD,ST}{HI,LO}.
986 'V' print the position of a single bit set.
987 'W' print the position of a single bit cleared.
988 't' print a memory address which is a register.
989 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
990 'o' output an operator. */
993 print_operand (FILE *stream, rtx x, int code)
996 enum machine_mode mode;
1004 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1005 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1006 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1009 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1012 trapa_attr = lookup_attribute ("trap_exit",
1013 DECL_ATTRIBUTES (current_function_decl));
1015 fprintf (stream, "trapa #%ld",
1016 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1017 else if (sh_cfun_interrupt_handler_p ())
1019 if (sh_cfun_resbank_handler_p ())
1020 fprintf (stream, "resbank\n");
1021 fprintf (stream, "rte");
1024 fprintf (stream, "rts");
1027 /* Output a nop if there's nothing in the delay slot. */
1028 if (dbr_sequence_length () == 0)
1029 fprintf (stream, "\n\tnop");
1033 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1035 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1036 fputs ("/u", stream);
1040 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1042 fputs ("\t! target: ", stream);
1043 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1047 x = mark_constant_pool_use (x);
1048 output_addr_const (stream, x);
1050 /* N.B.: %R / %S / %T adjust memory addresses by four.
1051 For SHMEDIA, that means they can be used to access the first and
1052 second 32 bit part of a 64 bit (or larger) value that
1053 might be held in floating point registers or memory.
1054 While they can be used to access 64 bit parts of a larger value
1055 held in general purpose registers, that won't work with memory -
1056 neither for fp registers, since the frxx names are used. */
1058 if (REG_P (x) || GET_CODE (x) == SUBREG)
1060 regno = true_regnum (x);
1061 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1062 fputs (reg_names[regno], (stream));
1066 x = adjust_address (x, SImode, 4 * LSW);
1067 print_operand_address (stream, XEXP (x, 0));
1073 mode = GET_MODE (x);
1074 if (mode == VOIDmode)
1076 if (GET_MODE_SIZE (mode) >= 8)
1077 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1079 print_operand (stream, sub, 0);
1081 output_operand_lossage ("invalid operand to %%R");
1085 if (REG_P (x) || GET_CODE (x) == SUBREG)
1087 regno = true_regnum (x);
1088 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1089 fputs (reg_names[regno], (stream));
1093 x = adjust_address (x, SImode, 4 * MSW);
1094 print_operand_address (stream, XEXP (x, 0));
1100 mode = GET_MODE (x);
1101 if (mode == VOIDmode)
1103 if (GET_MODE_SIZE (mode) >= 8)
1104 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1106 print_operand (stream, sub, 0);
1108 output_operand_lossage ("invalid operand to %%S");
1112 /* Next word of a double. */
1113 switch (GET_CODE (x))
1116 fputs (reg_names[REGNO (x) + 1], (stream));
1119 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1120 && GET_CODE (XEXP (x, 0)) != POST_INC)
1121 x = adjust_address (x, SImode, 4);
1122 print_operand_address (stream, XEXP (x, 0));
1130 gcc_assert (MEM_P (x));
1132 switch (GET_CODE (x))
1136 print_operand (stream, x, 0);
1144 switch (GET_CODE (x))
1146 case PLUS: fputs ("add", stream); break;
1147 case MINUS: fputs ("sub", stream); break;
1148 case MULT: fputs ("mul", stream); break;
1149 case DIV: fputs ("div", stream); break;
1150 case EQ: fputs ("eq", stream); break;
1151 case NE: fputs ("ne", stream); break;
1152 case GT: case LT: fputs ("gt", stream); break;
1153 case GE: case LE: fputs ("ge", stream); break;
1154 case GTU: case LTU: fputs ("gtu", stream); break;
1155 case GEU: case LEU: fputs ("geu", stream); break;
1164 && GET_CODE (XEXP (x, 0)) == PLUS
1165 && (REG_P (XEXP (XEXP (x, 0), 1))
1166 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1167 fputc ('x', stream);
1173 switch (GET_MODE (x))
1175 case QImode: fputs (".b", stream); break;
1176 case HImode: fputs (".w", stream); break;
1177 case SImode: fputs (".l", stream); break;
1178 case SFmode: fputs (".s", stream); break;
1179 case DFmode: fputs (".d", stream); break;
1180 default: gcc_unreachable ();
1187 gcc_assert (MEM_P (x));
1191 switch (GET_CODE (x))
1195 print_operand (stream, x, 0);
1196 fputs (", 0", stream);
1200 print_operand (stream, XEXP (x, 0), 0);
1201 fputs (", ", stream);
1202 print_operand (stream, XEXP (x, 1), 0);
1212 int num = exact_log2 (INTVAL (x));
1213 gcc_assert (num >= 0);
1214 fprintf (stream, "#%d", num);
1220 int num = exact_log2 (~INTVAL (x));
1221 gcc_assert (num >= 0);
1222 fprintf (stream, "#%d", num);
1227 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1229 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1233 if (x == CONST0_RTX (GET_MODE (x)))
1235 fprintf ((stream), "r63");
1238 goto default_output;
1240 if (CONST_INT_P (x))
1242 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1250 mode = GET_MODE (x);
1252 switch (GET_CODE (x))
1256 rtx inner = XEXP (x, 0);
1258 enum machine_mode inner_mode;
1260 /* We might see SUBREGs with vector mode registers inside. */
1261 if (GET_CODE (inner) == SUBREG
1262 && (GET_MODE_SIZE (GET_MODE (inner))
1263 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1264 && subreg_lowpart_p (inner))
1265 inner = SUBREG_REG (inner);
1266 if (CONST_INT_P (inner))
1268 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1269 goto default_output;
1271 inner_mode = GET_MODE (inner);
1272 if (GET_CODE (inner) == SUBREG
1273 && (GET_MODE_SIZE (GET_MODE (inner))
1274 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1275 && REG_P (SUBREG_REG (inner)))
1277 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1278 GET_MODE (SUBREG_REG (inner)),
1279 SUBREG_BYTE (inner),
1281 inner = SUBREG_REG (inner);
1283 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1285 /* Floating point register pairs are always big endian;
1286 general purpose registers are 64 bit wide. */
1287 regno = REGNO (inner);
1288 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1289 - HARD_REGNO_NREGS (regno, mode))
1297 /* FIXME: We need this on SHmedia32 because reload generates
1298 some sign-extended HI or QI loads into DImode registers
1299 but, because Pmode is SImode, the address ends up with a
1300 subreg:SI of the DImode register. Maybe reload should be
1301 fixed so as to apply alter_subreg to such loads? */
1303 gcc_assert (trapping_target_operand (x, VOIDmode));
1304 x = XEXP (XEXP (x, 2), 0);
1305 goto default_output;
1307 gcc_assert (SUBREG_BYTE (x) == 0
1308 && REG_P (SUBREG_REG (x)));
1316 if (FP_REGISTER_P (regno)
1317 && mode == V16SFmode)
1318 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1319 else if (FP_REGISTER_P (REGNO (x))
1320 && mode == V4SFmode)
1321 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1323 && mode == V2SFmode)
1324 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1325 else if (FP_REGISTER_P (REGNO (x))
1326 && GET_MODE_SIZE (mode) > 4)
1327 fprintf ((stream), "d%s", reg_names[regno] + 1);
1329 fputs (reg_names[regno], (stream));
1333 output_address (XEXP (x, 0));
1338 fputc ('#', stream);
1339 output_addr_const (stream, x);
1347 /* Encode symbol attributes of a SYMBOL_REF into its
1348 SYMBOL_REF_FLAGS. */
1350 sh_encode_section_info (tree decl, rtx rtl, int first)
1352 default_encode_section_info (decl, rtl, first);
1354 if (TREE_CODE (decl) == FUNCTION_DECL
1355 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1356 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1359 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1361 force_into (rtx value, rtx target)
1363 value = force_operand (value, target);
1364 if (! rtx_equal_p (value, target))
1365 emit_insn (gen_move_insn (target, value));
1368 /* Emit code to perform a block move. Choose the best method.
1370 OPERANDS[0] is the destination.
1371 OPERANDS[1] is the source.
1372 OPERANDS[2] is the size.
1373 OPERANDS[3] is the alignment safe to use. */
1376 expand_block_move (rtx *operands)
1378 int align = INTVAL (operands[3]);
1379 int constp = (CONST_INT_P (operands[2]));
1380 int bytes = (constp ? INTVAL (operands[2]) : 0);
1385 /* If we could use mov.l to move words and dest is word-aligned, we
1386 can use movua.l for loads and still generate a relatively short
1387 and efficient sequence. */
1388 if (TARGET_SH4A_ARCH && align < 4
1389 && MEM_ALIGN (operands[0]) >= 32
1390 && can_move_by_pieces (bytes, 32))
1392 rtx dest = copy_rtx (operands[0]);
1393 rtx src = copy_rtx (operands[1]);
1394 /* We could use different pseudos for each copied word, but
1395 since movua can only load into r0, it's kind of
1397 rtx temp = gen_reg_rtx (SImode);
1398 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1401 while (copied + 4 <= bytes)
1403 rtx to = adjust_address (dest, SImode, copied);
1404 rtx from = adjust_automodify_address (src, BLKmode,
1407 set_mem_size (from, GEN_INT (4));
1408 emit_insn (gen_movua (temp, from));
1409 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1410 emit_move_insn (to, temp);
1415 move_by_pieces (adjust_address (dest, BLKmode, copied),
1416 adjust_automodify_address (src, BLKmode,
1418 bytes - copied, align, 0);
1423 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1424 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1425 if (align < 4 || (bytes % 4 != 0))
1428 if (TARGET_HARD_SH4)
1432 else if (bytes == 12)
1434 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1435 rtx r4 = gen_rtx_REG (SImode, 4);
1436 rtx r5 = gen_rtx_REG (SImode, 5);
1438 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1439 force_into (XEXP (operands[0], 0), r4);
1440 force_into (XEXP (operands[1], 0), r5);
1441 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1444 else if (! TARGET_SMALLCODE)
1446 const char *entry_name;
1447 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1449 rtx r4 = gen_rtx_REG (SImode, 4);
1450 rtx r5 = gen_rtx_REG (SImode, 5);
1451 rtx r6 = gen_rtx_REG (SImode, 6);
1453 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1454 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1455 force_into (XEXP (operands[0], 0), r4);
1456 force_into (XEXP (operands[1], 0), r5);
1458 dwords = bytes >> 3;
1459 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1460 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1469 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1470 rtx r4 = gen_rtx_REG (SImode, 4);
1471 rtx r5 = gen_rtx_REG (SImode, 5);
1473 sprintf (entry, "__movmemSI%d", bytes);
1474 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1475 force_into (XEXP (operands[0], 0), r4);
1476 force_into (XEXP (operands[1], 0), r5);
1477 emit_insn (gen_block_move_real (func_addr_rtx));
1481 /* This is the same number of bytes as a memcpy call, but to a different
1482 less common function name, so this will occasionally use more space. */
1483 if (! TARGET_SMALLCODE)
1485 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1486 int final_switch, while_loop;
1487 rtx r4 = gen_rtx_REG (SImode, 4);
1488 rtx r5 = gen_rtx_REG (SImode, 5);
1489 rtx r6 = gen_rtx_REG (SImode, 6);
1491 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1492 force_into (XEXP (operands[0], 0), r4);
1493 force_into (XEXP (operands[1], 0), r5);
1495 /* r6 controls the size of the move. 16 is decremented from it
1496 for each 64 bytes moved. Then the negative bit left over is used
1497 as an index into a list of move instructions. e.g., a 72 byte move
1498 would be set up with size(r6) = 14, for one iteration through the
1499 big while loop, and a switch of -2 for the last part. */
1501 final_switch = 16 - ((bytes / 4) % 16);
1502 while_loop = ((bytes / 4) / 16 - 1) * 16;
1503 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1504 emit_insn (gen_block_lump_real (func_addr_rtx));
1511 /* Prepare operands for a move define_expand; specifically, one of the
1512 operands must be in a register. */
1515 prepare_move_operands (rtx operands[], enum machine_mode mode)
1517 if ((mode == SImode || mode == DImode)
1519 && ! ((mode == Pmode || mode == ptr_mode)
1520 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1523 if (SYMBOLIC_CONST_P (operands[1]))
1525 if (MEM_P (operands[0]))
1526 operands[1] = force_reg (Pmode, operands[1]);
1527 else if (TARGET_SHMEDIA
1528 && GET_CODE (operands[1]) == LABEL_REF
1529 && target_reg_operand (operands[0], mode))
1533 temp = (!can_create_pseudo_p ()
1535 : gen_reg_rtx (Pmode));
1536 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1539 else if (GET_CODE (operands[1]) == CONST
1540 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1541 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1543 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1544 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1546 operands[1] = expand_binop (mode, add_optab, temp,
1547 XEXP (XEXP (operands[1], 0), 1),
1548 (!can_create_pseudo_p ()
1550 : gen_reg_rtx (Pmode)),
1551 0, OPTAB_LIB_WIDEN);
1555 if (! reload_in_progress && ! reload_completed)
1557 /* Copy the source to a register if both operands aren't registers. */
1558 if (! register_operand (operands[0], mode)
1559 && ! sh_register_operand (operands[1], mode))
1560 operands[1] = copy_to_mode_reg (mode, operands[1]);
1562 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1564 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1565 except that we can't use that function because it is static. */
1566 rtx new_rtx = change_address (operands[0], mode, 0);
1567 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1568 operands[0] = new_rtx;
1571 /* This case can happen while generating code to move the result
1572 of a library call to the target. Reject `st r0,@(rX,rY)' because
1573 reload will fail to find a spill register for rX, since r0 is already
1574 being used for the source. */
1576 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1577 && MEM_P (operands[0])
1578 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1579 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1580 operands[1] = copy_to_mode_reg (mode, operands[1]);
1583 if (mode == Pmode || mode == ptr_mode)
1586 enum tls_model tls_kind;
1590 if (GET_CODE (op1) == CONST
1591 && GET_CODE (XEXP (op1, 0)) == PLUS
1592 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1595 opc = XEXP (XEXP (op1, 0), 1);
1596 op1 = XEXP (XEXP (op1, 0), 0);
1601 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1603 rtx tga_op1, tga_ret, tmp, tmp2;
1607 case TLS_MODEL_GLOBAL_DYNAMIC:
1608 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1609 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1613 case TLS_MODEL_LOCAL_DYNAMIC:
1614 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1615 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1617 tmp = gen_reg_rtx (Pmode);
1618 emit_move_insn (tmp, tga_ret);
1620 if (register_operand (op0, Pmode))
1623 tmp2 = gen_reg_rtx (Pmode);
1625 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1629 case TLS_MODEL_INITIAL_EXEC:
1632 /* Don't schedule insns for getting GOT address when
1633 the first scheduling is enabled, to avoid spill
1635 if (flag_schedule_insns)
1636 emit_insn (gen_blockage ());
1637 emit_insn (gen_GOTaddr2picreg ());
1638 emit_use (gen_rtx_REG (SImode, PIC_REG));
1639 if (flag_schedule_insns)
1640 emit_insn (gen_blockage ());
1642 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1643 tmp = gen_sym2GOTTPOFF (op1);
1644 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1648 case TLS_MODEL_LOCAL_EXEC:
1649 tmp2 = gen_reg_rtx (Pmode);
1650 emit_insn (gen_load_gbr (tmp2));
1651 tmp = gen_reg_rtx (Pmode);
1652 emit_insn (gen_symTPOFF2reg (tmp, op1));
1654 if (register_operand (op0, Pmode))
1657 op1 = gen_reg_rtx (Pmode);
1659 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1666 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1675 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1676 enum rtx_code comparison)
1679 rtx scratch = NULL_RTX;
1681 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1682 comparison = GET_CODE (operands[0]);
1684 scratch = operands[4];
1685 if (CONST_INT_P (operands[1])
1686 && !CONST_INT_P (operands[2]))
1688 rtx tmp = operands[1];
1690 operands[1] = operands[2];
1692 comparison = swap_condition (comparison);
1694 if (CONST_INT_P (operands[2]))
1696 HOST_WIDE_INT val = INTVAL (operands[2]);
1697 if ((val == -1 || val == -0x81)
1698 && (comparison == GT || comparison == LE))
1700 comparison = (comparison == GT) ? GE : LT;
1701 operands[2] = gen_int_mode (val + 1, mode);
1703 else if ((val == 1 || val == 0x80)
1704 && (comparison == GE || comparison == LT))
1706 comparison = (comparison == GE) ? GT : LE;
1707 operands[2] = gen_int_mode (val - 1, mode);
1709 else if (val == 1 && (comparison == GEU || comparison == LTU))
1711 comparison = (comparison == GEU) ? NE : EQ;
1712 operands[2] = CONST0_RTX (mode);
1714 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1716 comparison = (comparison == GEU) ? GTU : LEU;
1717 operands[2] = gen_int_mode (val - 1, mode);
1719 else if (val == 0 && (comparison == GTU || comparison == LEU))
1720 comparison = (comparison == GTU) ? NE : EQ;
1721 else if (mode == SImode
1722 && ((val == 0x7fffffff
1723 && (comparison == GTU || comparison == LEU))
1724 || ((unsigned HOST_WIDE_INT) val
1725 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1726 && (comparison == GEU || comparison == LTU))))
1728 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1729 operands[2] = CONST0_RTX (mode);
1733 if (can_create_pseudo_p ())
1734 operands[1] = force_reg (mode, op1);
1735 /* When we are handling DImode comparisons, we want to keep constants so
1736 that we can optimize the component comparisons; however, memory loads
1737 are better issued as a whole so that they can be scheduled well.
1738 SImode equality comparisons allow I08 constants, but only when they
1739 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1740 into a register, that register might as well be r0, and we allow the
1741 constant. If it is already in a register, this is likely to be
1742 allocated to a different hard register, thus we load the constant into
1743 a register unless it is zero. */
1744 if (!REG_P (operands[2])
1745 && (!CONST_INT_P (operands[2])
1746 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1747 && ((comparison != EQ && comparison != NE)
1748 || (REG_P (op1) && REGNO (op1) != R0_REG)
1749 || !satisfies_constraint_I08 (operands[2])))))
1751 if (scratch && GET_MODE (scratch) == mode)
1753 emit_move_insn (scratch, operands[2]);
1754 operands[2] = scratch;
1756 else if (can_create_pseudo_p ())
1757 operands[2] = force_reg (mode, operands[2]);
1763 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1765 rtx (*branch_expander) (rtx) = gen_branch_true;
1768 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1771 case NE: case LT: case LE: case LTU: case LEU:
1772 comparison = reverse_condition (comparison);
1773 branch_expander = gen_branch_false;
1776 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1777 gen_rtx_fmt_ee (comparison, SImode,
1778 operands[1], operands[2])));
1779 jump = emit_jump_insn (branch_expander (operands[3]));
1780 if (probability >= 0)
1781 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1785 /* ??? How should we distribute probabilities when more than one branch
1786 is generated. So far we only have soem ad-hoc observations:
1787 - If the operands are random, they are likely to differ in both parts.
1788 - If comparing items in a hash chain, the operands are random or equal;
1789 operation should be EQ or NE.
1790 - If items are searched in an ordered tree from the root, we can expect
1791 the highpart to be unequal about half of the time; operation should be
1792 an inequality comparison, operands non-constant, and overall probability
1793 about 50%. Likewise for quicksort.
1794 - Range checks will be often made against constants. Even if we assume for
1795 simplicity an even distribution of the non-constant operand over a
1796 sub-range here, the same probability could be generated with differently
1797 wide sub-ranges - as long as the ratio of the part of the subrange that
1798 is before the threshold to the part that comes after the threshold stays
1799 the same. Thus, we can't really tell anything here;
1800 assuming random distribution is at least simple.
1804 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1806 enum rtx_code msw_taken, msw_skip, lsw_taken;
1807 rtx skip_label = NULL_RTX;
1808 rtx op1h, op1l, op2h, op2l;
1811 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1812 rtx scratch = operands[4];
1814 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1815 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1816 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1817 op1l = gen_lowpart (SImode, operands[1]);
1818 op2l = gen_lowpart (SImode, operands[2]);
1819 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1820 prob = split_branch_probability;
1821 rev_prob = REG_BR_PROB_BASE - prob;
1824 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1825 That costs 1 cycle more when the first branch can be predicted taken,
1826 but saves us mispredicts because only one branch needs prediction.
1827 It also enables generating the cmpeqdi_t-1 pattern. */
1829 if (TARGET_CMPEQDI_T)
1831 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1832 emit_jump_insn (gen_branch_true (operands[3]));
1839 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1841 msw_skip_prob = rev_prob;
1842 if (REG_BR_PROB_BASE <= 65535)
1843 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1846 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1850 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1851 / ((HOST_WIDEST_INT) prob << 32)))
1857 if (TARGET_CMPEQDI_T)
1859 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1860 emit_jump_insn (gen_branch_false (operands[3]));
1864 msw_taken_prob = prob;
1869 msw_taken = comparison;
1870 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1872 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1873 msw_skip = swap_condition (msw_taken);
1877 if (op2l == CONST0_RTX (SImode))
1878 msw_taken = comparison;
1881 msw_taken = comparison == GE ? GT : GTU;
1882 msw_skip = swap_condition (msw_taken);
1887 msw_taken = comparison;
1888 if (op2l == CONST0_RTX (SImode))
1890 msw_skip = swap_condition (msw_taken);
1894 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1895 msw_taken = comparison;
1899 if (comparison == LE)
1901 else if (op2h != CONST0_RTX (SImode))
1905 msw_skip = swap_condition (msw_taken);
1908 default: return false;
1910 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1911 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1912 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1913 if (comparison != EQ && comparison != NE && num_branches > 1)
1915 if (!CONSTANT_P (operands[2])
1916 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1917 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1919 msw_taken_prob = prob / 2U;
1921 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1922 lsw_taken_prob = prob;
1926 msw_taken_prob = prob;
1927 msw_skip_prob = REG_BR_PROB_BASE;
1928 /* ??? If we have a constant op2h, should we use that when
1929 calculating lsw_taken_prob? */
1930 lsw_taken_prob = prob;
1935 operands[4] = NULL_RTX;
1936 if (reload_completed
1937 && ! arith_reg_or_0_operand (op2h, SImode)
1938 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1939 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1940 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1942 emit_move_insn (scratch, operands[2]);
1943 operands[2] = scratch;
1945 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1946 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
1947 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1949 rtx taken_label = operands[3];
1951 /* Operands were possibly modified, but msw_skip doesn't expect this.
1952 Always use the original ones. */
1953 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
1959 operands[3] = skip_label = gen_label_rtx ();
1960 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
1961 operands[3] = taken_label;
1965 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
1967 if (reload_completed
1968 && ! arith_reg_or_0_operand (op2l, SImode)
1969 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
1971 emit_move_insn (scratch, operands[2]);
1972 operands[2] = scratch;
1974 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
1976 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1977 emit_label (skip_label);
1981 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
1984 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
1986 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
1988 insn = gen_rtx_PARALLEL (VOIDmode,
1990 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
1991 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
1997 /* Prepare the operands for an scc instruction; make sure that the
1998 compare has been done and the result is in T_REG. */
2000 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2002 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2003 enum rtx_code oldcode = code;
2004 enum machine_mode mode;
2006 /* First need a compare insn. */
2010 /* It isn't possible to handle this case. */
2027 if (code != oldcode)
2034 mode = GET_MODE (op0);
2035 if (mode == VOIDmode)
2036 mode = GET_MODE (op1);
2038 op0 = force_reg (mode, op0);
2039 if ((code != EQ && code != NE
2040 && (op1 != const0_rtx
2041 || code == GTU || code == GEU || code == LTU || code == LEU))
2042 || (mode == DImode && op1 != const0_rtx)
2043 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2044 op1 = force_reg (mode, op1);
2046 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2047 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2052 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2055 rtx target = gen_reg_rtx (SImode);
2058 gcc_assert (TARGET_SHMEDIA);
2067 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2068 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2078 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2079 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2097 rtx t2 = gen_reg_rtx (DImode);
2098 emit_insn (gen_extendsidi2 (t2, target));
2102 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2105 /* Called from the md file, set up the operands of a compare instruction. */
2108 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2110 enum rtx_code code = GET_CODE (operands[0]);
2111 enum rtx_code branch_code;
2112 rtx op0 = operands[1];
2113 rtx op1 = operands[2];
2115 bool need_ccmpeq = false;
2117 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2119 op0 = force_reg (mode, op0);
2120 op1 = force_reg (mode, op1);
2124 if (code != EQ || mode == DImode)
2126 /* Force args into regs, since we can't use constants here. */
2127 op0 = force_reg (mode, op0);
2128 if (op1 != const0_rtx || code == GTU || code == GEU)
2129 op1 = force_reg (mode, op1);
2133 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2136 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2137 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2139 tem = op0, op0 = op1, op1 = tem;
2140 code = swap_condition (code);
2143 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2146 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2151 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2152 to EQ/GT respectively. */
2153 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2170 branch_code = reverse_condition (code);
2176 insn = gen_rtx_SET (VOIDmode,
2177 gen_rtx_REG (SImode, T_REG),
2178 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2180 sh_emit_set_t_insn (insn, mode);
2182 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2184 if (branch_code == code)
2185 emit_jump_insn (gen_branch_true (operands[3]));
2187 emit_jump_insn (gen_branch_false (operands[3]));
2191 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2193 enum rtx_code code = GET_CODE (operands[1]);
2194 rtx op0 = operands[2];
2195 rtx op1 = operands[3];
2197 bool invert = false;
2200 op0 = force_reg (mode, op0);
2201 if ((code != EQ && code != NE
2202 && (op1 != const0_rtx
2203 || code == GTU || code == GEU || code == LTU || code == LEU))
2204 || (mode == DImode && op1 != const0_rtx)
2205 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2206 op1 = force_reg (mode, op1);
2208 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2210 if (code == LT || code == LE)
2212 code = swap_condition (code);
2213 tem = op0, op0 = op1, op1 = tem;
2219 lab = gen_label_rtx ();
2220 sh_emit_scc_to_t (EQ, op0, op1);
2221 emit_jump_insn (gen_branch_true (lab));
2238 sh_emit_scc_to_t (code, op0, op1);
2242 emit_insn (gen_movnegt (operands[0]));
2244 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2247 /* Functions to output assembly code. */
2249 /* Return a sequence of instructions to perform DI or DF move.
2251 Since the SH cannot move a DI or DF in one instruction, we have
2252 to take care when we see overlapping source and dest registers. */
2255 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2256 enum machine_mode mode)
2258 rtx dst = operands[0];
2259 rtx src = operands[1];
2262 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2263 return "mov.l %T1,%0\n\tmov.l %1,%0";
2265 if (register_operand (dst, mode)
2266 && register_operand (src, mode))
2268 if (REGNO (src) == MACH_REG)
2269 return "sts mach,%S0\n\tsts macl,%R0";
2271 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2272 when mov.d r1,r0 do r1->r0 then r2->r1. */
2274 if (REGNO (src) + 1 == REGNO (dst))
2275 return "mov %T1,%T0\n\tmov %1,%0";
2277 return "mov %1,%0\n\tmov %T1,%T0";
2279 else if (CONST_INT_P (src))
2281 if (INTVAL (src) < 0)
2282 output_asm_insn ("mov #-1,%S0", operands);
2284 output_asm_insn ("mov #0,%S0", operands);
2286 return "mov %1,%R0";
2288 else if (MEM_P (src))
2291 int dreg = REGNO (dst);
2292 rtx inside = XEXP (src, 0);
2294 switch (GET_CODE (inside))
2297 ptrreg = REGNO (inside);
2301 ptrreg = subreg_regno (inside);
2305 ptrreg = REGNO (XEXP (inside, 0));
2306 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2307 an offsettable address. Unfortunately, offsettable addresses use
2308 QImode to check the offset, and a QImode offsettable address
2309 requires r0 for the other operand, which is not currently
2310 supported, so we can't use the 'o' constraint.
2311 Thus we must check for and handle r0+REG addresses here.
2312 We punt for now, since this is likely very rare. */
2313 gcc_assert (!REG_P (XEXP (inside, 1)));
2317 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2319 return "mov.l %1,%0\n\tmov.l %1,%T0";
2324 /* Work out the safe way to copy. Copy into the second half first. */
2326 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2329 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2332 /* Print an instruction which would have gone into a delay slot after
2333 another instruction, but couldn't because the other instruction expanded
2334 into a sequence where putting the slot insn at the end wouldn't work. */
2337 print_slot (rtx insn)
2339 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2341 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2345 output_far_jump (rtx insn, rtx op)
2347 struct { rtx lab, reg, op; } this_jmp;
2348 rtx braf_base_lab = NULL_RTX;
2351 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2354 this_jmp.lab = gen_label_rtx ();
2358 && offset - get_attr_length (insn) <= 32766)
2361 jump = "mov.w %O0,%1; braf %1";
2369 jump = "mov.l %O0,%1; braf %1";
2371 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2374 jump = "mov.l %O0,%1; jmp @%1";
2376 /* If we have a scratch register available, use it. */
2377 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2378 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2380 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2381 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2382 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2383 output_asm_insn (jump, &this_jmp.lab);
2384 if (dbr_sequence_length ())
2385 print_slot (final_sequence);
2387 output_asm_insn ("nop", 0);
2391 /* Output the delay slot insn first if any. */
2392 if (dbr_sequence_length ())
2393 print_slot (final_sequence);
2395 this_jmp.reg = gen_rtx_REG (SImode, 13);
2396 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2397 Fortunately, MACL is fixed and call-clobbered, and we never
2398 need its value across jumps, so save r13 in it instead of in
2401 output_asm_insn ("lds r13, macl", 0);
2403 output_asm_insn ("mov.l r13,@-r15", 0);
2404 output_asm_insn (jump, &this_jmp.lab);
2406 output_asm_insn ("sts macl, r13", 0);
2408 output_asm_insn ("mov.l @r15+,r13", 0);
2410 if (far && flag_pic && TARGET_SH2)
2412 braf_base_lab = gen_label_rtx ();
2413 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2414 CODE_LABEL_NUMBER (braf_base_lab));
2417 output_asm_insn (".align 2", 0);
2418 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2420 if (far && flag_pic)
2423 this_jmp.lab = braf_base_lab;
2424 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2427 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2431 /* Local label counter, used for constants in the pool and inside
2432 pattern branches. */
2434 static int lf = 100;
2436 /* Output code for ordinary branches. */
2439 output_branch (int logic, rtx insn, rtx *operands)
2441 switch (get_attr_length (insn))
2444 /* This can happen if filling the delay slot has caused a forward
2445 branch to exceed its range (we could reverse it, but only
2446 when we know we won't overextend other branches; this should
2447 best be handled by relaxation).
2448 It can also happen when other condbranches hoist delay slot insn
2449 from their destination, thus leading to code size increase.
2450 But the branch will still be in the range -4092..+4098 bytes. */
2455 /* The call to print_slot will clobber the operands. */
2456 rtx op0 = operands[0];
2458 /* If the instruction in the delay slot is annulled (true), then
2459 there is no delay slot where we can put it now. The only safe
2460 place for it is after the label. final will do that by default. */
2463 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2464 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2466 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2467 ASSEMBLER_DIALECT ? "/" : ".", label);
2468 print_slot (final_sequence);
2471 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2473 output_asm_insn ("bra\t%l0", &op0);
2474 fprintf (asm_out_file, "\tnop\n");
2475 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2479 /* When relaxing, handle this like a short branch. The linker
2480 will fix it up if it still doesn't fit after relaxation. */
2482 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2484 /* These are for SH2e, in which we have to account for the
2485 extra nop because of the hardware bug in annulled branches. */
2491 gcc_assert (!final_sequence
2492 || !(INSN_ANNULLED_BRANCH_P
2493 (XVECEXP (final_sequence, 0, 0))));
2494 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2496 ASSEMBLER_DIALECT ? "/" : ".", label);
2497 fprintf (asm_out_file, "\tnop\n");
2498 output_asm_insn ("bra\t%l0", operands);
2499 fprintf (asm_out_file, "\tnop\n");
2500 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2504 /* When relaxing, fall through. */
2509 sprintf (buffer, "b%s%ss\t%%l0",
2511 ASSEMBLER_DIALECT ? "/" : ".");
2512 output_asm_insn (buffer, &operands[0]);
2517 /* There should be no longer branches now - that would
2518 indicate that something has destroyed the branches set
2519 up in machine_dependent_reorg. */
2524 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2525 fill in operands 9 as a label to the successor insn.
2526 We try to use jump threading where possible.
2527 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2528 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2529 follow jmp and bt, if the address is in range. */
2531 output_branchy_insn (enum rtx_code code, const char *templ,
2532 rtx insn, rtx *operands)
2534 rtx next_insn = NEXT_INSN (insn);
2536 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2538 rtx src = SET_SRC (PATTERN (next_insn));
2539 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2541 /* Following branch not taken */
2542 operands[9] = gen_label_rtx ();
2543 emit_label_after (operands[9], next_insn);
2544 INSN_ADDRESSES_NEW (operands[9],
2545 INSN_ADDRESSES (INSN_UID (next_insn))
2546 + get_attr_length (next_insn));
2551 int offset = (branch_dest (next_insn)
2552 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2553 if (offset >= -252 && offset <= 258)
2555 if (GET_CODE (src) == IF_THEN_ELSE)
2557 src = XEXP (src, 1);
2563 operands[9] = gen_label_rtx ();
2564 emit_label_after (operands[9], insn);
2565 INSN_ADDRESSES_NEW (operands[9],
2566 INSN_ADDRESSES (INSN_UID (insn))
2567 + get_attr_length (insn));
2572 output_ieee_ccmpeq (rtx insn, rtx *operands)
2574 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2578 /* Output the start of the assembler file. */
2581 sh_file_start (void)
2583 default_file_start ();
2586 /* Declare the .directive section before it is used. */
2587 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2588 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2592 /* We need to show the text section with the proper
2593 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2594 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2595 will complain. We can teach GAS specifically about the
2596 default attributes for our choice of text section, but
2597 then we would have to change GAS again if/when we change
2598 the text section name. */
2599 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2601 /* Switch to the data section so that the coffsem symbol
2602 isn't in the text section. */
2603 switch_to_section (data_section);
2605 if (TARGET_LITTLE_ENDIAN)
2606 fputs ("\t.little\n", asm_out_file);
2610 if (TARGET_SHCOMPACT)
2611 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2612 else if (TARGET_SHMEDIA)
2613 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2614 TARGET_SHMEDIA64 ? 64 : 32);
2618 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2621 unspec_caller_rtx_p (rtx pat)
2626 split_const (pat, &base, &offset);
2627 if (GET_CODE (base) == UNSPEC)
2629 if (XINT (base, 1) == UNSPEC_CALLER)
2631 for (i = 0; i < XVECLEN (base, 0); i++)
2632 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2638 /* Indicate that INSN cannot be duplicated. This is true for insn
2639 that generates a unique label. */
2642 sh_cannot_copy_insn_p (rtx insn)
2646 if (!reload_completed || !flag_pic)
2649 if (!NONJUMP_INSN_P (insn))
2651 if (asm_noperands (insn) >= 0)
2654 pat = PATTERN (insn);
2655 if (GET_CODE (pat) != SET)
2657 pat = SET_SRC (pat);
2659 if (unspec_caller_rtx_p (pat))
2665 /* Actual number of instructions used to make a shift by N. */
2666 static const char ashiftrt_insns[] =
2667 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2669 /* Left shift and logical right shift are the same. */
2670 static const char shift_insns[] =
2671 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2673 /* Individual shift amounts needed to get the above length sequences.
2674 One bit right shifts clobber the T bit, so when possible, put one bit
2675 shifts in the middle of the sequence, so the ends are eligible for
2676 branch delay slots. */
2677 static const short shift_amounts[32][5] = {
2678 {0}, {1}, {2}, {2, 1},
2679 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2680 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2681 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2682 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2683 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2684 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2685 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2687 /* Likewise, but for shift amounts < 16, up to three highmost bits
2688 might be clobbered. This is typically used when combined with some
2689 kind of sign or zero extension. */
2691 static const char ext_shift_insns[] =
2692 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2694 static const short ext_shift_amounts[32][4] = {
2695 {0}, {1}, {2}, {2, 1},
2696 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2697 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2698 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2699 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2700 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2701 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2702 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2704 /* Assuming we have a value that has been sign-extended by at least one bit,
2705 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2706 to shift it by N without data loss, and quicker than by other means? */
2707 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2709 /* This is used in length attributes in sh.md to help compute the length
2710 of arbitrary constant shift instructions. */
2713 shift_insns_rtx (rtx insn)
2715 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2716 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2717 enum rtx_code shift_code = GET_CODE (set_src);
2722 return ashiftrt_insns[shift_count];
2725 return shift_insns[shift_count];
2731 /* Return the cost of a shift. */
2741 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2743 if (GET_MODE (x) == DImode
2744 && CONST_INT_P (XEXP (x, 1))
2745 && INTVAL (XEXP (x, 1)) == 1)
2748 /* Everything else is invalid, because there is no pattern for it. */
2751 /* If shift by a non constant, then this will be expensive. */
2752 if (!CONST_INT_P (XEXP (x, 1)))
2753 return SH_DYNAMIC_SHIFT_COST;
2755 /* Otherwise, return the true cost in instructions. Cope with out of range
2756 shift counts more or less arbitrarily. */
2757 value = INTVAL (XEXP (x, 1)) & 31;
2759 if (GET_CODE (x) == ASHIFTRT)
2761 int cost = ashiftrt_insns[value];
2762 /* If SH3, then we put the constant in a reg and use shad. */
2763 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2764 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2768 return shift_insns[value];
2771 /* Return the cost of an AND operation. */
2778 /* Anding with a register is a single cycle and instruction. */
2779 if (!CONST_INT_P (XEXP (x, 1)))
2782 i = INTVAL (XEXP (x, 1));
2786 if (satisfies_constraint_I10 (XEXP (x, 1))
2787 || satisfies_constraint_J16 (XEXP (x, 1)))
2790 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2793 /* These constants are single cycle extu.[bw] instructions. */
2794 if (i == 0xff || i == 0xffff)
2796 /* Constants that can be used in an and immediate instruction in a single
2797 cycle, but this requires r0, so make it a little more expensive. */
2798 if (CONST_OK_FOR_K08 (i))
2800 /* Constants that can be loaded with a mov immediate and an and.
2801 This case is probably unnecessary. */
2802 if (CONST_OK_FOR_I08 (i))
2804 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2805 This case is probably unnecessary. */
2809 /* Return the cost of an addition or a subtraction. */
2814 /* Adding a register is a single cycle insn. */
2815 if (REG_P (XEXP (x, 1))
2816 || GET_CODE (XEXP (x, 1)) == SUBREG)
2819 /* Likewise for small constants. */
2820 if (CONST_INT_P (XEXP (x, 1))
2821 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2825 switch (GET_CODE (XEXP (x, 1)))
2830 return TARGET_SHMEDIA64 ? 5 : 3;
2833 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2835 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2837 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2845 /* Any other constant requires a 2 cycle pc-relative load plus an
2850 /* Return the cost of a multiply. */
2852 multcosts (rtx x ATTRIBUTE_UNUSED)
2854 if (sh_multcost >= 0)
2857 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2858 accept constants. Ideally, we would use a cost of one or two and
2859 add the cost of the operand, but disregard the latter when inside loops
2860 and loop invariant code motion is still to follow.
2861 Using a multiply first and splitting it later if it's a loss
2862 doesn't work because of different sign / zero extension semantics
2863 of multiplies vs. shifts. */
2864 return TARGET_SMALLCODE ? 2 : 3;
2868 /* We have a mul insn, so we can never take more than the mul and the
2869 read of the mac reg, but count more because of the latency and extra
2871 if (TARGET_SMALLCODE)
2876 /* If we're aiming at small code, then just count the number of
2877 insns in a multiply call sequence. */
2878 if (TARGET_SMALLCODE)
2881 /* Otherwise count all the insns in the routine we'd be calling too. */
2885 /* Compute a (partial) cost for rtx X. Return true if the complete
2886 cost has been computed, and false if subexpressions should be
2887 scanned. In either case, *TOTAL contains the cost result. */
2890 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2891 bool speed ATTRIBUTE_UNUSED)
2898 if (INTVAL (x) == 0)
2900 else if (outer_code == AND && and_operand ((x), DImode))
2902 else if ((outer_code == IOR || outer_code == XOR
2903 || outer_code == PLUS)
2904 && CONST_OK_FOR_I10 (INTVAL (x)))
2906 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2907 *total = COSTS_N_INSNS (outer_code != SET);
2908 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2909 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2910 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2911 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2913 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2916 if (CONST_OK_FOR_I08 (INTVAL (x)))
2918 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2919 && CONST_OK_FOR_K08 (INTVAL (x)))
2921 /* prepare_cmp_insn will force costly constants int registers before
2922 the cbranch[sd]i4 patterns can see them, so preserve potentially
2923 interesting ones not covered by I08 above. */
2924 else if (outer_code == COMPARE
2925 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2926 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2927 || INTVAL (x) == 0x7fffffff
2928 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2937 if (TARGET_SHMEDIA64)
2938 *total = COSTS_N_INSNS (4);
2939 else if (TARGET_SHMEDIA32)
2940 *total = COSTS_N_INSNS (2);
2947 *total = COSTS_N_INSNS (4);
2948 /* prepare_cmp_insn will force costly constants int registers before
2949 the cbranchdi4 pattern can see them, so preserve potentially
2950 interesting ones. */
2951 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
2957 if (x == CONST0_RTX (GET_MODE (x)))
2959 else if (sh_1el_vec (x, VOIDmode))
2960 *total = outer_code != SET;
2961 if (sh_rep_vec (x, VOIDmode))
2962 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2963 + (outer_code != SET));
2964 *total = COSTS_N_INSNS (3) + (outer_code != SET);
2969 *total = COSTS_N_INSNS (addsubcosts (x));
2973 *total = COSTS_N_INSNS (andcosts (x));
2977 *total = COSTS_N_INSNS (multcosts (x));
2983 *total = COSTS_N_INSNS (shiftcosts (x));
2990 *total = COSTS_N_INSNS (20);
2994 if (sh_1el_vec (x, VOIDmode))
2995 *total = outer_code != SET;
2996 if (sh_rep_vec (x, VOIDmode))
2997 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
2998 + (outer_code != SET));
2999 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3012 /* Compute the cost of an address. For the SH, all valid addresses are
3013 the same cost. Use a slightly higher cost for reg + reg addressing,
3014 since it increases pressure on r0. */
3017 sh_address_cost (rtx X,
3018 bool speed ATTRIBUTE_UNUSED)
3020 return (GET_CODE (X) == PLUS
3021 && ! CONSTANT_P (XEXP (X, 1))
3022 && ! TARGET_SHMEDIA ? 1 : 0);
3025 /* Code to expand a shift. */
3028 gen_ashift (int type, int n, rtx reg)
3030 /* Negative values here come from the shift_amounts array. */
3043 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3047 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3049 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3052 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3057 /* Same for HImode */
3060 gen_ashift_hi (int type, int n, rtx reg)
3062 /* Negative values here come from the shift_amounts array. */
3076 /* We don't have HImode right shift operations because using the
3077 ordinary 32 bit shift instructions for that doesn't generate proper
3078 zero/sign extension.
3079 gen_ashift_hi is only called in contexts where we know that the
3080 sign extension works out correctly. */
3083 if (GET_CODE (reg) == SUBREG)
3085 offset = SUBREG_BYTE (reg);
3086 reg = SUBREG_REG (reg);
3088 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3092 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3097 /* Output RTL to split a constant shift into its component SH constant
3098 shift instructions. */
3101 gen_shifty_op (int code, rtx *operands)
3103 int value = INTVAL (operands[2]);
3106 /* Truncate the shift count in case it is out of bounds. */
3111 if (code == LSHIFTRT)
3113 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3114 emit_insn (gen_movt (operands[0]));
3117 else if (code == ASHIFT)
3119 /* There is a two instruction sequence for 31 bit left shifts,
3120 but it requires r0. */
3121 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3123 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3124 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3129 else if (value == 0)
3131 /* This can happen even when optimizing, if there were subregs before
3132 reload. Don't output a nop here, as this is never optimized away;
3133 use a no-op move instead. */
3134 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3138 max = shift_insns[value];
3139 for (i = 0; i < max; i++)
3140 gen_ashift (code, shift_amounts[value][i], operands[0]);
3143 /* Same as above, but optimized for values where the topmost bits don't
3147 gen_shifty_hi_op (int code, rtx *operands)
3149 int value = INTVAL (operands[2]);
3151 void (*gen_fun) (int, int, rtx);
3153 /* This operation is used by and_shl for SImode values with a few
3154 high bits known to be cleared. */
3158 emit_insn (gen_nop ());
3162 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3165 max = ext_shift_insns[value];
3166 for (i = 0; i < max; i++)
3167 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3170 /* When shifting right, emit the shifts in reverse order, so that
3171 solitary negative values come first. */
3172 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3173 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3176 /* Output RTL for an arithmetic right shift. */
3178 /* ??? Rewrite to use super-optimizer sequences. */
3181 expand_ashiftrt (rtx *operands)
3189 if (!CONST_INT_P (operands[2]))
3191 rtx count = copy_to_mode_reg (SImode, operands[2]);
3192 emit_insn (gen_negsi2 (count, count));
3193 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3196 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3197 > 1 + SH_DYNAMIC_SHIFT_COST)
3200 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3201 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3205 if (!CONST_INT_P (operands[2]))
3208 value = INTVAL (operands[2]) & 31;
3212 /* If we are called from abs expansion, arrange things so that we
3213 we can use a single MT instruction that doesn't clobber the source,
3214 if LICM can hoist out the load of the constant zero. */
3215 if (currently_expanding_to_rtl)
3217 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3219 emit_insn (gen_mov_neg_si_t (operands[0]));
3222 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3225 else if (value >= 16 && value <= 19)
3227 wrk = gen_reg_rtx (SImode);
3228 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3231 gen_ashift (ASHIFTRT, 1, wrk);
3232 emit_move_insn (operands[0], wrk);
3235 /* Expand a short sequence inline, longer call a magic routine. */
3236 else if (value <= 5)
3238 wrk = gen_reg_rtx (SImode);
3239 emit_move_insn (wrk, operands[1]);
3241 gen_ashift (ASHIFTRT, 1, wrk);
3242 emit_move_insn (operands[0], wrk);
3246 wrk = gen_reg_rtx (Pmode);
3248 /* Load the value into an arg reg and call a helper. */
3249 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3250 sprintf (func, "__ashiftrt_r4_%d", value);
3251 function_symbol (wrk, func, SFUNC_STATIC);
3252 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3253 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3258 sh_dynamicalize_shift_p (rtx count)
3260 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3263 /* Try to find a good way to implement the combiner pattern
3264 [(set (match_operand:SI 0 "register_operand" "r")
3265 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3266 (match_operand:SI 2 "const_int_operand" "n"))
3267 (match_operand:SI 3 "const_int_operand" "n"))) .
3268 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3269 return 0 for simple right / left or left/right shift combination.
3270 return 1 for a combination of shifts with zero_extend.
3271 return 2 for a combination of shifts with an AND that needs r0.
3272 return 3 for a combination of shifts with an AND that needs an extra
3273 scratch register, when the three highmost bits of the AND mask are clear.
3274 return 4 for a combination of shifts with an AND that needs an extra
3275 scratch register, when any of the three highmost bits of the AND mask
3277 If ATTRP is set, store an initial right shift width in ATTRP[0],
3278 and the instruction length in ATTRP[1] . These values are not valid
3280 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3281 shift_amounts for the last shift value that is to be used before the
3284 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3286 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3287 int left = INTVAL (left_rtx), right;
3289 int cost, best_cost = 10000;
3290 int best_right = 0, best_len = 0;
3294 if (left < 0 || left > 31)
3296 if (CONST_INT_P (mask_rtx))
3297 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3299 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3300 /* Can this be expressed as a right shift / left shift pair? */
3301 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3302 right = exact_log2 (lsb);
3303 mask2 = ~(mask + lsb - 1);
3304 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3305 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3307 best_cost = shift_insns[right] + shift_insns[right + left];
3308 /* mask has no trailing zeroes <==> ! right */
3309 else if (! right && mask2 == ~(lsb2 - 1))
3311 int late_right = exact_log2 (lsb2);
3312 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3314 /* Try to use zero extend. */
3315 if (mask2 == ~(lsb2 - 1))
3319 for (width = 8; width <= 16; width += 8)
3321 /* Can we zero-extend right away? */
3322 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3325 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3326 if (cost < best_cost)
3337 /* ??? Could try to put zero extend into initial right shift,
3338 or even shift a bit left before the right shift. */
3339 /* Determine value of first part of left shift, to get to the
3340 zero extend cut-off point. */
3341 first = width - exact_log2 (lsb2) + right;
3342 if (first >= 0 && right + left - first >= 0)
3344 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3345 + ext_shift_insns[right + left - first];
3346 if (cost < best_cost)
3358 /* Try to use r0 AND pattern */
3359 for (i = 0; i <= 2; i++)
3363 if (! CONST_OK_FOR_K08 (mask >> i))
3365 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3366 if (cost < best_cost)
3371 best_len = cost - 1;
3374 /* Try to use a scratch register to hold the AND operand. */
3375 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3376 for (i = 0; i <= 2; i++)
3380 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3381 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3382 if (cost < best_cost)
3387 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3393 attrp[0] = best_right;
3394 attrp[1] = best_len;
3399 /* This is used in length attributes of the unnamed instructions
3400 corresponding to shl_and_kind return values of 1 and 2. */
3402 shl_and_length (rtx insn)
3404 rtx set_src, left_rtx, mask_rtx;
3407 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3408 left_rtx = XEXP (XEXP (set_src, 0), 1);
3409 mask_rtx = XEXP (set_src, 1);
3410 shl_and_kind (left_rtx, mask_rtx, attributes);
3411 return attributes[1];
3414 /* This is used in length attribute of the and_shl_scratch instruction. */
3417 shl_and_scr_length (rtx insn)
3419 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3420 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3421 rtx op = XEXP (set_src, 0);
3422 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3423 op = XEXP (XEXP (op, 0), 0);
3424 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3427 /* Generate rtl for instructions for which shl_and_kind advised a particular
3428 method of generating them, i.e. returned zero. */
3431 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3434 unsigned HOST_WIDE_INT mask;
3435 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3436 int right, total_shift;
3437 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3439 right = attributes[0];
3440 total_shift = INTVAL (left_rtx) + right;
3441 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3448 int first = attributes[2];
3453 emit_insn ((mask << right) <= 0xff
3454 ? gen_zero_extendqisi2 (dest,
3455 gen_lowpart (QImode, source))
3456 : gen_zero_extendhisi2 (dest,
3457 gen_lowpart (HImode, source)));
3461 emit_insn (gen_movsi (dest, source));
3465 operands[2] = GEN_INT (right);
3466 gen_shifty_hi_op (LSHIFTRT, operands);
3470 operands[2] = GEN_INT (first);
3471 gen_shifty_hi_op (ASHIFT, operands);
3472 total_shift -= first;
3476 emit_insn (mask <= 0xff
3477 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3478 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3479 if (total_shift > 0)
3481 operands[2] = GEN_INT (total_shift);
3482 gen_shifty_hi_op (ASHIFT, operands);
3487 shift_gen_fun = gen_shifty_op;
3489 /* If the topmost bit that matters is set, set the topmost bits
3490 that don't matter. This way, we might be able to get a shorter
3492 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3493 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3495 /* Don't expand fine-grained when combining, because that will
3496 make the pattern fail. */
3497 if (currently_expanding_to_rtl
3498 || reload_in_progress || reload_completed)
3502 /* Cases 3 and 4 should be handled by this split
3503 only while combining */
3504 gcc_assert (kind <= 2);
3507 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3510 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3515 operands[2] = GEN_INT (total_shift);
3516 shift_gen_fun (ASHIFT, operands);
3523 if (kind != 4 && total_shift < 16)
3525 neg = -ext_shift_amounts[total_shift][1];
3527 neg -= ext_shift_amounts[total_shift][2];
3531 emit_insn (gen_and_shl_scratch (dest, source,
3534 GEN_INT (total_shift + neg),
3536 emit_insn (gen_movsi (dest, dest));
3543 /* Try to find a good way to implement the combiner pattern
3544 [(set (match_operand:SI 0 "register_operand" "=r")
3545 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3546 (match_operand:SI 2 "const_int_operand" "n")
3547 (match_operand:SI 3 "const_int_operand" "n")
3549 (clobber (reg:SI T_REG))]
3550 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3551 return 0 for simple left / right shift combination.
3552 return 1 for left shift / 8 bit sign extend / left shift.
3553 return 2 for left shift / 16 bit sign extend / left shift.
3554 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3555 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3556 return 5 for left shift / 16 bit sign extend / right shift
3557 return 6 for < 8 bit sign extend / left shift.
3558 return 7 for < 8 bit sign extend / left shift / single right shift.
3559 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3562 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3564 int left, size, insize, ext;
3565 int cost = 0, best_cost;
3568 left = INTVAL (left_rtx);
3569 size = INTVAL (size_rtx);
3570 insize = size - left;
3571 gcc_assert (insize > 0);
3572 /* Default to left / right shift. */
3574 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3577 /* 16 bit shift / sign extend / 16 bit shift */
3578 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3579 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3580 below, by alternative 3 or something even better. */
3581 if (cost < best_cost)
3587 /* Try a plain sign extend between two shifts. */
3588 for (ext = 16; ext >= insize; ext -= 8)
3592 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3593 if (cost < best_cost)
3595 kind = ext / (unsigned) 8;
3599 /* Check if we can do a sloppy shift with a final signed shift
3600 restoring the sign. */
3601 if (EXT_SHIFT_SIGNED (size - ext))
3602 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3603 /* If not, maybe it's still cheaper to do the second shift sloppy,
3604 and do a final sign extend? */
3605 else if (size <= 16)
3606 cost = ext_shift_insns[ext - insize] + 1
3607 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3610 if (cost < best_cost)
3612 kind = ext / (unsigned) 8 + 2;
3616 /* Check if we can sign extend in r0 */
3619 cost = 3 + shift_insns[left];
3620 if (cost < best_cost)
3625 /* Try the same with a final signed shift. */
3628 cost = 3 + ext_shift_insns[left + 1] + 1;
3629 if (cost < best_cost)
3638 /* Try to use a dynamic shift. */
3639 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3640 if (cost < best_cost)
3651 /* Function to be used in the length attribute of the instructions
3652 implementing this pattern. */
3655 shl_sext_length (rtx insn)
3657 rtx set_src, left_rtx, size_rtx;
3660 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3661 left_rtx = XEXP (XEXP (set_src, 0), 1);
3662 size_rtx = XEXP (set_src, 1);
3663 shl_sext_kind (left_rtx, size_rtx, &cost);
3667 /* Generate rtl for this pattern */
3670 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3673 int left, size, insize, cost;
3676 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3677 left = INTVAL (left_rtx);
3678 size = INTVAL (size_rtx);
3679 insize = size - left;
3687 int ext = kind & 1 ? 8 : 16;
3688 int shift2 = size - ext;
3690 /* Don't expand fine-grained when combining, because that will
3691 make the pattern fail. */
3692 if (! currently_expanding_to_rtl
3693 && ! reload_in_progress && ! reload_completed)
3695 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3696 emit_insn (gen_movsi (dest, source));
3700 emit_insn (gen_movsi (dest, source));
3704 operands[2] = GEN_INT (ext - insize);
3705 gen_shifty_hi_op (ASHIFT, operands);
3708 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3709 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3714 operands[2] = GEN_INT (shift2);
3715 gen_shifty_op (ASHIFT, operands);
3722 if (EXT_SHIFT_SIGNED (shift2))
3724 operands[2] = GEN_INT (shift2 + 1);
3725 gen_shifty_op (ASHIFT, operands);
3726 operands[2] = const1_rtx;
3727 gen_shifty_op (ASHIFTRT, operands);
3730 operands[2] = GEN_INT (shift2);
3731 gen_shifty_hi_op (ASHIFT, operands);
3735 operands[2] = GEN_INT (-shift2);
3736 gen_shifty_hi_op (LSHIFTRT, operands);
3738 emit_insn (size <= 8
3739 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3740 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3747 if (! currently_expanding_to_rtl
3748 && ! reload_in_progress && ! reload_completed)
3749 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3753 operands[2] = GEN_INT (16 - insize);
3754 gen_shifty_hi_op (ASHIFT, operands);
3755 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3757 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3759 gen_ashift (ASHIFTRT, 1, dest);
3764 /* Don't expand fine-grained when combining, because that will
3765 make the pattern fail. */
3766 if (! currently_expanding_to_rtl
3767 && ! reload_in_progress && ! reload_completed)
3769 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3770 emit_insn (gen_movsi (dest, source));
3773 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3774 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3775 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3777 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3778 gen_shifty_op (ASHIFT, operands);
3780 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3788 /* Prefix a symbol_ref name with "datalabel". */
3791 gen_datalabel_ref (rtx sym)
3795 if (GET_CODE (sym) == LABEL_REF)
3796 return gen_rtx_CONST (GET_MODE (sym),
3797 gen_rtx_UNSPEC (GET_MODE (sym),
3801 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3803 str = XSTR (sym, 0);
3804 /* Share all SYMBOL_REF strings with the same value - that is important
3806 str = IDENTIFIER_POINTER (get_identifier (str));
3807 XSTR (sym, 0) = str;
3813 static alloc_pool label_ref_list_pool;
3815 typedef struct label_ref_list_d
3818 struct label_ref_list_d *next;
3819 } *label_ref_list_t;
3821 /* The SH cannot load a large constant into a register, constants have to
3822 come from a pc relative load. The reference of a pc relative load
3823 instruction must be less than 1k in front of the instruction. This
3824 means that we often have to dump a constant inside a function, and
3825 generate code to branch around it.
3827 It is important to minimize this, since the branches will slow things
3828 down and make things bigger.
3830 Worst case code looks like:
3848 We fix this by performing a scan before scheduling, which notices which
3849 instructions need to have their operands fetched from the constant table
3850 and builds the table.
3854 scan, find an instruction which needs a pcrel move. Look forward, find the
3855 last barrier which is within MAX_COUNT bytes of the requirement.
3856 If there isn't one, make one. Process all the instructions between
3857 the find and the barrier.
3859 In the above example, we can tell that L3 is within 1k of L1, so
3860 the first move can be shrunk from the 3 insn+constant sequence into
3861 just 1 insn, and the constant moved to L3 to make:
3872 Then the second move becomes the target for the shortening process. */
3876 rtx value; /* Value in table. */
3877 rtx label; /* Label of value. */
3878 label_ref_list_t wend; /* End of window. */
3879 enum machine_mode mode; /* Mode of value. */
3881 /* True if this constant is accessed as part of a post-increment
3882 sequence. Note that HImode constants are never accessed in this way. */
3883 bool part_of_sequence_p;
3886 /* The maximum number of constants that can fit into one pool, since
3887 constants in the range 0..510 are at least 2 bytes long, and in the
3888 range from there to 1018 at least 4 bytes. */
3890 #define MAX_POOL_SIZE 372
3891 static pool_node pool_vector[MAX_POOL_SIZE];
3892 static int pool_size;
3893 static rtx pool_window_label;
3894 static int pool_window_last;
3896 static int max_labelno_before_reorg;
3898 /* ??? If we need a constant in HImode which is the truncated value of a
3899 constant we need in SImode, we could combine the two entries thus saving
3900 two bytes. Is this common enough to be worth the effort of implementing
3903 /* ??? This stuff should be done at the same time that we shorten branches.
3904 As it is now, we must assume that all branches are the maximum size, and
3905 this causes us to almost always output constant pools sooner than
3908 /* Add a constant to the pool and return its label. */
3911 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3915 label_ref_list_t ref, newref;
3917 /* First see if we've already got it. */
3918 for (i = 0; i < pool_size; i++)
3920 if (x->code == pool_vector[i].value->code
3921 && mode == pool_vector[i].mode)
3923 if (x->code == CODE_LABEL)
3925 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3928 if (rtx_equal_p (x, pool_vector[i].value))
3933 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3935 new_rtx = gen_label_rtx ();
3936 LABEL_REFS (new_rtx) = pool_vector[i].label;
3937 pool_vector[i].label = lab = new_rtx;
3939 if (lab && pool_window_label)
3941 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3942 newref->label = pool_window_label;
3943 ref = pool_vector[pool_window_last].wend;
3945 pool_vector[pool_window_last].wend = newref;
3948 pool_window_label = new_rtx;
3949 pool_window_last = i;
3955 /* Need a new one. */
3956 pool_vector[pool_size].value = x;
3957 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
3960 pool_vector[pool_size - 1].part_of_sequence_p = true;
3963 lab = gen_label_rtx ();
3964 pool_vector[pool_size].mode = mode;
3965 pool_vector[pool_size].label = lab;
3966 pool_vector[pool_size].wend = NULL;
3967 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
3968 if (lab && pool_window_label)
3970 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3971 newref->label = pool_window_label;
3972 ref = pool_vector[pool_window_last].wend;
3974 pool_vector[pool_window_last].wend = newref;
3977 pool_window_label = lab;
3978 pool_window_last = pool_size;
3983 /* Output the literal table. START, if nonzero, is the first instruction
3984 this table is needed for, and also indicates that there is at least one
3985 casesi_worker_2 instruction; We have to emit the operand3 labels from
3986 these insns at a 4-byte aligned position. BARRIER is the barrier
3987 after which we are to place the table. */
3990 dump_table (rtx start, rtx barrier)
3996 label_ref_list_t ref;
3999 /* Do two passes, first time dump out the HI sized constants. */
4001 for (i = 0; i < pool_size; i++)
4003 pool_node *p = &pool_vector[i];
4005 if (p->mode == HImode)
4009 scan = emit_insn_after (gen_align_2 (), scan);
4012 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4013 scan = emit_label_after (lab, scan);
4014 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4016 for (ref = p->wend; ref; ref = ref->next)
4019 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4022 else if (p->mode == DFmode)
4030 scan = emit_insn_after (gen_align_4 (), scan);
4032 for (; start != barrier; start = NEXT_INSN (start))
4033 if (NONJUMP_INSN_P (start)
4034 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4036 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4037 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4039 scan = emit_label_after (lab, scan);
4042 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4044 rtx align_insn = NULL_RTX;
4046 scan = emit_label_after (gen_label_rtx (), scan);
4047 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4050 for (i = 0; i < pool_size; i++)
4052 pool_node *p = &pool_vector[i];
4060 if (align_insn && !p->part_of_sequence_p)
4062 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4063 emit_label_before (lab, align_insn);
4064 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4066 for (ref = p->wend; ref; ref = ref->next)
4069 emit_insn_before (gen_consttable_window_end (lab),
4072 delete_insn (align_insn);
4073 align_insn = NULL_RTX;
4078 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4079 scan = emit_label_after (lab, scan);
4080 scan = emit_insn_after (gen_consttable_4 (p->value,
4082 need_align = ! need_align;
4088 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4093 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4094 scan = emit_label_after (lab, scan);
4095 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4102 if (p->mode != HImode)
4104 for (ref = p->wend; ref; ref = ref->next)
4107 scan = emit_insn_after (gen_consttable_window_end (lab),
4116 for (i = 0; i < pool_size; i++)
4118 pool_node *p = &pool_vector[i];
4129 scan = emit_label_after (gen_label_rtx (), scan);
4130 scan = emit_insn_after (gen_align_4 (), scan);
4132 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4133 scan = emit_label_after (lab, scan);
4134 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4142 scan = emit_label_after (gen_label_rtx (), scan);
4143 scan = emit_insn_after (gen_align_4 (), scan);
4145 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4146 scan = emit_label_after (lab, scan);
4147 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4154 if (p->mode != HImode)
4156 for (ref = p->wend; ref; ref = ref->next)
4159 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4164 scan = emit_insn_after (gen_consttable_end (), scan);
4165 scan = emit_barrier_after (scan);
4167 pool_window_label = NULL_RTX;
4168 pool_window_last = 0;
4171 /* Return nonzero if constant would be an ok source for a
4172 mov.w instead of a mov.l. */
4177 return (CONST_INT_P (src)
4178 && INTVAL (src) >= -32768
4179 && INTVAL (src) <= 32767);
4182 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4184 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4186 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4187 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4188 need to fix it if the input value is CONST_OK_FOR_I08. */
4191 broken_move (rtx insn)
4193 if (NONJUMP_INSN_P (insn))
4195 rtx pat = PATTERN (insn);
4196 if (GET_CODE (pat) == PARALLEL)
4197 pat = XVECEXP (pat, 0, 0);
4198 if (GET_CODE (pat) == SET
4199 /* We can load any 8-bit value if we don't care what the high
4200 order bits end up as. */
4201 && GET_MODE (SET_DEST (pat)) != QImode
4202 && (CONSTANT_P (SET_SRC (pat))
4203 /* Match mova_const. */
4204 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4205 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4206 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4208 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4209 && (fp_zero_operand (SET_SRC (pat))
4210 || fp_one_operand (SET_SRC (pat)))
4211 /* ??? If this is a -m4 or -m4-single compilation, in general
4212 we don't know the current setting of fpscr, so disable fldi.
4213 There is an exception if this was a register-register move
4214 before reload - and hence it was ascertained that we have
4215 single precision setting - and in a post-reload optimization
4216 we changed this to do a constant load. In that case
4217 we don't have an r0 clobber, hence we must use fldi. */
4218 && (! TARGET_SH4 || TARGET_FMOVD
4219 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4221 && REG_P (SET_DEST (pat))
4222 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4224 && GET_MODE (SET_DEST (pat)) == SImode
4225 && (satisfies_constraint_I20 (SET_SRC (pat))
4226 || satisfies_constraint_I28 (SET_SRC (pat))))
4227 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4237 return (NONJUMP_INSN_P (insn)
4238 && GET_CODE (PATTERN (insn)) == SET
4239 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4240 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4241 /* Don't match mova_const. */
4242 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4245 /* Fix up a mova from a switch that went out of range. */
4247 fixup_mova (rtx mova)
4249 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4252 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4253 INSN_CODE (mova) = -1;
4258 rtx lab = gen_label_rtx ();
4259 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4263 worker = NEXT_INSN (worker);
4265 && !LABEL_P (worker)
4266 && !JUMP_P (worker));
4267 } while (NOTE_P (worker)
4268 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4269 wpat = PATTERN (worker);
4270 wpat0 = XVECEXP (wpat, 0, 0);
4271 wpat1 = XVECEXP (wpat, 0, 1);
4272 wsrc = SET_SRC (wpat0);
4273 PATTERN (worker) = (gen_casesi_worker_2
4274 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4275 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4277 INSN_CODE (worker) = -1;
4278 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4279 base = gen_rtx_LABEL_REF (Pmode, lab);
4280 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4281 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4282 INSN_CODE (mova) = -1;
4286 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4287 *num_mova, and check if the new mova is not nested within the first one.
4288 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4289 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4291 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4293 int n_addr = 0; /* Initialization to shut up spurious warning. */
4294 int f_target, n_target = 0; /* Likewise. */
4298 /* If NEW_MOVA has no address yet, it will be handled later. */
4299 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4302 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4303 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4304 if (n_addr > n_target || n_addr + 1022 < n_target)
4306 /* Change the mova into a load.
4307 broken_move will then return true for it. */
4308 fixup_mova (new_mova);
4314 *first_mova = new_mova;
4319 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4324 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4325 > n_target - n_addr)
4327 fixup_mova (*first_mova);
4332 fixup_mova (new_mova);
4337 /* Find the last barrier from insn FROM which is close enough to hold the
4338 constant pool. If we can't find one, then create one near the end of
4342 find_barrier (int num_mova, rtx mova, rtx from)
4351 int leading_mova = num_mova;
4352 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4357 /* For HImode: range is 510, add 4 because pc counts from address of
4358 second instruction after this one, subtract 2 for the jump instruction
4359 that we may need to emit before the table, subtract 2 for the instruction
4360 that fills the jump delay slot (in very rare cases, reorg will take an
4361 instruction from after the constant pool or will leave the delay slot
4362 empty). This gives 510.
4363 For SImode: range is 1020, add 4 because pc counts from address of
4364 second instruction after this one, subtract 2 in case pc is 2 byte
4365 aligned, subtract 2 for the jump instruction that we may need to emit
4366 before the table, subtract 2 for the instruction that fills the jump
4367 delay slot. This gives 1018. */
4369 /* The branch will always be shortened now that the reference address for
4370 forward branches is the successor address, thus we need no longer make
4371 adjustments to the [sh]i_limit for -O0. */
4376 while (from && count_si < si_limit && count_hi < hi_limit)
4378 int inc = get_attr_length (from);
4381 /* If this is a label that existed at the time of the compute_alignments
4382 call, determine the alignment. N.B. When find_barrier recurses for
4383 an out-of-reach mova, we might see labels at the start of previously
4384 inserted constant tables. */
4386 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4389 new_align = 1 << label_to_alignment (from);
4390 else if (BARRIER_P (prev_nonnote_insn (from)))
4391 new_align = 1 << barrier_align (from);
4396 /* In case we are scanning a constant table because of recursion, check
4397 for explicit alignments. If the table is long, we might be forced
4398 to emit the new table in front of it; the length of the alignment
4399 might be the last straw. */
4400 else if (NONJUMP_INSN_P (from)
4401 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4402 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4403 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4404 /* When we find the end of a constant table, paste the new constant
4405 at the end. That is better than putting it in front because
4406 this way, we don't need extra alignment for adding a 4-byte-aligned
4407 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4408 else if (NONJUMP_INSN_P (from)
4409 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4410 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4413 if (BARRIER_P (from))
4417 found_barrier = from;
4419 /* If we are at the end of the function, or in front of an alignment
4420 instruction, we need not insert an extra alignment. We prefer
4421 this kind of barrier. */
4422 if (barrier_align (from) > 2)
4423 good_barrier = from;
4425 /* If we are at the end of a hot/cold block, dump the constants
4427 next = NEXT_INSN (from);
4430 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4434 if (broken_move (from))
4437 enum machine_mode mode;
4439 pat = PATTERN (from);
4440 if (GET_CODE (pat) == PARALLEL)
4441 pat = XVECEXP (pat, 0, 0);
4442 src = SET_SRC (pat);
4443 dst = SET_DEST (pat);
4444 mode = GET_MODE (dst);
4446 /* We must explicitly check the mode, because sometimes the
4447 front end will generate code to load unsigned constants into
4448 HImode targets without properly sign extending them. */
4450 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4453 /* We put the short constants before the long constants, so
4454 we must count the length of short constants in the range
4455 for the long constants. */
4456 /* ??? This isn't optimal, but is easy to do. */
4461 /* We dump DF/DI constants before SF/SI ones, because
4462 the limit is the same, but the alignment requirements
4463 are higher. We may waste up to 4 additional bytes
4464 for alignment, and the DF/DI constant may have
4465 another SF/SI constant placed before it. */
4466 if (TARGET_SHCOMPACT
4468 && (mode == DFmode || mode == DImode))
4473 while (si_align > 2 && found_si + si_align - 2 > count_si)
4475 if (found_si > count_si)
4476 count_si = found_si;
4477 found_si += GET_MODE_SIZE (mode);
4479 si_limit -= GET_MODE_SIZE (mode);
4485 switch (untangle_mova (&num_mova, &mova, from))
4487 case 0: return find_barrier (0, 0, mova);
4492 = good_barrier ? good_barrier : found_barrier;
4496 if (found_si > count_si)
4497 count_si = found_si;
4499 else if (JUMP_TABLE_DATA_P (from))
4501 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4503 && (prev_nonnote_insn (from)
4504 == XEXP (MOVA_LABELREF (mova), 0))))
4506 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4508 /* We have just passed the barrier in front of the
4509 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4510 the ADDR_DIFF_VEC is accessed as data, just like our pool
4511 constants, this is a good opportunity to accommodate what
4512 we have gathered so far.
4513 If we waited any longer, we could end up at a barrier in
4514 front of code, which gives worse cache usage for separated
4515 instruction / data caches. */
4516 good_barrier = found_barrier;
4521 rtx body = PATTERN (from);
4522 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4525 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4526 else if (JUMP_P (from)
4528 && ! TARGET_SMALLCODE)
4534 if (new_align > si_align)
4536 si_limit -= (count_si - 1) & (new_align - si_align);
4537 si_align = new_align;
4539 count_si = (count_si + new_align - 1) & -new_align;
4544 if (new_align > hi_align)
4546 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4547 hi_align = new_align;
4549 count_hi = (count_hi + new_align - 1) & -new_align;
4551 from = NEXT_INSN (from);
4558 /* Try as we might, the leading mova is out of range. Change
4559 it into a load (which will become a pcload) and retry. */
4561 return find_barrier (0, 0, mova);
4565 /* Insert the constant pool table before the mova instruction,
4566 to prevent the mova label reference from going out of range. */
4568 good_barrier = found_barrier = barrier_before_mova;
4574 if (good_barrier && next_real_insn (found_barrier))
4575 found_barrier = good_barrier;
4579 /* We didn't find a barrier in time to dump our stuff,
4580 so we'll make one. */
4581 rtx label = gen_label_rtx ();
4583 /* If we exceeded the range, then we must back up over the last
4584 instruction we looked at. Otherwise, we just need to undo the
4585 NEXT_INSN at the end of the loop. */
4586 if (PREV_INSN (from) != orig
4587 && (count_hi > hi_limit || count_si > si_limit))
4588 from = PREV_INSN (PREV_INSN (from));
4590 from = PREV_INSN (from);
4592 /* Walk back to be just before any jump or label.
4593 Putting it before a label reduces the number of times the branch
4594 around the constant pool table will be hit. Putting it before
4595 a jump makes it more likely that the bra delay slot will be
4597 while (NOTE_P (from) || JUMP_P (from)
4599 from = PREV_INSN (from);
4601 from = emit_jump_insn_after (gen_jump (label), from);
4602 JUMP_LABEL (from) = label;
4603 LABEL_NUSES (label) = 1;
4604 found_barrier = emit_barrier_after (from);
4605 emit_label_after (label, found_barrier);
4608 return found_barrier;
4611 /* If the instruction INSN is implemented by a special function, and we can
4612 positively find the register that is used to call the sfunc, and this
4613 register is not used anywhere else in this instruction - except as the
4614 destination of a set, return this register; else, return 0. */
4616 sfunc_uses_reg (rtx insn)
4619 rtx pattern, part, reg_part, reg;
4621 if (!NONJUMP_INSN_P (insn))
4623 pattern = PATTERN (insn);
4624 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4627 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4629 part = XVECEXP (pattern, 0, i);
4630 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4635 reg = XEXP (reg_part, 0);
4636 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4638 part = XVECEXP (pattern, 0, i);
4639 if (part == reg_part || GET_CODE (part) == CLOBBER)
4641 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4642 && REG_P (SET_DEST (part)))
4643 ? SET_SRC (part) : part)))
4649 /* See if the only way in which INSN uses REG is by calling it, or by
4650 setting it while calling it. Set *SET to a SET rtx if the register
4654 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4660 reg2 = sfunc_uses_reg (insn);
4661 if (reg2 && REGNO (reg2) == REGNO (reg))
4663 pattern = single_set (insn);
4665 && REG_P (SET_DEST (pattern))
4666 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4672 /* We don't use rtx_equal_p because we don't care if the mode is
4674 pattern = single_set (insn);
4676 && REG_P (SET_DEST (pattern))
4677 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4683 par = PATTERN (insn);
4684 if (GET_CODE (par) == PARALLEL)
4685 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4687 part = XVECEXP (par, 0, i);
4688 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4691 return reg_mentioned_p (reg, SET_SRC (pattern));
4697 pattern = PATTERN (insn);
4699 if (GET_CODE (pattern) == PARALLEL)
4703 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4704 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4706 pattern = XVECEXP (pattern, 0, 0);
4709 if (GET_CODE (pattern) == SET)
4711 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4713 /* We don't use rtx_equal_p, because we don't care if the
4714 mode is different. */
4715 if (!REG_P (SET_DEST (pattern))
4716 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4722 pattern = SET_SRC (pattern);
4725 if (GET_CODE (pattern) != CALL
4726 || !MEM_P (XEXP (pattern, 0))
4727 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4733 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4734 general registers. Bits 0..15 mean that the respective registers
4735 are used as inputs in the instruction. Bits 16..31 mean that the
4736 registers 0..15, respectively, are used as outputs, or are clobbered.
4737 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4739 regs_used (rtx x, int is_dest)
4747 code = GET_CODE (x);
4752 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4753 << (REGNO (x) + is_dest));
4757 rtx y = SUBREG_REG (x);
4762 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4764 subreg_regno_offset (REGNO (y),
4767 GET_MODE (x)) + is_dest));
4771 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4773 /* If there was a return value, it must have been indicated with USE. */
4788 fmt = GET_RTX_FORMAT (code);
4790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4795 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4796 used |= regs_used (XVECEXP (x, i, j), is_dest);
4798 else if (fmt[i] == 'e')
4799 used |= regs_used (XEXP (x, i), is_dest);
4804 /* Create an instruction that prevents redirection of a conditional branch
4805 to the destination of the JUMP with address ADDR.
4806 If the branch needs to be implemented as an indirect jump, try to find
4807 a scratch register for it.
4808 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4809 If any preceding insn that doesn't fit into a delay slot is good enough,
4810 pass 1. Pass 2 if a definite blocking insn is needed.
4811 -1 is used internally to avoid deep recursion.
4812 If a blocking instruction is made or recognized, return it. */
4815 gen_block_redirect (rtx jump, int addr, int need_block)
4818 rtx prev = prev_nonnote_insn (jump);
4821 /* First, check if we already have an instruction that satisfies our need. */
4822 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4824 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4826 if (GET_CODE (PATTERN (prev)) == USE
4827 || GET_CODE (PATTERN (prev)) == CLOBBER
4828 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4830 else if ((need_block &= ~1) < 0)
4832 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4835 if (GET_CODE (PATTERN (jump)) == RETURN)
4839 /* Reorg even does nasty things with return insns that cause branches
4840 to go out of range - see find_end_label and callers. */
4841 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4843 /* We can't use JUMP_LABEL here because it might be undefined
4844 when not optimizing. */
4845 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4846 /* If the branch is out of range, try to find a scratch register for it. */
4848 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4852 /* Don't look for the stack pointer as a scratch register,
4853 it would cause trouble if an interrupt occurred. */
4854 unsigned attempt = 0x7fff, used;
4855 int jump_left = flag_expensive_optimizations + 1;
4857 /* It is likely that the most recent eligible instruction is wanted for
4858 the delay slot. Therefore, find out which registers it uses, and
4859 try to avoid using them. */
4861 for (scan = jump; (scan = PREV_INSN (scan)); )
4865 if (INSN_DELETED_P (scan))
4867 code = GET_CODE (scan);
4868 if (code == CODE_LABEL || code == JUMP_INSN)
4871 && GET_CODE (PATTERN (scan)) != USE
4872 && GET_CODE (PATTERN (scan)) != CLOBBER
4873 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4875 attempt &= ~regs_used (PATTERN (scan), 0);
4879 for (used = dead = 0, scan = JUMP_LABEL (jump);
4880 (scan = NEXT_INSN (scan)); )
4884 if (INSN_DELETED_P (scan))
4886 code = GET_CODE (scan);
4889 used |= regs_used (PATTERN (scan), 0);
4890 if (code == CALL_INSN)
4891 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4892 dead |= (used >> 16) & ~used;
4898 if (code == JUMP_INSN)
4900 if (jump_left-- && simplejump_p (scan))
4901 scan = JUMP_LABEL (scan);
4907 /* Mask out the stack pointer again, in case it was
4908 the only 'free' register we have found. */
4911 /* If the immediate destination is still in range, check for possible
4912 threading with a jump beyond the delay slot insn.
4913 Don't check if we are called recursively; the jump has been or will be
4914 checked in a different invocation then. */
4916 else if (optimize && need_block >= 0)
4918 rtx next = next_active_insn (next_active_insn (dest));
4919 if (next && JUMP_P (next)
4920 && GET_CODE (PATTERN (next)) == SET
4921 && recog_memoized (next) == CODE_FOR_jump_compact)
4923 dest = JUMP_LABEL (next);
4925 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4927 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
4933 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
4935 /* It would be nice if we could convert the jump into an indirect
4936 jump / far branch right now, and thus exposing all constituent
4937 instructions to further optimization. However, reorg uses
4938 simplejump_p to determine if there is an unconditional jump where
4939 it should try to schedule instructions from the target of the
4940 branch; simplejump_p fails for indirect jumps even if they have
4942 rtx insn = emit_insn_before (gen_indirect_jump_scratch
4943 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
4945 /* ??? We would like this to have the scope of the jump, but that
4946 scope will change when a delay slot insn of an inner scope is added.
4947 Hence, after delay slot scheduling, we'll have to expect
4948 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
4951 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
4952 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
4955 else if (need_block)
4956 /* We can't use JUMP_LABEL here because it might be undefined
4957 when not optimizing. */
4958 return emit_insn_before (gen_block_branch_redirect
4959 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
4964 #define CONDJUMP_MIN -252
4965 #define CONDJUMP_MAX 262
4968 /* A label (to be placed) in front of the jump
4969 that jumps to our ultimate destination. */
4971 /* Where we are going to insert it if we cannot move the jump any farther,
4972 or the jump itself if we have picked up an existing jump. */
4974 /* The ultimate destination. */
4976 struct far_branch *prev;
4977 /* If the branch has already been created, its address;
4978 else the address of its first prospective user. */
4982 static void gen_far_branch (struct far_branch *);
4983 enum mdep_reorg_phase_e mdep_reorg_phase;
4985 gen_far_branch (struct far_branch *bp)
4987 rtx insn = bp->insert_place;
4989 rtx label = gen_label_rtx ();
4992 emit_label_after (label, insn);
4995 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
4996 LABEL_NUSES (bp->far_label)++;
4999 jump = emit_jump_insn_after (gen_return (), insn);
5000 /* Emit a barrier so that reorg knows that any following instructions
5001 are not reachable via a fall-through path.
5002 But don't do this when not optimizing, since we wouldn't suppress the
5003 alignment for the barrier then, and could end up with out-of-range
5004 pc-relative loads. */
5006 emit_barrier_after (jump);
5007 emit_label_after (bp->near_label, insn);
5008 JUMP_LABEL (jump) = bp->far_label;
5009 ok = invert_jump (insn, label, 1);
5012 /* If we are branching around a jump (rather than a return), prevent
5013 reorg from using an insn from the jump target as the delay slot insn -
5014 when reorg did this, it pessimized code (we rather hide the delay slot)
5015 and it could cause branches to go out of range. */
5018 (gen_stuff_delay_slot
5019 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
5020 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5022 /* Prevent reorg from undoing our splits. */
5023 gen_block_redirect (jump, bp->address += 2, 2);
5026 /* Fix up ADDR_DIFF_VECs. */
5028 fixup_addr_diff_vecs (rtx first)
5032 for (insn = first; insn; insn = NEXT_INSN (insn))
5034 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5037 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5039 pat = PATTERN (insn);
5040 vec_lab = XEXP (XEXP (pat, 0), 0);
5042 /* Search the matching casesi_jump_2. */
5043 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5047 prevpat = PATTERN (prev);
5048 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5050 x = XVECEXP (prevpat, 0, 1);
5051 if (GET_CODE (x) != USE)
5054 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5057 /* FIXME: This is a bug in the optimizer, but it seems harmless
5058 to just avoid panicing. */
5062 /* Emit the reference label of the braf where it belongs, right after
5063 the casesi_jump_2 (i.e. braf). */
5064 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5065 emit_label_after (braf_label, prev);
5067 /* Fix up the ADDR_DIF_VEC to be relative
5068 to the reference address of the braf. */
5069 XEXP (XEXP (pat, 0), 0) = braf_label;
5073 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5074 a barrier. Return the base 2 logarithm of the desired alignment. */
5076 barrier_align (rtx barrier_or_label)
5078 rtx next = next_real_insn (barrier_or_label), pat, prev;
5079 int slot, credit, jump_to_next = 0;
5084 pat = PATTERN (next);
5086 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5089 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5090 /* This is a barrier in front of a constant table. */
5093 prev = prev_real_insn (barrier_or_label);
5094 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5096 pat = PATTERN (prev);
5097 /* If this is a very small table, we want to keep the alignment after
5098 the table to the minimum for proper code alignment. */
5099 return ((TARGET_SMALLCODE
5100 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5101 <= (unsigned) 1 << (CACHE_LOG - 2)))
5102 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5105 if (TARGET_SMALLCODE)
5108 if (! TARGET_SH2 || ! optimize)
5109 return align_jumps_log;
5111 /* When fixing up pcloads, a constant table might be inserted just before
5112 the basic block that ends with the barrier. Thus, we can't trust the
5113 instruction lengths before that. */
5114 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5116 /* Check if there is an immediately preceding branch to the insn beyond
5117 the barrier. We must weight the cost of discarding useful information
5118 from the current cache line when executing this branch and there is
5119 an alignment, against that of fetching unneeded insn in front of the
5120 branch target when there is no alignment. */
5122 /* There are two delay_slot cases to consider. One is the simple case
5123 where the preceding branch is to the insn beyond the barrier (simple
5124 delay slot filling), and the other is where the preceding branch has
5125 a delay slot that is a duplicate of the insn after the barrier
5126 (fill_eager_delay_slots) and the branch is to the insn after the insn
5127 after the barrier. */
5129 /* PREV is presumed to be the JUMP_INSN for the barrier under
5130 investigation. Skip to the insn before it. */
5131 prev = prev_real_insn (prev);
5133 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5134 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5135 prev = prev_real_insn (prev))
5138 if (GET_CODE (PATTERN (prev)) == USE
5139 || GET_CODE (PATTERN (prev)) == CLOBBER)
5141 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5143 prev = XVECEXP (PATTERN (prev), 0, 1);
5144 if (INSN_UID (prev) == INSN_UID (next))
5146 /* Delay slot was filled with insn at jump target. */
5153 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5155 credit -= get_attr_length (prev);
5159 && JUMP_LABEL (prev))
5163 || next_real_insn (JUMP_LABEL (prev)) == next
5164 /* If relax_delay_slots() decides NEXT was redundant
5165 with some previous instruction, it will have
5166 redirected PREV's jump to the following insn. */
5167 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5168 /* There is no upper bound on redundant instructions
5169 that might have been skipped, but we must not put an
5170 alignment where none had been before. */
5171 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5173 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5174 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5175 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5177 rtx pat = PATTERN (prev);
5178 if (GET_CODE (pat) == PARALLEL)
5179 pat = XVECEXP (pat, 0, 0);
5180 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5186 return align_jumps_log;
5189 /* If we are inside a phony loop, almost any kind of label can turn up as the
5190 first one in the loop. Aligning a braf label causes incorrect switch
5191 destination addresses; we can detect braf labels because they are
5192 followed by a BARRIER.
5193 Applying loop alignment to small constant or switch tables is a waste
5194 of space, so we suppress this too. */
5196 sh_loop_align (rtx label)
5201 next = next_nonnote_insn (next);
5202 while (next && LABEL_P (next));
5206 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5207 || recog_memoized (next) == CODE_FOR_consttable_2)
5210 return align_loops_log;
5213 /* Do a final pass over the function, just before delayed branch
5219 rtx first, insn, mova = NULL_RTX;
5221 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5222 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5224 first = get_insns ();
5225 max_labelno_before_reorg = max_label_num ();
5227 /* We must split call insns before introducing `mova's. If we're
5228 optimizing, they'll have already been split. Otherwise, make
5229 sure we don't split them too late. */
5231 split_all_insns_noflow ();
5236 /* If relaxing, generate pseudo-ops to associate function calls with
5237 the symbols they call. It does no harm to not generate these
5238 pseudo-ops. However, when we can generate them, it enables to
5239 linker to potentially relax the jsr to a bsr, and eliminate the
5240 register load and, possibly, the constant pool entry. */
5242 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5245 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5246 own purposes. This works because none of the remaining passes
5247 need to look at them.
5249 ??? But it may break in the future. We should use a machine
5250 dependent REG_NOTE, or some other approach entirely. */
5251 for (insn = first; insn; insn = NEXT_INSN (insn))
5257 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5259 remove_note (insn, note);
5263 for (insn = first; insn; insn = NEXT_INSN (insn))
5265 rtx pattern, reg, link, set, scan, dies, label;
5266 int rescan = 0, foundinsn = 0;
5270 pattern = PATTERN (insn);
5272 if (GET_CODE (pattern) == PARALLEL)
5273 pattern = XVECEXP (pattern, 0, 0);
5274 if (GET_CODE (pattern) == SET)
5275 pattern = SET_SRC (pattern);
5277 if (GET_CODE (pattern) != CALL
5278 || !MEM_P (XEXP (pattern, 0)))
5281 reg = XEXP (XEXP (pattern, 0), 0);
5285 reg = sfunc_uses_reg (insn);
5293 /* Try scanning backward to find where the register is set. */
5295 for (scan = PREV_INSN (insn);
5296 scan && !LABEL_P (scan);
5297 scan = PREV_INSN (scan))
5299 if (! INSN_P (scan))
5302 if (! reg_mentioned_p (reg, scan))
5305 if (noncall_uses_reg (reg, scan, &set))
5318 /* The register is set at LINK. */
5320 /* We can only optimize the function call if the register is
5321 being set to a symbol. In theory, we could sometimes
5322 optimize calls to a constant location, but the assembler
5323 and linker do not support that at present. */
5324 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5325 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5328 /* Scan forward from LINK to the place where REG dies, and
5329 make sure that the only insns which use REG are
5330 themselves function calls. */
5332 /* ??? This doesn't work for call targets that were allocated
5333 by reload, since there may not be a REG_DEAD note for the
5337 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5341 /* Don't try to trace forward past a CODE_LABEL if we haven't
5342 seen INSN yet. Ordinarily, we will only find the setting insn
5343 if it is in the same basic block. However,
5344 cross-jumping can insert code labels in between the load and
5345 the call, and can result in situations where a single call
5346 insn may have two targets depending on where we came from. */
5348 if (LABEL_P (scan) && ! foundinsn)
5351 if (! INSN_P (scan))
5354 /* Don't try to trace forward past a JUMP. To optimize
5355 safely, we would have to check that all the
5356 instructions at the jump destination did not use REG. */
5361 if (! reg_mentioned_p (reg, scan))
5364 if (noncall_uses_reg (reg, scan, &scanset))
5371 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5373 /* There is a function call to this register other
5374 than the one we are checking. If we optimize
5375 this call, we need to rescan again below. */
5379 /* ??? We shouldn't have to worry about SCANSET here.
5380 We should just be able to check for a REG_DEAD note
5381 on a function call. However, the REG_DEAD notes are
5382 apparently not dependable around libcalls; c-torture
5383 execute/920501-2 is a test case. If SCANSET is set,
5384 then this insn sets the register, so it must have
5385 died earlier. Unfortunately, this will only handle
5386 the cases in which the register is, in fact, set in a
5389 /* ??? We shouldn't have to use FOUNDINSN here.
5390 This dates back to when we used LOG_LINKS to find
5391 the most recent insn which sets the register. */
5395 || find_reg_note (scan, REG_DEAD, reg)))
5404 /* Either there was a branch, or some insn used REG
5405 other than as a function call address. */
5409 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5410 on the insn which sets the register, and on each call insn
5411 which uses the register. In final_prescan_insn we look for
5412 the REG_LABEL_OPERAND notes, and output the appropriate label
5415 label = gen_label_rtx ();
5416 add_reg_note (link, REG_LABEL_OPERAND, label);
5417 add_reg_note (insn, REG_LABEL_OPERAND, label);
5425 scan = NEXT_INSN (scan);
5428 && reg_mentioned_p (reg, scan))
5429 || ((reg2 = sfunc_uses_reg (scan))
5430 && REGNO (reg2) == REGNO (reg))))
5431 add_reg_note (scan, REG_LABEL_OPERAND, label);
5433 while (scan != dies);
5439 fixup_addr_diff_vecs (first);
5443 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5444 shorten_branches (first);
5447 /* Scan the function looking for move instructions which have to be
5448 changed to pc-relative loads and insert the literal tables. */
5449 label_ref_list_pool = create_alloc_pool ("label references list",
5450 sizeof (struct label_ref_list_d),
5452 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5453 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5457 /* ??? basic block reordering can move a switch table dispatch
5458 below the switch table. Check if that has happened.
5459 We only have the addresses available when optimizing; but then,
5460 this check shouldn't be needed when not optimizing. */
5461 if (!untangle_mova (&num_mova, &mova, insn))
5467 else if (JUMP_P (insn)
5468 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5470 /* ??? loop invariant motion can also move a mova out of a
5471 loop. Since loop does this code motion anyway, maybe we
5472 should wrap UNSPEC_MOVA into a CONST, so that reload can
5475 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5476 || (prev_nonnote_insn (insn)
5477 == XEXP (MOVA_LABELREF (mova), 0))))
5484 /* Some code might have been inserted between the mova and
5485 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5486 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5487 total += get_attr_length (scan);
5489 /* range of mova is 1020, add 4 because pc counts from address of
5490 second instruction after this one, subtract 2 in case pc is 2
5491 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5492 cancels out with alignment effects of the mova itself. */
5495 /* Change the mova into a load, and restart scanning
5496 there. broken_move will then return true for mova. */
5501 if (broken_move (insn)
5502 || (NONJUMP_INSN_P (insn)
5503 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5506 /* Scan ahead looking for a barrier to stick the constant table
5508 rtx barrier = find_barrier (num_mova, mova, insn);
5509 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5510 int need_aligned_label = 0;
5512 if (num_mova && ! mova_p (mova))
5514 /* find_barrier had to change the first mova into a
5515 pcload; thus, we have to start with this new pcload. */
5519 /* Now find all the moves between the points and modify them. */
5520 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5524 if (NONJUMP_INSN_P (scan)
5525 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5526 need_aligned_label = 1;
5527 if (broken_move (scan))
5529 rtx *patp = &PATTERN (scan), pat = *patp;
5533 enum machine_mode mode;
5535 if (GET_CODE (pat) == PARALLEL)
5536 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5537 src = SET_SRC (pat);
5538 dst = SET_DEST (pat);
5539 mode = GET_MODE (dst);
5541 if (mode == SImode && hi_const (src)
5542 && REGNO (dst) != FPUL_REG)
5547 while (GET_CODE (dst) == SUBREG)
5549 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5550 GET_MODE (SUBREG_REG (dst)),
5553 dst = SUBREG_REG (dst);
5555 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5557 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5559 /* This must be an insn that clobbers r0. */
5560 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5561 XVECLEN (PATTERN (scan), 0)
5563 rtx clobber = *clobberp;
5565 gcc_assert (GET_CODE (clobber) == CLOBBER
5566 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5569 && reg_set_between_p (r0_rtx, last_float_move, scan))
5573 && GET_MODE_SIZE (mode) != 4
5574 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5576 lab = add_constant (src, mode, last_float);
5578 emit_insn_before (gen_mova (lab), scan);
5581 /* There will be a REG_UNUSED note for r0 on
5582 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5583 lest reorg:mark_target_live_regs will not
5584 consider r0 to be used, and we end up with delay
5585 slot insn in front of SCAN that clobbers r0. */
5587 = find_regno_note (last_float_move, REG_UNUSED, 0);
5589 /* If we are not optimizing, then there may not be
5592 PUT_REG_NOTE_KIND (note, REG_INC);
5594 *last_float_addr = r0_inc_rtx;
5596 last_float_move = scan;
5598 newsrc = gen_const_mem (mode,
5599 (((TARGET_SH4 && ! TARGET_FMOVD)
5600 || REGNO (dst) == FPUL_REG)
5603 last_float_addr = &XEXP (newsrc, 0);
5605 /* Remove the clobber of r0. */
5606 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5607 gen_rtx_SCRATCH (Pmode));
5609 /* This is a mova needing a label. Create it. */
5610 else if (GET_CODE (src) == UNSPEC
5611 && XINT (src, 1) == UNSPEC_MOVA
5612 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5614 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5615 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5616 newsrc = gen_rtx_UNSPEC (SImode,
5617 gen_rtvec (1, newsrc),
5622 lab = add_constant (src, mode, 0);
5623 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5624 newsrc = gen_const_mem (mode, newsrc);
5626 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5627 INSN_CODE (scan) = -1;
5630 dump_table (need_aligned_label ? insn : 0, barrier);
5634 free_alloc_pool (label_ref_list_pool);
5635 for (insn = first; insn; insn = NEXT_INSN (insn))
5636 PUT_MODE (insn, VOIDmode);
5638 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5639 INSN_ADDRESSES_FREE ();
5640 split_branches (first);
5642 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5643 also has an effect on the register that holds the address of the sfunc.
5644 Insert an extra dummy insn in front of each sfunc that pretends to
5645 use this register. */
5646 if (flag_delayed_branch)
5648 for (insn = first; insn; insn = NEXT_INSN (insn))
5650 rtx reg = sfunc_uses_reg (insn);
5654 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5658 /* fpscr is not actually a user variable, but we pretend it is for the
5659 sake of the previous optimization passes, since we want it handled like
5660 one. However, we don't have any debugging information for it, so turn
5661 it into a non-user variable now. */
5663 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5665 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5669 get_dest_uid (rtx label, int max_uid)
5671 rtx dest = next_real_insn (label);
5674 /* This can happen for an undefined label. */
5676 dest_uid = INSN_UID (dest);
5677 /* If this is a newly created branch redirection blocking instruction,
5678 we cannot index the branch_uid or insn_addresses arrays with its
5679 uid. But then, we won't need to, because the actual destination is
5680 the following branch. */
5681 while (dest_uid >= max_uid)
5683 dest = NEXT_INSN (dest);
5684 dest_uid = INSN_UID (dest);
5686 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5691 /* Split condbranches that are out of range. Also add clobbers for
5692 scratch registers that are needed in far jumps.
5693 We do this before delay slot scheduling, so that it can take our
5694 newly created instructions into account. It also allows us to
5695 find branches with common targets more easily. */
5698 split_branches (rtx first)
5701 struct far_branch **uid_branch, *far_branch_list = 0;
5702 int max_uid = get_max_uid ();
5705 /* Find out which branches are out of range. */
5706 shorten_branches (first);
5708 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5709 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5711 for (insn = first; insn; insn = NEXT_INSN (insn))
5712 if (! INSN_P (insn))
5714 else if (INSN_DELETED_P (insn))
5716 /* Shorten_branches would split this instruction again,
5717 so transform it into a note. */
5718 SET_INSN_DELETED (insn);
5720 else if (JUMP_P (insn)
5721 /* Don't mess with ADDR_DIFF_VEC */
5722 && (GET_CODE (PATTERN (insn)) == SET
5723 || GET_CODE (PATTERN (insn)) == RETURN))
5725 enum attr_type type = get_attr_type (insn);
5726 if (type == TYPE_CBRANCH)
5730 if (get_attr_length (insn) > 4)
5732 rtx src = SET_SRC (PATTERN (insn));
5733 rtx olabel = XEXP (XEXP (src, 1), 0);
5734 int addr = INSN_ADDRESSES (INSN_UID (insn));
5736 int dest_uid = get_dest_uid (olabel, max_uid);
5737 struct far_branch *bp = uid_branch[dest_uid];
5739 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5740 the label if the LABEL_NUSES count drops to zero. There is
5741 always a jump_optimize pass that sets these values, but it
5742 proceeds to delete unreferenced code, and then if not
5743 optimizing, to un-delete the deleted instructions, thus
5744 leaving labels with too low uses counts. */
5747 JUMP_LABEL (insn) = olabel;
5748 LABEL_NUSES (olabel)++;
5752 bp = (struct far_branch *) alloca (sizeof *bp);
5753 uid_branch[dest_uid] = bp;
5754 bp->prev = far_branch_list;
5755 far_branch_list = bp;
5757 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5758 LABEL_NUSES (bp->far_label)++;
5762 label = bp->near_label;
5763 if (! label && bp->address - addr >= CONDJUMP_MIN)
5765 rtx block = bp->insert_place;
5767 if (GET_CODE (PATTERN (block)) == RETURN)
5768 block = PREV_INSN (block);
5770 block = gen_block_redirect (block,
5772 label = emit_label_after (gen_label_rtx (),
5774 bp->near_label = label;
5776 else if (label && ! NEXT_INSN (label))
5778 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5779 bp->insert_place = insn;
5781 gen_far_branch (bp);
5785 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5787 bp->near_label = label = gen_label_rtx ();
5788 bp->insert_place = insn;
5791 ok = redirect_jump (insn, label, 0);
5796 /* get_attr_length (insn) == 2 */
5797 /* Check if we have a pattern where reorg wants to redirect
5798 the branch to a label from an unconditional branch that
5800 /* We can't use JUMP_LABEL here because it might be undefined
5801 when not optimizing. */
5802 /* A syntax error might cause beyond to be NULL_RTX. */
5804 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5809 || ((beyond = next_active_insn (beyond))
5810 && JUMP_P (beyond)))
5811 && GET_CODE (PATTERN (beyond)) == SET
5812 && recog_memoized (beyond) == CODE_FOR_jump_compact
5814 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5815 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5817 gen_block_redirect (beyond,
5818 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5821 next = next_active_insn (insn);
5824 || ((next = next_active_insn (next))
5826 && GET_CODE (PATTERN (next)) == SET
5827 && recog_memoized (next) == CODE_FOR_jump_compact
5829 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5830 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5832 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5834 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5836 int addr = INSN_ADDRESSES (INSN_UID (insn));
5839 struct far_branch *bp;
5841 if (type == TYPE_JUMP)
5843 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5844 dest_uid = get_dest_uid (far_label, max_uid);
5847 /* Parse errors can lead to labels outside
5849 if (! NEXT_INSN (far_label))
5854 JUMP_LABEL (insn) = far_label;
5855 LABEL_NUSES (far_label)++;
5857 redirect_jump (insn, NULL_RTX, 1);
5861 bp = uid_branch[dest_uid];
5864 bp = (struct far_branch *) alloca (sizeof *bp);
5865 uid_branch[dest_uid] = bp;
5866 bp->prev = far_branch_list;
5867 far_branch_list = bp;
5869 bp->far_label = far_label;
5871 LABEL_NUSES (far_label)++;
5873 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5874 if (addr - bp->address <= CONDJUMP_MAX)
5875 emit_label_after (bp->near_label, PREV_INSN (insn));
5878 gen_far_branch (bp);
5884 bp->insert_place = insn;
5886 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5888 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5891 /* Generate all pending far branches,
5892 and free our references to the far labels. */
5893 while (far_branch_list)
5895 if (far_branch_list->near_label
5896 && ! NEXT_INSN (far_branch_list->near_label))
5897 gen_far_branch (far_branch_list);
5899 && far_branch_list->far_label
5900 && ! --LABEL_NUSES (far_branch_list->far_label))
5901 delete_insn (far_branch_list->far_label);
5902 far_branch_list = far_branch_list->prev;
5905 /* Instruction length information is no longer valid due to the new
5906 instructions that have been generated. */
5907 init_insn_lengths ();
5910 /* Dump out instruction addresses, which is useful for debugging the
5911 constant pool table stuff.
5913 If relaxing, output the label and pseudo-ops used to link together
5914 calls and the instruction which set the registers. */
5916 /* ??? The addresses printed by this routine for insns are nonsense for
5917 insns which are inside of a sequence where none of the inner insns have
5918 variable length. This is because the second pass of shorten_branches
5919 does not bother to update them. */
5922 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
5923 int noperands ATTRIBUTE_UNUSED)
5925 if (TARGET_DUMPISIZE)
5926 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
5932 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
5937 pattern = PATTERN (insn);
5938 if (GET_CODE (pattern) == PARALLEL)
5939 pattern = XVECEXP (pattern, 0, 0);
5940 switch (GET_CODE (pattern))
5943 if (GET_CODE (SET_SRC (pattern)) != CALL
5944 && get_attr_type (insn) != TYPE_SFUNC)
5946 targetm.asm_out.internal_label
5947 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
5950 /* else FALLTHROUGH */
5952 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
5953 CODE_LABEL_NUMBER (XEXP (note, 0)));
5963 /* Dump out any constants accumulated in the final pass. These will
5967 output_jump_label_table (void)
5973 fprintf (asm_out_file, "\t.align 2\n");
5974 for (i = 0; i < pool_size; i++)
5976 pool_node *p = &pool_vector[i];
5978 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5979 CODE_LABEL_NUMBER (p->label));
5980 output_asm_insn (".long %O0", &p->value);
5988 /* A full frame looks like:
5992 [ if current_function_anonymous_args
6005 local-0 <- fp points here. */
6007 /* Number of bytes pushed for anonymous args, used to pass information
6008 between expand_prologue and expand_epilogue. */
6010 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6011 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6012 for an epilogue and a negative value means that it's for a sibcall
6013 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6014 all the registers that are about to be restored, and hence dead. */
6017 output_stack_adjust (int size, rtx reg, int epilogue_p,
6018 HARD_REG_SET *live_regs_mask)
6020 rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
6023 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6025 /* This test is bogus, as output_stack_adjust is used to re-align the
6028 gcc_assert (!(size % align));
6031 if (CONST_OK_FOR_ADD (size))
6032 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6033 /* Try to do it with two partial adjustments; however, we must make
6034 sure that the stack is properly aligned at all times, in case
6035 an interrupt occurs between the two partial adjustments. */
6036 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6037 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6039 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6040 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6046 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6049 /* If TEMP is invalid, we could temporarily save a general
6050 register to MACL. However, there is currently no need
6051 to handle this case, so just die when we see it. */
6053 || current_function_interrupt
6054 || ! call_really_used_regs[temp] || fixed_regs[temp])
6056 if (temp < 0 && ! current_function_interrupt
6057 && (TARGET_SHMEDIA || epilogue_p >= 0))
6060 COPY_HARD_REG_SET (temps, call_used_reg_set);
6061 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6065 if (crtl->return_rtx)
6067 enum machine_mode mode;
6068 mode = GET_MODE (crtl->return_rtx);
6069 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6070 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6072 for (i = 0; i < nreg; i++)
6073 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6074 if (crtl->calls_eh_return)
6076 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6077 for (i = 0; i <= 3; i++)
6078 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6081 if (TARGET_SHMEDIA && epilogue_p < 0)
6082 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6083 CLEAR_HARD_REG_BIT (temps, i);
6084 if (epilogue_p <= 0)
6086 for (i = FIRST_PARM_REG;
6087 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6088 CLEAR_HARD_REG_BIT (temps, i);
6089 if (cfun->static_chain_decl != NULL)
6090 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6092 temp = scavenge_reg (&temps);
6094 if (temp < 0 && live_regs_mask)
6098 COPY_HARD_REG_SET (temps, *live_regs_mask);
6099 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6100 temp = scavenge_reg (&temps);
6104 rtx adj_reg, tmp_reg, mem;
6106 /* If we reached here, the most likely case is the (sibcall)
6107 epilogue for non SHmedia. Put a special push/pop sequence
6108 for such case as the last resort. This looks lengthy but
6109 would not be problem because it seems to be very
6112 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6115 /* ??? There is still the slight possibility that r4 or
6116 r5 have been reserved as fixed registers or assigned
6117 as global registers, and they change during an
6118 interrupt. There are possible ways to handle this:
6120 - If we are adjusting the frame pointer (r14), we can do
6121 with a single temp register and an ordinary push / pop
6123 - Grab any call-used or call-saved registers (i.e. not
6124 fixed or globals) for the temps we need. We might
6125 also grab r14 if we are adjusting the stack pointer.
6126 If we can't find enough available registers, issue
6127 a diagnostic and die - the user must have reserved
6128 way too many registers.
6129 But since all this is rather unlikely to happen and
6130 would require extra testing, we just die if r4 / r5
6131 are not available. */
6132 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6133 && !global_regs[4] && !global_regs[5]);
6135 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6136 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6137 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6138 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6139 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6140 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6141 emit_move_insn (mem, tmp_reg);
6142 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6143 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6144 emit_move_insn (mem, tmp_reg);
6145 emit_move_insn (reg, adj_reg);
6146 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6147 emit_move_insn (adj_reg, mem);
6148 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6149 emit_move_insn (tmp_reg, mem);
6150 /* Tell flow the insns that pop r4/r5 aren't dead. */
6155 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6157 /* If SIZE is negative, subtract the positive value.
6158 This sometimes allows a constant pool entry to be shared
6159 between prologue and epilogue code. */
6162 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6163 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6167 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6168 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6171 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6172 gen_rtx_SET (VOIDmode, reg,
6173 gen_rtx_PLUS (SImode, reg,
6183 RTX_FRAME_RELATED_P (x) = 1;
6187 /* Output RTL to push register RN onto the stack. */
6194 x = gen_push_fpul ();
6195 else if (rn == FPSCR_REG)
6196 x = gen_push_fpscr ();
6197 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6198 && FP_OR_XD_REGISTER_P (rn))
6200 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6202 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6204 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6205 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6207 x = gen_push (gen_rtx_REG (SImode, rn));
6210 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6214 /* Output RTL to pop register RN from the stack. */
6221 x = gen_pop_fpul ();
6222 else if (rn == FPSCR_REG)
6223 x = gen_pop_fpscr ();
6224 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6225 && FP_OR_XD_REGISTER_P (rn))
6227 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6229 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6231 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6232 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6234 x = gen_pop (gen_rtx_REG (SImode, rn));
6237 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6240 /* Generate code to push the regs specified in the mask. */
6243 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6245 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6248 /* Push PR last; this gives better latencies after the prologue, and
6249 candidates for the return delay slot when there are no general
6250 registers pushed. */
6251 for (; i < FIRST_PSEUDO_REGISTER; i++)
6253 /* If this is an interrupt handler, and the SZ bit varies,
6254 and we have to push any floating point register, we need
6255 to switch to the correct precision first. */
6256 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6257 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6259 HARD_REG_SET unsaved;
6262 COMPL_HARD_REG_SET (unsaved, *mask);
6263 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6267 && (i != FPSCR_REG || ! skip_fpscr)
6268 && TEST_HARD_REG_BIT (*mask, i))
6270 /* If the ISR has RESBANK attribute assigned, don't push any of
6271 the following registers - R0-R14, MACH, MACL and GBR. */
6272 if (! (sh_cfun_resbank_handler_p ()
6273 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6281 /* Push banked registers last to improve delay slot opportunities. */
6282 if (interrupt_handler)
6283 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6284 if (TEST_HARD_REG_BIT (*mask, i))
6287 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6288 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6292 /* Calculate how much extra space is needed to save all callee-saved
6294 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6297 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6300 int stack_space = 0;
6301 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6303 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6304 if ((! call_really_used_regs[reg] || interrupt_handler)
6305 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6306 /* Leave space to save this target register on the stack,
6307 in case target register allocation wants to use it. */
6308 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6312 /* Decide whether we should reserve space for callee-save target registers,
6313 in case target register allocation wants to use them. REGS_SAVED is
6314 the space, in bytes, that is already required for register saves.
6315 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6318 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6319 HARD_REG_SET *live_regs_mask)
6323 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6326 /* Decide how much space to reserve for callee-save target registers
6327 in case target register allocation wants to use them.
6328 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6331 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6333 if (shmedia_space_reserved_for_target_registers)
6334 return shmedia_target_regs_stack_space (live_regs_mask);
6339 /* Work out the registers which need to be saved, both as a mask and a
6340 count of saved words. Return the count.
6342 If doing a pragma interrupt function, then push all regs used by the
6343 function, and if we call another function (we can tell by looking at PR),
6344 make sure that all the regs it clobbers are safe too. */
6347 calc_live_regs (HARD_REG_SET *live_regs_mask)
6352 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6353 bool nosave_low_regs;
6354 int pr_live, has_call;
6356 attrs = DECL_ATTRIBUTES (current_function_decl);
6357 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6358 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6359 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6360 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6362 CLEAR_HARD_REG_SET (*live_regs_mask);
6363 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6364 && df_regs_ever_live_p (FPSCR_REG))
6365 target_flags &= ~MASK_FPU_SINGLE;
6366 /* If we can save a lot of saves by switching to double mode, do that. */
6367 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6368 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6369 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6370 && (! call_really_used_regs[reg]
6371 || interrupt_handler)
6374 target_flags &= ~MASK_FPU_SINGLE;
6377 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6378 knows how to use it. That means the pseudo originally allocated for
6379 the initial value can become the PR_MEDIA_REG hard register, as seen for
6380 execute/20010122-1.c:test9. */
6382 /* ??? this function is called from initial_elimination_offset, hence we
6383 can't use the result of sh_media_register_for_return here. */
6384 pr_live = sh_pr_n_sets ();
6387 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6388 pr_live = (pr_initial
6389 ? (!REG_P (pr_initial)
6390 || REGNO (pr_initial) != (PR_REG))
6391 : df_regs_ever_live_p (PR_REG));
6392 /* For Shcompact, if not optimizing, we end up with a memory reference
6393 using the return address pointer for __builtin_return_address even
6394 though there is no actual need to put the PR register on the stack. */
6395 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6397 /* Force PR to be live if the prologue has to call the SHmedia
6398 argument decoder or register saver. */
6399 if (TARGET_SHCOMPACT
6400 && ((crtl->args.info.call_cookie
6401 & ~ CALL_COOKIE_RET_TRAMP (1))
6402 || crtl->saves_all_registers))
6404 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6405 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6407 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6410 ? (/* Need to save all the regs ever live. */
6411 (df_regs_ever_live_p (reg)
6412 || (call_really_used_regs[reg]
6413 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6414 || reg == PIC_OFFSET_TABLE_REGNUM)
6416 || (TARGET_SHMEDIA && has_call
6417 && REGISTER_NATURAL_MODE (reg) == SImode
6418 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6419 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6420 && reg != RETURN_ADDRESS_POINTER_REGNUM
6421 && reg != T_REG && reg != GBR_REG
6422 /* Push fpscr only on targets which have FPU */
6423 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6424 : (/* Only push those regs which are used and need to be saved. */
6427 && crtl->args.info.call_cookie
6428 && reg == PIC_OFFSET_TABLE_REGNUM)
6429 || (df_regs_ever_live_p (reg)
6430 && ((!call_really_used_regs[reg]
6431 && !(reg != PIC_OFFSET_TABLE_REGNUM
6432 && fixed_regs[reg] && call_used_regs[reg]))
6433 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6434 || (crtl->calls_eh_return
6435 && (reg == EH_RETURN_DATA_REGNO (0)
6436 || reg == EH_RETURN_DATA_REGNO (1)
6437 || reg == EH_RETURN_DATA_REGNO (2)
6438 || reg == EH_RETURN_DATA_REGNO (3)))
6439 || ((reg == MACL_REG || reg == MACH_REG)
6440 && df_regs_ever_live_p (reg)
6441 && sh_cfun_attr_renesas_p ())
6444 SET_HARD_REG_BIT (*live_regs_mask, reg);
6445 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6447 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6448 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6450 if (FP_REGISTER_P (reg))
6452 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6454 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6455 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6458 else if (XD_REGISTER_P (reg))
6460 /* Must switch to double mode to access these registers. */
6461 target_flags &= ~MASK_FPU_SINGLE;
6465 if (nosave_low_regs && reg == R8_REG)
6468 /* If we have a target register optimization pass after prologue / epilogue
6469 threading, we need to assume all target registers will be live even if
6471 if (flag_branch_target_load_optimize2
6472 && TARGET_SAVE_ALL_TARGET_REGS
6473 && shmedia_space_reserved_for_target_registers)
6474 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6475 if ((! call_really_used_regs[reg] || interrupt_handler)
6476 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6478 SET_HARD_REG_BIT (*live_regs_mask, reg);
6479 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6481 /* If this is an interrupt handler, we don't have any call-clobbered
6482 registers we can conveniently use for target register save/restore.
6483 Make sure we save at least one general purpose register when we need
6484 to save target registers. */
6485 if (interrupt_handler
6486 && hard_reg_set_intersect_p (*live_regs_mask,
6487 reg_class_contents[TARGET_REGS])
6488 && ! hard_reg_set_intersect_p (*live_regs_mask,
6489 reg_class_contents[GENERAL_REGS]))
6491 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6492 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6498 /* Code to generate prologue and epilogue sequences */
6500 /* PUSHED is the number of bytes that are being pushed on the
6501 stack for register saves. Return the frame size, padded
6502 appropriately so that the stack stays properly aligned. */
6503 static HOST_WIDE_INT
6504 rounded_frame_size (int pushed)
6506 HOST_WIDE_INT size = get_frame_size ();
6507 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6509 return ((size + pushed + align - 1) & -align) - pushed;
6512 /* Choose a call-clobbered target-branch register that remains
6513 unchanged along the whole function. We set it up as the return
6514 value in the prologue. */
6516 sh_media_register_for_return (void)
6521 if (! current_function_is_leaf)
6523 if (lookup_attribute ("interrupt_handler",
6524 DECL_ATTRIBUTES (current_function_decl)))
6526 if (sh_cfun_interrupt_handler_p ())
6529 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6531 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6532 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6538 /* The maximum registers we need to save are:
6539 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6540 - 32 floating point registers (for each pair, we save none,
6541 one single precision value, or a double precision value).
6542 - 8 target registers
6543 - add 1 entry for a delimiter. */
6544 #define MAX_SAVED_REGS (62+32+8)
6546 typedef struct save_entry_s
6555 /* There will be a delimiter entry with VOIDmode both at the start and the
6556 end of a filled in schedule. The end delimiter has the offset of the
6557 save with the smallest (i.e. most negative) offset. */
6558 typedef struct save_schedule_s
6560 save_entry entries[MAX_SAVED_REGS + 2];
6561 int temps[MAX_TEMPS+1];
6564 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6565 use reverse order. Returns the last entry written to (not counting
6566 the delimiter). OFFSET_BASE is a number to be added to all offset
6570 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6574 save_entry *entry = schedule->entries;
6578 if (! current_function_interrupt)
6579 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6580 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6581 && ! FUNCTION_ARG_REGNO_P (i)
6582 && i != FIRST_RET_REG
6583 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6584 && ! (crtl->calls_eh_return
6585 && (i == EH_RETURN_STACKADJ_REGNO
6586 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6587 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6588 schedule->temps[tmpx++] = i;
6590 entry->mode = VOIDmode;
6591 entry->offset = offset_base;
6593 /* We loop twice: first, we save 8-byte aligned registers in the
6594 higher addresses, that are known to be aligned. Then, we
6595 proceed to saving 32-bit registers that don't need 8-byte
6597 If this is an interrupt function, all registers that need saving
6598 need to be saved in full. moreover, we need to postpone saving
6599 target registers till we have saved some general purpose registers
6600 we can then use as scratch registers. */
6601 offset = offset_base;
6602 for (align = 1; align >= 0; align--)
6604 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6605 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6607 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6610 if (current_function_interrupt)
6612 if (TARGET_REGISTER_P (i))
6614 if (GENERAL_REGISTER_P (i))
6617 if (mode == SFmode && (i % 2) == 1
6618 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6619 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6626 /* If we're doing the aligned pass and this is not aligned,
6627 or we're doing the unaligned pass and this is aligned,
6629 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6633 if (current_function_interrupt
6634 && GENERAL_REGISTER_P (i)
6635 && tmpx < MAX_TEMPS)
6636 schedule->temps[tmpx++] = i;
6638 offset -= GET_MODE_SIZE (mode);
6641 entry->offset = offset;
6644 if (align && current_function_interrupt)
6645 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6646 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6648 offset -= GET_MODE_SIZE (DImode);
6650 entry->mode = DImode;
6651 entry->offset = offset;
6656 entry->mode = VOIDmode;
6657 entry->offset = offset;
6658 schedule->temps[tmpx] = -1;
6663 sh_expand_prologue (void)
6665 HARD_REG_SET live_regs_mask;
6668 int save_flags = target_flags;
6671 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6673 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6675 /* We have pretend args if we had an object sent partially in registers
6676 and partially on the stack, e.g. a large structure. */
6677 pretend_args = crtl->args.pretend_args_size;
6678 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6679 && (NPARM_REGS(SImode)
6680 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6682 output_stack_adjust (-pretend_args
6683 - crtl->args.info.stack_regs * 8,
6684 stack_pointer_rtx, 0, NULL);
6686 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6687 /* We're going to use the PIC register to load the address of the
6688 incoming-argument decoder and/or of the return trampoline from
6689 the GOT, so make sure the PIC register is preserved and
6691 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6693 if (TARGET_SHCOMPACT
6694 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6698 /* First, make all registers with incoming arguments that will
6699 be pushed onto the stack live, so that register renaming
6700 doesn't overwrite them. */
6701 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6702 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6703 >= NPARM_REGS (SImode) - reg)
6704 for (; reg < NPARM_REGS (SImode); reg++)
6705 emit_insn (gen_shcompact_preserve_incoming_args
6706 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6707 else if (CALL_COOKIE_INT_REG_GET
6708 (crtl->args.info.call_cookie, reg) == 1)
6709 emit_insn (gen_shcompact_preserve_incoming_args
6710 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6712 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6714 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6715 GEN_INT (crtl->args.info.call_cookie));
6716 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6717 gen_rtx_REG (SImode, R0_REG));
6719 else if (TARGET_SHMEDIA)
6721 int tr = sh_media_register_for_return ();
6724 emit_move_insn (gen_rtx_REG (DImode, tr),
6725 gen_rtx_REG (DImode, PR_MEDIA_REG));
6728 /* Emit the code for SETUP_VARARGS. */
6731 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6733 /* Push arg regs as if they'd been provided by caller in stack. */
6734 for (i = 0; i < NPARM_REGS(SImode); i++)
6736 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6739 if (i >= (NPARM_REGS(SImode)
6740 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6748 /* If we're supposed to switch stacks at function entry, do so now. */
6751 /* The argument specifies a variable holding the address of the
6752 stack the interrupt function should switch to/from at entry/exit. */
6754 = ggc_strdup (TREE_STRING_POINTER (TREE_VALUE (sp_switch_attr)));
6755 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6757 emit_insn (gen_sp_switch_1 (sp_switch));
6760 d = calc_live_regs (&live_regs_mask);
6761 /* ??? Maybe we could save some switching if we can move a mode switch
6762 that already happens to be at the function start into the prologue. */
6763 if (target_flags != save_flags && ! current_function_interrupt)
6764 emit_insn (gen_toggle_sz ());
6768 int offset_base, offset;
6770 int offset_in_r0 = -1;
6772 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6773 int total_size, save_size;
6774 save_schedule schedule;
6778 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6779 && ! current_function_interrupt)
6780 r0 = gen_rtx_REG (Pmode, R0_REG);
6782 /* D is the actual number of bytes that we need for saving registers,
6783 however, in initial_elimination_offset we have committed to using
6784 an additional TREGS_SPACE amount of bytes - in order to keep both
6785 addresses to arguments supplied by the caller and local variables
6786 valid, we must keep this gap. Place it between the incoming
6787 arguments and the actually saved registers in a bid to optimize
6788 locality of reference. */
6789 total_size = d + tregs_space;
6790 total_size += rounded_frame_size (total_size);
6791 save_size = total_size - rounded_frame_size (d);
6792 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6793 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6794 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6796 /* If adjusting the stack in a single step costs nothing extra, do so.
6797 I.e. either if a single addi is enough, or we need a movi anyway,
6798 and we don't exceed the maximum offset range (the test for the
6799 latter is conservative for simplicity). */
6801 && (CONST_OK_FOR_I10 (-total_size)
6802 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6803 && total_size <= 2044)))
6804 d_rounding = total_size - save_size;
6806 offset_base = d + d_rounding;
6808 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6811 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6812 tmp_pnt = schedule.temps;
6813 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6815 enum machine_mode mode = (enum machine_mode) entry->mode;
6816 unsigned int reg = entry->reg;
6817 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6820 offset = entry->offset;
6822 reg_rtx = gen_rtx_REG (mode, reg);
6824 mem_rtx = gen_frame_mem (mode,
6825 gen_rtx_PLUS (Pmode,
6829 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6835 if (HAVE_PRE_DECREMENT
6836 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6837 || mem_rtx == NULL_RTX
6838 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6840 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6842 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6847 offset += GET_MODE_SIZE (mode);
6851 if (mem_rtx != NULL_RTX)
6854 if (offset_in_r0 == -1)
6856 emit_move_insn (r0, GEN_INT (offset));
6857 offset_in_r0 = offset;
6859 else if (offset != offset_in_r0)
6864 GEN_INT (offset - offset_in_r0)));
6865 offset_in_r0 += offset - offset_in_r0;
6868 if (pre_dec != NULL_RTX)
6874 (Pmode, r0, stack_pointer_rtx));
6878 offset -= GET_MODE_SIZE (mode);
6879 offset_in_r0 -= GET_MODE_SIZE (mode);
6884 mem_rtx = gen_frame_mem (mode, r0);
6886 mem_rtx = gen_frame_mem (mode,
6887 gen_rtx_PLUS (Pmode,
6891 /* We must not use an r0-based address for target-branch
6892 registers or for special registers without pre-dec
6893 memory addresses, since we store their values in r0
6895 gcc_assert (!TARGET_REGISTER_P (reg)
6896 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
6897 || mem_rtx == pre_dec));
6900 orig_reg_rtx = reg_rtx;
6901 if (TARGET_REGISTER_P (reg)
6902 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
6903 && mem_rtx != pre_dec))
6905 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
6907 emit_move_insn (tmp_reg, reg_rtx);
6909 if (REGNO (tmp_reg) == R0_REG)
6913 gcc_assert (!refers_to_regno_p
6914 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
6917 if (*++tmp_pnt <= 0)
6918 tmp_pnt = schedule.temps;
6925 /* Mark as interesting for dwarf cfi generator */
6926 insn = emit_move_insn (mem_rtx, reg_rtx);
6927 RTX_FRAME_RELATED_P (insn) = 1;
6928 /* If we use an intermediate register for the save, we can't
6929 describe this exactly in cfi as a copy of the to-be-saved
6930 register into the temporary register and then the temporary
6931 register on the stack, because the temporary register can
6932 have a different natural size than the to-be-saved register.
6933 Thus, we gloss over the intermediate copy and pretend we do
6934 a direct save from the to-be-saved register. */
6935 if (REGNO (reg_rtx) != reg)
6939 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
6940 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6943 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
6945 rtx reg_rtx = gen_rtx_REG (mode, reg);
6947 rtx mem_rtx = gen_frame_mem (mode,
6948 gen_rtx_PLUS (Pmode,
6952 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
6953 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
6958 gcc_assert (entry->offset == d_rounding);
6961 push_regs (&live_regs_mask, current_function_interrupt);
6963 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
6964 emit_insn (gen_GOTaddr2picreg ());
6966 if (SHMEDIA_REGS_STACK_ADJUST ())
6968 /* This must NOT go through the PLT, otherwise mach and macl
6969 may be clobbered. */
6970 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6972 ? "__GCC_push_shmedia_regs"
6973 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
6974 emit_insn (gen_shmedia_save_restore_regs_compact
6975 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
6978 if (target_flags != save_flags && ! current_function_interrupt)
6979 emit_insn (gen_toggle_sz ());
6981 target_flags = save_flags;
6983 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
6984 stack_pointer_rtx, 0, NULL);
6986 if (frame_pointer_needed)
6987 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
6989 if (TARGET_SHCOMPACT
6990 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6992 /* This must NOT go through the PLT, otherwise mach and macl
6993 may be clobbered. */
6994 function_symbol (gen_rtx_REG (Pmode, R0_REG),
6995 "__GCC_shcompact_incoming_args", SFUNC_GOT);
6996 emit_insn (gen_shcompact_incoming_args ());
7001 sh_expand_epilogue (bool sibcall_p)
7003 HARD_REG_SET live_regs_mask;
7007 int save_flags = target_flags;
7008 int frame_size, save_size;
7009 int fpscr_deferred = 0;
7010 int e = sibcall_p ? -1 : 1;
7012 d = calc_live_regs (&live_regs_mask);
7015 frame_size = rounded_frame_size (d);
7019 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7021 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7022 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7023 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7025 total_size = d + tregs_space;
7026 total_size += rounded_frame_size (total_size);
7027 save_size = total_size - frame_size;
7029 /* If adjusting the stack in a single step costs nothing extra, do so.
7030 I.e. either if a single addi is enough, or we need a movi anyway,
7031 and we don't exceed the maximum offset range (the test for the
7032 latter is conservative for simplicity). */
7034 && ! frame_pointer_needed
7035 && (CONST_OK_FOR_I10 (total_size)
7036 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7037 && total_size <= 2044)))
7038 d_rounding = frame_size;
7040 frame_size -= d_rounding;
7043 if (frame_pointer_needed)
7045 /* We must avoid scheduling the epilogue with previous basic blocks.
7046 See PR/18032 and PR/40313. */
7047 emit_insn (gen_blockage ());
7048 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7051 /* We must avoid moving the stack pointer adjustment past code
7052 which reads from the local frame, else an interrupt could
7053 occur after the SP adjustment and clobber data in the local
7055 emit_insn (gen_blockage ());
7056 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7058 else if (frame_size)
7060 /* We must avoid moving the stack pointer adjustment past code
7061 which reads from the local frame, else an interrupt could
7062 occur after the SP adjustment and clobber data in the local
7064 emit_insn (gen_blockage ());
7065 output_stack_adjust (frame_size, stack_pointer_rtx, e, &live_regs_mask);
7068 if (SHMEDIA_REGS_STACK_ADJUST ())
7070 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7072 ? "__GCC_pop_shmedia_regs"
7073 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7074 /* This must NOT go through the PLT, otherwise mach and macl
7075 may be clobbered. */
7076 emit_insn (gen_shmedia_save_restore_regs_compact
7077 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7080 /* Pop all the registers. */
7082 if (target_flags != save_flags && ! current_function_interrupt)
7083 emit_insn (gen_toggle_sz ());
7086 int offset_base, offset;
7087 int offset_in_r0 = -1;
7089 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7090 save_schedule schedule;
7094 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7095 offset_base = -entry[1].offset + d_rounding;
7096 tmp_pnt = schedule.temps;
7097 for (; entry->mode != VOIDmode; entry--)
7099 enum machine_mode mode = (enum machine_mode) entry->mode;
7100 int reg = entry->reg;
7101 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7103 offset = offset_base + entry->offset;
7104 reg_rtx = gen_rtx_REG (mode, reg);
7106 mem_rtx = gen_frame_mem (mode,
7107 gen_rtx_PLUS (Pmode,
7111 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7114 if (HAVE_POST_INCREMENT
7115 && (offset == offset_in_r0
7116 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7117 && mem_rtx == NULL_RTX)
7118 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7120 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7122 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7123 post_inc = NULL_RTX;
7128 if (mem_rtx != NULL_RTX)
7131 if (offset_in_r0 == -1)
7133 emit_move_insn (r0, GEN_INT (offset));
7134 offset_in_r0 = offset;
7136 else if (offset != offset_in_r0)
7141 GEN_INT (offset - offset_in_r0)));
7142 offset_in_r0 += offset - offset_in_r0;
7145 if (post_inc != NULL_RTX)
7151 (Pmode, r0, stack_pointer_rtx));
7157 offset_in_r0 += GET_MODE_SIZE (mode);
7160 mem_rtx = gen_frame_mem (mode, r0);
7162 mem_rtx = gen_frame_mem (mode,
7163 gen_rtx_PLUS (Pmode,
7167 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7168 || mem_rtx == post_inc);
7171 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7172 && mem_rtx != post_inc)
7174 insn = emit_move_insn (r0, mem_rtx);
7177 else if (TARGET_REGISTER_P (reg))
7179 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7181 /* Give the scheduler a bit of freedom by using up to
7182 MAX_TEMPS registers in a round-robin fashion. */
7183 insn = emit_move_insn (tmp_reg, mem_rtx);
7186 tmp_pnt = schedule.temps;
7189 insn = emit_move_insn (reg_rtx, mem_rtx);
7192 gcc_assert (entry->offset + offset_base == d + d_rounding);
7194 else /* ! TARGET_SH5 */
7199 /* For an ISR with RESBANK attribute assigned, don't pop PR
7201 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7202 && !sh_cfun_resbank_handler_p ())
7204 if (!frame_pointer_needed)
7205 emit_insn (gen_blockage ());
7209 /* Banked registers are poped first to avoid being scheduled in the
7210 delay slot. RTE switches banks before the ds instruction. */
7211 if (current_function_interrupt)
7213 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7214 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7215 pop (LAST_BANKED_REG - i);
7217 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7220 last_reg = FIRST_PSEUDO_REGISTER;
7222 for (i = 0; i < last_reg; i++)
7224 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7226 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7227 && hard_reg_set_intersect_p (live_regs_mask,
7228 reg_class_contents[DF_REGS]))
7230 /* For an ISR with RESBANK attribute assigned, don't pop
7231 following registers, R0-R14, MACH, MACL and GBR. */
7232 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7233 && ! (sh_cfun_resbank_handler_p ()
7234 && ((j >= FIRST_GENERAL_REG
7235 && j < LAST_GENERAL_REG)
7241 if (j == FIRST_FP_REG && fpscr_deferred)
7245 if (target_flags != save_flags && ! current_function_interrupt)
7246 emit_insn (gen_toggle_sz ());
7247 target_flags = save_flags;
7249 output_stack_adjust (crtl->args.pretend_args_size
7250 + save_size + d_rounding
7251 + crtl->args.info.stack_regs * 8,
7252 stack_pointer_rtx, e, NULL);
7254 if (crtl->calls_eh_return)
7255 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7256 EH_RETURN_STACKADJ_RTX));
7258 /* Switch back to the normal stack if necessary. */
7259 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7260 emit_insn (gen_sp_switch_2 ());
7262 /* Tell flow the insn that pops PR isn't dead. */
7263 /* PR_REG will never be live in SHmedia mode, and we don't need to
7264 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7265 by the return pattern. */
7266 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7267 emit_use (gen_rtx_REG (SImode, PR_REG));
7270 static int sh_need_epilogue_known = 0;
7273 sh_need_epilogue (void)
7275 if (! sh_need_epilogue_known)
7280 sh_expand_epilogue (0);
7281 epilogue = get_insns ();
7283 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7285 return sh_need_epilogue_known > 0;
7288 /* Emit code to change the current function's return address to RA.
7289 TEMP is available as a scratch register, if needed. */
7292 sh_set_return_address (rtx ra, rtx tmp)
7294 HARD_REG_SET live_regs_mask;
7296 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7299 d = calc_live_regs (&live_regs_mask);
7301 /* If pr_reg isn't life, we can set it (or the register given in
7302 sh_media_register_for_return) directly. */
7303 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7309 int rr_regno = sh_media_register_for_return ();
7314 rr = gen_rtx_REG (DImode, rr_regno);
7317 rr = gen_rtx_REG (SImode, pr_reg);
7319 emit_insn (GEN_MOV (rr, ra));
7320 /* Tell flow the register for return isn't dead. */
7328 save_schedule schedule;
7331 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7332 offset = entry[1].offset;
7333 for (; entry->mode != VOIDmode; entry--)
7334 if (entry->reg == pr_reg)
7337 /* We can't find pr register. */
7341 offset = entry->offset - offset;
7342 pr_offset = (rounded_frame_size (d) + offset
7343 + SHMEDIA_REGS_STACK_ADJUST ());
7346 pr_offset = rounded_frame_size (d);
7348 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7349 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7351 tmp = gen_frame_mem (Pmode, tmp);
7352 emit_insn (GEN_MOV (tmp, ra));
7353 /* Tell this store isn't dead. */
7357 /* Clear variables at function end. */
7360 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7361 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7363 sh_need_epilogue_known = 0;
7367 sh_builtin_saveregs (void)
7369 /* First unnamed integer register. */
7370 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7371 /* Number of integer registers we need to save. */
7372 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7373 /* First unnamed SFmode float reg */
7374 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7375 /* Number of SFmode float regs to save. */
7376 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7379 alias_set_type alias_set;
7385 int pushregs = n_intregs;
7387 while (pushregs < NPARM_REGS (SImode) - 1
7388 && (CALL_COOKIE_INT_REG_GET
7389 (crtl->args.info.call_cookie,
7390 NPARM_REGS (SImode) - pushregs)
7393 crtl->args.info.call_cookie
7394 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7399 if (pushregs == NPARM_REGS (SImode))
7400 crtl->args.info.call_cookie
7401 |= (CALL_COOKIE_INT_REG (0, 1)
7402 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7404 crtl->args.info.call_cookie
7405 |= CALL_COOKIE_STACKSEQ (pushregs);
7407 crtl->args.pretend_args_size += 8 * n_intregs;
7409 if (TARGET_SHCOMPACT)
7413 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7415 error ("__builtin_saveregs not supported by this subtarget");
7422 /* Allocate block of memory for the regs. */
7423 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7424 Or can assign_stack_local accept a 0 SIZE argument? */
7425 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7428 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7429 else if (n_floatregs & 1)
7433 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7434 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7435 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7436 regbuf = change_address (regbuf, BLKmode, addr);
7438 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7442 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7443 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7444 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7445 emit_insn (gen_andsi3 (addr, addr, mask));
7446 regbuf = change_address (regbuf, BLKmode, addr);
7449 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7450 alias_set = get_varargs_alias_set ();
7451 set_mem_alias_set (regbuf, alias_set);
7454 This is optimized to only save the regs that are necessary. Explicitly
7455 named args need not be saved. */
7457 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7458 adjust_address (regbuf, BLKmode,
7459 n_floatregs * UNITS_PER_WORD),
7463 /* Return the address of the regbuf. */
7464 return XEXP (regbuf, 0);
7467 This is optimized to only save the regs that are necessary. Explicitly
7468 named args need not be saved.
7469 We explicitly build a pointer to the buffer because it halves the insn
7470 count when not optimizing (otherwise the pointer is built for each reg
7472 We emit the moves in reverse order so that we can use predecrement. */
7474 fpregs = copy_to_mode_reg (Pmode,
7475 plus_constant (XEXP (regbuf, 0),
7476 n_floatregs * UNITS_PER_WORD));
7477 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7480 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7482 emit_insn (gen_addsi3 (fpregs, fpregs,
7483 GEN_INT (-2 * UNITS_PER_WORD)));
7484 mem = change_address (regbuf, DFmode, fpregs);
7485 emit_move_insn (mem,
7486 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7488 regno = first_floatreg;
7491 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7492 mem = change_address (regbuf, SFmode, fpregs);
7493 emit_move_insn (mem,
7494 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7495 - (TARGET_LITTLE_ENDIAN != 0)));
7499 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7503 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7504 mem = change_address (regbuf, SFmode, fpregs);
7505 emit_move_insn (mem,
7506 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7509 /* Return the address of the regbuf. */
7510 return XEXP (regbuf, 0);
7513 /* Define the `__builtin_va_list' type for the ABI. */
7516 sh_build_builtin_va_list (void)
7518 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7521 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7522 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7523 return ptr_type_node;
7525 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7527 f_next_o = build_decl (BUILTINS_LOCATION,
7528 FIELD_DECL, get_identifier ("__va_next_o"),
7530 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7532 get_identifier ("__va_next_o_limit"),
7534 f_next_fp = build_decl (BUILTINS_LOCATION,
7535 FIELD_DECL, get_identifier ("__va_next_fp"),
7537 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7539 get_identifier ("__va_next_fp_limit"),
7541 f_next_stack = build_decl (BUILTINS_LOCATION,
7542 FIELD_DECL, get_identifier ("__va_next_stack"),
7545 DECL_FIELD_CONTEXT (f_next_o) = record;
7546 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7547 DECL_FIELD_CONTEXT (f_next_fp) = record;
7548 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7549 DECL_FIELD_CONTEXT (f_next_stack) = record;
7551 TYPE_FIELDS (record) = f_next_o;
7552 TREE_CHAIN (f_next_o) = f_next_o_limit;
7553 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7554 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7555 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7557 layout_type (record);
7562 /* Implement `va_start' for varargs and stdarg. */
7565 sh_va_start (tree valist, rtx nextarg)
7567 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7568 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7574 expand_builtin_saveregs ();
7575 std_expand_builtin_va_start (valist, nextarg);
7579 if ((! TARGET_SH2E && ! TARGET_SH4)
7580 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7582 std_expand_builtin_va_start (valist, nextarg);
7586 f_next_o = TYPE_FIELDS (va_list_type_node);
7587 f_next_o_limit = TREE_CHAIN (f_next_o);
7588 f_next_fp = TREE_CHAIN (f_next_o_limit);
7589 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7590 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7592 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7594 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7595 valist, f_next_o_limit, NULL_TREE);
7596 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7598 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7599 valist, f_next_fp_limit, NULL_TREE);
7600 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7601 valist, f_next_stack, NULL_TREE);
7603 /* Call __builtin_saveregs. */
7604 u = make_tree (sizetype, expand_builtin_saveregs ());
7605 u = fold_convert (ptr_type_node, u);
7606 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7607 TREE_SIDE_EFFECTS (t) = 1;
7608 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7610 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7615 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7616 size_int (UNITS_PER_WORD * nfp));
7617 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7618 TREE_SIDE_EFFECTS (t) = 1;
7619 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7621 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7622 TREE_SIDE_EFFECTS (t) = 1;
7623 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7625 nint = crtl->args.info.arg_count[SH_ARG_INT];
7630 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7631 size_int (UNITS_PER_WORD * nint));
7632 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7633 TREE_SIDE_EFFECTS (t) = 1;
7634 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7636 u = make_tree (ptr_type_node, nextarg);
7637 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7638 TREE_SIDE_EFFECTS (t) = 1;
7639 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7642 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7643 member, return it. */
7645 find_sole_member (tree type)
7647 tree field, member = NULL_TREE;
7649 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7651 if (TREE_CODE (field) != FIELD_DECL)
7653 if (!DECL_SIZE (field))
7655 if (integer_zerop (DECL_SIZE (field)))
7663 /* Implement `va_arg'. */
7666 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7667 gimple_seq *post_p ATTRIBUTE_UNUSED)
7669 HOST_WIDE_INT size, rsize;
7670 tree tmp, pptr_type_node;
7671 tree addr, lab_over = NULL, result = NULL;
7672 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7676 type = build_pointer_type (type);
7678 size = int_size_in_bytes (type);
7679 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7680 pptr_type_node = build_pointer_type (ptr_type_node);
7682 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7683 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7685 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7686 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7691 f_next_o = TYPE_FIELDS (va_list_type_node);
7692 f_next_o_limit = TREE_CHAIN (f_next_o);
7693 f_next_fp = TREE_CHAIN (f_next_o_limit);
7694 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7695 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7697 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7699 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7700 valist, f_next_o_limit, NULL_TREE);
7701 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7702 valist, f_next_fp, NULL_TREE);
7703 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7704 valist, f_next_fp_limit, NULL_TREE);
7705 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7706 valist, f_next_stack, NULL_TREE);
7708 /* Structures with a single member with a distinct mode are passed
7709 like their member. This is relevant if the latter has a REAL_TYPE
7710 or COMPLEX_TYPE type. */
7712 while (TREE_CODE (eff_type) == RECORD_TYPE
7713 && (member = find_sole_member (eff_type))
7714 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7715 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7716 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7718 tree field_type = TREE_TYPE (member);
7720 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7721 eff_type = field_type;
7724 gcc_assert ((TYPE_ALIGN (eff_type)
7725 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7726 || (TYPE_ALIGN (eff_type)
7727 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7732 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7734 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7735 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7736 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7741 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7744 addr = create_tmp_var (pptr_type_node, NULL);
7745 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7746 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7748 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7752 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7754 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7756 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7757 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7759 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7760 tmp = next_fp_limit;
7761 if (size > 4 && !is_double)
7762 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7763 unshare_expr (tmp), size_int (4 - size));
7764 tmp = build2 (GE_EXPR, boolean_type_node,
7765 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7766 cmp = build3 (COND_EXPR, void_type_node, tmp,
7767 build1 (GOTO_EXPR, void_type_node,
7768 unshare_expr (lab_false)), NULL_TREE);
7770 gimplify_and_add (cmp, pre_p);
7772 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7773 || (is_double || size == 16))
7775 tmp = fold_convert (sizetype, next_fp_tmp);
7776 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7777 size_int (UNITS_PER_WORD));
7778 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7779 unshare_expr (next_fp_tmp), tmp);
7780 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7783 gimplify_and_add (cmp, pre_p);
7785 #ifdef FUNCTION_ARG_SCmode_WART
7786 if (TYPE_MODE (eff_type) == SCmode
7787 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7789 tree subtype = TREE_TYPE (eff_type);
7793 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7794 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7797 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7798 real = get_initialized_tmp_var (real, pre_p, NULL);
7800 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7801 if (type != eff_type)
7802 result = build1 (VIEW_CONVERT_EXPR, type, result);
7803 result = get_initialized_tmp_var (result, pre_p, NULL);
7805 #endif /* FUNCTION_ARG_SCmode_WART */
7807 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7808 gimplify_and_add (tmp, pre_p);
7810 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7811 gimplify_and_add (tmp, pre_p);
7813 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7814 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7815 gimplify_assign (unshare_expr (next_fp_tmp),
7816 unshare_expr (valist), pre_p);
7818 gimplify_assign (unshare_expr (valist),
7819 unshare_expr (next_fp_tmp), post_p);
7820 valist = next_fp_tmp;
7824 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7825 unshare_expr (next_o), size_int (rsize));
7826 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7827 unshare_expr (next_o_limit));
7828 tmp = build3 (COND_EXPR, void_type_node, tmp,
7829 build1 (GOTO_EXPR, void_type_node,
7830 unshare_expr (lab_false)),
7832 gimplify_and_add (tmp, pre_p);
7834 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7835 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7837 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7838 gimplify_and_add (tmp, pre_p);
7840 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7841 gimplify_and_add (tmp, pre_p);
7843 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7844 gimplify_assign (unshare_expr (next_o),
7845 unshare_expr (next_o_limit), pre_p);
7847 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7848 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7853 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7854 gimplify_and_add (tmp, pre_p);
7858 /* ??? In va-sh.h, there had been code to make values larger than
7859 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7861 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7864 gimplify_assign (result, tmp, pre_p);
7866 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7867 gimplify_and_add (tmp, pre_p);
7873 result = build_va_arg_indirect_ref (result);
7878 /* 64 bit floating points memory transfers are paired single precision loads
7879 or store. So DWARF information needs fixing in little endian (unless
7880 PR=SZ=1 in FPSCR). */
7882 sh_dwarf_register_span (rtx reg)
7884 unsigned regno = REGNO (reg);
7886 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7890 gen_rtx_PARALLEL (VOIDmode,
7892 gen_rtx_REG (SFmode,
7893 DBX_REGISTER_NUMBER (regno+1)),
7894 gen_rtx_REG (SFmode,
7895 DBX_REGISTER_NUMBER (regno))));
7899 sh_promote_prototypes (const_tree type)
7905 return ! sh_attr_renesas_p (type);
7908 /* Whether an argument must be passed by reference. On SHcompact, we
7909 pretend arguments wider than 32-bits that would have been passed in
7910 registers are passed by reference, so that an SHmedia trampoline
7911 loads them into the full 64-bits registers. */
7914 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
7915 const_tree type, bool named)
7917 unsigned HOST_WIDE_INT size;
7920 size = int_size_in_bytes (type);
7922 size = GET_MODE_SIZE (mode);
7924 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
7926 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
7927 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
7928 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
7930 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
7931 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7938 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7939 const_tree type, bool named)
7941 if (targetm.calls.must_pass_in_stack (mode, type))
7944 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7945 wants to know about pass-by-reference semantics for incoming
7950 if (TARGET_SHCOMPACT)
7952 cum->byref = shcompact_byref (cum, mode, type, named);
7953 return cum->byref != 0;
7960 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7961 const_tree type, bool named ATTRIBUTE_UNUSED)
7963 /* ??? How can it possibly be correct to return true only on the
7964 caller side of the equation? Is there someplace else in the
7965 sh backend that's magically producing the copies? */
7966 return (cum->outgoing
7967 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7968 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7972 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7973 tree type, bool named ATTRIBUTE_UNUSED)
7978 && PASS_IN_REG_P (*cum, mode, type)
7979 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7980 && (ROUND_REG (*cum, mode)
7982 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
7983 : ROUND_ADVANCE (int_size_in_bytes (type)))
7984 > NPARM_REGS (mode)))
7985 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
7987 else if (!TARGET_SHCOMPACT
7988 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
7989 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
7991 return words * UNITS_PER_WORD;
7995 /* Define where to put the arguments to a function.
7996 Value is zero to push the argument on the stack,
7997 or a hard register in which to store the argument.
7999 MODE is the argument's machine mode.
8000 TYPE is the data type of the argument (as a tree).
8001 This is null for libcalls where that information may
8003 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8004 the preceding args and about the function being called.
8005 NAMED is nonzero if this argument is a named parameter
8006 (otherwise it is an extra parameter matching an ellipsis).
8008 On SH the first args are normally in registers
8009 and the rest are pushed. Any arg that starts within the first
8010 NPARM_REGS words is at least partially passed in a register unless
8011 its data type forbids. */
8015 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8016 tree type, int named)
8018 if (! TARGET_SH5 && mode == VOIDmode)
8019 return GEN_INT (ca->renesas_abi ? 1 : 0);
8022 && PASS_IN_REG_P (*ca, mode, type)
8023 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8027 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8028 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8030 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8031 gen_rtx_REG (SFmode,
8033 + (ROUND_REG (*ca, mode) ^ 1)),
8035 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8036 gen_rtx_REG (SFmode,
8038 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8040 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8043 /* If the alignment of a DF value causes an SF register to be
8044 skipped, we will use that skipped register for the next SF
8046 if ((TARGET_HITACHI || ca->renesas_abi)
8047 && ca->free_single_fp_reg
8049 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8051 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8052 ^ (mode == SFmode && TARGET_SH4
8053 && TARGET_LITTLE_ENDIAN != 0
8054 && ! TARGET_HITACHI && ! ca->renesas_abi);
8055 return gen_rtx_REG (mode, regno);
8061 if (mode == VOIDmode && TARGET_SHCOMPACT)
8062 return GEN_INT (ca->call_cookie);
8064 /* The following test assumes unnamed arguments are promoted to
8066 if (mode == SFmode && ca->free_single_fp_reg)
8067 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8069 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8070 && (named || ! ca->prototype_p)
8071 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8073 if (! ca->prototype_p && TARGET_SHMEDIA)
8074 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8076 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8078 + ca->arg_count[(int) SH_ARG_FLOAT]);
8081 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8082 && (! TARGET_SHCOMPACT
8083 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8084 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8087 return gen_rtx_REG (mode, (FIRST_PARM_REG
8088 + ca->arg_count[(int) SH_ARG_INT]));
8097 /* Update the data in CUM to advance over an argument
8098 of mode MODE and data type TYPE.
8099 (TYPE is null for libcalls where that information may not be
8103 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8104 tree type, int named)
8108 else if (TARGET_SH5)
8110 tree type2 = (ca->byref && type
8113 enum machine_mode mode2 = (ca->byref && type
8116 int dwords = ((ca->byref
8119 ? int_size_in_bytes (type2)
8120 : GET_MODE_SIZE (mode2)) + 7) / 8;
8121 int numregs = MIN (dwords, NPARM_REGS (SImode)
8122 - ca->arg_count[(int) SH_ARG_INT]);
8126 ca->arg_count[(int) SH_ARG_INT] += numregs;
8127 if (TARGET_SHCOMPACT
8128 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8131 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8133 /* N.B. We want this also for outgoing. */
8134 ca->stack_regs += numregs;
8139 ca->stack_regs += numregs;
8140 ca->byref_regs += numregs;
8144 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8148 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8151 else if (dwords > numregs)
8153 int pushregs = numregs;
8155 if (TARGET_SHCOMPACT)
8156 ca->stack_regs += numregs;
8157 while (pushregs < NPARM_REGS (SImode) - 1
8158 && (CALL_COOKIE_INT_REG_GET
8160 NPARM_REGS (SImode) - pushregs)
8164 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8168 if (numregs == NPARM_REGS (SImode))
8170 |= CALL_COOKIE_INT_REG (0, 1)
8171 | CALL_COOKIE_STACKSEQ (numregs - 1);
8174 |= CALL_COOKIE_STACKSEQ (numregs);
8177 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8178 && (named || ! ca->prototype_p))
8180 if (mode2 == SFmode && ca->free_single_fp_reg)
8181 ca->free_single_fp_reg = 0;
8182 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8183 < NPARM_REGS (SFmode))
8186 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8188 - ca->arg_count[(int) SH_ARG_FLOAT]);
8190 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8192 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8194 if (ca->outgoing && numregs > 0)
8198 |= (CALL_COOKIE_INT_REG
8199 (ca->arg_count[(int) SH_ARG_INT]
8200 - numregs + ((numfpregs - 2) / 2),
8201 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8204 while (numfpregs -= 2);
8206 else if (mode2 == SFmode && (named)
8207 && (ca->arg_count[(int) SH_ARG_FLOAT]
8208 < NPARM_REGS (SFmode)))
8209 ca->free_single_fp_reg
8210 = FIRST_FP_PARM_REG - numfpregs
8211 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8217 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8219 /* Note that we've used the skipped register. */
8220 if (mode == SFmode && ca->free_single_fp_reg)
8222 ca->free_single_fp_reg = 0;
8225 /* When we have a DF after an SF, there's an SF register that get
8226 skipped in order to align the DF value. We note this skipped
8227 register, because the next SF value will use it, and not the
8228 SF that follows the DF. */
8230 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8232 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8233 + BASE_ARG_REG (mode));
8237 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8238 || PASS_IN_REG_P (*ca, mode, type))
8239 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8240 = (ROUND_REG (*ca, mode)
8242 ? ROUND_ADVANCE (int_size_in_bytes (type))
8243 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8246 /* The Renesas calling convention doesn't quite fit into this scheme since
8247 the address is passed like an invisible argument, but one that is always
8248 passed in memory. */
8250 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8252 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8254 return gen_rtx_REG (Pmode, 2);
8257 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8260 sh_return_in_memory (const_tree type, const_tree fndecl)
8264 if (TYPE_MODE (type) == BLKmode)
8265 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8267 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8271 return (TYPE_MODE (type) == BLKmode
8272 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8273 && TREE_CODE (type) == RECORD_TYPE));
8277 /* We actually emit the code in sh_expand_prologue. We used to use
8278 a static variable to flag that we need to emit this code, but that
8279 doesn't when inlining, when functions are deferred and then emitted
8280 later. Fortunately, we already have two flags that are part of struct
8281 function that tell if a function uses varargs or stdarg. */
8283 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8284 enum machine_mode mode,
8286 int *pretend_arg_size,
8287 int second_time ATTRIBUTE_UNUSED)
8289 gcc_assert (cfun->stdarg);
8290 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8292 int named_parm_regs, anon_parm_regs;
8294 named_parm_regs = (ROUND_REG (*ca, mode)
8296 ? ROUND_ADVANCE (int_size_in_bytes (type))
8297 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8298 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8299 if (anon_parm_regs > 0)
8300 *pretend_arg_size = anon_parm_regs * 4;
8305 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8311 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8313 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8317 /* Define the offset between two registers, one to be eliminated, and
8318 the other its replacement, at the start of a routine. */
8321 initial_elimination_offset (int from, int to)
8324 int regs_saved_rounding = 0;
8325 int total_saved_regs_space;
8326 int total_auto_space;
8327 int save_flags = target_flags;
8329 HARD_REG_SET live_regs_mask;
8331 shmedia_space_reserved_for_target_registers = false;
8332 regs_saved = calc_live_regs (&live_regs_mask);
8333 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8335 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8337 shmedia_space_reserved_for_target_registers = true;
8338 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8341 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8342 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8343 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8345 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8346 copy_flags = target_flags;
8347 target_flags = save_flags;
8349 total_saved_regs_space = regs_saved + regs_saved_rounding;
8351 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8352 return total_saved_regs_space + total_auto_space
8353 + crtl->args.info.byref_regs * 8;
8355 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8356 return total_saved_regs_space + total_auto_space
8357 + crtl->args.info.byref_regs * 8;
8359 /* Initial gap between fp and sp is 0. */
8360 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8363 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8364 return rounded_frame_size (0);
8366 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8367 return rounded_frame_size (0);
8369 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8370 && (to == HARD_FRAME_POINTER_REGNUM
8371 || to == STACK_POINTER_REGNUM));
8374 int n = total_saved_regs_space;
8375 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8376 save_schedule schedule;
8379 n += total_auto_space;
8381 /* If it wasn't saved, there's not much we can do. */
8382 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8385 target_flags = copy_flags;
8387 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8388 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8389 if (entry->reg == pr_reg)
8391 target_flags = save_flags;
8392 return entry->offset;
8397 return total_auto_space;
8400 /* Parse the -mfixed-range= option string. */
8402 sh_fix_range (const char *const_str)
8405 char *str, *dash, *comma;
8407 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8408 REG2 are either register names or register numbers. The effect
8409 of this option is to mark the registers in the range from REG1 to
8410 REG2 as ``fixed'' so they won't be used by the compiler. */
8412 i = strlen (const_str);
8413 str = (char *) alloca (i + 1);
8414 memcpy (str, const_str, i + 1);
8418 dash = strchr (str, '-');
8421 warning (0, "value of -mfixed-range must have form REG1-REG2");
8425 comma = strchr (dash + 1, ',');
8429 first = decode_reg_name (str);
8432 warning (0, "unknown register name: %s", str);
8436 last = decode_reg_name (dash + 1);
8439 warning (0, "unknown register name: %s", dash + 1);
8447 warning (0, "%s-%s is an empty range", str, dash + 1);
8451 for (i = first; i <= last; ++i)
8452 fixed_regs[i] = call_used_regs[i] = 1;
8462 /* Insert any deferred function attributes from earlier pragmas. */
8464 sh_insert_attributes (tree node, tree *attributes)
8468 if (TREE_CODE (node) != FUNCTION_DECL)
8471 /* We are only interested in fields. */
8475 /* Append the attributes to the deferred attributes. */
8476 *sh_deferred_function_attributes_tail = *attributes;
8477 attrs = sh_deferred_function_attributes;
8481 /* Some attributes imply or require the interrupt attribute. */
8482 if (!lookup_attribute ("interrupt_handler", attrs)
8483 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8485 /* If we have a trapa_handler, but no interrupt_handler attribute,
8486 insert an interrupt_handler attribute. */
8487 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8488 /* We can't use sh_pr_interrupt here because that's not in the
8491 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8492 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8493 if the interrupt attribute is missing, we ignore the attribute
8495 else if (lookup_attribute ("sp_switch", attrs)
8496 || lookup_attribute ("trap_exit", attrs)
8497 || lookup_attribute ("nosave_low_regs", attrs)
8498 || lookup_attribute ("resbank", attrs))
8502 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8504 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8505 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8506 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8507 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8508 warning (OPT_Wattributes,
8509 "%qE attribute only applies to interrupt functions",
8510 TREE_PURPOSE (attrs));
8513 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8515 tail = &TREE_CHAIN (*tail);
8518 attrs = *attributes;
8522 /* Install the processed list. */
8523 *attributes = attrs;
8525 /* Clear deferred attributes. */
8526 sh_deferred_function_attributes = NULL_TREE;
8527 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8532 /* Supported attributes:
8534 interrupt_handler -- specifies this function is an interrupt handler.
8536 trapa_handler - like above, but don't save all registers.
8538 sp_switch -- specifies an alternate stack for an interrupt handler
8541 trap_exit -- use a trapa to exit an interrupt function instead of
8544 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8545 This is useful on the SH3 and upwards,
8546 which has a separate set of low regs for User and Supervisor modes.
8547 This should only be used for the lowest level of interrupts. Higher levels
8548 of interrupts must save the registers in case they themselves are
8551 renesas -- use Renesas calling/layout conventions (functions and
8554 resbank -- In case of an ISR, use a register bank to save registers
8555 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8558 /* Handle a 'resbank' attribute. */
8560 sh_handle_resbank_handler_attribute (tree * node, tree name,
8561 tree args ATTRIBUTE_UNUSED,
8562 int flags ATTRIBUTE_UNUSED,
8563 bool * no_add_attrs)
8567 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8569 *no_add_attrs = true;
8571 if (TREE_CODE (*node) != FUNCTION_DECL)
8573 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8575 *no_add_attrs = true;
8581 /* Handle an "interrupt_handler" attribute; arguments as in
8582 struct attribute_spec.handler. */
8584 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8585 tree args ATTRIBUTE_UNUSED,
8586 int flags ATTRIBUTE_UNUSED,
8589 if (TREE_CODE (*node) != FUNCTION_DECL)
8591 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8593 *no_add_attrs = true;
8595 else if (TARGET_SHCOMPACT)
8597 error ("attribute interrupt_handler is not compatible with -m5-compact");
8598 *no_add_attrs = true;
8604 /* Handle an 'function_vector' attribute; arguments as in
8605 struct attribute_spec.handler. */
8607 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8608 tree args ATTRIBUTE_UNUSED,
8609 int flags ATTRIBUTE_UNUSED,
8610 bool * no_add_attrs)
8614 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8616 *no_add_attrs = true;
8618 else if (TREE_CODE (*node) != FUNCTION_DECL)
8620 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8622 *no_add_attrs = true;
8624 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8626 /* The argument must be a constant integer. */
8627 warning (OPT_Wattributes,
8628 "%qE attribute argument not an integer constant",
8630 *no_add_attrs = true;
8632 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8634 /* The argument value must be between 0 to 255. */
8635 warning (OPT_Wattributes,
8636 "%qE attribute argument should be between 0 to 255",
8638 *no_add_attrs = true;
8643 /* Returns 1 if current function has been assigned the attribute
8644 'function_vector'. */
8646 sh2a_is_function_vector_call (rtx x)
8648 if (GET_CODE (x) == SYMBOL_REF
8649 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8651 tree tr = SYMBOL_REF_DECL (x);
8653 if (sh2a_function_vector_p (tr))
8660 /* Returns the function vector number, if the the attribute
8661 'function_vector' is assigned, otherwise returns zero. */
8663 sh2a_get_function_vector_number (rtx x)
8668 if ((GET_CODE (x) == SYMBOL_REF)
8669 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8671 t = SYMBOL_REF_DECL (x);
8673 if (TREE_CODE (t) != FUNCTION_DECL)
8676 list = SH_ATTRIBUTES (t);
8679 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8681 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8685 list = TREE_CHAIN (list);
8694 /* Handle an "sp_switch" attribute; arguments as in
8695 struct attribute_spec.handler. */
8697 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8698 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8700 if (TREE_CODE (*node) != FUNCTION_DECL)
8702 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8704 *no_add_attrs = true;
8706 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8708 /* The argument must be a constant string. */
8709 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8711 *no_add_attrs = true;
8717 /* Handle an "trap_exit" attribute; arguments as in
8718 struct attribute_spec.handler. */
8720 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8721 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8723 if (TREE_CODE (*node) != FUNCTION_DECL)
8725 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8727 *no_add_attrs = true;
8729 /* The argument specifies a trap number to be used in a trapa instruction
8730 at function exit (instead of an rte instruction). */
8731 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8733 /* The argument must be a constant integer. */
8734 warning (OPT_Wattributes, "%qE attribute argument not an "
8735 "integer constant", name);
8736 *no_add_attrs = true;
8743 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8744 tree name ATTRIBUTE_UNUSED,
8745 tree args ATTRIBUTE_UNUSED,
8746 int flags ATTRIBUTE_UNUSED,
8747 bool *no_add_attrs ATTRIBUTE_UNUSED)
8752 /* True if __attribute__((renesas)) or -mrenesas. */
8754 sh_attr_renesas_p (const_tree td)
8761 td = TREE_TYPE (td);
8762 if (td == error_mark_node)
8764 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8768 /* True if __attribute__((renesas)) or -mrenesas, for the current
8771 sh_cfun_attr_renesas_p (void)
8773 return sh_attr_renesas_p (current_function_decl);
8777 sh_cfun_interrupt_handler_p (void)
8779 return (lookup_attribute ("interrupt_handler",
8780 DECL_ATTRIBUTES (current_function_decl))
8784 /* Returns 1 if FUNC has been assigned the attribute
8785 "function_vector". */
8787 sh2a_function_vector_p (tree func)
8790 if (TREE_CODE (func) != FUNCTION_DECL)
8793 list = SH_ATTRIBUTES (func);
8796 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8799 list = TREE_CHAIN (list);
8804 /* Returns TRUE if given tree has the "resbank" attribute. */
8807 sh_cfun_resbank_handler_p (void)
8809 return ((lookup_attribute ("resbank",
8810 DECL_ATTRIBUTES (current_function_decl))
8812 && (lookup_attribute ("interrupt_handler",
8813 DECL_ATTRIBUTES (current_function_decl))
8814 != NULL_TREE) && TARGET_SH2A);
8817 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8820 sh_check_pch_target_flags (int old_flags)
8822 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8823 | MASK_SH_E | MASK_HARD_SH4
8824 | MASK_FPU_SINGLE | MASK_SH4))
8825 return _("created and used with different architectures / ABIs");
8826 if ((old_flags ^ target_flags) & MASK_HITACHI)
8827 return _("created and used with different ABIs");
8828 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8829 return _("created and used with different endianness");
8833 /* Predicates used by the templates. */
8835 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
8836 Used only in general_movsrc_operand. */
8839 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8851 /* Nonzero if OP is a floating point value with value 0.0. */
8854 fp_zero_operand (rtx op)
8858 if (GET_MODE (op) != SFmode)
8861 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8862 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
8865 /* Nonzero if OP is a floating point value with value 1.0. */
8868 fp_one_operand (rtx op)
8872 if (GET_MODE (op) != SFmode)
8875 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
8876 return REAL_VALUES_EQUAL (r, dconst1);
8879 /* For -m4 and -m4-single-only, mode switching is used. If we are
8880 compiling without -mfmovd, movsf_ie isn't taken into account for
8881 mode switching. We could check in machine_dependent_reorg for
8882 cases where we know we are in single precision mode, but there is
8883 interface to find that out during reload, so we must avoid
8884 choosing an fldi alternative during reload and thus failing to
8885 allocate a scratch register for the constant loading. */
8889 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
8893 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8895 enum rtx_code code = GET_CODE (op);
8896 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
8899 /* Return the TLS type for TLS symbols, 0 for otherwise. */
8901 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8903 if (GET_CODE (op) != SYMBOL_REF)
8904 return TLS_MODEL_NONE;
8905 return SYMBOL_REF_TLS_MODEL (op);
8908 /* Return the destination address of a branch. */
8911 branch_dest (rtx branch)
8913 rtx dest = SET_SRC (PATTERN (branch));
8916 if (GET_CODE (dest) == IF_THEN_ELSE)
8917 dest = XEXP (dest, 1);
8918 dest = XEXP (dest, 0);
8919 dest_uid = INSN_UID (dest);
8920 return INSN_ADDRESSES (dest_uid);
8923 /* Return nonzero if REG is not used after INSN.
8924 We assume REG is a reload reg, and therefore does
8925 not live past labels. It may live past calls or jumps though. */
8927 reg_unused_after (rtx reg, rtx insn)
8932 /* If the reg is set by this instruction, then it is safe for our
8933 case. Disregard the case where this is a store to memory, since
8934 we are checking a register used in the store address. */
8935 set = single_set (insn);
8936 if (set && !MEM_P (SET_DEST (set))
8937 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8940 while ((insn = NEXT_INSN (insn)))
8946 code = GET_CODE (insn);
8949 /* If this is a label that existed before reload, then the register
8950 if dead here. However, if this is a label added by reorg, then
8951 the register may still be live here. We can't tell the difference,
8952 so we just ignore labels completely. */
8953 if (code == CODE_LABEL)
8958 if (code == JUMP_INSN)
8961 /* If this is a sequence, we must handle them all at once.
8962 We could have for instance a call that sets the target register,
8963 and an insn in a delay slot that uses the register. In this case,
8964 we must return 0. */
8965 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8972 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
8973 rtx set = single_set (this_insn);
8975 if (CALL_P (this_insn))
8977 else if (JUMP_P (this_insn))
8979 if (INSN_ANNULLED_BRANCH_P (this_insn))
8984 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8986 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8988 if (!MEM_P (SET_DEST (set)))
8994 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8999 else if (code == JUMP_INSN)
9003 set = single_set (insn);
9004 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9006 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9007 return !MEM_P (SET_DEST (set));
9008 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9011 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9019 static GTY(()) rtx fpscr_rtx;
9021 get_fpscr_rtx (void)
9025 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9026 REG_USERVAR_P (fpscr_rtx) = 1;
9027 mark_user_reg (fpscr_rtx);
9029 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9030 mark_user_reg (fpscr_rtx);
9034 static GTY(()) tree fpscr_values;
9037 emit_fpu_switch (rtx scratch, int index)
9041 if (fpscr_values == NULL)
9045 t = build_index_type (integer_one_node);
9046 t = build_array_type (integer_type_node, t);
9047 t = build_decl (BUILTINS_LOCATION,
9048 VAR_DECL, get_identifier ("__fpscr_values"), t);
9049 DECL_ARTIFICIAL (t) = 1;
9050 DECL_IGNORED_P (t) = 1;
9051 DECL_EXTERNAL (t) = 1;
9052 TREE_STATIC (t) = 1;
9053 TREE_PUBLIC (t) = 1;
9059 src = DECL_RTL (fpscr_values);
9060 if (!can_create_pseudo_p ())
9062 emit_move_insn (scratch, XEXP (src, 0));
9064 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9065 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9068 src = adjust_address (src, PSImode, index * 4);
9070 dst = get_fpscr_rtx ();
9071 emit_move_insn (dst, src);
9075 emit_sf_insn (rtx pat)
9081 emit_df_insn (rtx pat)
9087 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9089 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9093 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9095 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9100 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9102 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9106 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9108 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9112 static rtx get_free_reg (HARD_REG_SET);
9114 /* This function returns a register to use to load the address to load
9115 the fpscr from. Currently it always returns r1 or r7, but when we are
9116 able to use pseudo registers after combine, or have a better mechanism
9117 for choosing a register, it should be done here. */
9118 /* REGS_LIVE is the liveness information for the point for which we
9119 need this allocation. In some bare-bones exit blocks, r1 is live at the
9120 start. We can even have all of r0..r3 being live:
9121 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9122 INSN before which new insns are placed with will clobber the register
9123 we return. If a basic block consists only of setting the return value
9124 register to a pseudo and using that register, the return value is not
9125 live before or after this block, yet we we'll insert our insns right in
9129 get_free_reg (HARD_REG_SET regs_live)
9131 if (! TEST_HARD_REG_BIT (regs_live, 1))
9132 return gen_rtx_REG (Pmode, 1);
9134 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
9135 there shouldn't be anything but a jump before the function end. */
9136 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9137 return gen_rtx_REG (Pmode, 7);
9140 /* This function will set the fpscr from memory.
9141 MODE is the mode we are setting it to. */
9143 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9145 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9146 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9149 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9150 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9153 /* Is the given character a logical line separator for the assembler? */
9154 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9155 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9159 sh_insn_length_adjustment (rtx insn)
9161 /* Instructions with unfilled delay slots take up an extra two bytes for
9162 the nop in the delay slot. */
9163 if (((NONJUMP_INSN_P (insn)
9164 && GET_CODE (PATTERN (insn)) != USE
9165 && GET_CODE (PATTERN (insn)) != CLOBBER)
9168 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9169 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
9170 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9171 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9174 /* SH2e has a bug that prevents the use of annulled branches, so if
9175 the delay slot is not filled, we'll have to put a NOP in it. */
9176 if (sh_cpu_attr == CPU_SH2E
9178 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9179 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9180 && get_attr_type (insn) == TYPE_CBRANCH
9181 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9184 /* sh-dsp parallel processing insn take four bytes instead of two. */
9186 if (NONJUMP_INSN_P (insn))
9189 rtx body = PATTERN (insn);
9192 int maybe_label = 1;
9194 if (GET_CODE (body) == ASM_INPUT)
9195 templ = XSTR (body, 0);
9196 else if (asm_noperands (body) >= 0)
9198 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9207 while (c == ' ' || c == '\t');
9208 /* all sh-dsp parallel-processing insns start with p.
9209 The only non-ppi sh insn starting with p is pref.
9210 The only ppi starting with pr is prnd. */
9211 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9213 /* The repeat pseudo-insn expands two three insns, a total of
9214 six bytes in size. */
9215 else if ((c == 'r' || c == 'R')
9216 && ! strncasecmp ("epeat", templ, 5))
9218 while (c && c != '\n'
9219 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9221 /* If this is a label, it is obviously not a ppi insn. */
9222 if (c == ':' && maybe_label)
9227 else if (c == '\'' || c == '"')
9232 maybe_label = c != ':';
9240 /* Return TRUE for a valid displacement for the REG+disp addressing
9243 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9244 into the FRx registers. We implement this by setting the maximum offset
9245 to zero when the value is SFmode. This also restricts loading of SFmode
9246 values into the integer registers, but that can't be helped. */
9248 /* The SH allows a displacement in a QI or HI amode, but only when the
9249 other operand is R0. GCC doesn't handle this very well, so we forgot
9252 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9253 DI can be any number 0..60. */
9256 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9258 if (CONST_INT_P (op))
9264 /* Check if this the address of an unaligned load / store. */
9265 if (mode == VOIDmode)
9266 return CONST_OK_FOR_I06 (INTVAL (op));
9268 size = GET_MODE_SIZE (mode);
9269 return (!(INTVAL (op) & (size - 1))
9270 && INTVAL (op) >= -512 * size
9271 && INTVAL (op) < 512 * size);
9276 if (GET_MODE_SIZE (mode) == 1
9277 && (unsigned) INTVAL (op) < 4096)
9281 if ((GET_MODE_SIZE (mode) == 4
9282 && (unsigned) INTVAL (op) < 64
9283 && !(INTVAL (op) & 3)
9284 && !(TARGET_SH2E && mode == SFmode))
9285 || (GET_MODE_SIZE (mode) == 4
9286 && (unsigned) INTVAL (op) < 16383
9287 && !(INTVAL (op) & 3) && TARGET_SH2A))
9290 if ((GET_MODE_SIZE (mode) == 8
9291 && (unsigned) INTVAL (op) < 60
9292 && !(INTVAL (op) & 3)
9293 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9294 || ((GET_MODE_SIZE (mode)==8)
9295 && (unsigned) INTVAL (op) < 8192
9296 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9297 && (TARGET_SH2A && mode == DFmode)))
9304 /* Recognize an RTL expression that is a valid memory address for
9306 The MODE argument is the machine mode for the MEM expression
9307 that wants to use this address.
9315 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9317 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9319 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9321 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9323 else if (GET_CODE (x) == PLUS
9324 && (mode != PSImode || reload_completed))
9326 rtx xop0 = XEXP (x, 0);
9327 rtx xop1 = XEXP (x, 1);
9329 if (GET_MODE_SIZE (mode) <= 8
9330 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9331 && sh_legitimate_index_p (mode, xop1))
9334 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9335 || ((xop0 == stack_pointer_rtx
9336 || xop0 == hard_frame_pointer_rtx)
9337 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9338 || ((xop1 == stack_pointer_rtx
9339 || xop1 == hard_frame_pointer_rtx)
9340 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9341 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9342 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9343 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9344 && TARGET_FMOVD && mode == DFmode)))
9346 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9347 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9349 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9350 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9358 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9359 isn't protected by a PIC unspec. */
9361 nonpic_symbol_mentioned_p (rtx x)
9363 register const char *fmt;
9366 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9367 || GET_CODE (x) == PC)
9370 /* We don't want to look into the possible MEM location of a
9371 CONST_DOUBLE, since we're not going to use it, in general. */
9372 if (GET_CODE (x) == CONST_DOUBLE)
9375 if (GET_CODE (x) == UNSPEC
9376 && (XINT (x, 1) == UNSPEC_PIC
9377 || XINT (x, 1) == UNSPEC_GOT
9378 || XINT (x, 1) == UNSPEC_GOTOFF
9379 || XINT (x, 1) == UNSPEC_GOTPLT
9380 || XINT (x, 1) == UNSPEC_GOTTPOFF
9381 || XINT (x, 1) == UNSPEC_DTPOFF
9382 || XINT (x, 1) == UNSPEC_PLT
9383 || XINT (x, 1) == UNSPEC_SYMOFF
9384 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9387 fmt = GET_RTX_FORMAT (GET_CODE (x));
9388 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9394 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9395 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9398 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9405 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9406 @GOTOFF in `reg'. */
9408 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9411 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9414 if (GET_CODE (orig) == LABEL_REF
9415 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9418 reg = gen_reg_rtx (Pmode);
9420 emit_insn (gen_symGOTOFF2reg (reg, orig));
9423 else if (GET_CODE (orig) == SYMBOL_REF)
9426 reg = gen_reg_rtx (Pmode);
9428 emit_insn (gen_symGOT2reg (reg, orig));
9434 /* Try machine-dependent ways of modifying an illegitimate address
9435 to be legitimate. If we find one, return the new, valid address.
9436 Otherwise, return X.
9438 For the SH, if X is almost suitable for indexing, but the offset is
9439 out of range, convert it into a normal form so that CSE has a chance
9440 of reducing the number of address registers used. */
9443 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9446 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9448 if (GET_CODE (x) == PLUS
9449 && (GET_MODE_SIZE (mode) == 4
9450 || GET_MODE_SIZE (mode) == 8)
9451 && CONST_INT_P (XEXP (x, 1))
9452 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9454 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9455 && ! (TARGET_SH2E && mode == SFmode))
9457 rtx index_rtx = XEXP (x, 1);
9458 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9461 /* On rare occasions, we might get an unaligned pointer
9462 that is indexed in a way to give an aligned address.
9463 Therefore, keep the lower two bits in offset_base. */
9464 /* Instead of offset_base 128..131 use 124..127, so that
9465 simple add suffices. */
9467 offset_base = ((offset + 4) & ~60) - 4;
9469 offset_base = offset & ~60;
9471 /* Sometimes the normal form does not suit DImode. We
9472 could avoid that by using smaller ranges, but that
9473 would give less optimized code when SImode is
9475 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9477 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9478 GEN_INT (offset_base), NULL_RTX, 0,
9481 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9488 /* Mark the use of a constant in the literal table. If the constant
9489 has multiple labels, make it unique. */
9491 mark_constant_pool_use (rtx x)
9493 rtx insn, lab, pattern;
9498 switch (GET_CODE (x))
9508 /* Get the first label in the list of labels for the same constant
9509 and delete another labels in the list. */
9511 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9514 || LABEL_REFS (insn) != NEXT_INSN (insn))
9519 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9520 INSN_DELETED_P (insn) = 1;
9522 /* Mark constants in a window. */
9523 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9525 if (!NONJUMP_INSN_P (insn))
9528 pattern = PATTERN (insn);
9529 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9532 switch (XINT (pattern, 1))
9534 case UNSPECV_CONST2:
9535 case UNSPECV_CONST4:
9536 case UNSPECV_CONST8:
9537 XVECEXP (pattern, 0, 1) = const1_rtx;
9539 case UNSPECV_WINDOW_END:
9540 if (XVECEXP (pattern, 0, 0) == x)
9543 case UNSPECV_CONST_END:
9553 /* Return true if it's possible to redirect BRANCH1 to the destination
9554 of an unconditional jump BRANCH2. We only want to do this if the
9555 resulting branch will have a short displacement. */
9557 sh_can_redirect_branch (rtx branch1, rtx branch2)
9559 if (flag_expensive_optimizations && simplejump_p (branch2))
9561 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9565 for (distance = 0, insn = NEXT_INSN (branch1);
9566 insn && distance < 256;
9567 insn = PREV_INSN (insn))
9572 distance += get_attr_length (insn);
9574 for (distance = 0, insn = NEXT_INSN (branch1);
9575 insn && distance < 256;
9576 insn = NEXT_INSN (insn))
9581 distance += get_attr_length (insn);
9587 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9589 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9590 unsigned int new_reg)
9592 /* Interrupt functions can only use registers that have already been
9593 saved by the prologue, even if they would normally be
9596 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9602 /* Function to update the integer COST
9603 based on the relationship between INSN that is dependent on
9604 DEP_INSN through the dependence LINK. The default is to make no
9605 adjustment to COST. This can be used for example to specify to
9606 the scheduler that an output- or anti-dependence does not incur
9607 the same cost as a data-dependence. The return value should be
9608 the new value for COST. */
9610 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9616 /* On SHmedia, if the dependence is an anti-dependence or
9617 output-dependence, there is no cost. */
9618 if (REG_NOTE_KIND (link) != 0)
9620 /* However, dependencies between target register loads and
9621 uses of the register in a subsequent block that are separated
9622 by a conditional branch are not modelled - we have to do with
9623 the anti-dependency between the target register load and the
9624 conditional branch that ends the current block. */
9625 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9626 && GET_CODE (PATTERN (dep_insn)) == SET
9627 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9628 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9629 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9631 int orig_cost = cost;
9632 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9633 rtx target = ((! note
9634 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9635 ? insn : JUMP_LABEL (insn));
9636 /* On the likely path, the branch costs 1, on the unlikely path,
9640 target = next_active_insn (target);
9641 while (target && ! flow_dependent_p (target, dep_insn)
9643 /* If two branches are executed in immediate succession, with the
9644 first branch properly predicted, this causes a stall at the
9645 second branch, hence we won't need the target for the
9646 second branch for two cycles after the launch of the first
9648 if (cost > orig_cost - 2)
9649 cost = orig_cost - 2;
9655 else if (get_attr_is_mac_media (insn)
9656 && get_attr_is_mac_media (dep_insn))
9659 else if (! reload_completed
9660 && GET_CODE (PATTERN (insn)) == SET
9661 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9662 && GET_CODE (PATTERN (dep_insn)) == SET
9663 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9666 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9667 that is needed at the target. */
9668 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9669 && ! flow_dependent_p (insn, dep_insn))
9672 else if (REG_NOTE_KIND (link) == 0)
9674 enum attr_type type;
9677 if (recog_memoized (insn) < 0
9678 || recog_memoized (dep_insn) < 0)
9681 dep_set = single_set (dep_insn);
9683 /* The latency that we specify in the scheduling description refers
9684 to the actual output, not to an auto-increment register; for that,
9685 the latency is one. */
9686 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9688 rtx set = single_set (insn);
9691 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9692 && (!MEM_P (SET_DEST (set))
9693 || !reg_mentioned_p (SET_DEST (dep_set),
9694 XEXP (SET_DEST (set), 0))))
9697 /* The only input for a call that is timing-critical is the
9698 function's address. */
9701 rtx call = PATTERN (insn);
9703 if (GET_CODE (call) == PARALLEL)
9704 call = XVECEXP (call, 0 ,0);
9705 if (GET_CODE (call) == SET)
9706 call = SET_SRC (call);
9707 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9708 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9709 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9710 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9711 cost -= TARGET_SH4_300 ? 3 : 6;
9713 /* Likewise, the most timing critical input for an sfuncs call
9714 is the function address. However, sfuncs typically start
9715 using their arguments pretty quickly.
9716 Assume a four cycle delay for SH4 before they are needed.
9717 Cached ST40-300 calls are quicker, so assume only a one
9719 ??? Maybe we should encode the delays till input registers
9720 are needed by sfuncs into the sfunc call insn. */
9721 /* All sfunc calls are parallels with at least four components.
9722 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9723 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9724 && XVECLEN (PATTERN (insn), 0) >= 4
9725 && (reg = sfunc_uses_reg (insn)))
9727 if (! reg_set_p (reg, dep_insn))
9728 cost -= TARGET_SH4_300 ? 1 : 4;
9730 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9732 enum attr_type dep_type = get_attr_type (dep_insn);
9734 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9736 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9737 && (type = get_attr_type (insn)) != TYPE_CALL
9738 && type != TYPE_SFUNC)
9740 /* When the preceding instruction loads the shift amount of
9741 the following SHAD/SHLD, the latency of the load is increased
9743 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9744 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9745 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9746 XEXP (SET_SRC (single_set (insn)),
9749 /* When an LS group instruction with a latency of less than
9750 3 cycles is followed by a double-precision floating-point
9751 instruction, FIPR, or FTRV, the latency of the first
9752 instruction is increased to 3 cycles. */
9754 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9755 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9757 /* The lsw register of a double-precision computation is ready one
9759 else if (reload_completed
9760 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9761 && (use_pat = single_set (insn))
9762 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9766 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9767 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9770 else if (TARGET_SH4_300)
9772 /* Stores need their input register two cycles later. */
9773 if (dep_set && cost >= 1
9774 && ((type = get_attr_type (insn)) == TYPE_STORE
9775 || type == TYPE_PSTORE
9776 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9778 rtx set = single_set (insn);
9780 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9781 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9784 /* But don't reduce the cost below 1 if the address depends
9785 on a side effect of dep_insn. */
9787 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9793 /* An anti-dependence penalty of two applies if the first insn is a double
9794 precision fadd / fsub / fmul. */
9795 else if (!TARGET_SH4_300
9796 && REG_NOTE_KIND (link) == REG_DEP_ANTI
9797 && recog_memoized (dep_insn) >= 0
9798 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9799 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9800 /* A lot of alleged anti-flow dependences are fake,
9801 so check this one is real. */
9802 && flow_dependent_p (dep_insn, insn))
9808 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9809 if DEP_INSN is anti-flow dependent on INSN. */
9811 flow_dependent_p (rtx insn, rtx dep_insn)
9813 rtx tmp = PATTERN (insn);
9815 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9816 return tmp == NULL_RTX;
9819 /* A helper function for flow_dependent_p called through note_stores. */
9821 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9823 rtx * pinsn = (rtx *) data;
9825 if (*pinsn && reg_referenced_p (x, *pinsn))
9829 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9830 'special function' patterns (type sfunc) that clobber pr, but that
9831 do not look like function calls to leaf_function_p. Hence we must
9832 do this extra check. */
9836 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
9839 /* Return where to allocate pseudo for a given hard register initial
9842 sh_allocate_initial_value (rtx hard_reg)
9846 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
9848 if (current_function_is_leaf
9849 && ! sh_pr_n_sets ()
9850 && ! (TARGET_SHCOMPACT
9851 && ((crtl->args.info.call_cookie
9852 & ~ CALL_COOKIE_RET_TRAMP (1))
9853 || crtl->saves_all_registers)))
9856 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
9864 /* This function returns "2" to indicate dual issue for the SH4
9865 processor. To be used by the DFA pipeline description. */
9867 sh_issue_rate (void)
9869 if (TARGET_SUPERSCALAR)
9875 /* Functions for ready queue reordering for sched1. */
9877 /* Get weight for mode for a set x. */
9879 find_set_regmode_weight (rtx x, enum machine_mode mode)
9881 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9883 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9885 if (REG_P (SET_DEST (x)))
9887 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9897 /* Get regmode weight for insn. */
9899 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
9901 short reg_weight = 0;
9904 /* Increment weight for each register born here. */
9906 reg_weight += find_set_regmode_weight (x, mode);
9907 if (GET_CODE (x) == PARALLEL)
9910 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9912 x = XVECEXP (PATTERN (insn), 0, j);
9913 reg_weight += find_set_regmode_weight (x, mode);
9916 /* Decrement weight for each register that dies here. */
9917 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9919 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9921 rtx note = XEXP (x, 0);
9922 if (REG_P (note) && GET_MODE (note) == mode)
9929 /* Calculate regmode weights for all insns of a basic block. */
9931 find_regmode_weight (basic_block b, enum machine_mode mode)
9933 rtx insn, next_tail, head, tail;
9935 get_ebb_head_tail (b, b, &head, &tail);
9936 next_tail = NEXT_INSN (tail);
9938 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9940 /* Handle register life information. */
9945 INSN_REGMODE_WEIGHT (insn, mode) =
9946 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
9947 else if (mode == SImode)
9948 INSN_REGMODE_WEIGHT (insn, mode) =
9949 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
9953 /* Comparison function for ready queue sorting. */
9955 rank_for_reorder (const void *x, const void *y)
9957 rtx tmp = *(const rtx *) y;
9958 rtx tmp2 = *(const rtx *) x;
9960 /* The insn in a schedule group should be issued the first. */
9961 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9962 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9964 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9965 minimizes instruction movement, thus minimizing sched's effect on
9966 register pressure. */
9967 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9970 /* Resort the array A in which only element at index N may be out of order. */
9972 swap_reorder (rtx *a, int n)
9974 rtx insn = a[n - 1];
9977 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9985 #define SCHED_REORDER(READY, N_READY) \
9988 if ((N_READY) == 2) \
9989 swap_reorder (READY, N_READY); \
9990 else if ((N_READY) > 2) \
9991 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
9995 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
9998 ready_reorder (rtx *ready, int nready)
10000 SCHED_REORDER (ready, nready);
10003 /* Count life regions of r0 for a block. */
10005 find_r0_life_regions (basic_block b)
10014 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10025 insn = BB_HEAD (b);
10027 r0_reg = gen_rtx_REG (SImode, R0_REG);
10032 if (find_regno_note (insn, REG_DEAD, R0_REG))
10038 && (pset = single_set (insn))
10039 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10040 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10048 insn = NEXT_INSN (insn);
10050 return set - death;
10053 /* Calculate regmode weights for all insns of all basic block. */
10055 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10056 int verbose ATTRIBUTE_UNUSED,
10061 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10062 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10063 r0_life_regions = 0;
10065 FOR_EACH_BB_REVERSE (b)
10067 find_regmode_weight (b, SImode);
10068 find_regmode_weight (b, SFmode);
10069 if (!reload_completed)
10070 r0_life_regions += find_r0_life_regions (b);
10073 CURR_REGMODE_PRESSURE (SImode) = 0;
10074 CURR_REGMODE_PRESSURE (SFmode) = 0;
10080 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10081 int verbose ATTRIBUTE_UNUSED)
10083 if (regmode_weight[0])
10085 free (regmode_weight[0]);
10086 regmode_weight[0] = NULL;
10088 if (regmode_weight[1])
10090 free (regmode_weight[1]);
10091 regmode_weight[1] = NULL;
10095 /* The scalar modes supported differs from the default version in TImode
10096 for 32-bit SHMEDIA. */
10098 sh_scalar_mode_supported_p (enum machine_mode mode)
10100 if (TARGET_SHMEDIA32 && mode == TImode)
10103 return default_scalar_mode_supported_p (mode);
10106 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10107 keep count of register pressures on SImode and SFmode. */
10109 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10110 int sched_verbose ATTRIBUTE_UNUSED,
10112 int can_issue_more)
10114 if (GET_CODE (PATTERN (insn)) != USE
10115 && GET_CODE (PATTERN (insn)) != CLOBBER)
10116 cached_can_issue_more = can_issue_more - 1;
10118 cached_can_issue_more = can_issue_more;
10120 if (reload_completed)
10121 return cached_can_issue_more;
10123 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10124 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10126 return cached_can_issue_more;
10130 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10131 int verbose ATTRIBUTE_UNUSED,
10132 int veclen ATTRIBUTE_UNUSED)
10134 CURR_REGMODE_PRESSURE (SImode) = 0;
10135 CURR_REGMODE_PRESSURE (SFmode) = 0;
10138 /* Some magic numbers. */
10139 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10140 functions that already have high pressure on r0. */
10141 #define R0_MAX_LIFE_REGIONS 2
10142 /* Register Pressure thresholds for SImode and SFmode registers. */
10143 #define SIMODE_MAX_WEIGHT 5
10144 #define SFMODE_MAX_WEIGHT 10
10146 /* Return true if the pressure is high for MODE. */
10148 high_pressure (enum machine_mode mode)
10150 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10151 functions that already have high pressure on r0. */
10152 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10155 if (mode == SFmode)
10156 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10158 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10161 /* Reorder ready queue if register pressure is high. */
10163 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10164 int sched_verbose ATTRIBUTE_UNUSED,
10167 int clock_var ATTRIBUTE_UNUSED)
10169 if (reload_completed)
10170 return sh_issue_rate ();
10172 if (high_pressure (SFmode) || high_pressure (SImode))
10174 ready_reorder (ready, *n_readyp);
10177 return sh_issue_rate ();
10180 /* Skip cycles if the current register pressure is high. */
10182 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10183 int sched_verbose ATTRIBUTE_UNUSED,
10184 rtx *ready ATTRIBUTE_UNUSED,
10185 int *n_readyp ATTRIBUTE_UNUSED,
10186 int clock_var ATTRIBUTE_UNUSED)
10188 if (reload_completed)
10189 return cached_can_issue_more;
10191 if (high_pressure(SFmode) || high_pressure (SImode))
10194 return cached_can_issue_more;
10197 /* Skip cycles without sorting the ready queue. This will move insn from
10198 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10199 queue by sh_reorder. */
10201 /* Generally, skipping these many cycles are sufficient for all insns to move
10203 #define MAX_SKIPS 8
10206 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10207 int sched_verbose ATTRIBUTE_UNUSED,
10208 rtx insn ATTRIBUTE_UNUSED,
10209 int last_clock_var,
10213 if (reload_completed)
10218 if ((clock_var - last_clock_var) < MAX_SKIPS)
10223 /* If this is the last cycle we are skipping, allow reordering of R. */
10224 if ((clock_var - last_clock_var) == MAX_SKIPS)
10236 /* SHmedia requires registers for branches, so we can't generate new
10237 branches past reload. */
10239 sh_cannot_modify_jumps_p (void)
10241 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10244 static enum reg_class
10245 sh_target_reg_class (void)
10247 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10251 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10253 HARD_REG_SET dummy;
10258 if (! shmedia_space_reserved_for_target_registers)
10260 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10262 if (calc_live_regs (&dummy) >= 6 * 8)
10268 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10270 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10274 On the SH1..SH4, the trampoline looks like
10275 2 0002 D202 mov.l l2,r2
10276 1 0000 D301 mov.l l1,r3
10277 3 0004 422B jmp @r2
10279 5 0008 00000000 l1: .long area
10280 6 000c 00000000 l2: .long function
10282 SH5 (compact) uses r1 instead of r3 for the static chain. */
10285 /* Emit RTL insns to initialize the variable parts of a trampoline.
10286 FNADDR is an RTX for the address of the function's pure code.
10287 CXT is an RTX for the static chain value for the function. */
10290 sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
10292 rtx tramp_mem = gen_frame_mem (BLKmode, tramp);
10294 if (TARGET_SHMEDIA64)
10299 rtx movi1 = GEN_INT (0xcc000010);
10300 rtx shori1 = GEN_INT (0xc8000010);
10303 /* The following trampoline works within a +- 128 KB range for cxt:
10304 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10305 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10306 gettr tr1,r1; blink tr0,r63 */
10307 /* Address rounding makes it hard to compute the exact bounds of the
10308 offset for this trampoline, but we have a rather generous offset
10309 range, so frame_offset should do fine as an upper bound. */
10310 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10312 /* ??? could optimize this trampoline initialization
10313 by writing DImode words with two insns each. */
10314 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10315 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10316 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10317 insn = gen_rtx_AND (DImode, insn, mask);
10318 /* Or in ptb/u .,tr1 pattern */
10319 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10320 insn = force_operand (insn, NULL_RTX);
10321 insn = gen_lowpart (SImode, insn);
10322 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10323 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10324 insn = gen_rtx_AND (DImode, insn, mask);
10325 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10326 insn = gen_lowpart (SImode, insn);
10327 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10328 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10329 insn = gen_rtx_AND (DImode, insn, mask);
10330 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10331 insn = gen_lowpart (SImode, insn);
10332 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10333 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10334 insn = gen_rtx_AND (DImode, insn, mask);
10335 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10336 insn = gen_lowpart (SImode, insn);
10337 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10338 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10339 insn = gen_rtx_AND (DImode, insn, mask);
10340 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10341 insn = gen_lowpart (SImode, insn);
10342 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10343 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10344 GEN_INT (0x6bf10600));
10345 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10346 GEN_INT (0x4415fc10));
10347 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10348 GEN_INT (0x4401fff0));
10349 emit_insn (gen_ic_invalidate_line (tramp));
10352 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10353 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10355 tramp_templ = gen_datalabel_ref (tramp_templ);
10357 src = gen_const_mem (BLKmode, tramp_templ);
10358 set_mem_align (dst, 256);
10359 set_mem_align (src, 64);
10360 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10362 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10363 emit_move_insn (adjust_address (tramp_mem, Pmode,
10364 fixed_len + GET_MODE_SIZE (Pmode)),
10366 emit_insn (gen_ic_invalidate_line (tramp));
10369 else if (TARGET_SHMEDIA)
10371 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10372 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10373 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10374 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10375 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10376 rotated 10 right, and higher 16 bit of every 32 selected. */
10378 = force_reg (V2HImode, (simplify_gen_subreg
10379 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10380 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10381 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10383 tramp = force_reg (Pmode, tramp);
10384 fnaddr = force_reg (SImode, fnaddr);
10385 cxt = force_reg (SImode, cxt);
10386 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10387 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10389 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10390 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10391 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10392 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10393 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10394 gen_rtx_SUBREG (V2HImode, cxt, 0),
10396 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10397 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10398 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10399 if (TARGET_LITTLE_ENDIAN)
10401 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10402 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10406 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10407 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10409 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10410 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10411 emit_insn (gen_ic_invalidate_line (tramp));
10414 else if (TARGET_SHCOMPACT)
10416 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10419 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10420 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10422 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10423 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10425 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10426 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10427 if (TARGET_HARVARD)
10429 if (!TARGET_INLINE_IC_INVALIDATE
10430 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10431 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10432 FUNCTION_ORDINARY),
10433 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10435 emit_insn (gen_ic_invalidate_line (tramp));
10439 /* FIXME: This is overly conservative. A SHcompact function that
10440 receives arguments ``by reference'' will have them stored in its
10441 own stack frame, so it must not pass pointers or references to
10442 these arguments to other functions by means of sibling calls. */
10443 /* If PIC, we cannot make sibling calls to global functions
10444 because the PLT requires r12 to be live. */
10446 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10449 && (! TARGET_SHCOMPACT
10450 || crtl->args.info.stack_regs == 0)
10451 && ! sh_cfun_interrupt_handler_p ()
10453 || (decl && ! TREE_PUBLIC (decl))
10454 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10457 /* Machine specific built-in functions. */
10459 struct builtin_description
10461 const enum insn_code icode;
10462 const char *const name;
10466 /* describe number and signedness of arguments; arg[0] == result
10467 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10468 /* 9: 64-bit pointer, 10: 32-bit pointer */
10469 static const char signature_args[][4] =
10471 #define SH_BLTIN_V2SI2 0
10473 #define SH_BLTIN_V4HI2 1
10475 #define SH_BLTIN_V2SI3 2
10477 #define SH_BLTIN_V4HI3 3
10479 #define SH_BLTIN_V8QI3 4
10481 #define SH_BLTIN_MAC_HISI 5
10483 #define SH_BLTIN_SH_HI 6
10485 #define SH_BLTIN_SH_SI 7
10487 #define SH_BLTIN_V4HI2V2SI 8
10489 #define SH_BLTIN_V4HI2V8QI 9
10491 #define SH_BLTIN_SISF 10
10493 #define SH_BLTIN_LDUA_L 11
10495 #define SH_BLTIN_LDUA_Q 12
10497 #define SH_BLTIN_STUA_L 13
10499 #define SH_BLTIN_STUA_Q 14
10501 #define SH_BLTIN_LDUA_L64 15
10503 #define SH_BLTIN_LDUA_Q64 16
10505 #define SH_BLTIN_STUA_L64 17
10507 #define SH_BLTIN_STUA_Q64 18
10509 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10510 #define SH_BLTIN_2 19
10511 #define SH_BLTIN_SU 19
10513 #define SH_BLTIN_3 20
10514 #define SH_BLTIN_SUS 20
10516 #define SH_BLTIN_PSSV 21
10518 #define SH_BLTIN_XXUU 22
10519 #define SH_BLTIN_UUUU 22
10521 #define SH_BLTIN_PV 23
10524 /* mcmv: operands considered unsigned. */
10525 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10526 /* mperm: control value considered unsigned int. */
10527 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10528 /* mshards_q: returns signed short. */
10529 /* nsb: takes long long arg, returns unsigned char. */
10530 static const struct builtin_description bdesc[] =
10532 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
10533 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
10534 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
10535 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
10536 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
10537 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
10538 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
10539 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
10540 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
10541 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
10542 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
10543 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
10544 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
10545 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
10546 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
10547 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
10548 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
10549 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
10550 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3 },
10551 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3 },
10552 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3 },
10553 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3 },
10554 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3 },
10555 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3 },
10556 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3 },
10557 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
10558 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
10559 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
10560 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
10561 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
10562 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
10563 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
10564 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
10565 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
10566 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
10567 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
10568 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
10569 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
10570 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
10571 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
10572 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
10573 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
10574 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
10575 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
10576 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
10577 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
10578 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
10579 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
10580 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
10581 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
10582 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
10583 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
10584 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
10585 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
10586 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
10587 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
10588 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
10589 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
10590 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
10591 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
10592 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
10593 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3 },
10594 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2 },
10595 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2 },
10596 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
10597 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
10598 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
10599 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
10600 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
10601 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
10602 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
10603 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
10604 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
10605 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64 },
10606 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64 },
10607 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64 },
10608 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64 },
10609 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64 },
10610 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64 },
10611 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64 },
10612 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64 },
10613 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
10614 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
10615 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
10619 sh_media_init_builtins (void)
10621 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10622 const struct builtin_description *d;
10624 memset (shared, 0, sizeof shared);
10625 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10627 tree type, arg_type = 0;
10628 int signature = d->signature;
10631 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10632 type = shared[signature];
10635 int has_result = signature_args[signature][0] != 0;
10637 if ((signature_args[signature][1] & 8)
10638 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10639 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10641 if (! TARGET_FPU_ANY
10642 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10644 type = void_list_node;
10647 int arg = signature_args[signature][i];
10648 int opno = i - 1 + has_result;
10651 arg_type = ptr_type_node;
10653 arg_type = (*lang_hooks.types.type_for_mode)
10654 (insn_data[d->icode].operand[opno].mode,
10659 arg_type = void_type_node;
10662 type = tree_cons (NULL_TREE, arg_type, type);
10664 type = build_function_type (arg_type, type);
10665 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10666 shared[signature] = type;
10668 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10673 /* Implements target hook vector_mode_supported_p. */
10675 sh_vector_mode_supported_p (enum machine_mode mode)
10678 && ((mode == V2SFmode)
10679 || (mode == V4SFmode)
10680 || (mode == V16SFmode)))
10683 else if (TARGET_SHMEDIA
10684 && ((mode == V8QImode)
10685 || (mode == V2HImode)
10686 || (mode == V4HImode)
10687 || (mode == V2SImode)))
10693 /* Implements target hook dwarf_calling_convention. Return an enum
10694 of dwarf_calling_convention. */
10696 sh_dwarf_calling_convention (const_tree func)
10698 if (sh_attr_renesas_p (func))
10699 return DW_CC_GNU_renesas_sh;
10701 return DW_CC_normal;
10705 sh_init_builtins (void)
10707 if (TARGET_SHMEDIA)
10708 sh_media_init_builtins ();
10711 /* Expand an expression EXP that calls a built-in function,
10712 with result going to TARGET if that's convenient
10713 (and in mode MODE if that's convenient).
10714 SUBTARGET may be used as the target for computing one of EXP's operands.
10715 IGNORE is nonzero if the value is to be ignored. */
10718 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10719 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10721 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10722 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10723 const struct builtin_description *d = &bdesc[fcode];
10724 enum insn_code icode = d->icode;
10725 int signature = d->signature;
10726 enum machine_mode tmode = VOIDmode;
10731 if (signature_args[signature][0])
10736 tmode = insn_data[icode].operand[0].mode;
10738 || GET_MODE (target) != tmode
10739 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10740 target = gen_reg_rtx (tmode);
10741 op[nop++] = target;
10746 for (i = 1; i <= 3; i++, nop++)
10749 enum machine_mode opmode, argmode;
10752 if (! signature_args[signature][i])
10754 arg = CALL_EXPR_ARG (exp, i - 1);
10755 if (arg == error_mark_node)
10757 if (signature_args[signature][i] & 8)
10760 optype = ptr_type_node;
10764 opmode = insn_data[icode].operand[nop].mode;
10765 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10767 argmode = TYPE_MODE (TREE_TYPE (arg));
10768 if (argmode != opmode)
10769 arg = build1 (NOP_EXPR, optype, arg);
10770 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10771 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10772 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10778 pat = (*insn_data[d->icode].genfun) (op[0]);
10781 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10784 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10787 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10790 gcc_unreachable ();
10799 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
10801 rtx sel0 = const0_rtx;
10802 rtx sel1 = const1_rtx;
10803 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
10804 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
10806 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
10807 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
10811 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
10813 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
10815 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
10816 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
10819 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
10820 We can allow any mode in any general register. The special registers
10821 only allow SImode. Don't allow any mode in the PR.
10823 We cannot hold DCmode values in the XD registers because alter_reg
10824 handles subregs of them incorrectly. We could work around this by
10825 spacing the XD registers like the DR registers, but this would require
10826 additional memory in every compilation to hold larger register vectors.
10827 We could hold SFmode / SCmode values in XD registers, but that
10828 would require a tertiary reload when reloading from / to memory,
10829 and a secondary reload to reload from / to general regs; that
10830 seems to be a loosing proposition.
10832 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10833 it won't be ferried through GP registers first. */
10836 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10838 if (SPECIAL_REGISTER_P (regno))
10839 return mode == SImode;
10841 if (regno == FPUL_REG)
10842 return (mode == SImode || mode == SFmode);
10844 if (FP_REGISTER_P (regno) && mode == SFmode)
10847 if (mode == V2SFmode)
10849 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10850 || GENERAL_REGISTER_P (regno)))
10856 if (mode == V4SFmode)
10858 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10859 || GENERAL_REGISTER_P (regno))
10865 if (mode == V16SFmode)
10867 if (TARGET_SHMEDIA)
10869 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
10875 return regno == FIRST_XD_REG;
10878 if (FP_REGISTER_P (regno))
10882 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
10883 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
10886 && (mode == DFmode || mode == DImode
10887 || mode == V2SFmode || mode == TImode)))
10888 && ((regno - FIRST_FP_REG) & 1) == 0)
10889 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
10890 && ((regno - FIRST_FP_REG) & 3) == 0))
10896 if (XD_REGISTER_P (regno))
10897 return mode == DFmode;
10899 if (TARGET_REGISTER_P (regno))
10900 return (mode == DImode || mode == SImode || mode == PDImode);
10902 if (regno == PR_REG)
10903 return mode == SImode;
10905 if (regno == FPSCR_REG)
10906 return mode == PSImode;
10908 /* FIXME. This works around PR target/37633 for -O0. */
10909 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
10911 unsigned int n = GET_MODE_SIZE (mode) / 8;
10913 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
10914 && regno <= FIRST_GENERAL_REG + 14)
10921 /* Return the class of registers for which a mode change from FROM to TO
10924 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
10925 enum reg_class rclass)
10927 /* We want to enable the use of SUBREGs as a means to
10928 VEC_SELECT a single element of a vector. */
10929 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10930 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
10932 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10934 if (TARGET_LITTLE_ENDIAN)
10936 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10937 return reg_classes_intersect_p (DF_REGS, rclass);
10941 if (GET_MODE_SIZE (from) < 8)
10942 return reg_classes_intersect_p (DF_HI_REGS, rclass);
10949 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10950 that label is used. */
10953 sh_mark_label (rtx address, int nuses)
10955 if (GOTOFF_P (address))
10957 /* Extract the label or symbol. */
10958 address = XEXP (address, 0);
10959 if (GET_CODE (address) == PLUS)
10960 address = XEXP (address, 0);
10961 address = XVECEXP (address, 0, 0);
10963 if (GET_CODE (address) == LABEL_REF
10964 && LABEL_P (XEXP (address, 0)))
10965 LABEL_NUSES (XEXP (address, 0)) += nuses;
10968 /* Compute extra cost of moving data between one register class
10971 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10972 uses this information. Hence, the general register <-> floating point
10973 register information here is not used for SFmode. */
10976 sh_register_move_cost (enum machine_mode mode,
10977 enum reg_class srcclass, enum reg_class dstclass)
10979 if (dstclass == T_REGS || dstclass == PR_REGS)
10982 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10985 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
10986 && REGCLASS_HAS_FP_REG (srcclass)
10987 && REGCLASS_HAS_FP_REG (dstclass))
10990 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10991 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10993 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10994 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10997 if ((REGCLASS_HAS_FP_REG (dstclass)
10998 && REGCLASS_HAS_GENERAL_REG (srcclass))
10999 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11000 && REGCLASS_HAS_FP_REG (srcclass)))
11001 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11002 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11004 if ((dstclass == FPUL_REGS
11005 && REGCLASS_HAS_GENERAL_REG (srcclass))
11006 || (srcclass == FPUL_REGS
11007 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11010 if ((dstclass == FPUL_REGS
11011 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11012 || (srcclass == FPUL_REGS
11013 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11016 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11017 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11020 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11022 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11024 if (sh_gettrcost >= 0)
11025 return sh_gettrcost;
11026 else if (!TARGET_PT_FIXED)
11030 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11031 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11036 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11037 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11038 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11040 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11043 static rtx emit_load_ptr (rtx, rtx);
11046 emit_load_ptr (rtx reg, rtx addr)
11048 rtx mem = gen_const_mem (ptr_mode, addr);
11050 if (Pmode != ptr_mode)
11051 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11052 return emit_move_insn (reg, mem);
11056 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11057 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11060 CUMULATIVE_ARGS cum;
11061 int structure_value_byref = 0;
11062 rtx this_rtx, this_value, sibcall, insns, funexp;
11063 tree funtype = TREE_TYPE (function);
11064 int simple_add = CONST_OK_FOR_ADD (delta);
11066 rtx scratch0, scratch1, scratch2;
11069 reload_completed = 1;
11070 epilogue_completed = 1;
11071 current_function_uses_only_leaf_regs = 1;
11073 emit_note (NOTE_INSN_PROLOGUE_END);
11075 /* Find the "this" pointer. We have such a wide range of ABIs for the
11076 SH that it's best to do this completely machine independently.
11077 "this" is passed as first argument, unless a structure return pointer
11078 comes first, in which case "this" comes second. */
11079 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11080 #ifndef PCC_STATIC_STRUCT_RETURN
11081 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11082 structure_value_byref = 1;
11083 #endif /* not PCC_STATIC_STRUCT_RETURN */
11084 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11086 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11088 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11090 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11092 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11093 static chain pointer (even if you can't have nested virtual functions
11094 right now, someone might implement them sometime), and the rest of the
11095 registers are used for argument passing, are callee-saved, or reserved. */
11096 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11097 -ffixed-reg has been used. */
11098 if (! call_used_regs[0] || fixed_regs[0])
11099 error ("r0 needs to be available as a call-clobbered register");
11100 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11103 if (call_used_regs[1] && ! fixed_regs[1])
11104 scratch1 = gen_rtx_REG (ptr_mode, 1);
11105 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11106 pointing where to return struct values. */
11107 if (call_used_regs[3] && ! fixed_regs[3])
11108 scratch2 = gen_rtx_REG (Pmode, 3);
11110 else if (TARGET_SHMEDIA)
11112 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11113 if (i != REGNO (scratch0) &&
11114 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11116 scratch1 = gen_rtx_REG (ptr_mode, i);
11119 if (scratch1 == scratch0)
11120 error ("Need a second call-clobbered general purpose register");
11121 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11122 if (call_used_regs[i] && ! fixed_regs[i])
11124 scratch2 = gen_rtx_REG (Pmode, i);
11127 if (scratch2 == scratch0)
11128 error ("Need a call-clobbered target register");
11131 this_value = plus_constant (this_rtx, delta);
11133 && (simple_add || scratch0 != scratch1)
11134 && strict_memory_address_p (ptr_mode, this_value))
11136 emit_load_ptr (scratch0, this_value);
11141 ; /* Do nothing. */
11142 else if (simple_add)
11143 emit_move_insn (this_rtx, this_value);
11146 emit_move_insn (scratch1, GEN_INT (delta));
11147 emit_insn (gen_add2_insn (this_rtx, scratch1));
11155 emit_load_ptr (scratch0, this_rtx);
11157 offset_addr = plus_constant (scratch0, vcall_offset);
11158 if (strict_memory_address_p (ptr_mode, offset_addr))
11159 ; /* Do nothing. */
11160 else if (! TARGET_SH5 && scratch0 != scratch1)
11162 /* scratch0 != scratch1, and we have indexed loads. Get better
11163 schedule by loading the offset into r1 and using an indexed
11164 load - then the load of r1 can issue before the load from
11165 (this_rtx + delta) finishes. */
11166 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11167 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11169 else if (CONST_OK_FOR_ADD (vcall_offset))
11171 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11172 offset_addr = scratch0;
11174 else if (scratch0 != scratch1)
11176 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11177 emit_insn (gen_add2_insn (scratch0, scratch1));
11178 offset_addr = scratch0;
11181 gcc_unreachable (); /* FIXME */
11182 emit_load_ptr (scratch0, offset_addr);
11184 if (Pmode != ptr_mode)
11185 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11186 emit_insn (gen_add2_insn (this_rtx, scratch0));
11189 /* Generate a tail call to the target function. */
11190 if (! TREE_USED (function))
11192 assemble_external (function);
11193 TREE_USED (function) = 1;
11195 funexp = XEXP (DECL_RTL (function), 0);
11196 /* If the function is overridden, so is the thunk, hence we don't
11197 need GOT addressing even if this is a public symbol. */
11199 if (TARGET_SH1 && ! flag_weak)
11200 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11203 if (TARGET_SH2 && flag_pic)
11205 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11206 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11210 if (TARGET_SHMEDIA && flag_pic)
11212 funexp = gen_sym2PIC (funexp);
11213 PUT_MODE (funexp, Pmode);
11215 emit_move_insn (scratch2, funexp);
11216 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11217 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11219 sibcall = emit_call_insn (sibcall);
11220 SIBLING_CALL_P (sibcall) = 1;
11221 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11224 /* Run just enough of rest_of_compilation to do scheduling and get
11225 the insns emitted. Note that use_thunk calls
11226 assemble_start_function and assemble_end_function. */
11228 insn_locators_alloc ();
11229 insns = get_insns ();
11235 split_all_insns_noflow ();
11240 if (optimize > 0 && flag_delayed_branch)
11241 dbr_schedule (insns);
11243 shorten_branches (insns);
11244 final_start_function (insns, file, 1);
11245 final (insns, file, 1);
11246 final_end_function ();
11247 free_after_compilation (cfun);
11249 reload_completed = 0;
11250 epilogue_completed = 0;
11254 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11258 /* If this is not an ordinary function, the name usually comes from a
11259 string literal or an sprintf buffer. Make sure we use the same
11260 string consistently, so that cse will be able to unify address loads. */
11261 if (kind != FUNCTION_ORDINARY)
11262 name = IDENTIFIER_POINTER (get_identifier (name));
11263 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11264 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11268 case FUNCTION_ORDINARY:
11272 rtx reg = target ? target : gen_reg_rtx (Pmode);
11274 emit_insn (gen_symGOT2reg (reg, sym));
11280 /* ??? To allow cse to work, we use GOTOFF relocations.
11281 we could add combiner patterns to transform this into
11282 straight pc-relative calls with sym2PIC / bsrf when
11283 label load and function call are still 1:1 and in the
11284 same basic block during combine. */
11285 rtx reg = target ? target : gen_reg_rtx (Pmode);
11287 emit_insn (gen_symGOTOFF2reg (reg, sym));
11292 if (target && sym != target)
11294 emit_move_insn (target, sym);
11300 /* Find the number of a general purpose register in S. */
11302 scavenge_reg (HARD_REG_SET *s)
11305 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11306 if (TEST_HARD_REG_BIT (*s, r))
11312 sh_get_pr_initial_val (void)
11316 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11317 PR register on SHcompact, because it might be clobbered by the prologue.
11318 We check first if that is known to be the case. */
11319 if (TARGET_SHCOMPACT
11320 && ((crtl->args.info.call_cookie
11321 & ~ CALL_COOKIE_RET_TRAMP (1))
11322 || crtl->saves_all_registers))
11323 return gen_frame_mem (SImode, return_address_pointer_rtx);
11325 /* If we haven't finished rtl generation, there might be a nonlocal label
11326 that we haven't seen yet.
11327 ??? get_hard_reg_initial_val fails if it is called after register
11328 allocation has started, unless it has been called before for the
11329 same register. And even then, we end in trouble if we didn't use
11330 the register in the same basic block before. So call
11331 get_hard_reg_initial_val now and wrap it in an unspec if we might
11332 need to replace it. */
11333 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11334 combine can put the pseudo returned by get_hard_reg_initial_val into
11335 instructions that need a general purpose registers, which will fail to
11336 be recognized when the pseudo becomes allocated to PR. */
11338 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11340 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11345 sh_expand_t_scc (rtx operands[])
11347 enum rtx_code code = GET_CODE (operands[1]);
11348 rtx target = operands[0];
11349 rtx op0 = operands[2];
11350 rtx op1 = operands[3];
11351 rtx result = target;
11354 if (!REG_P (op0) || REGNO (op0) != T_REG
11355 || !CONST_INT_P (op1))
11357 if (!REG_P (result))
11358 result = gen_reg_rtx (SImode);
11359 val = INTVAL (op1);
11360 if ((code == EQ && val == 1) || (code == NE && val == 0))
11361 emit_insn (gen_movt (result));
11362 else if (TARGET_SH2A && ((code == EQ && val == 0)
11363 || (code == NE && val == 1)))
11364 emit_insn (gen_xorsi3_movrt (result));
11365 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11367 emit_clobber (result);
11368 emit_insn (gen_subc (result, result, result));
11369 emit_insn (gen_addsi3 (result, result, const1_rtx));
11371 else if (code == EQ || code == NE)
11372 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11375 if (result != target)
11376 emit_move_insn (target, result);
11380 /* INSN is an sfunc; return the rtx that describes the address used. */
11382 extract_sfunc_addr (rtx insn)
11384 rtx pattern, part = NULL_RTX;
11387 pattern = PATTERN (insn);
11388 len = XVECLEN (pattern, 0);
11389 for (i = 0; i < len; i++)
11391 part = XVECEXP (pattern, 0, i);
11392 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11393 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11394 return XEXP (part, 0);
11396 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11397 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11400 /* Verify that the register in use_sfunc_addr still agrees with the address
11401 used in the sfunc. This prevents fill_slots_from_thread from changing
11403 INSN is the use_sfunc_addr instruction, and REG is the register it
11406 check_use_sfunc_addr (rtx insn, rtx reg)
11408 /* Search for the sfunc. It should really come right after INSN. */
11409 while ((insn = NEXT_INSN (insn)))
11411 if (LABEL_P (insn) || JUMP_P (insn))
11413 if (! INSN_P (insn))
11416 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11417 insn = XVECEXP (PATTERN (insn), 0, 0);
11418 if (GET_CODE (PATTERN (insn)) != PARALLEL
11419 || get_attr_type (insn) != TYPE_SFUNC)
11421 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11423 gcc_unreachable ();
11426 /* This function returns a constant rtx that represents pi / 2**15 in
11427 SFmode. it's used to scale SFmode angles, in radians, to a
11428 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11429 maps to 0x10000). */
11431 static GTY(()) rtx sh_fsca_sf2int_rtx;
11434 sh_fsca_sf2int (void)
11436 if (! sh_fsca_sf2int_rtx)
11438 REAL_VALUE_TYPE rv;
11440 real_from_string (&rv, "10430.378350470453");
11441 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11444 return sh_fsca_sf2int_rtx;
11447 /* This function returns a constant rtx that represents pi / 2**15 in
11448 DFmode. it's used to scale DFmode angles, in radians, to a
11449 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11450 maps to 0x10000). */
11452 static GTY(()) rtx sh_fsca_df2int_rtx;
11455 sh_fsca_df2int (void)
11457 if (! sh_fsca_df2int_rtx)
11459 REAL_VALUE_TYPE rv;
11461 real_from_string (&rv, "10430.378350470453");
11462 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11465 return sh_fsca_df2int_rtx;
11468 /* This function returns a constant rtx that represents 2**15 / pi in
11469 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11470 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11473 static GTY(()) rtx sh_fsca_int2sf_rtx;
11476 sh_fsca_int2sf (void)
11478 if (! sh_fsca_int2sf_rtx)
11480 REAL_VALUE_TYPE rv;
11482 real_from_string (&rv, "9.587379924285257e-5");
11483 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11486 return sh_fsca_int2sf_rtx;
11489 /* Initialize the CUMULATIVE_ARGS structure. */
11492 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11494 rtx libname ATTRIBUTE_UNUSED,
11496 signed int n_named_args,
11497 enum machine_mode mode)
11499 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11500 pcum->free_single_fp_reg = 0;
11501 pcum->stack_regs = 0;
11502 pcum->byref_regs = 0;
11504 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11506 /* XXX - Should we check TARGET_HITACHI here ??? */
11507 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11511 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11512 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11513 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11514 pcum->arg_count [(int) SH_ARG_INT]
11515 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11518 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11519 && pcum->arg_count [(int) SH_ARG_INT] == 0
11520 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11521 ? int_size_in_bytes (TREE_TYPE (fntype))
11522 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11523 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11524 == FIRST_RET_REG));
11528 pcum->arg_count [(int) SH_ARG_INT] = 0;
11529 pcum->prototype_p = FALSE;
11530 if (mode != VOIDmode)
11532 pcum->call_cookie =
11533 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11534 && GET_MODE_SIZE (mode) > 4
11535 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11537 /* If the default ABI is the Renesas ABI then all library
11538 calls must assume that the library will be using the
11539 Renesas ABI. So if the function would return its result
11540 in memory then we must force the address of this memory
11541 block onto the stack. Ideally we would like to call
11542 targetm.calls.return_in_memory() here but we do not have
11543 the TYPE or the FNDECL available so we synthesize the
11544 contents of that function as best we can. */
11546 (TARGET_DEFAULT & MASK_HITACHI)
11547 && (mode == BLKmode
11548 || (GET_MODE_SIZE (mode) > 4
11549 && !(mode == DFmode
11550 && TARGET_FPU_DOUBLE)));
11554 pcum->call_cookie = 0;
11555 pcum->force_mem = FALSE;
11560 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11561 not enter into CONST_DOUBLE for the replace.
11563 Note that copying is not done so X must not be shared unless all copies
11564 are to be modified.
11566 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11567 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11568 replacements[n*2+1] - and that we take mode changes into account.
11570 If a replacement is ambiguous, return NULL_RTX.
11572 If MODIFY is zero, don't modify any rtl in place,
11573 just return zero or nonzero for failure / success. */
11576 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11581 /* The following prevents loops occurrence when we change MEM in
11582 CONST_DOUBLE onto the same CONST_DOUBLE. */
11583 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11586 for (i = n_replacements - 1; i >= 0 ; i--)
11587 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11588 return replacements[i*2+1];
11590 /* Allow this function to make replacements in EXPR_LISTs. */
11594 if (GET_CODE (x) == SUBREG)
11596 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11597 n_replacements, modify);
11599 if (CONST_INT_P (new_rtx))
11601 x = simplify_subreg (GET_MODE (x), new_rtx,
11602 GET_MODE (SUBREG_REG (x)),
11608 SUBREG_REG (x) = new_rtx;
11612 else if (REG_P (x))
11614 unsigned regno = REGNO (x);
11615 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11616 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11617 rtx result = NULL_RTX;
11619 for (i = n_replacements - 1; i >= 0; i--)
11621 rtx from = replacements[i*2];
11622 rtx to = replacements[i*2+1];
11623 unsigned from_regno, from_nregs, to_regno, new_regno;
11627 from_regno = REGNO (from);
11628 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11629 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11630 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11632 if (regno < from_regno
11633 || regno + nregs > from_regno + nregs
11637 to_regno = REGNO (to);
11638 if (to_regno < FIRST_PSEUDO_REGISTER)
11640 new_regno = regno + to_regno - from_regno;
11641 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11644 result = gen_rtx_REG (GET_MODE (x), new_regno);
11646 else if (GET_MODE (x) <= GET_MODE (to))
11647 result = gen_lowpart_common (GET_MODE (x), to);
11649 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11652 return result ? result : x;
11654 else if (GET_CODE (x) == ZERO_EXTEND)
11656 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11657 n_replacements, modify);
11659 if (CONST_INT_P (new_rtx))
11661 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11662 new_rtx, GET_MODE (XEXP (x, 0)));
11667 XEXP (x, 0) = new_rtx;
11672 fmt = GET_RTX_FORMAT (GET_CODE (x));
11673 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11679 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11680 n_replacements, modify);
11684 XEXP (x, i) = new_rtx;
11686 else if (fmt[i] == 'E')
11687 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11689 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
11690 n_replacements, modify);
11694 XVECEXP (x, i, j) = new_rtx;
11702 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
11704 enum rtx_code code = TRUNCATE;
11706 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11708 rtx inner = XEXP (x, 0);
11709 enum machine_mode inner_mode = GET_MODE (inner);
11711 if (inner_mode == mode)
11713 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11715 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11716 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11718 code = GET_CODE (x);
11722 return gen_rtx_fmt_e (code, mode, x);
11725 /* called via for_each_rtx after reload, to clean up truncates of
11726 registers that span multiple actual hard registers. */
11728 shmedia_cleanup_truncate (rtx *p, void *n_changes)
11732 if (GET_CODE (x) != TRUNCATE)
11735 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
11737 enum machine_mode reg_mode = GET_MODE (reg);
11738 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
11739 subreg_lowpart_offset (DImode, reg_mode));
11740 *(int*) n_changes += 1;
11746 /* Load and store depend on the highpart of the address. However,
11747 set_attr_alternative does not give well-defined results before reload,
11748 so we must look at the rtl ourselves to see if any of the feeding
11749 registers is used in a memref. */
11751 /* Called by sh_contains_memref_p via for_each_rtx. */
11753 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
11755 return (MEM_P (*loc));
11758 /* Return nonzero iff INSN contains a MEM. */
11760 sh_contains_memref_p (rtx insn)
11762 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
11765 /* Return nonzero iff INSN loads a banked register. */
11767 sh_loads_bankedreg_p (rtx insn)
11769 if (GET_CODE (PATTERN (insn)) == SET)
11771 rtx op = SET_DEST (PATTERN(insn));
11772 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11779 /* FNADDR is the MEM expression from a call expander. Return an address
11780 to use in an SHmedia insn pattern. */
11782 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
11786 fnaddr = XEXP (fnaddr, 0);
11787 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
11788 if (flag_pic && is_sym)
11790 if (! SYMBOL_REF_LOCAL_P (fnaddr))
11792 rtx reg = gen_reg_rtx (Pmode);
11794 /* We must not use GOTPLT for sibcalls, because PIC_REG
11795 must be restored before the PLT code gets to run. */
11797 emit_insn (gen_symGOT2reg (reg, fnaddr));
11799 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
11804 fnaddr = gen_sym2PIC (fnaddr);
11805 PUT_MODE (fnaddr, Pmode);
11808 /* If ptabs might trap, make this visible to the rest of the compiler.
11809 We generally assume that symbols pertain to valid locations, but
11810 it is possible to generate invalid symbols with asm or linker tricks.
11811 In a list of functions where each returns its successor, an invalid
11812 symbol might denote an empty list. */
11813 if (!TARGET_PT_FIXED
11814 && (!is_sym || TARGET_INVALID_SYMBOLS)
11815 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
11817 rtx tr = gen_reg_rtx (PDImode);
11819 emit_insn (gen_ptabs (tr, fnaddr));
11822 else if (! target_reg_operand (fnaddr, Pmode))
11823 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
11828 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
11829 enum machine_mode mode, secondary_reload_info *sri)
11833 if (REGCLASS_HAS_FP_REG (rclass)
11834 && ! TARGET_SHMEDIA
11835 && immediate_operand ((x), mode)
11836 && ! ((fp_zero_operand (x) || fp_one_operand (x))
11837 && mode == SFmode && fldi_ok ()))
11841 sri->icode = CODE_FOR_reload_insf__frn;
11844 sri->icode = CODE_FOR_reload_indf__frn;
11847 /* ??? If we knew that we are in the appropriate mode -
11848 single precision - we could use a reload pattern directly. */
11853 if (rclass == FPUL_REGS
11855 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11856 || REGNO (x) == T_REG))
11857 || GET_CODE (x) == PLUS))
11858 return GENERAL_REGS;
11859 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11861 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11862 return GENERAL_REGS;
11863 else if (mode == SFmode)
11865 sri->icode = CODE_FOR_reload_insi__i_fpul;
11868 if (rclass == FPSCR_REGS
11869 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11870 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11871 return GENERAL_REGS;
11872 if (REGCLASS_HAS_FP_REG (rclass)
11874 && immediate_operand (x, mode)
11875 && x != CONST0_RTX (GET_MODE (x))
11876 && GET_MODE (x) != V4SFmode)
11877 return GENERAL_REGS;
11878 if ((mode == QImode || mode == HImode)
11879 && TARGET_SHMEDIA && inqhi_operand (x, mode))
11881 sri->icode = ((mode == QImode)
11882 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
11885 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
11886 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
11887 return TARGET_REGS;
11888 } /* end of input-only processing. */
11890 if (((REGCLASS_HAS_FP_REG (rclass)
11892 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11893 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11894 && TARGET_FMOVD))))
11895 || (REGCLASS_HAS_GENERAL_REG (rclass)
11897 && FP_REGISTER_P (REGNO (x))))
11898 && ! TARGET_SHMEDIA
11899 && (mode == SFmode || mode == SImode))
11901 if ((rclass == FPUL_REGS
11902 || (REGCLASS_HAS_FP_REG (rclass)
11903 && ! TARGET_SHMEDIA && mode == SImode))
11906 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11907 || REGNO (x) == T_REG
11908 || system_reg_operand (x, VOIDmode)))))
11910 if (rclass == FPUL_REGS)
11911 return GENERAL_REGS;
11914 if ((rclass == TARGET_REGS
11915 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
11916 && !satisfies_constraint_Csy (x)
11917 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
11918 return GENERAL_REGS;
11919 if ((rclass == MAC_REGS || rclass == PR_REGS)
11920 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11921 && rclass != REGNO_REG_CLASS (REGNO (x)))
11922 return GENERAL_REGS;
11923 if (rclass != GENERAL_REGS && REG_P (x)
11924 && TARGET_REGISTER_P (REGNO (x)))
11925 return GENERAL_REGS;
11929 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;