1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "insn-config.h"
37 #include "hard-reg-set.h"
39 #include "insn-attr.h"
42 #include "integrate.h"
46 #include "target-def.h"
48 #include "langhooks.h"
49 #include "basic-block.h"
51 #include "cfglayout.h"
53 #include "sched-int.h"
58 #include "alloc-pool.h"
59 #include "tm-constrs.h"
62 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
64 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
65 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
67 /* These are some macros to abstract register modes. */
68 #define CONST_OK_FOR_ADD(size) \
69 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
70 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
71 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
72 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
74 /* Used to simplify the logic below. Find the attributes wherever
76 #define SH_ATTRIBUTES(decl) \
77 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
78 : DECL_ATTRIBUTES (decl) \
79 ? (DECL_ATTRIBUTES (decl)) \
80 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
82 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
83 int current_function_interrupt;
85 tree sh_deferred_function_attributes;
86 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
88 /* Global variables for machine-dependent things. */
90 /* Which cpu are we scheduling for. */
91 enum processor_type sh_cpu;
93 /* Definitions used in ready queue reordering for first scheduling pass. */
95 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
96 static short *regmode_weight[2];
98 /* Total SFmode and SImode weights of scheduled insns. */
99 static int curr_regmode_pressure[2];
101 /* Number of r0 life regions. */
102 static int r0_life_regions;
104 /* If true, skip cycles for Q -> R movement. */
105 static int skip_cycles = 0;
107 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
108 and returned from sh_reorder2. */
109 static short cached_can_issue_more;
111 /* Unique number for UNSPEC_BBR pattern. */
112 static unsigned int unspec_bbr_uid = 1;
114 /* Provides the class number of the smallest class containing
117 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
119 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
125 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
141 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
152 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
153 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
154 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
155 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
156 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
157 GENERAL_REGS, GENERAL_REGS,
160 char sh_register_names[FIRST_PSEUDO_REGISTER] \
161 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
163 char sh_additional_register_names[ADDREGNAMES_SIZE] \
164 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
165 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
167 int assembler_dialect;
169 static bool shmedia_space_reserved_for_target_registers;
171 static bool sh_handle_option (size_t, const char *, int);
172 static void split_branches (rtx);
173 static int branch_dest (rtx);
174 static void force_into (rtx, rtx);
175 static void print_slot (rtx);
176 static rtx add_constant (rtx, enum machine_mode, rtx);
177 static void dump_table (rtx, rtx);
178 static int hi_const (rtx);
179 static int broken_move (rtx);
180 static int mova_p (rtx);
181 static rtx find_barrier (int, rtx, rtx);
182 static int noncall_uses_reg (rtx, rtx, rtx *);
183 static rtx gen_block_redirect (rtx, int, int);
184 static void sh_reorg (void);
185 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
186 static rtx frame_insn (rtx);
187 static rtx push (int);
188 static void pop (int);
189 static void push_regs (HARD_REG_SET *, int);
190 static int calc_live_regs (HARD_REG_SET *);
191 static HOST_WIDE_INT rounded_frame_size (int);
192 static bool sh_frame_pointer_required (void);
193 static rtx mark_constant_pool_use (rtx);
194 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);
195 static tree sh_handle_resbank_handler_attribute (tree *, tree,
197 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
199 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
200 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
201 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
202 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);
203 static void sh_insert_attributes (tree, tree *);
204 static const char *sh_check_pch_target_flags (int);
205 static int sh_adjust_cost (rtx, rtx, rtx, int);
206 static int sh_issue_rate (void);
207 static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);
208 static short find_set_regmode_weight (rtx, enum machine_mode);
209 static short find_insn_regmode_weight (rtx, enum machine_mode);
210 static void find_regmode_weight (basic_block, enum machine_mode);
211 static int find_r0_life_regions (basic_block);
212 static void sh_md_init_global (FILE *, int, int);
213 static void sh_md_finish_global (FILE *, int);
214 static int rank_for_reorder (const void *, const void *);
215 static void swap_reorder (rtx *, int);
216 static void ready_reorder (rtx *, int);
217 static short high_pressure (enum machine_mode);
218 static int sh_reorder (FILE *, int, rtx *, int *, int);
219 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
220 static void sh_md_init (FILE *, int, int);
221 static int sh_variable_issue (FILE *, int, rtx, int);
223 static bool sh_function_ok_for_sibcall (tree, tree);
225 static bool sh_cannot_modify_jumps_p (void);
226 static enum reg_class sh_target_reg_class (void);
227 static bool sh_optimize_target_register_callee_saved (bool);
228 static bool sh_ms_bitfield_layout_p (const_tree);
230 static void sh_init_builtins (void);
231 static tree sh_builtin_decl (unsigned, bool);
232 static void sh_media_init_builtins (void);
233 static tree sh_media_builtin_decl (unsigned, bool);
234 static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
235 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
236 static void sh_file_start (void);
237 static int flow_dependent_p (rtx, rtx);
238 static void flow_dependent_p_1 (rtx, const_rtx, void *);
239 static int shiftcosts (rtx);
240 static int andcosts (rtx);
241 static int addsubcosts (rtx);
242 static int multcosts (rtx);
243 static bool unspec_caller_rtx_p (rtx);
244 static bool sh_cannot_copy_insn_p (rtx);
245 static bool sh_rtx_costs (rtx, int, int, int *, bool);
246 static int sh_address_cost (rtx, bool);
247 static int sh_pr_n_sets (void);
248 static rtx sh_allocate_initial_value (rtx);
249 static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);
250 static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);
251 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
252 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
253 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
254 static int scavenge_reg (HARD_REG_SET *s);
255 struct save_schedule_s;
256 static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
257 struct save_schedule_s *, int);
259 static rtx sh_struct_value_rtx (tree, int);
260 static rtx sh_function_value (const_tree, const_tree, bool);
261 static rtx sh_libcall_value (enum machine_mode, const_rtx);
262 static bool sh_return_in_memory (const_tree, const_tree);
263 static rtx sh_builtin_saveregs (void);
264 static void sh_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
265 static bool sh_strict_argument_naming (CUMULATIVE_ARGS *);
266 static bool sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *);
267 static tree sh_build_builtin_va_list (void);
268 static void sh_va_start (tree, rtx);
269 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
270 static bool sh_promote_prototypes (const_tree);
271 static enum machine_mode sh_promote_function_mode (const_tree type,
276 static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
278 static bool sh_callee_copies (CUMULATIVE_ARGS *, enum machine_mode,
280 static int sh_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
282 static bool sh_scalar_mode_supported_p (enum machine_mode);
283 static int sh_dwarf_calling_convention (const_tree);
284 static void sh_encode_section_info (tree, rtx, int);
285 static int sh2a_function_vector_p (tree);
286 static void sh_trampoline_init (rtx, tree, rtx);
287 static rtx sh_trampoline_adjust_address (rtx);
289 static const struct attribute_spec sh_attribute_table[] =
291 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
292 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
293 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
294 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
295 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute },
296 { "trapa_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
297 { "nosave_low_regs", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
298 { "resbank", 0, 0, true, false, false, sh_handle_resbank_handler_attribute },
299 { "function_vector", 1, 1, true, false, false, sh2a_handle_function_vector_handler_attribute },
301 /* Symbian support adds three new attributes:
302 dllexport - for exporting a function/variable that will live in a dll
303 dllimport - for importing a function/variable from a dll
305 Microsoft allows multiple declspecs in one __declspec, separating
306 them with spaces. We do NOT support this. Instead, use __declspec
308 { "dllimport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
309 { "dllexport", 0, 0, true, false, false, sh_symbian_handle_dll_attribute },
311 { NULL, 0, 0, false, false, false, NULL }
314 /* Initialize the GCC target structure. */
315 #undef TARGET_ATTRIBUTE_TABLE
316 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
318 /* The next two are used for debug info when compiling with -gdwarf. */
319 #undef TARGET_ASM_UNALIGNED_HI_OP
320 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
321 #undef TARGET_ASM_UNALIGNED_SI_OP
322 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
324 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
325 #undef TARGET_ASM_UNALIGNED_DI_OP
326 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
327 #undef TARGET_ASM_ALIGNED_DI_OP
328 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
330 #undef TARGET_ASM_FUNCTION_EPILOGUE
331 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
333 #undef TARGET_ASM_OUTPUT_MI_THUNK
334 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
336 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
337 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
339 #undef TARGET_ASM_FILE_START
340 #define TARGET_ASM_FILE_START sh_file_start
341 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
342 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
344 #undef TARGET_DEFAULT_TARGET_FLAGS
345 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
346 #undef TARGET_HANDLE_OPTION
347 #define TARGET_HANDLE_OPTION sh_handle_option
349 #undef TARGET_INSERT_ATTRIBUTES
350 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
352 #undef TARGET_SCHED_ADJUST_COST
353 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
355 #undef TARGET_SCHED_ISSUE_RATE
356 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
358 /* The next 5 hooks have been implemented for reenabling sched1. With the
359 help of these macros we are limiting the movement of insns in sched1 to
360 reduce the register pressure. The overall idea is to keep count of SImode
361 and SFmode regs required by already scheduled insns. When these counts
362 cross some threshold values; give priority to insns that free registers.
363 The insn that frees registers is most likely to be the insn with lowest
364 LUID (original insn order); but such an insn might be there in the stalled
365 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
366 upto a max of 8 cycles so that such insns may move from Q -> R.
368 The description of the hooks are as below:
370 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
371 scheduler; it is called inside the sched_init function just after
372 find_insn_reg_weights function call. It is used to calculate the SImode
373 and SFmode weights of insns of basic blocks; much similar to what
374 find_insn_reg_weights does.
375 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
377 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
378 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
381 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
382 high; reorder the ready queue so that the insn with lowest LUID will be
385 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
386 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
388 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
389 can be returned from TARGET_SCHED_REORDER2.
391 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
393 #undef TARGET_SCHED_DFA_NEW_CYCLE
394 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
396 #undef TARGET_SCHED_INIT_GLOBAL
397 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
399 #undef TARGET_SCHED_FINISH_GLOBAL
400 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
402 #undef TARGET_SCHED_VARIABLE_ISSUE
403 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
405 #undef TARGET_SCHED_REORDER
406 #define TARGET_SCHED_REORDER sh_reorder
408 #undef TARGET_SCHED_REORDER2
409 #define TARGET_SCHED_REORDER2 sh_reorder2
411 #undef TARGET_SCHED_INIT
412 #define TARGET_SCHED_INIT sh_md_init
414 #undef TARGET_LEGITIMIZE_ADDRESS
415 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
417 #undef TARGET_CANNOT_MODIFY_JUMPS_P
418 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
419 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
420 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
421 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
422 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
423 sh_optimize_target_register_callee_saved
425 #undef TARGET_MS_BITFIELD_LAYOUT_P
426 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
428 #undef TARGET_INIT_BUILTINS
429 #define TARGET_INIT_BUILTINS sh_init_builtins
430 #undef TARGET_BUILTIN_DECL
431 #define TARGET_BUILTIN_DECL sh_builtin_decl
432 #undef TARGET_EXPAND_BUILTIN
433 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
435 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
436 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
438 #undef TARGET_CANNOT_COPY_INSN_P
439 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
440 #undef TARGET_RTX_COSTS
441 #define TARGET_RTX_COSTS sh_rtx_costs
442 #undef TARGET_ADDRESS_COST
443 #define TARGET_ADDRESS_COST sh_address_cost
444 #undef TARGET_ALLOCATE_INITIAL_VALUE
445 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
447 #undef TARGET_MACHINE_DEPENDENT_REORG
448 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
450 #undef TARGET_DWARF_REGISTER_SPAN
451 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
454 #undef TARGET_HAVE_TLS
455 #define TARGET_HAVE_TLS true
458 #undef TARGET_PROMOTE_PROTOTYPES
459 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
460 #undef TARGET_PROMOTE_FUNCTION_MODE
461 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
463 #undef TARGET_FUNCTION_VALUE
464 #define TARGET_FUNCTION_VALUE sh_function_value
465 #undef TARGET_LIBCALL_VALUE
466 #define TARGET_LIBCALL_VALUE sh_libcall_value
467 #undef TARGET_STRUCT_VALUE_RTX
468 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
469 #undef TARGET_RETURN_IN_MEMORY
470 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
472 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
473 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
474 #undef TARGET_SETUP_INCOMING_VARARGS
475 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
476 #undef TARGET_STRICT_ARGUMENT_NAMING
477 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
478 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
479 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
480 #undef TARGET_MUST_PASS_IN_STACK
481 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
482 #undef TARGET_PASS_BY_REFERENCE
483 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
484 #undef TARGET_CALLEE_COPIES
485 #define TARGET_CALLEE_COPIES sh_callee_copies
486 #undef TARGET_ARG_PARTIAL_BYTES
487 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
489 #undef TARGET_BUILD_BUILTIN_VA_LIST
490 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
491 #undef TARGET_EXPAND_BUILTIN_VA_START
492 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
493 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
494 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
496 #undef TARGET_SCALAR_MODE_SUPPORTED_P
497 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
498 #undef TARGET_VECTOR_MODE_SUPPORTED_P
499 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
501 #undef TARGET_CHECK_PCH_TARGET_FLAGS
502 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
504 #undef TARGET_DWARF_CALLING_CONVENTION
505 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
507 #undef TARGET_FRAME_POINTER_REQUIRED
508 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
510 /* Return regmode weight for insn. */
511 #define INSN_REGMODE_WEIGHT(INSN, MODE) regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
513 /* Return current register pressure for regmode. */
514 #define CURR_REGMODE_PRESSURE(MODE) curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
516 #undef TARGET_ENCODE_SECTION_INFO
517 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
521 #undef TARGET_ENCODE_SECTION_INFO
522 #define TARGET_ENCODE_SECTION_INFO sh_symbian_encode_section_info
523 #undef TARGET_STRIP_NAME_ENCODING
524 #define TARGET_STRIP_NAME_ENCODING sh_symbian_strip_name_encoding
525 #undef TARGET_CXX_IMPORT_EXPORT_CLASS
526 #define TARGET_CXX_IMPORT_EXPORT_CLASS sh_symbian_import_export_class
530 #undef TARGET_SECONDARY_RELOAD
531 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
533 #undef TARGET_LEGITIMATE_ADDRESS_P
534 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
536 #undef TARGET_TRAMPOLINE_INIT
537 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
538 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
539 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
541 /* Machine-specific symbol_ref flags. */
542 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
544 struct gcc_target targetm = TARGET_INITIALIZER;
546 /* Implement TARGET_HANDLE_OPTION. */
549 sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
550 int value ATTRIBUTE_UNUSED)
555 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
559 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
563 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
567 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
571 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
574 case OPT_m2a_single_only:
575 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
579 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
583 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
587 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
594 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
598 case OPT_m4_100_nofpu:
599 case OPT_m4_200_nofpu:
600 case OPT_m4_300_nofpu:
604 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
608 case OPT_m4_100_single:
609 case OPT_m4_200_single:
610 case OPT_m4_300_single:
611 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
614 case OPT_m4_single_only:
615 case OPT_m4_100_single_only:
616 case OPT_m4_200_single_only:
617 case OPT_m4_300_single_only:
618 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
622 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
627 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
631 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
634 case OPT_m4a_single_only:
635 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
639 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
642 case OPT_m5_32media_nofpu:
643 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
647 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
650 case OPT_m5_64media_nofpu:
651 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
655 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
658 case OPT_m5_compact_nofpu:
659 target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
667 /* Set default optimization options. */
669 sh_optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
674 sh_div_str = "inv:minlat";
678 target_flags |= MASK_SMALLCODE;
679 sh_div_str = SH_DIV_STR_FOR_SIZE ;
682 TARGET_CBRANCHDI4 = 1;
683 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options
684 haven't been parsed yet, hence we'd read only the default.
685 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so
686 it's OK to always set flag_branch_target_load_optimize. */
689 flag_branch_target_load_optimize = 1;
691 target_flags |= MASK_SAVE_ALL_TARGET_REGS;
693 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE
694 here, so leave it to OVERRIDE_OPTIONS to set
695 flag_finite_math_only. We set it to 2 here so we know if the user
696 explicitly requested this to be on or off. */
697 flag_finite_math_only = 2;
698 /* If flag_schedule_insns is 1, we set it to 2 here so we know if
699 the user explicitly requested this to be on or off. */
700 if (flag_schedule_insns > 0)
701 flag_schedule_insns = 2;
703 set_param_value ("simultaneous-prefetches", 2);
706 /* Implement OVERRIDE_OPTIONS macro. Validate and override various
707 options, and do some machine dependent initialization. */
709 sh_override_options (void)
713 SUBTARGET_OVERRIDE_OPTIONS;
714 if (flag_finite_math_only == 2)
715 flag_finite_math_only
716 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;
717 if (TARGET_SH2E && !flag_finite_math_only)
718 target_flags |= MASK_IEEE;
719 sh_cpu = PROCESSOR_SH1;
720 assembler_dialect = 0;
722 sh_cpu = PROCESSOR_SH2;
724 sh_cpu = PROCESSOR_SH2E;
726 sh_cpu = PROCESSOR_SH2A;
728 sh_cpu = PROCESSOR_SH3;
730 sh_cpu = PROCESSOR_SH3E;
733 assembler_dialect = 1;
734 sh_cpu = PROCESSOR_SH4;
736 if (TARGET_SH4A_ARCH)
738 assembler_dialect = 1;
739 sh_cpu = PROCESSOR_SH4A;
743 sh_cpu = PROCESSOR_SH5;
744 target_flags |= MASK_ALIGN_DOUBLE;
745 if (TARGET_SHMEDIA_FPU)
746 target_flags |= MASK_FMOVD;
749 /* There are no delay slots on SHmedia. */
750 flag_delayed_branch = 0;
751 /* Relaxation isn't yet supported for SHmedia */
752 target_flags &= ~MASK_RELAX;
753 /* After reload, if conversion does little good but can cause
755 - find_if_block doesn't do anything for SH because we don't
756 have conditional execution patterns. (We use conditional
757 move patterns, which are handled differently, and only
759 - find_cond_trap doesn't do anything for the SH because we
760 don't have conditional traps.
761 - find_if_case_1 uses redirect_edge_and_branch_force in
762 the only path that does an optimization, and this causes
763 an ICE when branch targets are in registers.
764 - find_if_case_2 doesn't do anything for the SHmedia after
765 reload except when it can redirect a tablejump - and
766 that's rather rare. */
767 flag_if_conversion2 = 0;
768 if (! strcmp (sh_div_str, "call"))
769 sh_div_strategy = SH_DIV_CALL;
770 else if (! strcmp (sh_div_str, "call2"))
771 sh_div_strategy = SH_DIV_CALL2;
772 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)
773 sh_div_strategy = SH_DIV_FP;
774 else if (! strcmp (sh_div_str, "inv"))
775 sh_div_strategy = SH_DIV_INV;
776 else if (! strcmp (sh_div_str, "inv:minlat"))
777 sh_div_strategy = SH_DIV_INV_MINLAT;
778 else if (! strcmp (sh_div_str, "inv20u"))
779 sh_div_strategy = SH_DIV_INV20U;
780 else if (! strcmp (sh_div_str, "inv20l"))
781 sh_div_strategy = SH_DIV_INV20L;
782 else if (! strcmp (sh_div_str, "inv:call2"))
783 sh_div_strategy = SH_DIV_INV_CALL2;
784 else if (! strcmp (sh_div_str, "inv:call"))
785 sh_div_strategy = SH_DIV_INV_CALL;
786 else if (! strcmp (sh_div_str, "inv:fp"))
789 sh_div_strategy = SH_DIV_INV_FP;
791 sh_div_strategy = SH_DIV_INV;
793 TARGET_CBRANCHDI4 = 0;
794 /* Assembler CFI isn't yet fully supported for SHmedia. */
795 flag_dwarf2_cfi_asm = 0;
800 /* Only the sh64-elf assembler fully supports .quad properly. */
801 targetm.asm_out.aligned_op.di = NULL;
802 targetm.asm_out.unaligned_op.di = NULL;
806 if (! strcmp (sh_div_str, "call-div1"))
807 sh_div_strategy = SH_DIV_CALL_DIV1;
808 else if (! strcmp (sh_div_str, "call-fp")
809 && (TARGET_FPU_DOUBLE
810 || (TARGET_HARD_SH4 && TARGET_SH2E)
811 || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))
812 sh_div_strategy = SH_DIV_CALL_FP;
813 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)
814 sh_div_strategy = SH_DIV_CALL_TABLE;
816 /* Pick one that makes most sense for the target in general.
817 It is not much good to use different functions depending
818 on -Os, since then we'll end up with two different functions
819 when some of the code is compiled for size, and some for
822 /* SH4 tends to emphasize speed. */
824 sh_div_strategy = SH_DIV_CALL_TABLE;
825 /* These have their own way of doing things. */
826 else if (TARGET_SH2A)
827 sh_div_strategy = SH_DIV_INTRINSIC;
828 /* ??? Should we use the integer SHmedia function instead? */
829 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)
830 sh_div_strategy = SH_DIV_CALL_FP;
831 /* SH1 .. SH3 cores often go into small-footprint systems, so
832 default to the smallest implementation available. */
833 else if (TARGET_SH2) /* ??? EXPERIMENTAL */
834 sh_div_strategy = SH_DIV_CALL_TABLE;
836 sh_div_strategy = SH_DIV_CALL_DIV1;
839 TARGET_PRETEND_CMOVE = 0;
840 if (sh_divsi3_libfunc[0])
841 ; /* User supplied - leave it alone. */
842 else if (TARGET_DIVIDE_CALL_FP)
843 sh_divsi3_libfunc = "__sdivsi3_i4";
844 else if (TARGET_DIVIDE_CALL_TABLE)
845 sh_divsi3_libfunc = "__sdivsi3_i4i";
847 sh_divsi3_libfunc = "__sdivsi3_1";
849 sh_divsi3_libfunc = "__sdivsi3";
850 if (sh_branch_cost == -1)
852 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1;
854 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
855 if (! VALID_REGISTER_P (regno))
856 sh_register_names[regno][0] = '\0';
858 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
859 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
860 sh_additional_register_names[regno][0] = '\0';
862 flag_omit_frame_pointer = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
864 if ((flag_pic && ! TARGET_PREFERGOT)
865 || (TARGET_SHMEDIA && !TARGET_PT_FIXED))
866 flag_no_function_cse = 1;
868 if (targetm.small_register_classes_for_mode_p (VOIDmode)) \
870 /* Never run scheduling before reload, since that can
871 break global alloc, and generates slower code anyway due
872 to the pressure on R0. */
873 /* Enable sched1 for SH4 if the user explicitly requests.
874 When sched1 is enabled, the ready queue will be reordered by
875 the target hooks if pressure is high. We can not do this for
876 PIC, SH3 and lower as they give spill failures for R0. */
877 if (!TARGET_HARD_SH4 || flag_pic)
878 flag_schedule_insns = 0;
879 /* ??? Current exception handling places basic block boundaries
880 after call_insns. It causes the high pressure on R0 and gives
881 spill failures for R0 in reload. See PR 22553 and the thread
883 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
884 else if (flag_exceptions)
886 if (flag_schedule_insns == 1)
887 warning (0, "ignoring -fschedule-insns because of exception handling bug");
888 flag_schedule_insns = 0;
890 else if (flag_schedule_insns == 2)
891 flag_schedule_insns = 0;
894 if ((target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) == 0)
895 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
897 /* Unwind info is not correct around the CFG unless either a frame
898 pointer is present or M_A_O_A is set. Fixing this requires rewriting
899 unwind info generation to be aware of the CFG and propagating states
901 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
902 || flag_exceptions || flag_non_call_exceptions)
903 && flag_omit_frame_pointer
904 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
906 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
907 warning (0, "unwind tables currently require either a frame pointer "
908 "or -maccumulate-outgoing-args for correctness");
909 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
912 /* Unwinding with -freorder-blocks-and-partition does not work on this
913 architecture, because it requires far jumps to label crossing between
914 hot/cold sections which are rejected on this architecture. */
915 if (flag_reorder_blocks_and_partition)
919 inform (input_location,
920 "-freorder-blocks-and-partition does not work with "
921 "exceptions on this architecture");
922 flag_reorder_blocks_and_partition = 0;
923 flag_reorder_blocks = 1;
925 else if (flag_unwind_tables)
927 inform (input_location,
928 "-freorder-blocks-and-partition does not support unwind "
929 "info on this architecture");
930 flag_reorder_blocks_and_partition = 0;
931 flag_reorder_blocks = 1;
935 if (align_loops == 0)
936 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
937 if (align_jumps == 0)
938 align_jumps = 1 << CACHE_LOG;
939 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
940 align_jumps = TARGET_SHMEDIA ? 4 : 2;
942 /* Allocation boundary (in *bytes*) for the code of a function.
943 SH1: 32 bit alignment is faster, because instructions are always
944 fetched as a pair from a longword boundary.
945 SH2 .. SH5 : align to cache line start. */
946 if (align_functions == 0)
948 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
949 /* The linker relaxation code breaks when a function contains
950 alignments that are larger than that at the start of a
955 = align_loops > align_jumps ? align_loops : align_jumps;
957 /* Also take possible .long constants / mova tables int account. */
960 if (align_functions < min_align)
961 align_functions = min_align;
964 if (sh_fixed_range_str)
965 sh_fix_range (sh_fixed_range_str);
968 /* Print the operand address in x to the stream. */
971 print_operand_address (FILE *stream, rtx x)
973 switch (GET_CODE (x))
977 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
982 rtx base = XEXP (x, 0);
983 rtx index = XEXP (x, 1);
985 switch (GET_CODE (index))
988 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
989 reg_names[true_regnum (base)]);
995 int base_num = true_regnum (base);
996 int index_num = true_regnum (index);
998 fprintf (stream, "@(r0,%s)",
999 reg_names[MAX (base_num, index_num)]);
1010 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
1014 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
1018 x = mark_constant_pool_use (x);
1019 output_addr_const (stream, x);
1024 /* Print operand x (an rtx) in assembler syntax to file stream
1025 according to modifier code.
1027 '.' print a .s if insn needs delay slot
1028 ',' print LOCAL_LABEL_PREFIX
1029 '@' print trap, rte or rts depending upon pragma interruptness
1030 '#' output a nop if there is nothing to put in the delay slot
1031 ''' print likelihood suffix (/u for unlikely).
1032 '>' print branch target if -fverbose-asm
1033 'O' print a constant without the #
1034 'R' print the LSW of a dp value - changes if in little endian
1035 'S' print the MSW of a dp value - changes if in little endian
1036 'T' print the next word of a dp value - same as 'R' in big endian mode.
1037 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1038 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1039 'N' print 'r63' if the operand is (const_int 0).
1040 'd' print a V2SF reg as dN instead of fpN.
1041 'm' print a pair `base,offset' or `base,index', for LD and ST.
1042 'U' Likewise for {LD,ST}{HI,LO}.
1043 'V' print the position of a single bit set.
1044 'W' print the position of a single bit cleared.
1045 't' print a memory address which is a register.
1046 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1047 'o' output an operator. */
1050 print_operand (FILE *stream, rtx x, int code)
1053 enum machine_mode mode;
1061 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1062 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
1063 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1066 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1069 trapa_attr = lookup_attribute ("trap_exit",
1070 DECL_ATTRIBUTES (current_function_decl));
1072 fprintf (stream, "trapa #%ld",
1073 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1074 else if (sh_cfun_interrupt_handler_p ())
1076 if (sh_cfun_resbank_handler_p ())
1077 fprintf (stream, "resbank\n");
1078 fprintf (stream, "rte");
1081 fprintf (stream, "rts");
1084 /* Output a nop if there's nothing in the delay slot. */
1085 if (dbr_sequence_length () == 0)
1086 fprintf (stream, "\n\tnop");
1090 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1092 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
1093 fputs ("/u", stream);
1097 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1099 fputs ("\t! target: ", stream);
1100 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1104 x = mark_constant_pool_use (x);
1105 output_addr_const (stream, x);
1107 /* N.B.: %R / %S / %T adjust memory addresses by four.
1108 For SHMEDIA, that means they can be used to access the first and
1109 second 32 bit part of a 64 bit (or larger) value that
1110 might be held in floating point registers or memory.
1111 While they can be used to access 64 bit parts of a larger value
1112 held in general purpose registers, that won't work with memory -
1113 neither for fp registers, since the frxx names are used. */
1115 if (REG_P (x) || GET_CODE (x) == SUBREG)
1117 regno = true_regnum (x);
1118 regno += FP_REGISTER_P (regno) ? 1 : LSW;
1119 fputs (reg_names[regno], (stream));
1123 x = adjust_address (x, SImode, 4 * LSW);
1124 print_operand_address (stream, XEXP (x, 0));
1130 mode = GET_MODE (x);
1131 if (mode == VOIDmode)
1133 if (GET_MODE_SIZE (mode) >= 8)
1134 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
1136 print_operand (stream, sub, 0);
1138 output_operand_lossage ("invalid operand to %%R");
1142 if (REG_P (x) || GET_CODE (x) == SUBREG)
1144 regno = true_regnum (x);
1145 regno += FP_REGISTER_P (regno) ? 0 : MSW;
1146 fputs (reg_names[regno], (stream));
1150 x = adjust_address (x, SImode, 4 * MSW);
1151 print_operand_address (stream, XEXP (x, 0));
1157 mode = GET_MODE (x);
1158 if (mode == VOIDmode)
1160 if (GET_MODE_SIZE (mode) >= 8)
1161 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
1163 print_operand (stream, sub, 0);
1165 output_operand_lossage ("invalid operand to %%S");
1169 /* Next word of a double. */
1170 switch (GET_CODE (x))
1173 fputs (reg_names[REGNO (x) + 1], (stream));
1176 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1177 && GET_CODE (XEXP (x, 0)) != POST_INC)
1178 x = adjust_address (x, SImode, 4);
1179 print_operand_address (stream, XEXP (x, 0));
1187 gcc_assert (MEM_P (x));
1189 switch (GET_CODE (x))
1193 print_operand (stream, x, 0);
1201 switch (GET_CODE (x))
1203 case PLUS: fputs ("add", stream); break;
1204 case MINUS: fputs ("sub", stream); break;
1205 case MULT: fputs ("mul", stream); break;
1206 case DIV: fputs ("div", stream); break;
1207 case EQ: fputs ("eq", stream); break;
1208 case NE: fputs ("ne", stream); break;
1209 case GT: case LT: fputs ("gt", stream); break;
1210 case GE: case LE: fputs ("ge", stream); break;
1211 case GTU: case LTU: fputs ("gtu", stream); break;
1212 case GEU: case LEU: fputs ("geu", stream); break;
1221 && GET_CODE (XEXP (x, 0)) == PLUS
1222 && (REG_P (XEXP (XEXP (x, 0), 1))
1223 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
1224 fputc ('x', stream);
1230 switch (GET_MODE (x))
1232 case QImode: fputs (".b", stream); break;
1233 case HImode: fputs (".w", stream); break;
1234 case SImode: fputs (".l", stream); break;
1235 case SFmode: fputs (".s", stream); break;
1236 case DFmode: fputs (".d", stream); break;
1237 default: gcc_unreachable ();
1244 gcc_assert (MEM_P (x));
1248 switch (GET_CODE (x))
1252 print_operand (stream, x, 0);
1253 fputs (", 0", stream);
1257 print_operand (stream, XEXP (x, 0), 0);
1258 fputs (", ", stream);
1259 print_operand (stream, XEXP (x, 1), 0);
1269 int num = exact_log2 (INTVAL (x));
1270 gcc_assert (num >= 0);
1271 fprintf (stream, "#%d", num);
1277 int num = exact_log2 (~INTVAL (x));
1278 gcc_assert (num >= 0);
1279 fprintf (stream, "#%d", num);
1284 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1286 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1290 if (x == CONST0_RTX (GET_MODE (x)))
1292 fprintf ((stream), "r63");
1295 goto default_output;
1297 if (CONST_INT_P (x))
1299 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1307 mode = GET_MODE (x);
1309 switch (GET_CODE (x))
1313 rtx inner = XEXP (x, 0);
1315 enum machine_mode inner_mode;
1317 /* We might see SUBREGs with vector mode registers inside. */
1318 if (GET_CODE (inner) == SUBREG
1319 && (GET_MODE_SIZE (GET_MODE (inner))
1320 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1321 && subreg_lowpart_p (inner))
1322 inner = SUBREG_REG (inner);
1323 if (CONST_INT_P (inner))
1325 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1326 goto default_output;
1328 inner_mode = GET_MODE (inner);
1329 if (GET_CODE (inner) == SUBREG
1330 && (GET_MODE_SIZE (GET_MODE (inner))
1331 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1332 && REG_P (SUBREG_REG (inner)))
1334 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1335 GET_MODE (SUBREG_REG (inner)),
1336 SUBREG_BYTE (inner),
1338 inner = SUBREG_REG (inner);
1340 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1342 /* Floating point register pairs are always big endian;
1343 general purpose registers are 64 bit wide. */
1344 regno = REGNO (inner);
1345 regno = (HARD_REGNO_NREGS (regno, inner_mode)
1346 - HARD_REGNO_NREGS (regno, mode))
1354 /* FIXME: We need this on SHmedia32 because reload generates
1355 some sign-extended HI or QI loads into DImode registers
1356 but, because Pmode is SImode, the address ends up with a
1357 subreg:SI of the DImode register. Maybe reload should be
1358 fixed so as to apply alter_subreg to such loads? */
1360 gcc_assert (trapping_target_operand (x, VOIDmode));
1361 x = XEXP (XEXP (x, 2), 0);
1362 goto default_output;
1364 gcc_assert (SUBREG_BYTE (x) == 0
1365 && REG_P (SUBREG_REG (x)));
1373 if (FP_REGISTER_P (regno)
1374 && mode == V16SFmode)
1375 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1376 else if (FP_REGISTER_P (REGNO (x))
1377 && mode == V4SFmode)
1378 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1380 && mode == V2SFmode)
1381 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1382 else if (FP_REGISTER_P (REGNO (x))
1383 && GET_MODE_SIZE (mode) > 4)
1384 fprintf ((stream), "d%s", reg_names[regno] + 1);
1386 fputs (reg_names[regno], (stream));
1390 output_address (XEXP (x, 0));
1395 fputc ('#', stream);
1396 output_addr_const (stream, x);
1404 /* Encode symbol attributes of a SYMBOL_REF into its
1405 SYMBOL_REF_FLAGS. */
1407 sh_encode_section_info (tree decl, rtx rtl, int first)
1409 default_encode_section_info (decl, rtl, first);
1411 if (TREE_CODE (decl) == FUNCTION_DECL
1412 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1413 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1416 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
1418 force_into (rtx value, rtx target)
1420 value = force_operand (value, target);
1421 if (! rtx_equal_p (value, target))
1422 emit_insn (gen_move_insn (target, value));
1425 /* Emit code to perform a block move. Choose the best method.
1427 OPERANDS[0] is the destination.
1428 OPERANDS[1] is the source.
1429 OPERANDS[2] is the size.
1430 OPERANDS[3] is the alignment safe to use. */
1433 expand_block_move (rtx *operands)
1435 int align = INTVAL (operands[3]);
1436 int constp = (CONST_INT_P (operands[2]));
1437 int bytes = (constp ? INTVAL (operands[2]) : 0);
1442 /* If we could use mov.l to move words and dest is word-aligned, we
1443 can use movua.l for loads and still generate a relatively short
1444 and efficient sequence. */
1445 if (TARGET_SH4A_ARCH && align < 4
1446 && MEM_ALIGN (operands[0]) >= 32
1447 && can_move_by_pieces (bytes, 32))
1449 rtx dest = copy_rtx (operands[0]);
1450 rtx src = copy_rtx (operands[1]);
1451 /* We could use different pseudos for each copied word, but
1452 since movua can only load into r0, it's kind of
1454 rtx temp = gen_reg_rtx (SImode);
1455 rtx src_addr = copy_addr_to_reg (XEXP (src, 0));
1458 while (copied + 4 <= bytes)
1460 rtx to = adjust_address (dest, SImode, copied);
1461 rtx from = adjust_automodify_address (src, BLKmode,
1464 set_mem_size (from, GEN_INT (4));
1465 emit_insn (gen_movua (temp, from));
1466 emit_move_insn (src_addr, plus_constant (src_addr, 4));
1467 emit_move_insn (to, temp);
1472 move_by_pieces (adjust_address (dest, BLKmode, copied),
1473 adjust_automodify_address (src, BLKmode,
1475 bytes - copied, align, 0);
1480 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
1481 alignment, or if it isn't a multiple of 4 bytes, then fail. */
1482 if (align < 4 || (bytes % 4 != 0))
1485 if (TARGET_HARD_SH4)
1489 else if (bytes == 12)
1491 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1492 rtx r4 = gen_rtx_REG (SImode, 4);
1493 rtx r5 = gen_rtx_REG (SImode, 5);
1495 function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
1496 force_into (XEXP (operands[0], 0), r4);
1497 force_into (XEXP (operands[1], 0), r5);
1498 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
1501 else if (! TARGET_SMALLCODE)
1503 const char *entry_name;
1504 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1506 rtx r4 = gen_rtx_REG (SImode, 4);
1507 rtx r5 = gen_rtx_REG (SImode, 5);
1508 rtx r6 = gen_rtx_REG (SImode, 6);
1510 entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
1511 function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
1512 force_into (XEXP (operands[0], 0), r4);
1513 force_into (XEXP (operands[1], 0), r5);
1515 dwords = bytes >> 3;
1516 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
1517 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
1526 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1527 rtx r4 = gen_rtx_REG (SImode, 4);
1528 rtx r5 = gen_rtx_REG (SImode, 5);
1530 sprintf (entry, "__movmemSI%d", bytes);
1531 function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
1532 force_into (XEXP (operands[0], 0), r4);
1533 force_into (XEXP (operands[1], 0), r5);
1534 emit_insn (gen_block_move_real (func_addr_rtx));
1538 /* This is the same number of bytes as a memcpy call, but to a different
1539 less common function name, so this will occasionally use more space. */
1540 if (! TARGET_SMALLCODE)
1542 rtx func_addr_rtx = gen_reg_rtx (Pmode);
1543 int final_switch, while_loop;
1544 rtx r4 = gen_rtx_REG (SImode, 4);
1545 rtx r5 = gen_rtx_REG (SImode, 5);
1546 rtx r6 = gen_rtx_REG (SImode, 6);
1548 function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
1549 force_into (XEXP (operands[0], 0), r4);
1550 force_into (XEXP (operands[1], 0), r5);
1552 /* r6 controls the size of the move. 16 is decremented from it
1553 for each 64 bytes moved. Then the negative bit left over is used
1554 as an index into a list of move instructions. e.g., a 72 byte move
1555 would be set up with size(r6) = 14, for one iteration through the
1556 big while loop, and a switch of -2 for the last part. */
1558 final_switch = 16 - ((bytes / 4) % 16);
1559 while_loop = ((bytes / 4) / 16 - 1) * 16;
1560 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
1561 emit_insn (gen_block_lump_real (func_addr_rtx));
1568 /* Prepare operands for a move define_expand; specifically, one of the
1569 operands must be in a register. */
1572 prepare_move_operands (rtx operands[], enum machine_mode mode)
1574 if ((mode == SImode || mode == DImode)
1576 && ! ((mode == Pmode || mode == ptr_mode)
1577 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1580 if (SYMBOLIC_CONST_P (operands[1]))
1582 if (MEM_P (operands[0]))
1583 operands[1] = force_reg (Pmode, operands[1]);
1584 else if (TARGET_SHMEDIA
1585 && GET_CODE (operands[1]) == LABEL_REF
1586 && target_reg_operand (operands[0], mode))
1590 temp = (!can_create_pseudo_p ()
1592 : gen_reg_rtx (Pmode));
1593 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1596 else if (GET_CODE (operands[1]) == CONST
1597 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1598 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1600 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1601 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1603 operands[1] = expand_binop (mode, add_optab, temp,
1604 XEXP (XEXP (operands[1], 0), 1),
1605 (!can_create_pseudo_p ()
1607 : gen_reg_rtx (Pmode)),
1608 0, OPTAB_LIB_WIDEN);
1612 if (! reload_in_progress && ! reload_completed)
1614 /* Copy the source to a register if both operands aren't registers. */
1615 if (! register_operand (operands[0], mode)
1616 && ! sh_register_operand (operands[1], mode))
1617 operands[1] = copy_to_mode_reg (mode, operands[1]);
1619 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1621 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1622 except that we can't use that function because it is static. */
1623 rtx new_rtx = change_address (operands[0], mode, 0);
1624 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1625 operands[0] = new_rtx;
1628 /* This case can happen while generating code to move the result
1629 of a library call to the target. Reject `st r0,@(rX,rY)' because
1630 reload will fail to find a spill register for rX, since r0 is already
1631 being used for the source. */
1633 && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
1634 && MEM_P (operands[0])
1635 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1636 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1637 operands[1] = copy_to_mode_reg (mode, operands[1]);
1640 if (mode == Pmode || mode == ptr_mode)
1643 enum tls_model tls_kind;
1647 if (GET_CODE (op1) == CONST
1648 && GET_CODE (XEXP (op1, 0)) == PLUS
1649 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1652 opc = XEXP (XEXP (op1, 0), 1);
1653 op1 = XEXP (XEXP (op1, 0), 0);
1658 if ((tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1660 rtx tga_op1, tga_ret, tmp, tmp2;
1664 case TLS_MODEL_GLOBAL_DYNAMIC:
1665 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1666 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1670 case TLS_MODEL_LOCAL_DYNAMIC:
1671 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1672 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1674 tmp = gen_reg_rtx (Pmode);
1675 emit_move_insn (tmp, tga_ret);
1677 if (register_operand (op0, Pmode))
1680 tmp2 = gen_reg_rtx (Pmode);
1682 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1686 case TLS_MODEL_INITIAL_EXEC:
1689 /* Don't schedule insns for getting GOT address when
1690 the first scheduling is enabled, to avoid spill
1692 if (flag_schedule_insns)
1693 emit_insn (gen_blockage ());
1694 emit_insn (gen_GOTaddr2picreg ());
1695 emit_use (gen_rtx_REG (SImode, PIC_REG));
1696 if (flag_schedule_insns)
1697 emit_insn (gen_blockage ());
1699 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1700 tmp = gen_sym2GOTTPOFF (op1);
1701 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1705 case TLS_MODEL_LOCAL_EXEC:
1706 tmp2 = gen_reg_rtx (Pmode);
1707 emit_insn (gen_load_gbr (tmp2));
1708 tmp = gen_reg_rtx (Pmode);
1709 emit_insn (gen_symTPOFF2reg (tmp, op1));
1711 if (register_operand (op0, Pmode))
1714 op1 = gen_reg_rtx (Pmode);
1716 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1723 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1732 prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
1733 enum rtx_code comparison)
1736 rtx scratch = NULL_RTX;
1738 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1739 comparison = GET_CODE (operands[0]);
1741 scratch = operands[4];
1742 if (CONST_INT_P (operands[1])
1743 && !CONST_INT_P (operands[2]))
1745 rtx tmp = operands[1];
1747 operands[1] = operands[2];
1749 comparison = swap_condition (comparison);
1751 if (CONST_INT_P (operands[2]))
1753 HOST_WIDE_INT val = INTVAL (operands[2]);
1754 if ((val == -1 || val == -0x81)
1755 && (comparison == GT || comparison == LE))
1757 comparison = (comparison == GT) ? GE : LT;
1758 operands[2] = gen_int_mode (val + 1, mode);
1760 else if ((val == 1 || val == 0x80)
1761 && (comparison == GE || comparison == LT))
1763 comparison = (comparison == GE) ? GT : LE;
1764 operands[2] = gen_int_mode (val - 1, mode);
1766 else if (val == 1 && (comparison == GEU || comparison == LTU))
1768 comparison = (comparison == GEU) ? NE : EQ;
1769 operands[2] = CONST0_RTX (mode);
1771 else if (val == 0x80 && (comparison == GEU || comparison == LTU))
1773 comparison = (comparison == GEU) ? GTU : LEU;
1774 operands[2] = gen_int_mode (val - 1, mode);
1776 else if (val == 0 && (comparison == GTU || comparison == LEU))
1777 comparison = (comparison == GTU) ? NE : EQ;
1778 else if (mode == SImode
1779 && ((val == 0x7fffffff
1780 && (comparison == GTU || comparison == LEU))
1781 || ((unsigned HOST_WIDE_INT) val
1782 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
1783 && (comparison == GEU || comparison == LTU))))
1785 comparison = (comparison == GTU || comparison == GEU) ? LT : GE;
1786 operands[2] = CONST0_RTX (mode);
1790 if (can_create_pseudo_p ())
1791 operands[1] = force_reg (mode, op1);
1792 /* When we are handling DImode comparisons, we want to keep constants so
1793 that we can optimize the component comparisons; however, memory loads
1794 are better issued as a whole so that they can be scheduled well.
1795 SImode equality comparisons allow I08 constants, but only when they
1796 compare r0. Hence, if operands[1] has to be loaded from somewhere else
1797 into a register, that register might as well be r0, and we allow the
1798 constant. If it is already in a register, this is likely to be
1799 allocated to a different hard register, thus we load the constant into
1800 a register unless it is zero. */
1801 if (!REG_P (operands[2])
1802 && (!CONST_INT_P (operands[2])
1803 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
1804 && ((comparison != EQ && comparison != NE)
1805 || (REG_P (op1) && REGNO (op1) != R0_REG)
1806 || !satisfies_constraint_I08 (operands[2])))))
1808 if (scratch && GET_MODE (scratch) == mode)
1810 emit_move_insn (scratch, operands[2]);
1811 operands[2] = scratch;
1813 else if (can_create_pseudo_p ())
1814 operands[2] = force_reg (mode, operands[2]);
1820 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
1822 rtx (*branch_expander) (rtx) = gen_branch_true;
1825 comparison = prepare_cbranch_operands (operands, SImode, comparison);
1828 case NE: case LT: case LE: case LTU: case LEU:
1829 comparison = reverse_condition (comparison);
1830 branch_expander = gen_branch_false;
1833 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
1834 gen_rtx_fmt_ee (comparison, SImode,
1835 operands[1], operands[2])));
1836 jump = emit_jump_insn (branch_expander (operands[3]));
1837 if (probability >= 0)
1838 add_reg_note (jump, REG_BR_PROB, GEN_INT (probability));
1842 /* ??? How should we distribute probabilities when more than one branch
1843 is generated. So far we only have soem ad-hoc observations:
1844 - If the operands are random, they are likely to differ in both parts.
1845 - If comparing items in a hash chain, the operands are random or equal;
1846 operation should be EQ or NE.
1847 - If items are searched in an ordered tree from the root, we can expect
1848 the highpart to be unequal about half of the time; operation should be
1849 an inequality comparison, operands non-constant, and overall probability
1850 about 50%. Likewise for quicksort.
1851 - Range checks will be often made against constants. Even if we assume for
1852 simplicity an even distribution of the non-constant operand over a
1853 sub-range here, the same probability could be generated with differently
1854 wide sub-ranges - as long as the ratio of the part of the subrange that
1855 is before the threshold to the part that comes after the threshold stays
1856 the same. Thus, we can't really tell anything here;
1857 assuming random distribution is at least simple.
1861 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
1863 enum rtx_code msw_taken, msw_skip, lsw_taken;
1864 rtx skip_label = NULL_RTX;
1865 rtx op1h, op1l, op2h, op2l;
1868 int msw_taken_prob = -1, msw_skip_prob = -1, lsw_taken_prob = -1;
1869 rtx scratch = operands[4];
1871 comparison = prepare_cbranch_operands (operands, DImode, comparison);
1872 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
1873 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
1874 op1l = gen_lowpart (SImode, operands[1]);
1875 op2l = gen_lowpart (SImode, operands[2]);
1876 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
1877 prob = split_branch_probability;
1878 rev_prob = REG_BR_PROB_BASE - prob;
1881 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
1882 That costs 1 cycle more when the first branch can be predicted taken,
1883 but saves us mispredicts because only one branch needs prediction.
1884 It also enables generating the cmpeqdi_t-1 pattern. */
1886 if (TARGET_CMPEQDI_T)
1888 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1889 emit_jump_insn (gen_branch_true (operands[3]));
1896 /* If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
1898 msw_skip_prob = rev_prob;
1899 if (REG_BR_PROB_BASE <= 65535)
1900 lsw_taken_prob = prob ? REG_BR_PROB_BASE : 0;
1903 gcc_assert (HOST_BITS_PER_WIDEST_INT >= 64);
1907 - ((HOST_WIDEST_INT) REG_BR_PROB_BASE * rev_prob
1908 / ((HOST_WIDEST_INT) prob << 32)))
1914 if (TARGET_CMPEQDI_T)
1916 emit_insn (gen_cmpeqdi_t (operands[1], operands[2]));
1917 emit_jump_insn (gen_branch_false (operands[3]));
1921 msw_taken_prob = prob;
1926 msw_taken = comparison;
1927 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1929 if (comparison != GTU || op2h != CONST0_RTX (SImode))
1930 msw_skip = swap_condition (msw_taken);
1934 if (op2l == CONST0_RTX (SImode))
1935 msw_taken = comparison;
1938 msw_taken = comparison == GE ? GT : GTU;
1939 msw_skip = swap_condition (msw_taken);
1944 msw_taken = comparison;
1945 if (op2l == CONST0_RTX (SImode))
1947 msw_skip = swap_condition (msw_taken);
1951 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
1952 msw_taken = comparison;
1956 if (comparison == LE)
1958 else if (op2h != CONST0_RTX (SImode))
1962 msw_skip = swap_condition (msw_taken);
1965 default: return false;
1967 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
1968 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
1969 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
1970 if (comparison != EQ && comparison != NE && num_branches > 1)
1972 if (!CONSTANT_P (operands[2])
1973 && prob >= (int) (REG_BR_PROB_BASE * 3 / 8U)
1974 && prob <= (int) (REG_BR_PROB_BASE * 5 / 8U))
1976 msw_taken_prob = prob / 2U;
1978 = REG_BR_PROB_BASE * rev_prob / (REG_BR_PROB_BASE + rev_prob);
1979 lsw_taken_prob = prob;
1983 msw_taken_prob = prob;
1984 msw_skip_prob = REG_BR_PROB_BASE;
1985 /* ??? If we have a constant op2h, should we use that when
1986 calculating lsw_taken_prob? */
1987 lsw_taken_prob = prob;
1992 operands[4] = NULL_RTX;
1993 if (reload_completed
1994 && ! arith_reg_or_0_operand (op2h, SImode)
1995 && (true_regnum (op1h) || (comparison != EQ && comparison != NE))
1996 && (msw_taken != LAST_AND_UNUSED_RTX_CODE
1997 || msw_skip != LAST_AND_UNUSED_RTX_CODE))
1999 emit_move_insn (scratch, operands[2]);
2000 operands[2] = scratch;
2002 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2003 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2004 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2006 rtx taken_label = operands[3];
2008 /* Operands were possibly modified, but msw_skip doesn't expect this.
2009 Always use the original ones. */
2010 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2016 operands[3] = skip_label = gen_label_rtx ();
2017 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2018 operands[3] = taken_label;
2022 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2024 if (reload_completed
2025 && ! arith_reg_or_0_operand (op2l, SImode)
2026 && (true_regnum (op1l) || (lsw_taken != EQ && lsw_taken != NE)))
2028 emit_move_insn (scratch, operands[2]);
2029 operands[2] = scratch;
2031 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2033 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2034 emit_label (skip_label);
2038 /* Emit INSN, possibly in a PARALLEL with an USE of fpscr for SH4. */
2041 sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
2043 if ((TARGET_SH4 || TARGET_SH2A) && GET_MODE_CLASS (mode) == MODE_FLOAT)
2045 insn = gen_rtx_PARALLEL (VOIDmode,
2047 gen_rtx_USE (VOIDmode, get_fpscr_rtx ())));
2048 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
2054 /* Prepare the operands for an scc instruction; make sure that the
2055 compare has been done and the result is in T_REG. */
2057 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2059 rtx t_reg = gen_rtx_REG (SImode, T_REG);
2060 enum rtx_code oldcode = code;
2061 enum machine_mode mode;
2063 /* First need a compare insn. */
2067 /* It isn't possible to handle this case. */
2084 if (code != oldcode)
2091 mode = GET_MODE (op0);
2092 if (mode == VOIDmode)
2093 mode = GET_MODE (op1);
2095 op0 = force_reg (mode, op0);
2096 if ((code != EQ && code != NE
2097 && (op1 != const0_rtx
2098 || code == GTU || code == GEU || code == LTU || code == LEU))
2099 || (mode == DImode && op1 != const0_rtx)
2100 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2101 op1 = force_reg (mode, op1);
2103 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode, t_reg,
2104 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2109 sh_emit_cheap_store_flag (enum machine_mode mode, enum rtx_code code,
2112 rtx target = gen_reg_rtx (SImode);
2115 gcc_assert (TARGET_SHMEDIA);
2124 tmp = gen_rtx_fmt_ee (code, SImode, op0, op1);
2125 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2135 tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1);
2136 emit_insn (gen_cstore4_media (target, tmp, op0, op1));
2154 rtx t2 = gen_reg_rtx (DImode);
2155 emit_insn (gen_extendsidi2 (t2, target));
2159 return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx);
2162 /* Called from the md file, set up the operands of a compare instruction. */
2165 sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
2167 enum rtx_code code = GET_CODE (operands[0]);
2168 enum rtx_code branch_code;
2169 rtx op0 = operands[1];
2170 rtx op1 = operands[2];
2172 bool need_ccmpeq = false;
2174 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2176 op0 = force_reg (mode, op0);
2177 op1 = force_reg (mode, op1);
2181 if (code != EQ || mode == DImode)
2183 /* Force args into regs, since we can't use constants here. */
2184 op0 = force_reg (mode, op0);
2185 if (op1 != const0_rtx || code == GTU || code == GEU)
2186 op1 = force_reg (mode, op1);
2190 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2193 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2194 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2196 tem = op0, op0 = op1, op1 = tem;
2197 code = swap_condition (code);
2200 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2203 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2208 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2209 to EQ/GT respectively. */
2210 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2227 branch_code = reverse_condition (code);
2233 insn = gen_rtx_SET (VOIDmode,
2234 gen_rtx_REG (SImode, T_REG),
2235 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2237 sh_emit_set_t_insn (insn, mode);
2239 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2241 if (branch_code == code)
2242 emit_jump_insn (gen_branch_true (operands[3]));
2244 emit_jump_insn (gen_branch_false (operands[3]));
2248 sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
2250 enum rtx_code code = GET_CODE (operands[1]);
2251 rtx op0 = operands[2];
2252 rtx op1 = operands[3];
2254 bool invert = false;
2257 op0 = force_reg (mode, op0);
2258 if ((code != EQ && code != NE
2259 && (op1 != const0_rtx
2260 || code == GTU || code == GEU || code == LTU || code == LEU))
2261 || (mode == DImode && op1 != const0_rtx)
2262 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2263 op1 = force_reg (mode, op1);
2265 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2267 if (code == LT || code == LE)
2269 code = swap_condition (code);
2270 tem = op0, op0 = op1, op1 = tem;
2276 lab = gen_label_rtx ();
2277 sh_emit_scc_to_t (EQ, op0, op1);
2278 emit_jump_insn (gen_branch_true (lab));
2295 sh_emit_scc_to_t (code, op0, op1);
2299 emit_insn (gen_movnegt (operands[0]));
2301 emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
2304 /* Functions to output assembly code. */
2306 /* Return a sequence of instructions to perform DI or DF move.
2308 Since the SH cannot move a DI or DF in one instruction, we have
2309 to take care when we see overlapping source and dest registers. */
2312 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2313 enum machine_mode mode)
2315 rtx dst = operands[0];
2316 rtx src = operands[1];
2319 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2320 return "mov.l %T1,%0\n\tmov.l %1,%0";
2322 if (register_operand (dst, mode)
2323 && register_operand (src, mode))
2325 if (REGNO (src) == MACH_REG)
2326 return "sts mach,%S0\n\tsts macl,%R0";
2328 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2329 when mov.d r1,r0 do r1->r0 then r2->r1. */
2331 if (REGNO (src) + 1 == REGNO (dst))
2332 return "mov %T1,%T0\n\tmov %1,%0";
2334 return "mov %1,%0\n\tmov %T1,%T0";
2336 else if (CONST_INT_P (src))
2338 if (INTVAL (src) < 0)
2339 output_asm_insn ("mov #-1,%S0", operands);
2341 output_asm_insn ("mov #0,%S0", operands);
2343 return "mov %1,%R0";
2345 else if (MEM_P (src))
2348 int dreg = REGNO (dst);
2349 rtx inside = XEXP (src, 0);
2351 switch (GET_CODE (inside))
2354 ptrreg = REGNO (inside);
2358 ptrreg = subreg_regno (inside);
2362 ptrreg = REGNO (XEXP (inside, 0));
2363 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2364 an offsettable address. Unfortunately, offsettable addresses use
2365 QImode to check the offset, and a QImode offsettable address
2366 requires r0 for the other operand, which is not currently
2367 supported, so we can't use the 'o' constraint.
2368 Thus we must check for and handle r0+REG addresses here.
2369 We punt for now, since this is likely very rare. */
2370 gcc_assert (!REG_P (XEXP (inside, 1)));
2374 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
2376 return "mov.l %1,%0\n\tmov.l %1,%T0";
2381 /* Work out the safe way to copy. Copy into the second half first. */
2383 return "mov.l %T1,%T0\n\tmov.l %1,%0";
2386 return "mov.l %1,%0\n\tmov.l %T1,%T0";
2389 /* Print an instruction which would have gone into a delay slot after
2390 another instruction, but couldn't because the other instruction expanded
2391 into a sequence where putting the slot insn at the end wouldn't work. */
2394 print_slot (rtx insn)
2396 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 1, NULL);
2398 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
2402 output_far_jump (rtx insn, rtx op)
2404 struct { rtx lab, reg, op; } this_jmp;
2405 rtx braf_base_lab = NULL_RTX;
2408 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2411 this_jmp.lab = gen_label_rtx ();
2415 && offset - get_attr_length (insn) <= 32766)
2418 jump = "mov.w %O0,%1; braf %1";
2426 jump = "mov.l %O0,%1; braf %1";
2428 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
2431 jump = "mov.l %O0,%1; jmp @%1";
2433 /* If we have a scratch register available, use it. */
2434 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2435 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2437 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2438 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2439 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
2440 output_asm_insn (jump, &this_jmp.lab);
2441 if (dbr_sequence_length ())
2442 print_slot (final_sequence);
2444 output_asm_insn ("nop", 0);
2448 /* Output the delay slot insn first if any. */
2449 if (dbr_sequence_length ())
2450 print_slot (final_sequence);
2452 this_jmp.reg = gen_rtx_REG (SImode, 13);
2453 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2454 Fortunately, MACL is fixed and call-clobbered, and we never
2455 need its value across jumps, so save r13 in it instead of in
2458 output_asm_insn ("lds r13, macl", 0);
2460 output_asm_insn ("mov.l r13,@-r15", 0);
2461 output_asm_insn (jump, &this_jmp.lab);
2463 output_asm_insn ("sts macl, r13", 0);
2465 output_asm_insn ("mov.l @r15+,r13", 0);
2467 if (far && flag_pic && TARGET_SH2)
2469 braf_base_lab = gen_label_rtx ();
2470 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2471 CODE_LABEL_NUMBER (braf_base_lab));
2474 output_asm_insn (".align 2", 0);
2475 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2477 if (far && flag_pic)
2480 this_jmp.lab = braf_base_lab;
2481 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2484 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2488 /* Local label counter, used for constants in the pool and inside
2489 pattern branches. */
2491 static int lf = 100;
2493 /* Output code for ordinary branches. */
2496 output_branch (int logic, rtx insn, rtx *operands)
2498 switch (get_attr_length (insn))
2501 /* This can happen if filling the delay slot has caused a forward
2502 branch to exceed its range (we could reverse it, but only
2503 when we know we won't overextend other branches; this should
2504 best be handled by relaxation).
2505 It can also happen when other condbranches hoist delay slot insn
2506 from their destination, thus leading to code size increase.
2507 But the branch will still be in the range -4092..+4098 bytes. */
2512 /* The call to print_slot will clobber the operands. */
2513 rtx op0 = operands[0];
2515 /* If the instruction in the delay slot is annulled (true), then
2516 there is no delay slot where we can put it now. The only safe
2517 place for it is after the label. final will do that by default. */
2520 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
2521 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
2523 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2524 ASSEMBLER_DIALECT ? "/" : ".", label);
2525 print_slot (final_sequence);
2528 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2530 output_asm_insn ("bra\t%l0", &op0);
2531 fprintf (asm_out_file, "\tnop\n");
2532 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2536 /* When relaxing, handle this like a short branch. The linker
2537 will fix it up if it still doesn't fit after relaxation. */
2539 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2541 /* These are for SH2e, in which we have to account for the
2542 extra nop because of the hardware bug in annulled branches. */
2548 gcc_assert (!final_sequence
2549 || !(INSN_ANNULLED_BRANCH_P
2550 (XVECEXP (final_sequence, 0, 0))));
2551 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2553 ASSEMBLER_DIALECT ? "/" : ".", label);
2554 fprintf (asm_out_file, "\tnop\n");
2555 output_asm_insn ("bra\t%l0", operands);
2556 fprintf (asm_out_file, "\tnop\n");
2557 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2561 /* When relaxing, fall through. */
2566 sprintf (buffer, "b%s%ss\t%%l0",
2568 ASSEMBLER_DIALECT ? "/" : ".");
2569 output_asm_insn (buffer, &operands[0]);
2574 /* There should be no longer branches now - that would
2575 indicate that something has destroyed the branches set
2576 up in machine_dependent_reorg. */
2581 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2582 fill in operands 9 as a label to the successor insn.
2583 We try to use jump threading where possible.
2584 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2585 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2586 follow jmp and bt, if the address is in range. */
2588 output_branchy_insn (enum rtx_code code, const char *templ,
2589 rtx insn, rtx *operands)
2591 rtx next_insn = NEXT_INSN (insn);
2593 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2595 rtx src = SET_SRC (PATTERN (next_insn));
2596 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2598 /* Following branch not taken */
2599 operands[9] = gen_label_rtx ();
2600 emit_label_after (operands[9], next_insn);
2601 INSN_ADDRESSES_NEW (operands[9],
2602 INSN_ADDRESSES (INSN_UID (next_insn))
2603 + get_attr_length (next_insn));
2608 int offset = (branch_dest (next_insn)
2609 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2610 if (offset >= -252 && offset <= 258)
2612 if (GET_CODE (src) == IF_THEN_ELSE)
2614 src = XEXP (src, 1);
2620 operands[9] = gen_label_rtx ();
2621 emit_label_after (operands[9], insn);
2622 INSN_ADDRESSES_NEW (operands[9],
2623 INSN_ADDRESSES (INSN_UID (insn))
2624 + get_attr_length (insn));
2629 output_ieee_ccmpeq (rtx insn, rtx *operands)
2631 return output_branchy_insn (NE, "bt\t%l9\n\tfcmp/eq\t%1,%0",
2635 /* Output the start of the assembler file. */
2638 sh_file_start (void)
2640 default_file_start ();
2643 /* Declare the .directive section before it is used. */
2644 fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
2645 fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
2649 /* We need to show the text section with the proper
2650 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2651 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2652 will complain. We can teach GAS specifically about the
2653 default attributes for our choice of text section, but
2654 then we would have to change GAS again if/when we change
2655 the text section name. */
2656 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2658 /* Switch to the data section so that the coffsem symbol
2659 isn't in the text section. */
2660 switch_to_section (data_section);
2662 if (TARGET_LITTLE_ENDIAN)
2663 fputs ("\t.little\n", asm_out_file);
2667 if (TARGET_SHCOMPACT)
2668 fputs ("\t.mode\tSHcompact\n", asm_out_file);
2669 else if (TARGET_SHMEDIA)
2670 fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2671 TARGET_SHMEDIA64 ? 64 : 32);
2675 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2678 unspec_caller_rtx_p (rtx pat)
2683 split_const (pat, &base, &offset);
2684 if (GET_CODE (base) == UNSPEC)
2686 if (XINT (base, 1) == UNSPEC_CALLER)
2688 for (i = 0; i < XVECLEN (base, 0); i++)
2689 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2695 /* Indicate that INSN cannot be duplicated. This is true for insn
2696 that generates a unique label. */
2699 sh_cannot_copy_insn_p (rtx insn)
2703 if (!reload_completed || !flag_pic)
2706 if (!NONJUMP_INSN_P (insn))
2708 if (asm_noperands (insn) >= 0)
2711 pat = PATTERN (insn);
2712 if (GET_CODE (pat) != SET)
2714 pat = SET_SRC (pat);
2716 if (unspec_caller_rtx_p (pat))
2722 /* Actual number of instructions used to make a shift by N. */
2723 static const char ashiftrt_insns[] =
2724 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2726 /* Left shift and logical right shift are the same. */
2727 static const char shift_insns[] =
2728 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2730 /* Individual shift amounts needed to get the above length sequences.
2731 One bit right shifts clobber the T bit, so when possible, put one bit
2732 shifts in the middle of the sequence, so the ends are eligible for
2733 branch delay slots. */
2734 static const short shift_amounts[32][5] = {
2735 {0}, {1}, {2}, {2, 1},
2736 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
2737 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2738 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
2739 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2740 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2741 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2742 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2744 /* Likewise, but for shift amounts < 16, up to three highmost bits
2745 might be clobbered. This is typically used when combined with some
2746 kind of sign or zero extension. */
2748 static const char ext_shift_insns[] =
2749 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
2751 static const short ext_shift_amounts[32][4] = {
2752 {0}, {1}, {2}, {2, 1},
2753 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
2754 {8}, {8, 1}, {8, 2}, {8, 1, 2},
2755 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
2756 {16}, {16, 1}, {16, 2}, {16, 1, 2},
2757 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
2758 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
2759 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
2761 /* Assuming we have a value that has been sign-extended by at least one bit,
2762 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
2763 to shift it by N without data loss, and quicker than by other means? */
2764 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
2766 /* This is used in length attributes in sh.md to help compute the length
2767 of arbitrary constant shift instructions. */
2770 shift_insns_rtx (rtx insn)
2772 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2773 int shift_count = INTVAL (XEXP (set_src, 1)) & 31;
2774 enum rtx_code shift_code = GET_CODE (set_src);
2779 return ashiftrt_insns[shift_count];
2782 return shift_insns[shift_count];
2788 /* Return the cost of a shift. */
2798 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
2800 if (GET_MODE (x) == DImode
2801 && CONST_INT_P (XEXP (x, 1))
2802 && INTVAL (XEXP (x, 1)) == 1)
2805 /* Everything else is invalid, because there is no pattern for it. */
2808 /* If shift by a non constant, then this will be expensive. */
2809 if (!CONST_INT_P (XEXP (x, 1)))
2810 return SH_DYNAMIC_SHIFT_COST;
2812 /* Otherwise, return the true cost in instructions. Cope with out of range
2813 shift counts more or less arbitrarily. */
2814 value = INTVAL (XEXP (x, 1)) & 31;
2816 if (GET_CODE (x) == ASHIFTRT)
2818 int cost = ashiftrt_insns[value];
2819 /* If SH3, then we put the constant in a reg and use shad. */
2820 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
2821 cost = 1 + SH_DYNAMIC_SHIFT_COST;
2825 return shift_insns[value];
2828 /* Return the cost of an AND operation. */
2835 /* Anding with a register is a single cycle and instruction. */
2836 if (!CONST_INT_P (XEXP (x, 1)))
2839 i = INTVAL (XEXP (x, 1));
2843 if (satisfies_constraint_I10 (XEXP (x, 1))
2844 || satisfies_constraint_J16 (XEXP (x, 1)))
2847 return 1 + rtx_cost (XEXP (x, 1), AND, !optimize_size);
2850 /* These constants are single cycle extu.[bw] instructions. */
2851 if (i == 0xff || i == 0xffff)
2853 /* Constants that can be used in an and immediate instruction in a single
2854 cycle, but this requires r0, so make it a little more expensive. */
2855 if (CONST_OK_FOR_K08 (i))
2857 /* Constants that can be loaded with a mov immediate and an and.
2858 This case is probably unnecessary. */
2859 if (CONST_OK_FOR_I08 (i))
2861 /* Any other constants requires a 2 cycle pc-relative load plus an and.
2862 This case is probably unnecessary. */
2866 /* Return the cost of an addition or a subtraction. */
2871 /* Adding a register is a single cycle insn. */
2872 if (REG_P (XEXP (x, 1))
2873 || GET_CODE (XEXP (x, 1)) == SUBREG)
2876 /* Likewise for small constants. */
2877 if (CONST_INT_P (XEXP (x, 1))
2878 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
2882 switch (GET_CODE (XEXP (x, 1)))
2887 return TARGET_SHMEDIA64 ? 5 : 3;
2890 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1))))
2892 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16))
2894 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
2902 /* Any other constant requires a 2 cycle pc-relative load plus an
2907 /* Return the cost of a multiply. */
2909 multcosts (rtx x ATTRIBUTE_UNUSED)
2911 if (sh_multcost >= 0)
2914 /* ??? We have a mul insn, but it has a latency of three, and doesn't
2915 accept constants. Ideally, we would use a cost of one or two and
2916 add the cost of the operand, but disregard the latter when inside loops
2917 and loop invariant code motion is still to follow.
2918 Using a multiply first and splitting it later if it's a loss
2919 doesn't work because of different sign / zero extension semantics
2920 of multiplies vs. shifts. */
2921 return TARGET_SMALLCODE ? 2 : 3;
2925 /* We have a mul insn, so we can never take more than the mul and the
2926 read of the mac reg, but count more because of the latency and extra
2928 if (TARGET_SMALLCODE)
2933 /* If we're aiming at small code, then just count the number of
2934 insns in a multiply call sequence. */
2935 if (TARGET_SMALLCODE)
2938 /* Otherwise count all the insns in the routine we'd be calling too. */
2942 /* Compute a (partial) cost for rtx X. Return true if the complete
2943 cost has been computed, and false if subexpressions should be
2944 scanned. In either case, *TOTAL contains the cost result. */
2947 sh_rtx_costs (rtx x, int code, int outer_code, int *total,
2948 bool speed ATTRIBUTE_UNUSED)
2955 if (INTVAL (x) == 0)
2957 else if (outer_code == AND && and_operand ((x), DImode))
2959 else if ((outer_code == IOR || outer_code == XOR
2960 || outer_code == PLUS)
2961 && CONST_OK_FOR_I10 (INTVAL (x)))
2963 else if (CONST_OK_FOR_I16 (INTVAL (x)))
2964 *total = COSTS_N_INSNS (outer_code != SET);
2965 else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16))
2966 *total = COSTS_N_INSNS ((outer_code != SET) + 1);
2967 else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16))
2968 *total = COSTS_N_INSNS ((outer_code != SET) + 2);
2970 *total = COSTS_N_INSNS ((outer_code != SET) + 3);
2973 if (CONST_OK_FOR_I08 (INTVAL (x)))
2975 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
2976 && CONST_OK_FOR_K08 (INTVAL (x)))
2978 /* prepare_cmp_insn will force costly constants int registers before
2979 the cbranch[sd]i4 patterns can see them, so preserve potentially
2980 interesting ones not covered by I08 above. */
2981 else if (outer_code == COMPARE
2982 && ((unsigned HOST_WIDE_INT) INTVAL (x)
2983 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
2984 || INTVAL (x) == 0x7fffffff
2985 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
2994 if (TARGET_SHMEDIA64)
2995 *total = COSTS_N_INSNS (4);
2996 else if (TARGET_SHMEDIA32)
2997 *total = COSTS_N_INSNS (2);
3004 *total = COSTS_N_INSNS (4);
3005 /* prepare_cmp_insn will force costly constants int registers before
3006 the cbranchdi4 pattern can see them, so preserve potentially
3007 interesting ones. */
3008 else if (outer_code == COMPARE && GET_MODE (x) == DImode)
3014 if (x == CONST0_RTX (GET_MODE (x)))
3016 else if (sh_1el_vec (x, VOIDmode))
3017 *total = outer_code != SET;
3018 if (sh_rep_vec (x, VOIDmode))
3019 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3020 + (outer_code != SET));
3021 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3026 *total = COSTS_N_INSNS (addsubcosts (x));
3030 *total = COSTS_N_INSNS (andcosts (x));
3034 *total = COSTS_N_INSNS (multcosts (x));
3040 *total = COSTS_N_INSNS (shiftcosts (x));
3047 *total = COSTS_N_INSNS (20);
3051 if (sh_1el_vec (x, VOIDmode))
3052 *total = outer_code != SET;
3053 if (sh_rep_vec (x, VOIDmode))
3054 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3055 + (outer_code != SET));
3056 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3069 /* Compute the cost of an address. For the SH, all valid addresses are
3070 the same cost. Use a slightly higher cost for reg + reg addressing,
3071 since it increases pressure on r0. */
3074 sh_address_cost (rtx X,
3075 bool speed ATTRIBUTE_UNUSED)
3077 return (GET_CODE (X) == PLUS
3078 && ! CONSTANT_P (XEXP (X, 1))
3079 && ! TARGET_SHMEDIA ? 1 : 0);
3082 /* Code to expand a shift. */
3085 gen_ashift (int type, int n, rtx reg)
3087 /* Negative values here come from the shift_amounts array. */
3100 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
3104 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
3106 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
3109 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
3114 /* Same for HImode */
3117 gen_ashift_hi (int type, int n, rtx reg)
3119 /* Negative values here come from the shift_amounts array. */
3133 /* We don't have HImode right shift operations because using the
3134 ordinary 32 bit shift instructions for that doesn't generate proper
3135 zero/sign extension.
3136 gen_ashift_hi is only called in contexts where we know that the
3137 sign extension works out correctly. */
3140 if (GET_CODE (reg) == SUBREG)
3142 offset = SUBREG_BYTE (reg);
3143 reg = SUBREG_REG (reg);
3145 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3149 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3154 /* Output RTL to split a constant shift into its component SH constant
3155 shift instructions. */
3158 gen_shifty_op (int code, rtx *operands)
3160 int value = INTVAL (operands[2]);
3163 /* Truncate the shift count in case it is out of bounds. */
3168 if (code == LSHIFTRT)
3170 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3171 emit_insn (gen_movt (operands[0]));
3174 else if (code == ASHIFT)
3176 /* There is a two instruction sequence for 31 bit left shifts,
3177 but it requires r0. */
3178 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3180 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3181 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3186 else if (value == 0)
3188 /* This can happen even when optimizing, if there were subregs before
3189 reload. Don't output a nop here, as this is never optimized away;
3190 use a no-op move instead. */
3191 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[0]));
3195 max = shift_insns[value];
3196 for (i = 0; i < max; i++)
3197 gen_ashift (code, shift_amounts[value][i], operands[0]);
3200 /* Same as above, but optimized for values where the topmost bits don't
3204 gen_shifty_hi_op (int code, rtx *operands)
3206 int value = INTVAL (operands[2]);
3208 void (*gen_fun) (int, int, rtx);
3210 /* This operation is used by and_shl for SImode values with a few
3211 high bits known to be cleared. */
3215 emit_insn (gen_nop ());
3219 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3222 max = ext_shift_insns[value];
3223 for (i = 0; i < max; i++)
3224 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3227 /* When shifting right, emit the shifts in reverse order, so that
3228 solitary negative values come first. */
3229 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
3230 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
3233 /* Output RTL for an arithmetic right shift. */
3235 /* ??? Rewrite to use super-optimizer sequences. */
3238 expand_ashiftrt (rtx *operands)
3246 if (!CONST_INT_P (operands[2]))
3248 rtx count = copy_to_mode_reg (SImode, operands[2]);
3249 emit_insn (gen_negsi2 (count, count));
3250 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3253 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3254 > 1 + SH_DYNAMIC_SHIFT_COST)
3257 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3258 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3262 if (!CONST_INT_P (operands[2]))
3265 value = INTVAL (operands[2]) & 31;
3269 /* If we are called from abs expansion, arrange things so that we
3270 we can use a single MT instruction that doesn't clobber the source,
3271 if LICM can hoist out the load of the constant zero. */
3272 if (currently_expanding_to_rtl)
3274 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3276 emit_insn (gen_mov_neg_si_t (operands[0]));
3279 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3282 else if (value >= 16 && value <= 19)
3284 wrk = gen_reg_rtx (SImode);
3285 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3288 gen_ashift (ASHIFTRT, 1, wrk);
3289 emit_move_insn (operands[0], wrk);
3292 /* Expand a short sequence inline, longer call a magic routine. */
3293 else if (value <= 5)
3295 wrk = gen_reg_rtx (SImode);
3296 emit_move_insn (wrk, operands[1]);
3298 gen_ashift (ASHIFTRT, 1, wrk);
3299 emit_move_insn (operands[0], wrk);
3303 wrk = gen_reg_rtx (Pmode);
3305 /* Load the value into an arg reg and call a helper. */
3306 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3307 sprintf (func, "__ashiftrt_r4_%d", value);
3308 function_symbol (wrk, func, SFUNC_STATIC);
3309 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
3310 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3315 sh_dynamicalize_shift_p (rtx count)
3317 return shift_insns[INTVAL (count) & 31] > 1 + SH_DYNAMIC_SHIFT_COST;
3320 /* Try to find a good way to implement the combiner pattern
3321 [(set (match_operand:SI 0 "register_operand" "r")
3322 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3323 (match_operand:SI 2 "const_int_operand" "n"))
3324 (match_operand:SI 3 "const_int_operand" "n"))) .
3325 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3326 return 0 for simple right / left or left/right shift combination.
3327 return 1 for a combination of shifts with zero_extend.
3328 return 2 for a combination of shifts with an AND that needs r0.
3329 return 3 for a combination of shifts with an AND that needs an extra
3330 scratch register, when the three highmost bits of the AND mask are clear.
3331 return 4 for a combination of shifts with an AND that needs an extra
3332 scratch register, when any of the three highmost bits of the AND mask
3334 If ATTRP is set, store an initial right shift width in ATTRP[0],
3335 and the instruction length in ATTRP[1] . These values are not valid
3337 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3338 shift_amounts for the last shift value that is to be used before the
3341 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3343 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3344 int left = INTVAL (left_rtx), right;
3346 int cost, best_cost = 10000;
3347 int best_right = 0, best_len = 0;
3351 if (left < 0 || left > 31)
3353 if (CONST_INT_P (mask_rtx))
3354 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3356 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3357 /* Can this be expressed as a right shift / left shift pair? */
3358 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3359 right = exact_log2 (lsb);
3360 mask2 = ~(mask + lsb - 1);
3361 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3362 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3364 best_cost = shift_insns[right] + shift_insns[right + left];
3365 /* mask has no trailing zeroes <==> ! right */
3366 else if (! right && mask2 == ~(lsb2 - 1))
3368 int late_right = exact_log2 (lsb2);
3369 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
3371 /* Try to use zero extend. */
3372 if (mask2 == ~(lsb2 - 1))
3376 for (width = 8; width <= 16; width += 8)
3378 /* Can we zero-extend right away? */
3379 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3382 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
3383 if (cost < best_cost)
3394 /* ??? Could try to put zero extend into initial right shift,
3395 or even shift a bit left before the right shift. */
3396 /* Determine value of first part of left shift, to get to the
3397 zero extend cut-off point. */
3398 first = width - exact_log2 (lsb2) + right;
3399 if (first >= 0 && right + left - first >= 0)
3401 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
3402 + ext_shift_insns[right + left - first];
3403 if (cost < best_cost)
3415 /* Try to use r0 AND pattern */
3416 for (i = 0; i <= 2; i++)
3420 if (! CONST_OK_FOR_K08 (mask >> i))
3422 cost = (i != 0) + 2 + ext_shift_insns[left + i];
3423 if (cost < best_cost)
3428 best_len = cost - 1;
3431 /* Try to use a scratch register to hold the AND operand. */
3432 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3433 for (i = 0; i <= 2; i++)
3437 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3438 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
3439 if (cost < best_cost)
3444 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
3450 attrp[0] = best_right;
3451 attrp[1] = best_len;
3456 /* This is used in length attributes of the unnamed instructions
3457 corresponding to shl_and_kind return values of 1 and 2. */
3459 shl_and_length (rtx insn)
3461 rtx set_src, left_rtx, mask_rtx;
3464 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3465 left_rtx = XEXP (XEXP (set_src, 0), 1);
3466 mask_rtx = XEXP (set_src, 1);
3467 shl_and_kind (left_rtx, mask_rtx, attributes);
3468 return attributes[1];
3471 /* This is used in length attribute of the and_shl_scratch instruction. */
3474 shl_and_scr_length (rtx insn)
3476 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3477 int len = shift_insns[INTVAL (XEXP (set_src, 1)) & 31];
3478 rtx op = XEXP (set_src, 0);
3479 len += shift_insns[INTVAL (XEXP (op, 1)) & 31] + 1;
3480 op = XEXP (XEXP (op, 0), 0);
3481 return len + shift_insns[INTVAL (XEXP (op, 1)) & 31];
3484 /* Generate rtl for instructions for which shl_and_kind advised a particular
3485 method of generating them, i.e. returned zero. */
3488 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
3491 unsigned HOST_WIDE_INT mask;
3492 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
3493 int right, total_shift;
3494 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
3496 right = attributes[0];
3497 total_shift = INTVAL (left_rtx) + right;
3498 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
3505 int first = attributes[2];
3510 emit_insn ((mask << right) <= 0xff
3511 ? gen_zero_extendqisi2 (dest,
3512 gen_lowpart (QImode, source))
3513 : gen_zero_extendhisi2 (dest,
3514 gen_lowpart (HImode, source)));
3518 emit_insn (gen_movsi (dest, source));
3522 operands[2] = GEN_INT (right);
3523 gen_shifty_hi_op (LSHIFTRT, operands);
3527 operands[2] = GEN_INT (first);
3528 gen_shifty_hi_op (ASHIFT, operands);
3529 total_shift -= first;
3533 emit_insn (mask <= 0xff
3534 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
3535 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3536 if (total_shift > 0)
3538 operands[2] = GEN_INT (total_shift);
3539 gen_shifty_hi_op (ASHIFT, operands);
3544 shift_gen_fun = gen_shifty_op;
3546 /* If the topmost bit that matters is set, set the topmost bits
3547 that don't matter. This way, we might be able to get a shorter
3549 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
3550 mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
3552 /* Don't expand fine-grained when combining, because that will
3553 make the pattern fail. */
3554 if (currently_expanding_to_rtl
3555 || reload_in_progress || reload_completed)
3559 /* Cases 3 and 4 should be handled by this split
3560 only while combining */
3561 gcc_assert (kind <= 2);
3564 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
3567 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
3572 operands[2] = GEN_INT (total_shift);
3573 shift_gen_fun (ASHIFT, operands);
3580 if (kind != 4 && total_shift < 16)
3582 neg = -ext_shift_amounts[total_shift][1];
3584 neg -= ext_shift_amounts[total_shift][2];
3588 emit_insn (gen_and_shl_scratch (dest, source,
3591 GEN_INT (total_shift + neg),
3593 emit_insn (gen_movsi (dest, dest));
3600 /* Try to find a good way to implement the combiner pattern
3601 [(set (match_operand:SI 0 "register_operand" "=r")
3602 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3603 (match_operand:SI 2 "const_int_operand" "n")
3604 (match_operand:SI 3 "const_int_operand" "n")
3606 (clobber (reg:SI T_REG))]
3607 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
3608 return 0 for simple left / right shift combination.
3609 return 1 for left shift / 8 bit sign extend / left shift.
3610 return 2 for left shift / 16 bit sign extend / left shift.
3611 return 3 for left shift / 8 bit sign extend / shift / sign extend.
3612 return 4 for left shift / 16 bit sign extend / shift / sign extend.
3613 return 5 for left shift / 16 bit sign extend / right shift
3614 return 6 for < 8 bit sign extend / left shift.
3615 return 7 for < 8 bit sign extend / left shift / single right shift.
3616 If COSTP is nonzero, assign the calculated cost to *COSTP. */
3619 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
3621 int left, size, insize, ext;
3622 int cost = 0, best_cost;
3625 left = INTVAL (left_rtx);
3626 size = INTVAL (size_rtx);
3627 insize = size - left;
3628 gcc_assert (insize > 0);
3629 /* Default to left / right shift. */
3631 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
3634 /* 16 bit shift / sign extend / 16 bit shift */
3635 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
3636 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
3637 below, by alternative 3 or something even better. */
3638 if (cost < best_cost)
3644 /* Try a plain sign extend between two shifts. */
3645 for (ext = 16; ext >= insize; ext -= 8)
3649 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
3650 if (cost < best_cost)
3652 kind = ext / (unsigned) 8;
3656 /* Check if we can do a sloppy shift with a final signed shift
3657 restoring the sign. */
3658 if (EXT_SHIFT_SIGNED (size - ext))
3659 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
3660 /* If not, maybe it's still cheaper to do the second shift sloppy,
3661 and do a final sign extend? */
3662 else if (size <= 16)
3663 cost = ext_shift_insns[ext - insize] + 1
3664 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
3667 if (cost < best_cost)
3669 kind = ext / (unsigned) 8 + 2;
3673 /* Check if we can sign extend in r0 */
3676 cost = 3 + shift_insns[left];
3677 if (cost < best_cost)
3682 /* Try the same with a final signed shift. */
3685 cost = 3 + ext_shift_insns[left + 1] + 1;
3686 if (cost < best_cost)
3695 /* Try to use a dynamic shift. */
3696 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
3697 if (cost < best_cost)
3708 /* Function to be used in the length attribute of the instructions
3709 implementing this pattern. */
3712 shl_sext_length (rtx insn)
3714 rtx set_src, left_rtx, size_rtx;
3717 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
3718 left_rtx = XEXP (XEXP (set_src, 0), 1);
3719 size_rtx = XEXP (set_src, 1);
3720 shl_sext_kind (left_rtx, size_rtx, &cost);
3724 /* Generate rtl for this pattern */
3727 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
3730 int left, size, insize, cost;
3733 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
3734 left = INTVAL (left_rtx);
3735 size = INTVAL (size_rtx);
3736 insize = size - left;
3744 int ext = kind & 1 ? 8 : 16;
3745 int shift2 = size - ext;
3747 /* Don't expand fine-grained when combining, because that will
3748 make the pattern fail. */
3749 if (! currently_expanding_to_rtl
3750 && ! reload_in_progress && ! reload_completed)
3752 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3753 emit_insn (gen_movsi (dest, source));
3757 emit_insn (gen_movsi (dest, source));
3761 operands[2] = GEN_INT (ext - insize);
3762 gen_shifty_hi_op (ASHIFT, operands);
3765 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3766 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3771 operands[2] = GEN_INT (shift2);
3772 gen_shifty_op (ASHIFT, operands);
3779 if (EXT_SHIFT_SIGNED (shift2))
3781 operands[2] = GEN_INT (shift2 + 1);
3782 gen_shifty_op (ASHIFT, operands);
3783 operands[2] = const1_rtx;
3784 gen_shifty_op (ASHIFTRT, operands);
3787 operands[2] = GEN_INT (shift2);
3788 gen_shifty_hi_op (ASHIFT, operands);
3792 operands[2] = GEN_INT (-shift2);
3793 gen_shifty_hi_op (LSHIFTRT, operands);
3795 emit_insn (size <= 8
3796 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
3797 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3804 if (! currently_expanding_to_rtl
3805 && ! reload_in_progress && ! reload_completed)
3806 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3810 operands[2] = GEN_INT (16 - insize);
3811 gen_shifty_hi_op (ASHIFT, operands);
3812 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
3814 /* Don't use gen_ashrsi3 because it generates new pseudos. */
3816 gen_ashift (ASHIFTRT, 1, dest);
3821 /* Don't expand fine-grained when combining, because that will
3822 make the pattern fail. */
3823 if (! currently_expanding_to_rtl
3824 && ! reload_in_progress && ! reload_completed)
3826 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
3827 emit_insn (gen_movsi (dest, source));
3830 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
3831 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
3832 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
3834 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
3835 gen_shifty_op (ASHIFT, operands);
3837 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
3845 /* Prefix a symbol_ref name with "datalabel". */
3848 gen_datalabel_ref (rtx sym)
3852 if (GET_CODE (sym) == LABEL_REF)
3853 return gen_rtx_CONST (GET_MODE (sym),
3854 gen_rtx_UNSPEC (GET_MODE (sym),
3858 gcc_assert (GET_CODE (sym) == SYMBOL_REF);
3860 str = XSTR (sym, 0);
3861 /* Share all SYMBOL_REF strings with the same value - that is important
3863 str = IDENTIFIER_POINTER (get_identifier (str));
3864 XSTR (sym, 0) = str;
3870 static alloc_pool label_ref_list_pool;
3872 typedef struct label_ref_list_d
3875 struct label_ref_list_d *next;
3876 } *label_ref_list_t;
3878 /* The SH cannot load a large constant into a register, constants have to
3879 come from a pc relative load. The reference of a pc relative load
3880 instruction must be less than 1k in front of the instruction. This
3881 means that we often have to dump a constant inside a function, and
3882 generate code to branch around it.
3884 It is important to minimize this, since the branches will slow things
3885 down and make things bigger.
3887 Worst case code looks like:
3905 We fix this by performing a scan before scheduling, which notices which
3906 instructions need to have their operands fetched from the constant table
3907 and builds the table.
3911 scan, find an instruction which needs a pcrel move. Look forward, find the
3912 last barrier which is within MAX_COUNT bytes of the requirement.
3913 If there isn't one, make one. Process all the instructions between
3914 the find and the barrier.
3916 In the above example, we can tell that L3 is within 1k of L1, so
3917 the first move can be shrunk from the 3 insn+constant sequence into
3918 just 1 insn, and the constant moved to L3 to make:
3929 Then the second move becomes the target for the shortening process. */
3933 rtx value; /* Value in table. */
3934 rtx label; /* Label of value. */
3935 label_ref_list_t wend; /* End of window. */
3936 enum machine_mode mode; /* Mode of value. */
3938 /* True if this constant is accessed as part of a post-increment
3939 sequence. Note that HImode constants are never accessed in this way. */
3940 bool part_of_sequence_p;
3943 /* The maximum number of constants that can fit into one pool, since
3944 constants in the range 0..510 are at least 2 bytes long, and in the
3945 range from there to 1018 at least 4 bytes. */
3947 #define MAX_POOL_SIZE 372
3948 static pool_node pool_vector[MAX_POOL_SIZE];
3949 static int pool_size;
3950 static rtx pool_window_label;
3951 static int pool_window_last;
3953 static int max_labelno_before_reorg;
3955 /* ??? If we need a constant in HImode which is the truncated value of a
3956 constant we need in SImode, we could combine the two entries thus saving
3957 two bytes. Is this common enough to be worth the effort of implementing
3960 /* ??? This stuff should be done at the same time that we shorten branches.
3961 As it is now, we must assume that all branches are the maximum size, and
3962 this causes us to almost always output constant pools sooner than
3965 /* Add a constant to the pool and return its label. */
3968 add_constant (rtx x, enum machine_mode mode, rtx last_value)
3972 label_ref_list_t ref, newref;
3974 /* First see if we've already got it. */
3975 for (i = 0; i < pool_size; i++)
3977 if (x->code == pool_vector[i].value->code
3978 && mode == pool_vector[i].mode)
3980 if (x->code == CODE_LABEL)
3982 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3985 if (rtx_equal_p (x, pool_vector[i].value))
3990 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
3992 new_rtx = gen_label_rtx ();
3993 LABEL_REFS (new_rtx) = pool_vector[i].label;
3994 pool_vector[i].label = lab = new_rtx;
3996 if (lab && pool_window_label)
3998 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
3999 newref->label = pool_window_label;
4000 ref = pool_vector[pool_window_last].wend;
4002 pool_vector[pool_window_last].wend = newref;
4005 pool_window_label = new_rtx;
4006 pool_window_last = i;
4012 /* Need a new one. */
4013 pool_vector[pool_size].value = x;
4014 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4017 pool_vector[pool_size - 1].part_of_sequence_p = true;
4020 lab = gen_label_rtx ();
4021 pool_vector[pool_size].mode = mode;
4022 pool_vector[pool_size].label = lab;
4023 pool_vector[pool_size].wend = NULL;
4024 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4025 if (lab && pool_window_label)
4027 newref = (label_ref_list_t) pool_alloc (label_ref_list_pool);
4028 newref->label = pool_window_label;
4029 ref = pool_vector[pool_window_last].wend;
4031 pool_vector[pool_window_last].wend = newref;
4034 pool_window_label = lab;
4035 pool_window_last = pool_size;
4040 /* Output the literal table. START, if nonzero, is the first instruction
4041 this table is needed for, and also indicates that there is at least one
4042 casesi_worker_2 instruction; We have to emit the operand3 labels from
4043 these insns at a 4-byte aligned position. BARRIER is the barrier
4044 after which we are to place the table. */
4047 dump_table (rtx start, rtx barrier)
4053 label_ref_list_t ref;
4056 /* Do two passes, first time dump out the HI sized constants. */
4058 for (i = 0; i < pool_size; i++)
4060 pool_node *p = &pool_vector[i];
4062 if (p->mode == HImode)
4066 scan = emit_insn_after (gen_align_2 (), scan);
4069 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4070 scan = emit_label_after (lab, scan);
4071 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4073 for (ref = p->wend; ref; ref = ref->next)
4076 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4079 else if (p->mode == DFmode)
4087 scan = emit_insn_after (gen_align_4 (), scan);
4089 for (; start != barrier; start = NEXT_INSN (start))
4090 if (NONJUMP_INSN_P (start)
4091 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4093 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4094 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4096 scan = emit_label_after (lab, scan);
4099 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4101 rtx align_insn = NULL_RTX;
4103 scan = emit_label_after (gen_label_rtx (), scan);
4104 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4107 for (i = 0; i < pool_size; i++)
4109 pool_node *p = &pool_vector[i];
4117 if (align_insn && !p->part_of_sequence_p)
4119 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4120 emit_label_before (lab, align_insn);
4121 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4123 for (ref = p->wend; ref; ref = ref->next)
4126 emit_insn_before (gen_consttable_window_end (lab),
4129 delete_insn (align_insn);
4130 align_insn = NULL_RTX;
4135 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4136 scan = emit_label_after (lab, scan);
4137 scan = emit_insn_after (gen_consttable_4 (p->value,
4139 need_align = ! need_align;
4145 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4150 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4151 scan = emit_label_after (lab, scan);
4152 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4159 if (p->mode != HImode)
4161 for (ref = p->wend; ref; ref = ref->next)
4164 scan = emit_insn_after (gen_consttable_window_end (lab),
4173 for (i = 0; i < pool_size; i++)
4175 pool_node *p = &pool_vector[i];
4186 scan = emit_label_after (gen_label_rtx (), scan);
4187 scan = emit_insn_after (gen_align_4 (), scan);
4189 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4190 scan = emit_label_after (lab, scan);
4191 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4199 scan = emit_label_after (gen_label_rtx (), scan);
4200 scan = emit_insn_after (gen_align_4 (), scan);
4202 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4203 scan = emit_label_after (lab, scan);
4204 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4211 if (p->mode != HImode)
4213 for (ref = p->wend; ref; ref = ref->next)
4216 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4221 scan = emit_insn_after (gen_consttable_end (), scan);
4222 scan = emit_barrier_after (scan);
4224 pool_window_label = NULL_RTX;
4225 pool_window_last = 0;
4228 /* Return nonzero if constant would be an ok source for a
4229 mov.w instead of a mov.l. */
4234 return (CONST_INT_P (src)
4235 && INTVAL (src) >= -32768
4236 && INTVAL (src) <= 32767);
4239 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4241 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4243 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4244 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4245 need to fix it if the input value is CONST_OK_FOR_I08. */
4248 broken_move (rtx insn)
4250 if (NONJUMP_INSN_P (insn))
4252 rtx pat = PATTERN (insn);
4253 if (GET_CODE (pat) == PARALLEL)
4254 pat = XVECEXP (pat, 0, 0);
4255 if (GET_CODE (pat) == SET
4256 /* We can load any 8-bit value if we don't care what the high
4257 order bits end up as. */
4258 && GET_MODE (SET_DEST (pat)) != QImode
4259 && (CONSTANT_P (SET_SRC (pat))
4260 /* Match mova_const. */
4261 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4262 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4263 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4265 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4266 && (fp_zero_operand (SET_SRC (pat))
4267 || fp_one_operand (SET_SRC (pat)))
4268 /* In general we don't know the current setting of fpscr, so disable fldi.
4269 There is an exception if this was a register-register move
4270 before reload - and hence it was ascertained that we have
4271 single precision setting - and in a post-reload optimization
4272 we changed this to do a constant load. In that case
4273 we don't have an r0 clobber, hence we must use fldi. */
4275 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4277 && REG_P (SET_DEST (pat))
4278 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4280 && GET_MODE (SET_DEST (pat)) == SImode
4281 && (satisfies_constraint_I20 (SET_SRC (pat))
4282 || satisfies_constraint_I28 (SET_SRC (pat))))
4283 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4293 return (NONJUMP_INSN_P (insn)
4294 && GET_CODE (PATTERN (insn)) == SET
4295 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4296 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4297 /* Don't match mova_const. */
4298 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4301 /* Fix up a mova from a switch that went out of range. */
4303 fixup_mova (rtx mova)
4305 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4308 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4309 INSN_CODE (mova) = -1;
4314 rtx lab = gen_label_rtx ();
4315 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4319 worker = NEXT_INSN (worker);
4321 && !LABEL_P (worker)
4322 && !JUMP_P (worker));
4323 } while (NOTE_P (worker)
4324 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4325 wpat = PATTERN (worker);
4326 wpat0 = XVECEXP (wpat, 0, 0);
4327 wpat1 = XVECEXP (wpat, 0, 1);
4328 wsrc = SET_SRC (wpat0);
4329 PATTERN (worker) = (gen_casesi_worker_2
4330 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4331 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4333 INSN_CODE (worker) = -1;
4334 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4335 base = gen_rtx_LABEL_REF (Pmode, lab);
4336 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4337 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4338 INSN_CODE (mova) = -1;
4342 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4343 *num_mova, and check if the new mova is not nested within the first one.
4344 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4345 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4347 untangle_mova (int *num_mova, rtx *first_mova, rtx new_mova)
4349 int n_addr = 0; /* Initialization to shut up spurious warning. */
4350 int f_target, n_target = 0; /* Likewise. */
4354 /* If NEW_MOVA has no address yet, it will be handled later. */
4355 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4358 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4359 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4360 if (n_addr > n_target || n_addr + 1022 < n_target)
4362 /* Change the mova into a load.
4363 broken_move will then return true for it. */
4364 fixup_mova (new_mova);
4370 *first_mova = new_mova;
4375 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4380 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4381 > n_target - n_addr)
4383 fixup_mova (*first_mova);
4388 fixup_mova (new_mova);
4393 /* Find the last barrier from insn FROM which is close enough to hold the
4394 constant pool. If we can't find one, then create one near the end of
4398 find_barrier (int num_mova, rtx mova, rtx from)
4407 int leading_mova = num_mova;
4408 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
4412 rtx last_got = NULL_RTX;
4413 rtx last_symoff = NULL_RTX;
4415 /* For HImode: range is 510, add 4 because pc counts from address of
4416 second instruction after this one, subtract 2 for the jump instruction
4417 that we may need to emit before the table, subtract 2 for the instruction
4418 that fills the jump delay slot (in very rare cases, reorg will take an
4419 instruction from after the constant pool or will leave the delay slot
4420 empty). This gives 510.
4421 For SImode: range is 1020, add 4 because pc counts from address of
4422 second instruction after this one, subtract 2 in case pc is 2 byte
4423 aligned, subtract 2 for the jump instruction that we may need to emit
4424 before the table, subtract 2 for the instruction that fills the jump
4425 delay slot. This gives 1018. */
4427 /* The branch will always be shortened now that the reference address for
4428 forward branches is the successor address, thus we need no longer make
4429 adjustments to the [sh]i_limit for -O0. */
4434 while (from && count_si < si_limit && count_hi < hi_limit)
4436 int inc = get_attr_length (from);
4439 /* If this is a label that existed at the time of the compute_alignments
4440 call, determine the alignment. N.B. When find_barrier recurses for
4441 an out-of-reach mova, we might see labels at the start of previously
4442 inserted constant tables. */
4444 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4447 new_align = 1 << label_to_alignment (from);
4448 else if (BARRIER_P (prev_nonnote_insn (from)))
4449 new_align = 1 << barrier_align (from);
4454 /* In case we are scanning a constant table because of recursion, check
4455 for explicit alignments. If the table is long, we might be forced
4456 to emit the new table in front of it; the length of the alignment
4457 might be the last straw. */
4458 else if (NONJUMP_INSN_P (from)
4459 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4460 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4461 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4462 /* When we find the end of a constant table, paste the new constant
4463 at the end. That is better than putting it in front because
4464 this way, we don't need extra alignment for adding a 4-byte-aligned
4465 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4466 else if (NONJUMP_INSN_P (from)
4467 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4468 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4471 if (BARRIER_P (from))
4475 found_barrier = from;
4477 /* If we are at the end of the function, or in front of an alignment
4478 instruction, we need not insert an extra alignment. We prefer
4479 this kind of barrier. */
4480 if (barrier_align (from) > 2)
4481 good_barrier = from;
4483 /* If we are at the end of a hot/cold block, dump the constants
4485 next = NEXT_INSN (from);
4488 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
4492 if (broken_move (from))
4495 enum machine_mode mode;
4497 pat = PATTERN (from);
4498 if (GET_CODE (pat) == PARALLEL)
4499 pat = XVECEXP (pat, 0, 0);
4500 src = SET_SRC (pat);
4501 dst = SET_DEST (pat);
4502 mode = GET_MODE (dst);
4504 /* GOT pcrelat setting comes in pair of
4507 instructions. (plus add r0,r12).
4508 Remember if we see one without the other. */
4509 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
4510 last_got = last_got ? NULL_RTX : from;
4511 else if (PIC_ADDR_P (src))
4512 last_got = last_got ? NULL_RTX : from;
4514 /* We must explicitly check the mode, because sometimes the
4515 front end will generate code to load unsigned constants into
4516 HImode targets without properly sign extending them. */
4518 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
4521 /* We put the short constants before the long constants, so
4522 we must count the length of short constants in the range
4523 for the long constants. */
4524 /* ??? This isn't optimal, but is easy to do. */
4529 /* We dump DF/DI constants before SF/SI ones, because
4530 the limit is the same, but the alignment requirements
4531 are higher. We may waste up to 4 additional bytes
4532 for alignment, and the DF/DI constant may have
4533 another SF/SI constant placed before it. */
4534 if (TARGET_SHCOMPACT
4536 && (mode == DFmode || mode == DImode))
4541 while (si_align > 2 && found_si + si_align - 2 > count_si)
4543 if (found_si > count_si)
4544 count_si = found_si;
4545 found_si += GET_MODE_SIZE (mode);
4547 si_limit -= GET_MODE_SIZE (mode);
4553 switch (untangle_mova (&num_mova, &mova, from))
4558 rtx src = SET_SRC (PATTERN (from));
4559 if (GET_CODE (src) == CONST
4560 && GET_CODE (XEXP (src, 0)) == UNSPEC
4561 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
4565 case 0: return find_barrier (0, 0, mova);
4570 = good_barrier ? good_barrier : found_barrier;
4574 if (found_si > count_si)
4575 count_si = found_si;
4577 else if (JUMP_TABLE_DATA_P (from))
4579 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
4581 && (prev_nonnote_insn (from)
4582 == XEXP (MOVA_LABELREF (mova), 0))))
4584 if (barrier_align (next_real_insn (from)) == align_jumps_log)
4586 /* We have just passed the barrier in front of the
4587 ADDR_DIFF_VEC, which is stored in found_barrier. Since
4588 the ADDR_DIFF_VEC is accessed as data, just like our pool
4589 constants, this is a good opportunity to accommodate what
4590 we have gathered so far.
4591 If we waited any longer, we could end up at a barrier in
4592 front of code, which gives worse cache usage for separated
4593 instruction / data caches. */
4594 good_barrier = found_barrier;
4599 rtx body = PATTERN (from);
4600 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
4603 /* For the SH1, we generate alignments even after jumps-around-jumps. */
4604 else if (JUMP_P (from)
4606 && ! TARGET_SMALLCODE)
4609 /* There is a possibility that a bf is transformed into a bf/s by the
4610 delay slot scheduler. */
4611 if (JUMP_P (from) && !JUMP_TABLE_DATA_P (from)
4612 && get_attr_type (from) == TYPE_CBRANCH
4613 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (from)))) != SEQUENCE)
4619 if (new_align > si_align)
4621 si_limit -= (count_si - 1) & (new_align - si_align);
4622 si_align = new_align;
4624 count_si = (count_si + new_align - 1) & -new_align;
4629 if (new_align > hi_align)
4631 hi_limit -= (count_hi - 1) & (new_align - hi_align);
4632 hi_align = new_align;
4634 count_hi = (count_hi + new_align - 1) & -new_align;
4636 from = NEXT_INSN (from);
4643 /* Try as we might, the leading mova is out of range. Change
4644 it into a load (which will become a pcload) and retry. */
4646 return find_barrier (0, 0, mova);
4650 /* Insert the constant pool table before the mova instruction,
4651 to prevent the mova label reference from going out of range. */
4653 good_barrier = found_barrier = barrier_before_mova;
4659 if (good_barrier && next_real_insn (found_barrier))
4660 found_barrier = good_barrier;
4664 /* We didn't find a barrier in time to dump our stuff,
4665 so we'll make one. */
4666 rtx label = gen_label_rtx ();
4668 /* Don't emit a constant table in the middle of insns for
4669 casesi_worker_2. This is a bit overkill but is enough
4670 because casesi_worker_2 wouldn't appear so frequently. */
4674 /* If we exceeded the range, then we must back up over the last
4675 instruction we looked at. Otherwise, we just need to undo the
4676 NEXT_INSN at the end of the loop. */
4677 if (PREV_INSN (from) != orig
4678 && (count_hi > hi_limit || count_si > si_limit))
4679 from = PREV_INSN (PREV_INSN (from));
4681 from = PREV_INSN (from);
4683 /* Don't emit a constant table int the middle of global pointer setting,
4684 since that that would move the addressing base GOT into another table.
4685 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
4686 in the pool anyway, so just move up the whole constant pool. */
4688 from = PREV_INSN (last_got);
4690 /* Don't insert the constant pool table at the position which
4691 may be the landing pad. */
4694 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
4695 from = PREV_INSN (from);
4697 /* Walk back to be just before any jump or label.
4698 Putting it before a label reduces the number of times the branch
4699 around the constant pool table will be hit. Putting it before
4700 a jump makes it more likely that the bra delay slot will be
4702 while (NOTE_P (from) || JUMP_P (from)
4704 from = PREV_INSN (from);
4706 from = emit_jump_insn_after (gen_jump (label), from);
4707 JUMP_LABEL (from) = label;
4708 LABEL_NUSES (label) = 1;
4709 found_barrier = emit_barrier_after (from);
4710 emit_label_after (label, found_barrier);
4713 return found_barrier;
4716 /* If the instruction INSN is implemented by a special function, and we can
4717 positively find the register that is used to call the sfunc, and this
4718 register is not used anywhere else in this instruction - except as the
4719 destination of a set, return this register; else, return 0. */
4721 sfunc_uses_reg (rtx insn)
4724 rtx pattern, part, reg_part, reg;
4726 if (!NONJUMP_INSN_P (insn))
4728 pattern = PATTERN (insn);
4729 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
4732 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4734 part = XVECEXP (pattern, 0, i);
4735 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
4740 reg = XEXP (reg_part, 0);
4741 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
4743 part = XVECEXP (pattern, 0, i);
4744 if (part == reg_part || GET_CODE (part) == CLOBBER)
4746 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
4747 && REG_P (SET_DEST (part)))
4748 ? SET_SRC (part) : part)))
4754 /* See if the only way in which INSN uses REG is by calling it, or by
4755 setting it while calling it. Set *SET to a SET rtx if the register
4759 noncall_uses_reg (rtx reg, rtx insn, rtx *set)
4765 reg2 = sfunc_uses_reg (insn);
4766 if (reg2 && REGNO (reg2) == REGNO (reg))
4768 pattern = single_set (insn);
4770 && REG_P (SET_DEST (pattern))
4771 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4777 /* We don't use rtx_equal_p because we don't care if the mode is
4779 pattern = single_set (insn);
4781 && REG_P (SET_DEST (pattern))
4782 && REGNO (reg) == REGNO (SET_DEST (pattern)))
4788 par = PATTERN (insn);
4789 if (GET_CODE (par) == PARALLEL)
4790 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
4792 part = XVECEXP (par, 0, i);
4793 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
4796 return reg_mentioned_p (reg, SET_SRC (pattern));
4802 pattern = PATTERN (insn);
4804 if (GET_CODE (pattern) == PARALLEL)
4808 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
4809 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
4811 pattern = XVECEXP (pattern, 0, 0);
4814 if (GET_CODE (pattern) == SET)
4816 if (reg_mentioned_p (reg, SET_DEST (pattern)))
4818 /* We don't use rtx_equal_p, because we don't care if the
4819 mode is different. */
4820 if (!REG_P (SET_DEST (pattern))
4821 || REGNO (reg) != REGNO (SET_DEST (pattern)))
4827 pattern = SET_SRC (pattern);
4830 if (GET_CODE (pattern) != CALL
4831 || !MEM_P (XEXP (pattern, 0))
4832 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
4838 /* Given a X, a pattern of an insn or a part of it, return a mask of used
4839 general registers. Bits 0..15 mean that the respective registers
4840 are used as inputs in the instruction. Bits 16..31 mean that the
4841 registers 0..15, respectively, are used as outputs, or are clobbered.
4842 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
4844 regs_used (rtx x, int is_dest)
4852 code = GET_CODE (x);
4857 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4858 << (REGNO (x) + is_dest));
4862 rtx y = SUBREG_REG (x);
4867 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
4869 subreg_regno_offset (REGNO (y),
4872 GET_MODE (x)) + is_dest));
4876 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
4878 /* If there was a return value, it must have been indicated with USE. */
4893 fmt = GET_RTX_FORMAT (code);
4895 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4900 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4901 used |= regs_used (XVECEXP (x, i, j), is_dest);
4903 else if (fmt[i] == 'e')
4904 used |= regs_used (XEXP (x, i), is_dest);
4909 /* Create an instruction that prevents redirection of a conditional branch
4910 to the destination of the JUMP with address ADDR.
4911 If the branch needs to be implemented as an indirect jump, try to find
4912 a scratch register for it.
4913 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
4914 If any preceding insn that doesn't fit into a delay slot is good enough,
4915 pass 1. Pass 2 if a definite blocking insn is needed.
4916 -1 is used internally to avoid deep recursion.
4917 If a blocking instruction is made or recognized, return it. */
4920 gen_block_redirect (rtx jump, int addr, int need_block)
4923 rtx prev = prev_nonnote_insn (jump);
4926 /* First, check if we already have an instruction that satisfies our need. */
4927 if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
4929 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
4931 if (GET_CODE (PATTERN (prev)) == USE
4932 || GET_CODE (PATTERN (prev)) == CLOBBER
4933 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
4935 else if ((need_block &= ~1) < 0)
4937 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
4940 if (GET_CODE (PATTERN (jump)) == RETURN)
4944 /* Reorg even does nasty things with return insns that cause branches
4945 to go out of range - see find_end_label and callers. */
4946 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
4948 /* We can't use JUMP_LABEL here because it might be undefined
4949 when not optimizing. */
4950 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
4951 /* If the branch is out of range, try to find a scratch register for it. */
4953 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
4957 /* Don't look for the stack pointer as a scratch register,
4958 it would cause trouble if an interrupt occurred. */
4959 unsigned attempt = 0x7fff, used;
4960 int jump_left = flag_expensive_optimizations + 1;
4962 /* It is likely that the most recent eligible instruction is wanted for
4963 the delay slot. Therefore, find out which registers it uses, and
4964 try to avoid using them. */
4966 for (scan = jump; (scan = PREV_INSN (scan)); )
4970 if (INSN_DELETED_P (scan))
4972 code = GET_CODE (scan);
4973 if (code == CODE_LABEL || code == JUMP_INSN)
4976 && GET_CODE (PATTERN (scan)) != USE
4977 && GET_CODE (PATTERN (scan)) != CLOBBER
4978 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
4980 attempt &= ~regs_used (PATTERN (scan), 0);
4984 for (used = dead = 0, scan = JUMP_LABEL (jump);
4985 (scan = NEXT_INSN (scan)); )
4989 if (INSN_DELETED_P (scan))
4991 code = GET_CODE (scan);
4994 used |= regs_used (PATTERN (scan), 0);
4995 if (code == CALL_INSN)
4996 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
4997 dead |= (used >> 16) & ~used;
5003 if (code == JUMP_INSN)
5005 if (jump_left-- && simplejump_p (scan))
5006 scan = JUMP_LABEL (scan);
5012 /* Mask out the stack pointer again, in case it was
5013 the only 'free' register we have found. */
5016 /* If the immediate destination is still in range, check for possible
5017 threading with a jump beyond the delay slot insn.
5018 Don't check if we are called recursively; the jump has been or will be
5019 checked in a different invocation then. */
5021 else if (optimize && need_block >= 0)
5023 rtx next = next_active_insn (next_active_insn (dest));
5024 if (next && JUMP_P (next)
5025 && GET_CODE (PATTERN (next)) == SET
5026 && recog_memoized (next) == CODE_FOR_jump_compact)
5028 dest = JUMP_LABEL (next);
5030 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5032 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5038 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5040 /* It would be nice if we could convert the jump into an indirect
5041 jump / far branch right now, and thus exposing all constituent
5042 instructions to further optimization. However, reorg uses
5043 simplejump_p to determine if there is an unconditional jump where
5044 it should try to schedule instructions from the target of the
5045 branch; simplejump_p fails for indirect jumps even if they have
5047 rtx insn = emit_insn_before (gen_indirect_jump_scratch
5048 (reg, GEN_INT (unspec_bbr_uid++)),
5050 /* ??? We would like this to have the scope of the jump, but that
5051 scope will change when a delay slot insn of an inner scope is added.
5052 Hence, after delay slot scheduling, we'll have to expect
5053 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5056 INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
5057 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5060 else if (need_block)
5061 /* We can't use JUMP_LABEL here because it might be undefined
5062 when not optimizing. */
5063 return emit_insn_before (gen_block_branch_redirect
5064 (GEN_INT (unspec_bbr_uid++)),
5069 #define CONDJUMP_MIN -252
5070 #define CONDJUMP_MAX 262
5073 /* A label (to be placed) in front of the jump
5074 that jumps to our ultimate destination. */
5076 /* Where we are going to insert it if we cannot move the jump any farther,
5077 or the jump itself if we have picked up an existing jump. */
5079 /* The ultimate destination. */
5081 struct far_branch *prev;
5082 /* If the branch has already been created, its address;
5083 else the address of its first prospective user. */
5087 static void gen_far_branch (struct far_branch *);
5088 enum mdep_reorg_phase_e mdep_reorg_phase;
5090 gen_far_branch (struct far_branch *bp)
5092 rtx insn = bp->insert_place;
5094 rtx label = gen_label_rtx ();
5097 emit_label_after (label, insn);
5100 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5101 LABEL_NUSES (bp->far_label)++;
5104 jump = emit_jump_insn_after (gen_return (), insn);
5105 /* Emit a barrier so that reorg knows that any following instructions
5106 are not reachable via a fall-through path.
5107 But don't do this when not optimizing, since we wouldn't suppress the
5108 alignment for the barrier then, and could end up with out-of-range
5109 pc-relative loads. */
5111 emit_barrier_after (jump);
5112 emit_label_after (bp->near_label, insn);
5113 JUMP_LABEL (jump) = bp->far_label;
5114 ok = invert_jump (insn, label, 1);
5117 /* If we are branching around a jump (rather than a return), prevent
5118 reorg from using an insn from the jump target as the delay slot insn -
5119 when reorg did this, it pessimized code (we rather hide the delay slot)
5120 and it could cause branches to go out of range. */
5123 (gen_stuff_delay_slot
5124 (GEN_INT (unspec_bbr_uid++),
5125 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5127 /* Prevent reorg from undoing our splits. */
5128 gen_block_redirect (jump, bp->address += 2, 2);
5131 /* Fix up ADDR_DIFF_VECs. */
5133 fixup_addr_diff_vecs (rtx first)
5137 for (insn = first; insn; insn = NEXT_INSN (insn))
5139 rtx vec_lab, pat, prev, prevpat, x, braf_label;
5142 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5144 pat = PATTERN (insn);
5145 vec_lab = XEXP (XEXP (pat, 0), 0);
5147 /* Search the matching casesi_jump_2. */
5148 for (prev = vec_lab; ; prev = PREV_INSN (prev))
5152 prevpat = PATTERN (prev);
5153 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5155 x = XVECEXP (prevpat, 0, 1);
5156 if (GET_CODE (x) != USE)
5159 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5162 /* FIXME: This is a bug in the optimizer, but it seems harmless
5163 to just avoid panicing. */
5167 /* Emit the reference label of the braf where it belongs, right after
5168 the casesi_jump_2 (i.e. braf). */
5169 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5170 emit_label_after (braf_label, prev);
5172 /* Fix up the ADDR_DIF_VEC to be relative
5173 to the reference address of the braf. */
5174 XEXP (XEXP (pat, 0), 0) = braf_label;
5178 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5179 a barrier. Return the base 2 logarithm of the desired alignment. */
5181 barrier_align (rtx barrier_or_label)
5183 rtx next = next_real_insn (barrier_or_label), pat, prev;
5184 int slot, credit, jump_to_next = 0;
5189 pat = PATTERN (next);
5191 if (GET_CODE (pat) == ADDR_DIFF_VEC)
5194 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5195 /* This is a barrier in front of a constant table. */
5198 prev = prev_real_insn (barrier_or_label);
5199 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
5201 pat = PATTERN (prev);
5202 /* If this is a very small table, we want to keep the alignment after
5203 the table to the minimum for proper code alignment. */
5204 return ((TARGET_SMALLCODE
5205 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5206 <= (unsigned) 1 << (CACHE_LOG - 2)))
5207 ? 1 << TARGET_SHMEDIA : align_jumps_log);
5210 if (TARGET_SMALLCODE)
5213 if (! TARGET_SH2 || ! optimize)
5214 return align_jumps_log;
5216 /* When fixing up pcloads, a constant table might be inserted just before
5217 the basic block that ends with the barrier. Thus, we can't trust the
5218 instruction lengths before that. */
5219 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5221 /* Check if there is an immediately preceding branch to the insn beyond
5222 the barrier. We must weight the cost of discarding useful information
5223 from the current cache line when executing this branch and there is
5224 an alignment, against that of fetching unneeded insn in front of the
5225 branch target when there is no alignment. */
5227 /* There are two delay_slot cases to consider. One is the simple case
5228 where the preceding branch is to the insn beyond the barrier (simple
5229 delay slot filling), and the other is where the preceding branch has
5230 a delay slot that is a duplicate of the insn after the barrier
5231 (fill_eager_delay_slots) and the branch is to the insn after the insn
5232 after the barrier. */
5234 /* PREV is presumed to be the JUMP_INSN for the barrier under
5235 investigation. Skip to the insn before it. */
5236 prev = prev_real_insn (prev);
5238 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5239 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5240 prev = prev_real_insn (prev))
5243 if (GET_CODE (PATTERN (prev)) == USE
5244 || GET_CODE (PATTERN (prev)) == CLOBBER)
5246 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
5248 prev = XVECEXP (PATTERN (prev), 0, 1);
5249 if (INSN_UID (prev) == INSN_UID (next))
5251 /* Delay slot was filled with insn at jump target. */
5258 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5260 credit -= get_attr_length (prev);
5264 && JUMP_LABEL (prev))
5268 || next_real_insn (JUMP_LABEL (prev)) == next
5269 /* If relax_delay_slots() decides NEXT was redundant
5270 with some previous instruction, it will have
5271 redirected PREV's jump to the following insn. */
5272 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5273 /* There is no upper bound on redundant instructions
5274 that might have been skipped, but we must not put an
5275 alignment where none had been before. */
5276 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5278 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5279 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5280 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5282 rtx pat = PATTERN (prev);
5283 if (GET_CODE (pat) == PARALLEL)
5284 pat = XVECEXP (pat, 0, 0);
5285 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5291 return align_jumps_log;
5294 /* If we are inside a phony loop, almost any kind of label can turn up as the
5295 first one in the loop. Aligning a braf label causes incorrect switch
5296 destination addresses; we can detect braf labels because they are
5297 followed by a BARRIER.
5298 Applying loop alignment to small constant or switch tables is a waste
5299 of space, so we suppress this too. */
5301 sh_loop_align (rtx label)
5306 next = next_nonnote_insn (next);
5307 while (next && LABEL_P (next));
5311 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
5312 || recog_memoized (next) == CODE_FOR_consttable_2)
5315 return align_loops_log;
5318 /* Do a final pass over the function, just before delayed branch
5324 rtx first, insn, mova = NULL_RTX;
5326 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5327 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5329 first = get_insns ();
5330 max_labelno_before_reorg = max_label_num ();
5332 /* We must split call insns before introducing `mova's. If we're
5333 optimizing, they'll have already been split. Otherwise, make
5334 sure we don't split them too late. */
5336 split_all_insns_noflow ();
5341 /* If relaxing, generate pseudo-ops to associate function calls with
5342 the symbols they call. It does no harm to not generate these
5343 pseudo-ops. However, when we can generate them, it enables to
5344 linker to potentially relax the jsr to a bsr, and eliminate the
5345 register load and, possibly, the constant pool entry. */
5347 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5350 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5351 own purposes. This works because none of the remaining passes
5352 need to look at them.
5354 ??? But it may break in the future. We should use a machine
5355 dependent REG_NOTE, or some other approach entirely. */
5356 for (insn = first; insn; insn = NEXT_INSN (insn))
5362 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5364 remove_note (insn, note);
5368 for (insn = first; insn; insn = NEXT_INSN (insn))
5370 rtx pattern, reg, link, set, scan, dies, label;
5371 int rescan = 0, foundinsn = 0;
5375 pattern = PATTERN (insn);
5377 if (GET_CODE (pattern) == PARALLEL)
5378 pattern = XVECEXP (pattern, 0, 0);
5379 if (GET_CODE (pattern) == SET)
5380 pattern = SET_SRC (pattern);
5382 if (GET_CODE (pattern) != CALL
5383 || !MEM_P (XEXP (pattern, 0)))
5386 reg = XEXP (XEXP (pattern, 0), 0);
5390 reg = sfunc_uses_reg (insn);
5398 /* Try scanning backward to find where the register is set. */
5400 for (scan = PREV_INSN (insn);
5401 scan && !LABEL_P (scan);
5402 scan = PREV_INSN (scan))
5404 if (! INSN_P (scan))
5407 if (! reg_mentioned_p (reg, scan))
5410 if (noncall_uses_reg (reg, scan, &set))
5423 /* The register is set at LINK. */
5425 /* We can only optimize the function call if the register is
5426 being set to a symbol. In theory, we could sometimes
5427 optimize calls to a constant location, but the assembler
5428 and linker do not support that at present. */
5429 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5430 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5433 /* Scan forward from LINK to the place where REG dies, and
5434 make sure that the only insns which use REG are
5435 themselves function calls. */
5437 /* ??? This doesn't work for call targets that were allocated
5438 by reload, since there may not be a REG_DEAD note for the
5442 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5446 /* Don't try to trace forward past a CODE_LABEL if we haven't
5447 seen INSN yet. Ordinarily, we will only find the setting insn
5448 if it is in the same basic block. However,
5449 cross-jumping can insert code labels in between the load and
5450 the call, and can result in situations where a single call
5451 insn may have two targets depending on where we came from. */
5453 if (LABEL_P (scan) && ! foundinsn)
5456 if (! INSN_P (scan))
5459 /* Don't try to trace forward past a JUMP. To optimize
5460 safely, we would have to check that all the
5461 instructions at the jump destination did not use REG. */
5466 if (! reg_mentioned_p (reg, scan))
5469 if (noncall_uses_reg (reg, scan, &scanset))
5476 && (CALL_P (scan) || sfunc_uses_reg (scan)))
5478 /* There is a function call to this register other
5479 than the one we are checking. If we optimize
5480 this call, we need to rescan again below. */
5484 /* ??? We shouldn't have to worry about SCANSET here.
5485 We should just be able to check for a REG_DEAD note
5486 on a function call. However, the REG_DEAD notes are
5487 apparently not dependable around libcalls; c-torture
5488 execute/920501-2 is a test case. If SCANSET is set,
5489 then this insn sets the register, so it must have
5490 died earlier. Unfortunately, this will only handle
5491 the cases in which the register is, in fact, set in a
5494 /* ??? We shouldn't have to use FOUNDINSN here.
5495 This dates back to when we used LOG_LINKS to find
5496 the most recent insn which sets the register. */
5500 || find_reg_note (scan, REG_DEAD, reg)))
5509 /* Either there was a branch, or some insn used REG
5510 other than as a function call address. */
5514 /* Create a code label, and put it in a REG_LABEL_OPERAND note
5515 on the insn which sets the register, and on each call insn
5516 which uses the register. In final_prescan_insn we look for
5517 the REG_LABEL_OPERAND notes, and output the appropriate label
5520 label = gen_label_rtx ();
5521 add_reg_note (link, REG_LABEL_OPERAND, label);
5522 add_reg_note (insn, REG_LABEL_OPERAND, label);
5530 scan = NEXT_INSN (scan);
5533 && reg_mentioned_p (reg, scan))
5534 || ((reg2 = sfunc_uses_reg (scan))
5535 && REGNO (reg2) == REGNO (reg))))
5536 add_reg_note (scan, REG_LABEL_OPERAND, label);
5538 while (scan != dies);
5544 fixup_addr_diff_vecs (first);
5548 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
5549 shorten_branches (first);
5552 /* Scan the function looking for move instructions which have to be
5553 changed to pc-relative loads and insert the literal tables. */
5554 label_ref_list_pool = create_alloc_pool ("label references list",
5555 sizeof (struct label_ref_list_d),
5557 mdep_reorg_phase = SH_FIXUP_PCLOAD;
5558 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
5562 /* ??? basic block reordering can move a switch table dispatch
5563 below the switch table. Check if that has happened.
5564 We only have the addresses available when optimizing; but then,
5565 this check shouldn't be needed when not optimizing. */
5566 if (!untangle_mova (&num_mova, &mova, insn))
5572 else if (JUMP_P (insn)
5573 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
5575 /* ??? loop invariant motion can also move a mova out of a
5576 loop. Since loop does this code motion anyway, maybe we
5577 should wrap UNSPEC_MOVA into a CONST, so that reload can
5580 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
5581 || (prev_nonnote_insn (insn)
5582 == XEXP (MOVA_LABELREF (mova), 0))))
5589 /* Some code might have been inserted between the mova and
5590 its ADDR_DIFF_VEC. Check if the mova is still in range. */
5591 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
5592 total += get_attr_length (scan);
5594 /* range of mova is 1020, add 4 because pc counts from address of
5595 second instruction after this one, subtract 2 in case pc is 2
5596 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
5597 cancels out with alignment effects of the mova itself. */
5600 /* Change the mova into a load, and restart scanning
5601 there. broken_move will then return true for mova. */
5606 if (broken_move (insn)
5607 || (NONJUMP_INSN_P (insn)
5608 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
5611 /* Scan ahead looking for a barrier to stick the constant table
5613 rtx barrier = find_barrier (num_mova, mova, insn);
5614 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
5615 int need_aligned_label = 0;
5617 if (num_mova && ! mova_p (mova))
5619 /* find_barrier had to change the first mova into a
5620 pcload; thus, we have to start with this new pcload. */
5624 /* Now find all the moves between the points and modify them. */
5625 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
5629 if (NONJUMP_INSN_P (scan)
5630 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
5631 need_aligned_label = 1;
5632 if (broken_move (scan))
5634 rtx *patp = &PATTERN (scan), pat = *patp;
5638 enum machine_mode mode;
5640 if (GET_CODE (pat) == PARALLEL)
5641 patp = &XVECEXP (pat, 0, 0), pat = *patp;
5642 src = SET_SRC (pat);
5643 dst = SET_DEST (pat);
5644 mode = GET_MODE (dst);
5646 if (mode == SImode && hi_const (src)
5647 && REGNO (dst) != FPUL_REG)
5652 while (GET_CODE (dst) == SUBREG)
5654 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
5655 GET_MODE (SUBREG_REG (dst)),
5658 dst = SUBREG_REG (dst);
5660 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
5662 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
5664 /* This must be an insn that clobbers r0. */
5665 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
5666 XVECLEN (PATTERN (scan), 0)
5668 rtx clobber = *clobberp;
5670 gcc_assert (GET_CODE (clobber) == CLOBBER
5671 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
5674 && reg_set_between_p (r0_rtx, last_float_move, scan))
5678 && GET_MODE_SIZE (mode) != 4
5679 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
5681 lab = add_constant (src, mode, last_float);
5683 emit_insn_before (gen_mova (lab), scan);
5686 /* There will be a REG_UNUSED note for r0 on
5687 LAST_FLOAT_MOVE; we have to change it to REG_INC,
5688 lest reorg:mark_target_live_regs will not
5689 consider r0 to be used, and we end up with delay
5690 slot insn in front of SCAN that clobbers r0. */
5692 = find_regno_note (last_float_move, REG_UNUSED, 0);
5694 /* If we are not optimizing, then there may not be
5697 PUT_REG_NOTE_KIND (note, REG_INC);
5699 *last_float_addr = r0_inc_rtx;
5701 last_float_move = scan;
5703 newsrc = gen_const_mem (mode,
5704 (((TARGET_SH4 && ! TARGET_FMOVD)
5705 || REGNO (dst) == FPUL_REG)
5708 last_float_addr = &XEXP (newsrc, 0);
5710 /* Remove the clobber of r0. */
5711 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
5712 gen_rtx_SCRATCH (Pmode));
5714 /* This is a mova needing a label. Create it. */
5715 else if (GET_CODE (src) == UNSPEC
5716 && XINT (src, 1) == UNSPEC_MOVA
5717 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
5719 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
5720 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5721 newsrc = gen_rtx_UNSPEC (SImode,
5722 gen_rtvec (1, newsrc),
5727 lab = add_constant (src, mode, 0);
5728 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
5729 newsrc = gen_const_mem (mode, newsrc);
5731 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
5732 INSN_CODE (scan) = -1;
5735 dump_table (need_aligned_label ? insn : 0, barrier);
5739 free_alloc_pool (label_ref_list_pool);
5740 for (insn = first; insn; insn = NEXT_INSN (insn))
5741 PUT_MODE (insn, VOIDmode);
5743 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
5744 INSN_ADDRESSES_FREE ();
5745 split_branches (first);
5747 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
5748 also has an effect on the register that holds the address of the sfunc.
5749 Insert an extra dummy insn in front of each sfunc that pretends to
5750 use this register. */
5751 if (flag_delayed_branch)
5753 for (insn = first; insn; insn = NEXT_INSN (insn))
5755 rtx reg = sfunc_uses_reg (insn);
5759 emit_insn_before (gen_use_sfunc_addr (reg), insn);
5763 /* fpscr is not actually a user variable, but we pretend it is for the
5764 sake of the previous optimization passes, since we want it handled like
5765 one. However, we don't have any debugging information for it, so turn
5766 it into a non-user variable now. */
5768 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
5770 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
5774 get_dest_uid (rtx label, int max_uid)
5776 rtx dest = next_real_insn (label);
5779 /* This can happen for an undefined label. */
5781 dest_uid = INSN_UID (dest);
5782 /* If this is a newly created branch redirection blocking instruction,
5783 we cannot index the branch_uid or insn_addresses arrays with its
5784 uid. But then, we won't need to, because the actual destination is
5785 the following branch. */
5786 while (dest_uid >= max_uid)
5788 dest = NEXT_INSN (dest);
5789 dest_uid = INSN_UID (dest);
5791 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
5796 /* Split condbranches that are out of range. Also add clobbers for
5797 scratch registers that are needed in far jumps.
5798 We do this before delay slot scheduling, so that it can take our
5799 newly created instructions into account. It also allows us to
5800 find branches with common targets more easily. */
5803 split_branches (rtx first)
5806 struct far_branch **uid_branch, *far_branch_list = 0;
5807 int max_uid = get_max_uid ();
5810 /* Find out which branches are out of range. */
5811 shorten_branches (first);
5813 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
5814 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
5816 for (insn = first; insn; insn = NEXT_INSN (insn))
5817 if (! INSN_P (insn))
5819 else if (INSN_DELETED_P (insn))
5821 /* Shorten_branches would split this instruction again,
5822 so transform it into a note. */
5823 SET_INSN_DELETED (insn);
5825 else if (JUMP_P (insn)
5826 /* Don't mess with ADDR_DIFF_VEC */
5827 && (GET_CODE (PATTERN (insn)) == SET
5828 || GET_CODE (PATTERN (insn)) == RETURN))
5830 enum attr_type type = get_attr_type (insn);
5831 if (type == TYPE_CBRANCH)
5835 if (get_attr_length (insn) > 4)
5837 rtx src = SET_SRC (PATTERN (insn));
5838 rtx olabel = XEXP (XEXP (src, 1), 0);
5839 int addr = INSN_ADDRESSES (INSN_UID (insn));
5841 int dest_uid = get_dest_uid (olabel, max_uid);
5842 struct far_branch *bp = uid_branch[dest_uid];
5844 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
5845 the label if the LABEL_NUSES count drops to zero. There is
5846 always a jump_optimize pass that sets these values, but it
5847 proceeds to delete unreferenced code, and then if not
5848 optimizing, to un-delete the deleted instructions, thus
5849 leaving labels with too low uses counts. */
5852 JUMP_LABEL (insn) = olabel;
5853 LABEL_NUSES (olabel)++;
5857 bp = (struct far_branch *) alloca (sizeof *bp);
5858 uid_branch[dest_uid] = bp;
5859 bp->prev = far_branch_list;
5860 far_branch_list = bp;
5862 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
5863 LABEL_NUSES (bp->far_label)++;
5867 label = bp->near_label;
5868 if (! label && bp->address - addr >= CONDJUMP_MIN)
5870 rtx block = bp->insert_place;
5872 if (GET_CODE (PATTERN (block)) == RETURN)
5873 block = PREV_INSN (block);
5875 block = gen_block_redirect (block,
5877 label = emit_label_after (gen_label_rtx (),
5879 bp->near_label = label;
5881 else if (label && ! NEXT_INSN (label))
5883 if (addr + 2 - bp->address <= CONDJUMP_MAX)
5884 bp->insert_place = insn;
5886 gen_far_branch (bp);
5890 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
5892 bp->near_label = label = gen_label_rtx ();
5893 bp->insert_place = insn;
5896 ok = redirect_jump (insn, label, 0);
5901 /* get_attr_length (insn) == 2 */
5902 /* Check if we have a pattern where reorg wants to redirect
5903 the branch to a label from an unconditional branch that
5905 /* We can't use JUMP_LABEL here because it might be undefined
5906 when not optimizing. */
5907 /* A syntax error might cause beyond to be NULL_RTX. */
5909 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
5914 || ((beyond = next_active_insn (beyond))
5915 && JUMP_P (beyond)))
5916 && GET_CODE (PATTERN (beyond)) == SET
5917 && recog_memoized (beyond) == CODE_FOR_jump_compact
5919 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
5920 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5922 gen_block_redirect (beyond,
5923 INSN_ADDRESSES (INSN_UID (beyond)), 1);
5926 next = next_active_insn (insn);
5930 || ((next = next_active_insn (next))
5932 && GET_CODE (PATTERN (next)) == SET
5933 && recog_memoized (next) == CODE_FOR_jump_compact
5935 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
5936 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
5938 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
5940 else if (type == TYPE_JUMP || type == TYPE_RETURN)
5942 int addr = INSN_ADDRESSES (INSN_UID (insn));
5945 struct far_branch *bp;
5947 if (type == TYPE_JUMP)
5949 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
5950 dest_uid = get_dest_uid (far_label, max_uid);
5953 /* Parse errors can lead to labels outside
5955 if (! NEXT_INSN (far_label))
5960 JUMP_LABEL (insn) = far_label;
5961 LABEL_NUSES (far_label)++;
5963 redirect_jump (insn, NULL_RTX, 1);
5967 bp = uid_branch[dest_uid];
5970 bp = (struct far_branch *) alloca (sizeof *bp);
5971 uid_branch[dest_uid] = bp;
5972 bp->prev = far_branch_list;
5973 far_branch_list = bp;
5975 bp->far_label = far_label;
5977 LABEL_NUSES (far_label)++;
5979 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
5980 if (addr - bp->address <= CONDJUMP_MAX)
5981 emit_label_after (bp->near_label, PREV_INSN (insn));
5984 gen_far_branch (bp);
5990 bp->insert_place = insn;
5992 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
5994 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
5997 /* Generate all pending far branches,
5998 and free our references to the far labels. */
5999 while (far_branch_list)
6001 if (far_branch_list->near_label
6002 && ! NEXT_INSN (far_branch_list->near_label))
6003 gen_far_branch (far_branch_list);
6005 && far_branch_list->far_label
6006 && ! --LABEL_NUSES (far_branch_list->far_label))
6007 delete_insn (far_branch_list->far_label);
6008 far_branch_list = far_branch_list->prev;
6011 /* Instruction length information is no longer valid due to the new
6012 instructions that have been generated. */
6013 init_insn_lengths ();
6016 /* Dump out instruction addresses, which is useful for debugging the
6017 constant pool table stuff.
6019 If relaxing, output the label and pseudo-ops used to link together
6020 calls and the instruction which set the registers. */
6022 /* ??? The addresses printed by this routine for insns are nonsense for
6023 insns which are inside of a sequence where none of the inner insns have
6024 variable length. This is because the second pass of shorten_branches
6025 does not bother to update them. */
6028 final_prescan_insn (rtx insn, rtx *opvec ATTRIBUTE_UNUSED,
6029 int noperands ATTRIBUTE_UNUSED)
6031 if (TARGET_DUMPISIZE)
6032 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6038 note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX);
6043 pattern = PATTERN (insn);
6044 if (GET_CODE (pattern) == PARALLEL)
6045 pattern = XVECEXP (pattern, 0, 0);
6046 switch (GET_CODE (pattern))
6049 if (GET_CODE (SET_SRC (pattern)) != CALL
6050 && get_attr_type (insn) != TYPE_SFUNC)
6052 targetm.asm_out.internal_label
6053 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6056 /* else FALLTHROUGH */
6058 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6059 CODE_LABEL_NUMBER (XEXP (note, 0)));
6069 /* Dump out any constants accumulated in the final pass. These will
6073 output_jump_label_table (void)
6079 fprintf (asm_out_file, "\t.align 2\n");
6080 for (i = 0; i < pool_size; i++)
6082 pool_node *p = &pool_vector[i];
6084 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6085 CODE_LABEL_NUMBER (p->label));
6086 output_asm_insn (".long %O0", &p->value);
6094 /* A full frame looks like:
6098 [ if current_function_anonymous_args
6111 local-0 <- fp points here. */
6113 /* Number of bytes pushed for anonymous args, used to pass information
6114 between expand_prologue and expand_epilogue. */
6116 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6117 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6118 for an epilogue and a negative value means that it's for a sibcall
6119 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6120 all the registers that are about to be restored, and hence dead. */
6123 output_stack_adjust (int size, rtx reg, int epilogue_p,
6124 HARD_REG_SET *live_regs_mask, bool frame_p)
6126 rtx (*emit_fn) (rtx) = frame_p ? &frame_insn : &emit_insn;
6129 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6131 /* This test is bogus, as output_stack_adjust is used to re-align the
6134 gcc_assert (!(size % align));
6137 if (CONST_OK_FOR_ADD (size))
6138 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6139 /* Try to do it with two partial adjustments; however, we must make
6140 sure that the stack is properly aligned at all times, in case
6141 an interrupt occurs between the two partial adjustments. */
6142 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6143 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6145 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6146 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6152 int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
6155 /* If TEMP is invalid, we could temporarily save a general
6156 register to MACL. However, there is currently no need
6157 to handle this case, so just die when we see it. */
6159 || current_function_interrupt
6160 || ! call_really_used_regs[temp] || fixed_regs[temp])
6162 if (temp < 0 && ! current_function_interrupt
6163 && (TARGET_SHMEDIA || epilogue_p >= 0))
6166 COPY_HARD_REG_SET (temps, call_used_reg_set);
6167 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6171 if (crtl->return_rtx)
6173 enum machine_mode mode;
6174 mode = GET_MODE (crtl->return_rtx);
6175 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6176 nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
6178 for (i = 0; i < nreg; i++)
6179 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6180 if (crtl->calls_eh_return)
6182 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6183 for (i = 0; i <= 3; i++)
6184 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6187 if (TARGET_SHMEDIA && epilogue_p < 0)
6188 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
6189 CLEAR_HARD_REG_BIT (temps, i);
6190 if (epilogue_p <= 0)
6192 for (i = FIRST_PARM_REG;
6193 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6194 CLEAR_HARD_REG_BIT (temps, i);
6195 if (cfun->static_chain_decl != NULL)
6196 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6198 temp = scavenge_reg (&temps);
6200 if (temp < 0 && live_regs_mask)
6204 COPY_HARD_REG_SET (temps, *live_regs_mask);
6205 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6206 temp = scavenge_reg (&temps);
6210 rtx adj_reg, tmp_reg, mem;
6212 /* If we reached here, the most likely case is the (sibcall)
6213 epilogue for non SHmedia. Put a special push/pop sequence
6214 for such case as the last resort. This looks lengthy but
6215 would not be problem because it seems to be very
6218 gcc_assert (!TARGET_SHMEDIA && epilogue_p);
6221 /* ??? There is still the slight possibility that r4 or
6222 r5 have been reserved as fixed registers or assigned
6223 as global registers, and they change during an
6224 interrupt. There are possible ways to handle this:
6226 - If we are adjusting the frame pointer (r14), we can do
6227 with a single temp register and an ordinary push / pop
6229 - Grab any call-used or call-saved registers (i.e. not
6230 fixed or globals) for the temps we need. We might
6231 also grab r14 if we are adjusting the stack pointer.
6232 If we can't find enough available registers, issue
6233 a diagnostic and die - the user must have reserved
6234 way too many registers.
6235 But since all this is rather unlikely to happen and
6236 would require extra testing, we just die if r4 / r5
6237 are not available. */
6238 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6239 && !global_regs[4] && !global_regs[5]);
6241 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6242 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6243 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6244 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6245 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6246 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6247 emit_move_insn (mem, tmp_reg);
6248 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6249 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6250 emit_move_insn (mem, tmp_reg);
6251 emit_move_insn (reg, adj_reg);
6252 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6253 emit_move_insn (adj_reg, mem);
6254 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6255 emit_move_insn (tmp_reg, mem);
6256 /* Tell flow the insns that pop r4/r5 aren't dead. */
6261 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6263 /* If SIZE is negative, subtract the positive value.
6264 This sometimes allows a constant pool entry to be shared
6265 between prologue and epilogue code. */
6268 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6269 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6273 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6274 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6277 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6278 gen_rtx_SET (VOIDmode, reg,
6279 gen_rtx_PLUS (SImode, reg,
6289 RTX_FRAME_RELATED_P (x) = 1;
6293 /* Output RTL to push register RN onto the stack. */
6300 x = gen_push_fpul ();
6301 else if (rn == FPSCR_REG)
6302 x = gen_push_fpscr ();
6303 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6304 && FP_OR_XD_REGISTER_P (rn))
6306 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6308 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6310 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6311 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6313 x = gen_push (gen_rtx_REG (SImode, rn));
6316 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6320 /* Output RTL to pop register RN from the stack. */
6327 x = gen_pop_fpul ();
6328 else if (rn == FPSCR_REG)
6329 x = gen_pop_fpscr ();
6330 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && ! TARGET_FPU_SINGLE
6331 && FP_OR_XD_REGISTER_P (rn))
6333 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6335 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6337 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6338 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6340 x = gen_pop (gen_rtx_REG (SImode, rn));
6343 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6346 /* Generate code to push the regs specified in the mask. */
6349 push_regs (HARD_REG_SET *mask, int interrupt_handler)
6351 int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6354 /* Push PR last; this gives better latencies after the prologue, and
6355 candidates for the return delay slot when there are no general
6356 registers pushed. */
6357 for (; i < FIRST_PSEUDO_REGISTER; i++)
6359 /* If this is an interrupt handler, and the SZ bit varies,
6360 and we have to push any floating point register, we need
6361 to switch to the correct precision first. */
6362 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6363 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6365 HARD_REG_SET unsaved;
6368 COMPL_HARD_REG_SET (unsaved, *mask);
6369 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6373 && (i != FPSCR_REG || ! skip_fpscr)
6374 && TEST_HARD_REG_BIT (*mask, i))
6376 /* If the ISR has RESBANK attribute assigned, don't push any of
6377 the following registers - R0-R14, MACH, MACL and GBR. */
6378 if (! (sh_cfun_resbank_handler_p ()
6379 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6387 /* Push banked registers last to improve delay slot opportunities. */
6388 if (interrupt_handler)
6389 for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6390 if (TEST_HARD_REG_BIT (*mask, i))
6393 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6394 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6398 /* Calculate how much extra space is needed to save all callee-saved
6400 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6403 shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
6406 int stack_space = 0;
6407 int interrupt_handler = sh_cfun_interrupt_handler_p ();
6409 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6410 if ((! call_really_used_regs[reg] || interrupt_handler)
6411 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6412 /* Leave space to save this target register on the stack,
6413 in case target register allocation wants to use it. */
6414 stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6418 /* Decide whether we should reserve space for callee-save target registers,
6419 in case target register allocation wants to use them. REGS_SAVED is
6420 the space, in bytes, that is already required for register saves.
6421 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6424 shmedia_reserve_space_for_target_registers_p (int regs_saved,
6425 HARD_REG_SET *live_regs_mask)
6429 return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved;
6432 /* Decide how much space to reserve for callee-save target registers
6433 in case target register allocation wants to use them.
6434 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
6437 shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask)
6439 if (shmedia_space_reserved_for_target_registers)
6440 return shmedia_target_regs_stack_space (live_regs_mask);
6445 /* Work out the registers which need to be saved, both as a mask and a
6446 count of saved words. Return the count.
6448 If doing a pragma interrupt function, then push all regs used by the
6449 function, and if we call another function (we can tell by looking at PR),
6450 make sure that all the regs it clobbers are safe too. */
6453 calc_live_regs (HARD_REG_SET *live_regs_mask)
6458 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6459 bool nosave_low_regs;
6460 int pr_live, has_call;
6462 attrs = DECL_ATTRIBUTES (current_function_decl);
6463 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6464 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6465 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6466 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6468 CLEAR_HARD_REG_SET (*live_regs_mask);
6469 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
6470 && df_regs_ever_live_p (FPSCR_REG))
6471 target_flags &= ~MASK_FPU_SINGLE;
6472 /* If we can save a lot of saves by switching to double mode, do that. */
6473 else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
6474 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6475 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6476 && (! call_really_used_regs[reg]
6477 || interrupt_handler)
6480 target_flags &= ~MASK_FPU_SINGLE;
6483 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
6484 knows how to use it. That means the pseudo originally allocated for
6485 the initial value can become the PR_MEDIA_REG hard register, as seen for
6486 execute/20010122-1.c:test9. */
6488 /* ??? this function is called from initial_elimination_offset, hence we
6489 can't use the result of sh_media_register_for_return here. */
6490 pr_live = sh_pr_n_sets ();
6493 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
6494 pr_live = (pr_initial
6495 ? (!REG_P (pr_initial)
6496 || REGNO (pr_initial) != (PR_REG))
6497 : df_regs_ever_live_p (PR_REG));
6498 /* For Shcompact, if not optimizing, we end up with a memory reference
6499 using the return address pointer for __builtin_return_address even
6500 though there is no actual need to put the PR register on the stack. */
6501 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
6503 /* Force PR to be live if the prologue has to call the SHmedia
6504 argument decoder or register saver. */
6505 if (TARGET_SHCOMPACT
6506 && ((crtl->args.info.call_cookie
6507 & ~ CALL_COOKIE_RET_TRAMP (1))
6508 || crtl->saves_all_registers))
6510 has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
6511 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
6513 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
6516 ? (/* Need to save all the regs ever live. */
6517 (df_regs_ever_live_p (reg)
6518 || (call_really_used_regs[reg]
6519 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
6520 || reg == PIC_OFFSET_TABLE_REGNUM)
6522 || (TARGET_SHMEDIA && has_call
6523 && REGISTER_NATURAL_MODE (reg) == SImode
6524 && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
6525 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
6526 && reg != RETURN_ADDRESS_POINTER_REGNUM
6527 && reg != T_REG && reg != GBR_REG
6528 /* Push fpscr only on targets which have FPU */
6529 && (reg != FPSCR_REG || TARGET_FPU_ANY))
6530 : (/* Only push those regs which are used and need to be saved. */
6533 && crtl->args.info.call_cookie
6534 && reg == PIC_OFFSET_TABLE_REGNUM)
6535 || (df_regs_ever_live_p (reg)
6536 && ((!call_really_used_regs[reg]
6537 && !(reg != PIC_OFFSET_TABLE_REGNUM
6538 && fixed_regs[reg] && call_used_regs[reg]))
6539 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
6540 || (crtl->calls_eh_return
6541 && (reg == EH_RETURN_DATA_REGNO (0)
6542 || reg == EH_RETURN_DATA_REGNO (1)
6543 || reg == EH_RETURN_DATA_REGNO (2)
6544 || reg == EH_RETURN_DATA_REGNO (3)))
6545 || ((reg == MACL_REG || reg == MACH_REG)
6546 && df_regs_ever_live_p (reg)
6547 && sh_cfun_attr_renesas_p ())
6550 SET_HARD_REG_BIT (*live_regs_mask, reg);
6551 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6553 if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD
6554 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
6556 if (FP_REGISTER_P (reg))
6558 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
6560 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
6561 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
6564 else if (XD_REGISTER_P (reg))
6566 /* Must switch to double mode to access these registers. */
6567 target_flags &= ~MASK_FPU_SINGLE;
6571 if (nosave_low_regs && reg == R8_REG)
6574 /* If we have a target register optimization pass after prologue / epilogue
6575 threading, we need to assume all target registers will be live even if
6577 if (flag_branch_target_load_optimize2
6578 && TARGET_SAVE_ALL_TARGET_REGS
6579 && shmedia_space_reserved_for_target_registers)
6580 for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
6581 if ((! call_really_used_regs[reg] || interrupt_handler)
6582 && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
6584 SET_HARD_REG_BIT (*live_regs_mask, reg);
6585 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
6587 /* If this is an interrupt handler, we don't have any call-clobbered
6588 registers we can conveniently use for target register save/restore.
6589 Make sure we save at least one general purpose register when we need
6590 to save target registers. */
6591 if (interrupt_handler
6592 && hard_reg_set_intersect_p (*live_regs_mask,
6593 reg_class_contents[TARGET_REGS])
6594 && ! hard_reg_set_intersect_p (*live_regs_mask,
6595 reg_class_contents[GENERAL_REGS]))
6597 SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
6598 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
6604 /* Code to generate prologue and epilogue sequences */
6606 /* PUSHED is the number of bytes that are being pushed on the
6607 stack for register saves. Return the frame size, padded
6608 appropriately so that the stack stays properly aligned. */
6609 static HOST_WIDE_INT
6610 rounded_frame_size (int pushed)
6612 HOST_WIDE_INT size = get_frame_size ();
6613 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6615 if (ACCUMULATE_OUTGOING_ARGS)
6616 size += crtl->outgoing_args_size;
6618 return ((size + pushed + align - 1) & -align) - pushed;
6621 /* Choose a call-clobbered target-branch register that remains
6622 unchanged along the whole function. We set it up as the return
6623 value in the prologue. */
6625 sh_media_register_for_return (void)
6630 if (! current_function_is_leaf)
6632 if (lookup_attribute ("interrupt_handler",
6633 DECL_ATTRIBUTES (current_function_decl)))
6635 if (sh_cfun_interrupt_handler_p ())
6638 tr0_used = flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6640 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
6641 if (call_really_used_regs[regno] && ! df_regs_ever_live_p (regno))
6647 /* The maximum registers we need to save are:
6648 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
6649 - 32 floating point registers (for each pair, we save none,
6650 one single precision value, or a double precision value).
6651 - 8 target registers
6652 - add 1 entry for a delimiter. */
6653 #define MAX_SAVED_REGS (62+32+8)
6655 typedef struct save_entry_s
6664 /* There will be a delimiter entry with VOIDmode both at the start and the
6665 end of a filled in schedule. The end delimiter has the offset of the
6666 save with the smallest (i.e. most negative) offset. */
6667 typedef struct save_schedule_s
6669 save_entry entries[MAX_SAVED_REGS + 2];
6670 int temps[MAX_TEMPS+1];
6673 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
6674 use reverse order. Returns the last entry written to (not counting
6675 the delimiter). OFFSET_BASE is a number to be added to all offset
6679 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
6683 save_entry *entry = schedule->entries;
6687 if (! current_function_interrupt)
6688 for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
6689 if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
6690 && ! FUNCTION_ARG_REGNO_P (i)
6691 && i != FIRST_RET_REG
6692 && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM)
6693 && ! (crtl->calls_eh_return
6694 && (i == EH_RETURN_STACKADJ_REGNO
6695 || ((unsigned) i >= EH_RETURN_DATA_REGNO (0)
6696 && (unsigned) i <= EH_RETURN_DATA_REGNO (3)))))
6697 schedule->temps[tmpx++] = i;
6699 entry->mode = VOIDmode;
6700 entry->offset = offset_base;
6702 /* We loop twice: first, we save 8-byte aligned registers in the
6703 higher addresses, that are known to be aligned. Then, we
6704 proceed to saving 32-bit registers that don't need 8-byte
6706 If this is an interrupt function, all registers that need saving
6707 need to be saved in full. moreover, we need to postpone saving
6708 target registers till we have saved some general purpose registers
6709 we can then use as scratch registers. */
6710 offset = offset_base;
6711 for (align = 1; align >= 0; align--)
6713 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
6714 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6716 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
6719 if (current_function_interrupt)
6721 if (TARGET_REGISTER_P (i))
6723 if (GENERAL_REGISTER_P (i))
6726 if (mode == SFmode && (i % 2) == 1
6727 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
6728 && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
6735 /* If we're doing the aligned pass and this is not aligned,
6736 or we're doing the unaligned pass and this is aligned,
6738 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
6742 if (current_function_interrupt
6743 && GENERAL_REGISTER_P (i)
6744 && tmpx < MAX_TEMPS)
6745 schedule->temps[tmpx++] = i;
6747 offset -= GET_MODE_SIZE (mode);
6750 entry->offset = offset;
6753 if (align && current_function_interrupt)
6754 for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
6755 if (TEST_HARD_REG_BIT (*live_regs_mask, i))
6757 offset -= GET_MODE_SIZE (DImode);
6759 entry->mode = DImode;
6760 entry->offset = offset;
6765 entry->mode = VOIDmode;
6766 entry->offset = offset;
6767 schedule->temps[tmpx] = -1;
6772 sh_expand_prologue (void)
6774 HARD_REG_SET live_regs_mask;
6777 int save_flags = target_flags;
6780 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
6782 current_function_interrupt = sh_cfun_interrupt_handler_p ();
6784 /* We have pretend args if we had an object sent partially in registers
6785 and partially on the stack, e.g. a large structure. */
6786 pretend_args = crtl->args.pretend_args_size;
6787 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
6788 && (NPARM_REGS(SImode)
6789 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
6791 /* Dwarf2 module doesn't expect frame related insns here. */
6792 output_stack_adjust (-pretend_args
6793 - crtl->args.info.stack_regs * 8,
6794 stack_pointer_rtx, 0, NULL, false);
6796 if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie)
6797 /* We're going to use the PIC register to load the address of the
6798 incoming-argument decoder and/or of the return trampoline from
6799 the GOT, so make sure the PIC register is preserved and
6801 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
6803 if (TARGET_SHCOMPACT
6804 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
6808 /* First, make all registers with incoming arguments that will
6809 be pushed onto the stack live, so that register renaming
6810 doesn't overwrite them. */
6811 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
6812 if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie)
6813 >= NPARM_REGS (SImode) - reg)
6814 for (; reg < NPARM_REGS (SImode); reg++)
6815 emit_insn (gen_shcompact_preserve_incoming_args
6816 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6817 else if (CALL_COOKIE_INT_REG_GET
6818 (crtl->args.info.call_cookie, reg) == 1)
6819 emit_insn (gen_shcompact_preserve_incoming_args
6820 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
6822 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
6824 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
6825 GEN_INT (crtl->args.info.call_cookie));
6826 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
6827 gen_rtx_REG (SImode, R0_REG));
6829 else if (TARGET_SHMEDIA)
6831 int tr = sh_media_register_for_return ();
6834 emit_move_insn (gen_rtx_REG (DImode, tr),
6835 gen_rtx_REG (DImode, PR_MEDIA_REG));
6838 /* Emit the code for SETUP_VARARGS. */
6841 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
6843 /* Push arg regs as if they'd been provided by caller in stack. */
6844 for (i = 0; i < NPARM_REGS(SImode); i++)
6846 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
6849 if (i >= (NPARM_REGS(SImode)
6850 - crtl->args.info.arg_count[(int) SH_ARG_INT]
6858 /* If we're supposed to switch stacks at function entry, do so now. */
6862 /* The argument specifies a variable holding the address of the
6863 stack the interrupt function should switch to/from at entry/exit. */
6864 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
6866 = ggc_strdup (TREE_STRING_POINTER (arg));
6867 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
6869 lab = add_constant (sp_switch, SImode, 0);
6870 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6871 newsrc = gen_const_mem (SImode, newsrc);
6873 emit_insn (gen_sp_switch_1 (newsrc));
6876 d = calc_live_regs (&live_regs_mask);
6877 /* ??? Maybe we could save some switching if we can move a mode switch
6878 that already happens to be at the function start into the prologue. */
6879 if (target_flags != save_flags && ! current_function_interrupt)
6880 emit_insn (gen_toggle_sz ());
6884 int offset_base, offset;
6886 int offset_in_r0 = -1;
6888 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
6889 int total_size, save_size;
6890 save_schedule schedule;
6894 if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG]
6895 && ! current_function_interrupt)
6896 r0 = gen_rtx_REG (Pmode, R0_REG);
6898 /* D is the actual number of bytes that we need for saving registers,
6899 however, in initial_elimination_offset we have committed to using
6900 an additional TREGS_SPACE amount of bytes - in order to keep both
6901 addresses to arguments supplied by the caller and local variables
6902 valid, we must keep this gap. Place it between the incoming
6903 arguments and the actually saved registers in a bid to optimize
6904 locality of reference. */
6905 total_size = d + tregs_space;
6906 total_size += rounded_frame_size (total_size);
6907 save_size = total_size - rounded_frame_size (d);
6908 if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT))
6909 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
6910 - save_size % (STACK_BOUNDARY / BITS_PER_UNIT));
6912 /* If adjusting the stack in a single step costs nothing extra, do so.
6913 I.e. either if a single addi is enough, or we need a movi anyway,
6914 and we don't exceed the maximum offset range (the test for the
6915 latter is conservative for simplicity). */
6917 && (CONST_OK_FOR_I10 (-total_size)
6918 || (! CONST_OK_FOR_I10 (-(save_size + d_rounding))
6919 && total_size <= 2044)))
6920 d_rounding = total_size - save_size;
6922 offset_base = d + d_rounding;
6924 output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
6927 sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
6928 tmp_pnt = schedule.temps;
6929 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
6931 enum machine_mode mode = (enum machine_mode) entry->mode;
6932 unsigned int reg = entry->reg;
6933 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
6936 offset = entry->offset;
6938 reg_rtx = gen_rtx_REG (mode, reg);
6940 mem_rtx = gen_frame_mem (mode,
6941 gen_rtx_PLUS (Pmode,
6945 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
6951 if (HAVE_PRE_DECREMENT
6952 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
6953 || mem_rtx == NULL_RTX
6954 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
6956 pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0));
6958 if (!memory_address_p (mode, XEXP (pre_dec, 0)))
6963 offset += GET_MODE_SIZE (mode);
6967 if (mem_rtx != NULL_RTX)
6970 if (offset_in_r0 == -1)
6972 emit_move_insn (r0, GEN_INT (offset));
6973 offset_in_r0 = offset;
6975 else if (offset != offset_in_r0)
6980 GEN_INT (offset - offset_in_r0)));
6981 offset_in_r0 += offset - offset_in_r0;
6984 if (pre_dec != NULL_RTX)
6990 (Pmode, r0, stack_pointer_rtx));
6994 offset -= GET_MODE_SIZE (mode);
6995 offset_in_r0 -= GET_MODE_SIZE (mode);
7000 mem_rtx = gen_frame_mem (mode, r0);
7002 mem_rtx = gen_frame_mem (mode,
7003 gen_rtx_PLUS (Pmode,
7007 /* We must not use an r0-based address for target-branch
7008 registers or for special registers without pre-dec
7009 memory addresses, since we store their values in r0
7011 gcc_assert (!TARGET_REGISTER_P (reg)
7012 && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7013 || mem_rtx == pre_dec));
7016 orig_reg_rtx = reg_rtx;
7017 if (TARGET_REGISTER_P (reg)
7018 || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7019 && mem_rtx != pre_dec))
7021 rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
7023 emit_move_insn (tmp_reg, reg_rtx);
7025 if (REGNO (tmp_reg) == R0_REG)
7029 gcc_assert (!refers_to_regno_p
7030 (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0));
7033 if (*++tmp_pnt <= 0)
7034 tmp_pnt = schedule.temps;
7041 /* Mark as interesting for dwarf cfi generator */
7042 insn = emit_move_insn (mem_rtx, reg_rtx);
7043 RTX_FRAME_RELATED_P (insn) = 1;
7044 /* If we use an intermediate register for the save, we can't
7045 describe this exactly in cfi as a copy of the to-be-saved
7046 register into the temporary register and then the temporary
7047 register on the stack, because the temporary register can
7048 have a different natural size than the to-be-saved register.
7049 Thus, we gloss over the intermediate copy and pretend we do
7050 a direct save from the to-be-saved register. */
7051 if (REGNO (reg_rtx) != reg)
7055 set = gen_rtx_SET (VOIDmode, mem_rtx, orig_reg_rtx);
7056 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7059 if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
7061 rtx reg_rtx = gen_rtx_REG (mode, reg);
7063 rtx mem_rtx = gen_frame_mem (mode,
7064 gen_rtx_PLUS (Pmode,
7068 set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
7069 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
7074 gcc_assert (entry->offset == d_rounding);
7077 push_regs (&live_regs_mask, current_function_interrupt);
7079 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7080 emit_insn (gen_GOTaddr2picreg ());
7082 if (SHMEDIA_REGS_STACK_ADJUST ())
7084 /* This must NOT go through the PLT, otherwise mach and macl
7085 may be clobbered. */
7086 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7088 ? "__GCC_push_shmedia_regs"
7089 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT);
7090 emit_insn (gen_shmedia_save_restore_regs_compact
7091 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7094 if (target_flags != save_flags && ! current_function_interrupt)
7095 emit_insn (gen_toggle_sz ());
7097 target_flags = save_flags;
7099 output_stack_adjust (-rounded_frame_size (d) + d_rounding,
7100 stack_pointer_rtx, 0, NULL, true);
7102 if (frame_pointer_needed)
7103 frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7105 if (TARGET_SHCOMPACT
7106 && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
7108 /* This must NOT go through the PLT, otherwise mach and macl
7109 may be clobbered. */
7110 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7111 "__GCC_shcompact_incoming_args", SFUNC_GOT);
7112 emit_insn (gen_shcompact_incoming_args ());
7117 sh_expand_epilogue (bool sibcall_p)
7119 HARD_REG_SET live_regs_mask;
7123 int save_flags = target_flags;
7124 int frame_size, save_size;
7125 int fpscr_deferred = 0;
7126 int e = sibcall_p ? -1 : 1;
7128 d = calc_live_regs (&live_regs_mask);
7131 frame_size = rounded_frame_size (d);
7135 int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
7137 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
7138 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
7139 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
7141 total_size = d + tregs_space;
7142 total_size += rounded_frame_size (total_size);
7143 save_size = total_size - frame_size;
7145 /* If adjusting the stack in a single step costs nothing extra, do so.
7146 I.e. either if a single addi is enough, or we need a movi anyway,
7147 and we don't exceed the maximum offset range (the test for the
7148 latter is conservative for simplicity). */
7150 && ! frame_pointer_needed
7151 && (CONST_OK_FOR_I10 (total_size)
7152 || (! CONST_OK_FOR_I10 (save_size + d_rounding)
7153 && total_size <= 2044)))
7154 d_rounding = frame_size;
7156 frame_size -= d_rounding;
7159 if (frame_pointer_needed)
7161 /* We must avoid scheduling the epilogue with previous basic blocks.
7162 See PR/18032 and PR/40313. */
7163 emit_insn (gen_blockage ());
7164 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7165 &live_regs_mask, false);
7167 /* We must avoid moving the stack pointer adjustment past code
7168 which reads from the local frame, else an interrupt could
7169 occur after the SP adjustment and clobber data in the local
7171 emit_insn (gen_blockage ());
7172 emit_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7174 else if (frame_size)
7176 /* We must avoid moving the stack pointer adjustment past code
7177 which reads from the local frame, else an interrupt could
7178 occur after the SP adjustment and clobber data in the local
7180 emit_insn (gen_blockage ());
7181 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7182 &live_regs_mask, false);
7185 if (SHMEDIA_REGS_STACK_ADJUST ())
7187 function_symbol (gen_rtx_REG (Pmode, R0_REG),
7189 ? "__GCC_pop_shmedia_regs"
7190 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT);
7191 /* This must NOT go through the PLT, otherwise mach and macl
7192 may be clobbered. */
7193 emit_insn (gen_shmedia_save_restore_regs_compact
7194 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7197 /* Pop all the registers. */
7199 if (target_flags != save_flags && ! current_function_interrupt)
7200 emit_insn (gen_toggle_sz ());
7203 int offset_base, offset;
7204 int offset_in_r0 = -1;
7206 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
7207 save_schedule schedule;
7211 entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
7212 offset_base = -entry[1].offset + d_rounding;
7213 tmp_pnt = schedule.temps;
7214 for (; entry->mode != VOIDmode; entry--)
7216 enum machine_mode mode = (enum machine_mode) entry->mode;
7217 int reg = entry->reg;
7218 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
7220 offset = offset_base + entry->offset;
7221 reg_rtx = gen_rtx_REG (mode, reg);
7223 mem_rtx = gen_frame_mem (mode,
7224 gen_rtx_PLUS (Pmode,
7228 if (!memory_address_p (mode, XEXP (mem_rtx, 0)))
7231 if (HAVE_POST_INCREMENT
7232 && (offset == offset_in_r0
7233 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
7234 && mem_rtx == NULL_RTX)
7235 || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
7237 post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0));
7239 if (!memory_address_p (mode, XEXP (post_inc, 0)))
7240 post_inc = NULL_RTX;
7245 if (mem_rtx != NULL_RTX)
7248 if (offset_in_r0 == -1)
7250 emit_move_insn (r0, GEN_INT (offset));
7251 offset_in_r0 = offset;
7253 else if (offset != offset_in_r0)
7258 GEN_INT (offset - offset_in_r0)));
7259 offset_in_r0 += offset - offset_in_r0;
7262 if (post_inc != NULL_RTX)
7268 (Pmode, r0, stack_pointer_rtx));
7274 offset_in_r0 += GET_MODE_SIZE (mode);
7277 mem_rtx = gen_frame_mem (mode, r0);
7279 mem_rtx = gen_frame_mem (mode,
7280 gen_rtx_PLUS (Pmode,
7284 gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg))
7285 || mem_rtx == post_inc);
7288 if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
7289 && mem_rtx != post_inc)
7291 insn = emit_move_insn (r0, mem_rtx);
7294 else if (TARGET_REGISTER_P (reg))
7296 rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
7298 /* Give the scheduler a bit of freedom by using up to
7299 MAX_TEMPS registers in a round-robin fashion. */
7300 insn = emit_move_insn (tmp_reg, mem_rtx);
7303 tmp_pnt = schedule.temps;
7306 insn = emit_move_insn (reg_rtx, mem_rtx);
7309 gcc_assert (entry->offset + offset_base == d + d_rounding);
7311 else /* ! TARGET_SH5 */
7316 /* For an ISR with RESBANK attribute assigned, don't pop PR
7318 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7319 && !sh_cfun_resbank_handler_p ())
7321 if (!frame_pointer_needed)
7322 emit_insn (gen_blockage ());
7326 /* Banked registers are popped first to avoid being scheduled in the
7327 delay slot. RTE switches banks before the ds instruction. */
7328 if (current_function_interrupt)
7330 for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7331 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7334 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7337 last_reg = FIRST_PSEUDO_REGISTER;
7339 for (i = 0; i < last_reg; i++)
7341 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7343 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7344 && hard_reg_set_intersect_p (live_regs_mask,
7345 reg_class_contents[DF_REGS]))
7347 /* For an ISR with RESBANK attribute assigned, don't pop
7348 following registers, R0-R14, MACH, MACL and GBR. */
7349 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7350 && ! (sh_cfun_resbank_handler_p ()
7351 && ((j >= FIRST_GENERAL_REG
7352 && j < LAST_GENERAL_REG)
7358 if (j == FIRST_FP_REG && fpscr_deferred)
7362 if (target_flags != save_flags && ! current_function_interrupt)
7363 emit_insn (gen_toggle_sz ());
7364 target_flags = save_flags;
7366 output_stack_adjust (crtl->args.pretend_args_size
7367 + save_size + d_rounding
7368 + crtl->args.info.stack_regs * 8,
7369 stack_pointer_rtx, e, NULL, false);
7371 if (crtl->calls_eh_return)
7372 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7373 EH_RETURN_STACKADJ_RTX));
7375 /* Switch back to the normal stack if necessary. */
7376 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7377 emit_insn (gen_sp_switch_2 ());
7379 /* Tell flow the insn that pops PR isn't dead. */
7380 /* PR_REG will never be live in SHmedia mode, and we don't need to
7381 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
7382 by the return pattern. */
7383 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7384 emit_use (gen_rtx_REG (SImode, PR_REG));
7387 static int sh_need_epilogue_known = 0;
7390 sh_need_epilogue (void)
7392 if (! sh_need_epilogue_known)
7397 sh_expand_epilogue (0);
7398 epilogue = get_insns ();
7400 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
7402 return sh_need_epilogue_known > 0;
7405 /* Emit code to change the current function's return address to RA.
7406 TEMP is available as a scratch register, if needed. */
7409 sh_set_return_address (rtx ra, rtx tmp)
7411 HARD_REG_SET live_regs_mask;
7413 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
7416 d = calc_live_regs (&live_regs_mask);
7418 /* If pr_reg isn't life, we can set it (or the register given in
7419 sh_media_register_for_return) directly. */
7420 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
7426 int rr_regno = sh_media_register_for_return ();
7431 rr = gen_rtx_REG (DImode, rr_regno);
7434 rr = gen_rtx_REG (SImode, pr_reg);
7436 emit_insn (GEN_MOV (rr, ra));
7437 /* Tell flow the register for return isn't dead. */
7445 save_schedule schedule;
7448 entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
7449 offset = entry[1].offset;
7450 for (; entry->mode != VOIDmode; entry--)
7451 if (entry->reg == pr_reg)
7454 /* We can't find pr register. */
7458 offset = entry->offset - offset;
7459 pr_offset = (rounded_frame_size (d) + offset
7460 + SHMEDIA_REGS_STACK_ADJUST ());
7463 pr_offset = rounded_frame_size (d);
7465 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7467 if (frame_pointer_needed)
7468 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7470 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7472 tmp = gen_frame_mem (Pmode, tmp);
7473 emit_insn (GEN_MOV (tmp, ra));
7474 /* Tell this store isn't dead. */
7478 /* Clear variables at function end. */
7481 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7482 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7484 sh_need_epilogue_known = 0;
7488 sh_builtin_saveregs (void)
7490 /* First unnamed integer register. */
7491 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7492 /* Number of integer registers we need to save. */
7493 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7494 /* First unnamed SFmode float reg */
7495 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7496 /* Number of SFmode float regs to save. */
7497 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7500 alias_set_type alias_set;
7506 int pushregs = n_intregs;
7508 while (pushregs < NPARM_REGS (SImode) - 1
7509 && (CALL_COOKIE_INT_REG_GET
7510 (crtl->args.info.call_cookie,
7511 NPARM_REGS (SImode) - pushregs)
7514 crtl->args.info.call_cookie
7515 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
7520 if (pushregs == NPARM_REGS (SImode))
7521 crtl->args.info.call_cookie
7522 |= (CALL_COOKIE_INT_REG (0, 1)
7523 | CALL_COOKIE_STACKSEQ (pushregs - 1));
7525 crtl->args.info.call_cookie
7526 |= CALL_COOKIE_STACKSEQ (pushregs);
7528 crtl->args.pretend_args_size += 8 * n_intregs;
7530 if (TARGET_SHCOMPACT)
7534 if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
7536 error ("__builtin_saveregs not supported by this subtarget");
7543 /* Allocate block of memory for the regs. */
7544 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7545 Or can assign_stack_local accept a 0 SIZE argument? */
7546 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7549 regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
7550 else if (n_floatregs & 1)
7554 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7555 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7556 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7557 regbuf = change_address (regbuf, BLKmode, addr);
7559 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7563 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7564 addr = copy_to_mode_reg (Pmode, plus_constant (XEXP (regbuf, 0), 4));
7565 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7566 emit_insn (gen_andsi3 (addr, addr, mask));
7567 regbuf = change_address (regbuf, BLKmode, addr);
7570 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7571 alias_set = get_varargs_alias_set ();
7572 set_mem_alias_set (regbuf, alias_set);
7575 This is optimized to only save the regs that are necessary. Explicitly
7576 named args need not be saved. */
7578 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7579 adjust_address (regbuf, BLKmode,
7580 n_floatregs * UNITS_PER_WORD),
7584 /* Return the address of the regbuf. */
7585 return XEXP (regbuf, 0);
7588 This is optimized to only save the regs that are necessary. Explicitly
7589 named args need not be saved.
7590 We explicitly build a pointer to the buffer because it halves the insn
7591 count when not optimizing (otherwise the pointer is built for each reg
7593 We emit the moves in reverse order so that we can use predecrement. */
7595 fpregs = copy_to_mode_reg (Pmode,
7596 plus_constant (XEXP (regbuf, 0),
7597 n_floatregs * UNITS_PER_WORD));
7598 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7601 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7603 emit_insn (gen_addsi3 (fpregs, fpregs,
7604 GEN_INT (-2 * UNITS_PER_WORD)));
7605 mem = change_address (regbuf, DFmode, fpregs);
7606 emit_move_insn (mem,
7607 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7609 regno = first_floatreg;
7612 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7613 mem = change_address (regbuf, SFmode, fpregs);
7614 emit_move_insn (mem,
7615 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno
7616 - (TARGET_LITTLE_ENDIAN != 0)));
7620 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7624 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7625 mem = change_address (regbuf, SFmode, fpregs);
7626 emit_move_insn (mem,
7627 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7630 /* Return the address of the regbuf. */
7631 return XEXP (regbuf, 0);
7634 /* Define the `__builtin_va_list' type for the ABI. */
7637 sh_build_builtin_va_list (void)
7639 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7642 if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
7643 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7644 return ptr_type_node;
7646 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7648 f_next_o = build_decl (BUILTINS_LOCATION,
7649 FIELD_DECL, get_identifier ("__va_next_o"),
7651 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7653 get_identifier ("__va_next_o_limit"),
7655 f_next_fp = build_decl (BUILTINS_LOCATION,
7656 FIELD_DECL, get_identifier ("__va_next_fp"),
7658 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7660 get_identifier ("__va_next_fp_limit"),
7662 f_next_stack = build_decl (BUILTINS_LOCATION,
7663 FIELD_DECL, get_identifier ("__va_next_stack"),
7666 DECL_FIELD_CONTEXT (f_next_o) = record;
7667 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7668 DECL_FIELD_CONTEXT (f_next_fp) = record;
7669 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7670 DECL_FIELD_CONTEXT (f_next_stack) = record;
7672 TYPE_FIELDS (record) = f_next_o;
7673 TREE_CHAIN (f_next_o) = f_next_o_limit;
7674 TREE_CHAIN (f_next_o_limit) = f_next_fp;
7675 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
7676 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
7678 layout_type (record);
7683 /* Implement `va_start' for varargs and stdarg. */
7686 sh_va_start (tree valist, rtx nextarg)
7688 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7689 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7695 expand_builtin_saveregs ();
7696 std_expand_builtin_va_start (valist, nextarg);
7700 if ((! TARGET_SH2E && ! TARGET_SH4)
7701 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7703 std_expand_builtin_va_start (valist, nextarg);
7707 f_next_o = TYPE_FIELDS (va_list_type_node);
7708 f_next_o_limit = TREE_CHAIN (f_next_o);
7709 f_next_fp = TREE_CHAIN (f_next_o_limit);
7710 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7711 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7713 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7715 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7716 valist, f_next_o_limit, NULL_TREE);
7717 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7719 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7720 valist, f_next_fp_limit, NULL_TREE);
7721 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7722 valist, f_next_stack, NULL_TREE);
7724 /* Call __builtin_saveregs. */
7725 u = make_tree (sizetype, expand_builtin_saveregs ());
7726 u = fold_convert (ptr_type_node, u);
7727 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7728 TREE_SIDE_EFFECTS (t) = 1;
7729 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7731 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7736 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7737 size_int (UNITS_PER_WORD * nfp));
7738 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7739 TREE_SIDE_EFFECTS (t) = 1;
7740 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7742 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7743 TREE_SIDE_EFFECTS (t) = 1;
7744 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7746 nint = crtl->args.info.arg_count[SH_ARG_INT];
7751 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u,
7752 size_int (UNITS_PER_WORD * nint));
7753 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7754 TREE_SIDE_EFFECTS (t) = 1;
7755 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7757 u = make_tree (ptr_type_node, nextarg);
7758 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7759 TREE_SIDE_EFFECTS (t) = 1;
7760 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7763 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7764 member, return it. */
7766 find_sole_member (tree type)
7768 tree field, member = NULL_TREE;
7770 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7772 if (TREE_CODE (field) != FIELD_DECL)
7774 if (!DECL_SIZE (field))
7776 if (integer_zerop (DECL_SIZE (field)))
7784 /* Implement `va_arg'. */
7787 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7788 gimple_seq *post_p ATTRIBUTE_UNUSED)
7790 HOST_WIDE_INT size, rsize;
7791 tree tmp, pptr_type_node;
7792 tree addr, lab_over = NULL, result = NULL;
7793 int pass_by_ref = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7797 type = build_pointer_type (type);
7799 size = int_size_in_bytes (type);
7800 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7801 pptr_type_node = build_pointer_type (ptr_type_node);
7803 if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
7804 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7806 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7807 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7812 f_next_o = TYPE_FIELDS (va_list_type_node);
7813 f_next_o_limit = TREE_CHAIN (f_next_o);
7814 f_next_fp = TREE_CHAIN (f_next_o_limit);
7815 f_next_fp_limit = TREE_CHAIN (f_next_fp);
7816 f_next_stack = TREE_CHAIN (f_next_fp_limit);
7818 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7820 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7821 valist, f_next_o_limit, NULL_TREE);
7822 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7823 valist, f_next_fp, NULL_TREE);
7824 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7825 valist, f_next_fp_limit, NULL_TREE);
7826 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7827 valist, f_next_stack, NULL_TREE);
7829 /* Structures with a single member with a distinct mode are passed
7830 like their member. This is relevant if the latter has a REAL_TYPE
7831 or COMPLEX_TYPE type. */
7833 while (TREE_CODE (eff_type) == RECORD_TYPE
7834 && (member = find_sole_member (eff_type))
7835 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7836 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7837 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7839 tree field_type = TREE_TYPE (member);
7841 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7842 eff_type = field_type;
7845 gcc_assert ((TYPE_ALIGN (eff_type)
7846 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7847 || (TYPE_ALIGN (eff_type)
7848 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7853 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7855 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7856 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7857 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7862 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7865 addr = create_tmp_var (pptr_type_node, NULL);
7866 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7867 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7869 valist = build1 (INDIRECT_REF, ptr_type_node, addr);
7873 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp), NULL);
7875 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7877 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7878 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7880 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7881 tmp = next_fp_limit;
7882 if (size > 4 && !is_double)
7883 tmp = build2 (POINTER_PLUS_EXPR, TREE_TYPE (tmp),
7884 unshare_expr (tmp), size_int (4 - size));
7885 tmp = build2 (GE_EXPR, boolean_type_node,
7886 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7887 cmp = build3 (COND_EXPR, void_type_node, tmp,
7888 build1 (GOTO_EXPR, void_type_node,
7889 unshare_expr (lab_false)), NULL_TREE);
7891 gimplify_and_add (cmp, pre_p);
7893 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7894 || (is_double || size == 16))
7896 tmp = fold_convert (sizetype, next_fp_tmp);
7897 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7898 size_int (UNITS_PER_WORD));
7899 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7900 unshare_expr (next_fp_tmp), tmp);
7901 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7904 gimplify_and_add (cmp, pre_p);
7906 #ifdef FUNCTION_ARG_SCmode_WART
7907 if (TYPE_MODE (eff_type) == SCmode
7908 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7910 tree subtype = TREE_TYPE (eff_type);
7914 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7915 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7918 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7919 real = get_initialized_tmp_var (real, pre_p, NULL);
7921 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7922 if (type != eff_type)
7923 result = build1 (VIEW_CONVERT_EXPR, type, result);
7924 result = get_initialized_tmp_var (result, pre_p, NULL);
7926 #endif /* FUNCTION_ARG_SCmode_WART */
7928 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7929 gimplify_and_add (tmp, pre_p);
7931 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7932 gimplify_and_add (tmp, pre_p);
7934 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7935 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7936 gimplify_assign (unshare_expr (next_fp_tmp),
7937 unshare_expr (valist), pre_p);
7939 gimplify_assign (unshare_expr (valist),
7940 unshare_expr (next_fp_tmp), post_p);
7941 valist = next_fp_tmp;
7945 tmp = build2 (POINTER_PLUS_EXPR, ptr_type_node,
7946 unshare_expr (next_o), size_int (rsize));
7947 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7948 unshare_expr (next_o_limit));
7949 tmp = build3 (COND_EXPR, void_type_node, tmp,
7950 build1 (GOTO_EXPR, void_type_node,
7951 unshare_expr (lab_false)),
7953 gimplify_and_add (tmp, pre_p);
7955 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7956 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7958 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7959 gimplify_and_add (tmp, pre_p);
7961 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7962 gimplify_and_add (tmp, pre_p);
7964 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7965 gimplify_assign (unshare_expr (next_o),
7966 unshare_expr (next_o_limit), pre_p);
7968 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7969 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7974 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7975 gimplify_and_add (tmp, pre_p);
7979 /* ??? In va-sh.h, there had been code to make values larger than
7980 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7982 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7985 gimplify_assign (result, tmp, pre_p);
7986 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7987 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7988 gimplify_and_add (tmp, pre_p);
7994 result = build_va_arg_indirect_ref (result);
7999 /* 64 bit floating points memory transfers are paired single precision loads
8000 or store. So DWARF information needs fixing in little endian (unless
8001 PR=SZ=1 in FPSCR). */
8003 sh_dwarf_register_span (rtx reg)
8005 unsigned regno = REGNO (reg);
8007 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
8011 gen_rtx_PARALLEL (VOIDmode,
8013 gen_rtx_REG (SFmode,
8014 DBX_REGISTER_NUMBER (regno+1)),
8015 gen_rtx_REG (SFmode,
8016 DBX_REGISTER_NUMBER (regno))));
8019 static enum machine_mode
8020 sh_promote_function_mode (const_tree type, enum machine_mode mode,
8021 int *punsignedp, const_tree funtype,
8022 int for_return ATTRIBUTE_UNUSED)
8024 if (sh_promote_prototypes (funtype))
8025 return promote_mode (type, mode, punsignedp);
8031 sh_promote_prototypes (const_tree type)
8037 return ! sh_attr_renesas_p (type);
8040 /* Whether an argument must be passed by reference. On SHcompact, we
8041 pretend arguments wider than 32-bits that would have been passed in
8042 registers are passed by reference, so that an SHmedia trampoline
8043 loads them into the full 64-bits registers. */
8046 shcompact_byref (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8047 const_tree type, bool named)
8049 unsigned HOST_WIDE_INT size;
8052 size = int_size_in_bytes (type);
8054 size = GET_MODE_SIZE (mode);
8056 if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode)
8058 || GET_SH_ARG_CLASS (mode) == SH_ARG_INT
8059 || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT
8060 && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode)))
8062 && !SHCOMPACT_FORCE_ON_STACK (mode, type)
8063 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8070 sh_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8071 const_tree type, bool named)
8073 if (targetm.calls.must_pass_in_stack (mode, type))
8076 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8077 wants to know about pass-by-reference semantics for incoming
8082 if (TARGET_SHCOMPACT)
8084 cum->byref = shcompact_byref (cum, mode, type, named);
8085 return cum->byref != 0;
8092 sh_callee_copies (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8093 const_tree type, bool named ATTRIBUTE_UNUSED)
8095 /* ??? How can it possibly be correct to return true only on the
8096 caller side of the equation? Is there someplace else in the
8097 sh backend that's magically producing the copies? */
8098 return (cum->outgoing
8099 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
8100 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
8104 sh_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8105 tree type, bool named ATTRIBUTE_UNUSED)
8110 && PASS_IN_REG_P (*cum, mode, type)
8111 && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
8112 && (ROUND_REG (*cum, mode)
8114 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
8115 : ROUND_ADVANCE (int_size_in_bytes (type)))
8116 > NPARM_REGS (mode)))
8117 words = NPARM_REGS (mode) - ROUND_REG (*cum, mode);
8119 else if (!TARGET_SHCOMPACT
8120 && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named))
8121 words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT];
8123 return words * UNITS_PER_WORD;
8127 /* Define where to put the arguments to a function.
8128 Value is zero to push the argument on the stack,
8129 or a hard register in which to store the argument.
8131 MODE is the argument's machine mode.
8132 TYPE is the data type of the argument (as a tree).
8133 This is null for libcalls where that information may
8135 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8136 the preceding args and about the function being called.
8137 NAMED is nonzero if this argument is a named parameter
8138 (otherwise it is an extra parameter matching an ellipsis).
8140 On SH the first args are normally in registers
8141 and the rest are pushed. Any arg that starts within the first
8142 NPARM_REGS words is at least partially passed in a register unless
8143 its data type forbids. */
8147 sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8148 tree type, int named)
8150 if (! TARGET_SH5 && mode == VOIDmode)
8151 return GEN_INT (ca->renesas_abi ? 1 : 0);
8154 && PASS_IN_REG_P (*ca, mode, type)
8155 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8159 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8160 && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
8162 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8163 gen_rtx_REG (SFmode,
8165 + (ROUND_REG (*ca, mode) ^ 1)),
8167 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8168 gen_rtx_REG (SFmode,
8170 + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
8172 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8175 /* If the alignment of a DF value causes an SF register to be
8176 skipped, we will use that skipped register for the next SF
8178 if ((TARGET_HITACHI || ca->renesas_abi)
8179 && ca->free_single_fp_reg
8181 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8183 regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
8184 ^ (mode == SFmode && TARGET_SH4
8185 && TARGET_LITTLE_ENDIAN != 0
8186 && ! TARGET_HITACHI && ! ca->renesas_abi);
8187 return gen_rtx_REG (mode, regno);
8193 if (mode == VOIDmode && TARGET_SHCOMPACT)
8194 return GEN_INT (ca->call_cookie);
8196 /* The following test assumes unnamed arguments are promoted to
8198 if (mode == SFmode && ca->free_single_fp_reg)
8199 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
8201 if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
8202 && (named || ! ca->prototype_p)
8203 && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
8205 if (! ca->prototype_p && TARGET_SHMEDIA)
8206 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
8208 return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
8210 + ca->arg_count[(int) SH_ARG_FLOAT]);
8213 if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
8214 && (! TARGET_SHCOMPACT
8215 || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
8216 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
8219 return gen_rtx_REG (mode, (FIRST_PARM_REG
8220 + ca->arg_count[(int) SH_ARG_INT]));
8229 /* Update the data in CUM to advance over an argument
8230 of mode MODE and data type TYPE.
8231 (TYPE is null for libcalls where that information may not be
8235 sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
8236 tree type, int named)
8240 else if (TARGET_SH5)
8242 tree type2 = (ca->byref && type
8245 enum machine_mode mode2 = (ca->byref && type
8248 int dwords = ((ca->byref
8251 ? int_size_in_bytes (type2)
8252 : GET_MODE_SIZE (mode2)) + 7) / 8;
8253 int numregs = MIN (dwords, NPARM_REGS (SImode)
8254 - ca->arg_count[(int) SH_ARG_INT]);
8258 ca->arg_count[(int) SH_ARG_INT] += numregs;
8259 if (TARGET_SHCOMPACT
8260 && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
8263 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8265 /* N.B. We want this also for outgoing. */
8266 ca->stack_regs += numregs;
8271 ca->stack_regs += numregs;
8272 ca->byref_regs += numregs;
8276 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8280 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
8283 else if (dwords > numregs)
8285 int pushregs = numregs;
8287 if (TARGET_SHCOMPACT)
8288 ca->stack_regs += numregs;
8289 while (pushregs < NPARM_REGS (SImode) - 1
8290 && (CALL_COOKIE_INT_REG_GET
8292 NPARM_REGS (SImode) - pushregs)
8296 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
8300 if (numregs == NPARM_REGS (SImode))
8302 |= CALL_COOKIE_INT_REG (0, 1)
8303 | CALL_COOKIE_STACKSEQ (numregs - 1);
8306 |= CALL_COOKIE_STACKSEQ (numregs);
8309 if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
8310 && (named || ! ca->prototype_p))
8312 if (mode2 == SFmode && ca->free_single_fp_reg)
8313 ca->free_single_fp_reg = 0;
8314 else if (ca->arg_count[(int) SH_ARG_FLOAT]
8315 < NPARM_REGS (SFmode))
8318 = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
8320 - ca->arg_count[(int) SH_ARG_FLOAT]);
8322 ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
8324 if (TARGET_SHCOMPACT && ! ca->prototype_p)
8326 if (ca->outgoing && numregs > 0)
8330 |= (CALL_COOKIE_INT_REG
8331 (ca->arg_count[(int) SH_ARG_INT]
8332 - numregs + ((numfpregs - 2) / 2),
8333 4 + (ca->arg_count[(int) SH_ARG_FLOAT]
8336 while (numfpregs -= 2);
8338 else if (mode2 == SFmode && (named)
8339 && (ca->arg_count[(int) SH_ARG_FLOAT]
8340 < NPARM_REGS (SFmode)))
8341 ca->free_single_fp_reg
8342 = FIRST_FP_PARM_REG - numfpregs
8343 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
8349 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8351 /* Note that we've used the skipped register. */
8352 if (mode == SFmode && ca->free_single_fp_reg)
8354 ca->free_single_fp_reg = 0;
8357 /* When we have a DF after an SF, there's an SF register that get
8358 skipped in order to align the DF value. We note this skipped
8359 register, because the next SF value will use it, and not the
8360 SF that follows the DF. */
8362 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
8364 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
8365 + BASE_ARG_REG (mode));
8369 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8370 || PASS_IN_REG_P (*ca, mode, type))
8371 (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
8372 = (ROUND_REG (*ca, mode)
8374 ? ROUND_ADVANCE (int_size_in_bytes (type))
8375 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
8378 /* The Renesas calling convention doesn't quite fit into this scheme since
8379 the address is passed like an invisible argument, but one that is always
8380 passed in memory. */
8382 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8384 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8386 return gen_rtx_REG (Pmode, 2);
8389 /* Worker function for TARGET_FUNCTION_VALUE.
8391 For the SH, this is like LIBCALL_VALUE, except that we must change the
8392 mode like PROMOTE_MODE does.
8393 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8394 tested here has to be kept in sync with the one in explow.c:promote_mode.
8398 sh_function_value (const_tree valtype,
8399 const_tree fn_decl_or_type,
8400 bool outgoing ATTRIBUTE_UNUSED)
8403 && !DECL_P (fn_decl_or_type))
8404 fn_decl_or_type = NULL;
8406 return gen_rtx_REG (
8407 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8408 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8409 && (TREE_CODE (valtype) == INTEGER_TYPE
8410 || TREE_CODE (valtype) == ENUMERAL_TYPE
8411 || TREE_CODE (valtype) == BOOLEAN_TYPE
8412 || TREE_CODE (valtype) == REAL_TYPE
8413 || TREE_CODE (valtype) == OFFSET_TYPE))
8414 && sh_promote_prototypes (fn_decl_or_type)
8415 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)),
8416 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8419 /* Worker function for TARGET_LIBCALL_VALUE. */
8422 sh_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8424 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8427 /* Worker function for FUNCTION_VALUE_REGNO_P. */
8430 sh_function_value_regno_p (const unsigned int regno)
8432 return ((regno) == FIRST_RET_REG
8433 || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG)
8434 || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG));
8437 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8440 sh_return_in_memory (const_tree type, const_tree fndecl)
8444 if (TYPE_MODE (type) == BLKmode)
8445 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
8447 return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
8451 return (TYPE_MODE (type) == BLKmode
8452 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8453 && TREE_CODE (type) == RECORD_TYPE));
8457 /* We actually emit the code in sh_expand_prologue. We used to use
8458 a static variable to flag that we need to emit this code, but that
8459 doesn't when inlining, when functions are deferred and then emitted
8460 later. Fortunately, we already have two flags that are part of struct
8461 function that tell if a function uses varargs or stdarg. */
8463 sh_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
8464 enum machine_mode mode,
8466 int *pretend_arg_size,
8467 int second_time ATTRIBUTE_UNUSED)
8469 gcc_assert (cfun->stdarg);
8470 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8472 int named_parm_regs, anon_parm_regs;
8474 named_parm_regs = (ROUND_REG (*ca, mode)
8476 ? ROUND_ADVANCE (int_size_in_bytes (type))
8477 : ROUND_ADVANCE (GET_MODE_SIZE (mode))));
8478 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8479 if (anon_parm_regs > 0)
8480 *pretend_arg_size = anon_parm_regs * 4;
8485 sh_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
8491 sh_pretend_outgoing_varargs_named (CUMULATIVE_ARGS *ca)
8493 return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
8497 /* Define the offset between two registers, one to be eliminated, and
8498 the other its replacement, at the start of a routine. */
8501 initial_elimination_offset (int from, int to)
8504 int regs_saved_rounding = 0;
8505 int total_saved_regs_space;
8506 int total_auto_space;
8507 int save_flags = target_flags;
8509 HARD_REG_SET live_regs_mask;
8511 shmedia_space_reserved_for_target_registers = false;
8512 regs_saved = calc_live_regs (&live_regs_mask);
8513 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
8515 if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask))
8517 shmedia_space_reserved_for_target_registers = true;
8518 regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask);
8521 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
8522 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
8523 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
8525 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8526 copy_flags = target_flags;
8527 target_flags = save_flags;
8529 total_saved_regs_space = regs_saved + regs_saved_rounding;
8531 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8532 return total_saved_regs_space + total_auto_space
8533 + crtl->args.info.byref_regs * 8;
8535 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8536 return total_saved_regs_space + total_auto_space
8537 + crtl->args.info.byref_regs * 8;
8539 /* Initial gap between fp and sp is 0. */
8540 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8543 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8544 return rounded_frame_size (0);
8546 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8547 return rounded_frame_size (0);
8549 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8550 && (to == HARD_FRAME_POINTER_REGNUM
8551 || to == STACK_POINTER_REGNUM));
8554 int n = total_saved_regs_space;
8555 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
8556 save_schedule schedule;
8559 n += total_auto_space;
8561 /* If it wasn't saved, there's not much we can do. */
8562 if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
8565 target_flags = copy_flags;
8567 sh5_schedule_saves (&live_regs_mask, &schedule, n);
8568 for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
8569 if (entry->reg == pr_reg)
8571 target_flags = save_flags;
8572 return entry->offset;
8577 return total_auto_space;
8580 /* Parse the -mfixed-range= option string. */
8582 sh_fix_range (const char *const_str)
8585 char *str, *dash, *comma;
8587 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8588 REG2 are either register names or register numbers. The effect
8589 of this option is to mark the registers in the range from REG1 to
8590 REG2 as ``fixed'' so they won't be used by the compiler. */
8592 i = strlen (const_str);
8593 str = (char *) alloca (i + 1);
8594 memcpy (str, const_str, i + 1);
8598 dash = strchr (str, '-');
8601 warning (0, "value of -mfixed-range must have form REG1-REG2");
8605 comma = strchr (dash + 1, ',');
8609 first = decode_reg_name (str);
8612 warning (0, "unknown register name: %s", str);
8616 last = decode_reg_name (dash + 1);
8619 warning (0, "unknown register name: %s", dash + 1);
8627 warning (0, "%s-%s is an empty range", str, dash + 1);
8631 for (i = first; i <= last; ++i)
8632 fixed_regs[i] = call_used_regs[i] = 1;
8642 /* Insert any deferred function attributes from earlier pragmas. */
8644 sh_insert_attributes (tree node, tree *attributes)
8648 if (TREE_CODE (node) != FUNCTION_DECL)
8651 /* We are only interested in fields. */
8655 /* Append the attributes to the deferred attributes. */
8656 *sh_deferred_function_attributes_tail = *attributes;
8657 attrs = sh_deferred_function_attributes;
8661 /* Some attributes imply or require the interrupt attribute. */
8662 if (!lookup_attribute ("interrupt_handler", attrs)
8663 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8665 /* If we have a trapa_handler, but no interrupt_handler attribute,
8666 insert an interrupt_handler attribute. */
8667 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8668 /* We can't use sh_pr_interrupt here because that's not in the
8671 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8672 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8673 if the interrupt attribute is missing, we ignore the attribute
8675 else if (lookup_attribute ("sp_switch", attrs)
8676 || lookup_attribute ("trap_exit", attrs)
8677 || lookup_attribute ("nosave_low_regs", attrs)
8678 || lookup_attribute ("resbank", attrs))
8682 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8684 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8685 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8686 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8687 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8688 warning (OPT_Wattributes,
8689 "%qE attribute only applies to interrupt functions",
8690 TREE_PURPOSE (attrs));
8693 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8695 tail = &TREE_CHAIN (*tail);
8698 attrs = *attributes;
8702 /* Install the processed list. */
8703 *attributes = attrs;
8705 /* Clear deferred attributes. */
8706 sh_deferred_function_attributes = NULL_TREE;
8707 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8712 /* Supported attributes:
8714 interrupt_handler -- specifies this function is an interrupt handler.
8716 trapa_handler - like above, but don't save all registers.
8718 sp_switch -- specifies an alternate stack for an interrupt handler
8721 trap_exit -- use a trapa to exit an interrupt function instead of
8724 nosave_low_regs - don't save r0..r7 in an interrupt handler.
8725 This is useful on the SH3 and upwards,
8726 which has a separate set of low regs for User and Supervisor modes.
8727 This should only be used for the lowest level of interrupts. Higher levels
8728 of interrupts must save the registers in case they themselves are
8731 renesas -- use Renesas calling/layout conventions (functions and
8734 resbank -- In case of an ISR, use a register bank to save registers
8735 R0-R14, MACH, MACL, GBR and PR. This is useful only on SH2A targets.
8738 /* Handle a 'resbank' attribute. */
8740 sh_handle_resbank_handler_attribute (tree * node, tree name,
8741 tree args ATTRIBUTE_UNUSED,
8742 int flags ATTRIBUTE_UNUSED,
8743 bool * no_add_attrs)
8747 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8749 *no_add_attrs = true;
8751 if (TREE_CODE (*node) != FUNCTION_DECL)
8753 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8755 *no_add_attrs = true;
8761 /* Handle an "interrupt_handler" attribute; arguments as in
8762 struct attribute_spec.handler. */
8764 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8765 tree args ATTRIBUTE_UNUSED,
8766 int flags ATTRIBUTE_UNUSED,
8769 if (TREE_CODE (*node) != FUNCTION_DECL)
8771 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8773 *no_add_attrs = true;
8775 else if (TARGET_SHCOMPACT)
8777 error ("attribute interrupt_handler is not compatible with -m5-compact");
8778 *no_add_attrs = true;
8784 /* Handle an 'function_vector' attribute; arguments as in
8785 struct attribute_spec.handler. */
8787 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8788 tree args ATTRIBUTE_UNUSED,
8789 int flags ATTRIBUTE_UNUSED,
8790 bool * no_add_attrs)
8794 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8796 *no_add_attrs = true;
8798 else if (TREE_CODE (*node) != FUNCTION_DECL)
8800 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8802 *no_add_attrs = true;
8804 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8806 /* The argument must be a constant integer. */
8807 warning (OPT_Wattributes,
8808 "%qE attribute argument not an integer constant",
8810 *no_add_attrs = true;
8812 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8814 /* The argument value must be between 0 to 255. */
8815 warning (OPT_Wattributes,
8816 "%qE attribute argument should be between 0 to 255",
8818 *no_add_attrs = true;
8823 /* Returns 1 if current function has been assigned the attribute
8824 'function_vector'. */
8826 sh2a_is_function_vector_call (rtx x)
8828 if (GET_CODE (x) == SYMBOL_REF
8829 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8831 tree tr = SYMBOL_REF_DECL (x);
8833 if (sh2a_function_vector_p (tr))
8840 /* Returns the function vector number, if the the attribute
8841 'function_vector' is assigned, otherwise returns zero. */
8843 sh2a_get_function_vector_number (rtx x)
8848 if ((GET_CODE (x) == SYMBOL_REF)
8849 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8851 t = SYMBOL_REF_DECL (x);
8853 if (TREE_CODE (t) != FUNCTION_DECL)
8856 list = SH_ATTRIBUTES (t);
8859 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8861 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8865 list = TREE_CHAIN (list);
8874 /* Handle an "sp_switch" attribute; arguments as in
8875 struct attribute_spec.handler. */
8877 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8878 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8880 if (TREE_CODE (*node) != FUNCTION_DECL)
8882 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8884 *no_add_attrs = true;
8886 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8888 /* The argument must be a constant string. */
8889 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8891 *no_add_attrs = true;
8897 /* Handle an "trap_exit" attribute; arguments as in
8898 struct attribute_spec.handler. */
8900 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8901 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8903 if (TREE_CODE (*node) != FUNCTION_DECL)
8905 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8907 *no_add_attrs = true;
8909 /* The argument specifies a trap number to be used in a trapa instruction
8910 at function exit (instead of an rte instruction). */
8911 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8913 /* The argument must be a constant integer. */
8914 warning (OPT_Wattributes, "%qE attribute argument not an "
8915 "integer constant", name);
8916 *no_add_attrs = true;
8923 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8924 tree name ATTRIBUTE_UNUSED,
8925 tree args ATTRIBUTE_UNUSED,
8926 int flags ATTRIBUTE_UNUSED,
8927 bool *no_add_attrs ATTRIBUTE_UNUSED)
8932 /* True if __attribute__((renesas)) or -mrenesas. */
8934 sh_attr_renesas_p (const_tree td)
8941 td = TREE_TYPE (td);
8942 if (td == error_mark_node)
8944 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
8948 /* True if __attribute__((renesas)) or -mrenesas, for the current
8951 sh_cfun_attr_renesas_p (void)
8953 return sh_attr_renesas_p (current_function_decl);
8957 sh_cfun_interrupt_handler_p (void)
8959 return (lookup_attribute ("interrupt_handler",
8960 DECL_ATTRIBUTES (current_function_decl))
8964 /* Returns 1 if FUNC has been assigned the attribute
8965 "function_vector". */
8967 sh2a_function_vector_p (tree func)
8970 if (TREE_CODE (func) != FUNCTION_DECL)
8973 list = SH_ATTRIBUTES (func);
8976 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8979 list = TREE_CHAIN (list);
8984 /* Returns TRUE if given tree has the "resbank" attribute. */
8987 sh_cfun_resbank_handler_p (void)
8989 return ((lookup_attribute ("resbank",
8990 DECL_ATTRIBUTES (current_function_decl))
8992 && (lookup_attribute ("interrupt_handler",
8993 DECL_ATTRIBUTES (current_function_decl))
8994 != NULL_TREE) && TARGET_SH2A);
8997 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9000 sh_check_pch_target_flags (int old_flags)
9002 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
9003 | MASK_SH_E | MASK_HARD_SH4
9004 | MASK_FPU_SINGLE | MASK_SH4))
9005 return _("created and used with different architectures / ABIs");
9006 if ((old_flags ^ target_flags) & MASK_HITACHI)
9007 return _("created and used with different ABIs");
9008 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
9009 return _("created and used with different endianness");
9013 /* Predicates used by the templates. */
9015 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
9016 Used only in general_movsrc_operand. */
9019 system_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9031 /* Nonzero if OP is a floating point value with value 0.0. */
9034 fp_zero_operand (rtx op)
9038 if (GET_MODE (op) != SFmode)
9041 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9042 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
9045 /* Nonzero if OP is a floating point value with value 1.0. */
9048 fp_one_operand (rtx op)
9052 if (GET_MODE (op) != SFmode)
9055 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
9056 return REAL_VALUES_EQUAL (r, dconst1);
9059 /* In general mode switching is used. If we are
9060 compiling without -mfmovd, movsf_ie isn't taken into account for
9061 mode switching. We could check in machine_dependent_reorg for
9062 cases where we know we are in single precision mode, but there is
9063 interface to find that out during reload, so we must avoid
9064 choosing an fldi alternative during reload and thus failing to
9065 allocate a scratch register for the constant loading. */
9073 tertiary_reload_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9075 enum rtx_code code = GET_CODE (op);
9076 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
9079 /* Return the TLS type for TLS symbols, 0 for otherwise. */
9081 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9083 if (GET_CODE (op) != SYMBOL_REF)
9084 return TLS_MODEL_NONE;
9085 return SYMBOL_REF_TLS_MODEL (op);
9088 /* Return the destination address of a branch. */
9091 branch_dest (rtx branch)
9093 rtx dest = SET_SRC (PATTERN (branch));
9096 if (GET_CODE (dest) == IF_THEN_ELSE)
9097 dest = XEXP (dest, 1);
9098 dest = XEXP (dest, 0);
9099 dest_uid = INSN_UID (dest);
9100 return INSN_ADDRESSES (dest_uid);
9103 /* Return nonzero if REG is not used after INSN.
9104 We assume REG is a reload reg, and therefore does
9105 not live past labels. It may live past calls or jumps though. */
9107 reg_unused_after (rtx reg, rtx insn)
9112 /* If the reg is set by this instruction, then it is safe for our
9113 case. Disregard the case where this is a store to memory, since
9114 we are checking a register used in the store address. */
9115 set = single_set (insn);
9116 if (set && !MEM_P (SET_DEST (set))
9117 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9120 while ((insn = NEXT_INSN (insn)))
9126 code = GET_CODE (insn);
9129 /* If this is a label that existed before reload, then the register
9130 if dead here. However, if this is a label added by reorg, then
9131 the register may still be live here. We can't tell the difference,
9132 so we just ignore labels completely. */
9133 if (code == CODE_LABEL)
9138 if (code == JUMP_INSN)
9141 /* If this is a sequence, we must handle them all at once.
9142 We could have for instance a call that sets the target register,
9143 and an insn in a delay slot that uses the register. In this case,
9144 we must return 0. */
9145 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
9150 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9152 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
9153 rtx set = single_set (this_insn);
9155 if (CALL_P (this_insn))
9157 else if (JUMP_P (this_insn))
9159 if (INSN_ANNULLED_BRANCH_P (this_insn))
9164 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9166 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9168 if (!MEM_P (SET_DEST (set)))
9174 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
9179 else if (code == JUMP_INSN)
9183 set = single_set (insn);
9184 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
9186 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
9187 return !MEM_P (SET_DEST (set));
9188 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9191 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
9199 static GTY(()) rtx fpscr_rtx;
9201 get_fpscr_rtx (void)
9205 fpscr_rtx = gen_rtx_REG (PSImode, FPSCR_REG);
9206 REG_USERVAR_P (fpscr_rtx) = 1;
9207 mark_user_reg (fpscr_rtx);
9209 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
9210 mark_user_reg (fpscr_rtx);
9214 static GTY(()) tree fpscr_values;
9217 emit_fpu_switch (rtx scratch, int index)
9221 if (fpscr_values == NULL)
9225 t = build_index_type (integer_one_node);
9226 t = build_array_type (integer_type_node, t);
9227 t = build_decl (BUILTINS_LOCATION,
9228 VAR_DECL, get_identifier ("__fpscr_values"), t);
9229 DECL_ARTIFICIAL (t) = 1;
9230 DECL_IGNORED_P (t) = 1;
9231 DECL_EXTERNAL (t) = 1;
9232 TREE_STATIC (t) = 1;
9233 TREE_PUBLIC (t) = 1;
9239 src = DECL_RTL (fpscr_values);
9240 if (!can_create_pseudo_p ())
9242 emit_move_insn (scratch, XEXP (src, 0));
9244 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
9245 src = adjust_automodify_address (src, PSImode, scratch, index * 4);
9248 src = adjust_address (src, PSImode, index * 4);
9250 dst = get_fpscr_rtx ();
9251 emit_move_insn (dst, src);
9255 emit_sf_insn (rtx pat)
9261 emit_df_insn (rtx pat)
9267 expand_sf_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9269 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9273 expand_sf_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9275 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
9280 expand_df_unop (rtx (*fun) (rtx, rtx, rtx), rtx *operands)
9282 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
9286 expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
9288 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
9292 static rtx get_free_reg (HARD_REG_SET);
9294 /* This function returns a register to use to load the address to load
9295 the fpscr from. Currently it always returns r1 or r7, but when we are
9296 able to use pseudo registers after combine, or have a better mechanism
9297 for choosing a register, it should be done here. */
9298 /* REGS_LIVE is the liveness information for the point for which we
9299 need this allocation. In some bare-bones exit blocks, r1 is live at the
9300 start. We can even have all of r0..r3 being live:
9301 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
9302 INSN before which new insns are placed with will clobber the register
9303 we return. If a basic block consists only of setting the return value
9304 register to a pseudo and using that register, the return value is not
9305 live before or after this block, yet we we'll insert our insns right in
9309 get_free_reg (HARD_REG_SET regs_live)
9311 if (! TEST_HARD_REG_BIT (regs_live, 1))
9312 return gen_rtx_REG (Pmode, 1);
9314 /* Hard reg 1 is live; since this is a small register classes target,
9315 there shouldn't be anything but a jump before the function end. */
9316 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
9317 return gen_rtx_REG (Pmode, 7);
9320 /* This function will set the fpscr from memory.
9321 MODE is the mode we are setting it to. */
9323 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
9325 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
9326 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
9329 addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
9330 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
9333 /* Is the given character a logical line separator for the assembler? */
9334 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
9335 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
9339 sh_insn_length_adjustment (rtx insn)
9341 /* Instructions with unfilled delay slots take up an extra two bytes for
9342 the nop in the delay slot. */
9343 if (((NONJUMP_INSN_P (insn)
9344 && GET_CODE (PATTERN (insn)) != USE
9345 && GET_CODE (PATTERN (insn)) != CLOBBER)
9347 || (JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)))
9348 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
9349 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
9352 /* SH2e has a bug that prevents the use of annulled branches, so if
9353 the delay slot is not filled, we'll have to put a NOP in it. */
9354 if (sh_cpu_attr == CPU_SH2E
9355 && JUMP_P (insn) && !JUMP_TABLE_DATA_P (insn)
9356 && get_attr_type (insn) == TYPE_CBRANCH
9357 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
9360 /* sh-dsp parallel processing insn take four bytes instead of two. */
9362 if (NONJUMP_INSN_P (insn))
9365 rtx body = PATTERN (insn);
9368 int maybe_label = 1;
9370 if (GET_CODE (body) == ASM_INPUT)
9371 templ = XSTR (body, 0);
9372 else if (asm_noperands (body) >= 0)
9374 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
9383 while (c == ' ' || c == '\t');
9384 /* all sh-dsp parallel-processing insns start with p.
9385 The only non-ppi sh insn starting with p is pref.
9386 The only ppi starting with pr is prnd. */
9387 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
9389 /* The repeat pseudo-insn expands two three insns, a total of
9390 six bytes in size. */
9391 else if ((c == 'r' || c == 'R')
9392 && ! strncasecmp ("epeat", templ, 5))
9394 while (c && c != '\n'
9395 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
9397 /* If this is a label, it is obviously not a ppi insn. */
9398 if (c == ':' && maybe_label)
9403 else if (c == '\'' || c == '"')
9408 maybe_label = c != ':';
9416 /* Return TRUE for a valid displacement for the REG+disp addressing
9419 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
9420 into the FRx registers. We implement this by setting the maximum offset
9421 to zero when the value is SFmode. This also restricts loading of SFmode
9422 values into the integer registers, but that can't be helped. */
9424 /* The SH allows a displacement in a QI or HI amode, but only when the
9425 other operand is R0. GCC doesn't handle this very well, so we forgot
9428 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
9429 DI can be any number 0..60. */
9432 sh_legitimate_index_p (enum machine_mode mode, rtx op)
9434 if (CONST_INT_P (op))
9440 /* Check if this the address of an unaligned load / store. */
9441 if (mode == VOIDmode)
9442 return CONST_OK_FOR_I06 (INTVAL (op));
9444 size = GET_MODE_SIZE (mode);
9445 return (!(INTVAL (op) & (size - 1))
9446 && INTVAL (op) >= -512 * size
9447 && INTVAL (op) < 512 * size);
9452 if (GET_MODE_SIZE (mode) == 1
9453 && (unsigned) INTVAL (op) < 4096)
9457 if ((GET_MODE_SIZE (mode) == 4
9458 && (unsigned) INTVAL (op) < 64
9459 && !(INTVAL (op) & 3)
9460 && !(TARGET_SH2E && mode == SFmode))
9461 || (GET_MODE_SIZE (mode) == 4
9462 && (unsigned) INTVAL (op) < 16383
9463 && !(INTVAL (op) & 3) && TARGET_SH2A))
9466 if ((GET_MODE_SIZE (mode) == 8
9467 && (unsigned) INTVAL (op) < 60
9468 && !(INTVAL (op) & 3)
9469 && !((TARGET_SH4 || TARGET_SH2A) && mode == DFmode))
9470 || ((GET_MODE_SIZE (mode)==8)
9471 && (unsigned) INTVAL (op) < 8192
9472 && !(INTVAL (op) & (TARGET_SH2A_DOUBLE ? 7 : 3))
9473 && (TARGET_SH2A && mode == DFmode)))
9480 /* Recognize an RTL expression that is a valid memory address for
9482 The MODE argument is the machine mode for the MEM expression
9483 that wants to use this address.
9491 sh_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
9493 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9495 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9497 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9499 else if (GET_CODE (x) == PLUS
9500 && (mode != PSImode || reload_completed))
9502 rtx xop0 = XEXP (x, 0);
9503 rtx xop1 = XEXP (x, 1);
9505 if (GET_MODE_SIZE (mode) <= 8
9506 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9507 && sh_legitimate_index_p (mode, xop1))
9510 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode
9511 || ((xop0 == stack_pointer_rtx
9512 || xop0 == hard_frame_pointer_rtx)
9513 && REG_P (xop1) && REGNO (xop1) == R0_REG)
9514 || ((xop1 == stack_pointer_rtx
9515 || xop1 == hard_frame_pointer_rtx)
9516 && REG_P (xop0) && REGNO (xop0) == R0_REG))
9517 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4)
9518 || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8)
9519 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
9520 && TARGET_FMOVD && mode == DFmode)))
9522 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9523 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9525 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9526 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9534 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9535 isn't protected by a PIC unspec. */
9537 nonpic_symbol_mentioned_p (rtx x)
9539 register const char *fmt;
9542 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9543 || GET_CODE (x) == PC)
9546 /* We don't want to look into the possible MEM location of a
9547 CONST_DOUBLE, since we're not going to use it, in general. */
9548 if (GET_CODE (x) == CONST_DOUBLE)
9551 if (GET_CODE (x) == UNSPEC
9552 && (XINT (x, 1) == UNSPEC_PIC
9553 || XINT (x, 1) == UNSPEC_GOT
9554 || XINT (x, 1) == UNSPEC_GOTOFF
9555 || XINT (x, 1) == UNSPEC_GOTPLT
9556 || XINT (x, 1) == UNSPEC_GOTTPOFF
9557 || XINT (x, 1) == UNSPEC_DTPOFF
9558 || XINT (x, 1) == UNSPEC_TPOFF
9559 || XINT (x, 1) == UNSPEC_PLT
9560 || XINT (x, 1) == UNSPEC_SYMOFF
9561 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
9564 fmt = GET_RTX_FORMAT (GET_CODE (x));
9565 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9572 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9575 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9582 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9583 @GOTOFF in `reg'. */
9585 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
9588 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9591 if (GET_CODE (orig) == LABEL_REF
9592 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9595 reg = gen_reg_rtx (Pmode);
9597 emit_insn (gen_symGOTOFF2reg (reg, orig));
9600 else if (GET_CODE (orig) == SYMBOL_REF)
9603 reg = gen_reg_rtx (Pmode);
9605 emit_insn (gen_symGOT2reg (reg, orig));
9611 /* Try machine-dependent ways of modifying an illegitimate address
9612 to be legitimate. If we find one, return the new, valid address.
9613 Otherwise, return X.
9615 For the SH, if X is almost suitable for indexing, but the offset is
9616 out of range, convert it into a normal form so that CSE has a chance
9617 of reducing the number of address registers used. */
9620 sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
9623 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9625 if (GET_CODE (x) == PLUS
9626 && (GET_MODE_SIZE (mode) == 4
9627 || GET_MODE_SIZE (mode) == 8)
9628 && CONST_INT_P (XEXP (x, 1))
9629 && BASE_REGISTER_RTX_P (XEXP (x, 0))
9631 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
9632 && ! (TARGET_SH2E && mode == SFmode))
9634 rtx index_rtx = XEXP (x, 1);
9635 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9638 /* On rare occasions, we might get an unaligned pointer
9639 that is indexed in a way to give an aligned address.
9640 Therefore, keep the lower two bits in offset_base. */
9641 /* Instead of offset_base 128..131 use 124..127, so that
9642 simple add suffices. */
9644 offset_base = ((offset + 4) & ~60) - 4;
9646 offset_base = offset & ~60;
9648 /* Sometimes the normal form does not suit DImode. We
9649 could avoid that by using smaller ranges, but that
9650 would give less optimized code when SImode is
9652 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9654 sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9655 GEN_INT (offset_base), NULL_RTX, 0,
9658 return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9665 /* Attempt to replace *P, which is an address that needs reloading, with
9666 a valid memory address for an operand of mode MODE.
9667 Like for sh_legitimize_address, for the SH we try to get a normal form
9668 of the address. That will allow inheritance of the address reloads. */
9671 sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum,
9674 enum reload_type type = (enum reload_type) itype;
9676 if (GET_CODE (*p) == PLUS
9677 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9678 && CONST_INT_P (XEXP (*p, 1))
9679 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)
9681 && ! (TARGET_SH4 && mode == DFmode)
9682 && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS)
9683 && (ALLOW_INDEXED_ADDRESS
9684 || XEXP (*p, 0) == stack_pointer_rtx
9685 || XEXP (*p, 0) == hard_frame_pointer_rtx))
9687 rtx index_rtx = XEXP (*p, 1);
9688 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;
9691 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9693 push_reload (*p, NULL_RTX, p, NULL,
9694 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9697 if (TARGET_SH2E && mode == SFmode)
9700 push_reload (*p, NULL_RTX, p, NULL,
9701 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9704 /* Instead of offset_base 128..131 use 124..127, so that
9705 simple add suffices. */
9707 offset_base = ((offset + 4) & ~60) - 4;
9709 offset_base = offset & ~60;
9710 /* Sometimes the normal form does not suit DImode. We could avoid
9711 that by using smaller ranges, but that would give less optimized
9712 code when SImode is prevalent. */
9713 if (GET_MODE_SIZE (mode) + offset - offset_base <= 64)
9715 sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base));
9716 *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));
9717 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9718 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9722 /* We must re-recognize what we created before. */
9723 else if (GET_CODE (*p) == PLUS
9724 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
9725 && GET_CODE (XEXP (*p, 0)) == PLUS
9726 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9727 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9728 && CONST_INT_P (XEXP (*p, 1))
9730 && ! (TARGET_SH2E && mode == SFmode))
9732 /* Because this address is so complex, we know it must have
9733 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9734 it is already unshared, and needs no further unsharing. */
9735 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9736 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9746 /* Mark the use of a constant in the literal table. If the constant
9747 has multiple labels, make it unique. */
9749 mark_constant_pool_use (rtx x)
9751 rtx insn, lab, pattern;
9756 switch (GET_CODE (x))
9766 /* Get the first label in the list of labels for the same constant
9767 and delete another labels in the list. */
9769 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
9772 || LABEL_REFS (insn) != NEXT_INSN (insn))
9777 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9778 INSN_DELETED_P (insn) = 1;
9780 /* Mark constants in a window. */
9781 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
9783 if (!NONJUMP_INSN_P (insn))
9786 pattern = PATTERN (insn);
9787 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9790 switch (XINT (pattern, 1))
9792 case UNSPECV_CONST2:
9793 case UNSPECV_CONST4:
9794 case UNSPECV_CONST8:
9795 XVECEXP (pattern, 0, 1) = const1_rtx;
9797 case UNSPECV_WINDOW_END:
9798 if (XVECEXP (pattern, 0, 0) == x)
9801 case UNSPECV_CONST_END:
9811 /* Return true if it's possible to redirect BRANCH1 to the destination
9812 of an unconditional jump BRANCH2. We only want to do this if the
9813 resulting branch will have a short displacement. */
9815 sh_can_redirect_branch (rtx branch1, rtx branch2)
9817 if (flag_expensive_optimizations && simplejump_p (branch2))
9819 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9823 for (distance = 0, insn = NEXT_INSN (branch1);
9824 insn && distance < 256;
9825 insn = PREV_INSN (insn))
9830 distance += get_attr_length (insn);
9832 for (distance = 0, insn = NEXT_INSN (branch1);
9833 insn && distance < 256;
9834 insn = NEXT_INSN (insn))
9839 distance += get_attr_length (insn);
9845 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9847 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9848 unsigned int new_reg)
9850 /* Interrupt functions can only use registers that have already been
9851 saved by the prologue, even if they would normally be
9854 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9860 /* Function to update the integer COST
9861 based on the relationship between INSN that is dependent on
9862 DEP_INSN through the dependence LINK. The default is to make no
9863 adjustment to COST. This can be used for example to specify to
9864 the scheduler that an output- or anti-dependence does not incur
9865 the same cost as a data-dependence. The return value should be
9866 the new value for COST. */
9868 sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
9874 /* On SHmedia, if the dependence is an anti-dependence or
9875 output-dependence, there is no cost. */
9876 if (REG_NOTE_KIND (link) != 0)
9878 /* However, dependencies between target register loads and
9879 uses of the register in a subsequent block that are separated
9880 by a conditional branch are not modelled - we have to do with
9881 the anti-dependency between the target register load and the
9882 conditional branch that ends the current block. */
9883 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
9884 && GET_CODE (PATTERN (dep_insn)) == SET
9885 && (get_attr_type (dep_insn) == TYPE_PT_MEDIA
9886 || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA)
9887 && get_attr_type (insn) == TYPE_CBRANCH_MEDIA)
9889 int orig_cost = cost;
9890 rtx note = find_reg_note (insn, REG_BR_PROB, 0);
9891 rtx target = ((! note
9892 || INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
9893 ? insn : JUMP_LABEL (insn));
9894 /* On the likely path, the branch costs 1, on the unlikely path,
9898 target = next_active_insn (target);
9899 while (target && ! flow_dependent_p (target, dep_insn)
9901 /* If two branches are executed in immediate succession, with the
9902 first branch properly predicted, this causes a stall at the
9903 second branch, hence we won't need the target for the
9904 second branch for two cycles after the launch of the first
9906 if (cost > orig_cost - 2)
9907 cost = orig_cost - 2;
9913 else if (get_attr_is_mac_media (insn)
9914 && get_attr_is_mac_media (dep_insn))
9917 else if (! reload_completed
9918 && GET_CODE (PATTERN (insn)) == SET
9919 && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT
9920 && GET_CODE (PATTERN (dep_insn)) == SET
9921 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode)
9924 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
9925 that is needed at the target. */
9926 else if (get_attr_type (insn) == TYPE_JUMP_MEDIA
9927 && ! flow_dependent_p (insn, dep_insn))
9930 else if (REG_NOTE_KIND (link) == 0)
9932 enum attr_type type;
9935 if (recog_memoized (insn) < 0
9936 || recog_memoized (dep_insn) < 0)
9939 dep_set = single_set (dep_insn);
9941 /* The latency that we specify in the scheduling description refers
9942 to the actual output, not to an auto-increment register; for that,
9943 the latency is one. */
9944 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9946 rtx set = single_set (insn);
9949 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9950 && (!MEM_P (SET_DEST (set))
9951 || !reg_mentioned_p (SET_DEST (dep_set),
9952 XEXP (SET_DEST (set), 0))))
9955 /* The only input for a call that is timing-critical is the
9956 function's address. */
9959 rtx call = PATTERN (insn);
9961 if (GET_CODE (call) == PARALLEL)
9962 call = XVECEXP (call, 0 ,0);
9963 if (GET_CODE (call) == SET)
9964 call = SET_SRC (call);
9965 if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
9966 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9967 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9968 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9969 cost -= TARGET_SH4_300 ? 3 : 6;
9971 /* Likewise, the most timing critical input for an sfuncs call
9972 is the function address. However, sfuncs typically start
9973 using their arguments pretty quickly.
9974 Assume a four cycle delay for SH4 before they are needed.
9975 Cached ST40-300 calls are quicker, so assume only a one
9977 ??? Maybe we should encode the delays till input registers
9978 are needed by sfuncs into the sfunc call insn. */
9979 /* All sfunc calls are parallels with at least four components.
9980 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9981 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9982 && XVECLEN (PATTERN (insn), 0) >= 4
9983 && (reg = sfunc_uses_reg (insn)))
9985 if (! reg_set_p (reg, dep_insn))
9986 cost -= TARGET_SH4_300 ? 1 : 4;
9988 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9990 enum attr_type dep_type = get_attr_type (dep_insn);
9992 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9994 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9995 && (type = get_attr_type (insn)) != TYPE_CALL
9996 && type != TYPE_SFUNC)
9998 /* When the preceding instruction loads the shift amount of
9999 the following SHAD/SHLD, the latency of the load is increased
10001 if (get_attr_type (insn) == TYPE_DYN_SHIFT
10002 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
10003 && reg_overlap_mentioned_p (SET_DEST (dep_set),
10004 XEXP (SET_SRC (single_set (insn)),
10007 /* When an LS group instruction with a latency of less than
10008 3 cycles is followed by a double-precision floating-point
10009 instruction, FIPR, or FTRV, the latency of the first
10010 instruction is increased to 3 cycles. */
10012 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
10013 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
10015 /* The lsw register of a double-precision computation is ready one
10017 else if (reload_completed
10018 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
10019 && (use_pat = single_set (insn))
10020 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
10021 SET_SRC (use_pat)))
10024 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
10025 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
10028 else if (TARGET_SH4_300)
10030 /* Stores need their input register two cycles later. */
10031 if (dep_set && cost >= 1
10032 && ((type = get_attr_type (insn)) == TYPE_STORE
10033 || type == TYPE_PSTORE
10034 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
10036 rtx set = single_set (insn);
10038 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
10039 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
10042 /* But don't reduce the cost below 1 if the address depends
10043 on a side effect of dep_insn. */
10045 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
10051 /* An anti-dependence penalty of two applies if the first insn is a double
10052 precision fadd / fsub / fmul. */
10053 else if (!TARGET_SH4_300
10054 && REG_NOTE_KIND (link) == REG_DEP_ANTI
10055 && recog_memoized (dep_insn) >= 0
10056 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
10057 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
10058 /* A lot of alleged anti-flow dependences are fake,
10059 so check this one is real. */
10060 && flow_dependent_p (dep_insn, insn))
10066 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10067 if DEP_INSN is anti-flow dependent on INSN. */
10069 flow_dependent_p (rtx insn, rtx dep_insn)
10071 rtx tmp = PATTERN (insn);
10073 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
10074 return tmp == NULL_RTX;
10077 /* A helper function for flow_dependent_p called through note_stores. */
10079 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10081 rtx * pinsn = (rtx *) data;
10083 if (*pinsn && reg_referenced_p (x, *pinsn))
10087 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10088 'special function' patterns (type sfunc) that clobber pr, but that
10089 do not look like function calls to leaf_function_p. Hence we must
10090 do this extra check. */
10092 sh_pr_n_sets (void)
10094 return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
10097 /* Return where to allocate pseudo for a given hard register initial
10100 sh_allocate_initial_value (rtx hard_reg)
10104 if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG))
10106 if (current_function_is_leaf
10107 && ! sh_pr_n_sets ()
10108 && ! (TARGET_SHCOMPACT
10109 && ((crtl->args.info.call_cookie
10110 & ~ CALL_COOKIE_RET_TRAMP (1))
10111 || crtl->saves_all_registers)))
10114 x = gen_frame_mem (Pmode, return_address_pointer_rtx);
10122 /* This function returns "2" to indicate dual issue for the SH4
10123 processor. To be used by the DFA pipeline description. */
10125 sh_issue_rate (void)
10127 if (TARGET_SUPERSCALAR)
10133 /* Functions for ready queue reordering for sched1. */
10135 /* Get weight for mode for a set x. */
10137 find_set_regmode_weight (rtx x, enum machine_mode mode)
10139 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
10141 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
10143 if (REG_P (SET_DEST (x)))
10145 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
10155 /* Get regmode weight for insn. */
10157 find_insn_regmode_weight (rtx insn, enum machine_mode mode)
10159 short reg_weight = 0;
10162 /* Increment weight for each register born here. */
10163 x = PATTERN (insn);
10164 reg_weight += find_set_regmode_weight (x, mode);
10165 if (GET_CODE (x) == PARALLEL)
10168 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
10170 x = XVECEXP (PATTERN (insn), 0, j);
10171 reg_weight += find_set_regmode_weight (x, mode);
10174 /* Decrement weight for each register that dies here. */
10175 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
10177 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
10179 rtx note = XEXP (x, 0);
10180 if (REG_P (note) && GET_MODE (note) == mode)
10187 /* Calculate regmode weights for all insns of a basic block. */
10189 find_regmode_weight (basic_block b, enum machine_mode mode)
10191 rtx insn, next_tail, head, tail;
10193 get_ebb_head_tail (b, b, &head, &tail);
10194 next_tail = NEXT_INSN (tail);
10196 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
10198 /* Handle register life information. */
10199 if (!INSN_P (insn))
10202 if (mode == SFmode)
10203 INSN_REGMODE_WEIGHT (insn, mode) =
10204 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DFmode);
10205 else if (mode == SImode)
10206 INSN_REGMODE_WEIGHT (insn, mode) =
10207 find_insn_regmode_weight (insn, mode) + 2 * find_insn_regmode_weight (insn, DImode);
10211 /* Comparison function for ready queue sorting. */
10213 rank_for_reorder (const void *x, const void *y)
10215 rtx tmp = *(const rtx *) y;
10216 rtx tmp2 = *(const rtx *) x;
10218 /* The insn in a schedule group should be issued the first. */
10219 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
10220 return SCHED_GROUP_P (tmp2) ? 1 : -1;
10222 /* If insns are equally good, sort by INSN_LUID (original insn order), This
10223 minimizes instruction movement, thus minimizing sched's effect on
10224 register pressure. */
10225 return INSN_LUID (tmp) - INSN_LUID (tmp2);
10228 /* Resort the array A in which only element at index N may be out of order. */
10230 swap_reorder (rtx *a, int n)
10232 rtx insn = a[n - 1];
10235 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
10243 #define SCHED_REORDER(READY, N_READY) \
10246 if ((N_READY) == 2) \
10247 swap_reorder (READY, N_READY); \
10248 else if ((N_READY) > 2) \
10249 qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
10253 /* Sort the ready list READY by ascending priority, using the SCHED_REORDER
10256 ready_reorder (rtx *ready, int nready)
10258 SCHED_REORDER (ready, nready);
10261 /* Count life regions of r0 for a block. */
10263 find_r0_life_regions (basic_block b)
10272 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
10283 insn = BB_HEAD (b);
10285 r0_reg = gen_rtx_REG (SImode, R0_REG);
10290 if (find_regno_note (insn, REG_DEAD, R0_REG))
10296 && (pset = single_set (insn))
10297 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
10298 && !find_regno_note (insn, REG_UNUSED, R0_REG))
10306 insn = NEXT_INSN (insn);
10308 return set - death;
10311 /* Calculate regmode weights for all insns of all basic block. */
10313 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
10314 int verbose ATTRIBUTE_UNUSED,
10319 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
10320 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
10321 r0_life_regions = 0;
10323 FOR_EACH_BB_REVERSE (b)
10325 find_regmode_weight (b, SImode);
10326 find_regmode_weight (b, SFmode);
10327 if (!reload_completed)
10328 r0_life_regions += find_r0_life_regions (b);
10331 CURR_REGMODE_PRESSURE (SImode) = 0;
10332 CURR_REGMODE_PRESSURE (SFmode) = 0;
10338 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
10339 int verbose ATTRIBUTE_UNUSED)
10341 if (regmode_weight[0])
10343 free (regmode_weight[0]);
10344 regmode_weight[0] = NULL;
10346 if (regmode_weight[1])
10348 free (regmode_weight[1]);
10349 regmode_weight[1] = NULL;
10353 /* The scalar modes supported differs from the default version in TImode
10354 for 32-bit SHMEDIA. */
10356 sh_scalar_mode_supported_p (enum machine_mode mode)
10358 if (TARGET_SHMEDIA32 && mode == TImode)
10361 return default_scalar_mode_supported_p (mode);
10364 /* Cache the can_issue_more so that we can return it from reorder2. Also,
10365 keep count of register pressures on SImode and SFmode. */
10367 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
10368 int sched_verbose ATTRIBUTE_UNUSED,
10370 int can_issue_more)
10372 if (GET_CODE (PATTERN (insn)) != USE
10373 && GET_CODE (PATTERN (insn)) != CLOBBER)
10374 cached_can_issue_more = can_issue_more - 1;
10376 cached_can_issue_more = can_issue_more;
10378 if (reload_completed)
10379 return cached_can_issue_more;
10381 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
10382 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
10384 return cached_can_issue_more;
10388 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
10389 int verbose ATTRIBUTE_UNUSED,
10390 int veclen ATTRIBUTE_UNUSED)
10392 CURR_REGMODE_PRESSURE (SImode) = 0;
10393 CURR_REGMODE_PRESSURE (SFmode) = 0;
10396 /* Some magic numbers. */
10397 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10398 functions that already have high pressure on r0. */
10399 #define R0_MAX_LIFE_REGIONS 2
10400 /* Register Pressure thresholds for SImode and SFmode registers. */
10401 #define SIMODE_MAX_WEIGHT 5
10402 #define SFMODE_MAX_WEIGHT 10
10404 /* Return true if the pressure is high for MODE. */
10406 high_pressure (enum machine_mode mode)
10408 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
10409 functions that already have high pressure on r0. */
10410 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
10413 if (mode == SFmode)
10414 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
10416 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
10419 /* Reorder ready queue if register pressure is high. */
10421 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
10422 int sched_verbose ATTRIBUTE_UNUSED,
10425 int clock_var ATTRIBUTE_UNUSED)
10427 if (reload_completed)
10428 return sh_issue_rate ();
10430 if (high_pressure (SFmode) || high_pressure (SImode))
10432 ready_reorder (ready, *n_readyp);
10435 return sh_issue_rate ();
10438 /* Skip cycles if the current register pressure is high. */
10440 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
10441 int sched_verbose ATTRIBUTE_UNUSED,
10442 rtx *ready ATTRIBUTE_UNUSED,
10443 int *n_readyp ATTRIBUTE_UNUSED,
10444 int clock_var ATTRIBUTE_UNUSED)
10446 if (reload_completed)
10447 return cached_can_issue_more;
10449 if (high_pressure(SFmode) || high_pressure (SImode))
10452 return cached_can_issue_more;
10455 /* Skip cycles without sorting the ready queue. This will move insn from
10456 Q->R. If this is the last cycle we are skipping; allow sorting of ready
10457 queue by sh_reorder. */
10459 /* Generally, skipping these many cycles are sufficient for all insns to move
10461 #define MAX_SKIPS 8
10464 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10465 int sched_verbose ATTRIBUTE_UNUSED,
10466 rtx insn ATTRIBUTE_UNUSED,
10467 int last_clock_var,
10471 if (reload_completed)
10476 if ((clock_var - last_clock_var) < MAX_SKIPS)
10481 /* If this is the last cycle we are skipping, allow reordering of R. */
10482 if ((clock_var - last_clock_var) == MAX_SKIPS)
10494 /* SHmedia requires registers for branches, so we can't generate new
10495 branches past reload. */
10497 sh_cannot_modify_jumps_p (void)
10499 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
10502 static enum reg_class
10503 sh_target_reg_class (void)
10505 return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
10509 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen)
10511 HARD_REG_SET dummy;
10516 if (! shmedia_space_reserved_for_target_registers)
10518 if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS)
10520 if (calc_live_regs (&dummy) >= 6 * 8)
10526 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10528 return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
10532 On the SH1..SH4, the trampoline looks like
10533 2 0002 D202 mov.l l2,r2
10534 1 0000 D301 mov.l l1,r3
10535 3 0004 422B jmp @r2
10537 5 0008 00000000 l1: .long area
10538 6 000c 00000000 l2: .long function
10540 SH5 (compact) uses r1 instead of r3 for the static chain. */
10543 /* Emit RTL insns to initialize the variable parts of a trampoline.
10544 FNADDR is an RTX for the address of the function's pure code.
10545 CXT is an RTX for the static chain value for the function. */
10548 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10550 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10551 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10553 if (TARGET_SHMEDIA64)
10558 rtx movi1 = GEN_INT (0xcc000010);
10559 rtx shori1 = GEN_INT (0xc8000010);
10562 /* The following trampoline works within a +- 128 KB range for cxt:
10563 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
10564 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
10565 gettr tr1,r1; blink tr0,r63 */
10566 /* Address rounding makes it hard to compute the exact bounds of the
10567 offset for this trampoline, but we have a rather generous offset
10568 range, so frame_offset should do fine as an upper bound. */
10569 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
10571 /* ??? could optimize this trampoline initialization
10572 by writing DImode words with two insns each. */
10573 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
10574 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
10575 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
10576 insn = gen_rtx_AND (DImode, insn, mask);
10577 /* Or in ptb/u .,tr1 pattern */
10578 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
10579 insn = force_operand (insn, NULL_RTX);
10580 insn = gen_lowpart (SImode, insn);
10581 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn);
10582 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
10583 insn = gen_rtx_AND (DImode, insn, mask);
10584 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
10585 insn = gen_lowpart (SImode, insn);
10586 emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn);
10587 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
10588 insn = gen_rtx_AND (DImode, insn, mask);
10589 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10590 insn = gen_lowpart (SImode, insn);
10591 emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn);
10592 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
10593 insn = gen_rtx_AND (DImode, insn, mask);
10594 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10595 insn = gen_lowpart (SImode, insn);
10596 emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn);
10597 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
10598 insn = gen_rtx_AND (DImode, insn, mask);
10599 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
10600 insn = gen_lowpart (SImode, insn);
10601 emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn);
10602 emit_move_insn (adjust_address (tramp_mem, SImode, 20),
10603 GEN_INT (0x6bf10600));
10604 emit_move_insn (adjust_address (tramp_mem, SImode, 24),
10605 GEN_INT (0x4415fc10));
10606 emit_move_insn (adjust_address (tramp_mem, SImode, 28),
10607 GEN_INT (0x4401fff0));
10608 emit_insn (gen_ic_invalidate_line (tramp));
10611 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
10612 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
10614 tramp_templ = gen_datalabel_ref (tramp_templ);
10616 src = gen_const_mem (BLKmode, tramp_templ);
10617 set_mem_align (dst, 256);
10618 set_mem_align (src, 64);
10619 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
10621 emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr);
10622 emit_move_insn (adjust_address (tramp_mem, Pmode,
10623 fixed_len + GET_MODE_SIZE (Pmode)),
10625 emit_insn (gen_ic_invalidate_line (tramp));
10628 else if (TARGET_SHMEDIA)
10630 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
10631 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
10632 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
10633 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
10634 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
10635 rotated 10 right, and higher 16 bit of every 32 selected. */
10637 = force_reg (V2HImode, (simplify_gen_subreg
10638 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
10639 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
10640 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
10642 fnaddr = force_reg (SImode, fnaddr);
10643 cxt = force_reg (SImode, cxt);
10644 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
10645 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
10647 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
10648 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10649 emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
10650 emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0);
10651 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
10652 gen_rtx_SUBREG (V2HImode, cxt, 0),
10654 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
10655 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
10656 emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
10657 if (TARGET_LITTLE_ENDIAN)
10659 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
10660 emit_insn (gen_mextr4 (quad2, cxtload, blink));
10664 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
10665 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
10667 emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1);
10668 emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2);
10669 emit_insn (gen_ic_invalidate_line (tramp));
10672 else if (TARGET_SHCOMPACT)
10674 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
10677 emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
10678 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
10680 emit_move_insn (adjust_address (tramp_mem, SImode, 4),
10681 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
10683 emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
10684 emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
10685 if (TARGET_HARVARD)
10687 if (!TARGET_INLINE_IC_INVALIDATE
10688 || (!(TARGET_SH4A_ARCH || TARGET_SH4_300) && TARGET_USERMODE))
10689 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10690 FUNCTION_ORDINARY),
10691 LCT_NORMAL, VOIDmode, 1, tramp, SImode);
10693 emit_insn (gen_ic_invalidate_line (tramp));
10697 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10700 sh_trampoline_adjust_address (rtx tramp)
10702 if (TARGET_SHMEDIA)
10703 tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx,
10704 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN);
10708 /* FIXME: This is overly conservative. A SHcompact function that
10709 receives arguments ``by reference'' will have them stored in its
10710 own stack frame, so it must not pass pointers or references to
10711 these arguments to other functions by means of sibling calls. */
10712 /* If PIC, we cannot make sibling calls to global functions
10713 because the PLT requires r12 to be live. */
10715 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10718 && (! TARGET_SHCOMPACT
10719 || crtl->args.info.stack_regs == 0)
10720 && ! sh_cfun_interrupt_handler_p ()
10722 || (decl && ! TREE_PUBLIC (decl))
10723 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10726 /* Machine specific built-in functions. */
10728 struct builtin_description
10730 const enum insn_code icode;
10731 const char *const name;
10736 /* describe number and signedness of arguments; arg[0] == result
10737 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10738 /* 9: 64-bit pointer, 10: 32-bit pointer */
10739 static const char signature_args[][4] =
10741 #define SH_BLTIN_V2SI2 0
10743 #define SH_BLTIN_V4HI2 1
10745 #define SH_BLTIN_V2SI3 2
10747 #define SH_BLTIN_V4HI3 3
10749 #define SH_BLTIN_V8QI3 4
10751 #define SH_BLTIN_MAC_HISI 5
10753 #define SH_BLTIN_SH_HI 6
10755 #define SH_BLTIN_SH_SI 7
10757 #define SH_BLTIN_V4HI2V2SI 8
10759 #define SH_BLTIN_V4HI2V8QI 9
10761 #define SH_BLTIN_SISF 10
10763 #define SH_BLTIN_LDUA_L 11
10765 #define SH_BLTIN_LDUA_Q 12
10767 #define SH_BLTIN_STUA_L 13
10769 #define SH_BLTIN_STUA_Q 14
10771 #define SH_BLTIN_LDUA_L64 15
10773 #define SH_BLTIN_LDUA_Q64 16
10775 #define SH_BLTIN_STUA_L64 17
10777 #define SH_BLTIN_STUA_Q64 18
10779 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10780 #define SH_BLTIN_2 19
10781 #define SH_BLTIN_SU 19
10783 #define SH_BLTIN_3 20
10784 #define SH_BLTIN_SUS 20
10786 #define SH_BLTIN_PSSV 21
10788 #define SH_BLTIN_XXUU 22
10789 #define SH_BLTIN_UUUU 22
10791 #define SH_BLTIN_PV 23
10794 /* mcmv: operands considered unsigned. */
10795 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10796 /* mperm: control value considered unsigned int. */
10797 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10798 /* mshards_q: returns signed short. */
10799 /* nsb: takes long long arg, returns unsigned char. */
10800 static struct builtin_description bdesc[] =
10802 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 },
10803 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 },
10804 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 },
10805 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 },
10806 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 },
10807 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 },
10808 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 },
10809 { CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 },
10810 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 },
10811 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 },
10812 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 },
10813 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 },
10814 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 },
10815 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 },
10816 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 },
10817 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 },
10818 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 },
10819 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 },
10820 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 },
10821 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 },
10822 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 },
10823 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 },
10824 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 },
10825 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 },
10826 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 },
10827 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 },
10828 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 },
10829 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 },
10830 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 },
10831 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 },
10832 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 },
10833 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 },
10834 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 },
10835 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 },
10836 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 },
10837 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 },
10838 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 },
10839 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 },
10840 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 },
10841 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 },
10842 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 },
10843 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 },
10844 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 },
10845 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 },
10846 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 },
10847 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 },
10848 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 },
10849 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 },
10850 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 },
10851 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 },
10852 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 },
10853 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 },
10854 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 },
10855 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 },
10856 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 },
10857 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 },
10858 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 },
10859 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 },
10860 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 },
10861 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 },
10862 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 },
10863 { CODE_FOR_mac_media, "__builtin_sh_media_FMAC_S", SH_BLTIN_3, 0 },
10864 { CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 },
10865 { CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 },
10866 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 },
10867 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 },
10868 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 },
10869 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 },
10870 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 },
10871 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 },
10872 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 },
10873 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 },
10874 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 },
10875 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 },
10876 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 },
10877 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 },
10878 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 },
10879 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 },
10880 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 },
10881 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 },
10882 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 },
10883 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 },
10884 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 },
10885 { CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 },
10889 sh_media_init_builtins (void)
10891 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10892 struct builtin_description *d;
10894 memset (shared, 0, sizeof shared);
10895 for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
10897 tree type, arg_type = 0;
10898 int signature = d->signature;
10901 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10902 type = shared[signature];
10905 int has_result = signature_args[signature][0] != 0;
10907 if ((signature_args[signature][1] & 8)
10908 && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32)
10909 || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64)))
10911 if (! TARGET_FPU_ANY
10912 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10914 type = void_list_node;
10917 int arg = signature_args[signature][i];
10918 int opno = i - 1 + has_result;
10921 arg_type = ptr_type_node;
10923 arg_type = (*lang_hooks.types.type_for_mode)
10924 (insn_data[d->icode].operand[opno].mode,
10929 arg_type = void_type_node;
10932 type = tree_cons (NULL_TREE, arg_type, type);
10934 type = build_function_type (arg_type, type);
10935 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10936 shared[signature] = type;
10939 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10944 /* Returns the shmedia builtin decl for CODE. */
10947 sh_media_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10949 if (code >= ARRAY_SIZE (bdesc))
10950 return error_mark_node;
10952 return bdesc[code].fndecl;
10955 /* Implements target hook vector_mode_supported_p. */
10957 sh_vector_mode_supported_p (enum machine_mode mode)
10960 && ((mode == V2SFmode)
10961 || (mode == V4SFmode)
10962 || (mode == V16SFmode)))
10965 else if (TARGET_SHMEDIA
10966 && ((mode == V8QImode)
10967 || (mode == V2HImode)
10968 || (mode == V4HImode)
10969 || (mode == V2SImode)))
10976 sh_frame_pointer_required (void)
10978 /* If needed override this in other tm.h files to cope with various OS
10979 lossage requiring a frame pointer. */
10980 if (SUBTARGET_FRAME_POINTER_REQUIRED)
10989 /* Implements target hook dwarf_calling_convention. Return an enum
10990 of dwarf_calling_convention. */
10992 sh_dwarf_calling_convention (const_tree func)
10994 if (sh_attr_renesas_p (func))
10995 return DW_CC_GNU_renesas_sh;
10997 return DW_CC_normal;
11001 sh_init_builtins (void)
11003 if (TARGET_SHMEDIA)
11004 sh_media_init_builtins ();
11007 /* Returns the sh builtin decl for CODE. */
11010 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11012 if (TARGET_SHMEDIA)
11013 return sh_media_builtin_decl (code, initialize_p);
11015 return error_mark_node;
11018 /* Expand an expression EXP that calls a built-in function,
11019 with result going to TARGET if that's convenient
11020 (and in mode MODE if that's convenient).
11021 SUBTARGET may be used as the target for computing one of EXP's operands.
11022 IGNORE is nonzero if the value is to be ignored. */
11025 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11026 enum machine_mode mode ATTRIBUTE_UNUSED, int ignore)
11028 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11029 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
11030 const struct builtin_description *d = &bdesc[fcode];
11031 enum insn_code icode = d->icode;
11032 int signature = d->signature;
11033 enum machine_mode tmode = VOIDmode;
11038 if (signature_args[signature][0])
11043 tmode = insn_data[icode].operand[0].mode;
11045 || GET_MODE (target) != tmode
11046 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11047 target = gen_reg_rtx (tmode);
11048 op[nop++] = target;
11053 for (i = 1; i <= 3; i++, nop++)
11056 enum machine_mode opmode, argmode;
11059 if (! signature_args[signature][i])
11061 arg = CALL_EXPR_ARG (exp, i - 1);
11062 if (arg == error_mark_node)
11064 if (signature_args[signature][i] & 8)
11067 optype = ptr_type_node;
11071 opmode = insn_data[icode].operand[nop].mode;
11072 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
11074 argmode = TYPE_MODE (TREE_TYPE (arg));
11075 if (argmode != opmode)
11076 arg = build1 (NOP_EXPR, optype, arg);
11077 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
11078 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
11079 op[nop] = copy_to_mode_reg (opmode, op[nop]);
11085 pat = (*insn_data[d->icode].genfun) (op[0]);
11088 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
11091 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
11094 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
11097 gcc_unreachable ();
11106 sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1)
11108 rtx sel0 = const0_rtx;
11109 rtx sel1 = const1_rtx;
11110 rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op;
11111 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
11113 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
11114 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
11118 sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
11120 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
11122 emit_insn (gen_binary_sf_op0 (op0, op1, op2, op));
11123 emit_insn (gen_binary_sf_op1 (op0, op1, op2, op));
11126 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
11127 We can allow any mode in any general register. The special registers
11128 only allow SImode. Don't allow any mode in the PR.
11130 We cannot hold DCmode values in the XD registers because alter_reg
11131 handles subregs of them incorrectly. We could work around this by
11132 spacing the XD registers like the DR registers, but this would require
11133 additional memory in every compilation to hold larger register vectors.
11134 We could hold SFmode / SCmode values in XD registers, but that
11135 would require a tertiary reload when reloading from / to memory,
11136 and a secondary reload to reload from / to general regs; that
11137 seems to be a loosing proposition.
11139 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
11140 it won't be ferried through GP registers first. */
11143 sh_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11145 if (SPECIAL_REGISTER_P (regno))
11146 return mode == SImode;
11148 if (regno == FPUL_REG)
11149 return (mode == SImode || mode == SFmode);
11151 if (FP_REGISTER_P (regno) && mode == SFmode)
11154 if (mode == V2SFmode)
11156 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
11157 || GENERAL_REGISTER_P (regno)))
11163 if (mode == V4SFmode)
11165 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
11166 || GENERAL_REGISTER_P (regno))
11172 if (mode == V16SFmode)
11174 if (TARGET_SHMEDIA)
11176 if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0)
11182 return regno == FIRST_XD_REG;
11185 if (FP_REGISTER_P (regno))
11189 || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode)
11190 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
11193 && (mode == DFmode || mode == DImode
11194 || mode == V2SFmode || mode == TImode)))
11195 && ((regno - FIRST_FP_REG) & 1) == 0)
11196 || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode
11197 && ((regno - FIRST_FP_REG) & 3) == 0))
11203 if (XD_REGISTER_P (regno))
11204 return mode == DFmode;
11206 if (TARGET_REGISTER_P (regno))
11207 return (mode == DImode || mode == SImode || mode == PDImode);
11209 if (regno == PR_REG)
11210 return mode == SImode;
11212 if (regno == FPSCR_REG)
11213 return mode == PSImode;
11215 /* FIXME. This works around PR target/37633 for -O0. */
11216 if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4)
11218 unsigned int n = GET_MODE_SIZE (mode) / 8;
11220 if (regno >= FIRST_GENERAL_REG + 10 - n + 1
11221 && regno <= FIRST_GENERAL_REG + 14)
11228 /* Return the class of registers for which a mode change from FROM to TO
11231 sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
11232 enum reg_class rclass)
11234 /* We want to enable the use of SUBREGs as a means to
11235 VEC_SELECT a single element of a vector. */
11236 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
11237 return (reg_classes_intersect_p (GENERAL_REGS, rclass));
11239 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
11241 if (TARGET_LITTLE_ENDIAN)
11243 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
11244 return reg_classes_intersect_p (DF_REGS, rclass);
11248 if (GET_MODE_SIZE (from) < 8)
11249 return reg_classes_intersect_p (DF_HI_REGS, rclass);
11255 /* Return true if registers in machine mode MODE will likely be
11256 allocated to registers in small register classes. */
11259 sh_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
11261 return (! TARGET_SHMEDIA);
11264 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
11265 that label is used. */
11268 sh_mark_label (rtx address, int nuses)
11270 if (GOTOFF_P (address))
11272 /* Extract the label or symbol. */
11273 address = XEXP (address, 0);
11274 if (GET_CODE (address) == PLUS)
11275 address = XEXP (address, 0);
11276 address = XVECEXP (address, 0, 0);
11278 if (GET_CODE (address) == LABEL_REF
11279 && LABEL_P (XEXP (address, 0)))
11280 LABEL_NUSES (XEXP (address, 0)) += nuses;
11283 /* Compute extra cost of moving data between one register class
11286 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
11287 uses this information. Hence, the general register <-> floating point
11288 register information here is not used for SFmode. */
11291 sh_register_move_cost (enum machine_mode mode,
11292 enum reg_class srcclass, enum reg_class dstclass)
11294 if (dstclass == T_REGS || dstclass == PR_REGS)
11297 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
11300 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
11301 && REGCLASS_HAS_FP_REG (srcclass)
11302 && REGCLASS_HAS_FP_REG (dstclass))
11305 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
11306 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
11308 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
11309 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
11312 if ((REGCLASS_HAS_FP_REG (dstclass)
11313 && REGCLASS_HAS_GENERAL_REG (srcclass))
11314 || (REGCLASS_HAS_GENERAL_REG (dstclass)
11315 && REGCLASS_HAS_FP_REG (srcclass)))
11316 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
11317 * ((GET_MODE_SIZE (mode) + 7) / 8U));
11319 if ((dstclass == FPUL_REGS
11320 && REGCLASS_HAS_GENERAL_REG (srcclass))
11321 || (srcclass == FPUL_REGS
11322 && REGCLASS_HAS_GENERAL_REG (dstclass)))
11325 if ((dstclass == FPUL_REGS
11326 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
11327 || (srcclass == FPUL_REGS
11328 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
11331 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11332 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11335 /* ??? ptabs faults on (value & 0x3) == 0x3 */
11337 && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS))
11339 if (sh_gettrcost >= 0)
11340 return sh_gettrcost;
11341 else if (!TARGET_PT_FIXED)
11345 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
11346 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
11351 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
11352 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
11353 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
11355 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
11358 static rtx emit_load_ptr (rtx, rtx);
11361 emit_load_ptr (rtx reg, rtx addr)
11363 rtx mem = gen_const_mem (ptr_mode, addr);
11365 if (Pmode != ptr_mode)
11366 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
11367 return emit_move_insn (reg, mem);
11371 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11372 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11375 CUMULATIVE_ARGS cum;
11376 int structure_value_byref = 0;
11377 rtx this_rtx, this_value, sibcall, insns, funexp;
11378 tree funtype = TREE_TYPE (function);
11379 int simple_add = CONST_OK_FOR_ADD (delta);
11381 rtx scratch0, scratch1, scratch2;
11384 reload_completed = 1;
11385 epilogue_completed = 1;
11386 current_function_uses_only_leaf_regs = 1;
11388 emit_note (NOTE_INSN_PROLOGUE_END);
11390 /* Find the "this" pointer. We have such a wide range of ABIs for the
11391 SH that it's best to do this completely machine independently.
11392 "this" is passed as first argument, unless a structure return pointer
11393 comes first, in which case "this" comes second. */
11394 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
11395 #ifndef PCC_STATIC_STRUCT_RETURN
11396 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11397 structure_value_byref = 1;
11398 #endif /* not PCC_STATIC_STRUCT_RETURN */
11399 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
11401 tree ptype = build_pointer_type (TREE_TYPE (funtype));
11403 FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
11405 this_rtx = FUNCTION_ARG (cum, Pmode, ptr_type_node, 1);
11407 /* For SHcompact, we only have r0 for a scratch register: r1 is the
11408 static chain pointer (even if you can't have nested virtual functions
11409 right now, someone might implement them sometime), and the rest of the
11410 registers are used for argument passing, are callee-saved, or reserved. */
11411 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
11412 -ffixed-reg has been used. */
11413 if (! call_used_regs[0] || fixed_regs[0])
11414 error ("r0 needs to be available as a call-clobbered register");
11415 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
11418 if (call_used_regs[1] && ! fixed_regs[1])
11419 scratch1 = gen_rtx_REG (ptr_mode, 1);
11420 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
11421 pointing where to return struct values. */
11422 if (call_used_regs[3] && ! fixed_regs[3])
11423 scratch2 = gen_rtx_REG (Pmode, 3);
11425 else if (TARGET_SHMEDIA)
11427 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
11428 if (i != REGNO (scratch0) &&
11429 call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i))
11431 scratch1 = gen_rtx_REG (ptr_mode, i);
11434 if (scratch1 == scratch0)
11435 error ("Need a second call-clobbered general purpose register");
11436 for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++)
11437 if (call_used_regs[i] && ! fixed_regs[i])
11439 scratch2 = gen_rtx_REG (Pmode, i);
11442 if (scratch2 == scratch0)
11443 error ("Need a call-clobbered target register");
11446 this_value = plus_constant (this_rtx, delta);
11448 && (simple_add || scratch0 != scratch1)
11449 && strict_memory_address_p (ptr_mode, this_value))
11451 emit_load_ptr (scratch0, this_value);
11456 ; /* Do nothing. */
11457 else if (simple_add)
11458 emit_move_insn (this_rtx, this_value);
11461 emit_move_insn (scratch1, GEN_INT (delta));
11462 emit_insn (gen_add2_insn (this_rtx, scratch1));
11470 emit_load_ptr (scratch0, this_rtx);
11472 offset_addr = plus_constant (scratch0, vcall_offset);
11473 if (strict_memory_address_p (ptr_mode, offset_addr))
11474 ; /* Do nothing. */
11475 else if (! TARGET_SH5 && scratch0 != scratch1)
11477 /* scratch0 != scratch1, and we have indexed loads. Get better
11478 schedule by loading the offset into r1 and using an indexed
11479 load - then the load of r1 can issue before the load from
11480 (this_rtx + delta) finishes. */
11481 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11482 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
11484 else if (CONST_OK_FOR_ADD (vcall_offset))
11486 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
11487 offset_addr = scratch0;
11489 else if (scratch0 != scratch1)
11491 emit_move_insn (scratch1, GEN_INT (vcall_offset));
11492 emit_insn (gen_add2_insn (scratch0, scratch1));
11493 offset_addr = scratch0;
11496 gcc_unreachable (); /* FIXME */
11497 emit_load_ptr (scratch0, offset_addr);
11499 if (Pmode != ptr_mode)
11500 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
11501 emit_insn (gen_add2_insn (this_rtx, scratch0));
11504 /* Generate a tail call to the target function. */
11505 if (! TREE_USED (function))
11507 assemble_external (function);
11508 TREE_USED (function) = 1;
11510 funexp = XEXP (DECL_RTL (function), 0);
11511 /* If the function is overridden, so is the thunk, hence we don't
11512 need GOT addressing even if this is a public symbol. */
11514 if (TARGET_SH1 && ! flag_weak)
11515 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
11518 if (TARGET_SH2 && flag_pic)
11520 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
11521 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
11525 if (TARGET_SHMEDIA && flag_pic)
11527 funexp = gen_sym2PIC (funexp);
11528 PUT_MODE (funexp, Pmode);
11530 emit_move_insn (scratch2, funexp);
11531 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
11532 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
11534 sibcall = emit_call_insn (sibcall);
11535 SIBLING_CALL_P (sibcall) = 1;
11536 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
11539 /* Run just enough of rest_of_compilation to do scheduling and get
11540 the insns emitted. Note that use_thunk calls
11541 assemble_start_function and assemble_end_function. */
11543 insn_locators_alloc ();
11544 insns = get_insns ();
11550 split_all_insns_noflow ();
11555 if (optimize > 0 && flag_delayed_branch)
11556 dbr_schedule (insns);
11558 shorten_branches (insns);
11559 final_start_function (insns, file, 1);
11560 final (insns, file, 1);
11561 final_end_function ();
11563 reload_completed = 0;
11564 epilogue_completed = 0;
11568 function_symbol (rtx target, const char *name, enum sh_function_kind kind)
11572 /* If this is not an ordinary function, the name usually comes from a
11573 string literal or an sprintf buffer. Make sure we use the same
11574 string consistently, so that cse will be able to unify address loads. */
11575 if (kind != FUNCTION_ORDINARY)
11576 name = IDENTIFIER_POINTER (get_identifier (name));
11577 sym = gen_rtx_SYMBOL_REF (Pmode, name);
11578 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
11582 case FUNCTION_ORDINARY:
11586 rtx reg = target ? target : gen_reg_rtx (Pmode);
11588 emit_insn (gen_symGOT2reg (reg, sym));
11594 /* ??? To allow cse to work, we use GOTOFF relocations.
11595 we could add combiner patterns to transform this into
11596 straight pc-relative calls with sym2PIC / bsrf when
11597 label load and function call are still 1:1 and in the
11598 same basic block during combine. */
11599 rtx reg = target ? target : gen_reg_rtx (Pmode);
11601 emit_insn (gen_symGOTOFF2reg (reg, sym));
11606 if (target && sym != target)
11608 emit_move_insn (target, sym);
11614 /* Find the number of a general purpose register in S. */
11616 scavenge_reg (HARD_REG_SET *s)
11619 for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11620 if (TEST_HARD_REG_BIT (*s, r))
11626 sh_get_pr_initial_val (void)
11630 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
11631 PR register on SHcompact, because it might be clobbered by the prologue.
11632 We check first if that is known to be the case. */
11633 if (TARGET_SHCOMPACT
11634 && ((crtl->args.info.call_cookie
11635 & ~ CALL_COOKIE_RET_TRAMP (1))
11636 || crtl->saves_all_registers))
11637 return gen_frame_mem (SImode, return_address_pointer_rtx);
11639 /* If we haven't finished rtl generation, there might be a nonlocal label
11640 that we haven't seen yet.
11641 ??? get_hard_reg_initial_val fails if it is called after register
11642 allocation has started, unless it has been called before for the
11643 same register. And even then, we end in trouble if we didn't use
11644 the register in the same basic block before. So call
11645 get_hard_reg_initial_val now and wrap it in an unspec if we might
11646 need to replace it. */
11647 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11648 combine can put the pseudo returned by get_hard_reg_initial_val into
11649 instructions that need a general purpose registers, which will fail to
11650 be recognized when the pseudo becomes allocated to PR. */
11652 = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
11654 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11659 sh_expand_t_scc (rtx operands[])
11661 enum rtx_code code = GET_CODE (operands[1]);
11662 rtx target = operands[0];
11663 rtx op0 = operands[2];
11664 rtx op1 = operands[3];
11665 rtx result = target;
11668 if (!REG_P (op0) || REGNO (op0) != T_REG
11669 || !CONST_INT_P (op1))
11671 if (!REG_P (result))
11672 result = gen_reg_rtx (SImode);
11673 val = INTVAL (op1);
11674 if ((code == EQ && val == 1) || (code == NE && val == 0))
11675 emit_insn (gen_movt (result));
11676 else if (TARGET_SH2A && ((code == EQ && val == 0)
11677 || (code == NE && val == 1)))
11678 emit_insn (gen_xorsi3_movrt (result));
11679 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11681 emit_clobber (result);
11682 emit_insn (gen_subc (result, result, result));
11683 emit_insn (gen_addsi3 (result, result, const1_rtx));
11685 else if (code == EQ || code == NE)
11686 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11689 if (result != target)
11690 emit_move_insn (target, result);
11694 /* INSN is an sfunc; return the rtx that describes the address used. */
11696 extract_sfunc_addr (rtx insn)
11698 rtx pattern, part = NULL_RTX;
11701 pattern = PATTERN (insn);
11702 len = XVECLEN (pattern, 0);
11703 for (i = 0; i < len; i++)
11705 part = XVECEXP (pattern, 0, i);
11706 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11707 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11708 return XEXP (part, 0);
11710 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11711 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11714 /* Verify that the register in use_sfunc_addr still agrees with the address
11715 used in the sfunc. This prevents fill_slots_from_thread from changing
11717 INSN is the use_sfunc_addr instruction, and REG is the register it
11720 check_use_sfunc_addr (rtx insn, rtx reg)
11722 /* Search for the sfunc. It should really come right after INSN. */
11723 while ((insn = NEXT_INSN (insn)))
11725 if (LABEL_P (insn) || JUMP_P (insn))
11727 if (! INSN_P (insn))
11730 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11731 insn = XVECEXP (PATTERN (insn), 0, 0);
11732 if (GET_CODE (PATTERN (insn)) != PARALLEL
11733 || get_attr_type (insn) != TYPE_SFUNC)
11735 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11737 gcc_unreachable ();
11740 /* This function returns a constant rtx that represents pi / 2**15 in
11741 SFmode. it's used to scale SFmode angles, in radians, to a
11742 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11743 maps to 0x10000). */
11745 static GTY(()) rtx sh_fsca_sf2int_rtx;
11748 sh_fsca_sf2int (void)
11750 if (! sh_fsca_sf2int_rtx)
11752 REAL_VALUE_TYPE rv;
11754 real_from_string (&rv, "10430.378350470453");
11755 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11758 return sh_fsca_sf2int_rtx;
11761 /* This function returns a constant rtx that represents pi / 2**15 in
11762 DFmode. it's used to scale DFmode angles, in radians, to a
11763 fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
11764 maps to 0x10000). */
11766 static GTY(()) rtx sh_fsca_df2int_rtx;
11769 sh_fsca_df2int (void)
11771 if (! sh_fsca_df2int_rtx)
11773 REAL_VALUE_TYPE rv;
11775 real_from_string (&rv, "10430.378350470453");
11776 sh_fsca_df2int_rtx = const_double_from_real_value (rv, DFmode);
11779 return sh_fsca_df2int_rtx;
11782 /* This function returns a constant rtx that represents 2**15 / pi in
11783 SFmode. it's used to scale a fixed-point signed 16.16-bit fraction
11784 of a full circle back to a SFmode value, i.e., 0x10000 maps to
11787 static GTY(()) rtx sh_fsca_int2sf_rtx;
11790 sh_fsca_int2sf (void)
11792 if (! sh_fsca_int2sf_rtx)
11794 REAL_VALUE_TYPE rv;
11796 real_from_string (&rv, "9.587379924285257e-5");
11797 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11800 return sh_fsca_int2sf_rtx;
11803 /* Initialize the CUMULATIVE_ARGS structure. */
11806 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11808 rtx libname ATTRIBUTE_UNUSED,
11810 signed int n_named_args,
11811 enum machine_mode mode)
11813 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11814 pcum->free_single_fp_reg = 0;
11815 pcum->stack_regs = 0;
11816 pcum->byref_regs = 0;
11818 pcum->outgoing = (n_named_args == -1) ? 0 : 1;
11820 /* XXX - Should we check TARGET_HITACHI here ??? */
11821 pcum->renesas_abi = sh_attr_renesas_p (fntype) ? 1 : 0;
11825 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11826 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11827 pcum->prototype_p = TYPE_ARG_TYPES (fntype) ? TRUE : FALSE;
11828 pcum->arg_count [(int) SH_ARG_INT]
11829 = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl);
11832 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11833 && pcum->arg_count [(int) SH_ARG_INT] == 0
11834 && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
11835 ? int_size_in_bytes (TREE_TYPE (fntype))
11836 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4
11837 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype)))
11838 == FIRST_RET_REG));
11842 pcum->arg_count [(int) SH_ARG_INT] = 0;
11843 pcum->prototype_p = FALSE;
11844 if (mode != VOIDmode)
11846 pcum->call_cookie =
11847 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
11848 && GET_MODE_SIZE (mode) > 4
11849 && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG);
11851 /* If the default ABI is the Renesas ABI then all library
11852 calls must assume that the library will be using the
11853 Renesas ABI. So if the function would return its result
11854 in memory then we must force the address of this memory
11855 block onto the stack. Ideally we would like to call
11856 targetm.calls.return_in_memory() here but we do not have
11857 the TYPE or the FNDECL available so we synthesize the
11858 contents of that function as best we can. */
11860 (TARGET_DEFAULT & MASK_HITACHI)
11861 && (mode == BLKmode
11862 || (GET_MODE_SIZE (mode) > 4
11863 && !(mode == DFmode
11864 && TARGET_FPU_DOUBLE)));
11868 pcum->call_cookie = 0;
11869 pcum->force_mem = FALSE;
11874 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
11875 not enter into CONST_DOUBLE for the replace.
11877 Note that copying is not done so X must not be shared unless all copies
11878 are to be modified.
11880 This is like replace_rtx, except that we operate on N_REPLACEMENTS
11881 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
11882 replacements[n*2+1] - and that we take mode changes into account.
11884 If a replacement is ambiguous, return NULL_RTX.
11886 If MODIFY is zero, don't modify any rtl in place,
11887 just return zero or nonzero for failure / success. */
11890 replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
11895 /* The following prevents loops occurrence when we change MEM in
11896 CONST_DOUBLE onto the same CONST_DOUBLE. */
11897 if (x != 0 && GET_CODE (x) == CONST_DOUBLE)
11900 for (i = n_replacements - 1; i >= 0 ; i--)
11901 if (x == replacements[i*2] && GET_MODE (x) == GET_MODE (replacements[i*2+1]))
11902 return replacements[i*2+1];
11904 /* Allow this function to make replacements in EXPR_LISTs. */
11908 if (GET_CODE (x) == SUBREG)
11910 rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
11911 n_replacements, modify);
11913 if (CONST_INT_P (new_rtx))
11915 x = simplify_subreg (GET_MODE (x), new_rtx,
11916 GET_MODE (SUBREG_REG (x)),
11922 SUBREG_REG (x) = new_rtx;
11926 else if (REG_P (x))
11928 unsigned regno = REGNO (x);
11929 unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
11930 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11931 rtx result = NULL_RTX;
11933 for (i = n_replacements - 1; i >= 0; i--)
11935 rtx from = replacements[i*2];
11936 rtx to = replacements[i*2+1];
11937 unsigned from_regno, from_nregs, to_regno, new_regno;
11941 from_regno = REGNO (from);
11942 from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
11943 ? HARD_REGNO_NREGS (from_regno, GET_MODE (from)) : 1);
11944 if (regno < from_regno + from_nregs && regno + nregs > from_regno)
11946 if (regno < from_regno
11947 || regno + nregs > from_regno + nregs
11951 to_regno = REGNO (to);
11952 if (to_regno < FIRST_PSEUDO_REGISTER)
11954 new_regno = regno + to_regno - from_regno;
11955 if ((unsigned) HARD_REGNO_NREGS (new_regno, GET_MODE (x))
11958 result = gen_rtx_REG (GET_MODE (x), new_regno);
11960 else if (GET_MODE (x) <= GET_MODE (to))
11961 result = gen_lowpart_common (GET_MODE (x), to);
11963 result = gen_lowpart_SUBREG (GET_MODE (x), to);
11966 return result ? result : x;
11968 else if (GET_CODE (x) == ZERO_EXTEND)
11970 rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
11971 n_replacements, modify);
11973 if (CONST_INT_P (new_rtx))
11975 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
11976 new_rtx, GET_MODE (XEXP (x, 0)));
11981 XEXP (x, 0) = new_rtx;
11986 fmt = GET_RTX_FORMAT (GET_CODE (x));
11987 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
11993 new_rtx = replace_n_hard_rtx (XEXP (x, i), replacements,
11994 n_replacements, modify);
11998 XEXP (x, i) = new_rtx;
12000 else if (fmt[i] == 'E')
12001 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12003 new_rtx = replace_n_hard_rtx (XVECEXP (x, i, j), replacements,
12004 n_replacements, modify);
12008 XVECEXP (x, i, j) = new_rtx;
12016 sh_gen_truncate (enum machine_mode mode, rtx x, int need_sign_ext)
12018 enum rtx_code code = TRUNCATE;
12020 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
12022 rtx inner = XEXP (x, 0);
12023 enum machine_mode inner_mode = GET_MODE (inner);
12025 if (inner_mode == mode)
12027 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
12029 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
12030 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
12032 code = GET_CODE (x);
12036 return gen_rtx_fmt_e (code, mode, x);
12039 /* called via for_each_rtx after reload, to clean up truncates of
12040 registers that span multiple actual hard registers. */
12042 shmedia_cleanup_truncate (rtx *p, void *n_changes)
12046 if (GET_CODE (x) != TRUNCATE)
12049 if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
12051 enum machine_mode reg_mode = GET_MODE (reg);
12052 XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
12053 subreg_lowpart_offset (DImode, reg_mode));
12054 *(int*) n_changes += 1;
12060 /* Load and store depend on the highpart of the address. However,
12061 set_attr_alternative does not give well-defined results before reload,
12062 so we must look at the rtl ourselves to see if any of the feeding
12063 registers is used in a memref. */
12065 /* Called by sh_contains_memref_p via for_each_rtx. */
12067 sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
12069 return (MEM_P (*loc));
12072 /* Return nonzero iff INSN contains a MEM. */
12074 sh_contains_memref_p (rtx insn)
12076 return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
12079 /* Return nonzero iff INSN loads a banked register. */
12081 sh_loads_bankedreg_p (rtx insn)
12083 if (GET_CODE (PATTERN (insn)) == SET)
12085 rtx op = SET_DEST (PATTERN(insn));
12086 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
12093 /* FNADDR is the MEM expression from a call expander. Return an address
12094 to use in an SHmedia insn pattern. */
12096 shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
12100 fnaddr = XEXP (fnaddr, 0);
12101 is_sym = GET_CODE (fnaddr) == SYMBOL_REF;
12102 if (flag_pic && is_sym)
12104 if (! SYMBOL_REF_LOCAL_P (fnaddr))
12106 rtx reg = gen_reg_rtx (Pmode);
12108 /* We must not use GOTPLT for sibcalls, because PIC_REG
12109 must be restored before the PLT code gets to run. */
12111 emit_insn (gen_symGOT2reg (reg, fnaddr));
12113 emit_insn (gen_symGOTPLT2reg (reg, fnaddr));
12118 fnaddr = gen_sym2PIC (fnaddr);
12119 PUT_MODE (fnaddr, Pmode);
12122 /* If ptabs might trap, make this visible to the rest of the compiler.
12123 We generally assume that symbols pertain to valid locations, but
12124 it is possible to generate invalid symbols with asm or linker tricks.
12125 In a list of functions where each returns its successor, an invalid
12126 symbol might denote an empty list. */
12127 if (!TARGET_PT_FIXED
12128 && (!is_sym || TARGET_INVALID_SYMBOLS)
12129 && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr))))
12131 rtx tr = gen_reg_rtx (PDImode);
12133 emit_insn (gen_ptabs (tr, fnaddr));
12136 else if (! target_reg_operand (fnaddr, Pmode))
12137 fnaddr = copy_to_mode_reg (Pmode, fnaddr);
12142 sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
12143 enum machine_mode mode, secondary_reload_info *sri)
12147 if (REGCLASS_HAS_FP_REG (rclass)
12148 && ! TARGET_SHMEDIA
12149 && immediate_operand ((x), mode)
12150 && ! ((fp_zero_operand (x) || fp_one_operand (x))
12151 && mode == SFmode && fldi_ok ()))
12155 sri->icode = CODE_FOR_reload_insf__frn;
12158 sri->icode = CODE_FOR_reload_indf__frn;
12161 /* ??? If we knew that we are in the appropriate mode -
12162 single precision - we could use a reload pattern directly. */
12167 if (rclass == FPUL_REGS
12169 && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
12170 || REGNO (x) == T_REG))
12171 || GET_CODE (x) == PLUS))
12172 return GENERAL_REGS;
12173 if (rclass == FPUL_REGS && immediate_operand (x, mode))
12175 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
12176 return GENERAL_REGS;
12177 else if (mode == SFmode)
12179 sri->icode = CODE_FOR_reload_insi__i_fpul;
12182 if (rclass == FPSCR_REGS
12183 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
12184 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
12185 return GENERAL_REGS;
12186 if (REGCLASS_HAS_FP_REG (rclass)
12188 && immediate_operand (x, mode)
12189 && x != CONST0_RTX (GET_MODE (x))
12190 && GET_MODE (x) != V4SFmode)
12191 return GENERAL_REGS;
12192 if ((mode == QImode || mode == HImode)
12193 && TARGET_SHMEDIA && inqhi_operand (x, mode))
12195 sri->icode = ((mode == QImode)
12196 ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi);
12199 if (TARGET_SHMEDIA && rclass == GENERAL_REGS
12200 && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x)))
12201 return TARGET_REGS;
12202 } /* end of input-only processing. */
12204 if (((REGCLASS_HAS_FP_REG (rclass)
12206 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
12207 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
12208 && TARGET_FMOVD))))
12209 || (REGCLASS_HAS_GENERAL_REG (rclass)
12211 && FP_REGISTER_P (REGNO (x))))
12212 && ! TARGET_SHMEDIA
12213 && (mode == SFmode || mode == SImode))
12215 if ((rclass == FPUL_REGS
12216 || (REGCLASS_HAS_FP_REG (rclass)
12217 && ! TARGET_SHMEDIA && mode == SImode))
12220 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
12221 || REGNO (x) == T_REG
12222 || system_reg_operand (x, VOIDmode)))))
12224 if (rclass == FPUL_REGS)
12225 return GENERAL_REGS;
12228 if ((rclass == TARGET_REGS
12229 || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
12230 && !satisfies_constraint_Csy (x)
12231 && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
12232 return GENERAL_REGS;
12233 if ((rclass == MAC_REGS || rclass == PR_REGS)
12234 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
12235 && rclass != REGNO_REG_CLASS (REGNO (x)))
12236 return GENERAL_REGS;
12237 if (rclass != GENERAL_REGS && REG_P (x)
12238 && TARGET_REGISTER_P (REGNO (x)))
12239 return GENERAL_REGS;
12243 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;