1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; Q -- Memory reference without index register and with short displacement.
51 ;; R -- Memory reference with index register and short displacement.
52 ;; S -- Memory reference without index register but with long displacement.
53 ;; T -- Memory reference with index register and long displacement.
54 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
55 ;; Offsettable memory reference of type specified by second letter.
56 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
57 ;; Memory reference of the type specified by second letter that
58 ;; does *not* refer to a literal pool entry.
59 ;; U -- Pointer with short displacement.
60 ;; W -- Pointer with long displacement.
61 ;; Y -- Shift count operand.
63 ;; Special formats used for outputting 390 instructions.
65 ;; %C: print opcode suffix for branch condition.
66 ;; %D: print opcode suffix for inverse branch condition.
67 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
68 ;; %O: print only the displacement of a memory reference.
69 ;; %R: print only the base register of a memory reference.
70 ;; %S: print S-type memory reference (base+displacement).
71 ;; %N: print the second word of a DImode operand.
72 ;; %M: print the second word of a TImode operand.
74 ;; %b: print integer X as if it's an unsigned byte.
75 ;; %x: print integer X as if it's an unsigned word.
76 ;; %h: print integer X as if it's a signed word.
77 ;; %i: print the first nonzero HImode part of X
78 ;; %j: print the first HImode part unequal to 0xffff of X
81 ;; We have a special constraint for pattern matching.
83 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
96 ; GOT/PLT and lt-relative accesses
97 (UNSPEC_LTREL_OFFSET 100)
98 (UNSPEC_LTREL_BASE 101)
106 (UNSPEC_RELOAD_BASE 210)
107 (UNSPEC_MAIN_BASE 211)
112 ; TLS relocation specifiers
117 (UNSPEC_GOTNTPOFF 504)
118 (UNSPEC_INDNTPOFF 505)
121 (UNSPEC_TLSLDM_NTPOFF 511)
122 (UNSPEC_TLS_LOAD 512)
127 ; Stack Smashing Protector
133 ;; UNSPEC_VOLATILE usage
141 (UNSPECV_TPF_PROLOGUE 20)
142 (UNSPECV_TPF_EPILOGUE 21)
146 (UNSPECV_POOL_SECTION 201)
147 (UNSPECV_POOL_ALIGN 202)
148 (UNSPECV_POOL_ENTRY 203)
149 (UNSPECV_MAIN_POOL 300)
165 ; Sibling call register.
167 ; Literal pool base register.
169 ; Return address register.
171 ; Condition code register.
173 ; Thread local storage pointer register.
178 ;; Instruction operand type as used in the Principles of Operation.
179 ;; Used to determine defaults for length and other attribute values.
181 (define_attr "op_type"
182 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
185 ;; Instruction type attribute used for scheduling.
187 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
188 cs,vs,store,sem,idiv,
189 imulhi,imulsi,imuldi,
190 branch,jsr,fsimpdf,fsimpsf,
191 floaddf,floadsf,fstoredf,fstoresf,
192 fmuldf,fmulsf,fdivdf,fdivsf,
193 ftoi,itof,fsqrtdf,fsqrtsf,
195 (cond [(eq_attr "op_type" "NN") (const_string "other")
196 (eq_attr "op_type" "SS") (const_string "cs")]
197 (const_string "integer")))
199 ;; Another attribute used for scheduling purposes:
200 ;; agen: Instruction uses the address generation unit
201 ;; reg: Instruction does not use the agen unit
203 (define_attr "atype" "agen,reg"
204 (cond [(eq_attr "op_type" "E") (const_string "reg")
205 (eq_attr "op_type" "RR") (const_string "reg")
206 (eq_attr "op_type" "RX") (const_string "agen")
207 (eq_attr "op_type" "RI") (const_string "reg")
208 (eq_attr "op_type" "RRE") (const_string "reg")
209 (eq_attr "op_type" "RS") (const_string "agen")
210 (eq_attr "op_type" "RSI") (const_string "agen")
211 (eq_attr "op_type" "S") (const_string "agen")
212 (eq_attr "op_type" "SI") (const_string "agen")
213 (eq_attr "op_type" "SS") (const_string "agen")
214 (eq_attr "op_type" "SSE") (const_string "agen")
215 (eq_attr "op_type" "RXE") (const_string "agen")
216 (eq_attr "op_type" "RSE") (const_string "agen")
217 (eq_attr "op_type" "RIL") (const_string "agen")
218 (eq_attr "op_type" "RXY") (const_string "agen")
219 (eq_attr "op_type" "RSY") (const_string "agen")
220 (eq_attr "op_type" "SIY") (const_string "agen")]
221 (const_string "agen")))
225 (define_attr "length" ""
226 (cond [(eq_attr "op_type" "E") (const_int 2)
227 (eq_attr "op_type" "RR") (const_int 2)
228 (eq_attr "op_type" "RX") (const_int 4)
229 (eq_attr "op_type" "RI") (const_int 4)
230 (eq_attr "op_type" "RRE") (const_int 4)
231 (eq_attr "op_type" "RS") (const_int 4)
232 (eq_attr "op_type" "RSI") (const_int 4)
233 (eq_attr "op_type" "S") (const_int 4)
234 (eq_attr "op_type" "SI") (const_int 4)
235 (eq_attr "op_type" "SS") (const_int 6)
236 (eq_attr "op_type" "SSE") (const_int 6)
237 (eq_attr "op_type" "RXE") (const_int 6)
238 (eq_attr "op_type" "RSE") (const_int 6)
239 (eq_attr "op_type" "RIL") (const_int 6)
240 (eq_attr "op_type" "RXY") (const_int 6)
241 (eq_attr "op_type" "RSY") (const_int 6)
242 (eq_attr "op_type" "SIY") (const_int 6)]
246 ;; Processor type. This attribute must exactly match the processor_type
247 ;; enumeration in s390.h. The current machine description does not
248 ;; distinguish between g5 and g6, but there are differences between the two
249 ;; CPUs could in theory be modeled.
251 (define_attr "cpu" "g5,g6,z900,z990"
252 (const (symbol_ref "s390_tune")))
254 ;; Pipeline description for z900. For lack of anything better,
255 ;; this description is also used for the g5 and g6.
258 ;; Pipeline description for z990.
262 (include "predicates.md")
269 ;; This mode macro allows DF and SF patterns to be generated from the
271 (define_mode_macro FPR [DF SF])
273 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
274 ;; from the same template.
275 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
276 (define_mode_macro DSI [DI SI])
278 ;; This mode macro allows :P to be used for patterns that operate on
279 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
280 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
282 ;; This mode macro allows the QI and HI patterns to be defined from
283 ;; the same template.
284 (define_mode_macro HQI [HI QI])
286 ;; This mode macro allows the integer patterns to be defined from the
288 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
290 ;; This macro allows to unify all 'bCOND' expander patterns.
291 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
292 ordered uneq unlt ungt unle unge ltgt])
294 ;; This macro allows to unify all 'sCOND' patterns.
295 (define_code_macro SCOND [ltu gtu leu geu])
297 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
298 ;; the same template.
299 (define_code_macro SHIFT [ashift lshiftrt])
302 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
303 ;; and "ltebr" in SFmode.
304 (define_mode_attr de [(DF "d") (SF "e")])
306 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
307 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
308 (define_mode_attr dee [(DF "d") (SF "ee")])
310 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
311 ;; 'ashift' and "srdl" in 'lshiftrt'.
312 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
314 ;; In SHIFT templates, this attribute holds the correct standard name for the
315 ;; pattern itself and the corresponding function calls.
316 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
318 ;; This attribute handles differences in the instruction 'type' and will result
319 ;; in "RRE" for DImode and "RR" for SImode.
320 (define_mode_attr E [(DI "E") (SI "")])
322 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
323 ;; and "lcr" in SImode.
324 (define_mode_attr g [(DI "g") (SI "")])
326 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
327 ;; and "cfdbr" in SImode.
328 (define_mode_attr gf [(DI "g") (SI "f")])
330 ;; ICM mask required to load MODE value into the highest subreg
331 ;; of a SImode register.
332 (define_mode_attr icm_hi [(HI "12") (QI "8")])
334 ;; ICM mask required to load MODE value into the lowest subreg
335 ;; of a SImode register.
336 (define_mode_attr icm_lo [(HI "3") (QI "1")])
338 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
339 ;; HImode and "llgc" in QImode.
340 (define_mode_attr hc [(HI "h") (QI "c")])
342 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
344 (define_mode_attr DBL [(DI "TI") (SI "DI")])
346 ;; Maximum unsigned integer that fits in MODE.
347 (define_mode_attr max_uint [(HI "65535") (QI "255")])
351 ;;- Compare instructions.
354 (define_expand "cmp<mode>"
355 [(set (reg:CC CC_REGNUM)
356 (compare:CC (match_operand:GPR 0 "register_operand" "")
357 (match_operand:GPR 1 "general_operand" "")))]
360 s390_compare_op0 = operands[0];
361 s390_compare_op1 = operands[1];
365 (define_expand "cmp<mode>"
366 [(set (reg:CC CC_REGNUM)
367 (compare:CC (match_operand:FPR 0 "register_operand" "")
368 (match_operand:FPR 1 "general_operand" "")))]
371 s390_compare_op0 = operands[0];
372 s390_compare_op1 = operands[1];
377 ; Test-under-Mask instructions
379 (define_insn "*tmqi_mem"
380 [(set (reg CC_REGNUM)
381 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
382 (match_operand:QI 1 "immediate_operand" "n,n"))
383 (match_operand:QI 2 "immediate_operand" "n,n")))]
384 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
388 [(set_attr "op_type" "SI,SIY")])
390 (define_insn "*tmdi_reg"
391 [(set (reg CC_REGNUM)
392 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
393 (match_operand:DI 1 "immediate_operand"
394 "N0HD0,N1HD0,N2HD0,N3HD0"))
395 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
397 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
398 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
404 [(set_attr "op_type" "RI")])
406 (define_insn "*tmsi_reg"
407 [(set (reg CC_REGNUM)
408 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
409 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
410 (match_operand:SI 2 "immediate_operand" "n,n")))]
411 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
412 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
416 [(set_attr "op_type" "RI")])
418 (define_insn "*tm<mode>_full"
419 [(set (reg CC_REGNUM)
420 (compare (match_operand:HQI 0 "register_operand" "d")
421 (match_operand:HQI 1 "immediate_operand" "n")))]
422 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
424 [(set_attr "op_type" "RI")])
427 ; Load-and-Test instructions
429 (define_insn "*tstdi_sign"
430 [(set (reg CC_REGNUM)
431 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
432 (const_int 32)) (const_int 32))
433 (match_operand:DI 1 "const0_operand" "")))
434 (set (match_operand:DI 2 "register_operand" "=d")
435 (sign_extend:DI (match_dup 0)))]
436 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
438 [(set_attr "op_type" "RRE")])
440 (define_insn "*tstdi"
441 [(set (reg CC_REGNUM)
442 (compare (match_operand:DI 0 "register_operand" "d")
443 (match_operand:DI 1 "const0_operand" "")))
444 (set (match_operand:DI 2 "register_operand" "=d")
446 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
448 [(set_attr "op_type" "RRE")])
450 (define_insn "*tstdi_cconly"
451 [(set (reg CC_REGNUM)
452 (compare (match_operand:DI 0 "register_operand" "d")
453 (match_operand:DI 1 "const0_operand" "")))]
454 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
456 [(set_attr "op_type" "RRE")])
458 (define_insn "*tstdi_cconly_31"
459 [(set (reg CC_REGNUM)
460 (compare (match_operand:DI 0 "register_operand" "d")
461 (match_operand:DI 1 "const0_operand" "")))]
462 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
464 [(set_attr "op_type" "RS")
465 (set_attr "atype" "reg")])
468 (define_insn "*tstsi"
469 [(set (reg CC_REGNUM)
470 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
471 (match_operand:SI 1 "const0_operand" "")))
472 (set (match_operand:SI 2 "register_operand" "=d,d,d")
474 "s390_match_ccmode(insn, CCSmode)"
479 [(set_attr "op_type" "RR,RS,RSY")])
481 (define_insn "*tstsi_cconly"
482 [(set (reg CC_REGNUM)
483 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
484 (match_operand:SI 1 "const0_operand" "")))
485 (clobber (match_scratch:SI 2 "=X,d,d"))]
486 "s390_match_ccmode(insn, CCSmode)"
491 [(set_attr "op_type" "RR,RS,RSY")])
493 (define_insn "*tstsi_cconly2"
494 [(set (reg CC_REGNUM)
495 (compare (match_operand:SI 0 "register_operand" "d")
496 (match_operand:SI 1 "const0_operand" "")))]
497 "s390_match_ccmode(insn, CCSmode)"
499 [(set_attr "op_type" "RR")])
501 (define_insn "*tst<mode>CCT"
502 [(set (reg CC_REGNUM)
503 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
504 (match_operand:HQI 1 "const0_operand" "")))
505 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
507 "s390_match_ccmode(insn, CCTmode)"
510 icmy\t%2,<icm_lo>,%S0
512 [(set_attr "op_type" "RS,RSY,RI")])
514 (define_insn "*tsthiCCT_cconly"
515 [(set (reg CC_REGNUM)
516 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d,d,X"))]
519 "s390_match_ccmode(insn, CCTmode)"
524 [(set_attr "op_type" "RS,RSY,RI")])
526 (define_insn "*tstqiCCT_cconly"
527 [(set (reg CC_REGNUM)
528 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
529 (match_operand:QI 1 "const0_operand" "")))]
530 "s390_match_ccmode(insn, CCTmode)"
535 [(set_attr "op_type" "SI,SIY,RI")])
537 (define_insn "*tst<mode>"
538 [(set (reg CC_REGNUM)
539 (compare (match_operand:HQI 0 "s_operand" "Q,S")
540 (match_operand:HQI 1 "const0_operand" "")))
541 (set (match_operand:HQI 2 "register_operand" "=d,d")
543 "s390_match_ccmode(insn, CCSmode)"
546 icmy\t%2,<icm_lo>,%S0"
547 [(set_attr "op_type" "RS,RSY")])
549 (define_insn "*tst<mode>_cconly"
550 [(set (reg CC_REGNUM)
551 (compare (match_operand:HQI 0 "s_operand" "Q,S")
552 (match_operand:HQI 1 "const0_operand" "")))
553 (clobber (match_scratch:HQI 2 "=d,d"))]
554 "s390_match_ccmode(insn, CCSmode)"
557 icmy\t%2,<icm_lo>,%S0"
558 [(set_attr "op_type" "RS,RSY")])
561 ; Compare (equality) instructions
563 (define_insn "*cmpdi_cct"
564 [(set (reg CC_REGNUM)
565 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
566 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
567 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
573 [(set_attr "op_type" "RRE,RI,RXY,SS")])
575 (define_insn "*cmpsi_cct"
576 [(set (reg CC_REGNUM)
577 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
578 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
579 "s390_match_ccmode (insn, CCTmode)"
586 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
589 ; Compare (signed) instructions
591 (define_insn "*cmpdi_ccs_sign"
592 [(set (reg CC_REGNUM)
593 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
594 (match_operand:DI 0 "register_operand" "d,d")))]
595 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
599 [(set_attr "op_type" "RRE,RXY")])
601 (define_insn "*cmpdi_ccs"
602 [(set (reg CC_REGNUM)
603 (compare (match_operand:DI 0 "register_operand" "d,d,d")
604 (match_operand:DI 1 "general_operand" "d,K,m")))]
605 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
610 [(set_attr "op_type" "RRE,RI,RXY")])
612 (define_insn "*cmpsi_ccs_sign"
613 [(set (reg CC_REGNUM)
614 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
615 (match_operand:SI 0 "register_operand" "d,d")))]
616 "s390_match_ccmode(insn, CCSRmode)"
620 [(set_attr "op_type" "RX,RXY")])
622 (define_insn "*cmpsi_ccs"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
625 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
626 "s390_match_ccmode(insn, CCSmode)"
632 [(set_attr "op_type" "RR,RI,RX,RXY")])
635 ; Compare (unsigned) instructions
637 (define_insn "*cmpdi_ccu_zero"
638 [(set (reg CC_REGNUM)
639 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
640 (match_operand:DI 0 "register_operand" "d,d")))]
641 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
645 [(set_attr "op_type" "RRE,RXY")])
647 (define_insn "*cmpdi_ccu"
648 [(set (reg CC_REGNUM)
649 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
650 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
651 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
657 [(set_attr "op_type" "RRE,RXY,SS,SS")])
659 (define_insn "*cmpsi_ccu"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
662 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
663 "s390_match_ccmode (insn, CCUmode)"
670 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
672 (define_insn "*cmphi_ccu"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
675 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
676 "s390_match_ccmode (insn, CCUmode)
677 && !register_operand (operands[1], HImode)"
683 [(set_attr "op_type" "RS,RSY,SS,SS")])
685 (define_insn "*cmpqi_ccu"
686 [(set (reg CC_REGNUM)
687 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
688 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
689 "s390_match_ccmode (insn, CCUmode)
690 && !register_operand (operands[1], QImode)"
698 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
701 ; Block compare (CLC) instruction patterns.
704 [(set (reg CC_REGNUM)
705 (compare (match_operand:BLK 0 "memory_operand" "Q")
706 (match_operand:BLK 1 "memory_operand" "Q")))
707 (use (match_operand 2 "const_int_operand" "n"))]
708 "s390_match_ccmode (insn, CCUmode)
709 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
710 "clc\t%O0(%2,%R0),%S1"
711 [(set_attr "op_type" "SS")])
714 [(set (reg CC_REGNUM)
715 (compare (match_operand 0 "memory_operand" "")
716 (match_operand 1 "memory_operand" "")))]
718 && s390_match_ccmode (insn, CCUmode)
719 && GET_MODE (operands[0]) == GET_MODE (operands[1])
720 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
722 [(set (match_dup 0) (match_dup 1))
723 (use (match_dup 2))])]
725 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
726 operands[0] = adjust_address (operands[0], BLKmode, 0);
727 operands[1] = adjust_address (operands[1], BLKmode, 0);
729 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
730 operands[0], operands[1]);
731 operands[0] = SET_DEST (PATTERN (curr_insn));
735 ; (DF|SF) instructions
737 (define_insn "*cmp<mode>_ccs_0"
738 [(set (reg CC_REGNUM)
739 (compare (match_operand:FPR 0 "register_operand" "f")
740 (match_operand:FPR 1 "const0_operand" "")))]
741 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
743 [(set_attr "op_type" "RRE")
744 (set_attr "type" "fsimp<mode>")])
746 (define_insn "*cmp<mode>_ccs_0_ibm"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:FPR 0 "register_operand" "f")
749 (match_operand:FPR 1 "const0_operand" "")))]
750 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
752 [(set_attr "op_type" "RR")
753 (set_attr "type" "fsimp<mode>")])
755 (define_insn "*cmp<mode>_ccs"
756 [(set (reg CC_REGNUM)
757 (compare (match_operand:FPR 0 "register_operand" "f,f")
758 (match_operand:FPR 1 "general_operand" "f,R")))]
759 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
763 [(set_attr "op_type" "RRE,RXE")
764 (set_attr "type" "fsimp<mode>")])
766 (define_insn "*cmp<mode>_ccs_ibm"
767 [(set (reg CC_REGNUM)
768 (compare (match_operand:FPR 0 "register_operand" "f,f")
769 (match_operand:FPR 1 "general_operand" "f,R")))]
770 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
774 [(set_attr "op_type" "RR,RX")
775 (set_attr "type" "fsimp<mode>")])
779 ;;- Move instructions.
783 ; movti instruction pattern(s).
787 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
788 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
796 [(set_attr "op_type" "RSY,RSY,*,*,SS")
797 (set_attr "type" "lm,stm,*,*,*")])
800 [(set (match_operand:TI 0 "nonimmediate_operand" "")
801 (match_operand:TI 1 "general_operand" ""))]
802 "TARGET_64BIT && reload_completed
803 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
804 [(set (match_dup 2) (match_dup 4))
805 (set (match_dup 3) (match_dup 5))]
807 operands[2] = operand_subword (operands[0], 0, 0, TImode);
808 operands[3] = operand_subword (operands[0], 1, 0, TImode);
809 operands[4] = operand_subword (operands[1], 0, 0, TImode);
810 operands[5] = operand_subword (operands[1], 1, 0, TImode);
814 [(set (match_operand:TI 0 "nonimmediate_operand" "")
815 (match_operand:TI 1 "general_operand" ""))]
816 "TARGET_64BIT && reload_completed
817 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
818 [(set (match_dup 2) (match_dup 4))
819 (set (match_dup 3) (match_dup 5))]
821 operands[2] = operand_subword (operands[0], 1, 0, TImode);
822 operands[3] = operand_subword (operands[0], 0, 0, TImode);
823 operands[4] = operand_subword (operands[1], 1, 0, TImode);
824 operands[5] = operand_subword (operands[1], 0, 0, TImode);
828 [(set (match_operand:TI 0 "register_operand" "")
829 (match_operand:TI 1 "memory_operand" ""))]
830 "TARGET_64BIT && reload_completed
831 && !s_operand (operands[1], VOIDmode)"
832 [(set (match_dup 0) (match_dup 1))]
834 rtx addr = operand_subword (operands[0], 1, 0, TImode);
835 s390_load_address (addr, XEXP (operands[1], 0));
836 operands[1] = replace_equiv_address (operands[1], addr);
839 (define_expand "reload_outti"
840 [(parallel [(match_operand:TI 0 "" "")
841 (match_operand:TI 1 "register_operand" "d")
842 (match_operand:DI 2 "register_operand" "=&a")])]
845 gcc_assert (MEM_P (operands[0]));
846 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
847 operands[0] = replace_equiv_address (operands[0], operands[2]);
848 emit_move_insn (operands[0], operands[1]);
853 ; movdi instruction pattern(s).
856 (define_expand "movdi"
857 [(set (match_operand:DI 0 "general_operand" "")
858 (match_operand:DI 1 "general_operand" ""))]
861 /* Handle symbolic constants. */
862 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
863 emit_symbolic_move (operands);
866 (define_insn "*movdi_larl"
867 [(set (match_operand:DI 0 "register_operand" "=d")
868 (match_operand:DI 1 "larl_operand" "X"))]
870 && !FP_REG_P (operands[0])"
872 [(set_attr "op_type" "RIL")
873 (set_attr "type" "larl")])
875 (define_insn "*movdi_64"
876 [(set (match_operand:DI 0 "nonimmediate_operand"
877 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
878 (match_operand:DI 1 "general_operand"
879 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
901 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
902 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
903 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
904 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
907 [(set (match_operand:DI 0 "register_operand" "")
908 (match_operand:DI 1 "register_operand" ""))]
909 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
910 [(set (match_dup 2) (match_dup 3))
911 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
912 (set (strict_low_part (match_dup 2)) (match_dup 4))]
913 "operands[2] = gen_lowpart (SImode, operands[0]);
914 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
917 [(set (match_operand:DI 0 "register_operand" "")
918 (match_operand:DI 1 "register_operand" ""))]
919 "TARGET_64BIT && ACCESS_REG_P (operands[0])
920 && dead_or_set_p (insn, operands[1])"
921 [(set (match_dup 3) (match_dup 2))
922 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
923 (set (match_dup 4) (match_dup 2))]
924 "operands[2] = gen_lowpart (SImode, operands[1]);
925 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
928 [(set (match_operand:DI 0 "register_operand" "")
929 (match_operand:DI 1 "register_operand" ""))]
930 "TARGET_64BIT && ACCESS_REG_P (operands[0])
931 && !dead_or_set_p (insn, operands[1])"
932 [(set (match_dup 3) (match_dup 2))
933 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
934 (set (match_dup 4) (match_dup 2))
935 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
936 "operands[2] = gen_lowpart (SImode, operands[1]);
937 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
939 (define_insn "*movdi_31"
940 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
941 (match_operand:DI 1 "general_operand" "Q,S,d,d,dKm,d,*f,R,T,*f,*f,Q"))]
956 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
957 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
960 [(set (match_operand:DI 0 "nonimmediate_operand" "")
961 (match_operand:DI 1 "general_operand" ""))]
962 "!TARGET_64BIT && reload_completed
963 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
964 [(set (match_dup 2) (match_dup 4))
965 (set (match_dup 3) (match_dup 5))]
967 operands[2] = operand_subword (operands[0], 0, 0, DImode);
968 operands[3] = operand_subword (operands[0], 1, 0, DImode);
969 operands[4] = operand_subword (operands[1], 0, 0, DImode);
970 operands[5] = operand_subword (operands[1], 1, 0, DImode);
974 [(set (match_operand:DI 0 "nonimmediate_operand" "")
975 (match_operand:DI 1 "general_operand" ""))]
976 "!TARGET_64BIT && reload_completed
977 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
978 [(set (match_dup 2) (match_dup 4))
979 (set (match_dup 3) (match_dup 5))]
981 operands[2] = operand_subword (operands[0], 1, 0, DImode);
982 operands[3] = operand_subword (operands[0], 0, 0, DImode);
983 operands[4] = operand_subword (operands[1], 1, 0, DImode);
984 operands[5] = operand_subword (operands[1], 0, 0, DImode);
988 [(set (match_operand:DI 0 "register_operand" "")
989 (match_operand:DI 1 "memory_operand" ""))]
990 "!TARGET_64BIT && reload_completed
991 && !FP_REG_P (operands[0])
992 && !s_operand (operands[1], VOIDmode)"
993 [(set (match_dup 0) (match_dup 1))]
995 rtx addr = operand_subword (operands[0], 1, 0, DImode);
996 s390_load_address (addr, XEXP (operands[1], 0));
997 operands[1] = replace_equiv_address (operands[1], addr);
1000 (define_expand "reload_outdi"
1001 [(parallel [(match_operand:DI 0 "" "")
1002 (match_operand:DI 1 "register_operand" "d")
1003 (match_operand:SI 2 "register_operand" "=&a")])]
1006 gcc_assert (MEM_P (operands[0]));
1007 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1008 operands[0] = replace_equiv_address (operands[0], operands[2]);
1009 emit_move_insn (operands[0], operands[1]);
1014 [(set (match_operand:DI 0 "register_operand" "")
1015 (mem:DI (match_operand 1 "address_operand" "")))]
1017 && !FP_REG_P (operands[0])
1018 && GET_CODE (operands[1]) == SYMBOL_REF
1019 && CONSTANT_POOL_ADDRESS_P (operands[1])
1020 && get_pool_mode (operands[1]) == DImode
1021 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1022 [(set (match_dup 0) (match_dup 2))]
1023 "operands[2] = get_pool_constant (operands[1]);")
1025 (define_insn "*la_64"
1026 [(set (match_operand:DI 0 "register_operand" "=d,d")
1027 (match_operand:QI 1 "address_operand" "U,W"))]
1032 [(set_attr "op_type" "RX,RXY")
1033 (set_attr "type" "la")])
1037 [(set (match_operand:DI 0 "register_operand" "")
1038 (match_operand:QI 1 "address_operand" ""))
1039 (clobber (reg:CC CC_REGNUM))])]
1041 && preferred_la_operand_p (operands[1], const0_rtx)"
1042 [(set (match_dup 0) (match_dup 1))]
1046 [(set (match_operand:DI 0 "register_operand" "")
1047 (match_operand:DI 1 "register_operand" ""))
1050 (plus:DI (match_dup 0)
1051 (match_operand:DI 2 "nonmemory_operand" "")))
1052 (clobber (reg:CC CC_REGNUM))])]
1054 && !reg_overlap_mentioned_p (operands[0], operands[2])
1055 && preferred_la_operand_p (operands[1], operands[2])"
1056 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1059 (define_expand "reload_indi"
1060 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1061 (match_operand:DI 1 "s390_plus_operand" "")
1062 (match_operand:DI 2 "register_operand" "=&a")])]
1065 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1070 ; movsi instruction pattern(s).
1073 (define_expand "movsi"
1074 [(set (match_operand:SI 0 "general_operand" "")
1075 (match_operand:SI 1 "general_operand" ""))]
1078 /* Handle symbolic constants. */
1079 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1080 emit_symbolic_move (operands);
1083 (define_insn "*movsi_larl"
1084 [(set (match_operand:SI 0 "register_operand" "=d")
1085 (match_operand:SI 1 "larl_operand" "X"))]
1086 "!TARGET_64BIT && TARGET_CPU_ZARCH
1087 && !FP_REG_P (operands[0])"
1089 [(set_attr "op_type" "RIL")
1090 (set_attr "type" "larl")])
1092 (define_insn "*movsi_zarch"
1093 [(set (match_operand:SI 0 "nonimmediate_operand"
1094 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1095 (match_operand:SI 1 "general_operand"
1096 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1118 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1119 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1120 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1121 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1123 (define_insn "*movsi_esa"
1124 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1125 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1140 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1141 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1144 [(set (match_operand:SI 0 "register_operand" "")
1145 (mem:SI (match_operand 1 "address_operand" "")))]
1146 "!FP_REG_P (operands[0])
1147 && GET_CODE (operands[1]) == SYMBOL_REF
1148 && CONSTANT_POOL_ADDRESS_P (operands[1])
1149 && get_pool_mode (operands[1]) == SImode
1150 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1151 [(set (match_dup 0) (match_dup 2))]
1152 "operands[2] = get_pool_constant (operands[1]);")
1154 (define_insn "*la_31"
1155 [(set (match_operand:SI 0 "register_operand" "=d,d")
1156 (match_operand:QI 1 "address_operand" "U,W"))]
1157 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1161 [(set_attr "op_type" "RX,RXY")
1162 (set_attr "type" "la")])
1166 [(set (match_operand:SI 0 "register_operand" "")
1167 (match_operand:QI 1 "address_operand" ""))
1168 (clobber (reg:CC CC_REGNUM))])]
1170 && preferred_la_operand_p (operands[1], const0_rtx)"
1171 [(set (match_dup 0) (match_dup 1))]
1175 [(set (match_operand:SI 0 "register_operand" "")
1176 (match_operand:SI 1 "register_operand" ""))
1179 (plus:SI (match_dup 0)
1180 (match_operand:SI 2 "nonmemory_operand" "")))
1181 (clobber (reg:CC CC_REGNUM))])]
1183 && !reg_overlap_mentioned_p (operands[0], operands[2])
1184 && preferred_la_operand_p (operands[1], operands[2])"
1185 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1188 (define_insn "*la_31_and"
1189 [(set (match_operand:SI 0 "register_operand" "=d,d")
1190 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1191 (const_int 2147483647)))]
1196 [(set_attr "op_type" "RX,RXY")
1197 (set_attr "type" "la")])
1199 (define_insn_and_split "*la_31_and_cc"
1200 [(set (match_operand:SI 0 "register_operand" "=d")
1201 (and:SI (match_operand:QI 1 "address_operand" "p")
1202 (const_int 2147483647)))
1203 (clobber (reg:CC CC_REGNUM))]
1206 "&& reload_completed"
1208 (and:SI (match_dup 1) (const_int 2147483647)))]
1210 [(set_attr "op_type" "RX")
1211 (set_attr "type" "la")])
1213 (define_insn "force_la_31"
1214 [(set (match_operand:SI 0 "register_operand" "=d,d")
1215 (match_operand:QI 1 "address_operand" "U,W"))
1216 (use (const_int 0))]
1221 [(set_attr "op_type" "RX")
1222 (set_attr "type" "la")])
1224 (define_expand "reload_insi"
1225 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1226 (match_operand:SI 1 "s390_plus_operand" "")
1227 (match_operand:SI 2 "register_operand" "=&a")])]
1230 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1235 ; movhi instruction pattern(s).
1238 (define_expand "movhi"
1239 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1240 (match_operand:HI 1 "general_operand" ""))]
1243 /* Make it explicit that loading a register from memory
1244 always sign-extends (at least) to SImode. */
1245 if (optimize && !no_new_pseudos
1246 && register_operand (operands[0], VOIDmode)
1247 && GET_CODE (operands[1]) == MEM)
1249 rtx tmp = gen_reg_rtx (SImode);
1250 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1251 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1252 operands[1] = gen_lowpart (HImode, tmp);
1256 (define_insn "*movhi"
1257 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1258 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1268 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1269 (set_attr "type" "lr,*,*,*,store,store,*")])
1272 [(set (match_operand:HI 0 "register_operand" "")
1273 (mem:HI (match_operand 1 "address_operand" "")))]
1274 "GET_CODE (operands[1]) == SYMBOL_REF
1275 && CONSTANT_POOL_ADDRESS_P (operands[1])
1276 && get_pool_mode (operands[1]) == HImode
1277 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1278 [(set (match_dup 0) (match_dup 2))]
1279 "operands[2] = get_pool_constant (operands[1]);")
1282 ; movqi instruction pattern(s).
1285 (define_expand "movqi"
1286 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1287 (match_operand:QI 1 "general_operand" ""))]
1290 /* On z/Architecture, zero-extending from memory to register
1291 is just as fast as a QImode load. */
1292 if (TARGET_ZARCH && optimize && !no_new_pseudos
1293 && register_operand (operands[0], VOIDmode)
1294 && GET_CODE (operands[1]) == MEM)
1296 rtx tmp = gen_reg_rtx (word_mode);
1297 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1298 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1299 operands[1] = gen_lowpart (QImode, tmp);
1303 (define_insn "*movqi"
1304 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1305 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1317 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1318 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1321 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1322 (mem:QI (match_operand 1 "address_operand" "")))]
1323 "GET_CODE (operands[1]) == SYMBOL_REF
1324 && CONSTANT_POOL_ADDRESS_P (operands[1])
1325 && get_pool_mode (operands[1]) == QImode
1326 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1327 [(set (match_dup 0) (match_dup 2))]
1328 "operands[2] = get_pool_constant (operands[1]);")
1331 ; movstrictqi instruction pattern(s).
1334 (define_insn "*movstrictqi"
1335 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1336 (match_operand:QI 1 "memory_operand" "R,T"))]
1341 [(set_attr "op_type" "RX,RXY")])
1344 ; movstricthi instruction pattern(s).
1347 (define_insn "*movstricthi"
1348 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1349 (match_operand:HI 1 "memory_operand" "Q,S"))
1350 (clobber (reg:CC CC_REGNUM))]
1355 [(set_attr "op_type" "RS,RSY")])
1358 ; movstrictsi instruction pattern(s).
1361 (define_insn "movstrictsi"
1362 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1363 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1370 [(set_attr "op_type" "RR,RX,RXY,RRE")
1371 (set_attr "type" "lr,load,load,*")])
1374 ; movdf instruction pattern(s).
1377 (define_expand "movdf"
1378 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1379 (match_operand:DF 1 "general_operand" ""))]
1383 (define_insn "*movdf_64"
1384 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1385 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1398 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1399 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1401 (define_insn "*movdf_31"
1402 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1403 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dKm,d,Q"))]
1419 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1420 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1421 lm,lm,stm,stm,*,*,*")])
1424 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1425 (match_operand:DF 1 "general_operand" ""))]
1426 "!TARGET_64BIT && reload_completed
1427 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1428 [(set (match_dup 2) (match_dup 4))
1429 (set (match_dup 3) (match_dup 5))]
1431 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1432 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1433 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1434 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1438 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1439 (match_operand:DF 1 "general_operand" ""))]
1440 "!TARGET_64BIT && reload_completed
1441 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1442 [(set (match_dup 2) (match_dup 4))
1443 (set (match_dup 3) (match_dup 5))]
1445 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1446 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1447 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1448 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1452 [(set (match_operand:DF 0 "register_operand" "")
1453 (match_operand:DF 1 "memory_operand" ""))]
1454 "!TARGET_64BIT && reload_completed
1455 && !FP_REG_P (operands[0])
1456 && !s_operand (operands[1], VOIDmode)"
1457 [(set (match_dup 0) (match_dup 1))]
1459 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1460 s390_load_address (addr, XEXP (operands[1], 0));
1461 operands[1] = replace_equiv_address (operands[1], addr);
1464 (define_expand "reload_outdf"
1465 [(parallel [(match_operand:DF 0 "" "")
1466 (match_operand:DF 1 "register_operand" "d")
1467 (match_operand:SI 2 "register_operand" "=&a")])]
1470 gcc_assert (MEM_P (operands[0]));
1471 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1472 operands[0] = replace_equiv_address (operands[0], operands[2]);
1473 emit_move_insn (operands[0], operands[1]);
1478 ; movsf instruction pattern(s).
1481 (define_insn "movsf"
1482 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1483 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1498 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1499 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1500 lr,load,load,store,store,*")])
1503 ; movcc instruction pattern
1506 (define_insn "movcc"
1507 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1508 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1518 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1519 (set_attr "type" "lr,*,*,store,store,load,load")])
1522 ; Block move (MVC) patterns.
1526 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1527 (match_operand:BLK 1 "memory_operand" "Q"))
1528 (use (match_operand 2 "const_int_operand" "n"))]
1529 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1530 "mvc\t%O0(%2,%R0),%S1"
1531 [(set_attr "op_type" "SS")])
1534 [(set (match_operand 0 "memory_operand" "")
1535 (match_operand 1 "memory_operand" ""))]
1537 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1538 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1540 [(set (match_dup 0) (match_dup 1))
1541 (use (match_dup 2))])]
1543 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1544 operands[0] = adjust_address (operands[0], BLKmode, 0);
1545 operands[1] = adjust_address (operands[1], BLKmode, 0);
1550 [(set (match_operand:BLK 0 "memory_operand" "")
1551 (match_operand:BLK 1 "memory_operand" ""))
1552 (use (match_operand 2 "const_int_operand" ""))])
1554 [(set (match_operand:BLK 3 "memory_operand" "")
1555 (match_operand:BLK 4 "memory_operand" ""))
1556 (use (match_operand 5 "const_int_operand" ""))])]
1557 "s390_offset_p (operands[0], operands[3], operands[2])
1558 && s390_offset_p (operands[1], operands[4], operands[2])
1559 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1561 [(set (match_dup 6) (match_dup 7))
1562 (use (match_dup 8))])]
1563 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1564 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1565 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1569 ; load_multiple pattern(s).
1571 ; ??? Due to reload problems with replacing registers inside match_parallel
1572 ; we currently support load_multiple/store_multiple only after reload.
1575 (define_expand "load_multiple"
1576 [(match_par_dup 3 [(set (match_operand 0 "" "")
1577 (match_operand 1 "" ""))
1578 (use (match_operand 2 "" ""))])]
1581 enum machine_mode mode;
1587 /* Support only loading a constant number of fixed-point registers from
1588 memory and only bother with this if more than two */
1589 if (GET_CODE (operands[2]) != CONST_INT
1590 || INTVAL (operands[2]) < 2
1591 || INTVAL (operands[2]) > 16
1592 || GET_CODE (operands[1]) != MEM
1593 || GET_CODE (operands[0]) != REG
1594 || REGNO (operands[0]) >= 16)
1597 count = INTVAL (operands[2]);
1598 regno = REGNO (operands[0]);
1599 mode = GET_MODE (operands[0]);
1600 if (mode != SImode && mode != word_mode)
1603 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1606 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1608 from = XEXP (operands[1], 0);
1611 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1612 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1613 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1615 from = XEXP (XEXP (operands[1], 0), 0);
1616 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1623 from = force_reg (Pmode, XEXP (operands[1], 0));
1627 for (i = 0; i < count; i++)
1628 XVECEXP (operands[3], 0, i)
1629 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1630 change_address (operands[1], mode,
1631 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1634 (define_insn "*load_multiple_di"
1635 [(match_parallel 0 "load_multiple_operation"
1636 [(set (match_operand:DI 1 "register_operand" "=r")
1637 (match_operand:DI 2 "s_operand" "QS"))])]
1638 "reload_completed && word_mode == DImode"
1640 int words = XVECLEN (operands[0], 0);
1641 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1642 return "lmg\t%1,%0,%S2";
1644 [(set_attr "op_type" "RSY")
1645 (set_attr "type" "lm")])
1647 (define_insn "*load_multiple_si"
1648 [(match_parallel 0 "load_multiple_operation"
1649 [(set (match_operand:SI 1 "register_operand" "=r,r")
1650 (match_operand:SI 2 "s_operand" "Q,S"))])]
1653 int words = XVECLEN (operands[0], 0);
1654 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1655 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1657 [(set_attr "op_type" "RS,RSY")
1658 (set_attr "type" "lm")])
1661 ; store multiple pattern(s).
1664 (define_expand "store_multiple"
1665 [(match_par_dup 3 [(set (match_operand 0 "" "")
1666 (match_operand 1 "" ""))
1667 (use (match_operand 2 "" ""))])]
1670 enum machine_mode mode;
1676 /* Support only storing a constant number of fixed-point registers to
1677 memory and only bother with this if more than two. */
1678 if (GET_CODE (operands[2]) != CONST_INT
1679 || INTVAL (operands[2]) < 2
1680 || INTVAL (operands[2]) > 16
1681 || GET_CODE (operands[0]) != MEM
1682 || GET_CODE (operands[1]) != REG
1683 || REGNO (operands[1]) >= 16)
1686 count = INTVAL (operands[2]);
1687 regno = REGNO (operands[1]);
1688 mode = GET_MODE (operands[1]);
1689 if (mode != SImode && mode != word_mode)
1692 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1696 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1698 to = XEXP (operands[0], 0);
1701 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1702 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1703 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1705 to = XEXP (XEXP (operands[0], 0), 0);
1706 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1713 to = force_reg (Pmode, XEXP (operands[0], 0));
1717 for (i = 0; i < count; i++)
1718 XVECEXP (operands[3], 0, i)
1719 = gen_rtx_SET (VOIDmode,
1720 change_address (operands[0], mode,
1721 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1722 gen_rtx_REG (mode, regno + i));
1725 (define_insn "*store_multiple_di"
1726 [(match_parallel 0 "store_multiple_operation"
1727 [(set (match_operand:DI 1 "s_operand" "=QS")
1728 (match_operand:DI 2 "register_operand" "r"))])]
1729 "reload_completed && word_mode == DImode"
1731 int words = XVECLEN (operands[0], 0);
1732 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1733 return "stmg\t%2,%0,%S1";
1735 [(set_attr "op_type" "RSY")
1736 (set_attr "type" "stm")])
1739 (define_insn "*store_multiple_si"
1740 [(match_parallel 0 "store_multiple_operation"
1741 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1742 (match_operand:SI 2 "register_operand" "r,r"))])]
1745 int words = XVECLEN (operands[0], 0);
1746 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1747 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1749 [(set_attr "op_type" "RS,RSY")
1750 (set_attr "type" "stm")])
1753 ;; String instructions.
1756 (define_insn "*execute"
1757 [(match_parallel 0 ""
1758 [(unspec [(match_operand 1 "register_operand" "a")
1759 (match_operand:BLK 2 "memory_operand" "R")
1760 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1761 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1762 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1764 [(set_attr "op_type" "RX")
1765 (set_attr "type" "cs")])
1769 ; strlenM instruction pattern(s).
1772 (define_expand "strlen<mode>"
1773 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1776 (unspec:P [(const_int 0)
1777 (match_operand:BLK 1 "memory_operand" "")
1779 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1780 (clobber (scratch:P))
1781 (clobber (reg:CC CC_REGNUM))])
1783 [(set (match_operand:P 0 "register_operand" "")
1784 (minus:P (match_dup 4) (match_dup 5)))
1785 (clobber (reg:CC CC_REGNUM))])]
1788 operands[4] = gen_reg_rtx (Pmode);
1789 operands[5] = gen_reg_rtx (Pmode);
1790 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1791 operands[1] = replace_equiv_address (operands[1], operands[5]);
1794 (define_insn "*strlen<mode>"
1795 [(set (match_operand:P 0 "register_operand" "=a")
1796 (unspec:P [(match_operand:P 2 "general_operand" "0")
1797 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1799 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1800 (clobber (match_scratch:P 1 "=a"))
1801 (clobber (reg:CC CC_REGNUM))]
1803 "srst\t%0,%1\;jo\t.-4"
1804 [(set_attr "length" "8")
1805 (set_attr "type" "vs")])
1808 ; cmpstrM instruction pattern(s).
1811 (define_expand "cmpstrsi"
1812 [(set (reg:SI 0) (const_int 0))
1814 [(clobber (match_operand 3 "" ""))
1815 (clobber (match_dup 4))
1816 (set (reg:CCU CC_REGNUM)
1817 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1818 (match_operand:BLK 2 "memory_operand" "")))
1821 [(set (match_operand:SI 0 "register_operand" "=d")
1822 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1823 (clobber (reg:CC CC_REGNUM))])]
1826 /* As the result of CMPINT is inverted compared to what we need,
1827 we have to swap the operands. */
1828 rtx op1 = operands[2];
1829 rtx op2 = operands[1];
1830 rtx addr1 = gen_reg_rtx (Pmode);
1831 rtx addr2 = gen_reg_rtx (Pmode);
1833 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1834 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1835 operands[1] = replace_equiv_address_nv (op1, addr1);
1836 operands[2] = replace_equiv_address_nv (op2, addr2);
1837 operands[3] = addr1;
1838 operands[4] = addr2;
1841 (define_insn "*cmpstr<mode>"
1842 [(clobber (match_operand:P 0 "register_operand" "=d"))
1843 (clobber (match_operand:P 1 "register_operand" "=d"))
1844 (set (reg:CCU CC_REGNUM)
1845 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1846 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1849 "clst\t%0,%1\;jo\t.-4"
1850 [(set_attr "length" "8")
1851 (set_attr "type" "vs")])
1854 ; movmemM instruction pattern(s).
1857 (define_expand "movmem<mode>"
1858 [(set (match_operand:BLK 0 "memory_operand" "")
1859 (match_operand:BLK 1 "memory_operand" ""))
1860 (use (match_operand:GPR 2 "general_operand" ""))
1861 (match_operand 3 "" "")]
1863 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1865 ; Move a block that is up to 256 bytes in length.
1866 ; The block length is taken as (operands[2] % 256) + 1.
1868 (define_expand "movmem_short"
1870 [(set (match_operand:BLK 0 "memory_operand" "")
1871 (match_operand:BLK 1 "memory_operand" ""))
1872 (use (match_operand 2 "nonmemory_operand" ""))
1873 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1874 (clobber (match_dup 3))])]
1876 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1878 (define_insn "*movmem_short"
1879 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1880 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1881 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1882 (use (match_operand 3 "immediate_operand" "X,R,X"))
1883 (clobber (match_scratch 4 "=X,X,&a"))]
1884 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1885 && GET_MODE (operands[4]) == Pmode"
1887 [(set_attr "type" "cs")])
1890 [(set (match_operand:BLK 0 "memory_operand" "")
1891 (match_operand:BLK 1 "memory_operand" ""))
1892 (use (match_operand 2 "const_int_operand" ""))
1893 (use (match_operand 3 "immediate_operand" ""))
1894 (clobber (scratch))]
1897 [(set (match_dup 0) (match_dup 1))
1898 (use (match_dup 2))])]
1899 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1902 [(set (match_operand:BLK 0 "memory_operand" "")
1903 (match_operand:BLK 1 "memory_operand" ""))
1904 (use (match_operand 2 "register_operand" ""))
1905 (use (match_operand 3 "memory_operand" ""))
1906 (clobber (scratch))]
1909 [(unspec [(match_dup 2) (match_dup 3)
1910 (const_int 0)] UNSPEC_EXECUTE)
1911 (set (match_dup 0) (match_dup 1))
1912 (use (const_int 1))])]
1916 [(set (match_operand:BLK 0 "memory_operand" "")
1917 (match_operand:BLK 1 "memory_operand" ""))
1918 (use (match_operand 2 "register_operand" ""))
1919 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1920 (clobber (match_operand 3 "register_operand" ""))]
1921 "reload_completed && TARGET_CPU_ZARCH"
1922 [(set (match_dup 3) (label_ref (match_dup 4)))
1924 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1925 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1926 (set (match_dup 0) (match_dup 1))
1927 (use (const_int 1))])]
1928 "operands[4] = gen_label_rtx ();")
1930 ; Move a block of arbitrary length.
1932 (define_expand "movmem_long"
1934 [(clobber (match_dup 2))
1935 (clobber (match_dup 3))
1936 (set (match_operand:BLK 0 "memory_operand" "")
1937 (match_operand:BLK 1 "memory_operand" ""))
1938 (use (match_operand 2 "general_operand" ""))
1940 (clobber (reg:CC CC_REGNUM))])]
1943 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1944 rtx reg0 = gen_reg_rtx (dword_mode);
1945 rtx reg1 = gen_reg_rtx (dword_mode);
1946 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1947 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1948 rtx len0 = gen_lowpart (Pmode, reg0);
1949 rtx len1 = gen_lowpart (Pmode, reg1);
1951 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1952 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1953 emit_move_insn (len0, operands[2]);
1955 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1956 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1957 emit_move_insn (len1, operands[2]);
1959 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1960 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1965 (define_insn "*movmem_long"
1966 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
1967 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
1968 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
1969 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
1972 (clobber (reg:CC CC_REGNUM))]
1974 "mvcle\t%0,%1,0\;jo\t.-4"
1975 [(set_attr "length" "8")
1976 (set_attr "type" "vs")])
1979 ; setmemM instruction pattern(s).
1982 (define_expand "setmem<mode>"
1983 [(set (match_operand:BLK 0 "memory_operand" "")
1984 (match_operand:QI 2 "general_operand" ""))
1985 (use (match_operand:GPR 1 "general_operand" ""))
1986 (match_operand 3 "" "")]
1988 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
1990 ; Clear a block that is up to 256 bytes in length.
1991 ; The block length is taken as (operands[1] % 256) + 1.
1993 (define_expand "clrmem_short"
1995 [(set (match_operand:BLK 0 "memory_operand" "")
1997 (use (match_operand 1 "nonmemory_operand" ""))
1998 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1999 (clobber (match_dup 2))
2000 (clobber (reg:CC CC_REGNUM))])]
2002 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2004 (define_insn "*clrmem_short"
2005 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2007 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2008 (use (match_operand 2 "immediate_operand" "X,R,X"))
2009 (clobber (match_scratch 3 "=X,X,&a"))
2010 (clobber (reg:CC CC_REGNUM))]
2011 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2012 && GET_MODE (operands[3]) == Pmode"
2014 [(set_attr "type" "cs")])
2017 [(set (match_operand:BLK 0 "memory_operand" "")
2019 (use (match_operand 1 "const_int_operand" ""))
2020 (use (match_operand 2 "immediate_operand" ""))
2022 (clobber (reg:CC CC_REGNUM))]
2025 [(set (match_dup 0) (const_int 0))
2027 (clobber (reg:CC CC_REGNUM))])]
2028 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2031 [(set (match_operand:BLK 0 "memory_operand" "")
2033 (use (match_operand 1 "register_operand" ""))
2034 (use (match_operand 2 "memory_operand" ""))
2036 (clobber (reg:CC CC_REGNUM))]
2039 [(unspec [(match_dup 1) (match_dup 2)
2040 (const_int 0)] UNSPEC_EXECUTE)
2041 (set (match_dup 0) (const_int 0))
2043 (clobber (reg:CC CC_REGNUM))])]
2047 [(set (match_operand:BLK 0 "memory_operand" "")
2049 (use (match_operand 1 "register_operand" ""))
2050 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2051 (clobber (match_operand 2 "register_operand" ""))
2052 (clobber (reg:CC CC_REGNUM))]
2053 "reload_completed && TARGET_CPU_ZARCH"
2054 [(set (match_dup 2) (label_ref (match_dup 3)))
2056 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2057 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2058 (set (match_dup 0) (const_int 0))
2060 (clobber (reg:CC CC_REGNUM))])]
2061 "operands[3] = gen_label_rtx ();")
2063 ; Initialize a block of arbitrary length with (operands[2] % 256).
2065 (define_expand "setmem_long"
2067 [(clobber (match_dup 1))
2068 (set (match_operand:BLK 0 "memory_operand" "")
2069 (match_operand 2 "setmem_operand" ""))
2070 (use (match_operand 1 "general_operand" ""))
2072 (clobber (reg:CC CC_REGNUM))])]
2075 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2076 rtx reg0 = gen_reg_rtx (dword_mode);
2077 rtx reg1 = gen_reg_rtx (dword_mode);
2078 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2079 rtx len0 = gen_lowpart (Pmode, reg0);
2081 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2082 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2083 emit_move_insn (len0, operands[1]);
2085 emit_move_insn (reg1, const0_rtx);
2087 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2092 (define_insn "*setmem_long"
2093 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2094 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2095 (match_operand 2 "setmem_operand" "Y"))
2097 (use (match_operand:<DBL> 1 "register_operand" "d"))
2098 (clobber (reg:CC CC_REGNUM))]
2100 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2101 [(set_attr "length" "8")
2102 (set_attr "type" "vs")])
2105 ; cmpmemM instruction pattern(s).
2108 (define_expand "cmpmemsi"
2109 [(set (match_operand:SI 0 "register_operand" "")
2110 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2111 (match_operand:BLK 2 "memory_operand" "") ) )
2112 (use (match_operand:SI 3 "general_operand" ""))
2113 (use (match_operand:SI 4 "" ""))]
2115 "s390_expand_cmpmem (operands[0], operands[1],
2116 operands[2], operands[3]); DONE;")
2118 ; Compare a block that is up to 256 bytes in length.
2119 ; The block length is taken as (operands[2] % 256) + 1.
2121 (define_expand "cmpmem_short"
2123 [(set (reg:CCU CC_REGNUM)
2124 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2125 (match_operand:BLK 1 "memory_operand" "")))
2126 (use (match_operand 2 "nonmemory_operand" ""))
2127 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2128 (clobber (match_dup 3))])]
2130 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2132 (define_insn "*cmpmem_short"
2133 [(set (reg:CCU CC_REGNUM)
2134 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2135 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2136 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2137 (use (match_operand 3 "immediate_operand" "X,R,X"))
2138 (clobber (match_scratch 4 "=X,X,&a"))]
2139 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2140 && GET_MODE (operands[4]) == Pmode"
2142 [(set_attr "type" "cs")])
2145 [(set (reg:CCU CC_REGNUM)
2146 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2147 (match_operand:BLK 1 "memory_operand" "")))
2148 (use (match_operand 2 "const_int_operand" ""))
2149 (use (match_operand 3 "immediate_operand" ""))
2150 (clobber (scratch))]
2153 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2154 (use (match_dup 2))])]
2155 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2158 [(set (reg:CCU CC_REGNUM)
2159 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2160 (match_operand:BLK 1 "memory_operand" "")))
2161 (use (match_operand 2 "register_operand" ""))
2162 (use (match_operand 3 "memory_operand" ""))
2163 (clobber (scratch))]
2166 [(unspec [(match_dup 2) (match_dup 3)
2167 (const_int 0)] UNSPEC_EXECUTE)
2168 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2169 (use (const_int 1))])]
2173 [(set (reg:CCU CC_REGNUM)
2174 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2175 (match_operand:BLK 1 "memory_operand" "")))
2176 (use (match_operand 2 "register_operand" ""))
2177 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2178 (clobber (match_operand 3 "register_operand" ""))]
2179 "reload_completed && TARGET_CPU_ZARCH"
2180 [(set (match_dup 3) (label_ref (match_dup 4)))
2182 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2183 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2184 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2185 (use (const_int 1))])]
2186 "operands[4] = gen_label_rtx ();")
2188 ; Compare a block of arbitrary length.
2190 (define_expand "cmpmem_long"
2192 [(clobber (match_dup 2))
2193 (clobber (match_dup 3))
2194 (set (reg:CCU CC_REGNUM)
2195 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2196 (match_operand:BLK 1 "memory_operand" "")))
2197 (use (match_operand 2 "general_operand" ""))
2198 (use (match_dup 3))])]
2201 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2202 rtx reg0 = gen_reg_rtx (dword_mode);
2203 rtx reg1 = gen_reg_rtx (dword_mode);
2204 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2205 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2206 rtx len0 = gen_lowpart (Pmode, reg0);
2207 rtx len1 = gen_lowpart (Pmode, reg1);
2209 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2210 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2211 emit_move_insn (len0, operands[2]);
2213 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2214 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2215 emit_move_insn (len1, operands[2]);
2217 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2218 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2223 (define_insn "*cmpmem_long"
2224 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2225 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2226 (set (reg:CCU CC_REGNUM)
2227 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2228 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2230 (use (match_dup 3))]
2232 "clcle\t%0,%1,0\;jo\t.-4"
2233 [(set_attr "length" "8")
2234 (set_attr "type" "vs")])
2236 ; Convert CCUmode condition code to integer.
2237 ; Result is zero if EQ, positive if LTU, negative if GTU.
2239 (define_insn_and_split "cmpint"
2240 [(set (match_operand:SI 0 "register_operand" "=d")
2241 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2243 (clobber (reg:CC CC_REGNUM))]
2247 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2249 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2250 (clobber (reg:CC CC_REGNUM))])])
2252 (define_insn_and_split "*cmpint_cc"
2253 [(set (reg CC_REGNUM)
2254 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2257 (set (match_operand:SI 0 "register_operand" "=d")
2258 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2259 "s390_match_ccmode (insn, CCSmode)"
2261 "&& reload_completed"
2262 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2264 [(set (match_dup 2) (match_dup 3))
2265 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2267 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2268 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2269 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2272 (define_insn_and_split "*cmpint_sign"
2273 [(set (match_operand:DI 0 "register_operand" "=d")
2274 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2276 (clobber (reg:CC CC_REGNUM))]
2279 "&& reload_completed"
2280 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2282 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2283 (clobber (reg:CC CC_REGNUM))])])
2285 (define_insn_and_split "*cmpint_sign_cc"
2286 [(set (reg CC_REGNUM)
2287 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2288 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2290 (const_int 32)) (const_int 32))
2292 (set (match_operand:DI 0 "register_operand" "=d")
2293 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2294 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2296 "&& reload_completed"
2297 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2299 [(set (match_dup 2) (match_dup 3))
2300 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2302 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2303 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2304 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2309 ;;- Conversion instructions.
2313 (define_insn "*sethigh<mode>si"
2314 [(set (match_operand:SI 0 "register_operand" "=d,d")
2315 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2316 (clobber (reg:CC CC_REGNUM))]
2319 icm\t%0,<icm_hi>,%S1
2320 icmy\t%0,<icm_hi>,%S1"
2321 [(set_attr "op_type" "RS,RSY")])
2323 (define_insn "*sethighqidi_64"
2324 [(set (match_operand:DI 0 "register_operand" "=d")
2325 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2326 (clobber (reg:CC CC_REGNUM))]
2329 [(set_attr "op_type" "RSY")])
2331 (define_insn "*sethighqidi_31"
2332 [(set (match_operand:DI 0 "register_operand" "=d,d")
2333 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2334 (clobber (reg:CC CC_REGNUM))]
2339 [(set_attr "op_type" "RS,RSY")])
2341 (define_insn_and_split "*extractqi"
2342 [(set (match_operand:SI 0 "register_operand" "=d")
2343 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2344 (match_operand 2 "const_int_operand" "n")
2346 (clobber (reg:CC CC_REGNUM))]
2348 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2350 "&& reload_completed"
2352 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2353 (clobber (reg:CC CC_REGNUM))])
2354 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2356 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2357 operands[1] = change_address (operands[1], QImode, 0);
2360 (define_insn_and_split "*extracthi"
2361 [(set (match_operand:SI 0 "register_operand" "=d")
2362 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2363 (match_operand 2 "const_int_operand" "n")
2365 (clobber (reg:CC CC_REGNUM))]
2367 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2369 "&& reload_completed"
2371 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2372 (clobber (reg:CC CC_REGNUM))])
2373 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2375 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2376 operands[1] = change_address (operands[1], HImode, 0);
2380 ; extendsidi2 instruction pattern(s).
2383 (define_expand "extendsidi2"
2384 [(set (match_operand:DI 0 "register_operand" "")
2385 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2391 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2392 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2393 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2394 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2400 (define_insn "*extendsidi2"
2401 [(set (match_operand:DI 0 "register_operand" "=d,d")
2402 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2407 [(set_attr "op_type" "RRE,RXY")])
2410 ; extend(hi|qi)di2 instruction pattern(s).
2413 (define_expand "extend<mode>di2"
2414 [(set (match_operand:DI 0 "register_operand" "")
2415 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2421 rtx tmp = gen_reg_rtx (SImode);
2422 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2423 emit_insn (gen_extendsidi2 (operands[0], tmp));
2428 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2429 GET_MODE_BITSIZE (<MODE>mode));
2430 operands[1] = gen_lowpart (DImode, operands[1]);
2431 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2432 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2438 (define_insn "*extendhidi2"
2439 [(set (match_operand:DI 0 "register_operand" "=d")
2440 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2443 [(set_attr "op_type" "RXY")])
2445 (define_insn "*extendqidi2"
2446 [(set (match_operand:DI 0 "register_operand" "=d")
2447 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2448 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2450 [(set_attr "op_type" "RXY")])
2452 (define_insn_and_split "*extendqidi2_short_displ"
2453 [(set (match_operand:DI 0 "register_operand" "=d")
2454 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2455 (clobber (reg:CC CC_REGNUM))]
2456 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2458 "&& reload_completed"
2460 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2461 (clobber (reg:CC CC_REGNUM))])
2463 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2464 (clobber (reg:CC CC_REGNUM))])]
2468 ; extend(hi|qi)si2 instruction pattern(s).
2471 (define_expand "extend<mode>si2"
2472 [(set (match_operand:SI 0 "register_operand" "")
2473 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2477 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2478 GET_MODE_BITSIZE(<MODE>mode));
2479 operands[1] = gen_lowpart (SImode, operands[1]);
2480 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2481 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2486 (define_insn "*extendhisi2"
2487 [(set (match_operand:SI 0 "register_operand" "=d,d")
2488 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2493 [(set_attr "op_type" "RX,RXY")])
2495 (define_insn "*extendqisi2"
2496 [(set (match_operand:SI 0 "register_operand" "=d")
2497 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2498 "TARGET_LONG_DISPLACEMENT"
2500 [(set_attr "op_type" "RXY")])
2502 (define_insn_and_split "*extendqisi2_short_displ"
2503 [(set (match_operand:SI 0 "register_operand" "=d")
2504 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2505 (clobber (reg:CC CC_REGNUM))]
2506 "!TARGET_LONG_DISPLACEMENT"
2508 "&& reload_completed"
2510 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2511 (clobber (reg:CC CC_REGNUM))])
2513 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2514 (clobber (reg:CC CC_REGNUM))])]
2518 ; extendqihi2 instruction pattern(s).
2523 ; zero_extendsidi2 instruction pattern(s).
2526 (define_expand "zero_extendsidi2"
2527 [(set (match_operand:DI 0 "register_operand" "")
2528 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2534 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2535 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2536 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2542 (define_insn "*zero_extendsidi2"
2543 [(set (match_operand:DI 0 "register_operand" "=d,d")
2544 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2549 [(set_attr "op_type" "RRE,RXY")])
2552 ; zero_extend(hi|qi)di2 instruction pattern(s).
2555 (define_expand "zero_extend<mode>di2"
2556 [(set (match_operand:DI 0 "register_operand" "")
2557 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2563 rtx tmp = gen_reg_rtx (SImode);
2564 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2565 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2570 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2571 GET_MODE_BITSIZE(<MODE>mode));
2572 operands[1] = gen_lowpart (DImode, operands[1]);
2573 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2574 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2580 (define_insn "*zero_extend<mode>di2"
2581 [(set (match_operand:DI 0 "register_operand" "=d")
2582 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2585 [(set_attr "op_type" "RXY")])
2588 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2591 (define_insn "*llgt_sidi"
2592 [(set (match_operand:DI 0 "register_operand" "=d")
2593 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2594 (const_int 2147483647)))]
2597 [(set_attr "op_type" "RXE")])
2599 (define_insn_and_split "*llgt_sidi_split"
2600 [(set (match_operand:DI 0 "register_operand" "=d")
2601 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2602 (const_int 2147483647)))
2603 (clobber (reg:CC CC_REGNUM))]
2606 "&& reload_completed"
2608 (and:DI (subreg:DI (match_dup 1) 0)
2609 (const_int 2147483647)))]
2612 (define_insn "*llgt_sisi"
2613 [(set (match_operand:SI 0 "register_operand" "=d,d")
2614 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2615 (const_int 2147483647)))]
2620 [(set_attr "op_type" "RRE,RXE")])
2622 (define_insn "*llgt_didi"
2623 [(set (match_operand:DI 0 "register_operand" "=d,d")
2624 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2625 (const_int 2147483647)))]
2630 [(set_attr "op_type" "RRE,RXE")])
2633 [(set (match_operand:GPR 0 "register_operand" "")
2634 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2635 (const_int 2147483647)))
2636 (clobber (reg:CC CC_REGNUM))]
2637 "TARGET_ZARCH && reload_completed"
2639 (and:GPR (match_dup 1)
2640 (const_int 2147483647)))]
2644 ; zero_extend(hi|qi)si2 instruction pattern(s).
2647 (define_expand "zero_extend<mode>si2"
2648 [(set (match_operand:SI 0 "register_operand" "")
2649 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2653 operands[1] = gen_lowpart (SImode, operands[1]);
2654 emit_insn (gen_andsi3 (operands[0], operands[1],
2655 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2660 (define_insn "*zero_extend<mode>si2_64"
2661 [(set (match_operand:SI 0 "register_operand" "=d")
2662 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2665 [(set_attr "op_type" "RXY")])
2667 (define_insn_and_split "*zero_extendhisi2_31"
2668 [(set (match_operand:SI 0 "register_operand" "=&d")
2669 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2670 (clobber (reg:CC CC_REGNUM))]
2673 "&& reload_completed"
2674 [(set (match_dup 0) (const_int 0))
2676 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2677 (clobber (reg:CC CC_REGNUM))])]
2678 "operands[2] = gen_lowpart (HImode, operands[0]);")
2680 (define_insn_and_split "*zero_extendqisi2_31"
2681 [(set (match_operand:SI 0 "register_operand" "=&d")
2682 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2685 "&& reload_completed"
2686 [(set (match_dup 0) (const_int 0))
2687 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2688 "operands[2] = gen_lowpart (QImode, operands[0]);")
2691 ; zero_extendqihi2 instruction pattern(s).
2694 (define_expand "zero_extendqihi2"
2695 [(set (match_operand:HI 0 "register_operand" "")
2696 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2700 operands[1] = gen_lowpart (HImode, operands[1]);
2701 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2706 (define_insn "*zero_extendqihi2_64"
2707 [(set (match_operand:HI 0 "register_operand" "=d")
2708 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2711 [(set_attr "op_type" "RXY")])
2713 (define_insn_and_split "*zero_extendqihi2_31"
2714 [(set (match_operand:HI 0 "register_operand" "=&d")
2715 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2718 "&& reload_completed"
2719 [(set (match_dup 0) (const_int 0))
2720 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2721 "operands[2] = gen_lowpart (QImode, operands[0]);")
2725 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2728 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2729 [(set (match_operand:GPR 0 "register_operand" "")
2730 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2731 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2733 rtx label1 = gen_label_rtx ();
2734 rtx label2 = gen_label_rtx ();
2735 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2736 REAL_VALUE_TYPE cmp, sub;
2738 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2739 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2740 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2742 emit_insn (gen_cmp<FPR:mode> (operands[1],
2743 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2744 emit_jump_insn (gen_blt (label1));
2745 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2746 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2747 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2751 emit_label (label1);
2752 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2753 operands[1], GEN_INT(5)));
2754 emit_label (label2);
2758 (define_expand "fix_trunc<FPR:mode>di2"
2759 [(set (match_operand:DI 0 "register_operand" "")
2760 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2761 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2763 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2764 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2769 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2770 [(set (match_operand:GPR 0 "register_operand" "=d")
2771 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2772 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2773 (clobber (reg:CC CC_REGNUM))]
2774 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2775 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2776 [(set_attr "op_type" "RRE")
2777 (set_attr "type" "ftoi")])
2780 ; fix_truncdfsi2 instruction pattern(s).
2783 (define_expand "fix_truncdfsi2"
2784 [(set (match_operand:SI 0 "register_operand" "")
2785 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2788 if (TARGET_IBM_FLOAT)
2790 /* This is the algorithm from POP chapter A.5.7.2. */
2792 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2793 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2794 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2796 operands[1] = force_reg (DFmode, operands[1]);
2797 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2798 two31r, two32, temp));
2802 operands[1] = force_reg (DFmode, operands[1]);
2803 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2809 (define_insn "fix_truncdfsi2_ibm"
2810 [(set (match_operand:SI 0 "register_operand" "=d")
2811 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2812 (use (match_operand:DI 2 "immediate_operand" "m"))
2813 (use (match_operand:DI 3 "immediate_operand" "m"))
2814 (use (match_operand:BLK 4 "memory_operand" "m"))
2815 (clobber (reg:CC CC_REGNUM))]
2816 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2818 output_asm_insn ("sd\t%1,%2", operands);
2819 output_asm_insn ("aw\t%1,%3", operands);
2820 output_asm_insn ("std\t%1,%4", operands);
2821 output_asm_insn ("xi\t%N4,128", operands);
2824 [(set_attr "length" "20")])
2827 ; fix_truncsfsi2 instruction pattern(s).
2830 (define_expand "fix_truncsfsi2"
2831 [(set (match_operand:SI 0 "register_operand" "")
2832 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2835 if (TARGET_IBM_FLOAT)
2837 /* Convert to DFmode and then use the POP algorithm. */
2838 rtx temp = gen_reg_rtx (DFmode);
2839 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2840 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2844 operands[1] = force_reg (SFmode, operands[1]);
2845 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2852 ; floatdi(df|sf)2 instruction pattern(s).
2855 (define_insn "floatdi<mode>2"
2856 [(set (match_operand:FPR 0 "register_operand" "=f")
2857 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2858 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2860 [(set_attr "op_type" "RRE")
2861 (set_attr "type" "itof" )])
2864 ; floatsidf2 instruction pattern(s).
2867 (define_expand "floatsidf2"
2868 [(set (match_operand:DF 0 "register_operand" "")
2869 (float:DF (match_operand:SI 1 "register_operand" "")))]
2872 if (TARGET_IBM_FLOAT)
2874 /* This is the algorithm from POP chapter A.5.7.1. */
2876 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2877 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2879 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2884 (define_insn "floatsidf2_ieee"
2885 [(set (match_operand:DF 0 "register_operand" "=f")
2886 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2887 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2889 [(set_attr "op_type" "RRE")
2890 (set_attr "type" "itof" )])
2892 (define_insn "floatsidf2_ibm"
2893 [(set (match_operand:DF 0 "register_operand" "=f")
2894 (float:DF (match_operand:SI 1 "register_operand" "d")))
2895 (use (match_operand:DI 2 "immediate_operand" "m"))
2896 (use (match_operand:BLK 3 "memory_operand" "m"))
2897 (clobber (reg:CC CC_REGNUM))]
2898 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2900 output_asm_insn ("st\t%1,%N3", operands);
2901 output_asm_insn ("xi\t%N3,128", operands);
2902 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2903 output_asm_insn ("ld\t%0,%3", operands);
2906 [(set_attr "length" "20")])
2909 ; floatsisf2 instruction pattern(s).
2912 (define_expand "floatsisf2"
2913 [(set (match_operand:SF 0 "register_operand" "")
2914 (float:SF (match_operand:SI 1 "register_operand" "")))]
2917 if (TARGET_IBM_FLOAT)
2919 /* Use the POP algorithm to convert to DFmode and then truncate. */
2920 rtx temp = gen_reg_rtx (DFmode);
2921 emit_insn (gen_floatsidf2 (temp, operands[1]));
2922 emit_insn (gen_truncdfsf2 (operands[0], temp));
2927 (define_insn "floatsisf2_ieee"
2928 [(set (match_operand:SF 0 "register_operand" "=f")
2929 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2930 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2932 [(set_attr "op_type" "RRE")
2933 (set_attr "type" "itof" )])
2936 ; truncdfsf2 instruction pattern(s).
2939 (define_expand "truncdfsf2"
2940 [(set (match_operand:SF 0 "register_operand" "")
2941 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2945 (define_insn "truncdfsf2_ieee"
2946 [(set (match_operand:SF 0 "register_operand" "=f")
2947 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2948 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2950 [(set_attr "op_type" "RRE")])
2952 (define_insn "truncdfsf2_ibm"
2953 [(set (match_operand:SF 0 "register_operand" "=f,f")
2954 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2955 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2959 [(set_attr "op_type" "RR,RX")
2960 (set_attr "type" "floadsf")])
2963 ; extendsfdf2 instruction pattern(s).
2966 (define_expand "extendsfdf2"
2967 [(set (match_operand:DF 0 "register_operand" "")
2968 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2971 if (TARGET_IBM_FLOAT)
2973 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2978 (define_insn "extendsfdf2_ieee"
2979 [(set (match_operand:DF 0 "register_operand" "=f,f")
2980 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2981 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2985 [(set_attr "op_type" "RRE,RXE")
2986 (set_attr "type" "floadsf")])
2988 (define_insn "extendsfdf2_ibm"
2989 [(set (match_operand:DF 0 "register_operand" "=f,f")
2990 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2991 (clobber (reg:CC CC_REGNUM))]
2992 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2994 sdr\t%0,%0\;ler\t%0,%1
2995 sdr\t%0,%0\;le\t%0,%1"
2996 [(set_attr "length" "4,6")
2997 (set_attr "type" "floadsf")])
3001 ;; ARITHMETIC OPERATIONS
3003 ; arithmetic operations set the ConditionCode,
3004 ; because of unpredictable Bits in Register for Halfword and Byte
3005 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3008 ;;- Add instructions.
3012 ; addti3 instruction pattern(s).
3015 (define_insn_and_split "addti3"
3016 [(set (match_operand:TI 0 "register_operand" "=&d")
3017 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3018 (match_operand:TI 2 "general_operand" "do") ) )
3019 (clobber (reg:CC CC_REGNUM))]
3022 "&& reload_completed"
3024 [(set (reg:CCL1 CC_REGNUM)
3025 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3027 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3029 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3030 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3031 (clobber (reg:CC CC_REGNUM))])]
3032 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3033 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3034 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3035 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3036 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3037 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3040 ; adddi3 instruction pattern(s).
3043 (define_insn "*adddi3_sign"
3044 [(set (match_operand:DI 0 "register_operand" "=d,d")
3045 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3046 (match_operand:DI 1 "register_operand" "0,0")))
3047 (clobber (reg:CC CC_REGNUM))]
3052 [(set_attr "op_type" "RRE,RXY")])
3054 (define_insn "*adddi3_zero_cc"
3055 [(set (reg CC_REGNUM)
3056 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3057 (match_operand:DI 1 "register_operand" "0,0"))
3059 (set (match_operand:DI 0 "register_operand" "=d,d")
3060 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3061 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3065 [(set_attr "op_type" "RRE,RXY")])
3067 (define_insn "*adddi3_zero_cconly"
3068 [(set (reg CC_REGNUM)
3069 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3070 (match_operand:DI 1 "register_operand" "0,0"))
3072 (clobber (match_scratch:DI 0 "=d,d"))]
3073 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3077 [(set_attr "op_type" "RRE,RXY")])
3079 (define_insn "*adddi3_zero"
3080 [(set (match_operand:DI 0 "register_operand" "=d,d")
3081 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3082 (match_operand:DI 1 "register_operand" "0,0")))
3083 (clobber (reg:CC CC_REGNUM))]
3088 [(set_attr "op_type" "RRE,RXY")])
3090 (define_insn "*adddi3_imm_cc"
3091 [(set (reg CC_REGNUM)
3092 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3093 (match_operand:DI 2 "const_int_operand" "K"))
3095 (set (match_operand:DI 0 "register_operand" "=d")
3096 (plus:DI (match_dup 1) (match_dup 2)))]
3098 && s390_match_ccmode (insn, CCAmode)
3099 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3101 [(set_attr "op_type" "RI")])
3103 (define_insn "*adddi3_carry1_cc"
3104 [(set (reg CC_REGNUM)
3105 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3106 (match_operand:DI 2 "general_operand" "d,m"))
3108 (set (match_operand:DI 0 "register_operand" "=d,d")
3109 (plus:DI (match_dup 1) (match_dup 2)))]
3110 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3114 [(set_attr "op_type" "RRE,RXY")])
3116 (define_insn "*adddi3_carry1_cconly"
3117 [(set (reg CC_REGNUM)
3118 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3119 (match_operand:DI 2 "general_operand" "d,m"))
3121 (clobber (match_scratch:DI 0 "=d,d"))]
3122 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3126 [(set_attr "op_type" "RRE,RXY")])
3128 (define_insn "*adddi3_carry2_cc"
3129 [(set (reg CC_REGNUM)
3130 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3131 (match_operand:DI 2 "general_operand" "d,m"))
3133 (set (match_operand:DI 0 "register_operand" "=d,d")
3134 (plus:DI (match_dup 1) (match_dup 2)))]
3135 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3139 [(set_attr "op_type" "RRE,RXY")])
3141 (define_insn "*adddi3_carry2_cconly"
3142 [(set (reg CC_REGNUM)
3143 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3144 (match_operand:DI 2 "general_operand" "d,m"))
3146 (clobber (match_scratch:DI 0 "=d,d"))]
3147 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3151 [(set_attr "op_type" "RRE,RXY")])
3153 (define_insn "*adddi3_cc"
3154 [(set (reg CC_REGNUM)
3155 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3156 (match_operand:DI 2 "general_operand" "d,m"))
3158 (set (match_operand:DI 0 "register_operand" "=d,d")
3159 (plus:DI (match_dup 1) (match_dup 2)))]
3160 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3164 [(set_attr "op_type" "RRE,RXY")])
3166 (define_insn "*adddi3_cconly"
3167 [(set (reg CC_REGNUM)
3168 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3169 (match_operand:DI 2 "general_operand" "d,m"))
3171 (clobber (match_scratch:DI 0 "=d,d"))]
3172 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3176 [(set_attr "op_type" "RRE,RXY")])
3178 (define_insn "*adddi3_cconly2"
3179 [(set (reg CC_REGNUM)
3180 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3181 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3182 (clobber (match_scratch:DI 0 "=d,d"))]
3183 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3187 [(set_attr "op_type" "RRE,RXY")])
3189 (define_insn "*adddi3_64"
3190 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3191 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3192 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3193 (clobber (reg:CC CC_REGNUM))]
3199 [(set_attr "op_type" "RRE,RI,RXY")])
3201 (define_insn_and_split "*adddi3_31z"
3202 [(set (match_operand:DI 0 "register_operand" "=&d")
3203 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3204 (match_operand:DI 2 "general_operand" "do") ) )
3205 (clobber (reg:CC CC_REGNUM))]
3206 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3208 "&& reload_completed"
3210 [(set (reg:CCL1 CC_REGNUM)
3211 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3213 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3215 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3216 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3217 (clobber (reg:CC CC_REGNUM))])]
3218 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3219 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3220 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3221 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3222 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3223 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3225 (define_insn_and_split "*adddi3_31"
3226 [(set (match_operand:DI 0 "register_operand" "=&d")
3227 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3228 (match_operand:DI 2 "general_operand" "do") ) )
3229 (clobber (reg:CC CC_REGNUM))]
3232 "&& reload_completed"
3234 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3235 (clobber (reg:CC CC_REGNUM))])
3237 [(set (reg:CCL1 CC_REGNUM)
3238 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3240 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3242 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3244 (label_ref (match_dup 9))))
3246 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3247 (clobber (reg:CC CC_REGNUM))])
3249 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3250 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3251 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3252 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3253 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3254 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3255 operands[9] = gen_label_rtx ();")
3257 (define_expand "adddi3"
3259 [(set (match_operand:DI 0 "register_operand" "")
3260 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3261 (match_operand:DI 2 "general_operand" "")))
3262 (clobber (reg:CC CC_REGNUM))])]
3267 ; addsi3 instruction pattern(s).
3270 (define_insn "*addsi3_imm_cc"
3271 [(set (reg CC_REGNUM)
3272 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3273 (match_operand:SI 2 "const_int_operand" "K"))
3275 (set (match_operand:SI 0 "register_operand" "=d")
3276 (plus:SI (match_dup 1) (match_dup 2)))]
3277 "s390_match_ccmode (insn, CCAmode)
3278 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3280 [(set_attr "op_type" "RI")])
3282 (define_insn "*addsi3_carry1_cc"
3283 [(set (reg CC_REGNUM)
3284 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3285 (match_operand:SI 2 "general_operand" "d,R,T"))
3287 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3288 (plus:SI (match_dup 1) (match_dup 2)))]
3289 "s390_match_ccmode (insn, CCL1mode)"
3294 [(set_attr "op_type" "RR,RX,RXY")])
3296 (define_insn "*addsi3_carry1_cconly"
3297 [(set (reg CC_REGNUM)
3298 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3299 (match_operand:SI 2 "general_operand" "d,R,T"))
3301 (clobber (match_scratch:SI 0 "=d,d,d"))]
3302 "s390_match_ccmode (insn, CCL1mode)"
3307 [(set_attr "op_type" "RR,RX,RXY")])
3309 (define_insn "*addsi3_carry2_cc"
3310 [(set (reg CC_REGNUM)
3311 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3312 (match_operand:SI 2 "general_operand" "d,R,T"))
3314 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3315 (plus:SI (match_dup 1) (match_dup 2)))]
3316 "s390_match_ccmode (insn, CCL1mode)"
3321 [(set_attr "op_type" "RR,RX,RXY")])
3323 (define_insn "*addsi3_carry2_cconly"
3324 [(set (reg CC_REGNUM)
3325 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3326 (match_operand:SI 2 "general_operand" "d,R,T"))
3328 (clobber (match_scratch:SI 0 "=d,d,d"))]
3329 "s390_match_ccmode (insn, CCL1mode)"
3334 [(set_attr "op_type" "RR,RX,RXY")])
3336 (define_insn "*addsi3_cc"
3337 [(set (reg CC_REGNUM)
3338 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3339 (match_operand:SI 2 "general_operand" "d,R,T"))
3341 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3342 (plus:SI (match_dup 1) (match_dup 2)))]
3343 "s390_match_ccmode (insn, CCLmode)"
3348 [(set_attr "op_type" "RR,RX,RXY")])
3350 (define_insn "*addsi3_cconly"
3351 [(set (reg CC_REGNUM)
3352 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3353 (match_operand:SI 2 "general_operand" "d,R,T"))
3355 (clobber (match_scratch:SI 0 "=d,d,d"))]
3356 "s390_match_ccmode (insn, CCLmode)"
3361 [(set_attr "op_type" "RR,RX,RXY")])
3363 (define_insn "*addsi3_cconly2"
3364 [(set (reg CC_REGNUM)
3365 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3366 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3367 (clobber (match_scratch:SI 0 "=d,d,d"))]
3368 "s390_match_ccmode (insn, CCLmode)"
3373 [(set_attr "op_type" "RR,RX,RXY")])
3375 (define_insn "*addsi3_sign"
3376 [(set (match_operand:SI 0 "register_operand" "=d,d")
3377 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3378 (match_operand:SI 1 "register_operand" "0,0")))
3379 (clobber (reg:CC CC_REGNUM))]
3384 [(set_attr "op_type" "RX,RXY")])
3386 (define_insn "addsi3"
3387 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3388 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3389 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3390 (clobber (reg:CC CC_REGNUM))]
3397 [(set_attr "op_type" "RR,RI,RX,RXY")])
3400 ; add(df|sf)3 instruction pattern(s).
3403 (define_expand "add<mode>3"
3405 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3406 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3407 (match_operand:FPR 2 "general_operand" "f,R")))
3408 (clobber (reg:CC CC_REGNUM))])]
3412 (define_insn "*add<mode>3"
3413 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3414 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3415 (match_operand:FPR 2 "general_operand" "f,R")))
3416 (clobber (reg:CC CC_REGNUM))]
3417 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3421 [(set_attr "op_type" "RRE,RXE")
3422 (set_attr "type" "fsimp<mode>")])
3424 (define_insn "*add<mode>3_cc"
3425 [(set (reg CC_REGNUM)
3426 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3427 (match_operand:FPR 2 "general_operand" "f,R"))
3428 (match_operand:FPR 3 "const0_operand" "")))
3429 (set (match_operand:FPR 0 "register_operand" "=f,f")
3430 (plus:FPR (match_dup 1) (match_dup 2)))]
3431 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3435 [(set_attr "op_type" "RRE,RXE")
3436 (set_attr "type" "fsimp<mode>")])
3438 (define_insn "*add<mode>3_cconly"
3439 [(set (reg CC_REGNUM)
3440 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3441 (match_operand:FPR 2 "general_operand" "f,R"))
3442 (match_operand:FPR 3 "const0_operand" "")))
3443 (clobber (match_scratch:FPR 0 "=f,f"))]
3444 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3448 [(set_attr "op_type" "RRE,RXE")
3449 (set_attr "type" "fsimp<mode>")])
3451 (define_insn "*add<mode>3_ibm"
3452 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3453 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3454 (match_operand:FPR 2 "general_operand" "f,R")))
3455 (clobber (reg:CC CC_REGNUM))]
3456 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3460 [(set_attr "op_type" "RR,RX")
3461 (set_attr "type" "fsimp<mode>")])
3465 ;;- Subtract instructions.
3469 ; subti3 instruction pattern(s).
3472 (define_insn_and_split "subti3"
3473 [(set (match_operand:TI 0 "register_operand" "=&d")
3474 (minus:TI (match_operand:TI 1 "register_operand" "0")
3475 (match_operand:TI 2 "general_operand" "do") ) )
3476 (clobber (reg:CC CC_REGNUM))]
3479 "&& reload_completed"
3481 [(set (reg:CCL2 CC_REGNUM)
3482 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3484 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3486 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3487 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3488 (clobber (reg:CC CC_REGNUM))])]
3489 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3490 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3491 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3492 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3493 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3494 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3497 ; subdi3 instruction pattern(s).
3500 (define_insn "*subdi3_sign"
3501 [(set (match_operand:DI 0 "register_operand" "=d,d")
3502 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3503 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3504 (clobber (reg:CC CC_REGNUM))]
3509 [(set_attr "op_type" "RRE,RXY")])
3511 (define_insn "*subdi3_zero_cc"
3512 [(set (reg CC_REGNUM)
3513 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3514 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3516 (set (match_operand:DI 0 "register_operand" "=d,d")
3517 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3518 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3522 [(set_attr "op_type" "RRE,RXY")])
3524 (define_insn "*subdi3_zero_cconly"
3525 [(set (reg CC_REGNUM)
3526 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3527 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3529 (clobber (match_scratch:DI 0 "=d,d"))]
3530 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3534 [(set_attr "op_type" "RRE,RXY")])
3536 (define_insn "*subdi3_zero"
3537 [(set (match_operand:DI 0 "register_operand" "=d,d")
3538 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3539 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3540 (clobber (reg:CC CC_REGNUM))]
3545 [(set_attr "op_type" "RRE,RXY")])
3547 (define_insn "*subdi3_borrow_cc"
3548 [(set (reg CC_REGNUM)
3549 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3550 (match_operand:DI 2 "general_operand" "d,m"))
3552 (set (match_operand:DI 0 "register_operand" "=d,d")
3553 (minus:DI (match_dup 1) (match_dup 2)))]
3554 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3558 [(set_attr "op_type" "RRE,RXY")])
3560 (define_insn "*subdi3_borrow_cconly"
3561 [(set (reg CC_REGNUM)
3562 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3563 (match_operand:DI 2 "general_operand" "d,m"))
3565 (clobber (match_scratch:DI 0 "=d,d"))]
3566 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3570 [(set_attr "op_type" "RRE,RXY")])
3572 (define_insn "*subdi3_cc"
3573 [(set (reg CC_REGNUM)
3574 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3575 (match_operand:DI 2 "general_operand" "d,m"))
3577 (set (match_operand:DI 0 "register_operand" "=d,d")
3578 (minus:DI (match_dup 1) (match_dup 2)))]
3579 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3583 [(set_attr "op_type" "RRE,RXY")])
3585 (define_insn "*subdi3_cc2"
3586 [(set (reg CC_REGNUM)
3587 (compare (match_operand:DI 1 "register_operand" "0,0")
3588 (match_operand:DI 2 "general_operand" "d,m")))
3589 (set (match_operand:DI 0 "register_operand" "=d,d")
3590 (minus:DI (match_dup 1) (match_dup 2)))]
3591 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3595 [(set_attr "op_type" "RRE,RXY")])
3597 (define_insn "*subdi3_cconly"
3598 [(set (reg CC_REGNUM)
3599 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3600 (match_operand:DI 2 "general_operand" "d,m"))
3602 (clobber (match_scratch:DI 0 "=d,d"))]
3603 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3607 [(set_attr "op_type" "RRE,RXY")])
3609 (define_insn "*subdi3_cconly2"
3610 [(set (reg CC_REGNUM)
3611 (compare (match_operand:DI 1 "register_operand" "0,0")
3612 (match_operand:DI 2 "general_operand" "d,m")))
3613 (clobber (match_scratch:DI 0 "=d,d"))]
3614 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3618 [(set_attr "op_type" "RRE,RXY")])
3620 (define_insn "*subdi3_64"
3621 [(set (match_operand:DI 0 "register_operand" "=d,d")
3622 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3623 (match_operand:DI 2 "general_operand" "d,m") ) )
3624 (clobber (reg:CC CC_REGNUM))]
3629 [(set_attr "op_type" "RRE,RRE")])
3631 (define_insn_and_split "*subdi3_31z"
3632 [(set (match_operand:DI 0 "register_operand" "=&d")
3633 (minus:DI (match_operand:DI 1 "register_operand" "0")
3634 (match_operand:DI 2 "general_operand" "do") ) )
3635 (clobber (reg:CC CC_REGNUM))]
3636 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3638 "&& reload_completed"
3640 [(set (reg:CCL2 CC_REGNUM)
3641 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3643 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3645 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3646 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3647 (clobber (reg:CC CC_REGNUM))])]
3648 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3649 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3650 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3651 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3652 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3653 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3655 (define_insn_and_split "*subdi3_31"
3656 [(set (match_operand:DI 0 "register_operand" "=&d")
3657 (minus:DI (match_operand:DI 1 "register_operand" "0")
3658 (match_operand:DI 2 "general_operand" "do") ) )
3659 (clobber (reg:CC CC_REGNUM))]
3662 "&& reload_completed"
3664 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3665 (clobber (reg:CC CC_REGNUM))])
3667 [(set (reg:CCL2 CC_REGNUM)
3668 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3670 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3672 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3674 (label_ref (match_dup 9))))
3676 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3677 (clobber (reg:CC CC_REGNUM))])
3679 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3680 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3681 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3682 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3683 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3684 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3685 operands[9] = gen_label_rtx ();")
3687 (define_expand "subdi3"
3689 [(set (match_operand:DI 0 "register_operand" "")
3690 (minus:DI (match_operand:DI 1 "register_operand" "")
3691 (match_operand:DI 2 "general_operand" "")))
3692 (clobber (reg:CC CC_REGNUM))])]
3697 ; subsi3 instruction pattern(s).
3700 (define_insn "*subsi3_borrow_cc"
3701 [(set (reg CC_REGNUM)
3702 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3703 (match_operand:SI 2 "general_operand" "d,R,T"))
3705 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3706 (minus:SI (match_dup 1) (match_dup 2)))]
3707 "s390_match_ccmode (insn, CCL2mode)"
3712 [(set_attr "op_type" "RR,RX,RXY")])
3714 (define_insn "*subsi3_borrow_cconly"
3715 [(set (reg CC_REGNUM)
3716 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3717 (match_operand:SI 2 "general_operand" "d,R,T"))
3719 (clobber (match_scratch:SI 0 "=d,d,d"))]
3720 "s390_match_ccmode (insn, CCL2mode)"
3725 [(set_attr "op_type" "RR,RX,RXY")])
3727 (define_insn "*subsi3_cc"
3728 [(set (reg CC_REGNUM)
3729 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3730 (match_operand:SI 2 "general_operand" "d,R,T"))
3732 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3733 (minus:SI (match_dup 1) (match_dup 2)))]
3734 "s390_match_ccmode (insn, CCLmode)"
3739 [(set_attr "op_type" "RR,RX,RXY")])
3741 (define_insn "*subsi3_cc2"
3742 [(set (reg CC_REGNUM)
3743 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3744 (match_operand:SI 2 "general_operand" "d,R,T")))
3745 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3746 (minus:SI (match_dup 1) (match_dup 2)))]
3747 "s390_match_ccmode (insn, CCL3mode)"
3752 [(set_attr "op_type" "RR,RX,RXY")])
3754 (define_insn "*subsi3_cconly"
3755 [(set (reg CC_REGNUM)
3756 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3757 (match_operand:SI 2 "general_operand" "d,R,T"))
3759 (clobber (match_scratch:SI 0 "=d,d,d"))]
3760 "s390_match_ccmode (insn, CCLmode)"
3765 [(set_attr "op_type" "RR,RX,RXY")])
3767 (define_insn "*subsi3_cconly2"
3768 [(set (reg CC_REGNUM)
3769 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3770 (match_operand:SI 2 "general_operand" "d,R,T")))
3771 (clobber (match_scratch:SI 0 "=d,d,d"))]
3772 "s390_match_ccmode (insn, CCL3mode)"
3777 [(set_attr "op_type" "RR,RX,RXY")])
3779 (define_insn "*subsi3_sign"
3780 [(set (match_operand:SI 0 "register_operand" "=d,d")
3781 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3782 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3783 (clobber (reg:CC CC_REGNUM))]
3788 [(set_attr "op_type" "RX,RXY")])
3790 (define_insn "subsi3"
3791 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3792 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3793 (match_operand:SI 2 "general_operand" "d,R,T")))
3794 (clobber (reg:CC CC_REGNUM))]
3800 [(set_attr "op_type" "RR,RX,RXY")])
3804 ; sub(df|sf)3 instruction pattern(s).
3807 (define_expand "sub<mode>3"
3809 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3810 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3811 (match_operand:FPR 2 "general_operand" "f,R")))
3812 (clobber (reg:CC CC_REGNUM))])]
3816 (define_insn "*sub<mode>3"
3817 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3818 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3819 (match_operand:FPR 2 "general_operand" "f,R")))
3820 (clobber (reg:CC CC_REGNUM))]
3821 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3825 [(set_attr "op_type" "RRE,RXE")
3826 (set_attr "type" "fsimp<mode>")])
3828 (define_insn "*sub<mode>3_cc"
3829 [(set (reg CC_REGNUM)
3830 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3831 (match_operand:FPR 2 "general_operand" "f,R"))
3832 (match_operand:FPR 3 "const0_operand" "")))
3833 (set (match_operand:FPR 0 "register_operand" "=f,f")
3834 (minus:FPR (match_dup 1) (match_dup 2)))]
3835 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3839 [(set_attr "op_type" "RRE,RXE")
3840 (set_attr "type" "fsimp<mode>")])
3842 (define_insn "*sub<mode>3_cconly"
3843 [(set (reg CC_REGNUM)
3844 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3845 (match_operand:FPR 2 "general_operand" "f,R"))
3846 (match_operand:FPR 3 "const0_operand" "")))
3847 (clobber (match_scratch:FPR 0 "=f,f"))]
3848 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3852 [(set_attr "op_type" "RRE,RXE")
3853 (set_attr "type" "fsimp<mode>")])
3855 (define_insn "*sub<mode>3_ibm"
3856 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3857 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3858 (match_operand:FPR 2 "general_operand" "f,R")))
3859 (clobber (reg:CC CC_REGNUM))]
3860 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3864 [(set_attr "op_type" "RR,RX")
3865 (set_attr "type" "fsimp<mode>")])
3869 ;;- Conditional add/subtract instructions.
3873 ; add(di|si)cc instruction pattern(s).
3876 (define_insn "*add<mode>3_alc_cc"
3877 [(set (reg CC_REGNUM)
3879 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3880 (match_operand:GPR 2 "general_operand" "d,m"))
3881 (match_operand:GPR 3 "s390_alc_comparison" ""))
3883 (set (match_operand:GPR 0 "register_operand" "=d,d")
3884 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3885 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3889 [(set_attr "op_type" "RRE,RXY")])
3891 (define_insn "*add<mode>3_alc"
3892 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3893 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3894 (match_operand:GPR 2 "general_operand" "d,m"))
3895 (match_operand:GPR 3 "s390_alc_comparison" "")))
3896 (clobber (reg:CC CC_REGNUM))]
3901 [(set_attr "op_type" "RRE,RXY")])
3903 (define_insn "*sub<mode>3_slb_cc"
3904 [(set (reg CC_REGNUM)
3906 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3907 (match_operand:GPR 2 "general_operand" "d,m"))
3908 (match_operand:GPR 3 "s390_slb_comparison" ""))
3910 (set (match_operand:GPR 0 "register_operand" "=d,d")
3911 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3912 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3916 [(set_attr "op_type" "RRE,RXY")])
3918 (define_insn "*sub<mode>3_slb"
3919 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3920 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3921 (match_operand:GPR 2 "general_operand" "d,m"))
3922 (match_operand:GPR 3 "s390_slb_comparison" "")))
3923 (clobber (reg:CC CC_REGNUM))]
3928 [(set_attr "op_type" "RRE,RXY")])
3930 (define_expand "add<mode>cc"
3931 [(match_operand:GPR 0 "register_operand" "")
3932 (match_operand 1 "comparison_operator" "")
3933 (match_operand:GPR 2 "register_operand" "")
3934 (match_operand:GPR 3 "const_int_operand" "")]
3936 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3937 s390_compare_op0, s390_compare_op1,
3938 operands[0], operands[2],
3939 operands[3])) FAIL; DONE;")
3942 ; scond instruction pattern(s).
3945 (define_insn_and_split "*scond<mode>"
3946 [(set (match_operand:GPR 0 "register_operand" "=&d")
3947 (match_operand:GPR 1 "s390_alc_comparison" ""))
3948 (clobber (reg:CC CC_REGNUM))]
3951 "&& reload_completed"
3952 [(set (match_dup 0) (const_int 0))
3954 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3956 (clobber (reg:CC CC_REGNUM))])]
3959 (define_insn_and_split "*scond<mode>_neg"
3960 [(set (match_operand:GPR 0 "register_operand" "=&d")
3961 (match_operand:GPR 1 "s390_slb_comparison" ""))
3962 (clobber (reg:CC CC_REGNUM))]
3965 "&& reload_completed"
3966 [(set (match_dup 0) (const_int 0))
3968 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3970 (clobber (reg:CC CC_REGNUM))])
3972 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3973 (clobber (reg:CC CC_REGNUM))])]
3977 (define_expand "s<code>"
3978 [(set (match_operand:SI 0 "register_operand" "")
3979 (SCOND (match_dup 0)
3982 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3983 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3985 (define_expand "seq"
3987 [(set (match_operand:SI 0 "register_operand" "=d")
3989 (clobber (reg:CC CC_REGNUM))])
3991 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
3992 (clobber (reg:CC CC_REGNUM))])]
3995 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
3997 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
3998 PUT_MODE (operands[1], SImode);
4001 (define_insn_and_split "*sne"
4002 [(set (match_operand:SI 0 "register_operand" "=d")
4003 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4005 (clobber (reg:CC CC_REGNUM))]
4010 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4011 (clobber (reg:CC CC_REGNUM))])])
4015 ;;- Multiply instructions.
4019 ; muldi3 instruction pattern(s).
4022 (define_insn "*muldi3_sign"
4023 [(set (match_operand:DI 0 "register_operand" "=d,d")
4024 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4025 (match_operand:DI 1 "register_operand" "0,0")))]
4030 [(set_attr "op_type" "RRE,RXY")
4031 (set_attr "type" "imuldi")])
4033 (define_insn "muldi3"
4034 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4035 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4036 (match_operand:DI 2 "general_operand" "d,K,m")))]
4042 [(set_attr "op_type" "RRE,RI,RXY")
4043 (set_attr "type" "imuldi")])
4046 ; mulsi3 instruction pattern(s).
4049 (define_insn "*mulsi3_sign"
4050 [(set (match_operand:SI 0 "register_operand" "=d")
4051 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4052 (match_operand:SI 1 "register_operand" "0")))]
4055 [(set_attr "op_type" "RX")
4056 (set_attr "type" "imulhi")])
4058 (define_insn "mulsi3"
4059 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4060 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4061 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4068 [(set_attr "op_type" "RRE,RI,RX,RXY")
4069 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4072 ; mulsidi3 instruction pattern(s).
4075 (define_insn "mulsidi3"
4076 [(set (match_operand:DI 0 "register_operand" "=d,d")
4077 (mult:DI (sign_extend:DI
4078 (match_operand:SI 1 "register_operand" "%0,0"))
4080 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4085 [(set_attr "op_type" "RR,RX")
4086 (set_attr "type" "imulsi")])
4089 ; umulsidi3 instruction pattern(s).
4092 (define_insn "umulsidi3"
4093 [(set (match_operand:DI 0 "register_operand" "=d,d")
4094 (mult:DI (zero_extend:DI
4095 (match_operand:SI 1 "register_operand" "%0,0"))
4097 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4098 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4102 [(set_attr "op_type" "RRE,RXY")
4103 (set_attr "type" "imulsi")])
4106 ; mul(df|sf)3 instruction pattern(s).
4109 (define_expand "mul<mode>3"
4110 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4111 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4112 (match_operand:FPR 2 "general_operand" "f,R")))]
4116 (define_insn "*mul<mode>3"
4117 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4118 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4119 (match_operand:FPR 2 "general_operand" "f,R")))]
4120 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4124 [(set_attr "op_type" "RRE,RXE")
4125 (set_attr "type" "fmul<mode>")])
4127 (define_insn "*mul<mode>3_ibm"
4128 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4129 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4130 (match_operand:FPR 2 "general_operand" "f,R")))]
4131 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4135 [(set_attr "op_type" "RR,RX")
4136 (set_attr "type" "fmul<mode>")])
4138 (define_insn "*fmadd<mode>"
4139 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4140 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4141 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4142 (match_operand:FPR 3 "register_operand" "0,0")))]
4143 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4147 [(set_attr "op_type" "RRE,RXE")
4148 (set_attr "type" "fmul<mode>")])
4150 (define_insn "*fmsub<mode>"
4151 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4152 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4153 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4154 (match_operand:FPR 3 "register_operand" "0,0")))]
4155 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4159 [(set_attr "op_type" "RRE,RXE")
4160 (set_attr "type" "fmul<mode>")])
4163 ;;- Divide and modulo instructions.
4167 ; divmoddi4 instruction pattern(s).
4170 (define_expand "divmoddi4"
4171 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4172 (div:DI (match_operand:DI 1 "register_operand" "")
4173 (match_operand:DI 2 "general_operand" "")))
4174 (set (match_operand:DI 3 "general_operand" "")
4175 (mod:DI (match_dup 1) (match_dup 2)))])
4176 (clobber (match_dup 4))]
4179 rtx insn, div_equal, mod_equal;
4181 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4182 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4184 operands[4] = gen_reg_rtx(TImode);
4185 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4187 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4189 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4191 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4193 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4198 (define_insn "divmodtidi3"
4199 [(set (match_operand:TI 0 "register_operand" "=d,d")
4203 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4204 (match_operand:DI 2 "general_operand" "d,m")))
4206 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4211 [(set_attr "op_type" "RRE,RXY")
4212 (set_attr "type" "idiv")])
4214 (define_insn "divmodtisi3"
4215 [(set (match_operand:TI 0 "register_operand" "=d,d")
4219 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4221 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4224 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4229 [(set_attr "op_type" "RRE,RXY")
4230 (set_attr "type" "idiv")])
4233 ; udivmoddi4 instruction pattern(s).
4236 (define_expand "udivmoddi4"
4237 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4238 (udiv:DI (match_operand:DI 1 "general_operand" "")
4239 (match_operand:DI 2 "nonimmediate_operand" "")))
4240 (set (match_operand:DI 3 "general_operand" "")
4241 (umod:DI (match_dup 1) (match_dup 2)))])
4242 (clobber (match_dup 4))]
4245 rtx insn, div_equal, mod_equal, equal;
4247 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4248 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4249 equal = gen_rtx_IOR (TImode,
4250 gen_rtx_ASHIFT (TImode,
4251 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4253 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4255 operands[4] = gen_reg_rtx(TImode);
4256 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4257 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4258 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4259 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4261 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4263 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4265 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4267 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4269 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4274 (define_insn "udivmodtidi3"
4275 [(set (match_operand:TI 0 "register_operand" "=d,d")
4280 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4282 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4286 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4291 [(set_attr "op_type" "RRE,RXY")
4292 (set_attr "type" "idiv")])
4295 ; divmodsi4 instruction pattern(s).
4298 (define_expand "divmodsi4"
4299 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4300 (div:SI (match_operand:SI 1 "general_operand" "")
4301 (match_operand:SI 2 "nonimmediate_operand" "")))
4302 (set (match_operand:SI 3 "general_operand" "")
4303 (mod:SI (match_dup 1) (match_dup 2)))])
4304 (clobber (match_dup 4))]
4307 rtx insn, div_equal, mod_equal, equal;
4309 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4310 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4311 equal = gen_rtx_IOR (DImode,
4312 gen_rtx_ASHIFT (DImode,
4313 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4315 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4317 operands[4] = gen_reg_rtx(DImode);
4318 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4319 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4321 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4323 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4325 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4327 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4329 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4334 (define_insn "divmoddisi3"
4335 [(set (match_operand:DI 0 "register_operand" "=d,d")
4340 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4342 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4346 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4351 [(set_attr "op_type" "RR,RX")
4352 (set_attr "type" "idiv")])
4355 ; udivsi3 and umodsi3 instruction pattern(s).
4358 (define_expand "udivmodsi4"
4359 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4360 (udiv:SI (match_operand:SI 1 "general_operand" "")
4361 (match_operand:SI 2 "nonimmediate_operand" "")))
4362 (set (match_operand:SI 3 "general_operand" "")
4363 (umod:SI (match_dup 1) (match_dup 2)))])
4364 (clobber (match_dup 4))]
4365 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4367 rtx insn, div_equal, mod_equal, equal;
4369 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4370 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4371 equal = gen_rtx_IOR (DImode,
4372 gen_rtx_ASHIFT (DImode,
4373 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4375 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4377 operands[4] = gen_reg_rtx(DImode);
4378 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4379 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4380 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4381 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4383 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4385 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4387 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4389 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4391 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4396 (define_insn "udivmoddisi3"
4397 [(set (match_operand:DI 0 "register_operand" "=d,d")
4402 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4404 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4408 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4409 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4413 [(set_attr "op_type" "RRE,RXY")
4414 (set_attr "type" "idiv")])
4416 (define_expand "udivsi3"
4417 [(set (match_operand:SI 0 "register_operand" "=d")
4418 (udiv:SI (match_operand:SI 1 "general_operand" "")
4419 (match_operand:SI 2 "general_operand" "")))
4420 (clobber (match_dup 3))]
4421 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4423 rtx insn, udiv_equal, umod_equal, equal;
4425 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4426 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4427 equal = gen_rtx_IOR (DImode,
4428 gen_rtx_ASHIFT (DImode,
4429 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4431 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4433 operands[3] = gen_reg_rtx (DImode);
4435 if (CONSTANT_P (operands[2]))
4437 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4439 rtx label1 = gen_label_rtx ();
4441 operands[1] = make_safe_from (operands[1], operands[0]);
4442 emit_move_insn (operands[0], const0_rtx);
4443 emit_insn (gen_cmpsi (operands[1], operands[2]));
4444 emit_jump_insn (gen_bltu (label1));
4445 emit_move_insn (operands[0], const1_rtx);
4446 emit_label (label1);
4450 operands[2] = force_reg (SImode, operands[2]);
4451 operands[2] = make_safe_from (operands[2], operands[0]);
4453 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4454 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4457 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4459 insn = emit_move_insn (operands[0],
4460 gen_lowpart (SImode, operands[3]));
4462 gen_rtx_EXPR_LIST (REG_EQUAL,
4463 udiv_equal, REG_NOTES (insn));
4468 rtx label1 = gen_label_rtx ();
4469 rtx label2 = gen_label_rtx ();
4470 rtx label3 = gen_label_rtx ();
4472 operands[1] = force_reg (SImode, operands[1]);
4473 operands[1] = make_safe_from (operands[1], operands[0]);
4474 operands[2] = force_reg (SImode, operands[2]);
4475 operands[2] = make_safe_from (operands[2], operands[0]);
4477 emit_move_insn (operands[0], const0_rtx);
4478 emit_insn (gen_cmpsi (operands[2], operands[1]));
4479 emit_jump_insn (gen_bgtu (label3));
4480 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4481 emit_jump_insn (gen_blt (label2));
4482 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4483 emit_jump_insn (gen_beq (label1));
4484 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4485 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4488 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4490 insn = emit_move_insn (operands[0],
4491 gen_lowpart (SImode, operands[3]));
4493 gen_rtx_EXPR_LIST (REG_EQUAL,
4494 udiv_equal, REG_NOTES (insn));
4496 emit_label (label1);
4497 emit_move_insn (operands[0], operands[1]);
4499 emit_label (label2);
4500 emit_move_insn (operands[0], const1_rtx);
4501 emit_label (label3);
4503 emit_move_insn (operands[0], operands[0]);
4507 (define_expand "umodsi3"
4508 [(set (match_operand:SI 0 "register_operand" "=d")
4509 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4510 (match_operand:SI 2 "nonimmediate_operand" "")))
4511 (clobber (match_dup 3))]
4512 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4514 rtx insn, udiv_equal, umod_equal, equal;
4516 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4517 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4518 equal = gen_rtx_IOR (DImode,
4519 gen_rtx_ASHIFT (DImode,
4520 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4522 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4524 operands[3] = gen_reg_rtx (DImode);
4526 if (CONSTANT_P (operands[2]))
4528 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4530 rtx label1 = gen_label_rtx ();
4532 operands[1] = make_safe_from (operands[1], operands[0]);
4533 emit_move_insn (operands[0], operands[1]);
4534 emit_insn (gen_cmpsi (operands[0], operands[2]));
4535 emit_jump_insn (gen_bltu (label1));
4536 emit_insn (gen_abssi2 (operands[0], operands[2]));
4537 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4538 emit_label (label1);
4542 operands[2] = force_reg (SImode, operands[2]);
4543 operands[2] = make_safe_from (operands[2], operands[0]);
4545 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4546 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4549 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4551 insn = emit_move_insn (operands[0],
4552 gen_highpart (SImode, operands[3]));
4554 gen_rtx_EXPR_LIST (REG_EQUAL,
4555 umod_equal, REG_NOTES (insn));
4560 rtx label1 = gen_label_rtx ();
4561 rtx label2 = gen_label_rtx ();
4562 rtx label3 = gen_label_rtx ();
4564 operands[1] = force_reg (SImode, operands[1]);
4565 operands[1] = make_safe_from (operands[1], operands[0]);
4566 operands[2] = force_reg (SImode, operands[2]);
4567 operands[2] = make_safe_from (operands[2], operands[0]);
4569 emit_move_insn(operands[0], operands[1]);
4570 emit_insn (gen_cmpsi (operands[2], operands[1]));
4571 emit_jump_insn (gen_bgtu (label3));
4572 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4573 emit_jump_insn (gen_blt (label2));
4574 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4575 emit_jump_insn (gen_beq (label1));
4576 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4577 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4580 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4582 insn = emit_move_insn (operands[0],
4583 gen_highpart (SImode, operands[3]));
4585 gen_rtx_EXPR_LIST (REG_EQUAL,
4586 umod_equal, REG_NOTES (insn));
4588 emit_label (label1);
4589 emit_move_insn (operands[0], const0_rtx);
4591 emit_label (label2);
4592 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4593 emit_label (label3);
4599 ; div(df|sf)3 instruction pattern(s).
4602 (define_expand "div<mode>3"
4603 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4604 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4605 (match_operand:FPR 2 "general_operand" "f,R")))]
4609 (define_insn "*div<mode>3"
4610 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4611 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4612 (match_operand:FPR 2 "general_operand" "f,R")))]
4613 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4617 [(set_attr "op_type" "RRE,RXE")
4618 (set_attr "type" "fdiv<mode>")])
4620 (define_insn "*div<mode>3_ibm"
4621 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4622 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4623 (match_operand:FPR 2 "general_operand" "f,R")))]
4624 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4628 [(set_attr "op_type" "RR,RX")
4629 (set_attr "type" "fdiv<mode>")])
4633 ;;- And instructions.
4636 (define_expand "and<mode>3"
4637 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4638 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4639 (match_operand:INT 2 "general_operand" "")))
4640 (clobber (reg:CC CC_REGNUM))]
4642 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4645 ; anddi3 instruction pattern(s).
4648 (define_insn "*anddi3_cc"
4649 [(set (reg CC_REGNUM)
4650 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4651 (match_operand:DI 2 "general_operand" "d,m"))
4653 (set (match_operand:DI 0 "register_operand" "=d,d")
4654 (and:DI (match_dup 1) (match_dup 2)))]
4655 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4659 [(set_attr "op_type" "RRE,RXY")])
4661 (define_insn "*anddi3_cconly"
4662 [(set (reg CC_REGNUM)
4663 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4664 (match_operand:DI 2 "general_operand" "d,m"))
4666 (clobber (match_scratch:DI 0 "=d,d"))]
4667 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4668 /* Do not steal TM patterns. */
4669 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4673 [(set_attr "op_type" "RRE,RXY")])
4675 (define_insn "*anddi3"
4676 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4677 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4678 "%d,o,0,0,0,0,0,0,0,0")
4679 (match_operand:DI 2 "general_operand"
4680 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4681 (clobber (reg:CC CC_REGNUM))]
4682 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4694 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4697 [(set (match_operand:DI 0 "s_operand" "")
4698 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4699 (clobber (reg:CC CC_REGNUM))]
4702 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4703 (clobber (reg:CC CC_REGNUM))])]
4704 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4708 ; andsi3 instruction pattern(s).
4711 (define_insn "*andsi3_cc"
4712 [(set (reg CC_REGNUM)
4713 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4714 (match_operand:SI 2 "general_operand" "d,R,T"))
4716 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4717 (and:SI (match_dup 1) (match_dup 2)))]
4718 "s390_match_ccmode(insn, CCTmode)"
4723 [(set_attr "op_type" "RR,RX,RXY")])
4725 (define_insn "*andsi3_cconly"
4726 [(set (reg CC_REGNUM)
4727 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4728 (match_operand:SI 2 "general_operand" "d,R,T"))
4730 (clobber (match_scratch:SI 0 "=d,d,d"))]
4731 "s390_match_ccmode(insn, CCTmode)
4732 /* Do not steal TM patterns. */
4733 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4738 [(set_attr "op_type" "RR,RX,RXY")])
4740 (define_insn "*andsi3_zarch"
4741 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4742 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4743 "%d,o,0,0,0,0,0,0,0")
4744 (match_operand:SI 2 "general_operand"
4745 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4746 (clobber (reg:CC CC_REGNUM))]
4747 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4758 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4760 (define_insn "*andsi3_esa"
4761 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4762 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4763 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4764 (clobber (reg:CC CC_REGNUM))]
4765 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4771 [(set_attr "op_type" "RR,RX,SI,SS")])
4774 [(set (match_operand:SI 0 "s_operand" "")
4775 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4776 (clobber (reg:CC CC_REGNUM))]
4779 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4780 (clobber (reg:CC CC_REGNUM))])]
4781 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4784 ; andhi3 instruction pattern(s).
4787 (define_insn "*andhi3_zarch"
4788 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4789 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4790 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4791 (clobber (reg:CC CC_REGNUM))]
4792 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4798 [(set_attr "op_type" "RR,RI,SI,SS")])
4800 (define_insn "*andhi3_esa"
4801 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4802 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4803 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4804 (clobber (reg:CC CC_REGNUM))]
4805 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4810 [(set_attr "op_type" "RR,SI,SS")])
4813 [(set (match_operand:HI 0 "s_operand" "")
4814 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4815 (clobber (reg:CC CC_REGNUM))]
4818 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4819 (clobber (reg:CC CC_REGNUM))])]
4820 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4823 ; andqi3 instruction pattern(s).
4826 (define_insn "*andqi3_zarch"
4827 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4828 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4829 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4830 (clobber (reg:CC CC_REGNUM))]
4831 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4838 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4840 (define_insn "*andqi3_esa"
4841 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4842 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4843 (match_operand:QI 2 "general_operand" "d,n,Q")))
4844 (clobber (reg:CC CC_REGNUM))]
4845 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4850 [(set_attr "op_type" "RR,SI,SS")])
4853 ; Block and (NC) patterns.
4857 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4858 (and:BLK (match_dup 0)
4859 (match_operand:BLK 1 "memory_operand" "Q")))
4860 (use (match_operand 2 "const_int_operand" "n"))
4861 (clobber (reg:CC CC_REGNUM))]
4862 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4863 "nc\t%O0(%2,%R0),%S1"
4864 [(set_attr "op_type" "SS")])
4867 [(set (match_operand 0 "memory_operand" "")
4869 (match_operand 1 "memory_operand" "")))
4870 (clobber (reg:CC CC_REGNUM))]
4872 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4873 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4875 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4877 (clobber (reg:CC CC_REGNUM))])]
4879 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4880 operands[0] = adjust_address (operands[0], BLKmode, 0);
4881 operands[1] = adjust_address (operands[1], BLKmode, 0);
4886 [(set (match_operand:BLK 0 "memory_operand" "")
4887 (and:BLK (match_dup 0)
4888 (match_operand:BLK 1 "memory_operand" "")))
4889 (use (match_operand 2 "const_int_operand" ""))
4890 (clobber (reg:CC CC_REGNUM))])
4892 [(set (match_operand:BLK 3 "memory_operand" "")
4893 (and:BLK (match_dup 3)
4894 (match_operand:BLK 4 "memory_operand" "")))
4895 (use (match_operand 5 "const_int_operand" ""))
4896 (clobber (reg:CC CC_REGNUM))])]
4897 "s390_offset_p (operands[0], operands[3], operands[2])
4898 && s390_offset_p (operands[1], operands[4], operands[2])
4899 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4901 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4903 (clobber (reg:CC CC_REGNUM))])]
4904 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4905 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4906 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4910 ;;- Bit set (inclusive or) instructions.
4913 (define_expand "ior<mode>3"
4914 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4915 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4916 (match_operand:INT 2 "general_operand" "")))
4917 (clobber (reg:CC CC_REGNUM))]
4919 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4922 ; iordi3 instruction pattern(s).
4925 (define_insn "*iordi3_cc"
4926 [(set (reg CC_REGNUM)
4927 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4928 (match_operand:DI 2 "general_operand" "d,m"))
4930 (set (match_operand:DI 0 "register_operand" "=d,d")
4931 (ior:DI (match_dup 1) (match_dup 2)))]
4932 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4936 [(set_attr "op_type" "RRE,RXY")])
4938 (define_insn "*iordi3_cconly"
4939 [(set (reg CC_REGNUM)
4940 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4941 (match_operand:DI 2 "general_operand" "d,m"))
4943 (clobber (match_scratch:DI 0 "=d,d"))]
4944 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4948 [(set_attr "op_type" "RRE,RXY")])
4950 (define_insn "*iordi3"
4951 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4952 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4953 (match_operand:DI 2 "general_operand"
4954 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4955 (clobber (reg:CC CC_REGNUM))]
4956 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4966 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4969 [(set (match_operand:DI 0 "s_operand" "")
4970 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4971 (clobber (reg:CC CC_REGNUM))]
4974 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4975 (clobber (reg:CC CC_REGNUM))])]
4976 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4979 ; iorsi3 instruction pattern(s).
4982 (define_insn "*iorsi3_cc"
4983 [(set (reg CC_REGNUM)
4984 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4985 (match_operand:SI 2 "general_operand" "d,R,T"))
4987 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4988 (ior:SI (match_dup 1) (match_dup 2)))]
4989 "s390_match_ccmode(insn, CCTmode)"
4994 [(set_attr "op_type" "RR,RX,RXY")])
4996 (define_insn "*iorsi3_cconly"
4997 [(set (reg CC_REGNUM)
4998 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4999 (match_operand:SI 2 "general_operand" "d,R,T"))
5001 (clobber (match_scratch:SI 0 "=d,d,d"))]
5002 "s390_match_ccmode(insn, CCTmode)"
5007 [(set_attr "op_type" "RR,RX,RXY")])
5009 (define_insn "*iorsi3_zarch"
5010 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5011 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5012 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5013 (clobber (reg:CC CC_REGNUM))]
5014 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5023 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5025 (define_insn "*iorsi3_esa"
5026 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5027 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5028 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5029 (clobber (reg:CC CC_REGNUM))]
5030 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5036 [(set_attr "op_type" "RR,RX,SI,SS")])
5039 [(set (match_operand:SI 0 "s_operand" "")
5040 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5041 (clobber (reg:CC CC_REGNUM))]
5044 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5045 (clobber (reg:CC CC_REGNUM))])]
5046 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5049 ; iorhi3 instruction pattern(s).
5052 (define_insn "*iorhi3_zarch"
5053 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5054 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5055 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5056 (clobber (reg:CC CC_REGNUM))]
5057 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5063 [(set_attr "op_type" "RR,RI,SI,SS")])
5065 (define_insn "*iorhi3_esa"
5066 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5067 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5068 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5069 (clobber (reg:CC CC_REGNUM))]
5070 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5075 [(set_attr "op_type" "RR,SI,SS")])
5078 [(set (match_operand:HI 0 "s_operand" "")
5079 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5080 (clobber (reg:CC CC_REGNUM))]
5083 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5084 (clobber (reg:CC CC_REGNUM))])]
5085 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5088 ; iorqi3 instruction pattern(s).
5091 (define_insn "*iorqi3_zarch"
5092 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5093 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5094 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5095 (clobber (reg:CC CC_REGNUM))]
5096 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5103 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5105 (define_insn "*iorqi3_esa"
5106 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5107 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5108 (match_operand:QI 2 "general_operand" "d,n,Q")))
5109 (clobber (reg:CC CC_REGNUM))]
5110 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5115 [(set_attr "op_type" "RR,SI,SS")])
5118 ; Block inclusive or (OC) patterns.
5122 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5123 (ior:BLK (match_dup 0)
5124 (match_operand:BLK 1 "memory_operand" "Q")))
5125 (use (match_operand 2 "const_int_operand" "n"))
5126 (clobber (reg:CC CC_REGNUM))]
5127 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5128 "oc\t%O0(%2,%R0),%S1"
5129 [(set_attr "op_type" "SS")])
5132 [(set (match_operand 0 "memory_operand" "")
5134 (match_operand 1 "memory_operand" "")))
5135 (clobber (reg:CC CC_REGNUM))]
5137 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5138 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5140 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5142 (clobber (reg:CC CC_REGNUM))])]
5144 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5145 operands[0] = adjust_address (operands[0], BLKmode, 0);
5146 operands[1] = adjust_address (operands[1], BLKmode, 0);
5151 [(set (match_operand:BLK 0 "memory_operand" "")
5152 (ior:BLK (match_dup 0)
5153 (match_operand:BLK 1 "memory_operand" "")))
5154 (use (match_operand 2 "const_int_operand" ""))
5155 (clobber (reg:CC CC_REGNUM))])
5157 [(set (match_operand:BLK 3 "memory_operand" "")
5158 (ior:BLK (match_dup 3)
5159 (match_operand:BLK 4 "memory_operand" "")))
5160 (use (match_operand 5 "const_int_operand" ""))
5161 (clobber (reg:CC CC_REGNUM))])]
5162 "s390_offset_p (operands[0], operands[3], operands[2])
5163 && s390_offset_p (operands[1], operands[4], operands[2])
5164 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5166 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5168 (clobber (reg:CC CC_REGNUM))])]
5169 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5170 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5171 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5175 ;;- Xor instructions.
5178 (define_expand "xor<mode>3"
5179 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5180 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5181 (match_operand:INT 2 "general_operand" "")))
5182 (clobber (reg:CC CC_REGNUM))]
5184 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5187 ; xordi3 instruction pattern(s).
5190 (define_insn "*xordi3_cc"
5191 [(set (reg CC_REGNUM)
5192 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5193 (match_operand:DI 2 "general_operand" "d,m"))
5195 (set (match_operand:DI 0 "register_operand" "=d,d")
5196 (xor:DI (match_dup 1) (match_dup 2)))]
5197 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5201 [(set_attr "op_type" "RRE,RXY")])
5203 (define_insn "*xordi3_cconly"
5204 [(set (reg CC_REGNUM)
5205 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5206 (match_operand:DI 2 "general_operand" "d,m"))
5208 (clobber (match_scratch:DI 0 "=d,d"))]
5209 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5213 [(set_attr "op_type" "RRE,RXY")])
5215 (define_insn "*xordi3"
5216 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5217 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5218 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5219 (clobber (reg:CC CC_REGNUM))]
5220 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5226 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5229 [(set (match_operand:DI 0 "s_operand" "")
5230 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5231 (clobber (reg:CC CC_REGNUM))]
5234 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5235 (clobber (reg:CC CC_REGNUM))])]
5236 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5239 ; xorsi3 instruction pattern(s).
5242 (define_insn "*xorsi3_cc"
5243 [(set (reg CC_REGNUM)
5244 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5245 (match_operand:SI 2 "general_operand" "d,R,T"))
5247 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5248 (xor:SI (match_dup 1) (match_dup 2)))]
5249 "s390_match_ccmode(insn, CCTmode)"
5254 [(set_attr "op_type" "RR,RX,RXY")])
5256 (define_insn "*xorsi3_cconly"
5257 [(set (reg CC_REGNUM)
5258 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5259 (match_operand:SI 2 "general_operand" "d,R,T"))
5261 (clobber (match_scratch:SI 0 "=d,d,d"))]
5262 "s390_match_ccmode(insn, CCTmode)"
5267 [(set_attr "op_type" "RR,RX,RXY")])
5269 (define_insn "*xorsi3"
5270 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5271 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5272 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5273 (clobber (reg:CC CC_REGNUM))]
5274 "s390_logical_operator_ok_p (operands)"
5281 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5284 [(set (match_operand:SI 0 "s_operand" "")
5285 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5286 (clobber (reg:CC CC_REGNUM))]
5289 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5290 (clobber (reg:CC CC_REGNUM))])]
5291 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5294 ; xorhi3 instruction pattern(s).
5297 (define_insn "*xorhi3"
5298 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5299 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5300 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5301 (clobber (reg:CC CC_REGNUM))]
5302 "s390_logical_operator_ok_p (operands)"
5307 [(set_attr "op_type" "RR,SI,SS")])
5310 [(set (match_operand:HI 0 "s_operand" "")
5311 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5312 (clobber (reg:CC CC_REGNUM))]
5315 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5316 (clobber (reg:CC CC_REGNUM))])]
5317 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5320 ; xorqi3 instruction pattern(s).
5323 (define_insn "*xorqi3"
5324 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5325 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5326 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5327 (clobber (reg:CC CC_REGNUM))]
5328 "s390_logical_operator_ok_p (operands)"
5334 [(set_attr "op_type" "RR,SI,SIY,SS")])
5337 ; Block exclusive or (XC) patterns.
5341 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5342 (xor:BLK (match_dup 0)
5343 (match_operand:BLK 1 "memory_operand" "Q")))
5344 (use (match_operand 2 "const_int_operand" "n"))
5345 (clobber (reg:CC CC_REGNUM))]
5346 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5347 "xc\t%O0(%2,%R0),%S1"
5348 [(set_attr "op_type" "SS")])
5351 [(set (match_operand 0 "memory_operand" "")
5353 (match_operand 1 "memory_operand" "")))
5354 (clobber (reg:CC CC_REGNUM))]
5356 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5357 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5359 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5361 (clobber (reg:CC CC_REGNUM))])]
5363 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5364 operands[0] = adjust_address (operands[0], BLKmode, 0);
5365 operands[1] = adjust_address (operands[1], BLKmode, 0);
5370 [(set (match_operand:BLK 0 "memory_operand" "")
5371 (xor:BLK (match_dup 0)
5372 (match_operand:BLK 1 "memory_operand" "")))
5373 (use (match_operand 2 "const_int_operand" ""))
5374 (clobber (reg:CC CC_REGNUM))])
5376 [(set (match_operand:BLK 3 "memory_operand" "")
5377 (xor:BLK (match_dup 3)
5378 (match_operand:BLK 4 "memory_operand" "")))
5379 (use (match_operand 5 "const_int_operand" ""))
5380 (clobber (reg:CC CC_REGNUM))])]
5381 "s390_offset_p (operands[0], operands[3], operands[2])
5382 && s390_offset_p (operands[1], operands[4], operands[2])
5383 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5385 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5387 (clobber (reg:CC CC_REGNUM))])]
5388 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5389 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5390 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5393 ; Block xor (XC) patterns with src == dest.
5396 (define_insn "*xc_zero"
5397 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5399 (use (match_operand 1 "const_int_operand" "n"))
5400 (clobber (reg:CC CC_REGNUM))]
5401 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5402 "xc\t%O0(%1,%R0),%S0"
5403 [(set_attr "op_type" "SS")])
5407 [(set (match_operand:BLK 0 "memory_operand" "")
5409 (use (match_operand 1 "const_int_operand" ""))
5410 (clobber (reg:CC CC_REGNUM))])
5412 [(set (match_operand:BLK 2 "memory_operand" "")
5414 (use (match_operand 3 "const_int_operand" ""))
5415 (clobber (reg:CC CC_REGNUM))])]
5416 "s390_offset_p (operands[0], operands[2], operands[1])
5417 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5419 [(set (match_dup 4) (const_int 0))
5421 (clobber (reg:CC CC_REGNUM))])]
5422 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5423 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5427 ;;- Negate instructions.
5431 ; neg(di|si)2 instruction pattern(s).
5434 (define_expand "neg<mode>2"
5436 [(set (match_operand:DSI 0 "register_operand" "=d")
5437 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5438 (clobber (reg:CC CC_REGNUM))])]
5442 (define_insn "*negdi2_sign_cc"
5443 [(set (reg CC_REGNUM)
5444 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5445 (match_operand:SI 1 "register_operand" "d") 0)
5446 (const_int 32)) (const_int 32)))
5448 (set (match_operand:DI 0 "register_operand" "=d")
5449 (neg:DI (sign_extend:DI (match_dup 1))))]
5450 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5452 [(set_attr "op_type" "RRE")])
5454 (define_insn "*negdi2_sign"
5455 [(set (match_operand:DI 0 "register_operand" "=d")
5456 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5457 (clobber (reg:CC CC_REGNUM))]
5460 [(set_attr "op_type" "RRE")])
5462 (define_insn "*neg<mode>2_cc"
5463 [(set (reg CC_REGNUM)
5464 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5466 (set (match_operand:GPR 0 "register_operand" "=d")
5467 (neg:GPR (match_dup 1)))]
5468 "s390_match_ccmode (insn, CCAmode)"
5470 [(set_attr "op_type" "RR<E>")])
5472 (define_insn "*neg<mode>2_cconly"
5473 [(set (reg CC_REGNUM)
5474 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5476 (clobber (match_scratch:GPR 0 "=d"))]
5477 "s390_match_ccmode (insn, CCAmode)"
5479 [(set_attr "op_type" "RR<E>")])
5481 (define_insn "*neg<mode>2"
5482 [(set (match_operand:GPR 0 "register_operand" "=d")
5483 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5484 (clobber (reg:CC CC_REGNUM))]
5487 [(set_attr "op_type" "RR<E>")])
5489 (define_insn_and_split "*negdi2_31"
5490 [(set (match_operand:DI 0 "register_operand" "=d")
5491 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5492 (clobber (reg:CC CC_REGNUM))]
5495 "&& reload_completed"
5497 [(set (match_dup 2) (neg:SI (match_dup 3)))
5498 (clobber (reg:CC CC_REGNUM))])
5500 [(set (reg:CCAP CC_REGNUM)
5501 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5502 (set (match_dup 4) (neg:SI (match_dup 5)))])
5504 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5506 (label_ref (match_dup 6))))
5508 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5509 (clobber (reg:CC CC_REGNUM))])
5511 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5512 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5513 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5514 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5515 operands[6] = gen_label_rtx ();")
5518 ; neg(df|sf)2 instruction pattern(s).
5521 (define_expand "neg<mode>2"
5523 [(set (match_operand:FPR 0 "register_operand" "=f")
5524 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5525 (clobber (reg:CC CC_REGNUM))])]
5529 (define_insn "*neg<mode>2_cc"
5530 [(set (reg CC_REGNUM)
5531 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5532 (match_operand:FPR 2 "const0_operand" "")))
5533 (set (match_operand:FPR 0 "register_operand" "=f")
5534 (neg:FPR (match_dup 1)))]
5535 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5537 [(set_attr "op_type" "RRE")
5538 (set_attr "type" "fsimp<mode>")])
5540 (define_insn "*neg<mode>2_cconly"
5541 [(set (reg CC_REGNUM)
5542 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5543 (match_operand:FPR 2 "const0_operand" "")))
5544 (clobber (match_scratch:FPR 0 "=f"))]
5545 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5547 [(set_attr "op_type" "RRE")
5548 (set_attr "type" "fsimp<mode>")])
5550 (define_insn "*neg<mode>2"
5551 [(set (match_operand:FPR 0 "register_operand" "=f")
5552 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5553 (clobber (reg:CC CC_REGNUM))]
5554 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5556 [(set_attr "op_type" "RRE")
5557 (set_attr "type" "fsimp<mode>")])
5559 (define_insn "*neg<mode>2_ibm"
5560 [(set (match_operand:FPR 0 "register_operand" "=f")
5561 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5562 (clobber (reg:CC CC_REGNUM))]
5563 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5565 [(set_attr "op_type" "RR")
5566 (set_attr "type" "fsimp<mode>")])
5570 ;;- Absolute value instructions.
5574 ; abs(di|si)2 instruction pattern(s).
5577 (define_insn "*absdi2_sign_cc"
5578 [(set (reg CC_REGNUM)
5579 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5580 (match_operand:SI 1 "register_operand" "d") 0)
5581 (const_int 32)) (const_int 32)))
5583 (set (match_operand:DI 0 "register_operand" "=d")
5584 (abs:DI (sign_extend:DI (match_dup 1))))]
5585 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5587 [(set_attr "op_type" "RRE")])
5589 (define_insn "*absdi2_sign"
5590 [(set (match_operand:DI 0 "register_operand" "=d")
5591 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5592 (clobber (reg:CC CC_REGNUM))]
5595 [(set_attr "op_type" "RRE")])
5597 (define_insn "*abs<mode>2_cc"
5598 [(set (reg CC_REGNUM)
5599 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5601 (set (match_operand:GPR 0 "register_operand" "=d")
5602 (abs:GPR (match_dup 1)))]
5603 "s390_match_ccmode (insn, CCAmode)"
5605 [(set_attr "op_type" "RR<E>")])
5607 (define_insn "*abs<mode>2_cconly"
5608 [(set (reg CC_REGNUM)
5609 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5611 (clobber (match_scratch:GPR 0 "=d"))]
5612 "s390_match_ccmode (insn, CCAmode)"
5614 [(set_attr "op_type" "RR<E>")])
5616 (define_insn "abs<mode>2"
5617 [(set (match_operand:GPR 0 "register_operand" "=d")
5618 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5619 (clobber (reg:CC CC_REGNUM))]
5622 [(set_attr "op_type" "RR<E>")])
5625 ; abs(df|sf)2 instruction pattern(s).
5628 (define_expand "abs<mode>2"
5630 [(set (match_operand:FPR 0 "register_operand" "=f")
5631 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5632 (clobber (reg:CC CC_REGNUM))])]
5636 (define_insn "*abs<mode>2_cc"
5637 [(set (reg CC_REGNUM)
5638 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5639 (match_operand:FPR 2 "const0_operand" "")))
5640 (set (match_operand:FPR 0 "register_operand" "=f")
5641 (abs:FPR (match_dup 1)))]
5642 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5644 [(set_attr "op_type" "RRE")
5645 (set_attr "type" "fsimp<mode>")])
5647 (define_insn "*abs<mode>2_cconly"
5648 [(set (reg CC_REGNUM)
5649 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5650 (match_operand:FPR 2 "const0_operand" "")))
5651 (clobber (match_scratch:FPR 0 "=f"))]
5652 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5654 [(set_attr "op_type" "RRE")
5655 (set_attr "type" "fsimp<mode>")])
5657 (define_insn "*abs<mode>2"
5658 [(set (match_operand:FPR 0 "register_operand" "=f")
5659 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5660 (clobber (reg:CC CC_REGNUM))]
5661 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5663 [(set_attr "op_type" "RRE")
5664 (set_attr "type" "fsimp<mode>")])
5666 (define_insn "*abs<mode>2_ibm"
5667 [(set (match_operand:FPR 0 "register_operand" "=f")
5668 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5669 (clobber (reg:CC CC_REGNUM))]
5670 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5672 [(set_attr "op_type" "RR")
5673 (set_attr "type" "fsimp<mode>")])
5676 ;;- Negated absolute value instructions
5683 (define_insn "*negabsdi2_sign_cc"
5684 [(set (reg CC_REGNUM)
5685 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5686 (match_operand:SI 1 "register_operand" "d") 0)
5687 (const_int 32)) (const_int 32))))
5689 (set (match_operand:DI 0 "register_operand" "=d")
5690 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5691 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5693 [(set_attr "op_type" "RRE")])
5695 (define_insn "*negabsdi2_sign"
5696 [(set (match_operand:DI 0 "register_operand" "=d")
5697 (neg:DI (abs:DI (sign_extend:DI
5698 (match_operand:SI 1 "register_operand" "d")))))
5699 (clobber (reg:CC CC_REGNUM))]
5702 [(set_attr "op_type" "RRE")])
5704 (define_insn "*negabs<mode>2_cc"
5705 [(set (reg CC_REGNUM)
5706 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5708 (set (match_operand:GPR 0 "register_operand" "=d")
5709 (neg:GPR (abs:GPR (match_dup 1))))]
5710 "s390_match_ccmode (insn, CCAmode)"
5712 [(set_attr "op_type" "RR<E>")])
5714 (define_insn "*negabs<mode>2_cconly"
5715 [(set (reg CC_REGNUM)
5716 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5718 (clobber (match_scratch:GPR 0 "=d"))]
5719 "s390_match_ccmode (insn, CCAmode)"
5721 [(set_attr "op_type" "RR<E>")])
5723 (define_insn "*negabs<mode>2"
5724 [(set (match_operand:GPR 0 "register_operand" "=d")
5725 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5726 (clobber (reg:CC CC_REGNUM))]
5729 [(set_attr "op_type" "RR<E>")])
5735 (define_insn "*negabs<mode>2_cc"
5736 [(set (reg CC_REGNUM)
5737 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5738 (match_operand:FPR 2 "const0_operand" "")))
5739 (set (match_operand:FPR 0 "register_operand" "=f")
5740 (neg:FPR (abs:FPR (match_dup 1))))]
5741 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5743 [(set_attr "op_type" "RRE")
5744 (set_attr "type" "fsimp<mode>")])
5746 (define_insn "*negabs<mode>2_cconly"
5747 [(set (reg CC_REGNUM)
5748 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5749 (match_operand:FPR 2 "const0_operand" "")))
5750 (clobber (match_scratch:FPR 0 "=f"))]
5751 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5753 [(set_attr "op_type" "RRE")
5754 (set_attr "type" "fsimp<mode>")])
5756 (define_insn "*negabs<mode>2"
5757 [(set (match_operand:FPR 0 "register_operand" "=f")
5758 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5759 (clobber (reg:CC CC_REGNUM))]
5760 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5762 [(set_attr "op_type" "RRE")
5763 (set_attr "type" "fsimp<mode>")])
5766 ;;- Square root instructions.
5770 ; sqrt(df|sf)2 instruction pattern(s).
5773 (define_insn "sqrt<mode>2"
5774 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5775 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5776 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5780 [(set_attr "op_type" "RRE,RXE")
5781 (set_attr "type" "fsqrt<mode>")])
5785 ;;- One complement instructions.
5789 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5792 (define_expand "one_cmpl<mode>2"
5794 [(set (match_operand:INT 0 "register_operand" "")
5795 (xor:INT (match_operand:INT 1 "register_operand" "")
5797 (clobber (reg:CC CC_REGNUM))])]
5803 ;;- Rotate instructions.
5807 ; rotl(di|si)3 instruction pattern(s).
5810 (define_insn "rotl<mode>3"
5811 [(set (match_operand:GPR 0 "register_operand" "=d")
5812 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5813 (match_operand:SI 2 "shift_count_operand" "Y")))]
5816 [(set_attr "op_type" "RSE")
5817 (set_attr "atype" "reg")])
5821 ;;- Shift instructions.
5825 ; (ashl|lshr)di3 instruction pattern(s).
5828 (define_expand "<shift>di3"
5829 [(set (match_operand:DI 0 "register_operand" "")
5830 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5831 (match_operand:SI 2 "shift_count_operand" "")))]
5835 (define_insn "*<shift>di3_31"
5836 [(set (match_operand:DI 0 "register_operand" "=d")
5837 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5838 (match_operand:SI 2 "shift_count_operand" "Y")))]
5841 [(set_attr "op_type" "RS")
5842 (set_attr "atype" "reg")])
5844 (define_insn "*<shift>di3_64"
5845 [(set (match_operand:DI 0 "register_operand" "=d")
5846 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5847 (match_operand:SI 2 "shift_count_operand" "Y")))]
5849 "s<lr>lg\t%0,%1,%Y2"
5850 [(set_attr "op_type" "RSE")
5851 (set_attr "atype" "reg")])
5854 ; ashrdi3 instruction pattern(s).
5857 (define_expand "ashrdi3"
5859 [(set (match_operand:DI 0 "register_operand" "")
5860 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5861 (match_operand:SI 2 "shift_count_operand" "")))
5862 (clobber (reg:CC CC_REGNUM))])]
5866 (define_insn "*ashrdi3_cc_31"
5867 [(set (reg CC_REGNUM)
5868 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5869 (match_operand:SI 2 "shift_count_operand" "Y"))
5871 (set (match_operand:DI 0 "register_operand" "=d")
5872 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5873 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5875 [(set_attr "op_type" "RS")
5876 (set_attr "atype" "reg")])
5878 (define_insn "*ashrdi3_cconly_31"
5879 [(set (reg CC_REGNUM)
5880 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5881 (match_operand:SI 2 "shift_count_operand" "Y"))
5883 (clobber (match_scratch:DI 0 "=d"))]
5884 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5886 [(set_attr "op_type" "RS")
5887 (set_attr "atype" "reg")])
5889 (define_insn "*ashrdi3_31"
5890 [(set (match_operand:DI 0 "register_operand" "=d")
5891 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5892 (match_operand:SI 2 "shift_count_operand" "Y")))
5893 (clobber (reg:CC CC_REGNUM))]
5896 [(set_attr "op_type" "RS")
5897 (set_attr "atype" "reg")])
5899 (define_insn "*ashrdi3_cc_64"
5900 [(set (reg CC_REGNUM)
5901 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5902 (match_operand:SI 2 "shift_count_operand" "Y"))
5904 (set (match_operand:DI 0 "register_operand" "=d")
5905 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5906 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5908 [(set_attr "op_type" "RSE")
5909 (set_attr "atype" "reg")])
5911 (define_insn "*ashrdi3_cconly_64"
5912 [(set (reg CC_REGNUM)
5913 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5914 (match_operand:SI 2 "shift_count_operand" "Y"))
5916 (clobber (match_scratch:DI 0 "=d"))]
5917 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5919 [(set_attr "op_type" "RSE")
5920 (set_attr "atype" "reg")])
5922 (define_insn "*ashrdi3_64"
5923 [(set (match_operand:DI 0 "register_operand" "=d")
5924 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5925 (match_operand:SI 2 "shift_count_operand" "Y")))
5926 (clobber (reg:CC CC_REGNUM))]
5929 [(set_attr "op_type" "RSE")
5930 (set_attr "atype" "reg")])
5934 ; (ashl|lshr)si3 instruction pattern(s).
5937 (define_insn "<shift>si3"
5938 [(set (match_operand:SI 0 "register_operand" "=d")
5939 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5940 (match_operand:SI 2 "shift_count_operand" "Y")))]
5943 [(set_attr "op_type" "RS")
5944 (set_attr "atype" "reg")])
5947 ; ashrsi3 instruction pattern(s).
5950 (define_insn "*ashrsi3_cc"
5951 [(set (reg CC_REGNUM)
5952 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5953 (match_operand:SI 2 "shift_count_operand" "Y"))
5955 (set (match_operand:SI 0 "register_operand" "=d")
5956 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5957 "s390_match_ccmode(insn, CCSmode)"
5959 [(set_attr "op_type" "RS")
5960 (set_attr "atype" "reg")])
5963 (define_insn "*ashrsi3_cconly"
5964 [(set (reg CC_REGNUM)
5965 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5966 (match_operand:SI 2 "shift_count_operand" "Y"))
5968 (clobber (match_scratch:SI 0 "=d"))]
5969 "s390_match_ccmode(insn, CCSmode)"
5971 [(set_attr "op_type" "RS")
5972 (set_attr "atype" "reg")])
5974 (define_insn "ashrsi3"
5975 [(set (match_operand:SI 0 "register_operand" "=d")
5976 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5977 (match_operand:SI 2 "shift_count_operand" "Y")))
5978 (clobber (reg:CC CC_REGNUM))]
5981 [(set_attr "op_type" "RS")
5982 (set_attr "atype" "reg")])
5986 ;; Branch instruction patterns.
5989 (define_expand "b<code>"
5991 (if_then_else (COMPARE (match_operand 0 "" "")
5996 "s390_emit_jump (operands[0],
5997 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6001 ;;- Conditional jump instructions.
6004 (define_insn "*cjump_64"
6007 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6008 (label_ref (match_operand 0 "" ""))
6012 if (get_attr_length (insn) == 4)
6015 return "jg%C1\t%l0";
6017 [(set_attr "op_type" "RI")
6018 (set_attr "type" "branch")
6019 (set (attr "length")
6020 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6021 (const_int 4) (const_int 6)))])
6023 (define_insn "*cjump_31"
6026 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6027 (label_ref (match_operand 0 "" ""))
6031 gcc_assert (get_attr_length (insn) == 4);
6034 [(set_attr "op_type" "RI")
6035 (set_attr "type" "branch")
6036 (set (attr "length")
6037 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6038 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6039 (const_int 4) (const_int 6))
6040 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6041 (const_int 4) (const_int 8))))])
6043 (define_insn "*cjump_long"
6046 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6047 (match_operand 0 "address_operand" "U")
6051 if (get_attr_op_type (insn) == OP_TYPE_RR)
6056 [(set (attr "op_type")
6057 (if_then_else (match_operand 0 "register_operand" "")
6058 (const_string "RR") (const_string "RX")))
6059 (set_attr "type" "branch")
6060 (set_attr "atype" "agen")])
6064 ;;- Negated conditional jump instructions.
6067 (define_insn "*icjump_64"
6070 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6072 (label_ref (match_operand 0 "" ""))))]
6075 if (get_attr_length (insn) == 4)
6078 return "jg%D1\t%l0";
6080 [(set_attr "op_type" "RI")
6081 (set_attr "type" "branch")
6082 (set (attr "length")
6083 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6084 (const_int 4) (const_int 6)))])
6086 (define_insn "*icjump_31"
6089 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6091 (label_ref (match_operand 0 "" ""))))]
6094 gcc_assert (get_attr_length (insn) == 4);
6097 [(set_attr "op_type" "RI")
6098 (set_attr "type" "branch")
6099 (set (attr "length")
6100 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6101 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6102 (const_int 4) (const_int 6))
6103 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6104 (const_int 4) (const_int 8))))])
6106 (define_insn "*icjump_long"
6109 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6111 (match_operand 0 "address_operand" "U")))]
6114 if (get_attr_op_type (insn) == OP_TYPE_RR)
6119 [(set (attr "op_type")
6120 (if_then_else (match_operand 0 "register_operand" "")
6121 (const_string "RR") (const_string "RX")))
6122 (set_attr "type" "branch")
6123 (set_attr "atype" "agen")])
6126 ;;- Trap instructions.
6130 [(trap_if (const_int 1) (const_int 0))]
6133 [(set_attr "op_type" "RI")
6134 (set_attr "type" "branch")])
6136 (define_expand "conditional_trap"
6137 [(trap_if (match_operand 0 "comparison_operator" "")
6138 (match_operand 1 "general_operand" ""))]
6141 if (operands[1] != const0_rtx) FAIL;
6142 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6143 s390_compare_op0, s390_compare_op1);
6146 (define_insn "*trap"
6147 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6151 [(set_attr "op_type" "RI")
6152 (set_attr "type" "branch")])
6155 ;;- Loop instructions.
6157 ;; This is all complicated by the fact that since this is a jump insn
6158 ;; we must handle our own output reloads.
6160 (define_expand "doloop_end"
6161 [(use (match_operand 0 "" "")) ; loop pseudo
6162 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6163 (use (match_operand 2 "" "")) ; max iterations
6164 (use (match_operand 3 "" "")) ; loop level
6165 (use (match_operand 4 "" ""))] ; label
6168 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6169 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6170 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6171 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6172 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6173 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6180 (define_insn_and_split "doloop_si64"
6183 (ne (match_operand:SI 1 "register_operand" "d,d")
6185 (label_ref (match_operand 0 "" ""))
6187 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6188 (plus:SI (match_dup 1) (const_int -1)))
6189 (clobber (match_scratch:SI 3 "=X,&1"))
6190 (clobber (reg:CC CC_REGNUM))]
6193 if (which_alternative != 0)
6195 else if (get_attr_length (insn) == 4)
6196 return "brct\t%1,%l0";
6198 return "ahi\t%1,-1\;jgne\t%l0";
6200 "&& reload_completed
6201 && (! REG_P (operands[2])
6202 || ! rtx_equal_p (operands[1], operands[2]))"
6203 [(parallel [(set (reg:CCAN CC_REGNUM)
6204 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6206 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6207 (set (match_dup 2) (match_dup 3))
6208 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6209 (label_ref (match_dup 0))
6212 [(set_attr "op_type" "RI")
6213 (set_attr "type" "branch")
6214 (set (attr "length")
6215 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6216 (const_int 4) (const_int 10)))])
6218 (define_insn_and_split "doloop_si31"
6221 (ne (match_operand:SI 1 "register_operand" "d,d")
6223 (label_ref (match_operand 0 "" ""))
6225 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6226 (plus:SI (match_dup 1) (const_int -1)))
6227 (clobber (match_scratch:SI 3 "=X,&1"))
6228 (clobber (reg:CC CC_REGNUM))]
6231 if (which_alternative != 0)
6233 else if (get_attr_length (insn) == 4)
6234 return "brct\t%1,%l0";
6238 "&& reload_completed
6239 && (! REG_P (operands[2])
6240 || ! rtx_equal_p (operands[1], operands[2]))"
6241 [(parallel [(set (reg:CCAN CC_REGNUM)
6242 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6244 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6245 (set (match_dup 2) (match_dup 3))
6246 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6247 (label_ref (match_dup 0))
6250 [(set_attr "op_type" "RI")
6251 (set_attr "type" "branch")
6252 (set (attr "length")
6253 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6254 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6255 (const_int 4) (const_int 6))
6256 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6257 (const_int 4) (const_int 8))))])
6259 (define_insn "*doloop_si_long"
6262 (ne (match_operand:SI 1 "register_operand" "d,d")
6264 (match_operand 0 "address_operand" "U,U")
6266 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6267 (plus:SI (match_dup 1) (const_int -1)))
6268 (clobber (match_scratch:SI 3 "=X,&1"))
6269 (clobber (reg:CC CC_REGNUM))]
6272 if (get_attr_op_type (insn) == OP_TYPE_RR)
6273 return "bctr\t%1,%0";
6275 return "bct\t%1,%a0";
6277 [(set (attr "op_type")
6278 (if_then_else (match_operand 0 "register_operand" "")
6279 (const_string "RR") (const_string "RX")))
6280 (set_attr "type" "branch")
6281 (set_attr "atype" "agen")])
6283 (define_insn_and_split "doloop_di"
6286 (ne (match_operand:DI 1 "register_operand" "d,d")
6288 (label_ref (match_operand 0 "" ""))
6290 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6291 (plus:DI (match_dup 1) (const_int -1)))
6292 (clobber (match_scratch:DI 3 "=X,&1"))
6293 (clobber (reg:CC CC_REGNUM))]
6296 if (which_alternative != 0)
6298 else if (get_attr_length (insn) == 4)
6299 return "brctg\t%1,%l0";
6301 return "aghi\t%1,-1\;jgne\t%l0";
6303 "&& reload_completed
6304 && (! REG_P (operands[2])
6305 || ! rtx_equal_p (operands[1], operands[2]))"
6306 [(parallel [(set (reg:CCAN CC_REGNUM)
6307 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6309 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6310 (set (match_dup 2) (match_dup 3))
6311 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6312 (label_ref (match_dup 0))
6315 [(set_attr "op_type" "RI")
6316 (set_attr "type" "branch")
6317 (set (attr "length")
6318 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6319 (const_int 4) (const_int 10)))])
6322 ;;- Unconditional jump instructions.
6326 ; jump instruction pattern(s).
6329 (define_expand "jump"
6330 [(match_operand 0 "" "")]
6332 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6334 (define_insn "*jump64"
6335 [(set (pc) (label_ref (match_operand 0 "" "")))]
6338 if (get_attr_length (insn) == 4)
6343 [(set_attr "op_type" "RI")
6344 (set_attr "type" "branch")
6345 (set (attr "length")
6346 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6347 (const_int 4) (const_int 6)))])
6349 (define_insn "*jump31"
6350 [(set (pc) (label_ref (match_operand 0 "" "")))]
6353 gcc_assert (get_attr_length (insn) == 4);
6356 [(set_attr "op_type" "RI")
6357 (set_attr "type" "branch")
6358 (set (attr "length")
6359 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6360 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6361 (const_int 4) (const_int 6))
6362 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6363 (const_int 4) (const_int 8))))])
6366 ; indirect-jump instruction pattern(s).
6369 (define_insn "indirect_jump"
6370 [(set (pc) (match_operand 0 "address_operand" "U"))]
6373 if (get_attr_op_type (insn) == OP_TYPE_RR)
6378 [(set (attr "op_type")
6379 (if_then_else (match_operand 0 "register_operand" "")
6380 (const_string "RR") (const_string "RX")))
6381 (set_attr "type" "branch")
6382 (set_attr "atype" "agen")])
6385 ; casesi instruction pattern(s).
6388 (define_insn "casesi_jump"
6389 [(set (pc) (match_operand 0 "address_operand" "U"))
6390 (use (label_ref (match_operand 1 "" "")))]
6393 if (get_attr_op_type (insn) == OP_TYPE_RR)
6398 [(set (attr "op_type")
6399 (if_then_else (match_operand 0 "register_operand" "")
6400 (const_string "RR") (const_string "RX")))
6401 (set_attr "type" "branch")
6402 (set_attr "atype" "agen")])
6404 (define_expand "casesi"
6405 [(match_operand:SI 0 "general_operand" "")
6406 (match_operand:SI 1 "general_operand" "")
6407 (match_operand:SI 2 "general_operand" "")
6408 (label_ref (match_operand 3 "" ""))
6409 (label_ref (match_operand 4 "" ""))]
6412 rtx index = gen_reg_rtx (SImode);
6413 rtx base = gen_reg_rtx (Pmode);
6414 rtx target = gen_reg_rtx (Pmode);
6416 emit_move_insn (index, operands[0]);
6417 emit_insn (gen_subsi3 (index, index, operands[1]));
6418 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6421 if (Pmode != SImode)
6422 index = convert_to_mode (Pmode, index, 1);
6423 if (GET_CODE (index) != REG)
6424 index = copy_to_mode_reg (Pmode, index);
6427 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6429 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6431 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6433 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6434 emit_move_insn (target, index);
6437 target = gen_rtx_PLUS (Pmode, base, target);
6438 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6445 ;;- Jump to subroutine.
6450 ; untyped call instruction pattern(s).
6453 ;; Call subroutine returning any type.
6454 (define_expand "untyped_call"
6455 [(parallel [(call (match_operand 0 "" "")
6457 (match_operand 1 "" "")
6458 (match_operand 2 "" "")])]
6463 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6465 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6467 rtx set = XVECEXP (operands[2], 0, i);
6468 emit_move_insn (SET_DEST (set), SET_SRC (set));
6471 /* The optimizer does not know that the call sets the function value
6472 registers we stored in the result block. We avoid problems by
6473 claiming that all hard registers are used and clobbered at this
6475 emit_insn (gen_blockage ());
6480 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6481 ;; all of memory. This blocks insns from being moved across this point.
6483 (define_insn "blockage"
6484 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6487 [(set_attr "type" "none")
6488 (set_attr "length" "0")])
6494 (define_expand "sibcall"
6495 [(call (match_operand 0 "" "")
6496 (match_operand 1 "" ""))]
6499 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6503 (define_insn "*sibcall_br"
6504 [(call (mem:QI (reg SIBCALL_REGNUM))
6505 (match_operand 0 "const_int_operand" "n"))]
6506 "SIBLING_CALL_P (insn)
6507 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6509 [(set_attr "op_type" "RR")
6510 (set_attr "type" "branch")
6511 (set_attr "atype" "agen")])
6513 (define_insn "*sibcall_brc"
6514 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6515 (match_operand 1 "const_int_operand" "n"))]
6516 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6518 [(set_attr "op_type" "RI")
6519 (set_attr "type" "branch")])
6521 (define_insn "*sibcall_brcl"
6522 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6523 (match_operand 1 "const_int_operand" "n"))]
6524 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6526 [(set_attr "op_type" "RIL")
6527 (set_attr "type" "branch")])
6530 ; sibcall_value patterns
6533 (define_expand "sibcall_value"
6534 [(set (match_operand 0 "" "")
6535 (call (match_operand 1 "" "")
6536 (match_operand 2 "" "")))]
6539 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6543 (define_insn "*sibcall_value_br"
6544 [(set (match_operand 0 "" "")
6545 (call (mem:QI (reg SIBCALL_REGNUM))
6546 (match_operand 1 "const_int_operand" "n")))]
6547 "SIBLING_CALL_P (insn)
6548 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6550 [(set_attr "op_type" "RR")
6551 (set_attr "type" "branch")
6552 (set_attr "atype" "agen")])
6554 (define_insn "*sibcall_value_brc"
6555 [(set (match_operand 0 "" "")
6556 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6557 (match_operand 2 "const_int_operand" "n")))]
6558 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6560 [(set_attr "op_type" "RI")
6561 (set_attr "type" "branch")])
6563 (define_insn "*sibcall_value_brcl"
6564 [(set (match_operand 0 "" "")
6565 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6566 (match_operand 2 "const_int_operand" "n")))]
6567 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6569 [(set_attr "op_type" "RIL")
6570 (set_attr "type" "branch")])
6574 ; call instruction pattern(s).
6577 (define_expand "call"
6578 [(call (match_operand 0 "" "")
6579 (match_operand 1 "" ""))
6580 (use (match_operand 2 "" ""))]
6583 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6584 gen_rtx_REG (Pmode, RETURN_REGNUM));
6588 (define_insn "*bras"
6589 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6590 (match_operand 1 "const_int_operand" "n"))
6591 (clobber (match_operand 2 "register_operand" "=r"))]
6592 "!SIBLING_CALL_P (insn)
6593 && TARGET_SMALL_EXEC
6594 && GET_MODE (operands[2]) == Pmode"
6596 [(set_attr "op_type" "RI")
6597 (set_attr "type" "jsr")])
6599 (define_insn "*brasl"
6600 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6601 (match_operand 1 "const_int_operand" "n"))
6602 (clobber (match_operand 2 "register_operand" "=r"))]
6603 "!SIBLING_CALL_P (insn)
6605 && GET_MODE (operands[2]) == Pmode"
6607 [(set_attr "op_type" "RIL")
6608 (set_attr "type" "jsr")])
6610 (define_insn "*basr"
6611 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6612 (match_operand 1 "const_int_operand" "n"))
6613 (clobber (match_operand 2 "register_operand" "=r"))]
6614 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6616 if (get_attr_op_type (insn) == OP_TYPE_RR)
6617 return "basr\t%2,%0";
6619 return "bas\t%2,%a0";
6621 [(set (attr "op_type")
6622 (if_then_else (match_operand 0 "register_operand" "")
6623 (const_string "RR") (const_string "RX")))
6624 (set_attr "type" "jsr")
6625 (set_attr "atype" "agen")])
6628 ; call_value instruction pattern(s).
6631 (define_expand "call_value"
6632 [(set (match_operand 0 "" "")
6633 (call (match_operand 1 "" "")
6634 (match_operand 2 "" "")))
6635 (use (match_operand 3 "" ""))]
6638 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6639 gen_rtx_REG (Pmode, RETURN_REGNUM));
6643 (define_insn "*bras_r"
6644 [(set (match_operand 0 "" "")
6645 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6646 (match_operand:SI 2 "const_int_operand" "n")))
6647 (clobber (match_operand 3 "register_operand" "=r"))]
6648 "!SIBLING_CALL_P (insn)
6649 && TARGET_SMALL_EXEC
6650 && GET_MODE (operands[3]) == Pmode"
6652 [(set_attr "op_type" "RI")
6653 (set_attr "type" "jsr")])
6655 (define_insn "*brasl_r"
6656 [(set (match_operand 0 "" "")
6657 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6658 (match_operand 2 "const_int_operand" "n")))
6659 (clobber (match_operand 3 "register_operand" "=r"))]
6660 "!SIBLING_CALL_P (insn)
6662 && GET_MODE (operands[3]) == Pmode"
6664 [(set_attr "op_type" "RIL")
6665 (set_attr "type" "jsr")])
6667 (define_insn "*basr_r"
6668 [(set (match_operand 0 "" "")
6669 (call (mem:QI (match_operand 1 "address_operand" "U"))
6670 (match_operand 2 "const_int_operand" "n")))
6671 (clobber (match_operand 3 "register_operand" "=r"))]
6672 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6674 if (get_attr_op_type (insn) == OP_TYPE_RR)
6675 return "basr\t%3,%1";
6677 return "bas\t%3,%a1";
6679 [(set (attr "op_type")
6680 (if_then_else (match_operand 1 "register_operand" "")
6681 (const_string "RR") (const_string "RX")))
6682 (set_attr "type" "jsr")
6683 (set_attr "atype" "agen")])
6686 ;;- Thread-local storage support.
6689 (define_expand "get_tp_64"
6690 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6694 (define_expand "get_tp_31"
6695 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6699 (define_expand "set_tp_64"
6700 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6701 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6705 (define_expand "set_tp_31"
6706 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6707 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6711 (define_insn "*set_tp"
6712 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6715 [(set_attr "type" "none")
6716 (set_attr "length" "0")])
6718 (define_insn "*tls_load_64"
6719 [(set (match_operand:DI 0 "register_operand" "=d")
6720 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6721 (match_operand:DI 2 "" "")]
6725 [(set_attr "op_type" "RXE")])
6727 (define_insn "*tls_load_31"
6728 [(set (match_operand:SI 0 "register_operand" "=d,d")
6729 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6730 (match_operand:SI 2 "" "")]
6736 [(set_attr "op_type" "RX,RXY")])
6738 (define_insn "*bras_tls"
6739 [(set (match_operand 0 "" "")
6740 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6741 (match_operand 2 "const_int_operand" "n")))
6742 (clobber (match_operand 3 "register_operand" "=r"))
6743 (use (match_operand 4 "" ""))]
6744 "!SIBLING_CALL_P (insn)
6745 && TARGET_SMALL_EXEC
6746 && GET_MODE (operands[3]) == Pmode"
6748 [(set_attr "op_type" "RI")
6749 (set_attr "type" "jsr")])
6751 (define_insn "*brasl_tls"
6752 [(set (match_operand 0 "" "")
6753 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6754 (match_operand 2 "const_int_operand" "n")))
6755 (clobber (match_operand 3 "register_operand" "=r"))
6756 (use (match_operand 4 "" ""))]
6757 "!SIBLING_CALL_P (insn)
6759 && GET_MODE (operands[3]) == Pmode"
6761 [(set_attr "op_type" "RIL")
6762 (set_attr "type" "jsr")])
6764 (define_insn "*basr_tls"
6765 [(set (match_operand 0 "" "")
6766 (call (mem:QI (match_operand 1 "address_operand" "U"))
6767 (match_operand 2 "const_int_operand" "n")))
6768 (clobber (match_operand 3 "register_operand" "=r"))
6769 (use (match_operand 4 "" ""))]
6770 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6772 if (get_attr_op_type (insn) == OP_TYPE_RR)
6773 return "basr\t%3,%1%J4";
6775 return "bas\t%3,%a1%J4";
6777 [(set (attr "op_type")
6778 (if_then_else (match_operand 1 "register_operand" "")
6779 (const_string "RR") (const_string "RX")))
6780 (set_attr "type" "jsr")
6781 (set_attr "atype" "agen")])
6784 ;;- Atomic operations
6788 ; memory barrier pattern.
6791 (define_expand "memory_barrier"
6792 [(set (mem:BLK (match_dup 0))
6793 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
6796 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
6797 MEM_VOLATILE_P (operands[0]) = 1;
6800 (define_insn "*memory_barrier"
6801 [(set (match_operand:BLK 0 "" "")
6802 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
6805 [(set_attr "op_type" "RR")])
6808 ; compare and swap patterns.
6811 (define_insn "sync_compare_and_swap<mode>"
6812 [(set (match_operand:GPR 0 "register_operand" "=r")
6813 (match_operand:GPR 1 "memory_operand" "+Q"))
6815 (unspec_volatile:GPR
6817 (match_operand:GPR 2 "register_operand" "0")
6818 (match_operand:GPR 3 "register_operand" "r")]
6820 (clobber (reg:CC CC_REGNUM))]
6823 [(set_attr "op_type" "RS<E>")
6824 (set_attr "type" "sem")])
6826 (define_expand "sync_compare_and_swap_cc<mode>"
6828 [(set (match_operand:GPR 0 "register_operand" "")
6829 (match_operand:GPR 1 "memory_operand" ""))
6831 (unspec_volatile:GPR
6833 (match_operand:GPR 2 "register_operand" "")
6834 (match_operand:GPR 3 "register_operand" "")]
6837 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
6840 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
6841 s390_compare_op0 = operands[1];
6842 s390_compare_op1 = operands[2];
6843 s390_compare_emitted = operands[4];
6846 (define_insn "*sync_compare_and_swap_cc<mode>"
6847 [(set (match_operand:GPR 0 "register_operand" "=r")
6848 (match_operand:GPR 1 "memory_operand" "+Q"))
6850 (unspec_volatile:GPR
6852 (match_operand:GPR 2 "register_operand" "0")
6853 (match_operand:GPR 3 "register_operand" "r")]
6855 (set (reg:CCZ1 CC_REGNUM)
6856 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
6859 [(set_attr "op_type" "RS<E>")
6860 (set_attr "type" "sem")])
6864 ;;- Miscellaneous instructions.
6868 ; allocate stack instruction pattern(s).
6871 (define_expand "allocate_stack"
6872 [(match_operand 0 "general_operand" "")
6873 (match_operand 1 "general_operand" "")]
6876 rtx temp = gen_reg_rtx (Pmode);
6878 emit_move_insn (temp, s390_back_chain_rtx ());
6879 anti_adjust_stack (operands[1]);
6880 emit_move_insn (s390_back_chain_rtx (), temp);
6882 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6888 ; setjmp instruction pattern.
6891 (define_expand "builtin_setjmp_receiver"
6892 [(match_operand 0 "" "")]
6895 emit_insn (s390_load_got ());
6896 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6900 ;; These patterns say how to save and restore the stack pointer. We need not
6901 ;; save the stack pointer at function level since we are careful to
6902 ;; preserve the backchain. At block level, we have to restore the backchain
6903 ;; when we restore the stack pointer.
6905 ;; For nonlocal gotos, we must save both the stack pointer and its
6906 ;; backchain and restore both. Note that in the nonlocal case, the
6907 ;; save area is a memory location.
6909 (define_expand "save_stack_function"
6910 [(match_operand 0 "general_operand" "")
6911 (match_operand 1 "general_operand" "")]
6915 (define_expand "restore_stack_function"
6916 [(match_operand 0 "general_operand" "")
6917 (match_operand 1 "general_operand" "")]
6921 (define_expand "restore_stack_block"
6922 [(match_operand 0 "register_operand" "")
6923 (match_operand 1 "register_operand" "")]
6926 rtx temp = gen_reg_rtx (Pmode);
6928 emit_move_insn (temp, s390_back_chain_rtx ());
6929 emit_move_insn (operands[0], operands[1]);
6930 emit_move_insn (s390_back_chain_rtx (), temp);
6935 (define_expand "save_stack_nonlocal"
6936 [(match_operand 0 "memory_operand" "")
6937 (match_operand 1 "register_operand" "")]
6940 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6941 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6943 /* Copy the backchain to the first word, sp to the second and the
6944 literal pool base to the third. */
6946 if (TARGET_BACKCHAIN)
6948 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6949 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6952 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6953 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6958 (define_expand "restore_stack_nonlocal"
6959 [(match_operand 0 "register_operand" "")
6960 (match_operand 1 "memory_operand" "")]
6963 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6964 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6965 rtx temp = NULL_RTX;
6967 /* Restore the backchain from the first word, sp from the second and the
6968 literal pool base from the third. */
6970 if (TARGET_BACKCHAIN)
6971 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6973 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6974 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6977 emit_move_insn (s390_back_chain_rtx (), temp);
6979 emit_insn (gen_rtx_USE (VOIDmode, base));
6983 (define_expand "exception_receiver"
6987 s390_set_has_landing_pad_p (true);
6992 ; nop instruction pattern(s).
6999 [(set_attr "op_type" "RR")])
7003 ; Special literal pool access instruction pattern(s).
7006 (define_insn "*pool_entry"
7007 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7008 UNSPECV_POOL_ENTRY)]
7011 enum machine_mode mode = GET_MODE (PATTERN (insn));
7012 unsigned int align = GET_MODE_BITSIZE (mode);
7013 s390_output_pool_entry (operands[0], mode, align);
7016 [(set (attr "length")
7017 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7019 (define_insn "pool_align"
7020 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7021 UNSPECV_POOL_ALIGN)]
7024 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7026 (define_insn "pool_section_start"
7027 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7030 [(set_attr "length" "0")])
7032 (define_insn "pool_section_end"
7033 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7036 [(set_attr "length" "0")])
7038 (define_insn "main_base_31_small"
7039 [(set (match_operand 0 "register_operand" "=a")
7040 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7041 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7043 [(set_attr "op_type" "RR")
7044 (set_attr "type" "la")])
7046 (define_insn "main_base_31_large"
7047 [(set (match_operand 0 "register_operand" "=a")
7048 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7049 (set (pc) (label_ref (match_operand 2 "" "")))]
7050 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7052 [(set_attr "op_type" "RI")])
7054 (define_insn "main_base_64"
7055 [(set (match_operand 0 "register_operand" "=a")
7056 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7057 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7059 [(set_attr "op_type" "RIL")
7060 (set_attr "type" "larl")])
7062 (define_insn "main_pool"
7063 [(set (match_operand 0 "register_operand" "=a")
7064 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7065 "GET_MODE (operands[0]) == Pmode"
7070 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7071 (const_string "larl") (const_string "la")))])
7073 (define_insn "reload_base_31"
7074 [(set (match_operand 0 "register_operand" "=a")
7075 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7076 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7077 "basr\t%0,0\;la\t%0,%1-.(%0)"
7078 [(set_attr "length" "6")
7079 (set_attr "type" "la")])
7081 (define_insn "reload_base_64"
7082 [(set (match_operand 0 "register_operand" "=a")
7083 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7084 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7086 [(set_attr "op_type" "RIL")
7087 (set_attr "type" "larl")])
7090 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7095 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7098 ;; Insns related to generating the function prologue and epilogue.
7102 (define_expand "prologue"
7103 [(use (const_int 0))]
7105 "s390_emit_prologue (); DONE;")
7107 (define_expand "epilogue"
7108 [(use (const_int 1))]
7110 "s390_emit_epilogue (false); DONE;")
7112 (define_expand "sibcall_epilogue"
7113 [(use (const_int 0))]
7115 "s390_emit_epilogue (true); DONE;")
7117 (define_insn "*return"
7119 (use (match_operand 0 "register_operand" "a"))]
7120 "GET_MODE (operands[0]) == Pmode"
7122 [(set_attr "op_type" "RR")
7123 (set_attr "type" "jsr")
7124 (set_attr "atype" "agen")])
7127 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7128 ;; pointer. This is used for compatibility.
7130 (define_expand "ptr_extend"
7131 [(set (match_operand:DI 0 "register_operand" "=r")
7132 (match_operand:SI 1 "register_operand" "r"))]
7135 emit_insn (gen_anddi3 (operands[0],
7136 gen_lowpart (DImode, operands[1]),
7137 GEN_INT (0x7fffffff)));
7141 ;; Instruction definition to expand eh_return macro to support
7142 ;; swapping in special linkage return addresses.
7144 (define_expand "eh_return"
7145 [(use (match_operand 0 "register_operand" ""))]
7148 s390_emit_tpf_eh_return (operands[0]);
7153 ; Stack Protector Patterns
7156 (define_expand "stack_protect_set"
7157 [(set (match_operand 0 "memory_operand" "")
7158 (match_operand 1 "memory_operand" ""))]
7161 #ifdef TARGET_THREAD_SSP_OFFSET
7163 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7164 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7167 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7169 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7174 (define_insn "stack_protect_set<mode>"
7175 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7176 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7178 "mvc\t%O0(%G0,%R0),%S1"
7179 [(set_attr "op_type" "SS")])
7181 (define_expand "stack_protect_test"
7182 [(set (reg:CC CC_REGNUM)
7183 (compare (match_operand 0 "memory_operand" "")
7184 (match_operand 1 "memory_operand" "")))
7185 (match_operand 2 "" "")]
7188 #ifdef TARGET_THREAD_SSP_OFFSET
7190 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7191 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7193 s390_compare_op0 = operands[0];
7194 s390_compare_op1 = operands[1];
7195 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7198 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7200 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7202 emit_jump_insn (gen_beq (operands[2]));
7207 (define_insn "stack_protect_test<mode>"
7208 [(set (reg:CCZ CC_REGNUM)
7209 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7210 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7212 "clc\t%O0(%G0,%R0),%S1"
7213 [(set_attr "op_type" "SS")])